FIRRTL version 3.3.0 circuit VCU118RocketSystem : module IntXbar_i2_o1 : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 22:9] output auto : { flip anon_in_1 : UInt<1>[1], flip anon_in_0 : UInt<1>[10], anon_out : UInt<1>[11]} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire anonIn : UInt<1>[10] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn[2] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn[3] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn[4] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn[5] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn[6] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn[7] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn[8] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn[9] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonIn_1 : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn_1[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : UInt<1>[11] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut[2] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut[3] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut[4] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut[5] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut[6] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut[7] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut[8] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut[9] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut[10] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonIn_1, auto.anon_in_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonOut[0], anonIn[0] @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 25:44] connect anonOut[1], anonIn[1] @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 25:44] connect anonOut[2], anonIn[2] @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 25:44] connect anonOut[3], anonIn[3] @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 25:44] connect anonOut[4], anonIn[4] @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 25:44] connect anonOut[5], anonIn[5] @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 25:44] connect anonOut[6], anonIn[6] @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 25:44] connect anonOut[7], anonIn[7] @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 25:44] connect anonOut[8], anonIn[8] @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 25:44] connect anonOut[9], anonIn[9] @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 25:44] connect anonOut[10], anonIn_1[0] @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 25:44] module NonSyncResetSynchronizerPrimitiveShiftReg_d3 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 37:15] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 37:15] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 37:15] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] reg sync_0 : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:66] reg sync_1 : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:66] reg sync_2 : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:66] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module SynchronizerShiftReg_w1_d3 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 169:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 169:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 169:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 173:39] inst output_chain of NonSyncResetSynchronizerPrimitiveShiftReg_d3 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, reset connect output_chain.io.d, _output_T @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 175:8] module IntSyncAsyncCrossingSink_n1x1 : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 74:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 74:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 74:9] output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] inst chain of SynchronizerShiftReg_w1_d3 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect chain.clock, clock connect chain.reset, reset connect chain.io.d, nodeIn.sync[0] @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _WIRE : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] wire _WIRE_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _WIRE_1, chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] node _T = bits(_WIRE_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _WIRE[0], _T @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect nodeOut, _WIRE @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 77:11] module AsyncResetRegVec_w1_i0 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 56:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 56:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 56:7] output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 59:14] node _reg_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 61:29] regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 61:50] when io.en : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 62:16] connect reg, io.d @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 63:9] connect io.q, reg @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 65:8] module IntSyncCrossingSource_n1x1 : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 41:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 41:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 41:9] output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] inst reg of AsyncResetRegVec_w1_i0 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 86:21] connect reg.clock, clock connect reg.reset, reset connect reg.io.d, nodeIn[0] @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 88:14] connect reg.io.en, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 89:15] node _T = bits(reg.io.q, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 45:50] connect nodeOut.sync[0], _T @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 45:16] module ClockSinkDomain : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 14:9] output auto : { flip int_bus_anon_in : UInt<1>[10], int_bus_anon_out : UInt<1>[11], flip with_no_name_in : UInt<1>[1], flip clock_in : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 21:19] output reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 22:19] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] inst int_bus of IntXbar_i2_o1 @[hardware/upstream/rocket-chip/src/main/scala/subsystem/InterruptBus.scala 19:27] inst intsink of IntSyncAsyncCrossingSink_n1x1 @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 86:29] connect intsink.clock, childClock connect intsink.reset, childReset inst intsource of IntSyncCrossingSource_n1x1 @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 29:31] connect intsource.clock, childClock connect intsource.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate clockNodeIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate clockNodeIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire int_in_xingOut : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate int_in_xingOut.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire int_in_xingIn : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate int_in_xingIn.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect int_in_xingOut, int_in_xingIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire int_in_xingOut_1 : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate int_in_xingOut_1.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire int_in_xingIn_1 : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate int_in_xingIn_1.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect int_in_xingOut_1, int_in_xingIn_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire with_no_nameOut : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate with_no_nameOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire with_no_nameIn : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate with_no_nameIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect with_no_nameOut, with_no_nameIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect int_bus.auto.anon_in_1[0], intsink.auto.out[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect intsink.auto.in.sync[0], int_in_xingOut.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect int_in_xingIn, int_in_xingOut_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect int_in_xingIn_1, intsource.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect intsource.auto.in[0], with_no_nameOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect clockNodeIn, auto.clock_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect with_no_nameIn, auto.with_no_name_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.int_bus_anon_out, int_bus.auto.anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect int_bus.auto.anon_in_0[0], auto.int_bus_anon_in[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect int_bus.auto.anon_in_0[1], auto.int_bus_anon_in[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect int_bus.auto.anon_in_0[2], auto.int_bus_anon_in[2] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect int_bus.auto.anon_in_0[3], auto.int_bus_anon_in[3] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect int_bus.auto.anon_in_0[4], auto.int_bus_anon_in[4] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect int_bus.auto.anon_in_0[5], auto.int_bus_anon_in[5] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect int_bus.auto.anon_in_0[6], auto.int_bus_anon_in[6] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect int_bus.auto.anon_in_0[7], auto.int_bus_anon_in[7] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect int_bus.auto.anon_in_0[8], auto.int_bus_anon_in[8] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect int_bus.auto.anon_in_0[9], auto.int_bus_anon_in[9] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect childClock, clockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 15:16] connect childReset, clockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 16:16] connect clock, clockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 23:11] connect reset, clockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 24:11] module ClockGroupAggregator_aggregator : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 53:9] output auto : { flip in : { member : { aggregator_3 : { clock : Clock, reset : Reset}, aggregator_2 : { clock : Clock, reset : Reset}, aggregator_1 : { clock : Clock, reset : Reset}, aggregator_0 : { clock : Clock, reset : Reset}}}, out : { member : { sbus_3 : { clock : Clock, reset : Reset}, sbus_2 : { clock : Clock, reset : Reset}, sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeOut : { member : { sbus_3 : { clock : Clock, reset : Reset}, sbus_2 : { clock : Clock, reset : Reset}, sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.member.sbus_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.member.sbus_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.member.sbus_1.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.member.sbus_1.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.member.sbus_2.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.member.sbus_2.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.member.sbus_3.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.member.sbus_3.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire nodeIn : { member : { aggregator_3 : { clock : Clock, reset : Reset}, aggregator_2 : { clock : Clock, reset : Reset}, aggregator_1 : { clock : Clock, reset : Reset}, aggregator_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.member.aggregator_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.aggregator_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.aggregator_1.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.aggregator_1.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.aggregator_2.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.aggregator_2.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.aggregator_3.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.aggregator_3.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut.member.sbus_0, nodeIn.member.aggregator_0 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 60:65] connect nodeOut.member.sbus_1, nodeIn.member.aggregator_1 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 60:65] connect nodeOut.member.sbus_2, nodeIn.member.aggregator_2 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 60:65] connect nodeOut.member.sbus_3, nodeIn.member.aggregator_3 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 60:65] module ClockGroupAggregator_sbus : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 53:9] output auto : { flip in : { member : { sbus_3 : { clock : Clock, reset : Reset}, sbus_2 : { clock : Clock, reset : Reset}, sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}}, out_2 : { member : { fbus_0 : { clock : Clock, reset : Reset}}}, out_1 : { member : { cbus_1 : { clock : Clock, reset : Reset}, cbus_0 : { clock : Clock, reset : Reset}}}, out_0 : { member : { sbus_0 : { clock : Clock, reset : Reset}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeIn : { member : { sbus_3 : { clock : Clock, reset : Reset}, sbus_2 : { clock : Clock, reset : Reset}, sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.member.sbus_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.sbus_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.sbus_1.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.sbus_1.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.sbus_2.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.sbus_2.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.sbus_3.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.sbus_3.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { member : { sbus_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.member.sbus_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.member.sbus_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_nodeOut : { member : { cbus_1 : { clock : Clock, reset : Reset}, cbus_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_nodeOut.member.cbus_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.member.cbus_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.member.cbus_1.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.member.cbus_1.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_nodeOut_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_nodeOut_1.member.fbus_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut_1.member.fbus_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out_0, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.out_1, x1_nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.out_2, x1_nodeOut_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut.member.sbus_0, nodeIn.member.sbus_0 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 60:65] connect x1_nodeOut.member.cbus_0, nodeIn.member.sbus_1 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 60:65] connect x1_nodeOut.member.cbus_1, nodeIn.member.sbus_2 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 60:65] connect x1_nodeOut_1.member.fbus_0, nodeIn.member.sbus_3 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 60:65] module ClockGroup : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 24:9] output auto : { flip in : { member : { sbus_0 : { clock : Clock, reset : Reset}}}, out : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeOut : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire nodeIn : { member : { sbus_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.member.sbus_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.sbus_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut, nodeIn.member.sbus_0 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 31:57] module FixedClockBroadcast_3 : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 104:9] output auto : { flip anon_in : { clock : Clock, reset : Reset}, anon_out_2 : { clock : Clock, reset : Reset}, anon_out_1 : { clock : Clock, reset : Reset}, anon_out_0 : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire anonIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut_1 : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut_1.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out_0, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_1, x1_anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_2, x1_anonOut_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonOut, anonIn @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 109:21] connect x1_anonOut, anonIn @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 109:21] connect x1_anonOut_1, anonIn @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 109:21] module BundleBridgeNexus_NoOutput : @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 21:9] output auto : { } @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] module TLXbar_sbus_i2_o1_a32d64s2k1z4u : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn_1.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonIn_1, auto.anon_in_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 159:18] invalidate in[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.data, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.mask, anonIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.address, anonIn.a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.source, anonIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.size, anonIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.param, anonIn.a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.opcode, anonIn.a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.valid, anonIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect anonIn.a.ready, in[0].a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:55] connect in[0].a.bits.source, _in_0_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:29] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_1.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_3.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 180:23] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 181:26] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_9.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_11.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.bits, _WIRE_12.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, _WIRE_12.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.ready, _WIRE_12.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 191:23] wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.bits, _WIRE_14.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.valid, _WIRE_14.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.ready, _WIRE_14.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 192:26] connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.data, in[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.denied, in[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.sink, in[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.source, in[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.size, in[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.param, in[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.opcode, in[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.valid, in[0].d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect in[0].d.ready, anonIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 197:32] wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.bits, _WIRE_16.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.valid, _WIRE_16.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.ready, _WIRE_16.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_17.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_17.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_17.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.bits, _WIRE_18.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.valid, _WIRE_18.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.ready, _WIRE_18.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_19.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_19.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_19.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.bits, _WIRE_20.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.valid, _WIRE_20.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.ready, _WIRE_20.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 210:23] wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.bits, _WIRE_22.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.valid, _WIRE_22.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, _WIRE_22.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 211:26] invalidate in[1].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[1].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[1].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[1].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[1].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[1].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[1].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.data, anonIn_1.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.mask, anonIn_1.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.user.amba_prot.fetch, anonIn_1.a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.user.amba_prot.secure, anonIn_1.a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.user.amba_prot.privileged, anonIn_1.a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.user.amba_prot.writealloc, anonIn_1.a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.user.amba_prot.readalloc, anonIn_1.a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.user.amba_prot.modifiable, anonIn_1.a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.user.amba_prot.bufferable, anonIn_1.a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.address, anonIn_1.a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.source, anonIn_1.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.size, anonIn_1.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.param, anonIn_1.a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.valid, anonIn_1.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect anonIn_1.a.ready, in[1].a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:55] connect in[1].a.bits.source, _in_1_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:29] wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.bits, _WIRE_24.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.valid, _WIRE_24.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.ready, _WIRE_24.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_25.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_25.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_25.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_25.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_25.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_25.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_25.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_25.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_25.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_25.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.bits, _WIRE_26.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.valid, _WIRE_26.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.ready, _WIRE_26.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_27.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_27.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_27.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_27.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_27.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_27.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_27.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_27.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_27.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_27.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.bits, _WIRE_28.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.valid, _WIRE_28.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.ready, _WIRE_28.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 180:23] wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.bits, _WIRE_30.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.valid, _WIRE_30.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.ready, _WIRE_30.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 181:26] wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.bits, _WIRE_32.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.valid, _WIRE_32.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.ready, _WIRE_32.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_33.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.bits, _WIRE_34.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.valid, _WIRE_34.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.ready, _WIRE_34.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_35.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.bits, _WIRE_36.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.valid, _WIRE_36.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.ready, _WIRE_36.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 191:23] wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.bits, _WIRE_38.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.valid, _WIRE_38.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.ready, _WIRE_38.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 192:26] connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn_1.d.bits.data, in[1].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn_1.d.bits.denied, in[1].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn_1.d.bits.sink, in[1].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn_1.d.bits.source, in[1].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn_1.d.bits.size, in[1].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn_1.d.bits.param, in[1].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn_1.d.valid, in[1].d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect in[1].d.ready, anonIn_1.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] node _anonIn_d_bits_source_T = bits(in[1].d.bits.source, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 156:69] connect anonIn_1.d.bits.source, _anonIn_d_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 197:32] wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.bits, _WIRE_40.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.valid, _WIRE_40.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.ready, _WIRE_40.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_41.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_41.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_41.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.bits, _WIRE_42.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.valid, _WIRE_42.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.ready, _WIRE_42.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_43.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_43.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_43.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.bits, _WIRE_44.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.valid, _WIRE_44.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.ready, _WIRE_44.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 210:23] wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.bits, _WIRE_46.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.valid, _WIRE_46.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.ready, _WIRE_46.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 211:26] wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 216:19] invalidate out[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.data, out[0].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.mask, out[0].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.fetch, out[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.secure, out[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.privileged, out[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.writealloc, out[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.readalloc, out[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.modifiable, out[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.bufferable, out[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.address, out[0].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.source, out[0].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.size, out[0].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.param, out[0].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.opcode, out[0].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.valid, out[0].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[0].a.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_49.bits, _WIRE_48.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_49.valid, _WIRE_48.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_49.ready, _WIRE_48.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_49.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_51.bits, _WIRE_50.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_51.valid, _WIRE_50.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_51.ready, _WIRE_50.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_51.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.bits, _WIRE_52.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.valid, _WIRE_52.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.ready, _WIRE_52.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.bits, _WIRE_54.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.valid, _WIRE_54.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.ready, _WIRE_54.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_57.bits, _WIRE_56.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_57.valid, _WIRE_56.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_57.ready, _WIRE_56.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_57.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_59.bits, _WIRE_58.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_59.valid, _WIRE_58.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_59.ready, _WIRE_58.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_59.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.bits, _WIRE_60.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.valid, _WIRE_60.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.ready, _WIRE_60.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.bits, _WIRE_62.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.valid, _WIRE_62.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.ready, _WIRE_62.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.valid, anonOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect anonOut.d.ready, out[0].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[0].d.bits.sink, _out_0_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_64.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_64.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_64.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_65.bits, _WIRE_64.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_65.valid, _WIRE_64.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_65.ready, _WIRE_64.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_65.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_65.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_65.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_66.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_66.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_66.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_67.bits, _WIRE_66.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_67.valid, _WIRE_66.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_67.ready, _WIRE_66.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_67.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_67.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_67.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_68.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_68.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_68.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.bits, _WIRE_68.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.valid, _WIRE_68.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.ready, _WIRE_68.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_70.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_70.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_70.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.bits, _WIRE_70.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.valid, _WIRE_70.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.ready, _WIRE_70.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.bits, _addressC_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.valid, _addressC_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.ready, _addressC_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] wire _addressC_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _addressC_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_3.bits, _addressC_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_3.valid, _addressC_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_3.ready, _addressC_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_1 = cvt(_requestAIO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_3 = asSInt(_requestAIO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_6 = cvt(_requestAIO_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_8 = asSInt(_requestAIO_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_1 = cvt(_requestCIO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_3 = asSInt(_requestCIO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] node _requestCIO_T_5 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_6 = cvt(_requestCIO_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_8 = asSInt(_requestCIO_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node requestBOI_0_0 = eq(_requestBOI_WIRE_1.bits.source, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 48:9] wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_3.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestBOI_T = shr(_requestBOI_WIRE_3.bits.source, 1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestBOI_0_1 = and(_requestBOI_T_3, _requestBOI_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] node requestDOI_0_0 = eq(out[0].d.bits.source, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 48:9] node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestDOI_T = shr(out[0].d.bits.source, 1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestDOI_0_1 = and(_requestDOI_T_3, _requestDOI_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 102:36] node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsCI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _beatsCI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_3.bits, _beatsCI_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_3.valid, _beatsCI_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_3.ready, _beatsCI_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), _beatsCI_WIRE_3.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsCI_opdata_1 = bits(_beatsCI_WIRE_3.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 102:36] node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire _beatsEI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE_2.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _beatsEI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_3.bits, _beatsEI_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_3.valid, _beatsEI_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_3.ready, _beatsEI_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsAOI_filtered[0].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect in[0].a.ready, portsAOI_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsAOI_filtered_1[0].bits, in[1].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect in[1].a.ready, portsAOI_filtered_1[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsBIO_filtered[1].bits, _portsBIO_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_1_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_1_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] node _portsBIO_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsBIO_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsBIO_T_2 = or(_portsBIO_T, _portsBIO_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _portsBIO_WIRE_2 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsBIO_WIRE_2, _portsBIO_T_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsCOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _portsCOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_3.bits, _portsCOI_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_3.valid, _portsCOI_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_3.ready, _portsCOI_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsCOI_filtered_1[0].bits, _portsCOI_WIRE_3.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_0_valid_T_3 = and(_portsCOI_WIRE_3.valid, _portsCOI_filtered_0_valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsCOI_WIRE_3.ready, portsCOI_filtered_1[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.data, out[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.source, out[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.size, out[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.param, out[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[1].bits.data, out[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[1].bits.source, out[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[1].bits.size, out[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[1].bits.param, out[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _portsDIO_out_0_d_ready_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsEOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE_2.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _portsEOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_3.bits, _portsEOI_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_3.valid, _portsEOI_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_3.ready, _portsEOI_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsEOI_filtered_1[0].bits, _portsEOI_WIRE_3.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_0_valid_T_3 = and(_portsEOI_WIRE_3.valid, _portsEOI_filtered_0_valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsEOI_WIRE_3.ready, portsEOI_filtered_1[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 60:30] node idle = eq(beatsLeft, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 61:28] node latch = and(idle, out[0].a.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 62:24] node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:51] node readys_valid = bits(_readys_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 21:23] node _readys_T_1 = eq(readys_valid, _readys_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:19] node _readys_T_2 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] when _readys_T_3 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] when _readys_T_4 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 23:23] node _readys_filter_T = not(readys_mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 24:30] node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 24:28] node readys_filter = cat(_readys_filter_T_1, readys_valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 24:21] node _readys_unready_T = shr(readys_filter, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 263:48] node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 263:43] node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 264:17] node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 25:52] node _readys_unready_T_4 = shl(readys_mask, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 25:66] node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 25:58] node _readys_readys_T = shr(readys_unready, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:29] node _readys_readys_T_1 = bits(readys_unready, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:48] node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:39] node readys_readys = not(_readys_readys_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:18] node _readys_T_5 = orr(readys_valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 27:27] node _readys_T_6 = and(latch, _readys_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 27:18] when _readys_T_6 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 27:32] node _readys_mask_T = and(readys_readys, readys_valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 28:29] node _readys_mask_T_1 = shl(_readys_mask_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 255:17] connect readys_mask, _readys_mask_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 28:12] node _readys_T_7 = bits(readys_readys, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 30:11] node _readys_T_8 = bits(_readys_T_7, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] node _readys_T_9 = bits(_readys_T_7, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] wire readys : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[0], _readys_T_8 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[1], _readys_T_9 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] node _winner_T = and(readys[0], portsAOI_filtered[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] wire winner : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[0], _winner_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[1], _winner_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] node prefixOR_1 = or(UInt<1>(0h0), winner[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node _prefixOR_T = or(prefixOR_1, winner[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_1 = eq(winner[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_2 = or(_T, _T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_4 = eq(winner[1], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_5 = or(_T_3, _T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_6 = and(_T_2, _T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:77] node _T_7 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_8 = eq(_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_9 = eq(_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] when _T_9 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] assert(clock, _T_6, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:31] node _T_11 = eq(_T_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:15] node _T_12 = or(winner[0], winner[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:54] node _T_13 = or(_T_11, _T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:36] node _T_14 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node _T_15 = eq(_T_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] when _T_15 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node _T_16 = eq(_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] when _T_16 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node initBeats = or(maskedBeats_0, maskedBeats_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 84:44] node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:52] node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:52] node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:23] connect beatsLeft, _beatsLeft_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:17] wire _state_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] regreset state : UInt<1>[2], clock, reset, _state_WIRE @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:26] node muxState = mux(idle, winner, state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 89:25] connect state, muxState @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 90:13] node allowed = mux(idle, readys, state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 92:24] node _filtered_0_ready_T = and(out[0].a.ready, allowed[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect portsAOI_filtered[0].ready, _filtered_0_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:46] node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_valid_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:24] connect out[0].a.valid, _out_0_a_valid_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:18] wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_1 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_2 : UInt<64> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_3 : UInt<8> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3 @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_4 : { } @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4 @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_5 : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}} @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_6 : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>} @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.fetch, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.fetch, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_7 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_11 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_6.fetch, _out_0_a_bits_WIRE_7 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.secure, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.secure, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_8 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_14 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_6.secure, _out_0_a_bits_WIRE_8 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.privileged, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.privileged, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_9 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_17 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_6.privileged, _out_0_a_bits_WIRE_9 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.writealloc, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.writealloc, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_10 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_20 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_6.writealloc, _out_0_a_bits_WIRE_10 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.readalloc, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.readalloc, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_11 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_11, _out_0_a_bits_T_23 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_6.readalloc, _out_0_a_bits_WIRE_11 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_24 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.modifiable, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_25 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.modifiable, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_26 = or(_out_0_a_bits_T_24, _out_0_a_bits_T_25) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_12 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_12, _out_0_a_bits_T_26 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_6.modifiable, _out_0_a_bits_WIRE_12 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_27 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.bufferable, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_28 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.bufferable, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_29 = or(_out_0_a_bits_T_27, _out_0_a_bits_T_28) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_13 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_13, _out_0_a_bits_T_29 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_6.bufferable, _out_0_a_bits_WIRE_13 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_5.amba_prot, _out_0_a_bits_WIRE_6 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_30 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_31 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_32 = or(_out_0_a_bits_T_30, _out_0_a_bits_T_31) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_14 : UInt<32> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_14, _out_0_a_bits_T_32 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_14 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_33 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_34 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_35 = or(_out_0_a_bits_T_33, _out_0_a_bits_T_34) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_15 : UInt<2> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_15, _out_0_a_bits_T_35 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_15 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_36 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_37 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_38 = or(_out_0_a_bits_T_36, _out_0_a_bits_T_37) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_16 : UInt<4> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_16, _out_0_a_bits_T_38 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_16 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_39 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_40 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_41 = or(_out_0_a_bits_T_39, _out_0_a_bits_T_40) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_17 : UInt<3> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_17, _out_0_a_bits_T_41 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_17 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_42 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_43 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_44 = or(_out_0_a_bits_T_42, _out_0_a_bits_T_43) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_18 : UInt<3> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_18, _out_0_a_bits_T_44 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_18 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.data, _out_0_a_bits_WIRE.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.user.amba_prot.fetch, _out_0_a_bits_WIRE.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.user.amba_prot.secure, _out_0_a_bits_WIRE.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.user.amba_prot.privileged, _out_0_a_bits_WIRE.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.user.amba_prot.writealloc, _out_0_a_bits_WIRE.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.user.amba_prot.readalloc, _out_0_a_bits_WIRE.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.user.amba_prot.modifiable, _out_0_a_bits_WIRE.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.user.amba_prot.bufferable, _out_0_a_bits_WIRE.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.address, _out_0_a_bits_WIRE.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.source, _out_0_a_bits_WIRE.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.size, _out_0_a_bits_WIRE.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.param, _out_0_a_bits_WIRE.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_73.bits, _WIRE_72.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_73.valid, _WIRE_72.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_73.ready, _WIRE_72.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_73.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_74.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_74.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_74.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_75.bits, _WIRE_74.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_75.valid, _WIRE_74.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_75.ready, _WIRE_74.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_75.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsCOI_filtered_1[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] connect portsEOI_filtered_1[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_77.bits, _WIRE_76.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_77.valid, _WIRE_76.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_77.ready, _WIRE_76.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_77.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect in[0].d, portsDIO_filtered[0] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] connect portsBIO_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_79.bits, _WIRE_78.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_79.valid, _WIRE_78.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_79.ready, _WIRE_78.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_79.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_79.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_79.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_79.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_79.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_79.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_79.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_79.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect in[1].d, portsDIO_filtered[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] connect portsBIO_filtered[1].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] module TLFIFOFixer : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 50:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 50:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 50:9] output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire x1_anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate x1_anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.anon_out_0, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_1, x1_anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect x1_anonIn, auto.anon_in_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] node _a_notFIFO_T = xor(anonIn.a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_notFIFO_T_1 = cvt(_a_notFIFO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_notFIFO_T_2 = and(_a_notFIFO_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_notFIFO_T_3 = asSInt(_a_notFIFO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_notFIFO_T_4 = eq(_a_notFIFO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_id_T = xor(anonIn.a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_id_T_1 = cvt(_a_id_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_id_T_2 = and(_a_id_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_3 = asSInt(_a_id_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_4 = eq(_a_id_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node a_noDomain = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 63:29] node _a_first_T = and(anonIn.a.ready, anonIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), anonIn.a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _a_first_beats1_opdata_T = bits(anonIn.a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node a_first_counter1 = tail(_a_first_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node a_first = eq(a_first_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node a_first_last = or(_a_first_last_T, _a_first_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node a_first_done = and(a_first_last, _a_first_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _a_first_count_T = not(a_first_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node a_first_count = and(a_first_beats1, _a_first_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _a_first_T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect a_first_counter, _a_first_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node _d_first_T = and(anonOut.d.ready, anonOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), anonOut.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node d_first_beats1_opdata = bits(anonOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node d_first_counter1 = tail(_d_first_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node d_first_first = eq(d_first_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node d_first_last = or(_d_first_last_T, _d_first_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node d_first_done = and(d_first_last, _d_first_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _d_first_count_T = not(d_first_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node d_first_count = and(d_first_beats1, _d_first_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _d_first_T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _d_first_counter_T = mux(d_first_first, d_first_beats1, d_first_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect d_first_counter, _d_first_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node _d_first_T_1 = neq(anonOut.d.bits.opcode, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 75:63] node d_first = and(d_first_first, _d_first_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 75:42] wire _flight_WIRE : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 79:35] connect _flight_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 79:35] regreset flight : UInt<1>[1], clock, reset, _flight_WIRE @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 79:27] node _T = and(anonIn.a.ready, anonIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_1 = and(a_first, _T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 80:21] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 80:35] wire _WIRE : UInt connect _WIRE, UInt<1>(0h0) node _flight_T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 80:65] connect flight[_WIRE], _flight_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 80:62] node _T_2 = and(anonIn.d.ready, anonIn.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_3 = and(d_first, _T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 81:21] when _T_3 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 81:35] wire _WIRE_1 : UInt connect _WIRE_1, UInt<1>(0h0) connect flight[_WIRE_1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 81:62] connect anonOut.a, anonIn.a @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 93:13] connect anonIn.d, anonOut.d @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 94:12] node _anonOut_a_valid_T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 95:50] node _anonOut_a_valid_T_1 = or(UInt<1>(0h0), _anonOut_a_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 95:47] node _anonOut_a_valid_T_2 = and(anonIn.a.valid, _anonOut_a_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 95:33] connect anonOut.a.valid, _anonOut_a_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 95:19] node _anonIn_a_ready_T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 96:50] node _anonIn_a_ready_T_1 = or(UInt<1>(0h0), _anonIn_a_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 96:47] node _anonIn_a_ready_T_2 = and(anonOut.a.ready, _anonIn_a_ready_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 96:33] connect anonIn.a.ready, _anonIn_a_ready_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 96:18] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 103:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_4.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_4.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_4.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_4.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_4.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_4.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_4.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 104:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_6.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 105:20] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_9.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 106:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 107:21] wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_12.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_12.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_12.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_13.bits, _WIRE_12.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_13.valid, _WIRE_12.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_13.ready, _WIRE_12.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_13.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 108:21] node _T_4 = and(anonIn.a.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 113:33] regreset SourceIdFIFOed : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 115:35] wire SourceIdSet : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 116:36] connect SourceIdSet, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 116:36] wire SourceIdClear : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 117:38] connect SourceIdClear, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 117:38] node _T_5 = and(anonIn.a.ready, anonIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_6 = and(a_first, _T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 119:21] node _T_7 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 119:37] node _T_8 = and(_T_6, _T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 119:34] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 119:50] node _SourceIdSet_T = dshl(UInt<1>(0h1), anonIn.a.bits.source) @[src/main/scala/chisel3/util/OneHot.scala 58:35] connect SourceIdSet, _SourceIdSet_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 120:21] node _T_9 = and(anonIn.d.ready, anonIn.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_10 = and(d_first, _T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 122:21] when _T_10 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 122:36] node _SourceIdClear_T = dshl(UInt<1>(0h1), anonIn.d.bits.source) @[src/main/scala/chisel3/util/OneHot.scala 58:35] connect SourceIdClear, _SourceIdClear_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 123:23] node _SourceIdFIFOed_T = or(SourceIdFIFOed, SourceIdSet) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 126:40] connect SourceIdFIFOed, _SourceIdFIFOed_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 126:22] node allIDs_FIFOed = eq(SourceIdFIFOed, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 127:41] node _T_11 = eq(flight[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 131:22] node _T_12 = gt(SourceIdSet, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 132:34] node _T_13 = gt(SourceIdClear, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 133:36] node _a_notFIFO_T_5 = xor(x1_anonIn.a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_notFIFO_T_6 = cvt(_a_notFIFO_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_notFIFO_T_7 = and(_a_notFIFO_T_6, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_notFIFO_T_8 = asSInt(_a_notFIFO_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_notFIFO_T_9 = eq(_a_notFIFO_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_id_T_5 = xor(x1_anonIn.a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_id_T_6 = cvt(_a_id_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_id_T_7 = and(_a_id_T_6, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_8 = asSInt(_a_id_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_9 = eq(_a_id_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node a_noDomain_1 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 63:29] node _a_first_T_1 = and(x1_anonIn.a.ready, x1_anonIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), x1_anonIn.a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _a_first_beats1_opdata_T_1 = bits(x1_anonIn.a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node a_first_done_1 = and(a_first_last_1, _a_first_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _a_first_count_T_1 = not(a_first_counter1_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _a_first_T_1 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect a_first_counter_1, _a_first_counter_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node _d_first_T_2 = and(x1_anonOut.d.ready, x1_anonOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), x1_anonOut.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node d_first_beats1_opdata_1 = bits(x1_anonOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node d_first_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node d_first_done_1 = and(d_first_last_1, _d_first_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _d_first_count_T_1 = not(d_first_counter1_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _d_first_T_2 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _d_first_counter_T_1 = mux(d_first_first_1, d_first_beats1_1, d_first_counter1_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect d_first_counter_1, _d_first_counter_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node _d_first_T_3 = neq(x1_anonOut.d.bits.opcode, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 75:63] node d_first_1 = and(d_first_first_1, _d_first_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 75:42] wire _flight_WIRE_1 : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 79:35] connect _flight_WIRE_1[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 79:35] connect _flight_WIRE_1[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 79:35] regreset flight_1 : UInt<1>[2], clock, reset, _flight_WIRE_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 79:27] node _T_14 = and(x1_anonIn.a.ready, x1_anonIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_15 = and(a_first_1, _T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 80:21] when _T_15 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 80:35] node _flight_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 80:65] connect flight_1[x1_anonIn.a.bits.source], _flight_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 80:62] node _T_16 = and(x1_anonIn.d.ready, x1_anonIn.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_17 = and(d_first_1, _T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 81:21] when _T_17 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 81:35] connect flight_1[x1_anonIn.d.bits.source], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 81:62] connect x1_anonOut.a, x1_anonIn.a @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 93:13] connect x1_anonIn.d, x1_anonOut.d @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 94:12] node _anonOut_a_valid_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 95:50] node _anonOut_a_valid_T_4 = or(UInt<1>(0h0), _anonOut_a_valid_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 95:47] node _anonOut_a_valid_T_5 = and(x1_anonIn.a.valid, _anonOut_a_valid_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 95:33] connect x1_anonOut.a.valid, _anonOut_a_valid_T_5 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 95:19] node _anonIn_a_ready_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 96:50] node _anonIn_a_ready_T_4 = or(UInt<1>(0h0), _anonIn_a_ready_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 96:47] node _anonIn_a_ready_T_5 = and(x1_anonOut.a.ready, _anonIn_a_ready_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 96:33] connect x1_anonIn.a.ready, _anonIn_a_ready_T_5 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 96:18] wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_14.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_14.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_14.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_14.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_14.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_14.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_14.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_14.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_14.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_14.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_15.bits, _WIRE_14.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_15.valid, _WIRE_14.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_15.ready, _WIRE_14.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_15.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 103:20] wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_16.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_16.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_16.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_16.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_16.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_16.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_16.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_16.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_16.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_17.bits, _WIRE_16.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_17.valid, _WIRE_16.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_17.ready, _WIRE_16.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_17.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 104:20] wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.bits, _WIRE_18.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.valid, _WIRE_18.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.ready, _WIRE_18.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 105:20] wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_20.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_20.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_20.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_20.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_20.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_20.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_20.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_20.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_20.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_20.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_21.bits, _WIRE_20.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_21.valid, _WIRE_20.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_21.ready, _WIRE_20.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_21.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 106:21] wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_22.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_22.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_22.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_22.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_22.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_22.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_22.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_22.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_22.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_23.bits, _WIRE_22.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_23.valid, _WIRE_22.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_23.ready, _WIRE_22.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_23.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 107:21] wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_24.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_24.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_24.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_25.bits, _WIRE_24.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_25.valid, _WIRE_24.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_25.ready, _WIRE_24.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_25.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 108:21] node _T_18 = and(x1_anonIn.a.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 113:33] regreset SourceIdFIFOed_1 : UInt<2>, clock, reset, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 115:35] wire SourceIdSet_1 : UInt<2> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 116:36] connect SourceIdSet_1, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 116:36] wire SourceIdClear_1 : UInt<2> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 117:38] connect SourceIdClear_1, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 117:38] node _T_19 = and(x1_anonIn.a.ready, x1_anonIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_20 = and(a_first_1, _T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 119:21] node _T_21 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 119:37] node _T_22 = and(_T_20, _T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 119:34] when _T_22 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 119:50] node _SourceIdSet_T_1 = dshl(UInt<1>(0h1), x1_anonIn.a.bits.source) @[src/main/scala/chisel3/util/OneHot.scala 58:35] connect SourceIdSet_1, _SourceIdSet_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 120:21] node _T_23 = and(x1_anonIn.d.ready, x1_anonIn.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_24 = and(d_first_1, _T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 122:21] when _T_24 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 122:36] node _SourceIdClear_T_1 = dshl(UInt<1>(0h1), x1_anonIn.d.bits.source) @[src/main/scala/chisel3/util/OneHot.scala 58:35] connect SourceIdClear_1, _SourceIdClear_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 123:23] node _SourceIdFIFOed_T_1 = or(SourceIdFIFOed_1, SourceIdSet_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 126:40] connect SourceIdFIFOed_1, _SourceIdFIFOed_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 126:22] node _allIDs_FIFOed_T = mux(UInt<1>(0h1), UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 127:48] node allIDs_FIFOed_1 = eq(SourceIdFIFOed_1, _allIDs_FIFOed_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 127:41] node _T_25 = or(flight_1[0], flight_1[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 131:40] node _T_26 = eq(_T_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 131:22] node _T_27 = gt(SourceIdSet_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 132:34] node _T_28 = gt(SourceIdClear_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 133:36] module TLWidthWidget8 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonOut.a.bits, anonIn.a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonOut.a.valid, anonIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 155:19] connect anonIn.a.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 156:18] connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.valid, anonOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 155:19] connect anonOut.d.ready, anonIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 156:18] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 215:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 216:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 217:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 218:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 219:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 220:21] module TLInterconnectCoupler_sbus_to_bus_named_cbus : @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input clock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input reset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] output auto : { flip widget_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] inst widget of TLWidthWidget8 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 230:28] connect widget.clock, clock connect widget.reset, reset wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate bus_xingOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate bus_xingIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect bus_xingOut, bus_xingIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect widget.auto.anon_out.d, bus_xingIn.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect bus_xingIn.a.bits, widget.auto.anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect bus_xingIn.a.valid, widget.auto.anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect widget.auto.anon_out.a.ready, bus_xingIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect auto.bus_xing_out, bus_xingOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect widget.auto.anon_in, auto.widget_anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] module TLWidthWidget8_1 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonOut.a.bits, anonIn.a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonOut.a.valid, anonIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 155:19] connect anonIn.a.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 156:18] connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.valid, anonOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 155:19] connect anonOut.d.ready, anonIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 156:18] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 215:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 216:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 217:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 218:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 219:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 220:21] module TLInterconnectCoupler_sbus_from_bus_named_fbus : @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input clock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input reset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] output auto : { widget_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] inst widget of TLWidthWidget8_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 230:28] connect widget.clock, clock connect widget.reset, reset wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate bus_xingOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate bus_xingIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect bus_xingOut, bus_xingIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect widget.auto.anon_in, bus_xingOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect bus_xingIn, auto.bus_xing_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect widget.auto.anon_out.d, auto.widget_anon_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.widget_anon_out.a.bits, widget.auto.anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.widget_anon_out.a.valid, widget.auto.anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect widget.auto.anon_out.a.ready, auto.widget_anon_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] module TLInterconnectCoupler_sbus_from_rockettile : @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input clock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input reset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] output auto : { flip tl_master_clock_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate tlOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tlIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect tlOut, tlIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire no_bufferOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate no_bufferOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire no_bufferIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate no_bufferIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect no_bufferOut, no_bufferIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire tlMasterClockXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate tlMasterClockXingOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire tlMasterClockXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tlMasterClockXingIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect tlMasterClockXingOut, tlMasterClockXingIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect tlIn, no_bufferOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect no_bufferIn, tlMasterClockXingOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect auto.tl_out, tlOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect tlMasterClockXingIn, auto.tl_master_clock_xing_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] module SystemBus : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 14:9] output auto : { flip coupler_from_rockettile_tl_master_clock_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip coupler_from_bus_named_fbus_bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_cbus_bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip sbus_clock_groups_in : { member : { sbus_3 : { clock : Clock, reset : Reset}, sbus_2 : { clock : Clock, reset : Reset}, sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}}, sbus_clock_groups_out_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}}, sbus_clock_groups_out_0 : { member : { cbus_1 : { clock : Clock, reset : Reset}, cbus_0 : { clock : Clock, reset : Reset}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 21:19] output reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 22:19] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] inst sbus_clock_groups of ClockGroupAggregator_sbus @[hardware/upstream/rocket-chip/src/main/scala/tilelink/BusWrapper.scala 52:48] inst clockGroup of ClockGroup @[hardware/upstream/rocket-chip/src/main/scala/tilelink/BusWrapper.scala 53:38] inst fixedClockNode of FixedClockBroadcast_3 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 115:114] inst broadcast of BundleBridgeNexus_NoOutput @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/package.scala 25:31] inst system_bus_xbar of TLXbar_sbus_i2_o1_a32d64s2k1z4u @[hardware/upstream/rocket-chip/src/main/scala/subsystem/SystemBus.scala 47:43] connect system_bus_xbar.clock, childClock connect system_bus_xbar.reset, childReset inst fixer of TLFIFOFixer @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 152:27] connect fixer.clock, childClock connect fixer.reset, childReset inst coupler_to_bus_named_cbus of TLInterconnectCoupler_sbus_to_bus_named_cbus @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyScope.scala 99:27] connect coupler_to_bus_named_cbus.clock, childClock connect coupler_to_bus_named_cbus.reset, childReset inst coupler_from_bus_named_fbus of TLInterconnectCoupler_sbus_from_bus_named_fbus @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyScope.scala 99:27] connect coupler_from_bus_named_fbus.clock, childClock connect coupler_from_bus_named_fbus.reset, childReset inst coupler_from_rockettile of TLInterconnectCoupler_sbus_from_rockettile @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyScope.scala 99:27] connect coupler_from_rockettile.clock, childClock connect coupler_from_rockettile.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate clockSinkNodeIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate clockSinkNodeIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect clockGroup.auto.in, sbus_clock_groups.auto.out_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fixedClockNode.auto.anon_in, clockGroup.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect coupler_to_bus_named_cbus.auto.widget_anon_in, system_bus_xbar.auto.anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect system_bus_xbar.auto.anon_in_0, fixer.auto.anon_out_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect system_bus_xbar.auto.anon_in_1, fixer.auto.anon_out_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect fixer.auto.anon_in_0, coupler_from_bus_named_fbus.auto.widget_anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect fixer.auto.anon_in_1, coupler_from_rockettile.auto.tl_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect auto.sbus_clock_groups_out_0, sbus_clock_groups.auto.out_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.sbus_clock_groups_out_1, sbus_clock_groups.auto.out_2 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect sbus_clock_groups.auto.in, auto.sbus_clock_groups_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_bus_named_cbus.auto.bus_xing_out.d, auto.coupler_to_bus_named_cbus_bus_xing_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.bits, coupler_to_bus_named_cbus.auto.bus_xing_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.valid, coupler_to_bus_named_cbus.auto.bus_xing_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_bus_named_cbus.auto.bus_xing_out.a.ready, auto.coupler_to_bus_named_cbus_bus_xing_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_from_bus_named_fbus.auto.bus_xing_in, auto.coupler_from_bus_named_fbus_bus_xing_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect coupler_from_rockettile.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect childClock, clockSinkNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 15:16] connect childReset, clockSinkNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 16:16] connect clock, clockSinkNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 23:11] connect reset, clockSinkNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 24:11] module ClockGroupAggregator_pbus : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 53:9] output auto : { flip in : { member : { pbus_0 : { clock : Clock, reset : Reset}}}, out : { member : { pbus_0 : { clock : Clock, reset : Reset}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeOut : { member : { pbus_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.member.pbus_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.member.pbus_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire nodeIn : { member : { pbus_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.member.pbus_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.pbus_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut.member.pbus_0, nodeIn.member.pbus_0 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 60:65] module ClockGroup_1 : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 24:9] output auto : { flip in : { member : { pbus_0 : { clock : Clock, reset : Reset}}}, out : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeOut : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire nodeIn : { member : { pbus_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.member.pbus_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.pbus_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut, nodeIn.member.pbus_0 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 31:57] module FixedClockBroadcast_5 : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 104:9] output auto : { flip anon_in : { clock : Clock, reset : Reset}, anon_out_4 : { clock : Clock, reset : Reset}, anon_out_3 : { clock : Clock, reset : Reset}, anon_out_2 : { clock : Clock, reset : Reset}, anon_out_1 : { clock : Clock, reset : Reset}, anon_out_0 : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire anonIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut_1 : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut_1.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut_2 : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut_2.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut_3 : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut_3.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out_0, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_1, x1_anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_2, x1_anonOut_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_3, x1_anonOut_2 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_4, x1_anonOut_3 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonOut, anonIn @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 109:21] connect x1_anonOut, anonIn @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 109:21] connect x1_anonOut_1, anonIn @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 109:21] connect x1_anonOut_2, anonIn @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 109:21] connect x1_anonOut_3, anonIn @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 109:21] module BundleBridgeNexus_NoOutput_1 : @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 21:9] output auto : { } @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] module TLFIFOFixer_1 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 50:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 50:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 50:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] node _a_notFIFO_T = xor(anonIn.a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_notFIFO_T_1 = cvt(_a_notFIFO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_notFIFO_T_2 = and(_a_notFIFO_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_notFIFO_T_3 = asSInt(_a_notFIFO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_notFIFO_T_4 = eq(_a_notFIFO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_id_T = xor(anonIn.a.bits.address, UInt<14>(0h3000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_id_T_1 = cvt(_a_id_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_id_T_2 = and(_a_id_T_1, asSInt(UInt<19>(0h23000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_3 = asSInt(_a_id_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_4 = eq(_a_id_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_id_T_5 = xor(anonIn.a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_id_T_6 = cvt(_a_id_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_id_T_7 = and(_a_id_T_6, asSInt(UInt<19>(0h23000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_8 = asSInt(_a_id_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_9 = eq(_a_id_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_id_T_10 = xor(anonIn.a.bits.address, UInt<13>(0h1000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_id_T_11 = cvt(_a_id_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_id_T_12 = and(_a_id_T_11, asSInt(UInt<19>(0h23000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_13 = asSInt(_a_id_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_14 = eq(_a_id_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_id_T_15 = xor(anonIn.a.bits.address, UInt<18>(0h20000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_id_T_16 = cvt(_a_id_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_id_T_17 = and(_a_id_T_16, asSInt(UInt<19>(0h20000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_18 = asSInt(_a_id_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_19 = eq(_a_id_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_id_T_20 = mux(_a_id_T_4, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _a_id_T_21 = mux(_a_id_T_9, UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _a_id_T_22 = mux(_a_id_T_14, UInt<2>(0h3), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _a_id_T_23 = mux(_a_id_T_19, UInt<3>(0h4), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _a_id_T_24 = or(_a_id_T_20, _a_id_T_21) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _a_id_T_25 = or(_a_id_T_24, _a_id_T_22) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _a_id_T_26 = or(_a_id_T_25, _a_id_T_23) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire a_id : UInt<3> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect a_id, _a_id_T_26 @[src/main/scala/chisel3/util/Mux.scala 30:73] node a_noDomain = eq(a_id, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 63:29] node _a_first_T = and(anonIn.a.ready, anonIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), anonIn.a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _a_first_beats1_opdata_T = bits(anonIn.a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node a_first_counter1 = tail(_a_first_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node a_first = eq(a_first_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node a_first_last = or(_a_first_last_T, _a_first_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node a_first_done = and(a_first_last, _a_first_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _a_first_count_T = not(a_first_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node a_first_count = and(a_first_beats1, _a_first_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _a_first_T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect a_first_counter, _a_first_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node _d_first_T = and(anonOut.d.ready, anonOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), anonOut.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node d_first_beats1_opdata = bits(anonOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node d_first_counter1 = tail(_d_first_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node d_first_first = eq(d_first_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node d_first_last = or(_d_first_last_T, _d_first_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node d_first_done = and(d_first_last, _d_first_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _d_first_count_T = not(d_first_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node d_first_count = and(d_first_beats1, _d_first_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _d_first_T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _d_first_counter_T = mux(d_first_first, d_first_beats1, d_first_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect d_first_counter, _d_first_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node _d_first_T_1 = neq(anonOut.d.bits.opcode, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 75:63] node d_first = and(d_first_first, _d_first_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 75:42] wire _flight_WIRE : UInt<1>[3] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 79:35] connect _flight_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 79:35] connect _flight_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 79:35] connect _flight_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 79:35] regreset flight : UInt<1>[3], clock, reset, _flight_WIRE @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 79:27] node _T = and(anonIn.a.ready, anonIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_1 = and(a_first, _T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 80:21] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 80:35] node _flight_T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 80:65] connect flight[anonIn.a.bits.source], _flight_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 80:62] node _T_2 = and(anonIn.d.ready, anonIn.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_3 = and(d_first, _T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 81:21] when _T_3 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 81:35] connect flight[anonIn.d.bits.source], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 81:62] connect anonOut.a, anonIn.a @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 93:13] connect anonIn.d, anonOut.d @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 94:12] node _anonOut_a_valid_T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 95:50] node _anonOut_a_valid_T_1 = or(UInt<1>(0h0), _anonOut_a_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 95:47] node _anonOut_a_valid_T_2 = and(anonIn.a.valid, _anonOut_a_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 95:33] connect anonOut.a.valid, _anonOut_a_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 95:19] node _anonIn_a_ready_T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 96:50] node _anonIn_a_ready_T_1 = or(UInt<1>(0h0), _anonIn_a_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 96:47] node _anonIn_a_ready_T_2 = and(anonOut.a.ready, _anonIn_a_ready_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 96:33] connect anonIn.a.ready, _anonIn_a_ready_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 96:18] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 103:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 104:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 105:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 106:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 107:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 108:21] node _T_4 = and(anonIn.a.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 113:33] regreset SourceIdFIFOed : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 115:35] wire SourceIdSet : UInt<3> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 116:36] connect SourceIdSet, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 116:36] wire SourceIdClear : UInt<3> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 117:38] connect SourceIdClear, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 117:38] node _T_5 = and(anonIn.a.ready, anonIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_6 = and(a_first, _T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 119:21] node _T_7 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 119:37] node _T_8 = and(_T_6, _T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 119:34] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 119:50] node _SourceIdSet_T = dshl(UInt<1>(0h1), anonIn.a.bits.source) @[src/main/scala/chisel3/util/OneHot.scala 58:35] connect SourceIdSet, _SourceIdSet_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 120:21] node _T_9 = and(anonIn.d.ready, anonIn.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_10 = and(d_first, _T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 122:21] when _T_10 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 122:36] node _SourceIdClear_T = dshl(UInt<1>(0h1), anonIn.d.bits.source) @[src/main/scala/chisel3/util/OneHot.scala 58:35] connect SourceIdClear, _SourceIdClear_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 123:23] node _SourceIdFIFOed_T = or(SourceIdFIFOed, SourceIdSet) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 126:40] connect SourceIdFIFOed, _SourceIdFIFOed_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 126:22] node _allIDs_FIFOed_T = mux(UInt<1>(0h1), UInt<3>(0h7), UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 127:48] node allIDs_FIFOed = eq(SourceIdFIFOed, _allIDs_FIFOed_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 127:41] node _T_11 = or(flight[0], flight[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 131:40] node _T_12 = or(_T_11, flight[2]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 131:40] node _T_13 = eq(_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 131:22] node _T_14 = gt(SourceIdSet, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 132:34] node _T_15 = gt(SourceIdClear, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 133:36] module TLXbar_pbus_in_i1_o1_a29d64s2k1z3u : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 159:18] invalidate in[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.data, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.mask, anonIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.address, anonIn.a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.source, anonIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.size, anonIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.param, anonIn.a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.opcode, anonIn.a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.valid, anonIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect anonIn.a.ready, in[0].a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:55] connect in[0].a.bits.source, _in_0_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:29] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_1.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_3.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 180:23] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 181:26] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_9.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_11.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.bits, _WIRE_12.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, _WIRE_12.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.ready, _WIRE_12.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 191:23] wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.bits, _WIRE_14.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.valid, _WIRE_14.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.ready, _WIRE_14.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 192:26] connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.data, in[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.denied, in[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.sink, in[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.source, in[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.size, in[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.param, in[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.opcode, in[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.valid, in[0].d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect in[0].d.ready, anonIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 156:69] connect anonIn.d.bits.source, _anonIn_d_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 197:32] wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.bits, _WIRE_16.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.valid, _WIRE_16.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.ready, _WIRE_16.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_17.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_17.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_17.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.bits, _WIRE_18.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.valid, _WIRE_18.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.ready, _WIRE_18.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_19.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_19.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_19.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.bits, _WIRE_20.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.valid, _WIRE_20.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.ready, _WIRE_20.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 210:23] wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.bits, _WIRE_22.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.valid, _WIRE_22.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, _WIRE_22.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 211:26] wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 216:19] invalidate out[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.data, out[0].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.mask, out[0].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.fetch, out[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.secure, out[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.privileged, out[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.writealloc, out[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.readalloc, out[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.modifiable, out[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.bufferable, out[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.address, out[0].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.source, out[0].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.size, out[0].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.param, out[0].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.opcode, out[0].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.valid, out[0].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[0].a.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.bits, _WIRE_24.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.valid, _WIRE_24.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.ready, _WIRE_24.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_25.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.bits, _WIRE_26.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.valid, _WIRE_26.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.ready, _WIRE_26.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_27.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.bits, _WIRE_28.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.valid, _WIRE_28.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.ready, _WIRE_28.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.bits, _WIRE_30.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.valid, _WIRE_30.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.ready, _WIRE_30.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.bits, _WIRE_32.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.valid, _WIRE_32.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.ready, _WIRE_32.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_33.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.bits, _WIRE_34.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.valid, _WIRE_34.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.ready, _WIRE_34.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_35.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.bits, _WIRE_36.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.valid, _WIRE_36.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.ready, _WIRE_36.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.bits, _WIRE_38.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.valid, _WIRE_38.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.ready, _WIRE_38.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.valid, anonOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect anonOut.d.ready, out[0].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[0].d.bits.sink, _out_0_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.bits, _WIRE_40.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.valid, _WIRE_40.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.ready, _WIRE_40.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_41.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_41.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_41.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.bits, _WIRE_42.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.valid, _WIRE_42.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.ready, _WIRE_42.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_43.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_43.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_43.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.bits, _WIRE_44.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.valid, _WIRE_44.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.ready, _WIRE_44.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.bits, _WIRE_46.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.valid, _WIRE_46.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.ready, _WIRE_46.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.bits, _addressC_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.valid, _addressC_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.ready, _addressC_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_1 = cvt(_requestAIO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_3 = asSInt(_requestAIO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_1 = cvt(_requestCIO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_3 = asSInt(_requestCIO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestDOI_T = shr(out[0].d.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] node _beatsAI_decode_T = dshl(UInt<6>(0h3f), in[0].a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T = dshl(UInt<6>(0h3f), _beatsBO_WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _beatsCI_decode_T = dshl(UInt<6>(0h3f), _beatsCI_WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 102:36] node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T = dshl(UInt<6>(0h3f), out[0].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsAOI_filtered[0].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect in[0].a.ready, portsAOI_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.data, out[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.source, out[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.size, out[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.param, out[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect out[0].d.ready, portsDIO_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] connect out[0].a, portsAOI_filtered[0] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_49.bits, _WIRE_48.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_49.valid, _WIRE_48.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_49.ready, _WIRE_48.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_49.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_50.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_50.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_50.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_51.bits, _WIRE_50.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_51.valid, _WIRE_50.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_51.ready, _WIRE_50.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_51.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.bits, _WIRE_52.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.valid, _WIRE_52.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.ready, _WIRE_52.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_53.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect in[0].d, portsDIO_filtered[0] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] connect portsBIO_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] module TLXbar_pbus_out_i1_o4_a29d64s2k1z3u : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut_1.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut_2.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out_0, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_1, x1_anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_2, x1_anonOut_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_3, x1_anonOut_2 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 159:18] invalidate in[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.data, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.mask, anonIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.address, anonIn.a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.source, anonIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.size, anonIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.param, anonIn.a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.opcode, anonIn.a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.valid, anonIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect anonIn.a.ready, in[0].a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:55] connect in[0].a.bits.source, _in_0_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:29] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_1.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_3.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 180:23] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 181:26] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_9.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_11.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.bits, _WIRE_12.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, _WIRE_12.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.ready, _WIRE_12.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 191:23] wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.bits, _WIRE_14.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.valid, _WIRE_14.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.ready, _WIRE_14.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 192:26] connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.data, in[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.denied, in[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.sink, in[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.source, in[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.size, in[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.param, in[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.opcode, in[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.valid, in[0].d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect in[0].d.ready, anonIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 156:69] connect anonIn.d.bits.source, _anonIn_d_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 197:32] wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.bits, _WIRE_16.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.valid, _WIRE_16.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.ready, _WIRE_16.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_17.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_17.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_17.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.bits, _WIRE_18.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.valid, _WIRE_18.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.ready, _WIRE_18.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_19.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_19.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_19.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.bits, _WIRE_20.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.valid, _WIRE_20.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.ready, _WIRE_20.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 210:23] wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.bits, _WIRE_22.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.valid, _WIRE_22.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, _WIRE_22.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 211:26] wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[4] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 216:19] invalidate out[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.data, out[0].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.mask, out[0].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.address, out[0].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.source, out[0].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.size, out[0].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.param, out[0].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.opcode, out[0].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.valid, out[0].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[0].a.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.bits, _WIRE_24.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.valid, _WIRE_24.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.ready, _WIRE_24.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_25.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.bits, _WIRE_26.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.valid, _WIRE_26.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.ready, _WIRE_26.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_27.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.bits, _WIRE_28.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.valid, _WIRE_28.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.ready, _WIRE_28.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.bits, _WIRE_30.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.valid, _WIRE_30.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.ready, _WIRE_30.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.bits, _WIRE_32.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.valid, _WIRE_32.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.ready, _WIRE_32.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_33.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.bits, _WIRE_34.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.valid, _WIRE_34.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.ready, _WIRE_34.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_35.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.bits, _WIRE_36.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.valid, _WIRE_36.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.ready, _WIRE_36.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.bits, _WIRE_38.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.valid, _WIRE_38.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.ready, _WIRE_38.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.valid, anonOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect anonOut.d.ready, out[0].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[0].d.bits.sink, _out_0_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.bits, _WIRE_40.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.valid, _WIRE_40.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.ready, _WIRE_40.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_41.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_41.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_41.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.bits, _WIRE_42.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.valid, _WIRE_42.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.ready, _WIRE_42.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_43.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_43.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_43.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.bits, _WIRE_44.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.valid, _WIRE_44.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.ready, _WIRE_44.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.bits, _WIRE_46.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.valid, _WIRE_46.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.ready, _WIRE_46.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] invalidate out[1].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[1].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[1].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[1].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[1].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[1].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[1].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.data, out[1].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.mask, out[1].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.address, out[1].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.source, out[1].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.size, out[1].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.param, out[1].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.valid, out[1].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[1].a.ready, x1_anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_49.bits, _WIRE_48.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_49.valid, _WIRE_48.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_49.ready, _WIRE_48.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_49.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_51.bits, _WIRE_50.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_51.valid, _WIRE_50.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_51.ready, _WIRE_50.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_51.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.bits, _WIRE_52.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.valid, _WIRE_52.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.ready, _WIRE_52.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.bits, _WIRE_54.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.valid, _WIRE_54.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.ready, _WIRE_54.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_57.bits, _WIRE_56.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_57.valid, _WIRE_56.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_57.ready, _WIRE_56.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_57.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_59.bits, _WIRE_58.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_59.valid, _WIRE_58.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_59.ready, _WIRE_58.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_59.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.bits, _WIRE_60.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.valid, _WIRE_60.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.ready, _WIRE_60.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.bits, _WIRE_62.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.valid, _WIRE_62.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.ready, _WIRE_62.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.data, x1_anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.denied, x1_anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.sink, x1_anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.source, x1_anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.size, x1_anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.param, x1_anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.valid, x1_anonOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect x1_anonOut.d.ready, out[1].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[1].d.bits.sink, _out_1_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_64.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_64.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_64.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_65.bits, _WIRE_64.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_65.valid, _WIRE_64.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_65.ready, _WIRE_64.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_65.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_65.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_65.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_66.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_66.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_66.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_67.bits, _WIRE_66.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_67.valid, _WIRE_66.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_67.ready, _WIRE_66.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_67.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_67.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_67.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_68.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_68.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_68.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.bits, _WIRE_68.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.valid, _WIRE_68.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.ready, _WIRE_68.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_70.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_70.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_70.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.bits, _WIRE_70.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.valid, _WIRE_70.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.ready, _WIRE_70.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] invalidate out[2].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[2].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[2].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[2].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[2].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[2].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[2].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] connect x1_anonOut_1.a.bits.corrupt, out[2].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_1.a.bits.data, out[2].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_1.a.bits.mask, out[2].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_1.a.bits.address, out[2].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_1.a.bits.source, out[2].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_1.a.bits.size, out[2].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_1.a.bits.param, out[2].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_1.a.bits.opcode, out[2].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_1.a.valid, out[2].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[2].a.ready, x1_anonOut_1.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_73.bits, _WIRE_72.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_73.valid, _WIRE_72.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_73.ready, _WIRE_72.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_73.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_73.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_73.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_73.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_73.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_73.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_73.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_73.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_73.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_73.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_75.bits, _WIRE_74.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_75.valid, _WIRE_74.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_75.ready, _WIRE_74.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_75.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_75.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_75.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_75.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_75.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_75.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_75.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_75.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_75.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_75.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_77.bits, _WIRE_76.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_77.valid, _WIRE_76.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_77.ready, _WIRE_76.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_77.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_79.bits, _WIRE_78.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_79.valid, _WIRE_78.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_79.ready, _WIRE_78.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_79.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_81.bits, _WIRE_80.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_81.valid, _WIRE_80.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_81.ready, _WIRE_80.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_81.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_82 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_82.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_82.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_82.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_82.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_82.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_82.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_82.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_82.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_82.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_83 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_83.bits, _WIRE_82.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_83.valid, _WIRE_82.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_83.ready, _WIRE_82.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_83.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_83.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_83.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_83.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_83.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_83.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_83.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_83.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_83.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_84 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_85 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_85.bits, _WIRE_84.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_85.valid, _WIRE_84.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_85.ready, _WIRE_84.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_85.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_86 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_86.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_86.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_86.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_86.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_86.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_86.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_86.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_86.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_86.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_87 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_87.bits, _WIRE_86.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_87.valid, _WIRE_86.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_87.ready, _WIRE_86.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_87.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[2].d.bits.corrupt, x1_anonOut_1.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[2].d.bits.data, x1_anonOut_1.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[2].d.bits.denied, x1_anonOut_1.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[2].d.bits.sink, x1_anonOut_1.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[2].d.bits.source, x1_anonOut_1.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[2].d.bits.size, x1_anonOut_1.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[2].d.bits.param, x1_anonOut_1.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[2].d.bits.opcode, x1_anonOut_1.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[2].d.valid, x1_anonOut_1.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect x1_anonOut_1.d.ready, out[2].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_2_d_bits_sink_T = or(x1_anonOut_1.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[2].d.bits.sink, _out_2_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_88 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_88.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_88.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_88.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_89 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_89.bits, _WIRE_88.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_89.valid, _WIRE_88.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_89.ready, _WIRE_88.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_89.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_89.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_89.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_90 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_90.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_90.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_90.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_91 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_91.bits, _WIRE_90.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_91.valid, _WIRE_90.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_91.ready, _WIRE_90.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_91.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_91.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_91.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_92 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_92.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_92.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_92.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_93 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_93.bits, _WIRE_92.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_93.valid, _WIRE_92.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_93.ready, _WIRE_92.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_93.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_94 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_94.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_94.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_94.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_95 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_95.bits, _WIRE_94.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_95.valid, _WIRE_94.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_95.ready, _WIRE_94.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_95.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] invalidate out[3].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[3].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[3].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[3].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[3].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[3].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[3].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] connect x1_anonOut_2.a.bits.corrupt, out[3].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.data, out[3].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.mask, out[3].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.user.amba_prot.fetch, out[3].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.user.amba_prot.secure, out[3].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.user.amba_prot.privileged, out[3].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.user.amba_prot.writealloc, out[3].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.user.amba_prot.readalloc, out[3].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.user.amba_prot.modifiable, out[3].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.user.amba_prot.bufferable, out[3].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.address, out[3].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.source, out[3].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.size, out[3].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.param, out[3].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.opcode, out[3].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.valid, out[3].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[3].a.ready, x1_anonOut_2.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_96 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_97 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_97.bits, _WIRE_96.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_97.valid, _WIRE_96.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_97.ready, _WIRE_96.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_97.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_97.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_97.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_97.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_97.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_97.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_97.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_97.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_97.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_97.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_98 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_99 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_99.bits, _WIRE_98.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_99.valid, _WIRE_98.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_99.ready, _WIRE_98.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_99.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_99.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_99.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_99.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_99.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_99.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_99.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_99.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_99.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_99.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_100 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_101 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_101.bits, _WIRE_100.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_101.valid, _WIRE_100.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_101.ready, _WIRE_100.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_101.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_102 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_103 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_103.bits, _WIRE_102.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_103.valid, _WIRE_102.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_103.ready, _WIRE_102.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_103.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_104 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_105 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_105.bits, _WIRE_104.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_105.valid, _WIRE_104.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_105.ready, _WIRE_104.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_105.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_106 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_107 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_107.bits, _WIRE_106.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_107.valid, _WIRE_106.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_107.ready, _WIRE_106.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_107.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_108 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_109 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_109.bits, _WIRE_108.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_109.valid, _WIRE_108.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_109.ready, _WIRE_108.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_109.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_110 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_111 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_111.bits, _WIRE_110.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_111.valid, _WIRE_110.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_111.ready, _WIRE_110.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_111.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[3].d.bits.corrupt, x1_anonOut_2.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[3].d.bits.data, x1_anonOut_2.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[3].d.bits.denied, x1_anonOut_2.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[3].d.bits.sink, x1_anonOut_2.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[3].d.bits.source, x1_anonOut_2.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[3].d.bits.size, x1_anonOut_2.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[3].d.bits.param, x1_anonOut_2.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[3].d.bits.opcode, x1_anonOut_2.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[3].d.valid, x1_anonOut_2.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect x1_anonOut_2.d.ready, out[3].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_3_d_bits_sink_T = or(x1_anonOut_2.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[3].d.bits.sink, _out_3_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_112 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_112.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_112.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_112.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_113 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_113.bits, _WIRE_112.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_113.valid, _WIRE_112.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_113.ready, _WIRE_112.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_113.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_113.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_113.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_114 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_114.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_114.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_114.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_115 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_115.bits, _WIRE_114.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_115.valid, _WIRE_114.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_115.ready, _WIRE_114.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_115.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_115.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_115.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_116 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_116.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_116.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_116.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_117 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_117.bits, _WIRE_116.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_117.valid, _WIRE_116.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_117.ready, _WIRE_116.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_117.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_118 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_118.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_118.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_118.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_119 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_119.bits, _WIRE_118.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_119.valid, _WIRE_118.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_119.ready, _WIRE_118.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_119.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.bits, _addressC_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.valid, _addressC_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.ready, _addressC_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _requestAIO_T = xor(in[0].a.bits.address, UInt<14>(0h3000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_1 = cvt(_requestAIO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<19>(0h23000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_3 = asSInt(_requestAIO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_6 = cvt(_requestAIO_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<19>(0h23000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_8 = asSInt(_requestAIO_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestAIO_T_10 = xor(in[0].a.bits.address, UInt<13>(0h1000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_11 = cvt(_requestAIO_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<19>(0h23000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_13 = asSInt(_requestAIO_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_0_2 = or(UInt<1>(0h0), _requestAIO_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestAIO_T_15 = xor(in[0].a.bits.address, UInt<18>(0h20000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_16 = cvt(_requestAIO_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_17 = and(_requestAIO_T_16, asSInt(UInt<19>(0h20000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_18 = asSInt(_requestAIO_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_19 = eq(_requestAIO_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_0_3 = or(UInt<1>(0h0), _requestAIO_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_1 = cvt(_requestCIO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_3 = asSInt(_requestCIO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_6 = cvt(_requestCIO_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_8 = asSInt(_requestCIO_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] node _requestCIO_T_10 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_11 = cvt(_requestCIO_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_12 = and(_requestCIO_T_11, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_13 = asSInt(_requestCIO_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_14 = eq(_requestCIO_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_2 = or(UInt<1>(0h1), _requestCIO_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] node _requestCIO_T_15 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_16 = cvt(_requestCIO_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_17 = and(_requestCIO_T_16, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_18 = asSInt(_requestCIO_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_19 = eq(_requestCIO_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_3 = or(UInt<1>(0h1), _requestCIO_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestBOI_1_0 = and(_requestBOI_T_8, _requestBOI_T_9) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] wire _requestBOI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_5.bits, _requestBOI_WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_5.valid, _requestBOI_WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_5.ready, _requestBOI_WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _requestBOI_uncommonBits_T_2 = or(_requestBOI_WIRE_5.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestBOI_uncommonBits_2 = bits(_requestBOI_uncommonBits_T_2, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestBOI_T_10 = shr(_requestBOI_WIRE_5.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestBOI_T_11 = eq(_requestBOI_T_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestBOI_T_12 = leq(UInt<1>(0h0), requestBOI_uncommonBits_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestBOI_T_13 = and(_requestBOI_T_11, _requestBOI_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestBOI_T_14 = leq(requestBOI_uncommonBits_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestBOI_2_0 = and(_requestBOI_T_13, _requestBOI_T_14) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] wire _requestBOI_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_7.bits, _requestBOI_WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_7.valid, _requestBOI_WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_7.ready, _requestBOI_WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _requestBOI_uncommonBits_T_3 = or(_requestBOI_WIRE_7.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestBOI_uncommonBits_3 = bits(_requestBOI_uncommonBits_T_3, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestBOI_T_15 = shr(_requestBOI_WIRE_7.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestBOI_T_16 = eq(_requestBOI_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestBOI_T_17 = leq(UInt<1>(0h0), requestBOI_uncommonBits_3) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestBOI_T_18 = and(_requestBOI_T_16, _requestBOI_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestBOI_T_19 = leq(requestBOI_uncommonBits_3, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestBOI_3_0 = and(_requestBOI_T_18, _requestBOI_T_19) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestDOI_T = shr(out[0].d.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] node _requestDOI_uncommonBits_T_1 = or(out[1].d.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestDOI_T_5 = shr(out[1].d.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestDOI_1_0 = and(_requestDOI_T_8, _requestDOI_T_9) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] node _requestDOI_uncommonBits_T_2 = or(out[2].d.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestDOI_uncommonBits_2 = bits(_requestDOI_uncommonBits_T_2, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestDOI_T_10 = shr(out[2].d.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestDOI_T_11 = eq(_requestDOI_T_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestDOI_T_12 = leq(UInt<1>(0h0), requestDOI_uncommonBits_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestDOI_T_13 = and(_requestDOI_T_11, _requestDOI_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestDOI_T_14 = leq(requestDOI_uncommonBits_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestDOI_2_0 = and(_requestDOI_T_13, _requestDOI_T_14) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] node _requestDOI_uncommonBits_T_3 = or(out[3].d.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestDOI_uncommonBits_3 = bits(_requestDOI_uncommonBits_T_3, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestDOI_T_15 = shr(out[3].d.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestDOI_T_16 = eq(_requestDOI_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestDOI_T_17 = leq(UInt<1>(0h0), requestDOI_uncommonBits_3) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestDOI_T_18 = and(_requestDOI_T_16, _requestDOI_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestDOI_T_19 = leq(requestDOI_uncommonBits_3, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestDOI_3_0 = and(_requestDOI_T_18, _requestDOI_T_19) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire _requestEIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_5.bits, _requestEIO_WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_5.valid, _requestEIO_WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_5.ready, _requestEIO_WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire _requestEIO_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_6.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_7.bits, _requestEIO_WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_7.valid, _requestEIO_WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_7.ready, _requestEIO_WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] node _beatsAI_decode_T = dshl(UInt<6>(0h3f), in[0].a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T = dshl(UInt<6>(0h3f), _beatsBO_WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_5.bits, _beatsBO_WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_5.valid, _beatsBO_WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_5.ready, _beatsBO_WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T_6 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_5.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_7 = bits(_beatsBO_decode_T_6, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_8 = not(_beatsBO_decode_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode_2 = shr(_beatsBO_decode_T_8, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T_2 = bits(_beatsBO_WIRE_5.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata_2 = eq(_beatsBO_opdata_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_2 = mux(UInt<1>(0h0), beatsBO_decode_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_7.bits, _beatsBO_WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_7.valid, _beatsBO_WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_7.ready, _beatsBO_WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T_9 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_7.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_10 = bits(_beatsBO_decode_T_9, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_11 = not(_beatsBO_decode_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode_3 = shr(_beatsBO_decode_T_11, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T_3 = bits(_beatsBO_WIRE_7.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata_3 = eq(_beatsBO_opdata_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_3 = mux(UInt<1>(0h0), beatsBO_decode_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _beatsCI_decode_T = dshl(UInt<6>(0h3f), _beatsCI_WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 102:36] node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T = dshl(UInt<6>(0h3f), out[0].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T_6 = dshl(UInt<6>(0h3f), out[2].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_7 = bits(_beatsDO_decode_T_6, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_8 = not(_beatsDO_decode_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode_2 = shr(_beatsDO_decode_T_8, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata_2 = bits(out[2].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_2 = mux(beatsDO_opdata_2, beatsDO_decode_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T_9 = dshl(UInt<6>(0h3f), out[3].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_10 = bits(_beatsDO_decode_T_9, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_11 = not(_beatsDO_decode_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode_3 = shr(_beatsDO_decode_T_11, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata_3 = bits(out[3].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_3 = mux(beatsDO_opdata_3, beatsDO_decode_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[4] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsAOI_filtered[0].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsAOI_filtered[1].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsAOI_filtered[2].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_2_valid_T = or(requestAIO_0_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_2_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_2_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[2].valid, _portsAOI_filtered_2_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsAOI_filtered[3].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_3_valid_T = or(requestAIO_0_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_3_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_3_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[3].valid, _portsAOI_filtered_3_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_2 = mux(requestAIO_0_2, portsAOI_filtered[2].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_3 = mux(requestAIO_0_3, portsAOI_filtered[3].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_4 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_5 = or(_portsAOI_in_0_a_ready_T_4, _portsAOI_in_0_a_ready_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_6 = or(_portsAOI_in_0_a_ready_T_5, _portsAOI_in_0_a_ready_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _portsAOI_in_0_a_ready_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_6 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_3.bits, _portsBIO_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_3.valid, _portsBIO_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_3.ready, _portsBIO_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_3.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_3.valid, _portsBIO_filtered_0_valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsBIO_WIRE_3.ready, portsBIO_filtered_1[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_5.bits, _portsBIO_WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_5.valid, _portsBIO_WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_5.ready, _portsBIO_WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered_2[0].bits, _portsBIO_WIRE_5.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T_4 = or(requestBOI_2_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_5 = and(_portsBIO_WIRE_5.valid, _portsBIO_filtered_0_valid_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered_2[0].valid, _portsBIO_filtered_0_valid_T_5 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsBIO_WIRE_5.ready, portsBIO_filtered_2[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_7.bits, _portsBIO_WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_7.valid, _portsBIO_WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_7.ready, _portsBIO_WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered_3[0].bits, _portsBIO_WIRE_7.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T_6 = or(requestBOI_3_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_7 = and(_portsBIO_WIRE_7.valid, _portsBIO_filtered_0_valid_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered_3[0].valid, _portsBIO_filtered_0_valid_T_7 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsBIO_WIRE_7.ready, portsBIO_filtered_3[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[4] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsCOI_filtered[2].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_2_valid_T = or(requestCIO_0_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_2_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_2_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[2].valid, _portsCOI_filtered_2_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsCOI_filtered[3].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_3_valid_T = or(requestCIO_0_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_3_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_3_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[3].valid, _portsCOI_filtered_3_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_2 = mux(requestCIO_0_2, portsCOI_filtered[2].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_3 = mux(requestCIO_0_3, portsCOI_filtered[3].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_4 = or(_portsCOI_T, _portsCOI_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_5 = or(_portsCOI_T_4, _portsCOI_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_6 = or(_portsCOI_T_5, _portsCOI_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _portsCOI_WIRE_2 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsCOI_WIRE_2, _portsCOI_T_6 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.data, out[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.source, out[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.size, out[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.param, out[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect out[0].d.ready, portsDIO_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect out[1].d.ready, portsDIO_filtered_1[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered_2[0].bits.corrupt, out[2].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_2[0].bits.data, out[2].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_2[0].bits.denied, out[2].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_2[0].bits.sink, out[2].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_2[0].bits.source, out[2].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_2[0].bits.size, out[2].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_2[0].bits.param, out[2].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_2[0].bits.opcode, out[2].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T_4 = or(requestDOI_2_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_5 = and(out[2].d.valid, _portsDIO_filtered_0_valid_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered_2[0].valid, _portsDIO_filtered_0_valid_T_5 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect out[2].d.ready, portsDIO_filtered_2[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered_3[0].bits.corrupt, out[3].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_3[0].bits.data, out[3].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_3[0].bits.denied, out[3].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_3[0].bits.sink, out[3].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_3[0].bits.source, out[3].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_3[0].bits.size, out[3].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_3[0].bits.param, out[3].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_3[0].bits.opcode, out[3].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T_6 = or(requestDOI_3_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_7 = and(out[3].d.valid, _portsDIO_filtered_0_valid_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered_3[0].valid, _portsDIO_filtered_0_valid_T_7 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect out[3].d.ready, portsDIO_filtered_3[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[4] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsEOI_filtered[2].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_2_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_2_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_2_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[2].valid, _portsEOI_filtered_2_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsEOI_filtered[3].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_3_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_3_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_3_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[3].valid, _portsEOI_filtered_3_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_2 = mux(UInt<1>(0h0), portsEOI_filtered[2].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_3 = mux(UInt<1>(0h0), portsEOI_filtered[3].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_4 = or(_portsEOI_T, _portsEOI_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_5 = or(_portsEOI_T_4, _portsEOI_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_6 = or(_portsEOI_T_5, _portsEOI_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _portsEOI_WIRE_2 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsEOI_WIRE_2, _portsEOI_T_6 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] connect out[0].a, portsAOI_filtered[0] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] wire _WIRE_120 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_120.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_120.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_120.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_120.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_120.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_120.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_120.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_120.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_120.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_120.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_120.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_120.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_120.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_120.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_120.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_120.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_121 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_121.bits, _WIRE_120.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_121.valid, _WIRE_120.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_121.ready, _WIRE_120.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_121.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_121.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_121.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_121.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_121.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_121.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_121.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_121.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_121.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_121.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_121.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_121.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_121.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_121.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_122 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_122.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_122.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_122.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_123 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_123.bits, _WIRE_122.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_123.valid, _WIRE_122.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_123.ready, _WIRE_122.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_123.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] connect out[1].a, portsAOI_filtered[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] wire _WIRE_124 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_124.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_124.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_124.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_124.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_124.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_124.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_124.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_124.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_124.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_124.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_124.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_124.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_124.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_124.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_124.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_124.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_125 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_125.bits, _WIRE_124.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_125.valid, _WIRE_124.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_125.ready, _WIRE_124.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_125.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_125.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_125.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_125.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_125.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_125.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_125.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_125.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_125.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_125.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_125.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_125.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_125.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_125.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_126 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_126.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_126.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_126.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_127 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_127.bits, _WIRE_126.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_127.valid, _WIRE_126.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_127.ready, _WIRE_126.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_127.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[1].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[1].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] connect out[2].a, portsAOI_filtered[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] wire _WIRE_128 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_129 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_129.bits, _WIRE_128.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_129.valid, _WIRE_128.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_129.ready, _WIRE_128.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_129.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_129.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_129.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_129.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_129.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_129.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_129.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_129.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_129.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_129.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_129.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_129.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_129.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_129.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_130 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_130.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_130.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_130.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_131 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_131.bits, _WIRE_130.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_131.valid, _WIRE_130.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_131.ready, _WIRE_130.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_131.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[2].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[2].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] connect out[3].a, portsAOI_filtered[3] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] wire _WIRE_132 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_133 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_133.bits, _WIRE_132.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_133.valid, _WIRE_132.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_133.ready, _WIRE_132.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_133.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_133.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_133.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_133.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_133.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_133.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_133.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_133.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_133.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_133.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_133.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_133.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_133.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_133.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_134 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_134.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_134.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_134.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_135 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_135.bits, _WIRE_134.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_135.valid, _WIRE_134.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_135.ready, _WIRE_134.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_135.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[3].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[3].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] wire _WIRE_136 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_136.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_136.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_136.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_136.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_136.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_136.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_136.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_136.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_136.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_136.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_137 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_137.bits, _WIRE_136.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_137.valid, _WIRE_136.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_137.ready, _WIRE_136.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_137.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_137.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_137.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_137.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_137.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_137.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_137.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_137.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 60:30] node idle = eq(beatsLeft, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 61:28] node latch = and(idle, in[0].d.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 62:24] node readys_lo = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:51] node readys_hi = cat(portsDIO_filtered_3[0].valid, portsDIO_filtered_2[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:51] node _readys_T = cat(readys_hi, readys_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:51] node readys_valid = bits(_readys_T, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 21:23] node _readys_T_1 = eq(readys_valid, _readys_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:19] node _readys_T_2 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] when _readys_T_3 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] when _readys_T_4 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] regreset readys_mask : UInt<4>, clock, reset, UInt<4>(0hf) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 23:23] node _readys_filter_T = not(readys_mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 24:30] node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 24:28] node readys_filter = cat(_readys_filter_T_1, readys_valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 24:21] node _readys_unready_T = shr(readys_filter, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 263:48] node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 263:43] node _readys_unready_T_2 = shr(_readys_unready_T_1, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 263:48] node _readys_unready_T_3 = or(_readys_unready_T_1, _readys_unready_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 263:43] node _readys_unready_T_4 = bits(_readys_unready_T_3, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 264:17] node _readys_unready_T_5 = shr(_readys_unready_T_4, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 25:52] node _readys_unready_T_6 = shl(readys_mask, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 25:66] node readys_unready = or(_readys_unready_T_5, _readys_unready_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 25:58] node _readys_readys_T = shr(readys_unready, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:29] node _readys_readys_T_1 = bits(readys_unready, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:48] node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:39] node readys_readys = not(_readys_readys_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:18] node _readys_T_5 = orr(readys_valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 27:27] node _readys_T_6 = and(latch, _readys_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 27:18] when _readys_T_6 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 27:32] node _readys_mask_T = and(readys_readys, readys_valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 28:29] node _readys_mask_T_1 = shl(_readys_mask_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _readys_mask_T_2 = bits(_readys_mask_T_1, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _readys_mask_T_4 = shl(_readys_mask_T_3, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _readys_mask_T_5 = bits(_readys_mask_T_4, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _readys_mask_T_6 = or(_readys_mask_T_3, _readys_mask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _readys_mask_T_7 = bits(_readys_mask_T_6, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 255:17] connect readys_mask, _readys_mask_T_7 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 28:12] node _readys_T_7 = bits(readys_readys, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 30:11] node _readys_T_8 = bits(_readys_T_7, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] node _readys_T_9 = bits(_readys_T_7, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] node _readys_T_10 = bits(_readys_T_7, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] node _readys_T_11 = bits(_readys_T_7, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] wire readys : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[0], _readys_T_8 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[1], _readys_T_9 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[2], _readys_T_10 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[3], _readys_T_11 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] node _winner_T = and(readys[0], portsDIO_filtered[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] node _winner_T_1 = and(readys[1], portsDIO_filtered_1[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] node _winner_T_2 = and(readys[2], portsDIO_filtered_2[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] node _winner_T_3 = and(readys[3], portsDIO_filtered_3[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] wire winner : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[0], _winner_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[1], _winner_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[2], _winner_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[3], _winner_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] node prefixOR_1 = or(UInt<1>(0h0), winner[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node prefixOR_2 = or(prefixOR_1, winner[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node prefixOR_3 = or(prefixOR_2, winner[2]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node _prefixOR_T = or(prefixOR_3, winner[3]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_1 = eq(winner[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_2 = or(_T, _T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_4 = eq(winner[1], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_5 = or(_T_3, _T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_6 = eq(prefixOR_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_7 = eq(winner[2], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_8 = or(_T_6, _T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_9 = eq(prefixOR_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_10 = eq(winner[3], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_11 = or(_T_9, _T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_12 = and(_T_2, _T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:77] node _T_13 = and(_T_12, _T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:77] node _T_14 = and(_T_13, _T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:77] node _T_15 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_16 = eq(_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] when _T_16 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_17 = eq(_T_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] when _T_17 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] assert(clock, _T_14, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_18 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:31] node _T_19 = or(_T_18, portsDIO_filtered_2[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:31] node _T_20 = or(_T_19, portsDIO_filtered_3[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:31] node _T_21 = eq(_T_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:15] node _T_22 = or(winner[0], winner[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:54] node _T_23 = or(_T_22, winner[2]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:54] node _T_24 = or(_T_23, winner[3]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:54] node _T_25 = or(_T_21, _T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:36] node _T_26 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node _T_27 = eq(_T_26, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] when _T_27 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node _T_28 = eq(_T_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] when _T_28 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] assert(clock, _T_25, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node maskedBeats_0 = mux(winner[0], beatsDO_0, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node maskedBeats_1 = mux(winner[1], beatsDO_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node maskedBeats_2 = mux(winner[2], beatsDO_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node maskedBeats_3 = mux(winner[3], beatsDO_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node _initBeats_T = or(maskedBeats_0, maskedBeats_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 84:44] node _initBeats_T_1 = or(_initBeats_T, maskedBeats_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 84:44] node initBeats = or(_initBeats_T_1, maskedBeats_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 84:44] node _beatsLeft_T = and(in[0].d.ready, in[0].d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:52] node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:52] node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:23] connect beatsLeft, _beatsLeft_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:17] wire _state_WIRE : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] regreset state : UInt<1>[4], clock, reset, _state_WIRE @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:26] node muxState = mux(idle, winner, state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 89:25] connect state, muxState @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 90:13] node allowed = mux(idle, readys, state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 92:24] node _filtered_0_ready_T = and(in[0].d.ready, allowed[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect portsDIO_filtered[0].ready, _filtered_0_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _filtered_0_ready_T_1 = and(in[0].d.ready, allowed[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _filtered_0_ready_T_2 = and(in[0].d.ready, allowed[2]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect portsDIO_filtered_2[0].ready, _filtered_0_ready_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _filtered_0_ready_T_3 = and(in[0].d.ready, allowed[3]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect portsDIO_filtered_3[0].ready, _filtered_0_ready_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:46] node _in_0_d_valid_T_1 = or(_in_0_d_valid_T, portsDIO_filtered_2[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:46] node _in_0_d_valid_T_2 = or(_in_0_d_valid_T_1, portsDIO_filtered_3[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:46] node _in_0_d_valid_T_3 = mux(state[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_4 = mux(state[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_5 = mux(state[2], portsDIO_filtered_2[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_6 = mux(state[3], portsDIO_filtered_3[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_7 = or(_in_0_d_valid_T_3, _in_0_d_valid_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_8 = or(_in_0_d_valid_T_7, _in_0_d_valid_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_9 = or(_in_0_d_valid_T_8, _in_0_d_valid_T_6) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_valid_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_valid_WIRE, _in_0_d_valid_T_9 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_10 = mux(idle, _in_0_d_valid_T_2, _in_0_d_valid_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:24] connect in[0].d.valid, _in_0_d_valid_T_10 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:18] wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T = mux(muxState[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_1 = mux(muxState[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_2 = mux(muxState[2], portsDIO_filtered_2[0].bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_3 = mux(muxState[3], portsDIO_filtered_3[0].bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_4 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_4, _in_0_d_bits_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_6 = or(_in_0_d_bits_T_5, _in_0_d_bits_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_1 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_6 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_7 = mux(muxState[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_8 = mux(muxState[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_9 = mux(muxState[2], portsDIO_filtered_2[0].bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_10 = mux(muxState[3], portsDIO_filtered_3[0].bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_7, _in_0_d_bits_T_8) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_12 = or(_in_0_d_bits_T_11, _in_0_d_bits_T_9) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_13 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_10) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_2 : UInt<64> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_13 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_3 : { } @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_4 : { } @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_14 = mux(muxState[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_15 = mux(muxState[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_16 = mux(muxState[2], portsDIO_filtered_2[0].bits.denied, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_17 = mux(muxState[3], portsDIO_filtered_3[0].bits.denied, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_18 = or(_in_0_d_bits_T_14, _in_0_d_bits_T_15) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_19 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_16) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_19, _in_0_d_bits_T_17) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_5 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_20 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_21 = mux(muxState[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_22 = mux(muxState[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_23 = mux(muxState[2], portsDIO_filtered_2[0].bits.sink, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_24 = mux(muxState[3], portsDIO_filtered_3[0].bits.sink, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_25 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_26 = or(_in_0_d_bits_T_25, _in_0_d_bits_T_23) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_27 = or(_in_0_d_bits_T_26, _in_0_d_bits_T_24) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_6 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_27 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_28 = mux(muxState[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_29 = mux(muxState[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_30 = mux(muxState[2], portsDIO_filtered_2[0].bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_31 = mux(muxState[3], portsDIO_filtered_3[0].bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_32 = or(_in_0_d_bits_T_28, _in_0_d_bits_T_29) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_33 = or(_in_0_d_bits_T_32, _in_0_d_bits_T_30) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_34 = or(_in_0_d_bits_T_33, _in_0_d_bits_T_31) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_7 : UInt<2> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_34 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_35 = mux(muxState[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_36 = mux(muxState[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_37 = mux(muxState[2], portsDIO_filtered_2[0].bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_38 = mux(muxState[3], portsDIO_filtered_3[0].bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_39 = or(_in_0_d_bits_T_35, _in_0_d_bits_T_36) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_40 = or(_in_0_d_bits_T_39, _in_0_d_bits_T_37) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_41 = or(_in_0_d_bits_T_40, _in_0_d_bits_T_38) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_8 : UInt<3> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_41 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_42 = mux(muxState[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_43 = mux(muxState[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_44 = mux(muxState[2], portsDIO_filtered_2[0].bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_45 = mux(muxState[3], portsDIO_filtered_3[0].bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_46 = or(_in_0_d_bits_T_42, _in_0_d_bits_T_43) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_47 = or(_in_0_d_bits_T_46, _in_0_d_bits_T_44) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_48 = or(_in_0_d_bits_T_47, _in_0_d_bits_T_45) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_9 : UInt<2> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_48 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_49 = mux(muxState[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_50 = mux(muxState[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_51 = mux(muxState[2], portsDIO_filtered_2[0].bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_52 = mux(muxState[3], portsDIO_filtered_3[0].bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_53 = or(_in_0_d_bits_T_49, _in_0_d_bits_T_50) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_54 = or(_in_0_d_bits_T_53, _in_0_d_bits_T_51) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_55 = or(_in_0_d_bits_T_54, _in_0_d_bits_T_52) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_10 : UInt<3> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_55 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.data, _in_0_d_bits_WIRE.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.source, _in_0_d_bits_WIRE.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.size, _in_0_d_bits_WIRE.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.param, _in_0_d_bits_WIRE.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect portsBIO_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] connect portsBIO_filtered_1[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] connect portsBIO_filtered_2[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] connect portsBIO_filtered_3[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] module Queue2_TLBundleA_a29d64s2k1z3u : @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input clock : Clock @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input reset : Reset @[src/main/scala/chisel3/util/Decoupled.scala 243:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, count : UInt<2>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} [2] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] regreset enq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset deq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] infer mport MPORT = ram[enq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 270:24] node wrap = eq(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T = add(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_1 = tail(_value_T, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect enq_ptr_value, _value_T_1 @[src/main/scala/chisel3/util/Counter.scala 77:15] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] node wrap_1 = eq(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_3 = tail(_value_T_2, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect deq_ptr_value, _value_T_3 @[src/main/scala/chisel3/util/Counter.scala 77:15] node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] infer mport io_deq_bits_MPORT = ram[deq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module Queue2_TLBundleD_a29d64s2k1z3u : @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input clock : Clock @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input reset : Reset @[src/main/scala/chisel3/util/Decoupled.scala 243:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, count : UInt<2>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} [2] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] regreset enq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset deq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] infer mport MPORT = ram[enq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 270:24] node wrap = eq(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T = add(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_1 = tail(_value_T, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect enq_ptr_value, _value_T_1 @[src/main/scala/chisel3/util/Counter.scala 77:15] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] node wrap_1 = eq(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_3 = tail(_value_T_2, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect deq_ptr_value, _value_T_3 @[src/main/scala/chisel3/util/Counter.scala 77:15] node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] infer mport io_deq_bits_MPORT = ram[deq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module TLBuffer_a29d64s2k1z3u : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] inst nodeOut_a_q of Queue2_TLBundleA_a29d64s2k1z3u @[src/main/scala/chisel3/util/Decoupled.scala 362:21] connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid @[src/main/scala/chisel3/util/Decoupled.scala 364:22] connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.fetch, nodeIn.a.bits.user.amba_prot.fetch @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.secure, nodeIn.a.bits.user.amba_prot.secure @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.privileged, nodeIn.a.bits.user.amba_prot.privileged @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.writealloc, nodeIn.a.bits.user.amba_prot.writealloc @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.readalloc, nodeIn.a.bits.user.amba_prot.readalloc @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.modifiable, nodeIn.a.bits.user.amba_prot.modifiable @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.bufferable, nodeIn.a.bits.user.amba_prot.bufferable @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready @[src/main/scala/chisel3/util/Decoupled.scala 366:17] connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] inst nodeIn_d_q of Queue2_TLBundleD_a29d64s2k1z3u @[src/main/scala/chisel3/util/Decoupled.scala 362:21] connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid @[src/main/scala/chisel3/util/Decoupled.scala 364:22] connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready @[src/main/scala/chisel3/util/Decoupled.scala 366:17] connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 52:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 53:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 54:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 55:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 56:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 57:21] module TLAtomicAutomata_pbus : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 36:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 36:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 36:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] wire initval : { state : UInt<2>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 80:27] connect initval.state, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 81:23] wire _cam_s_WIRE : { state : UInt<2>}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 82:50] connect _cam_s_WIRE[0], initval @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 82:50] regreset cam_s : { state : UInt<2>}[1], clock, reset, _cam_s_WIRE @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 82:28] reg cam_a : { bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, fifoId : UInt<1>, lut : UInt<4>}[1], clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 83:24] reg cam_d : { data : UInt<64>, denied : UInt<1>, corrupt : UInt<1>}[1], clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 84:24] node cam_free_0 = eq(cam_s[0].state, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 86:44] node cam_amo_0 = eq(cam_s[0].state, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 87:44] node _cam_abusy_T = eq(cam_s[0].state, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 88:49] node _cam_abusy_T_1 = eq(cam_s[0].state, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 88:68] node cam_abusy_0 = or(_cam_abusy_T, _cam_abusy_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 88:57] node cam_dmatch_0 = neq(cam_s[0].state, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 89:49] node _a_canLogical_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _a_canLogical_T_1 = xor(nodeIn.a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canLogical_T_2 = cvt(_a_canLogical_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canLogical_T_3 = and(_a_canLogical_T_2, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_4 = asSInt(_a_canLogical_T_3) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_5 = eq(_a_canLogical_T_4, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canLogical_T_6 = and(_a_canLogical_T, _a_canLogical_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _a_canLogical_T_7 = or(UInt<1>(0h0), _a_canLogical_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node a_canLogical = and(UInt<1>(0h1), _a_canLogical_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 94:45] node _a_canArithmetic_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _a_canArithmetic_T_1 = xor(nodeIn.a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canArithmetic_T_2 = cvt(_a_canArithmetic_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canArithmetic_T_3 = and(_a_canArithmetic_T_2, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_4 = asSInt(_a_canArithmetic_T_3) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_5 = eq(_a_canArithmetic_T_4, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canArithmetic_T_6 = and(_a_canArithmetic_T, _a_canArithmetic_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _a_canArithmetic_T_7 = or(UInt<1>(0h0), _a_canArithmetic_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node a_canArithmetic = and(UInt<1>(0h1), _a_canArithmetic_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 95:45] node a_isLogical = eq(nodeIn.a.bits.opcode, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 96:47] node a_isArithmetic = eq(nodeIn.a.bits.opcode, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 97:47] node _a_isSupported_T = mux(a_isArithmetic, a_canArithmetic, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 98:63] node a_isSupported = mux(a_isLogical, a_canLogical, _a_isSupported_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 98:32] node _a_cam_por_put_T = or(UInt<1>(0h0), cam_amo_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 102:56] node _a_cam_sel_put_T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 103:83] node a_cam_sel_put_0 = and(cam_amo_0, _a_cam_sel_put_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 103:80] node _a_fifoId_T = xor(nodeIn.a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_fifoId_T_1 = cvt(_a_fifoId_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_fifoId_T_2 = and(_a_fifoId_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_fifoId_T_3 = asSInt(_a_fifoId_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_fifoId_T_4 = eq(_a_fifoId_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_cam_busy_T = eq(cam_a[0].fifoId, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 111:60] node a_cam_busy = and(cam_abusy_0, _a_cam_busy_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 111:96] node _a_cam_por_free_T = or(UInt<1>(0h0), cam_free_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 115:58] node _a_cam_sel_free_T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 116:85] node a_cam_sel_free_0 = and(cam_free_0, _a_cam_sel_free_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 116:82] node _indexes_T = bits(cam_a[0].bits.data, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_1 = bits(cam_d[0].data, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_0 = cat(_indexes_T, _indexes_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_2 = bits(cam_a[0].bits.data, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_3 = bits(cam_d[0].data, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_1 = cat(_indexes_T_2, _indexes_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_4 = bits(cam_a[0].bits.data, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_5 = bits(cam_d[0].data, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_2 = cat(_indexes_T_4, _indexes_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_6 = bits(cam_a[0].bits.data, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_7 = bits(cam_d[0].data, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_3 = cat(_indexes_T_6, _indexes_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_8 = bits(cam_a[0].bits.data, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_9 = bits(cam_d[0].data, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_4 = cat(_indexes_T_8, _indexes_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_10 = bits(cam_a[0].bits.data, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_11 = bits(cam_d[0].data, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_5 = cat(_indexes_T_10, _indexes_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_12 = bits(cam_a[0].bits.data, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_13 = bits(cam_d[0].data, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_6 = cat(_indexes_T_12, _indexes_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_14 = bits(cam_a[0].bits.data, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_15 = bits(cam_d[0].data, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_7 = cat(_indexes_T_14, _indexes_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_16 = bits(cam_a[0].bits.data, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_17 = bits(cam_d[0].data, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_8 = cat(_indexes_T_16, _indexes_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_18 = bits(cam_a[0].bits.data, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_19 = bits(cam_d[0].data, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_9 = cat(_indexes_T_18, _indexes_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_20 = bits(cam_a[0].bits.data, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_21 = bits(cam_d[0].data, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_10 = cat(_indexes_T_20, _indexes_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_22 = bits(cam_a[0].bits.data, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_23 = bits(cam_d[0].data, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_11 = cat(_indexes_T_22, _indexes_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_24 = bits(cam_a[0].bits.data, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_25 = bits(cam_d[0].data, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_12 = cat(_indexes_T_24, _indexes_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_26 = bits(cam_a[0].bits.data, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_27 = bits(cam_d[0].data, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_13 = cat(_indexes_T_26, _indexes_T_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_28 = bits(cam_a[0].bits.data, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_29 = bits(cam_d[0].data, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_14 = cat(_indexes_T_28, _indexes_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_30 = bits(cam_a[0].bits.data, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_31 = bits(cam_d[0].data, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_15 = cat(_indexes_T_30, _indexes_T_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_32 = bits(cam_a[0].bits.data, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_33 = bits(cam_d[0].data, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_16 = cat(_indexes_T_32, _indexes_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_34 = bits(cam_a[0].bits.data, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_35 = bits(cam_d[0].data, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_17 = cat(_indexes_T_34, _indexes_T_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_36 = bits(cam_a[0].bits.data, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_37 = bits(cam_d[0].data, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_18 = cat(_indexes_T_36, _indexes_T_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_38 = bits(cam_a[0].bits.data, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_39 = bits(cam_d[0].data, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_19 = cat(_indexes_T_38, _indexes_T_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_40 = bits(cam_a[0].bits.data, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_41 = bits(cam_d[0].data, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_20 = cat(_indexes_T_40, _indexes_T_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_42 = bits(cam_a[0].bits.data, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_43 = bits(cam_d[0].data, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_21 = cat(_indexes_T_42, _indexes_T_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_44 = bits(cam_a[0].bits.data, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_45 = bits(cam_d[0].data, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_22 = cat(_indexes_T_44, _indexes_T_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_46 = bits(cam_a[0].bits.data, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_47 = bits(cam_d[0].data, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_23 = cat(_indexes_T_46, _indexes_T_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_48 = bits(cam_a[0].bits.data, 24, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_49 = bits(cam_d[0].data, 24, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_24 = cat(_indexes_T_48, _indexes_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_50 = bits(cam_a[0].bits.data, 25, 25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_51 = bits(cam_d[0].data, 25, 25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_25 = cat(_indexes_T_50, _indexes_T_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_52 = bits(cam_a[0].bits.data, 26, 26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_53 = bits(cam_d[0].data, 26, 26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_26 = cat(_indexes_T_52, _indexes_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_54 = bits(cam_a[0].bits.data, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_55 = bits(cam_d[0].data, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_27 = cat(_indexes_T_54, _indexes_T_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_56 = bits(cam_a[0].bits.data, 28, 28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_57 = bits(cam_d[0].data, 28, 28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_28 = cat(_indexes_T_56, _indexes_T_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_58 = bits(cam_a[0].bits.data, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_59 = bits(cam_d[0].data, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_29 = cat(_indexes_T_58, _indexes_T_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_60 = bits(cam_a[0].bits.data, 30, 30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_61 = bits(cam_d[0].data, 30, 30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_30 = cat(_indexes_T_60, _indexes_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_62 = bits(cam_a[0].bits.data, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_63 = bits(cam_d[0].data, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_31 = cat(_indexes_T_62, _indexes_T_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_64 = bits(cam_a[0].bits.data, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_65 = bits(cam_d[0].data, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_32 = cat(_indexes_T_64, _indexes_T_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_66 = bits(cam_a[0].bits.data, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_67 = bits(cam_d[0].data, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_33 = cat(_indexes_T_66, _indexes_T_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_68 = bits(cam_a[0].bits.data, 34, 34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_69 = bits(cam_d[0].data, 34, 34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_34 = cat(_indexes_T_68, _indexes_T_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_70 = bits(cam_a[0].bits.data, 35, 35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_71 = bits(cam_d[0].data, 35, 35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_35 = cat(_indexes_T_70, _indexes_T_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_72 = bits(cam_a[0].bits.data, 36, 36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_73 = bits(cam_d[0].data, 36, 36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_36 = cat(_indexes_T_72, _indexes_T_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_74 = bits(cam_a[0].bits.data, 37, 37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_75 = bits(cam_d[0].data, 37, 37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_37 = cat(_indexes_T_74, _indexes_T_75) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_76 = bits(cam_a[0].bits.data, 38, 38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_77 = bits(cam_d[0].data, 38, 38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_38 = cat(_indexes_T_76, _indexes_T_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_78 = bits(cam_a[0].bits.data, 39, 39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_79 = bits(cam_d[0].data, 39, 39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_39 = cat(_indexes_T_78, _indexes_T_79) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_80 = bits(cam_a[0].bits.data, 40, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_81 = bits(cam_d[0].data, 40, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_40 = cat(_indexes_T_80, _indexes_T_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_82 = bits(cam_a[0].bits.data, 41, 41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_83 = bits(cam_d[0].data, 41, 41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_41 = cat(_indexes_T_82, _indexes_T_83) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_84 = bits(cam_a[0].bits.data, 42, 42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_85 = bits(cam_d[0].data, 42, 42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_42 = cat(_indexes_T_84, _indexes_T_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_86 = bits(cam_a[0].bits.data, 43, 43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_87 = bits(cam_d[0].data, 43, 43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_43 = cat(_indexes_T_86, _indexes_T_87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_88 = bits(cam_a[0].bits.data, 44, 44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_89 = bits(cam_d[0].data, 44, 44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_44 = cat(_indexes_T_88, _indexes_T_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_90 = bits(cam_a[0].bits.data, 45, 45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_91 = bits(cam_d[0].data, 45, 45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_45 = cat(_indexes_T_90, _indexes_T_91) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_92 = bits(cam_a[0].bits.data, 46, 46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_93 = bits(cam_d[0].data, 46, 46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_46 = cat(_indexes_T_92, _indexes_T_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_94 = bits(cam_a[0].bits.data, 47, 47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_95 = bits(cam_d[0].data, 47, 47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_47 = cat(_indexes_T_94, _indexes_T_95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_96 = bits(cam_a[0].bits.data, 48, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_97 = bits(cam_d[0].data, 48, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_48 = cat(_indexes_T_96, _indexes_T_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_98 = bits(cam_a[0].bits.data, 49, 49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_99 = bits(cam_d[0].data, 49, 49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_49 = cat(_indexes_T_98, _indexes_T_99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_100 = bits(cam_a[0].bits.data, 50, 50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_101 = bits(cam_d[0].data, 50, 50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_50 = cat(_indexes_T_100, _indexes_T_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_102 = bits(cam_a[0].bits.data, 51, 51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_103 = bits(cam_d[0].data, 51, 51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_51 = cat(_indexes_T_102, _indexes_T_103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_104 = bits(cam_a[0].bits.data, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_105 = bits(cam_d[0].data, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_52 = cat(_indexes_T_104, _indexes_T_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_106 = bits(cam_a[0].bits.data, 53, 53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_107 = bits(cam_d[0].data, 53, 53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_53 = cat(_indexes_T_106, _indexes_T_107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_108 = bits(cam_a[0].bits.data, 54, 54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_109 = bits(cam_d[0].data, 54, 54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_54 = cat(_indexes_T_108, _indexes_T_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_110 = bits(cam_a[0].bits.data, 55, 55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_111 = bits(cam_d[0].data, 55, 55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_55 = cat(_indexes_T_110, _indexes_T_111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_112 = bits(cam_a[0].bits.data, 56, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_113 = bits(cam_d[0].data, 56, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_56 = cat(_indexes_T_112, _indexes_T_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_114 = bits(cam_a[0].bits.data, 57, 57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_115 = bits(cam_d[0].data, 57, 57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_57 = cat(_indexes_T_114, _indexes_T_115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_116 = bits(cam_a[0].bits.data, 58, 58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_117 = bits(cam_d[0].data, 58, 58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_58 = cat(_indexes_T_116, _indexes_T_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_118 = bits(cam_a[0].bits.data, 59, 59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_119 = bits(cam_d[0].data, 59, 59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_59 = cat(_indexes_T_118, _indexes_T_119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_120 = bits(cam_a[0].bits.data, 60, 60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_121 = bits(cam_d[0].data, 60, 60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_60 = cat(_indexes_T_120, _indexes_T_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_122 = bits(cam_a[0].bits.data, 61, 61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_123 = bits(cam_d[0].data, 61, 61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_61 = cat(_indexes_T_122, _indexes_T_123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_124 = bits(cam_a[0].bits.data, 62, 62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_125 = bits(cam_d[0].data, 62, 62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_62 = cat(_indexes_T_124, _indexes_T_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_126 = bits(cam_a[0].bits.data, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_127 = bits(cam_d[0].data, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_63 = cat(_indexes_T_126, _indexes_T_127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _logic_out_T = dshr(cam_a[0].lut, indexes_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_1 = bits(_logic_out_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_2 = dshr(cam_a[0].lut, indexes_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_3 = bits(_logic_out_T_2, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_4 = dshr(cam_a[0].lut, indexes_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_5 = bits(_logic_out_T_4, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_6 = dshr(cam_a[0].lut, indexes_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_7 = bits(_logic_out_T_6, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_8 = dshr(cam_a[0].lut, indexes_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_9 = bits(_logic_out_T_8, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_10 = dshr(cam_a[0].lut, indexes_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_11 = bits(_logic_out_T_10, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_12 = dshr(cam_a[0].lut, indexes_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_13 = bits(_logic_out_T_12, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_14 = dshr(cam_a[0].lut, indexes_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_15 = bits(_logic_out_T_14, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_16 = dshr(cam_a[0].lut, indexes_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_17 = bits(_logic_out_T_16, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_18 = dshr(cam_a[0].lut, indexes_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_19 = bits(_logic_out_T_18, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_20 = dshr(cam_a[0].lut, indexes_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_21 = bits(_logic_out_T_20, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_22 = dshr(cam_a[0].lut, indexes_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_23 = bits(_logic_out_T_22, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_24 = dshr(cam_a[0].lut, indexes_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_25 = bits(_logic_out_T_24, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_26 = dshr(cam_a[0].lut, indexes_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_27 = bits(_logic_out_T_26, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_28 = dshr(cam_a[0].lut, indexes_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_29 = bits(_logic_out_T_28, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_30 = dshr(cam_a[0].lut, indexes_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_31 = bits(_logic_out_T_30, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_32 = dshr(cam_a[0].lut, indexes_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_33 = bits(_logic_out_T_32, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_34 = dshr(cam_a[0].lut, indexes_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_35 = bits(_logic_out_T_34, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_36 = dshr(cam_a[0].lut, indexes_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_37 = bits(_logic_out_T_36, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_38 = dshr(cam_a[0].lut, indexes_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_39 = bits(_logic_out_T_38, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_40 = dshr(cam_a[0].lut, indexes_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_41 = bits(_logic_out_T_40, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_42 = dshr(cam_a[0].lut, indexes_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_43 = bits(_logic_out_T_42, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_44 = dshr(cam_a[0].lut, indexes_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_45 = bits(_logic_out_T_44, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_46 = dshr(cam_a[0].lut, indexes_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_47 = bits(_logic_out_T_46, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_48 = dshr(cam_a[0].lut, indexes_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_49 = bits(_logic_out_T_48, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_50 = dshr(cam_a[0].lut, indexes_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_51 = bits(_logic_out_T_50, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_52 = dshr(cam_a[0].lut, indexes_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_53 = bits(_logic_out_T_52, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_54 = dshr(cam_a[0].lut, indexes_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_55 = bits(_logic_out_T_54, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_56 = dshr(cam_a[0].lut, indexes_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_57 = bits(_logic_out_T_56, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_58 = dshr(cam_a[0].lut, indexes_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_59 = bits(_logic_out_T_58, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_60 = dshr(cam_a[0].lut, indexes_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_61 = bits(_logic_out_T_60, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_62 = dshr(cam_a[0].lut, indexes_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_63 = bits(_logic_out_T_62, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_64 = dshr(cam_a[0].lut, indexes_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_65 = bits(_logic_out_T_64, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_66 = dshr(cam_a[0].lut, indexes_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_67 = bits(_logic_out_T_66, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_68 = dshr(cam_a[0].lut, indexes_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_69 = bits(_logic_out_T_68, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_70 = dshr(cam_a[0].lut, indexes_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_71 = bits(_logic_out_T_70, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_72 = dshr(cam_a[0].lut, indexes_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_73 = bits(_logic_out_T_72, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_74 = dshr(cam_a[0].lut, indexes_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_75 = bits(_logic_out_T_74, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_76 = dshr(cam_a[0].lut, indexes_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_77 = bits(_logic_out_T_76, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_78 = dshr(cam_a[0].lut, indexes_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_79 = bits(_logic_out_T_78, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_80 = dshr(cam_a[0].lut, indexes_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_81 = bits(_logic_out_T_80, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_82 = dshr(cam_a[0].lut, indexes_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_83 = bits(_logic_out_T_82, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_84 = dshr(cam_a[0].lut, indexes_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_85 = bits(_logic_out_T_84, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_86 = dshr(cam_a[0].lut, indexes_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_87 = bits(_logic_out_T_86, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_88 = dshr(cam_a[0].lut, indexes_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_89 = bits(_logic_out_T_88, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_90 = dshr(cam_a[0].lut, indexes_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_91 = bits(_logic_out_T_90, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_92 = dshr(cam_a[0].lut, indexes_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_93 = bits(_logic_out_T_92, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_94 = dshr(cam_a[0].lut, indexes_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_95 = bits(_logic_out_T_94, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_96 = dshr(cam_a[0].lut, indexes_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_97 = bits(_logic_out_T_96, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_98 = dshr(cam_a[0].lut, indexes_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_99 = bits(_logic_out_T_98, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_100 = dshr(cam_a[0].lut, indexes_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_101 = bits(_logic_out_T_100, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_102 = dshr(cam_a[0].lut, indexes_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_103 = bits(_logic_out_T_102, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_104 = dshr(cam_a[0].lut, indexes_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_105 = bits(_logic_out_T_104, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_106 = dshr(cam_a[0].lut, indexes_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_107 = bits(_logic_out_T_106, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_108 = dshr(cam_a[0].lut, indexes_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_109 = bits(_logic_out_T_108, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_110 = dshr(cam_a[0].lut, indexes_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_111 = bits(_logic_out_T_110, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_112 = dshr(cam_a[0].lut, indexes_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_113 = bits(_logic_out_T_112, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_114 = dshr(cam_a[0].lut, indexes_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_115 = bits(_logic_out_T_114, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_116 = dshr(cam_a[0].lut, indexes_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_117 = bits(_logic_out_T_116, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_118 = dshr(cam_a[0].lut, indexes_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_119 = bits(_logic_out_T_118, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_120 = dshr(cam_a[0].lut, indexes_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_121 = bits(_logic_out_T_120, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_122 = dshr(cam_a[0].lut, indexes_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_123 = bits(_logic_out_T_122, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_124 = dshr(cam_a[0].lut, indexes_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_125 = bits(_logic_out_T_124, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_126 = dshr(cam_a[0].lut, indexes_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_127 = bits(_logic_out_T_126, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node logic_out_lo_lo_lo_lo_lo = cat(_logic_out_T_3, _logic_out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_lo_lo_hi = cat(_logic_out_T_7, _logic_out_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_lo_lo = cat(logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_lo_hi_lo = cat(_logic_out_T_11, _logic_out_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_lo_hi_hi = cat(_logic_out_T_15, _logic_out_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_lo_hi = cat(logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_lo = cat(logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_hi_lo_lo = cat(_logic_out_T_19, _logic_out_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_hi_lo_hi = cat(_logic_out_T_23, _logic_out_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_hi_lo = cat(logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_hi_hi_lo = cat(_logic_out_T_27, _logic_out_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_hi_hi_hi = cat(_logic_out_T_31, _logic_out_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_hi_hi = cat(logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_hi = cat(logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo = cat(logic_out_lo_lo_hi, logic_out_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_lo_lo_lo = cat(_logic_out_T_35, _logic_out_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_lo_lo_hi = cat(_logic_out_T_39, _logic_out_T_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_lo_lo = cat(logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_lo_hi_lo = cat(_logic_out_T_43, _logic_out_T_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_lo_hi_hi = cat(_logic_out_T_47, _logic_out_T_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_lo_hi = cat(logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_lo = cat(logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_hi_lo_lo = cat(_logic_out_T_51, _logic_out_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_hi_lo_hi = cat(_logic_out_T_55, _logic_out_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_hi_lo = cat(logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_hi_hi_lo = cat(_logic_out_T_59, _logic_out_T_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_hi_hi_hi = cat(_logic_out_T_63, _logic_out_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_hi_hi = cat(logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_hi = cat(logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi = cat(logic_out_lo_hi_hi, logic_out_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo = cat(logic_out_lo_hi, logic_out_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_lo_lo_lo = cat(_logic_out_T_67, _logic_out_T_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_lo_lo_hi = cat(_logic_out_T_71, _logic_out_T_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_lo_lo = cat(logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_lo_hi_lo = cat(_logic_out_T_75, _logic_out_T_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_lo_hi_hi = cat(_logic_out_T_79, _logic_out_T_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_lo_hi = cat(logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_lo = cat(logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_hi_lo_lo = cat(_logic_out_T_83, _logic_out_T_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_hi_lo_hi = cat(_logic_out_T_87, _logic_out_T_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_hi_lo = cat(logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_hi_hi_lo = cat(_logic_out_T_91, _logic_out_T_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_hi_hi_hi = cat(_logic_out_T_95, _logic_out_T_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_hi_hi = cat(logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_hi = cat(logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo = cat(logic_out_hi_lo_hi, logic_out_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_lo_lo_lo = cat(_logic_out_T_99, _logic_out_T_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_lo_lo_hi = cat(_logic_out_T_103, _logic_out_T_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_lo_lo = cat(logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_lo_hi_lo = cat(_logic_out_T_107, _logic_out_T_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_lo_hi_hi = cat(_logic_out_T_111, _logic_out_T_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_lo_hi = cat(logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_lo = cat(logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_hi_lo_lo = cat(_logic_out_T_115, _logic_out_T_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_hi_lo_hi = cat(_logic_out_T_119, _logic_out_T_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_hi_lo = cat(logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_hi_hi_lo = cat(_logic_out_T_123, _logic_out_T_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_hi_hi_hi = cat(_logic_out_T_127, _logic_out_T_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_hi_hi = cat(logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_hi = cat(logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi = cat(logic_out_hi_hi_hi, logic_out_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi = cat(logic_out_hi_hi, logic_out_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out = cat(logic_out_hi, logic_out_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node unsigned = bits(cam_a[0].bits.param, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 123:42] node take_max = bits(cam_a[0].bits.param, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 124:42] node adder = bits(cam_a[0].bits.param, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 125:39] node _signSel_T = not(cam_a[0].bits.mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 127:25] node _signSel_T_1 = shr(cam_a[0].bits.mask, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 127:39] node _signSel_T_2 = or(_signSel_T, _signSel_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 127:31] node signSel = not(_signSel_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 127:23] node _signbits_a_T = bits(cam_a[0].bits.data, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:64] node _signbits_a_T_1 = bits(cam_a[0].bits.data, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:64] node _signbits_a_T_2 = bits(cam_a[0].bits.data, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:64] node _signbits_a_T_3 = bits(cam_a[0].bits.data, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:64] node _signbits_a_T_4 = bits(cam_a[0].bits.data, 39, 39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:64] node _signbits_a_T_5 = bits(cam_a[0].bits.data, 47, 47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:64] node _signbits_a_T_6 = bits(cam_a[0].bits.data, 55, 55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:64] node _signbits_a_T_7 = bits(cam_a[0].bits.data, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:64] node signbits_a_lo_lo = cat(_signbits_a_T_1, _signbits_a_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:29] node signbits_a_lo_hi = cat(_signbits_a_T_3, _signbits_a_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:29] node signbits_a_lo = cat(signbits_a_lo_hi, signbits_a_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:29] node signbits_a_hi_lo = cat(_signbits_a_T_5, _signbits_a_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:29] node signbits_a_hi_hi = cat(_signbits_a_T_7, _signbits_a_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:29] node signbits_a_hi = cat(signbits_a_hi_hi, signbits_a_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:29] node signbits_a = cat(signbits_a_hi, signbits_a_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:29] node _signbits_d_T = bits(cam_d[0].data, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:64] node _signbits_d_T_1 = bits(cam_d[0].data, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:64] node _signbits_d_T_2 = bits(cam_d[0].data, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:64] node _signbits_d_T_3 = bits(cam_d[0].data, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:64] node _signbits_d_T_4 = bits(cam_d[0].data, 39, 39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:64] node _signbits_d_T_5 = bits(cam_d[0].data, 47, 47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:64] node _signbits_d_T_6 = bits(cam_d[0].data, 55, 55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:64] node _signbits_d_T_7 = bits(cam_d[0].data, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:64] node signbits_d_lo_lo = cat(_signbits_d_T_1, _signbits_d_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:29] node signbits_d_lo_hi = cat(_signbits_d_T_3, _signbits_d_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:29] node signbits_d_lo = cat(signbits_d_lo_hi, signbits_d_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:29] node signbits_d_hi_lo = cat(_signbits_d_T_5, _signbits_d_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:29] node signbits_d_hi_hi = cat(_signbits_d_T_7, _signbits_d_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:29] node signbits_d_hi = cat(signbits_d_hi_hi, signbits_d_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:29] node signbits_d = cat(signbits_d_hi, signbits_d_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:29] node _signbit_a_T = and(signbits_a, signSel) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 131:38] node _signbit_a_T_1 = shl(_signbit_a_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 131:49] node signbit_a = bits(_signbit_a_T_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 131:54] node _signbit_d_T = and(signbits_d, signSel) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 132:38] node _signbit_d_T_1 = shl(_signbit_d_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 132:49] node signbit_d = bits(_signbit_d_T_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 132:54] node _signext_a_T = shl(signbit_a, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _signext_a_T_1 = bits(_signext_a_T, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _signext_a_T_2 = or(signbit_a, _signext_a_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _signext_a_T_3 = shl(_signext_a_T_2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _signext_a_T_4 = bits(_signext_a_T_3, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _signext_a_T_5 = or(_signext_a_T_2, _signext_a_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _signext_a_T_6 = shl(_signext_a_T_5, 4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _signext_a_T_7 = bits(_signext_a_T_6, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _signext_a_T_8 = or(_signext_a_T_5, _signext_a_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _signext_a_T_9 = bits(_signext_a_T_8, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 255:17] node _signext_a_T_10 = bits(_signext_a_T_9, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_11 = bits(_signext_a_T_9, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_12 = bits(_signext_a_T_9, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_13 = bits(_signext_a_T_9, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_14 = bits(_signext_a_T_9, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_15 = bits(_signext_a_T_9, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_16 = bits(_signext_a_T_9, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_17 = bits(_signext_a_T_9, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_18 = mux(_signext_a_T_10, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_19 = mux(_signext_a_T_11, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_20 = mux(_signext_a_T_12, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_21 = mux(_signext_a_T_13, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_22 = mux(_signext_a_T_14, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_23 = mux(_signext_a_T_15, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_24 = mux(_signext_a_T_16, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_25 = mux(_signext_a_T_17, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node signext_a_lo_lo = cat(_signext_a_T_19, _signext_a_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node signext_a_lo_hi = cat(_signext_a_T_21, _signext_a_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node signext_a_lo = cat(signext_a_lo_hi, signext_a_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node signext_a_hi_lo = cat(_signext_a_T_23, _signext_a_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node signext_a_hi_hi = cat(_signext_a_T_25, _signext_a_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node signext_a_hi = cat(signext_a_hi_hi, signext_a_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node signext_a = cat(signext_a_hi, signext_a_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_d_T = shl(signbit_d, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _signext_d_T_1 = bits(_signext_d_T, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _signext_d_T_2 = or(signbit_d, _signext_d_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _signext_d_T_3 = shl(_signext_d_T_2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _signext_d_T_4 = bits(_signext_d_T_3, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _signext_d_T_5 = or(_signext_d_T_2, _signext_d_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _signext_d_T_6 = shl(_signext_d_T_5, 4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _signext_d_T_7 = bits(_signext_d_T_6, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _signext_d_T_8 = or(_signext_d_T_5, _signext_d_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _signext_d_T_9 = bits(_signext_d_T_8, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 255:17] node _signext_d_T_10 = bits(_signext_d_T_9, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_11 = bits(_signext_d_T_9, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_12 = bits(_signext_d_T_9, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_13 = bits(_signext_d_T_9, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_14 = bits(_signext_d_T_9, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_15 = bits(_signext_d_T_9, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_16 = bits(_signext_d_T_9, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_17 = bits(_signext_d_T_9, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_18 = mux(_signext_d_T_10, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_19 = mux(_signext_d_T_11, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_20 = mux(_signext_d_T_12, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_21 = mux(_signext_d_T_13, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_22 = mux(_signext_d_T_14, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_23 = mux(_signext_d_T_15, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_24 = mux(_signext_d_T_16, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_25 = mux(_signext_d_T_17, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node signext_d_lo_lo = cat(_signext_d_T_19, _signext_d_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node signext_d_lo_hi = cat(_signext_d_T_21, _signext_d_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node signext_d_lo = cat(signext_d_lo_hi, signext_d_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node signext_d_hi_lo = cat(_signext_d_T_23, _signext_d_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node signext_d_hi_hi = cat(_signext_d_T_25, _signext_d_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node signext_d_hi = cat(signext_d_hi_hi, signext_d_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node signext_d = cat(signext_d_hi, signext_d_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _wide_mask_T = bits(cam_a[0].bits.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_1 = bits(cam_a[0].bits.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_2 = bits(cam_a[0].bits.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_3 = bits(cam_a[0].bits.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_4 = bits(cam_a[0].bits.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_5 = bits(cam_a[0].bits.mask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_6 = bits(cam_a[0].bits.mask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_7 = bits(cam_a[0].bits.mask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_8 = mux(_wide_mask_T, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_9 = mux(_wide_mask_T_1, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_10 = mux(_wide_mask_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_11 = mux(_wide_mask_T_3, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_12 = mux(_wide_mask_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_13 = mux(_wide_mask_T_5, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_14 = mux(_wide_mask_T_6, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_15 = mux(_wide_mask_T_7, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node wide_mask_lo_lo = cat(_wide_mask_T_9, _wide_mask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node wide_mask_lo_hi = cat(_wide_mask_T_11, _wide_mask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node wide_mask_lo = cat(wide_mask_lo_hi, wide_mask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node wide_mask_hi_lo = cat(_wide_mask_T_13, _wide_mask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node wide_mask_hi_hi = cat(_wide_mask_T_15, _wide_mask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node wide_mask_hi = cat(wide_mask_hi_hi, wide_mask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node wide_mask = cat(wide_mask_hi, wide_mask_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _a_a_ext_T = and(cam_a[0].bits.data, wide_mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 137:28] node a_a_ext = or(_a_a_ext_T, signext_a) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 137:41] node _a_d_ext_T = and(cam_d[0].data, wide_mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 138:28] node a_d_ext = or(_a_d_ext_T, signext_d) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 138:41] node _a_d_inv_T = not(a_d_ext) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 139:43] node a_d_inv = mux(adder, a_d_ext, _a_d_inv_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 139:26] node _adder_out_T = add(a_a_ext, a_d_inv) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 140:33] node adder_out = tail(_adder_out_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 140:33] node _a_bigger_uneq_T = bits(a_a_ext, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 142:49] node a_bigger_uneq = eq(unsigned, _a_bigger_uneq_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 142:38] node _a_bigger_T = bits(a_a_ext, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 143:35] node _a_bigger_T_1 = bits(a_d_ext, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 143:50] node _a_bigger_T_2 = eq(_a_bigger_T, _a_bigger_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 143:39] node _a_bigger_T_3 = bits(adder_out, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 143:65] node _a_bigger_T_4 = eq(_a_bigger_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 143:55] node a_bigger = mux(_a_bigger_T_2, _a_bigger_T_4, a_bigger_uneq) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 143:27] node pick_a = eq(take_max, a_bigger) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 144:31] node _arith_out_T = mux(pick_a, cam_a[0].bits.data, cam_d[0].data) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 145:50] node arith_out = mux(adder, adder_out, _arith_out_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 145:28] node _amo_data_T = bits(cam_a[0].bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 151:34] node amo_data = mux(_amo_data_T, logic_out, arith_out) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 151:14] wire source_i : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 154:28] node _a_allow_T = eq(a_cam_busy, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 155:23] node _a_allow_T_1 = or(a_isSupported, cam_free_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 155:53] node a_allow = and(_a_allow_T, _a_allow_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 155:35] node _nodeIn_a_ready_T = and(source_i.ready, a_allow) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 156:38] connect nodeIn.a.ready, _nodeIn_a_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 156:20] node _source_i_valid_T = and(nodeIn.a.valid, a_allow) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 157:38] connect source_i.valid, _source_i_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 157:24] connect source_i.bits, nodeIn.a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 158:24] node _T = eq(a_isSupported, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 159:15] when _T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 159:31] connect source_i.bits.opcode, UInt<3>(0h4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 160:32] connect source_i.bits.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 161:32] wire source_c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 165:28] connect source_c.valid, cam_amo_0 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 166:24] node _source_c_bits_T = or(cam_a[0].bits.corrupt, cam_d[0].corrupt) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 172:45] node _source_c_bits_legal_T = leq(UInt<1>(0h0), cam_a[0].bits.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _source_c_bits_legal_T_1 = leq(cam_a[0].bits.size, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _source_c_bits_legal_T_2 = and(_source_c_bits_legal_T, _source_c_bits_legal_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _source_c_bits_legal_T_3 = or(UInt<1>(0h0), _source_c_bits_legal_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _source_c_bits_legal_T_4 = xor(cam_a[0].bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _source_c_bits_legal_T_5 = cvt(_source_c_bits_legal_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _source_c_bits_legal_T_6 = and(_source_c_bits_legal_T_5, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_7 = asSInt(_source_c_bits_legal_T_6) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_8 = eq(_source_c_bits_legal_T_7, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _source_c_bits_legal_T_9 = and(_source_c_bits_legal_T_3, _source_c_bits_legal_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node source_c_bits_legal = or(UInt<1>(0h0), _source_c_bits_legal_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire source_c_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 480:17] connect source_c_bits_a.opcode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 481:15] connect source_c_bits_a.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 482:15] connect source_c_bits_a.size, cam_a[0].bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 483:15] connect source_c_bits_a.source, cam_a[0].bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 484:15] connect source_c_bits_a.address, cam_a[0].bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 485:15] invalidate source_c_bits_a.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate source_c_bits_a.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate source_c_bits_a.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate source_c_bits_a.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate source_c_bits_a.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate source_c_bits_a.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate source_c_bits_a.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] node _source_c_bits_a_mask_sizeOH_T = or(cam_a[0].bits.size, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node source_c_bits_a_mask_sizeOH_shiftAmount = bits(_source_c_bits_a_mask_sizeOH_T, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _source_c_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), source_c_bits_a_mask_sizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _source_c_bits_a_mask_sizeOH_T_2 = bits(_source_c_bits_a_mask_sizeOH_T_1, 2, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node source_c_bits_a_mask_sizeOH = or(_source_c_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] node source_c_bits_a_mask_sub_sub_sub_0_1 = geq(cam_a[0].bits.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 206:21] node source_c_bits_a_mask_sub_sub_size = bits(source_c_bits_a_mask_sizeOH, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node source_c_bits_a_mask_sub_sub_bit = bits(cam_a[0].bits.address, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node source_c_bits_a_mask_sub_sub_nbit = eq(source_c_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node source_c_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_sub_sub_acc_T = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_0_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_sub_sub_0_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_sub_sub_acc_T_1 = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_1_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_sub_sub_1_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_sub_size = bits(source_c_bits_a_mask_sizeOH, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node source_c_bits_a_mask_sub_bit = bits(cam_a[0].bits.address, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node source_c_bits_a_mask_sub_nbit = eq(source_c_bits_a_mask_sub_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node source_c_bits_a_mask_sub_0_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_sub_acc_T = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_0_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_sub_0_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_sub_1_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_sub_acc_T_1 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_1_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_sub_1_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_sub_2_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_sub_acc_T_2 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_2_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_sub_2_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_sub_3_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_sub_acc_T_3 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_3_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_sub_3_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_size = bits(source_c_bits_a_mask_sizeOH, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node source_c_bits_a_mask_bit = bits(cam_a[0].bits.address, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node source_c_bits_a_mask_nbit = eq(source_c_bits_a_mask_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node source_c_bits_a_mask_eq = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_acc_T = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_acc = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_eq_1 = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_acc_T_1 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_acc_1 = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_eq_2 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_acc_T_2 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_acc_2 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_eq_3 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_acc_T_3 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_acc_3 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_eq_4 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_acc_T_4 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_acc_4 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_eq_5 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_acc_T_5 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_acc_5 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_eq_6 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_acc_T_6 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_acc_6 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_eq_7 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_acc_T_7 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_acc_7 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_lo_lo = cat(source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node source_c_bits_a_mask_lo_hi = cat(source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node source_c_bits_a_mask_lo = cat(source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node source_c_bits_a_mask_hi_lo = cat(source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node source_c_bits_a_mask_hi_hi = cat(source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node source_c_bits_a_mask_hi = cat(source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node _source_c_bits_a_mask_T = cat(source_c_bits_a_mask_hi, source_c_bits_a_mask_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] connect source_c_bits_a.mask, _source_c_bits_a_mask_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 488:15] connect source_c_bits_a.data, amo_data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 489:15] connect source_c_bits_a.corrupt, _source_c_bits_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 490:15] connect source_c.bits, source_c_bits_a @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 167:23] connect source_c.bits.user.amba_prot.fetch, cam_a[0].bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 173:28] connect source_c.bits.user.amba_prot.secure, cam_a[0].bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 173:28] connect source_c.bits.user.amba_prot.privileged, cam_a[0].bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 173:28] connect source_c.bits.user.amba_prot.writealloc, cam_a[0].bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 173:28] connect source_c.bits.user.amba_prot.readalloc, cam_a[0].bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 173:28] connect source_c.bits.user.amba_prot.modifiable, cam_a[0].bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 173:28] connect source_c.bits.user.amba_prot.bufferable, cam_a[0].bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 173:28] node _decode_T = dshl(UInt<6>(0h3f), nodeIn.a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _decode_T_1 = bits(_decode_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _decode_T_2 = not(_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node decode = shr(_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node opdata = eq(_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node _T_1 = mux(opdata, decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 60:30] node idle = eq(beatsLeft, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 61:28] node latch = and(idle, nodeOut.a.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 62:24] node _readys_T = cat(source_i.valid, source_c.valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:51] node _readys_T_1 = shl(_readys_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _readys_T_2 = bits(_readys_T_1, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _readys_T_3 = or(_readys_T, _readys_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _readys_T_4 = bits(_readys_T_3, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 255:17] node _readys_T_5 = shl(_readys_T_4, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 16:78] node _readys_T_6 = bits(_readys_T_5, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 16:83] node _readys_T_7 = not(_readys_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 16:61] node _readys_T_8 = bits(_readys_T_7, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] node _readys_T_9 = bits(_readys_T_7, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] wire readys : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[0], _readys_T_8 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[1], _readys_T_9 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] node _winner_T = and(readys[0], source_c.valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] node _winner_T_1 = and(readys[1], source_i.valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] wire winner : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[0], _winner_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[1], _winner_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] node prefixOR_1 = or(UInt<1>(0h0), winner[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node _prefixOR_T = or(prefixOR_1, winner[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node _T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_3 = eq(winner[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_4 = or(_T_2, _T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_5 = eq(prefixOR_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_6 = eq(winner[1], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_7 = or(_T_5, _T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_8 = and(_T_4, _T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:77] node _T_9 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_10 = eq(_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] when _T_10 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_11 = eq(_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] when _T_11 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] assert(clock, _T_8, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_12 = or(source_c.valid, source_i.valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:31] node _T_13 = eq(_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:15] node _T_14 = or(winner[0], winner[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:54] node _T_15 = or(_T_13, _T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:36] node _T_16 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node _T_17 = eq(_T_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] when _T_17 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node _T_18 = eq(_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] when _T_18 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] assert(clock, _T_15, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node maskedBeats_0 = mux(winner[0], UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node maskedBeats_1 = mux(winner[1], _T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node initBeats = or(maskedBeats_0, maskedBeats_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 84:44] node _beatsLeft_T = and(nodeOut.a.ready, nodeOut.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:52] node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:52] node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:23] connect beatsLeft, _beatsLeft_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:17] wire _state_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] regreset state : UInt<1>[2], clock, reset, _state_WIRE @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:26] node muxState = mux(idle, winner, state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 89:25] connect state, muxState @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 90:13] node allowed = mux(idle, readys, state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 92:24] node _source_c_ready_T = and(nodeOut.a.ready, allowed[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect source_c.ready, _source_c_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _source_i_ready_T = and(nodeOut.a.ready, allowed[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect source_i.ready, _source_i_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _nodeOut_a_valid_T = or(source_c.valid, source_i.valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:46] node _nodeOut_a_valid_T_1 = mux(state[0], source_c.valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_valid_T_2 = mux(state[1], source_i.valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_valid_T_3 = or(_nodeOut_a_valid_T_1, _nodeOut_a_valid_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_valid_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_valid_WIRE, _nodeOut_a_valid_T_3 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_valid_T_4 = mux(idle, _nodeOut_a_valid_T, _nodeOut_a_valid_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:24] connect nodeOut.a.valid, _nodeOut_a_valid_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:18] wire _nodeOut_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T = mux(muxState[0], source_c.bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_1 = mux(muxState[1], source_i.bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_2 = or(_nodeOut_a_bits_T, _nodeOut_a_bits_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_1 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_1, _nodeOut_a_bits_T_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.corrupt, _nodeOut_a_bits_WIRE_1 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_3 = mux(muxState[0], source_c.bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_4 = mux(muxState[1], source_i.bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_5 = or(_nodeOut_a_bits_T_3, _nodeOut_a_bits_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_2 : UInt<64> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_2, _nodeOut_a_bits_T_5 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.data, _nodeOut_a_bits_WIRE_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_6 = mux(muxState[0], source_c.bits.mask, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_7 = mux(muxState[1], source_i.bits.mask, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_8 = or(_nodeOut_a_bits_T_6, _nodeOut_a_bits_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_3 : UInt<8> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_3, _nodeOut_a_bits_T_8 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.mask, _nodeOut_a_bits_WIRE_3 @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_4 : { } @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.echo, _nodeOut_a_bits_WIRE_4 @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_5 : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}} @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_6 : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>} @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_9 = mux(muxState[0], source_c.bits.user.amba_prot.fetch, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_10 = mux(muxState[1], source_i.bits.user.amba_prot.fetch, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_11 = or(_nodeOut_a_bits_T_9, _nodeOut_a_bits_T_10) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_7 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_7, _nodeOut_a_bits_T_11 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_6.fetch, _nodeOut_a_bits_WIRE_7 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_12 = mux(muxState[0], source_c.bits.user.amba_prot.secure, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_13 = mux(muxState[1], source_i.bits.user.amba_prot.secure, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_14 = or(_nodeOut_a_bits_T_12, _nodeOut_a_bits_T_13) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_8 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_8, _nodeOut_a_bits_T_14 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_6.secure, _nodeOut_a_bits_WIRE_8 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_15 = mux(muxState[0], source_c.bits.user.amba_prot.privileged, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_16 = mux(muxState[1], source_i.bits.user.amba_prot.privileged, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_17 = or(_nodeOut_a_bits_T_15, _nodeOut_a_bits_T_16) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_9 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_9, _nodeOut_a_bits_T_17 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_6.privileged, _nodeOut_a_bits_WIRE_9 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_18 = mux(muxState[0], source_c.bits.user.amba_prot.writealloc, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_19 = mux(muxState[1], source_i.bits.user.amba_prot.writealloc, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_20 = or(_nodeOut_a_bits_T_18, _nodeOut_a_bits_T_19) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_10 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_10, _nodeOut_a_bits_T_20 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_6.writealloc, _nodeOut_a_bits_WIRE_10 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_21 = mux(muxState[0], source_c.bits.user.amba_prot.readalloc, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_22 = mux(muxState[1], source_i.bits.user.amba_prot.readalloc, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_23 = or(_nodeOut_a_bits_T_21, _nodeOut_a_bits_T_22) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_11 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_11, _nodeOut_a_bits_T_23 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_6.readalloc, _nodeOut_a_bits_WIRE_11 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_24 = mux(muxState[0], source_c.bits.user.amba_prot.modifiable, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_25 = mux(muxState[1], source_i.bits.user.amba_prot.modifiable, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_26 = or(_nodeOut_a_bits_T_24, _nodeOut_a_bits_T_25) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_12 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_12, _nodeOut_a_bits_T_26 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_6.modifiable, _nodeOut_a_bits_WIRE_12 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_27 = mux(muxState[0], source_c.bits.user.amba_prot.bufferable, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_28 = mux(muxState[1], source_i.bits.user.amba_prot.bufferable, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_29 = or(_nodeOut_a_bits_T_27, _nodeOut_a_bits_T_28) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_13 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_13, _nodeOut_a_bits_T_29 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_6.bufferable, _nodeOut_a_bits_WIRE_13 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_5.amba_prot, _nodeOut_a_bits_WIRE_6 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.user, _nodeOut_a_bits_WIRE_5 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_30 = mux(muxState[0], source_c.bits.address, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_31 = mux(muxState[1], source_i.bits.address, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_32 = or(_nodeOut_a_bits_T_30, _nodeOut_a_bits_T_31) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_14 : UInt<29> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_14, _nodeOut_a_bits_T_32 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.address, _nodeOut_a_bits_WIRE_14 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_33 = mux(muxState[0], source_c.bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_34 = mux(muxState[1], source_i.bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_35 = or(_nodeOut_a_bits_T_33, _nodeOut_a_bits_T_34) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_15 : UInt<2> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_15, _nodeOut_a_bits_T_35 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.source, _nodeOut_a_bits_WIRE_15 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_36 = mux(muxState[0], source_c.bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_37 = mux(muxState[1], source_i.bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_38 = or(_nodeOut_a_bits_T_36, _nodeOut_a_bits_T_37) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_16 : UInt<3> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_16, _nodeOut_a_bits_T_38 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.size, _nodeOut_a_bits_WIRE_16 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_39 = mux(muxState[0], source_c.bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_40 = mux(muxState[1], source_i.bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_41 = or(_nodeOut_a_bits_T_39, _nodeOut_a_bits_T_40) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_17 : UInt<3> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_17, _nodeOut_a_bits_T_41 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.param, _nodeOut_a_bits_WIRE_17 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_42 = mux(muxState[0], source_c.bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_43 = mux(muxState[1], source_i.bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_44 = or(_nodeOut_a_bits_T_42, _nodeOut_a_bits_T_43) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_18 : UInt<3> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_18, _nodeOut_a_bits_T_44 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.opcode, _nodeOut_a_bits_WIRE_18 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect nodeOut.a.bits.corrupt, _nodeOut_a_bits_WIRE.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.data, _nodeOut_a_bits_WIRE.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.mask, _nodeOut_a_bits_WIRE.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.user.amba_prot.fetch, _nodeOut_a_bits_WIRE.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.user.amba_prot.secure, _nodeOut_a_bits_WIRE.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.user.amba_prot.privileged, _nodeOut_a_bits_WIRE.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.user.amba_prot.writealloc, _nodeOut_a_bits_WIRE.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.user.amba_prot.readalloc, _nodeOut_a_bits_WIRE.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.user.amba_prot.modifiable, _nodeOut_a_bits_WIRE.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.user.amba_prot.bufferable, _nodeOut_a_bits_WIRE.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.address, _nodeOut_a_bits_WIRE.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.source, _nodeOut_a_bits_WIRE.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.size, _nodeOut_a_bits_WIRE.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.param, _nodeOut_a_bits_WIRE.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.opcode, _nodeOut_a_bits_WIRE.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] node _T_19 = and(source_i.ready, source_i.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_20 = eq(a_isSupported, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 180:32] node _T_21 = and(_T_19, _T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 180:29] when _T_21 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 180:48] when a_cam_sel_free_0 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 182:23] connect cam_a[0].fifoId, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 183:24] connect cam_a[0].bits.corrupt, nodeIn.a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 184:24] connect cam_a[0].bits.data, nodeIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 184:24] connect cam_a[0].bits.mask, nodeIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 184:24] connect cam_a[0].bits.user, nodeIn.a.bits.user @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 184:24] connect cam_a[0].bits.address, nodeIn.a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 184:24] connect cam_a[0].bits.source, nodeIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 184:24] connect cam_a[0].bits.size, nodeIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 184:24] connect cam_a[0].bits.param, nodeIn.a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 184:24] connect cam_a[0].bits.opcode, nodeIn.a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 184:24] node _cam_a_0_lut_T = bits(nodeIn.a.bits.param, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 185:52] node _cam_a_0_lut_T_1 = eq(UInt<3>(0h1), _cam_a_0_lut_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 185:69] node _cam_a_0_lut_T_2 = mux(_cam_a_0_lut_T_1, UInt<4>(0he), UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 185:69] node _cam_a_0_lut_T_3 = eq(UInt<3>(0h0), _cam_a_0_lut_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 185:69] node _cam_a_0_lut_T_4 = mux(_cam_a_0_lut_T_3, UInt<3>(0h6), _cam_a_0_lut_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 185:69] node _cam_a_0_lut_T_5 = eq(UInt<3>(0h3), _cam_a_0_lut_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 185:69] node _cam_a_0_lut_T_6 = mux(_cam_a_0_lut_T_5, UInt<4>(0hc), _cam_a_0_lut_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 185:69] connect cam_a[0].lut, _cam_a_0_lut_T_6 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 185:24] when a_cam_sel_free_0 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 193:23] connect cam_s[0].state, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 194:23] node _T_22 = and(source_c.ready, source_c.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_22 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 200:30] when a_cam_sel_put_0 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 202:23] connect cam_s[0].state, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 203:23] node _d_first_T = and(nodeOut.d.ready, nodeOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), nodeOut.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node d_first_beats1_opdata = bits(nodeOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node d_first_counter1 = tail(_d_first_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node d_first = eq(d_first_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node d_first_last = or(_d_first_last_T, _d_first_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node d_first_done = and(d_first_last, _d_first_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _d_first_count_T = not(d_first_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node d_first_count = and(d_first_beats1, _d_first_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _d_first_T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect d_first_counter, _d_first_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node d_cam_sel_raw_0 = eq(cam_a[0].bits.source, nodeIn.d.bits.source) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 210:53] node d_cam_sel_match_0 = and(d_cam_sel_raw_0, cam_dmatch_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 211:83] node d_cam_sel_0 = mux(UInt<1>(0h0), a_cam_sel_free_0, d_cam_sel_match_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 217:85] node d_cam_sel_any = or(UInt<1>(0h0), d_cam_sel_match_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 218:46] node d_ackd = eq(nodeOut.d.bits.opcode, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 219:40] node d_ack = eq(nodeOut.d.bits.opcode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 220:40] node _T_23 = and(nodeOut.d.ready, nodeOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_24 = and(_T_23, d_first) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 222:26] when _T_24 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 222:38] node _T_25 = and(d_cam_sel_0, d_ackd) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 224:22] when _T_25 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 224:33] connect cam_d[0].data, nodeOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 225:22] connect cam_d[0].denied, nodeOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 226:24] connect cam_d[0].corrupt, nodeOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 227:25] when d_cam_sel_0 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 231:23] node _cam_s_0_state_T = mux(d_ackd, UInt<2>(0h2), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 233:29] connect cam_s[0].state, _cam_s_0_state_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 233:23] node _d_drop_T = and(d_first, d_ackd) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 238:30] node d_drop = and(_d_drop_T, d_cam_sel_any) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 238:40] node _d_replace_T = and(d_first, d_ack) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 239:33] node d_replace = and(_d_replace_T, d_cam_sel_match_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 239:42] node _nodeIn_d_valid_T = eq(d_drop, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 241:38] node _nodeIn_d_valid_T_1 = and(nodeOut.d.valid, _nodeIn_d_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 241:35] connect nodeIn.d.valid, _nodeIn_d_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 241:20] node _nodeOut_d_ready_T = or(nodeIn.d.ready, d_drop) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 242:35] connect nodeOut.d.ready, _nodeOut_d_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 242:21] connect nodeIn.d.bits.corrupt, nodeOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 244:19] connect nodeIn.d.bits.data, nodeOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 244:19] connect nodeIn.d.bits.denied, nodeOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 244:19] connect nodeIn.d.bits.sink, nodeOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 244:19] connect nodeIn.d.bits.source, nodeOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 244:19] connect nodeIn.d.bits.size, nodeOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 244:19] connect nodeIn.d.bits.param, nodeOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 244:19] connect nodeIn.d.bits.opcode, nodeOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 244:19] when d_replace : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 245:26] connect nodeIn.d.bits.opcode, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 246:28] connect nodeIn.d.bits.data, cam_d[0].data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 247:26] node _nodeIn_d_bits_corrupt_T = or(cam_d[0].corrupt, nodeOut.d.bits.denied) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 248:46] connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_corrupt_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 248:29] node _nodeIn_d_bits_denied_T = or(cam_d[0].denied, nodeOut.d.bits.denied) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 249:46] connect nodeIn.d.bits.denied, _nodeIn_d_bits_denied_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 249:29] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 274:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 275:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 276:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 277:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 278:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 279:21] module Queue2_TLBundleA_a29d64s2k1z3u_1 : @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input clock : Clock @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input reset : Reset @[src/main/scala/chisel3/util/Decoupled.scala 243:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, count : UInt<2>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} [2] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] regreset enq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset deq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] infer mport MPORT = ram[enq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 270:24] node wrap = eq(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T = add(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_1 = tail(_value_T, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect enq_ptr_value, _value_T_1 @[src/main/scala/chisel3/util/Counter.scala 77:15] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] node wrap_1 = eq(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_3 = tail(_value_T_2, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect deq_ptr_value, _value_T_3 @[src/main/scala/chisel3/util/Counter.scala 77:15] node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] infer mport io_deq_bits_MPORT = ram[deq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module Queue2_TLBundleD_a29d64s2k1z3u_1 : @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input clock : Clock @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input reset : Reset @[src/main/scala/chisel3/util/Decoupled.scala 243:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, count : UInt<2>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} [2] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] regreset enq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset deq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] infer mport MPORT = ram[enq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 270:24] node wrap = eq(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T = add(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_1 = tail(_value_T, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect enq_ptr_value, _value_T_1 @[src/main/scala/chisel3/util/Counter.scala 77:15] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] node wrap_1 = eq(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_3 = tail(_value_T_2, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect deq_ptr_value, _value_T_3 @[src/main/scala/chisel3/util/Counter.scala 77:15] node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] infer mport io_deq_bits_MPORT = ram[deq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module TLBuffer_a29d64s2k1z3u_1 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] inst nodeOut_a_q of Queue2_TLBundleA_a29d64s2k1z3u_1 @[src/main/scala/chisel3/util/Decoupled.scala 362:21] connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid @[src/main/scala/chisel3/util/Decoupled.scala 364:22] connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.fetch, nodeIn.a.bits.user.amba_prot.fetch @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.secure, nodeIn.a.bits.user.amba_prot.secure @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.privileged, nodeIn.a.bits.user.amba_prot.privileged @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.writealloc, nodeIn.a.bits.user.amba_prot.writealloc @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.readalloc, nodeIn.a.bits.user.amba_prot.readalloc @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.modifiable, nodeIn.a.bits.user.amba_prot.modifiable @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.bufferable, nodeIn.a.bits.user.amba_prot.bufferable @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready @[src/main/scala/chisel3/util/Decoupled.scala 366:17] connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] inst nodeIn_d_q of Queue2_TLBundleD_a29d64s2k1z3u_1 @[src/main/scala/chisel3/util/Decoupled.scala 362:21] connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid @[src/main/scala/chisel3/util/Decoupled.scala 364:22] connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready @[src/main/scala/chisel3/util/Decoupled.scala 366:17] connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 52:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 53:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 54:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 55:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 56:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 57:21] module Repeater_TLBundleA_a29d64s2k1z3u : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 13:14] regreset full : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 20:21] reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 21:18] node _io_deq_valid_T = or(io.enq.valid, full) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:32] connect io.deq.valid, _io_deq_valid_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:35] node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:32] connect io.enq.ready, _io_enq_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:16] node _io_deq_bits_T = mux(full, saved, io.enq.bits) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:21] connect io.deq.bits, _io_deq_bits_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:15] connect io.full, full @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 27:11] node _T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_1 = and(_T, io.repeat) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:21] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:36] connect full, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:43] connect saved, io.enq.bits @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] node _T_2 = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_3 = eq(io.repeat, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:24] node _T_4 = and(_T_2, _T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:21] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:36] connect full, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:43] module TLFragmenter_FPGAUART : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 201:29] reg dOrig : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 202:24] regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 203:30] node dFragnum = bits(anonOut.d.bits.source, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 204:41] node dFirst = eq(acknum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 205:29] node dLast = eq(dFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 206:30] node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node dsizeOH = bits(_dsizeOH_T, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node dsizeOH1 = not(_dsizeOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node dHasData = bits(anonOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node acknum_fragment = shl(dFragnum, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 212:40] node acknum_size = shr(dsizeOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 213:36] node _T = eq(anonOut.d.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:17] node _T_1 = and(acknum_fragment, acknum_size) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:50] node _T_2 = eq(_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:65] node _T_3 = or(_T, _T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:30] node _T_4 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _T_5 = eq(_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _T_6 = eq(_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] when _T_6 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] assert(clock, _T_3, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 215:50] node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 215:45] node _ack_decrement_T = shr(dsizeOH, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 216:56] node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 216:32] node _dFirst_size_T = shl(dFragnum, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 218:47] node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 218:69] node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:35] node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:40] node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:53] node _dFirst_size_T_5 = not(_dFirst_size_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:49] node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:47] node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _dFirst_size_T_7 = orr(dFirst_size_hi) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _dFirst_size_T_9 = orr(dFirst_size_hi_1) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) @[src/main/scala/chisel3/util/CircuitMath.scala 28:8] node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node _T_7 = and(anonOut.d.ready, anonOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_7 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 220:27] node _acknum_T = sub(acknum, ack_decrement) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:55] node _acknum_T_1 = tail(_acknum_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:55] node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:24] connect acknum, _acknum_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:18] when dFirst : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 222:25] connect dOrig, dFirst_size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 223:19] node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 224:41] connect dToggle, _dToggle_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 224:21] node _drop_T = eq(dHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:20] node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:37] node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:33] node drop = and(_drop_T, _drop_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:30] node _anonOut_d_ready_T = or(anonIn.d.ready, drop) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 235:35] connect anonOut.d.ready, _anonOut_d_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 235:21] node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:39] node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:36] connect anonIn.d.valid, _anonIn_d_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:21] connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 238:47] connect anonIn.d.bits.source, _anonIn_d_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 238:26] node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 239:32] connect anonIn.d.bits.size, _anonIn_d_bits_size_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 239:26] inst repeater of Repeater_TLBundleA_a29d64s2k1z3u @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 274:30] connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 275:25] node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_1 = cvt(_find_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_3 = asSInt(_find_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] wire find : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[0], _find_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _aFrag_T = gt(repeater.io.deq.bits.size, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 297:31] node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 297:24] node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node aOrigOH1 = not(_aOrigOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node aFragOH1 = not(_aFragOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 301:24] regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 303:29] node aFirst = eq(gennum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 304:29] node _old_gennum1_T = shr(aOrigOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:48] node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:79] node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:79] node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:30] node _new_gennum_T = not(old_gennum1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:28] node _new_gennum_T_1 = shr(aMask, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:50] node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:41] node new_gennum = not(_new_gennum_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:26] node _aFragnum_T = shr(old_gennum1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:40] node _aFragnum_T_1 = not(_aFragnum_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:26] node _aFragnum_T_2 = shr(aFragOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:84] node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:72] node aFragnum = not(_aFragnum_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:24] node aLast = eq(aFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 308:30] reg aToggle_r : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] when aFirst : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] connect aToggle_r, dToggle @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] node _aToggle_T = mux(aFirst, dToggle, aToggle_r) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:27] node aToggle = eq(_aToggle_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:23] node _T_8 = and(anonOut.a.ready, anonOut.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 312:27] connect gennum, new_gennum @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 312:36] node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:31] node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:53] node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:41] connect repeater.io.repeat, _repeater_io_repeat_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:28] connect anonOut.a.bits, repeater.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] connect anonOut.a.valid, repeater.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] connect repeater.io.deq.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] node _anonOut_a_bits_address_T = shl(old_gennum1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:65] node _anonOut_a_bits_address_T_1 = not(aOrigOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:90] node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:88] node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:100] node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:111] node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:51] node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:49] connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:28] node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] connect anonOut.a.bits.source, _anonOut_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:27] connect anonOut.a.bits.size, aFrag @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 318:25] node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:17] node _T_10 = eq(aHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:38] node _T_11 = or(_T_9, _T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:35] node _T_12 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] node _T_13 = eq(_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] when _T_13 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] node _T_14 = eq(_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] when _T_14 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] connect anonOut.a.bits.data, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 322:25] node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:17] node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:53] node _T_17 = or(_T_15, _T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:35] node _T_18 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _T_19 = eq(_T_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] when _T_19 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _T_20 = eq(_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] when _T_20 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 325:31] connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 325:25] wire anonOut_a_bits_user_out : { } @[hardware/upstream/rocket-chip/src/main/scala/util/BundleMap.scala 114:19] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 329:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 330:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 331:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 332:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 333:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 334:21] module TLInterconnectCoupler_pbus_to_fpga_uart : @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input clock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input reset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] inst fragmenter of TLFragmenter_FPGAUART @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 345:34] connect fragmenter.clock, clock connect fragmenter.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate tlOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tlIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect tlOut, tlIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect fragmenter.auto.anon_in, tlOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect tlIn, auto.tl_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] module Repeater_TLBundleA_a29d64s2k1z3u_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 13:14] regreset full : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 20:21] reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 21:18] node _io_deq_valid_T = or(io.enq.valid, full) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:32] connect io.deq.valid, _io_deq_valid_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:35] node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:32] connect io.enq.ready, _io_enq_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:16] node _io_deq_bits_T = mux(full, saved, io.enq.bits) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:21] connect io.deq.bits, _io_deq_bits_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:15] connect io.full, full @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 27:11] node _T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_1 = and(_T, io.repeat) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:21] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:36] connect full, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:43] connect saved, io.enq.bits @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] node _T_2 = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_3 = eq(io.repeat, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:24] node _T_4 = and(_T_2, _T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:21] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:36] connect full, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:43] module TLFragmenter_FPGASPI : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 201:29] reg dOrig : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 202:24] regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 203:30] node dFragnum = bits(anonOut.d.bits.source, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 204:41] node dFirst = eq(acknum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 205:29] node dLast = eq(dFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 206:30] node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node dsizeOH = bits(_dsizeOH_T, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node dsizeOH1 = not(_dsizeOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node dHasData = bits(anonOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node acknum_fragment = shl(dFragnum, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 212:40] node acknum_size = shr(dsizeOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 213:36] node _T = eq(anonOut.d.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:17] node _T_1 = and(acknum_fragment, acknum_size) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:50] node _T_2 = eq(_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:65] node _T_3 = or(_T, _T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:30] node _T_4 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _T_5 = eq(_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _T_6 = eq(_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] when _T_6 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] assert(clock, _T_3, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 215:50] node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 215:45] node _ack_decrement_T = shr(dsizeOH, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 216:56] node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 216:32] node _dFirst_size_T = shl(dFragnum, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 218:47] node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 218:69] node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:35] node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:40] node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:53] node _dFirst_size_T_5 = not(_dFirst_size_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:49] node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:47] node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _dFirst_size_T_7 = orr(dFirst_size_hi) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _dFirst_size_T_9 = orr(dFirst_size_hi_1) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) @[src/main/scala/chisel3/util/CircuitMath.scala 28:8] node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node _T_7 = and(anonOut.d.ready, anonOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_7 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 220:27] node _acknum_T = sub(acknum, ack_decrement) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:55] node _acknum_T_1 = tail(_acknum_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:55] node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:24] connect acknum, _acknum_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:18] when dFirst : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 222:25] connect dOrig, dFirst_size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 223:19] node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 224:41] connect dToggle, _dToggle_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 224:21] node _drop_T = eq(dHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:20] node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:37] node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:33] node drop = and(_drop_T, _drop_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:30] node _anonOut_d_ready_T = or(anonIn.d.ready, drop) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 235:35] connect anonOut.d.ready, _anonOut_d_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 235:21] node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:39] node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:36] connect anonIn.d.valid, _anonIn_d_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:21] connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 238:47] connect anonIn.d.bits.source, _anonIn_d_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 238:26] node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 239:32] connect anonIn.d.bits.size, _anonIn_d_bits_size_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 239:26] inst repeater of Repeater_TLBundleA_a29d64s2k1z3u_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 274:30] connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 275:25] node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_1 = cvt(_find_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_3 = asSInt(_find_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] wire find : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[0], _find_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _aFrag_T = gt(repeater.io.deq.bits.size, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 297:31] node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 297:24] node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node aOrigOH1 = not(_aOrigOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node aFragOH1 = not(_aFragOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 301:24] regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 303:29] node aFirst = eq(gennum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 304:29] node _old_gennum1_T = shr(aOrigOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:48] node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:79] node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:79] node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:30] node _new_gennum_T = not(old_gennum1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:28] node _new_gennum_T_1 = shr(aMask, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:50] node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:41] node new_gennum = not(_new_gennum_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:26] node _aFragnum_T = shr(old_gennum1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:40] node _aFragnum_T_1 = not(_aFragnum_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:26] node _aFragnum_T_2 = shr(aFragOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:84] node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:72] node aFragnum = not(_aFragnum_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:24] node aLast = eq(aFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 308:30] reg aToggle_r : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] when aFirst : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] connect aToggle_r, dToggle @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] node _aToggle_T = mux(aFirst, dToggle, aToggle_r) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:27] node aToggle = eq(_aToggle_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:23] node _T_8 = and(anonOut.a.ready, anonOut.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 312:27] connect gennum, new_gennum @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 312:36] node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:31] node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:53] node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:41] connect repeater.io.repeat, _repeater_io_repeat_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:28] connect anonOut.a.bits, repeater.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] connect anonOut.a.valid, repeater.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] connect repeater.io.deq.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] node _anonOut_a_bits_address_T = shl(old_gennum1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:65] node _anonOut_a_bits_address_T_1 = not(aOrigOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:90] node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:88] node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:100] node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:111] node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:51] node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:49] connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:28] node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] connect anonOut.a.bits.source, _anonOut_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:27] connect anonOut.a.bits.size, aFrag @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 318:25] node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:17] node _T_10 = eq(aHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:38] node _T_11 = or(_T_9, _T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:35] node _T_12 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] node _T_13 = eq(_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] when _T_13 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] node _T_14 = eq(_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] when _T_14 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] connect anonOut.a.bits.data, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 322:25] node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:17] node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:53] node _T_17 = or(_T_15, _T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:35] node _T_18 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _T_19 = eq(_T_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] when _T_19 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _T_20 = eq(_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] when _T_20 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 325:31] connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 325:25] wire anonOut_a_bits_user_out : { } @[hardware/upstream/rocket-chip/src/main/scala/util/BundleMap.scala 114:19] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 329:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 330:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 331:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 332:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 333:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 334:21] module TLInterconnectCoupler_pbus_to_fpga_spi : @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input clock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input reset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] inst fragmenter of TLFragmenter_FPGASPI @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 345:34] connect fragmenter.clock, clock connect fragmenter.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate tlOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tlIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect tlOut, tlIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect fragmenter.auto.anon_in, tlOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect tlIn, auto.tl_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] module Repeater_TLBundleA_a29d64s2k1z3u_2 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 13:14] regreset full : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 20:21] reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 21:18] node _io_deq_valid_T = or(io.enq.valid, full) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:32] connect io.deq.valid, _io_deq_valid_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:35] node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:32] connect io.enq.ready, _io_enq_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:16] node _io_deq_bits_T = mux(full, saved, io.enq.bits) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:21] connect io.deq.bits, _io_deq_bits_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:15] connect io.full, full @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 27:11] node _T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_1 = and(_T, io.repeat) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:21] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:36] connect full, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:43] connect saved, io.enq.bits @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] node _T_2 = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_3 = eq(io.repeat, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:24] node _T_4 = and(_T_2, _T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:21] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:36] connect full, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:43] module TLFragmenter_FPGAPMODSPI : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 201:29] reg dOrig : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 202:24] regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 203:30] node dFragnum = bits(anonOut.d.bits.source, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 204:41] node dFirst = eq(acknum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 205:29] node dLast = eq(dFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 206:30] node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node dsizeOH = bits(_dsizeOH_T, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node dsizeOH1 = not(_dsizeOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node dHasData = bits(anonOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node acknum_fragment = shl(dFragnum, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 212:40] node acknum_size = shr(dsizeOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 213:36] node _T = eq(anonOut.d.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:17] node _T_1 = and(acknum_fragment, acknum_size) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:50] node _T_2 = eq(_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:65] node _T_3 = or(_T, _T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:30] node _T_4 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _T_5 = eq(_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _T_6 = eq(_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] when _T_6 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] assert(clock, _T_3, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 215:50] node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 215:45] node _ack_decrement_T = shr(dsizeOH, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 216:56] node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 216:32] node _dFirst_size_T = shl(dFragnum, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 218:47] node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 218:69] node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:35] node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:40] node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:53] node _dFirst_size_T_5 = not(_dFirst_size_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:49] node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:47] node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _dFirst_size_T_7 = orr(dFirst_size_hi) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _dFirst_size_T_9 = orr(dFirst_size_hi_1) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) @[src/main/scala/chisel3/util/CircuitMath.scala 28:8] node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node _T_7 = and(anonOut.d.ready, anonOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_7 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 220:27] node _acknum_T = sub(acknum, ack_decrement) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:55] node _acknum_T_1 = tail(_acknum_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:55] node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:24] connect acknum, _acknum_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:18] when dFirst : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 222:25] connect dOrig, dFirst_size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 223:19] node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 224:41] connect dToggle, _dToggle_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 224:21] node _drop_T = eq(dHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:20] node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:37] node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:33] node drop = and(_drop_T, _drop_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:30] node _anonOut_d_ready_T = or(anonIn.d.ready, drop) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 235:35] connect anonOut.d.ready, _anonOut_d_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 235:21] node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:39] node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:36] connect anonIn.d.valid, _anonIn_d_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:21] connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 238:47] connect anonIn.d.bits.source, _anonIn_d_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 238:26] node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 239:32] connect anonIn.d.bits.size, _anonIn_d_bits_size_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 239:26] inst repeater of Repeater_TLBundleA_a29d64s2k1z3u_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 274:30] connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 275:25] node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_1 = cvt(_find_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_3 = asSInt(_find_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] wire find : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[0], _find_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _aFrag_T = gt(repeater.io.deq.bits.size, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 297:31] node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 297:24] node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node aOrigOH1 = not(_aOrigOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node aFragOH1 = not(_aFragOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 301:24] regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 303:29] node aFirst = eq(gennum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 304:29] node _old_gennum1_T = shr(aOrigOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:48] node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:79] node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:79] node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:30] node _new_gennum_T = not(old_gennum1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:28] node _new_gennum_T_1 = shr(aMask, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:50] node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:41] node new_gennum = not(_new_gennum_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:26] node _aFragnum_T = shr(old_gennum1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:40] node _aFragnum_T_1 = not(_aFragnum_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:26] node _aFragnum_T_2 = shr(aFragOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:84] node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:72] node aFragnum = not(_aFragnum_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:24] node aLast = eq(aFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 308:30] reg aToggle_r : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] when aFirst : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] connect aToggle_r, dToggle @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] node _aToggle_T = mux(aFirst, dToggle, aToggle_r) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:27] node aToggle = eq(_aToggle_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:23] node _T_8 = and(anonOut.a.ready, anonOut.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 312:27] connect gennum, new_gennum @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 312:36] node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:31] node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:53] node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:41] connect repeater.io.repeat, _repeater_io_repeat_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:28] connect anonOut.a.bits, repeater.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] connect anonOut.a.valid, repeater.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] connect repeater.io.deq.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] node _anonOut_a_bits_address_T = shl(old_gennum1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:65] node _anonOut_a_bits_address_T_1 = not(aOrigOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:90] node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:88] node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:100] node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:111] node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:51] node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:49] connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:28] node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] connect anonOut.a.bits.source, _anonOut_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:27] connect anonOut.a.bits.size, aFrag @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 318:25] node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:17] node _T_10 = eq(aHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:38] node _T_11 = or(_T_9, _T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:35] node _T_12 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] node _T_13 = eq(_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] when _T_13 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] node _T_14 = eq(_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] when _T_14 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] connect anonOut.a.bits.data, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 322:25] node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:17] node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:53] node _T_17 = or(_T_15, _T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:35] node _T_18 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _T_19 = eq(_T_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] when _T_19 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _T_20 = eq(_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] when _T_20 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 325:31] connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 325:25] wire anonOut_a_bits_user_out : { } @[hardware/upstream/rocket-chip/src/main/scala/util/BundleMap.scala 114:19] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 329:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 330:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 331:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 332:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 333:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 334:21] module TLInterconnectCoupler_pbus_to_fpga_pmod_spi : @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input clock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input reset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] inst fragmenter of TLFragmenter_FPGAPMODSPI @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 345:34] connect fragmenter.clock, clock connect fragmenter.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate tlOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tlIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect tlOut, tlIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect fragmenter.auto.anon_in, tlOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect tlIn, auto.tl_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] module Repeater_TLBundleA_a29d32s2k1z3u : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}} @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 13:14] regreset full : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 20:21] reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 21:18] node _io_deq_valid_T = or(io.enq.valid, full) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:32] connect io.deq.valid, _io_deq_valid_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:35] node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:32] connect io.enq.ready, _io_enq_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:16] node _io_deq_bits_T = mux(full, saved, io.enq.bits) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:21] connect io.deq.bits, _io_deq_bits_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:15] connect io.full, full @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 27:11] node _T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_1 = and(_T, io.repeat) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:21] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:36] connect full, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:43] connect saved.corrupt, io.enq.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] connect saved.data, io.enq.bits.data @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] connect saved.mask, io.enq.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] connect saved.user, io.enq.bits.user @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] connect saved.address, io.enq.bits.address @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] connect saved.source, io.enq.bits.source @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] connect saved.size, io.enq.bits.size @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] connect saved.param, io.enq.bits.param @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] connect saved.opcode, io.enq.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] node _T_2 = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_3 = eq(io.repeat, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:24] node _T_4 = and(_T_2, _T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:21] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:36] connect full, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:43] module TLFragmenter_FPGAGPS : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] regreset acknum : UInt<4>, clock, reset, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 201:29] reg dOrig : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 202:24] regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 203:30] node dFragnum = bits(anonOut.d.bits.source, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 204:41] node dFirst = eq(acknum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 205:29] node dLast = eq(dFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 206:30] node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node dsizeOH = bits(_dsizeOH_T, 2, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node _dsizeOH1_T = dshl(UInt<2>(0h3), anonOut.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node dsizeOH1 = not(_dsizeOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node dHasData = bits(anonOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node acknum_fragment = shl(dFragnum, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 212:40] node acknum_size = shr(dsizeOH1, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 213:36] node _T = eq(anonOut.d.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:17] node _T_1 = and(acknum_fragment, acknum_size) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:50] node _T_2 = eq(_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:65] node _T_3 = or(_T, _T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:30] node _T_4 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _T_5 = eq(_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _T_6 = eq(_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] when _T_6 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] assert(clock, _T_3, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 215:50] node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 215:45] node _ack_decrement_T = shr(dsizeOH, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 216:56] node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 216:32] node _dFirst_size_T = shl(dFragnum, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 218:47] node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 218:69] node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:35] node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:40] node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:53] node _dFirst_size_T_5 = not(_dFirst_size_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:49] node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:47] node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _dFirst_size_T_7 = orr(dFirst_size_hi) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _dFirst_size_T_9 = orr(dFirst_size_hi_1) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) @[src/main/scala/chisel3/util/CircuitMath.scala 28:8] node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node _T_7 = and(anonOut.d.ready, anonOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_7 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 220:27] node _acknum_T = sub(acknum, ack_decrement) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:55] node _acknum_T_1 = tail(_acknum_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:55] node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:24] connect acknum, _acknum_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:18] when dFirst : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 222:25] connect dOrig, dFirst_size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 223:19] node _dToggle_T = bits(anonOut.d.bits.source, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 224:41] connect dToggle, _dToggle_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 224:21] node _drop_T = eq(dHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:20] node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:37] node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:33] node drop = and(_drop_T, _drop_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:30] node _anonOut_d_ready_T = or(anonIn.d.ready, drop) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 235:35] connect anonOut.d.ready, _anonOut_d_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 235:21] node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:39] node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:36] connect anonIn.d.valid, _anonIn_d_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:21] connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 238:47] connect anonIn.d.bits.source, _anonIn_d_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 238:26] node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 239:32] connect anonIn.d.bits.size, _anonIn_d_bits_size_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 239:26] reg r_denied : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 242:29] node _d_denied_T = eq(dFirst, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 243:27] node _d_denied_T_1 = and(_d_denied_T, r_denied) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 243:35] node d_denied = or(_d_denied_T_1, anonOut.d.bits.denied) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 243:48] node _T_8 = and(anonOut.d.ready, anonOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 244:29] connect r_denied, d_denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 244:40] connect anonIn.d.bits.denied, d_denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 245:28] inst repeater of Repeater_TLBundleA_a29d32s2k1z3u @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 274:30] connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 275:25] node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_1 = cvt(_find_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_2 = and(_find_T_1, asSInt(UInt<17>(0hf000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_3 = asSInt(_find_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _find_T_5 = xor(repeater.io.deq.bits.address, UInt<13>(0h1000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_6 = cvt(_find_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_7 = and(_find_T_6, asSInt(UInt<17>(0hf000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_8 = asSInt(_find_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_9 = eq(_find_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _find_T_10 = xor(repeater.io.deq.bits.address, UInt<14>(0h2000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_11 = cvt(_find_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_12 = and(_find_T_11, asSInt(UInt<17>(0hf000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_13 = asSInt(_find_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_14 = eq(_find_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _find_T_15 = xor(repeater.io.deq.bits.address, UInt<14>(0h3000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_16 = cvt(_find_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_17 = and(_find_T_16, asSInt(UInt<17>(0hf000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_18 = asSInt(_find_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_19 = eq(_find_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _find_T_20 = xor(repeater.io.deq.bits.address, UInt<15>(0h4000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_21 = cvt(_find_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_22 = and(_find_T_21, asSInt(UInt<17>(0hf000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_23 = asSInt(_find_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_24 = eq(_find_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _find_T_25 = xor(repeater.io.deq.bits.address, UInt<15>(0h5000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_26 = cvt(_find_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_27 = and(_find_T_26, asSInt(UInt<17>(0hf000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_28 = asSInt(_find_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_29 = eq(_find_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _find_T_30 = xor(repeater.io.deq.bits.address, UInt<15>(0h6000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_31 = cvt(_find_T_30) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_32 = and(_find_T_31, asSInt(UInt<17>(0hf000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_33 = asSInt(_find_T_32) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_34 = eq(_find_T_33, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _find_T_35 = xor(repeater.io.deq.bits.address, UInt<15>(0h7000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_36 = cvt(_find_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_37 = and(_find_T_36, asSInt(UInt<17>(0hf000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_38 = asSInt(_find_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_39 = eq(_find_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _find_T_40 = xor(repeater.io.deq.bits.address, UInt<16>(0h8000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_41 = cvt(_find_T_40) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_42 = and(_find_T_41, asSInt(UInt<17>(0hf000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_43 = asSInt(_find_T_42) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_44 = eq(_find_T_43, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _find_T_45 = xor(repeater.io.deq.bits.address, UInt<16>(0h9000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_46 = cvt(_find_T_45) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_47 = and(_find_T_46, asSInt(UInt<17>(0hf000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_48 = asSInt(_find_T_47) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_49 = eq(_find_T_48, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _find_T_50 = xor(repeater.io.deq.bits.address, UInt<16>(0ha000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_51 = cvt(_find_T_50) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_52 = and(_find_T_51, asSInt(UInt<17>(0hf000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_53 = asSInt(_find_T_52) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_54 = eq(_find_T_53, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] wire find : UInt<1>[11] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[0], _find_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[1], _find_T_9 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[2], _find_T_14 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[3], _find_T_19 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[4], _find_T_24 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[5], _find_T_29 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[6], _find_T_34 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[7], _find_T_39 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[8], _find_T_44 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[9], _find_T_49 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[10], _find_T_54 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] node _maxLgArithmetic_T = mux(find[0], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_1 = mux(find[1], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_2 = mux(find[2], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_3 = mux(find[3], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_4 = mux(find[4], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_5 = mux(find[5], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_6 = mux(find[6], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_7 = mux(find[7], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_8 = mux(find[8], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_9 = mux(find[9], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_10 = mux(find[10], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_11 = or(_maxLgArithmetic_T, _maxLgArithmetic_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_12 = or(_maxLgArithmetic_T_11, _maxLgArithmetic_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_13 = or(_maxLgArithmetic_T_12, _maxLgArithmetic_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_14 = or(_maxLgArithmetic_T_13, _maxLgArithmetic_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_15 = or(_maxLgArithmetic_T_14, _maxLgArithmetic_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_16 = or(_maxLgArithmetic_T_15, _maxLgArithmetic_T_6) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_17 = or(_maxLgArithmetic_T_16, _maxLgArithmetic_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_18 = or(_maxLgArithmetic_T_17, _maxLgArithmetic_T_8) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_19 = or(_maxLgArithmetic_T_18, _maxLgArithmetic_T_9) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgArithmetic_T_20 = or(_maxLgArithmetic_T_19, _maxLgArithmetic_T_10) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire maxLgArithmetic : UInt<2> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect maxLgArithmetic, _maxLgArithmetic_T_20 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T = mux(find[0], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_1 = mux(find[1], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_2 = mux(find[2], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_3 = mux(find[3], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_4 = mux(find[4], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_5 = mux(find[5], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_6 = mux(find[6], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_7 = mux(find[7], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_8 = mux(find[8], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_9 = mux(find[9], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_10 = mux(find[10], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_11 = or(_maxLgLogical_T, _maxLgLogical_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_12 = or(_maxLgLogical_T_11, _maxLgLogical_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_13 = or(_maxLgLogical_T_12, _maxLgLogical_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_14 = or(_maxLgLogical_T_13, _maxLgLogical_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_15 = or(_maxLgLogical_T_14, _maxLgLogical_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_16 = or(_maxLgLogical_T_15, _maxLgLogical_T_6) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_17 = or(_maxLgLogical_T_16, _maxLgLogical_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_18 = or(_maxLgLogical_T_17, _maxLgLogical_T_8) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_19 = or(_maxLgLogical_T_18, _maxLgLogical_T_9) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgLogical_T_20 = or(_maxLgLogical_T_19, _maxLgLogical_T_10) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire maxLgLogical : UInt<2> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect maxLgLogical, _maxLgLogical_T_20 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T = mux(find[0], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_1 = mux(find[1], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_2 = mux(find[2], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_3 = mux(find[3], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_4 = mux(find[4], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_5 = mux(find[5], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_6 = mux(find[6], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_7 = mux(find[7], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_8 = mux(find[8], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_9 = mux(find[9], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_10 = mux(find[10], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_11 = or(_maxLgGet_T, _maxLgGet_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_12 = or(_maxLgGet_T_11, _maxLgGet_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_13 = or(_maxLgGet_T_12, _maxLgGet_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_14 = or(_maxLgGet_T_13, _maxLgGet_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_15 = or(_maxLgGet_T_14, _maxLgGet_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_16 = or(_maxLgGet_T_15, _maxLgGet_T_6) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_17 = or(_maxLgGet_T_16, _maxLgGet_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_18 = or(_maxLgGet_T_17, _maxLgGet_T_8) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_19 = or(_maxLgGet_T_18, _maxLgGet_T_9) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgGet_T_20 = or(_maxLgGet_T_19, _maxLgGet_T_10) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire maxLgGet : UInt<2> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect maxLgGet, _maxLgGet_T_20 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T = mux(find[0], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_1 = mux(find[1], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_2 = mux(find[2], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_3 = mux(find[3], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_4 = mux(find[4], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_5 = mux(find[5], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_6 = mux(find[6], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_7 = mux(find[7], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_8 = mux(find[8], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_9 = mux(find[9], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_10 = mux(find[10], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_11 = or(_maxLgPutFull_T, _maxLgPutFull_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_12 = or(_maxLgPutFull_T_11, _maxLgPutFull_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_13 = or(_maxLgPutFull_T_12, _maxLgPutFull_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_14 = or(_maxLgPutFull_T_13, _maxLgPutFull_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_15 = or(_maxLgPutFull_T_14, _maxLgPutFull_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_16 = or(_maxLgPutFull_T_15, _maxLgPutFull_T_6) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_17 = or(_maxLgPutFull_T_16, _maxLgPutFull_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_18 = or(_maxLgPutFull_T_17, _maxLgPutFull_T_8) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_19 = or(_maxLgPutFull_T_18, _maxLgPutFull_T_9) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutFull_T_20 = or(_maxLgPutFull_T_19, _maxLgPutFull_T_10) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire maxLgPutFull : UInt<2> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect maxLgPutFull, _maxLgPutFull_T_20 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T = mux(find[0], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_1 = mux(find[1], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_2 = mux(find[2], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_3 = mux(find[3], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_4 = mux(find[4], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_5 = mux(find[5], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_6 = mux(find[6], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_7 = mux(find[7], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_8 = mux(find[8], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_9 = mux(find[9], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_10 = mux(find[10], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_11 = or(_maxLgPutPartial_T, _maxLgPutPartial_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_12 = or(_maxLgPutPartial_T_11, _maxLgPutPartial_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_13 = or(_maxLgPutPartial_T_12, _maxLgPutPartial_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_14 = or(_maxLgPutPartial_T_13, _maxLgPutPartial_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_15 = or(_maxLgPutPartial_T_14, _maxLgPutPartial_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_16 = or(_maxLgPutPartial_T_15, _maxLgPutPartial_T_6) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_17 = or(_maxLgPutPartial_T_16, _maxLgPutPartial_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_18 = or(_maxLgPutPartial_T_17, _maxLgPutPartial_T_8) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_19 = or(_maxLgPutPartial_T_18, _maxLgPutPartial_T_9) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgPutPartial_T_20 = or(_maxLgPutPartial_T_19, _maxLgPutPartial_T_10) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire maxLgPutPartial : UInt<2> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect maxLgPutPartial, _maxLgPutPartial_T_20 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T = mux(find[0], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_1 = mux(find[1], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_2 = mux(find[2], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_3 = mux(find[3], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_4 = mux(find[4], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_5 = mux(find[5], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_6 = mux(find[6], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_7 = mux(find[7], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_8 = mux(find[8], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_9 = mux(find[9], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_10 = mux(find[10], UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_11 = or(_maxLgHint_T, _maxLgHint_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_12 = or(_maxLgHint_T_11, _maxLgHint_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_13 = or(_maxLgHint_T_12, _maxLgHint_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_14 = or(_maxLgHint_T_13, _maxLgHint_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_15 = or(_maxLgHint_T_14, _maxLgHint_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_16 = or(_maxLgHint_T_15, _maxLgHint_T_6) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_17 = or(_maxLgHint_T_16, _maxLgHint_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_18 = or(_maxLgHint_T_17, _maxLgHint_T_8) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_19 = or(_maxLgHint_T_18, _maxLgHint_T_9) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _maxLgHint_T_20 = or(_maxLgHint_T_19, _maxLgHint_T_10) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire maxLgHint : UInt<2> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect maxLgHint, _maxLgHint_T_20 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_1 = mux(_limit_T, maxLgPutFull, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_3 = mux(_limit_T_2, maxLgPutPartial, _limit_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_5 = mux(_limit_T_4, maxLgArithmetic, _limit_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_7 = mux(_limit_T_6, maxLgLogical, _limit_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_9 = mux(_limit_T_8, maxLgGet, _limit_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node limit = mux(_limit_T_10, maxLgHint, _limit_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _aFrag_T = gt(repeater.io.deq.bits.size, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 297:31] node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 297:24] node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node aOrigOH1 = not(_aOrigOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _aFragOH1_T = dshl(UInt<2>(0h3), aFrag) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _aFragOH1_T_1 = bits(_aFragOH1_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node aFragOH1 = not(_aFragOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 301:24] regreset gennum : UInt<4>, clock, reset, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 303:29] node aFirst = eq(gennum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 304:29] node _old_gennum1_T = shr(aOrigOH1, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:48] node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:79] node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:79] node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:30] node _new_gennum_T = not(old_gennum1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:28] node _new_gennum_T_1 = shr(aMask, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:50] node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:41] node new_gennum = not(_new_gennum_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:26] node _aFragnum_T = shr(old_gennum1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:40] node _aFragnum_T_1 = not(_aFragnum_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:26] node _aFragnum_T_2 = shr(aFragOH1, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:84] node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:72] node aFragnum = not(_aFragnum_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:24] node aLast = eq(aFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 308:30] reg aToggle_r : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] when aFirst : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] connect aToggle_r, dToggle @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] node _aToggle_T = mux(aFirst, dToggle, aToggle_r) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:27] node aToggle = eq(_aToggle_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:23] node _T_9 = and(anonOut.a.ready, anonOut.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_9 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 312:27] connect gennum, new_gennum @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 312:36] node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:31] node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:53] node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:41] connect repeater.io.repeat, _repeater_io_repeat_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:28] connect anonOut.a.bits, repeater.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] connect anonOut.a.valid, repeater.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] connect repeater.io.deq.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] node _anonOut_a_bits_address_T = shl(old_gennum1, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:65] node _anonOut_a_bits_address_T_1 = not(aOrigOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:90] node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:88] node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:100] node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:111] node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:51] node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:49] connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:28] node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] connect anonOut.a.bits.source, _anonOut_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:27] connect anonOut.a.bits.size, aFrag @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 318:25] node _T_10 = eq(repeater.io.full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:17] node _T_11 = eq(aHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:38] node _T_12 = or(_T_10, _T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:35] node _T_13 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] node _T_14 = eq(_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] when _T_14 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] node _T_15 = eq(_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] when _T_15 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] assert(clock, _T_12, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] connect anonOut.a.bits.data, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 322:25] node _T_16 = eq(repeater.io.full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:17] node _T_17 = eq(repeater.io.deq.bits.mask, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:53] node _T_18 = or(_T_16, _T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:35] node _T_19 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _T_20 = eq(_T_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] when _T_20 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _T_21 = eq(_T_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] when _T_21 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] assert(clock, _T_18, UInt<1>(0h1), "") : assert_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<4>(0hf), anonIn.a.bits.mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 325:31] connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 325:25] wire anonOut_a_bits_user_out : { } @[hardware/upstream/rocket-chip/src/main/scala/util/BundleMap.scala 114:19] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 329:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 330:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 331:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, address : UInt<29>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, address : UInt<29>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 332:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 333:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 334:21] module Repeater_TLBundleA_a29d64s2k1z3u_3 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 13:14] regreset full : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 20:21] reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 21:18] node _io_deq_valid_T = or(io.enq.valid, full) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:32] connect io.deq.valid, _io_deq_valid_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:35] node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:32] connect io.enq.ready, _io_enq_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:16] node _io_deq_bits_T = mux(full, saved, io.enq.bits) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:21] connect io.deq.bits, _io_deq_bits_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:15] connect io.full, full @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 27:11] node _T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_1 = and(_T, io.repeat) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:21] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:36] connect full, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:43] connect saved.corrupt, io.enq.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] connect saved.data, io.enq.bits.data @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] connect saved.mask, io.enq.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] connect saved.user, io.enq.bits.user @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] connect saved.address, io.enq.bits.address @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] connect saved.source, io.enq.bits.source @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] connect saved.size, io.enq.bits.size @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] connect saved.param, io.enq.bits.param @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] connect saved.opcode, io.enq.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] node _T_2 = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_3 = eq(io.repeat, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:24] node _T_4 = and(_T_2, _T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:21] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:36] connect full, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:43] module TLWidthWidget8_2 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] wire repeat : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 159:26] inst repeated_repeater of Repeater_TLBundleA_a29d64s2k1z3u_3 @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 36:26] connect repeated_repeater.clock, clock connect repeated_repeater.reset, reset connect repeated_repeater.io.repeat, repeat @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 37:24] connect repeated_repeater.io.enq, anonIn.a @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 38:21] wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 161:25] connect cated.bits, repeated_repeater.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 162:15] connect cated.valid, repeated_repeater.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 162:15] connect repeated_repeater.io.deq.ready, cated.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 162:15] node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 164:37] node _cated_bits_data_T_1 = bits(anonIn.a.bits.data, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 165:31] node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 163:39] connect cated.bits.data, _cated_bits_data_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 163:33] node _repeat_hasData_opdata_T = bits(cated.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node repeat_hasData = eq(_repeat_hasData_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node _repeat_limit_T = dshl(UInt<3>(0h7), cated.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _repeat_limit_T_1 = bits(_repeat_limit_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _repeat_limit_T_2 = not(_repeat_limit_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node repeat_limit = shr(_repeat_limit_T_2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 103:47] regreset repeat_count : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 105:26] node repeat_first = eq(repeat_count, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 106:25] node _repeat_last_T = eq(repeat_count, repeat_limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 107:25] node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 107:38] node repeat_last = or(_repeat_last_T, _repeat_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 107:35] node _repeat_T = and(anonOut.a.ready, anonOut.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _repeat_T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 109:23] node _repeat_count_T = add(repeat_count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 110:24] node _repeat_count_T_1 = tail(_repeat_count_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 110:24] connect repeat_count, _repeat_count_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 110:15] when repeat_last : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 111:21] connect repeat_count, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 111:29] node repeat_sel = bits(cated.bits.address, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 116:39] node repeat_index = or(repeat_sel, repeat_count) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 126:24] connect anonOut.a.bits, cated.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 132:16] connect anonOut.a.valid, cated.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 133:17] connect cated.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 134:16] node _repeat_anonOut_a_bits_data_mux_T = bits(cated.bits.data, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:55] node _repeat_anonOut_a_bits_data_mux_T_1 = bits(cated.bits.data, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:55] wire repeat_anonOut_a_bits_data_mux : UInt<32>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:43] connect repeat_anonOut_a_bits_data_mux[0], _repeat_anonOut_a_bits_data_mux_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:43] connect repeat_anonOut_a_bits_data_mux[1], _repeat_anonOut_a_bits_data_mux_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:43] connect anonOut.a.bits.data, repeat_anonOut_a_bits_data_mux[repeat_index] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 137:30] node _repeat_anonOut_a_bits_mask_mux_T = bits(cated.bits.mask, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:55] node _repeat_anonOut_a_bits_mask_mux_T_1 = bits(cated.bits.mask, 7, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:55] wire repeat_anonOut_a_bits_mask_mux : UInt<4>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:43] connect repeat_anonOut_a_bits_mask_mux[0], _repeat_anonOut_a_bits_mask_mux_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:43] connect repeat_anonOut_a_bits_mask_mux[1], _repeat_anonOut_a_bits_mask_mux_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:43] connect anonOut.a.bits.mask, repeat_anonOut_a_bits_mask_mux[repeat_index] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 140:53] node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 148:7] connect repeat, _repeat_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 166:16] node hasData = bits(anonOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node _limit_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _limit_T_1 = bits(_limit_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _limit_T_2 = not(_limit_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node limit = shr(_limit_T_2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 38:47] regreset count : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 40:27] node first = eq(count, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 41:26] node _last_T = eq(count, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 42:26] node _last_T_1 = eq(hasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 42:39] node last = or(_last_T, _last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 42:36] node _enable_T = xor(count, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:56] node _enable_T_1 = and(_enable_T, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:63] node _enable_T_2 = orr(_enable_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:72] node enable_0 = eq(_enable_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:47] node _enable_T_3 = xor(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:56] node _enable_T_4 = and(_enable_T_3, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:63] node _enable_T_5 = orr(_enable_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:72] node enable_1 = eq(_enable_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:47] regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 45:32] node corrupt_out = or(anonOut.d.bits.corrupt, corrupt_reg) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 47:36] node _T = and(anonOut.d.ready, anonOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 49:22] node _count_T = add(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 50:24] node _count_T_1 = tail(_count_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 50:24] connect count, _count_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 50:15] connect corrupt_reg, corrupt_out @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 51:21] when last : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 52:21] connect count, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 53:17] connect corrupt_reg, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 54:23] node _anonOut_d_ready_T = eq(last, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 76:32] node _anonOut_d_ready_T_1 = or(anonIn.d.ready, _anonOut_d_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 76:29] connect anonOut.d.ready, _anonOut_d_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 76:16] node _anonIn_d_valid_T = and(anonOut.d.valid, last) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 77:29] connect anonIn.d.valid, _anonIn_d_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 77:17] connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 78:16] connect anonIn.d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 78:16] connect anonIn.d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 78:16] connect anonIn.d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 78:16] connect anonIn.d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 78:16] connect anonIn.d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 78:16] connect anonIn.d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 78:16] connect anonIn.d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 78:16] regreset anonIn_d_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 62:41] node _anonIn_d_bits_data_masked_enable_T = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:45] node anonIn_d_bits_data_masked_enable_0 = or(enable_0, _anonIn_d_bits_data_masked_enable_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:42] node _anonIn_d_bits_data_masked_enable_T_1 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:45] node anonIn_d_bits_data_masked_enable_1 = or(enable_1, _anonIn_d_bits_data_masked_enable_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:42] wire anonIn_d_bits_data_odata_0 : UInt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] connect anonIn_d_bits_data_odata_0, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] wire anonIn_d_bits_data_odata_1 : UInt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] connect anonIn_d_bits_data_odata_1, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] reg anonIn_d_bits_data_rdata : UInt<32>[1], clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 66:24] node anonIn_d_bits_data_mdata_0 = mux(anonIn_d_bits_data_masked_enable_0, anonIn_d_bits_data_odata_0, anonIn_d_bits_data_rdata[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 68:88] node anonIn_d_bits_data_mdata_1 = mux(anonIn_d_bits_data_masked_enable_1, anonIn_d_bits_data_odata_1, anonOut.d.bits.data) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 68:88] node _anonIn_d_bits_data_T = and(anonOut.d.ready, anonOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _anonIn_d_bits_data_T_1 = eq(last, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 69:26] node _anonIn_d_bits_data_T_2 = and(_anonIn_d_bits_data_T, _anonIn_d_bits_data_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 69:23] when _anonIn_d_bits_data_T_2 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 69:33] connect anonIn_d_bits_data_rdata_written_once, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 70:30] connect anonIn_d_bits_data_rdata[0], anonIn_d_bits_data_mdata_0 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 71:56] node _anonIn_d_bits_data_T_3 = cat(anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 73:12] connect anonIn.d.bits.data, _anonIn_d_bits_data_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 81:30] connect anonIn.d.bits.corrupt, corrupt_out @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 82:33] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 215:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 216:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 217:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 218:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 219:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 220:21] module TLInterconnectCoupler_pbus_to_gps : @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input clock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input reset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] inst fragmenter of TLFragmenter_FPGAGPS @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 345:34] connect fragmenter.clock, clock connect fragmenter.reset, reset inst widget of TLWidthWidget8_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 230:28] connect widget.clock, clock connect widget.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate tlOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tlIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect tlOut, tlIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect widget.auto.anon_in, tlOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fragmenter.auto.anon_in, widget.auto.anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tlIn, auto.tl_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] module PeripheryBus_pbus : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 14:9] output auto : { coupler_to_gps_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, coupler_to_fpga_pmod_spi_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_fpga_spi_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_fpga_uart_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out_3 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_2 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip pbus_clock_groups_in : { member : { pbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 21:19] output reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 22:19] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] inst pbus_clock_groups of ClockGroupAggregator_pbus @[hardware/upstream/rocket-chip/src/main/scala/tilelink/BusWrapper.scala 52:48] inst clockGroup of ClockGroup_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/BusWrapper.scala 53:38] inst fixedClockNode of FixedClockBroadcast_5 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 115:114] inst broadcast of BundleBridgeNexus_NoOutput_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/package.scala 25:31] inst fixer of TLFIFOFixer_1 @[hardware/upstream/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala 54:33] connect fixer.clock, childClock connect fixer.reset, childReset inst in_xbar of TLXbar_pbus_in_i1_o1_a29d64s2k1z3u @[hardware/upstream/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala 56:29] connect in_xbar.clock, childClock connect in_xbar.reset, childReset inst out_xbar of TLXbar_pbus_out_i1_o4_a29d64s2k1z3u @[hardware/upstream/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala 57:30] connect out_xbar.clock, childClock connect out_xbar.reset, childReset inst buffer of TLBuffer_a29d64s2k1z3u @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 75:28] connect buffer.clock, childClock connect buffer.reset, childReset inst atomics of TLAtomicAutomata_pbus @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 289:29] connect atomics.clock, childClock connect atomics.reset, childReset inst buffer_1 of TLBuffer_a29d64s2k1z3u_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 75:28] connect buffer_1.clock, childClock connect buffer_1.reset, childReset inst coupler_to_fpga_uart of TLInterconnectCoupler_pbus_to_fpga_uart @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyScope.scala 99:27] connect coupler_to_fpga_uart.clock, childClock connect coupler_to_fpga_uart.reset, childReset inst coupler_to_fpga_spi of TLInterconnectCoupler_pbus_to_fpga_spi @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyScope.scala 99:27] connect coupler_to_fpga_spi.clock, childClock connect coupler_to_fpga_spi.reset, childReset inst coupler_to_fpga_pmod_spi of TLInterconnectCoupler_pbus_to_fpga_pmod_spi @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyScope.scala 99:27] connect coupler_to_fpga_pmod_spi.clock, childClock connect coupler_to_fpga_pmod_spi.reset, childReset inst coupler_to_gps of TLInterconnectCoupler_pbus_to_gps @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyScope.scala 99:27] connect coupler_to_gps.clock, childClock connect coupler_to_gps.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate clockSinkNodeIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate clockSinkNodeIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate bus_xingOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate bus_xingIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect bus_xingOut, bus_xingIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect clockGroup.auto.in, pbus_clock_groups.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fixedClockNode.auto.anon_in, clockGroup.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect out_xbar.auto.anon_in, fixer.auto.anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect atomics.auto.in, in_xbar.auto.anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect coupler_to_fpga_uart.auto.tl_in, out_xbar.auto.anon_out_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect coupler_to_fpga_spi.auto.tl_in, out_xbar.auto.anon_out_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect coupler_to_fpga_pmod_spi.auto.tl_in, out_xbar.auto.anon_out_2 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect coupler_to_gps.auto.tl_in, out_xbar.auto.anon_out_3 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fixer.auto.anon_in, buffer.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect buffer.auto.in, atomics.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect in_xbar.auto.anon_in, buffer_1.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect buffer_1.auto.in, bus_xingOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect bus_xingIn, auto.bus_xing_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect pbus_clock_groups.auto.in, auto.pbus_clock_groups_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fixedClockNode_anon_out_2, fixedClockNode.auto.anon_out_3 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fixedClockNode_anon_out_3, fixedClockNode.auto.anon_out_4 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_fpga_uart.auto.fragmenter_anon_out.d, auto.coupler_to_fpga_uart_fragmenter_anon_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_fpga_uart_fragmenter_anon_out.a.bits, coupler_to_fpga_uart.auto.fragmenter_anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_fpga_uart_fragmenter_anon_out.a.valid, coupler_to_fpga_uart.auto.fragmenter_anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_fpga_uart.auto.fragmenter_anon_out.a.ready, auto.coupler_to_fpga_uart_fragmenter_anon_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_fpga_spi.auto.fragmenter_anon_out.d, auto.coupler_to_fpga_spi_fragmenter_anon_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_fpga_spi_fragmenter_anon_out.a.bits, coupler_to_fpga_spi.auto.fragmenter_anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_fpga_spi_fragmenter_anon_out.a.valid, coupler_to_fpga_spi.auto.fragmenter_anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_fpga_spi.auto.fragmenter_anon_out.a.ready, auto.coupler_to_fpga_spi_fragmenter_anon_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_fpga_pmod_spi.auto.fragmenter_anon_out.d, auto.coupler_to_fpga_pmod_spi_fragmenter_anon_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_fpga_pmod_spi_fragmenter_anon_out.a.bits, coupler_to_fpga_pmod_spi.auto.fragmenter_anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_fpga_pmod_spi_fragmenter_anon_out.a.valid, coupler_to_fpga_pmod_spi.auto.fragmenter_anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_fpga_pmod_spi.auto.fragmenter_anon_out.a.ready, auto.coupler_to_fpga_pmod_spi_fragmenter_anon_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_gps.auto.fragmenter_anon_out.d, auto.coupler_to_gps_fragmenter_anon_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_gps_fragmenter_anon_out.a.bits, coupler_to_gps.auto.fragmenter_anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_gps_fragmenter_anon_out.a.valid, coupler_to_gps.auto.fragmenter_anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_gps.auto.fragmenter_anon_out.a.ready, auto.coupler_to_gps_fragmenter_anon_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect childClock, clockSinkNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 15:16] connect childReset, clockSinkNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 16:16] connect clock, clockSinkNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 23:11] connect reset, clockSinkNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 24:11] module ClockGroupAggregator_fbus : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 53:9] output auto : { flip in : { member : { fbus_0 : { clock : Clock, reset : Reset}}}, out : { member : { fbus_0 : { clock : Clock, reset : Reset}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeOut : { member : { fbus_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.member.fbus_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.member.fbus_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire nodeIn : { member : { fbus_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.member.fbus_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.fbus_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut.member.fbus_0, nodeIn.member.fbus_0 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 60:65] module ClockGroup_2 : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 24:9] output auto : { flip in : { member : { fbus_0 : { clock : Clock, reset : Reset}}}, out : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeOut : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire nodeIn : { member : { fbus_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.member.fbus_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.fbus_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut, nodeIn.member.fbus_0 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 31:57] module FixedClockBroadcast_1 : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 104:9] output auto : { flip anon_in : { clock : Clock, reset : Reset}, anon_out : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire anonOut : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire anonIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonOut, anonIn @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 109:21] module BundleBridgeNexus_NoOutput_2 : @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 21:9] output auto : { } @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] module TLXbar_fbus_i1_o1_a32d64s1k1z4u : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 159:18] invalidate in[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.data, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.mask, anonIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.address, anonIn.a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.source, anonIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.size, anonIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.param, anonIn.a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.opcode, anonIn.a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.valid, anonIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect anonIn.a.ready, in[0].a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:55] connect in[0].a.bits.source, _in_0_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:29] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_1.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_3.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 180:23] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 181:26] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_9.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_11.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.bits, _WIRE_12.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, _WIRE_12.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.ready, _WIRE_12.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 191:23] wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.bits, _WIRE_14.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.valid, _WIRE_14.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.ready, _WIRE_14.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 192:26] connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.data, in[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.denied, in[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.sink, in[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.source, in[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.size, in[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.param, in[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.opcode, in[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.valid, in[0].d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect in[0].d.ready, anonIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 197:32] wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.bits, _WIRE_16.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.valid, _WIRE_16.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.ready, _WIRE_16.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_17.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_17.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_17.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.bits, _WIRE_18.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.valid, _WIRE_18.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.ready, _WIRE_18.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_19.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_19.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_19.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.bits, _WIRE_20.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.valid, _WIRE_20.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.ready, _WIRE_20.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 210:23] wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.bits, _WIRE_22.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.valid, _WIRE_22.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, _WIRE_22.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 211:26] wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 216:19] invalidate out[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.data, out[0].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.mask, out[0].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.fetch, out[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.secure, out[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.privileged, out[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.writealloc, out[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.readalloc, out[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.modifiable, out[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.bufferable, out[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.address, out[0].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.source, out[0].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.size, out[0].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.param, out[0].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.opcode, out[0].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.valid, out[0].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[0].a.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.bits, _WIRE_24.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.valid, _WIRE_24.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.ready, _WIRE_24.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_25.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.bits, _WIRE_26.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.valid, _WIRE_26.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.ready, _WIRE_26.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_27.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.bits, _WIRE_28.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.valid, _WIRE_28.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.ready, _WIRE_28.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.bits, _WIRE_30.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.valid, _WIRE_30.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.ready, _WIRE_30.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.bits, _WIRE_32.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.valid, _WIRE_32.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.ready, _WIRE_32.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_33.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.bits, _WIRE_34.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.valid, _WIRE_34.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.ready, _WIRE_34.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_35.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.bits, _WIRE_36.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.valid, _WIRE_36.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.ready, _WIRE_36.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.bits, _WIRE_38.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.valid, _WIRE_38.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.ready, _WIRE_38.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.valid, anonOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect anonOut.d.ready, out[0].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[0].d.bits.sink, _out_0_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.bits, _WIRE_40.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.valid, _WIRE_40.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.ready, _WIRE_40.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_41.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_41.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_41.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.bits, _WIRE_42.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.valid, _WIRE_42.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.ready, _WIRE_42.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_43.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_43.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_43.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.bits, _WIRE_44.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.valid, _WIRE_44.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.ready, _WIRE_44.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.bits, _WIRE_46.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.valid, _WIRE_46.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.ready, _WIRE_46.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.bits, _addressC_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.valid, _addressC_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.ready, _addressC_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_1 = cvt(_requestAIO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_3 = asSInt(_requestAIO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_1 = cvt(_requestCIO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_3 = asSInt(_requestCIO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node requestBOI_0_0 = eq(_requestBOI_WIRE_1.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 48:9] node requestDOI_0_0 = eq(out[0].d.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 48:9] wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 102:36] node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsAOI_filtered[0].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect in[0].a.ready, portsAOI_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.data, out[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.source, out[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.size, out[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.param, out[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect out[0].d.ready, portsDIO_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] connect out[0].a, portsAOI_filtered[0] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_49.bits, _WIRE_48.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_49.valid, _WIRE_48.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_49.ready, _WIRE_48.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_49.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_50.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_50.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_50.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_51.bits, _WIRE_50.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_51.valid, _WIRE_50.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_51.ready, _WIRE_50.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_51.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.bits, _WIRE_52.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.valid, _WIRE_52.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.ready, _WIRE_52.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_53.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect in[0].d, portsDIO_filtered[0] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] connect portsBIO_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] module Queue2_TLBundleA_a32d64s1k1z4u : @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input clock : Clock @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input reset : Reset @[src/main/scala/chisel3/util/Decoupled.scala 243:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, count : UInt<2>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} [2] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] regreset enq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset deq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] infer mport MPORT = ram[enq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 270:24] node wrap = eq(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T = add(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_1 = tail(_value_T, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect enq_ptr_value, _value_T_1 @[src/main/scala/chisel3/util/Counter.scala 77:15] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] node wrap_1 = eq(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_3 = tail(_value_T_2, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect deq_ptr_value, _value_T_3 @[src/main/scala/chisel3/util/Counter.scala 77:15] node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] infer mport io_deq_bits_MPORT = ram[deq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module Queue2_TLBundleD_a32d64s1k1z4u : @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input clock : Clock @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input reset : Reset @[src/main/scala/chisel3/util/Decoupled.scala 243:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, count : UInt<2>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} [2] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] regreset enq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset deq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] infer mport MPORT = ram[enq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 270:24] node wrap = eq(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T = add(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_1 = tail(_value_T, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect enq_ptr_value, _value_T_1 @[src/main/scala/chisel3/util/Counter.scala 77:15] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] node wrap_1 = eq(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_3 = tail(_value_T_2, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect deq_ptr_value, _value_T_3 @[src/main/scala/chisel3/util/Counter.scala 77:15] node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] infer mport io_deq_bits_MPORT = ram[deq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module TLBuffer_a32d64s1k1z4u : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] inst nodeOut_a_q of Queue2_TLBundleA_a32d64s1k1z4u @[src/main/scala/chisel3/util/Decoupled.scala 362:21] connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid @[src/main/scala/chisel3/util/Decoupled.scala 364:22] connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.fetch, nodeIn.a.bits.user.amba_prot.fetch @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.secure, nodeIn.a.bits.user.amba_prot.secure @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.privileged, nodeIn.a.bits.user.amba_prot.privileged @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.writealloc, nodeIn.a.bits.user.amba_prot.writealloc @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.readalloc, nodeIn.a.bits.user.amba_prot.readalloc @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.modifiable, nodeIn.a.bits.user.amba_prot.modifiable @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.bufferable, nodeIn.a.bits.user.amba_prot.bufferable @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready @[src/main/scala/chisel3/util/Decoupled.scala 366:17] connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] inst nodeIn_d_q of Queue2_TLBundleD_a32d64s1k1z4u @[src/main/scala/chisel3/util/Decoupled.scala 362:21] connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid @[src/main/scala/chisel3/util/Decoupled.scala 364:22] connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready @[src/main/scala/chisel3/util/Decoupled.scala 366:17] connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 52:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 53:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 54:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 55:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 56:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 57:21] module Repeater_TLBundleD_a32d64s1k1z4u : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 13:14] regreset full : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 20:21] reg saved : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 21:18] node _io_deq_valid_T = or(io.enq.valid, full) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:32] connect io.deq.valid, _io_deq_valid_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:35] node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:32] connect io.enq.ready, _io_enq_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:16] node _io_deq_bits_T = mux(full, saved, io.enq.bits) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:21] connect io.deq.bits, _io_deq_bits_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:15] connect io.full, full @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 27:11] node _T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_1 = and(_T, io.repeat) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:21] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:36] connect full, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:43] connect saved, io.enq.bits @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] node _T_2 = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_3 = eq(io.repeat, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:24] node _T_4 = and(_T_2, _T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:21] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:36] connect full, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:43] module TLWidthWidget1 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] node _hasData_opdata_T = bits(anonIn.a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node hasData = eq(_hasData_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node _limit_T = dshl(UInt<3>(0h7), anonIn.a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _limit_T_1 = bits(_limit_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _limit_T_2 = not(_limit_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node limit = shr(_limit_T_2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 38:47] regreset count : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 40:27] node first = eq(count, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 41:26] node _last_T = eq(count, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 42:26] node _last_T_1 = eq(hasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 42:39] node last = or(_last_T, _last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 42:36] node _enable_T = xor(count, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:56] node _enable_T_1 = and(_enable_T, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:63] node _enable_T_2 = orr(_enable_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:72] node enable_0 = eq(_enable_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:47] node _enable_T_3 = xor(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:56] node _enable_T_4 = and(_enable_T_3, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:63] node _enable_T_5 = orr(_enable_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:72] node enable_1 = eq(_enable_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:47] node _enable_T_6 = xor(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:56] node _enable_T_7 = and(_enable_T_6, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:63] node _enable_T_8 = orr(_enable_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:72] node enable_2 = eq(_enable_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:47] node _enable_T_9 = xor(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:56] node _enable_T_10 = and(_enable_T_9, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:63] node _enable_T_11 = orr(_enable_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:72] node enable_3 = eq(_enable_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:47] node _enable_T_12 = xor(count, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:56] node _enable_T_13 = and(_enable_T_12, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:63] node _enable_T_14 = orr(_enable_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:72] node enable_4 = eq(_enable_T_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:47] node _enable_T_15 = xor(count, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:56] node _enable_T_16 = and(_enable_T_15, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:63] node _enable_T_17 = orr(_enable_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:72] node enable_5 = eq(_enable_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:47] node _enable_T_18 = xor(count, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:56] node _enable_T_19 = and(_enable_T_18, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:63] node _enable_T_20 = orr(_enable_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:72] node enable_6 = eq(_enable_T_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:47] node _enable_T_21 = xor(count, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:56] node _enable_T_22 = and(_enable_T_21, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:63] node _enable_T_23 = orr(_enable_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:72] node enable_7 = eq(_enable_T_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 43:47] regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 45:32] node corrupt_out = or(anonIn.a.bits.corrupt, corrupt_reg) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 47:36] node _T = and(anonIn.a.ready, anonIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 49:22] node _count_T = add(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 50:24] node _count_T_1 = tail(_count_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 50:24] connect count, _count_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 50:15] connect corrupt_reg, corrupt_out @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 51:21] when last : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 52:21] connect count, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 53:17] connect corrupt_reg, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 54:23] node _anonIn_a_ready_T = eq(last, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 76:32] node _anonIn_a_ready_T_1 = or(anonOut.a.ready, _anonIn_a_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 76:29] connect anonIn.a.ready, _anonIn_a_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 76:16] node _anonOut_a_valid_T = and(anonIn.a.valid, last) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 77:29] connect anonOut.a.valid, _anonOut_a_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 77:17] connect anonOut.a.bits, anonIn.a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 78:16] regreset anonOut_a_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 62:41] node _anonOut_a_bits_data_masked_enable_T = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:45] node anonOut_a_bits_data_masked_enable_0 = or(enable_0, _anonOut_a_bits_data_masked_enable_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:42] node _anonOut_a_bits_data_masked_enable_T_1 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:45] node anonOut_a_bits_data_masked_enable_1 = or(enable_1, _anonOut_a_bits_data_masked_enable_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:42] node _anonOut_a_bits_data_masked_enable_T_2 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:45] node anonOut_a_bits_data_masked_enable_2 = or(enable_2, _anonOut_a_bits_data_masked_enable_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:42] node _anonOut_a_bits_data_masked_enable_T_3 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:45] node anonOut_a_bits_data_masked_enable_3 = or(enable_3, _anonOut_a_bits_data_masked_enable_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:42] node _anonOut_a_bits_data_masked_enable_T_4 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:45] node anonOut_a_bits_data_masked_enable_4 = or(enable_4, _anonOut_a_bits_data_masked_enable_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:42] node _anonOut_a_bits_data_masked_enable_T_5 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:45] node anonOut_a_bits_data_masked_enable_5 = or(enable_5, _anonOut_a_bits_data_masked_enable_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:42] node _anonOut_a_bits_data_masked_enable_T_6 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:45] node anonOut_a_bits_data_masked_enable_6 = or(enable_6, _anonOut_a_bits_data_masked_enable_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:42] node _anonOut_a_bits_data_masked_enable_T_7 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:45] node anonOut_a_bits_data_masked_enable_7 = or(enable_7, _anonOut_a_bits_data_masked_enable_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:42] wire anonOut_a_bits_data_odata_0 : UInt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] connect anonOut_a_bits_data_odata_0, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] wire anonOut_a_bits_data_odata_1 : UInt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] connect anonOut_a_bits_data_odata_1, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] wire anonOut_a_bits_data_odata_2 : UInt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] connect anonOut_a_bits_data_odata_2, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] wire anonOut_a_bits_data_odata_3 : UInt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] connect anonOut_a_bits_data_odata_3, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] wire anonOut_a_bits_data_odata_4 : UInt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] connect anonOut_a_bits_data_odata_4, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] wire anonOut_a_bits_data_odata_5 : UInt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] connect anonOut_a_bits_data_odata_5, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] wire anonOut_a_bits_data_odata_6 : UInt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] connect anonOut_a_bits_data_odata_6, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] wire anonOut_a_bits_data_odata_7 : UInt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] connect anonOut_a_bits_data_odata_7, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] reg anonOut_a_bits_data_rdata : UInt<8>[7], clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 66:24] node anonOut_a_bits_data_mdata_0 = mux(anonOut_a_bits_data_masked_enable_0, anonOut_a_bits_data_odata_0, anonOut_a_bits_data_rdata[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 68:88] node anonOut_a_bits_data_mdata_1 = mux(anonOut_a_bits_data_masked_enable_1, anonOut_a_bits_data_odata_1, anonOut_a_bits_data_rdata[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 68:88] node anonOut_a_bits_data_mdata_2 = mux(anonOut_a_bits_data_masked_enable_2, anonOut_a_bits_data_odata_2, anonOut_a_bits_data_rdata[2]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 68:88] node anonOut_a_bits_data_mdata_3 = mux(anonOut_a_bits_data_masked_enable_3, anonOut_a_bits_data_odata_3, anonOut_a_bits_data_rdata[3]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 68:88] node anonOut_a_bits_data_mdata_4 = mux(anonOut_a_bits_data_masked_enable_4, anonOut_a_bits_data_odata_4, anonOut_a_bits_data_rdata[4]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 68:88] node anonOut_a_bits_data_mdata_5 = mux(anonOut_a_bits_data_masked_enable_5, anonOut_a_bits_data_odata_5, anonOut_a_bits_data_rdata[5]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 68:88] node anonOut_a_bits_data_mdata_6 = mux(anonOut_a_bits_data_masked_enable_6, anonOut_a_bits_data_odata_6, anonOut_a_bits_data_rdata[6]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 68:88] node anonOut_a_bits_data_mdata_7 = mux(anonOut_a_bits_data_masked_enable_7, anonOut_a_bits_data_odata_7, anonIn.a.bits.data) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 68:88] node _anonOut_a_bits_data_T = and(anonIn.a.ready, anonIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _anonOut_a_bits_data_T_1 = eq(last, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 69:26] node _anonOut_a_bits_data_T_2 = and(_anonOut_a_bits_data_T, _anonOut_a_bits_data_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 69:23] when _anonOut_a_bits_data_T_2 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 69:33] connect anonOut_a_bits_data_rdata_written_once, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 70:30] connect anonOut_a_bits_data_rdata[0], anonOut_a_bits_data_mdata_0 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 71:56] connect anonOut_a_bits_data_rdata[1], anonOut_a_bits_data_mdata_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 71:56] connect anonOut_a_bits_data_rdata[2], anonOut_a_bits_data_mdata_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 71:56] connect anonOut_a_bits_data_rdata[3], anonOut_a_bits_data_mdata_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 71:56] connect anonOut_a_bits_data_rdata[4], anonOut_a_bits_data_mdata_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 71:56] connect anonOut_a_bits_data_rdata[5], anonOut_a_bits_data_mdata_5 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 71:56] connect anonOut_a_bits_data_rdata[6], anonOut_a_bits_data_mdata_6 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 71:56] node anonOut_a_bits_data_lo_lo = cat(anonOut_a_bits_data_mdata_1, anonOut_a_bits_data_mdata_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 73:12] node anonOut_a_bits_data_lo_hi = cat(anonOut_a_bits_data_mdata_3, anonOut_a_bits_data_mdata_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 73:12] node anonOut_a_bits_data_lo = cat(anonOut_a_bits_data_lo_hi, anonOut_a_bits_data_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 73:12] node anonOut_a_bits_data_hi_lo = cat(anonOut_a_bits_data_mdata_5, anonOut_a_bits_data_mdata_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 73:12] node anonOut_a_bits_data_hi_hi = cat(anonOut_a_bits_data_mdata_7, anonOut_a_bits_data_mdata_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 73:12] node anonOut_a_bits_data_hi = cat(anonOut_a_bits_data_hi_hi, anonOut_a_bits_data_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 73:12] node _anonOut_a_bits_data_T_3 = cat(anonOut_a_bits_data_hi, anonOut_a_bits_data_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 73:12] connect anonOut.a.bits.data, _anonOut_a_bits_data_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 81:30] connect anonOut.a.bits.corrupt, corrupt_out @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 82:33] node _anonOut_a_bits_mask_sizeOH_T = or(anonOut.a.bits.size, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node anonOut_a_bits_mask_sizeOH_shiftAmount = bits(_anonOut_a_bits_mask_sizeOH_T, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _anonOut_a_bits_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), anonOut_a_bits_mask_sizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _anonOut_a_bits_mask_sizeOH_T_2 = bits(_anonOut_a_bits_mask_sizeOH_T_1, 2, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node anonOut_a_bits_mask_sizeOH = or(_anonOut_a_bits_mask_sizeOH_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] node anonOut_a_bits_mask_sub_sub_sub_0_1 = geq(anonOut.a.bits.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 206:21] node anonOut_a_bits_mask_sub_sub_size = bits(anonOut_a_bits_mask_sizeOH, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node anonOut_a_bits_mask_sub_sub_bit = bits(anonOut.a.bits.address, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node anonOut_a_bits_mask_sub_sub_nbit = eq(anonOut_a_bits_mask_sub_sub_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node anonOut_a_bits_mask_sub_sub_0_2 = and(UInt<1>(0h1), anonOut_a_bits_mask_sub_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _anonOut_a_bits_mask_sub_sub_acc_T = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_0_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node anonOut_a_bits_mask_sub_sub_0_1 = or(anonOut_a_bits_mask_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node anonOut_a_bits_mask_sub_sub_1_2 = and(UInt<1>(0h1), anonOut_a_bits_mask_sub_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _anonOut_a_bits_mask_sub_sub_acc_T_1 = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_1_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node anonOut_a_bits_mask_sub_sub_1_1 = or(anonOut_a_bits_mask_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node anonOut_a_bits_mask_sub_size = bits(anonOut_a_bits_mask_sizeOH, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node anonOut_a_bits_mask_sub_bit = bits(anonOut.a.bits.address, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node anonOut_a_bits_mask_sub_nbit = eq(anonOut_a_bits_mask_sub_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node anonOut_a_bits_mask_sub_0_2 = and(anonOut_a_bits_mask_sub_sub_0_2, anonOut_a_bits_mask_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _anonOut_a_bits_mask_sub_acc_T = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_0_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node anonOut_a_bits_mask_sub_0_1 = or(anonOut_a_bits_mask_sub_sub_0_1, _anonOut_a_bits_mask_sub_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node anonOut_a_bits_mask_sub_1_2 = and(anonOut_a_bits_mask_sub_sub_0_2, anonOut_a_bits_mask_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _anonOut_a_bits_mask_sub_acc_T_1 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_1_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node anonOut_a_bits_mask_sub_1_1 = or(anonOut_a_bits_mask_sub_sub_0_1, _anonOut_a_bits_mask_sub_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node anonOut_a_bits_mask_sub_2_2 = and(anonOut_a_bits_mask_sub_sub_1_2, anonOut_a_bits_mask_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _anonOut_a_bits_mask_sub_acc_T_2 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_2_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node anonOut_a_bits_mask_sub_2_1 = or(anonOut_a_bits_mask_sub_sub_1_1, _anonOut_a_bits_mask_sub_acc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node anonOut_a_bits_mask_sub_3_2 = and(anonOut_a_bits_mask_sub_sub_1_2, anonOut_a_bits_mask_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _anonOut_a_bits_mask_sub_acc_T_3 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_3_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node anonOut_a_bits_mask_sub_3_1 = or(anonOut_a_bits_mask_sub_sub_1_1, _anonOut_a_bits_mask_sub_acc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node anonOut_a_bits_mask_size = bits(anonOut_a_bits_mask_sizeOH, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node anonOut_a_bits_mask_bit = bits(anonOut.a.bits.address, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node anonOut_a_bits_mask_nbit = eq(anonOut_a_bits_mask_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node anonOut_a_bits_mask_eq = and(anonOut_a_bits_mask_sub_0_2, anonOut_a_bits_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _anonOut_a_bits_mask_acc_T = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node anonOut_a_bits_mask_acc = or(anonOut_a_bits_mask_sub_0_1, _anonOut_a_bits_mask_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node anonOut_a_bits_mask_eq_1 = and(anonOut_a_bits_mask_sub_0_2, anonOut_a_bits_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _anonOut_a_bits_mask_acc_T_1 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node anonOut_a_bits_mask_acc_1 = or(anonOut_a_bits_mask_sub_0_1, _anonOut_a_bits_mask_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node anonOut_a_bits_mask_eq_2 = and(anonOut_a_bits_mask_sub_1_2, anonOut_a_bits_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _anonOut_a_bits_mask_acc_T_2 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node anonOut_a_bits_mask_acc_2 = or(anonOut_a_bits_mask_sub_1_1, _anonOut_a_bits_mask_acc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node anonOut_a_bits_mask_eq_3 = and(anonOut_a_bits_mask_sub_1_2, anonOut_a_bits_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _anonOut_a_bits_mask_acc_T_3 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node anonOut_a_bits_mask_acc_3 = or(anonOut_a_bits_mask_sub_1_1, _anonOut_a_bits_mask_acc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node anonOut_a_bits_mask_eq_4 = and(anonOut_a_bits_mask_sub_2_2, anonOut_a_bits_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _anonOut_a_bits_mask_acc_T_4 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node anonOut_a_bits_mask_acc_4 = or(anonOut_a_bits_mask_sub_2_1, _anonOut_a_bits_mask_acc_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node anonOut_a_bits_mask_eq_5 = and(anonOut_a_bits_mask_sub_2_2, anonOut_a_bits_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _anonOut_a_bits_mask_acc_T_5 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node anonOut_a_bits_mask_acc_5 = or(anonOut_a_bits_mask_sub_2_1, _anonOut_a_bits_mask_acc_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node anonOut_a_bits_mask_eq_6 = and(anonOut_a_bits_mask_sub_3_2, anonOut_a_bits_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _anonOut_a_bits_mask_acc_T_6 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node anonOut_a_bits_mask_acc_6 = or(anonOut_a_bits_mask_sub_3_1, _anonOut_a_bits_mask_acc_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node anonOut_a_bits_mask_eq_7 = and(anonOut_a_bits_mask_sub_3_2, anonOut_a_bits_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _anonOut_a_bits_mask_acc_T_7 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node anonOut_a_bits_mask_acc_7 = or(anonOut_a_bits_mask_sub_3_1, _anonOut_a_bits_mask_acc_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node anonOut_a_bits_mask_lo_lo = cat(anonOut_a_bits_mask_acc_1, anonOut_a_bits_mask_acc) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node anonOut_a_bits_mask_lo_hi = cat(anonOut_a_bits_mask_acc_3, anonOut_a_bits_mask_acc_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node anonOut_a_bits_mask_lo = cat(anonOut_a_bits_mask_lo_hi, anonOut_a_bits_mask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node anonOut_a_bits_mask_hi_lo = cat(anonOut_a_bits_mask_acc_5, anonOut_a_bits_mask_acc_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node anonOut_a_bits_mask_hi_hi = cat(anonOut_a_bits_mask_acc_7, anonOut_a_bits_mask_acc_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node anonOut_a_bits_mask_hi = cat(anonOut_a_bits_mask_hi_hi, anonOut_a_bits_mask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node _anonOut_a_bits_mask_T = cat(anonOut_a_bits_mask_hi, anonOut_a_bits_mask_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] regreset anonOut_a_bits_mask_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 62:41] node _anonOut_a_bits_mask_masked_enable_T = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:45] node anonOut_a_bits_mask_masked_enable_0 = or(enable_0, _anonOut_a_bits_mask_masked_enable_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:42] node _anonOut_a_bits_mask_masked_enable_T_1 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:45] node anonOut_a_bits_mask_masked_enable_1 = or(enable_1, _anonOut_a_bits_mask_masked_enable_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:42] node _anonOut_a_bits_mask_masked_enable_T_2 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:45] node anonOut_a_bits_mask_masked_enable_2 = or(enable_2, _anonOut_a_bits_mask_masked_enable_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:42] node _anonOut_a_bits_mask_masked_enable_T_3 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:45] node anonOut_a_bits_mask_masked_enable_3 = or(enable_3, _anonOut_a_bits_mask_masked_enable_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:42] node _anonOut_a_bits_mask_masked_enable_T_4 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:45] node anonOut_a_bits_mask_masked_enable_4 = or(enable_4, _anonOut_a_bits_mask_masked_enable_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:42] node _anonOut_a_bits_mask_masked_enable_T_5 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:45] node anonOut_a_bits_mask_masked_enable_5 = or(enable_5, _anonOut_a_bits_mask_masked_enable_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:42] node _anonOut_a_bits_mask_masked_enable_T_6 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:45] node anonOut_a_bits_mask_masked_enable_6 = or(enable_6, _anonOut_a_bits_mask_masked_enable_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:42] node _anonOut_a_bits_mask_masked_enable_T_7 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:45] node anonOut_a_bits_mask_masked_enable_7 = or(enable_7, _anonOut_a_bits_mask_masked_enable_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 63:42] wire anonOut_a_bits_mask_odata_0 : UInt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] connect anonOut_a_bits_mask_odata_0, anonIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] wire anonOut_a_bits_mask_odata_1 : UInt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] connect anonOut_a_bits_mask_odata_1, anonIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] wire anonOut_a_bits_mask_odata_2 : UInt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] connect anonOut_a_bits_mask_odata_2, anonIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] wire anonOut_a_bits_mask_odata_3 : UInt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] connect anonOut_a_bits_mask_odata_3, anonIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] wire anonOut_a_bits_mask_odata_4 : UInt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] connect anonOut_a_bits_mask_odata_4, anonIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] wire anonOut_a_bits_mask_odata_5 : UInt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] connect anonOut_a_bits_mask_odata_5, anonIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] wire anonOut_a_bits_mask_odata_6 : UInt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] connect anonOut_a_bits_mask_odata_6, anonIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] wire anonOut_a_bits_mask_odata_7 : UInt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] connect anonOut_a_bits_mask_odata_7, anonIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 65:47] reg anonOut_a_bits_mask_rdata : UInt<1>[7], clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 66:24] node anonOut_a_bits_mask_mdata_0 = mux(anonOut_a_bits_mask_masked_enable_0, anonOut_a_bits_mask_odata_0, anonOut_a_bits_mask_rdata[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 68:88] node anonOut_a_bits_mask_mdata_1 = mux(anonOut_a_bits_mask_masked_enable_1, anonOut_a_bits_mask_odata_1, anonOut_a_bits_mask_rdata[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 68:88] node anonOut_a_bits_mask_mdata_2 = mux(anonOut_a_bits_mask_masked_enable_2, anonOut_a_bits_mask_odata_2, anonOut_a_bits_mask_rdata[2]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 68:88] node anonOut_a_bits_mask_mdata_3 = mux(anonOut_a_bits_mask_masked_enable_3, anonOut_a_bits_mask_odata_3, anonOut_a_bits_mask_rdata[3]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 68:88] node anonOut_a_bits_mask_mdata_4 = mux(anonOut_a_bits_mask_masked_enable_4, anonOut_a_bits_mask_odata_4, anonOut_a_bits_mask_rdata[4]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 68:88] node anonOut_a_bits_mask_mdata_5 = mux(anonOut_a_bits_mask_masked_enable_5, anonOut_a_bits_mask_odata_5, anonOut_a_bits_mask_rdata[5]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 68:88] node anonOut_a_bits_mask_mdata_6 = mux(anonOut_a_bits_mask_masked_enable_6, anonOut_a_bits_mask_odata_6, anonOut_a_bits_mask_rdata[6]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 68:88] node anonOut_a_bits_mask_mdata_7 = mux(anonOut_a_bits_mask_masked_enable_7, anonOut_a_bits_mask_odata_7, anonIn.a.bits.mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 68:88] node _anonOut_a_bits_mask_T_1 = and(anonIn.a.ready, anonIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _anonOut_a_bits_mask_T_2 = eq(last, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 69:26] node _anonOut_a_bits_mask_T_3 = and(_anonOut_a_bits_mask_T_1, _anonOut_a_bits_mask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 69:23] when _anonOut_a_bits_mask_T_3 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 69:33] connect anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 70:30] connect anonOut_a_bits_mask_rdata[0], anonOut_a_bits_mask_mdata_0 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 71:56] connect anonOut_a_bits_mask_rdata[1], anonOut_a_bits_mask_mdata_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 71:56] connect anonOut_a_bits_mask_rdata[2], anonOut_a_bits_mask_mdata_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 71:56] connect anonOut_a_bits_mask_rdata[3], anonOut_a_bits_mask_mdata_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 71:56] connect anonOut_a_bits_mask_rdata[4], anonOut_a_bits_mask_mdata_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 71:56] connect anonOut_a_bits_mask_rdata[5], anonOut_a_bits_mask_mdata_5 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 71:56] connect anonOut_a_bits_mask_rdata[6], anonOut_a_bits_mask_mdata_6 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 71:56] node anonOut_a_bits_mask_lo_lo_1 = cat(anonOut_a_bits_mask_mdata_1, anonOut_a_bits_mask_mdata_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 73:12] node anonOut_a_bits_mask_lo_hi_1 = cat(anonOut_a_bits_mask_mdata_3, anonOut_a_bits_mask_mdata_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 73:12] node anonOut_a_bits_mask_lo_1 = cat(anonOut_a_bits_mask_lo_hi_1, anonOut_a_bits_mask_lo_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 73:12] node anonOut_a_bits_mask_hi_lo_1 = cat(anonOut_a_bits_mask_mdata_5, anonOut_a_bits_mask_mdata_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 73:12] node anonOut_a_bits_mask_hi_hi_1 = cat(anonOut_a_bits_mask_mdata_7, anonOut_a_bits_mask_mdata_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 73:12] node anonOut_a_bits_mask_hi_1 = cat(anonOut_a_bits_mask_hi_hi_1, anonOut_a_bits_mask_hi_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 73:12] node _anonOut_a_bits_mask_T_4 = cat(anonOut_a_bits_mask_hi_1, anonOut_a_bits_mask_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 73:12] node _anonOut_a_bits_mask_T_5 = not(UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 85:119] node _anonOut_a_bits_mask_T_6 = mux(hasData, _anonOut_a_bits_mask_T_4, _anonOut_a_bits_mask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 85:93] node _anonOut_a_bits_mask_T_7 = and(_anonOut_a_bits_mask_T, _anonOut_a_bits_mask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 85:88] connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T_7 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 85:53] wire repeat : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 159:26] inst repeated_repeater of Repeater_TLBundleD_a32d64s1k1z4u @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 36:26] connect repeated_repeater.clock, clock connect repeated_repeater.reset, reset connect repeated_repeater.io.repeat, repeat @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 37:24] connect repeated_repeater.io.enq, anonOut.d @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 38:21] wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 161:25] connect cated.bits, repeated_repeater.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 162:15] connect cated.valid, repeated_repeater.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 162:15] connect repeated_repeater.io.deq.ready, cated.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 162:15] node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 63, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 164:37] node _cated_bits_data_T_1 = bits(anonOut.d.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 165:31] node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 163:39] connect cated.bits.data, _cated_bits_data_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 163:33] node repeat_hasData = bits(cated.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node _repeat_limit_T = dshl(UInt<3>(0h7), cated.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _repeat_limit_T_1 = bits(_repeat_limit_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _repeat_limit_T_2 = not(_repeat_limit_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node repeat_limit = shr(_repeat_limit_T_2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 103:47] regreset repeat_count : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 105:26] node repeat_first = eq(repeat_count, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 106:25] node _repeat_last_T = eq(repeat_count, repeat_limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 107:25] node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 107:38] node repeat_last = or(_repeat_last_T, _repeat_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 107:35] node _repeat_T = and(anonIn.d.ready, anonIn.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _repeat_T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 109:23] node _repeat_count_T = add(repeat_count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 110:24] node _repeat_count_T_1 = tail(_repeat_count_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 110:24] connect repeat_count, _repeat_count_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 110:15] when repeat_last : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 111:21] connect repeat_count, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 111:29] reg repeat_sel_sel_sources : UInt<3>[1], clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 187:27] node repeat_sel_sel_a_sel = bits(anonIn.a.bits.address, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 188:38] node _repeat_sel_sel_T = and(anonIn.a.ready, anonIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _repeat_sel_sel_T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 189:26] connect repeat_sel_sel_sources[0], repeat_sel_sel_a_sel @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 191:24] node _repeat_sel_sel_bypass_T = eq(anonIn.a.bits.source, UInt<0>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 200:53] node repeat_sel_sel_bypass = and(anonIn.a.valid, _repeat_sel_sel_bypass_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 200:33] reg repeat_sel_hold_r : UInt<3>, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 121:47] when repeat_first : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 121:47] connect repeat_sel_hold_r, repeat_sel_sel_sources[0] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 121:47] node repeat_sel_hold = mux(repeat_first, repeat_sel_sel_sources[0], repeat_sel_hold_r) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 121:25] node _repeat_sel_T = not(repeat_limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 122:18] node repeat_sel = and(repeat_sel_hold, _repeat_sel_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 122:16] node repeat_index = or(repeat_sel, repeat_count) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 126:24] connect anonIn.d.bits.corrupt, cated.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 132:16] connect anonIn.d.bits.data, cated.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 132:16] connect anonIn.d.bits.denied, cated.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 132:16] connect anonIn.d.bits.sink, cated.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 132:16] connect anonIn.d.bits.source, cated.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 132:16] connect anonIn.d.bits.size, cated.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 132:16] connect anonIn.d.bits.param, cated.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 132:16] connect anonIn.d.bits.opcode, cated.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 132:16] connect anonIn.d.valid, cated.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 133:17] connect cated.ready, anonIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 134:16] node _repeat_anonIn_d_bits_data_mux_T = bits(cated.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:55] node _repeat_anonIn_d_bits_data_mux_T_1 = bits(cated.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:55] node _repeat_anonIn_d_bits_data_mux_T_2 = bits(cated.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:55] node _repeat_anonIn_d_bits_data_mux_T_3 = bits(cated.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:55] node _repeat_anonIn_d_bits_data_mux_T_4 = bits(cated.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:55] node _repeat_anonIn_d_bits_data_mux_T_5 = bits(cated.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:55] node _repeat_anonIn_d_bits_data_mux_T_6 = bits(cated.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:55] node _repeat_anonIn_d_bits_data_mux_T_7 = bits(cated.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:55] wire repeat_anonIn_d_bits_data_mux : UInt<8>[8] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:43] connect repeat_anonIn_d_bits_data_mux[0], _repeat_anonIn_d_bits_data_mux_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:43] connect repeat_anonIn_d_bits_data_mux[1], _repeat_anonIn_d_bits_data_mux_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:43] connect repeat_anonIn_d_bits_data_mux[2], _repeat_anonIn_d_bits_data_mux_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:43] connect repeat_anonIn_d_bits_data_mux[3], _repeat_anonIn_d_bits_data_mux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:43] connect repeat_anonIn_d_bits_data_mux[4], _repeat_anonIn_d_bits_data_mux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:43] connect repeat_anonIn_d_bits_data_mux[5], _repeat_anonIn_d_bits_data_mux_T_5 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:43] connect repeat_anonIn_d_bits_data_mux[6], _repeat_anonIn_d_bits_data_mux_T_6 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:43] connect repeat_anonIn_d_bits_data_mux[7], _repeat_anonIn_d_bits_data_mux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 128:43] connect anonIn.d.bits.data, repeat_anonIn_d_bits_data_mux[repeat_index] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 137:30] node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 148:7] connect repeat, _repeat_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 166:16] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 215:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 216:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 217:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 218:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 219:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 220:21] module TLInterconnectCoupler_fbus_from_debug_sb : @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input clock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input reset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] output auto : { flip widget_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, tl_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] inst widget of TLWidthWidget1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 230:28] connect widget.clock, clock connect widget.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate tlOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tlIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect tlOut, tlIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect widget.auto.anon_out.d, tlIn.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tlIn.a.bits, widget.auto.anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tlIn.a.valid, widget.auto.anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect widget.auto.anon_out.a.ready, tlIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect auto.tl_out, tlOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect widget.auto.anon_in, auto.widget_anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] module FrontBus : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 14:9] output auto : { flip coupler_from_debug_sb_widget_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, flip fbus_clock_groups_in : { member : { fbus_0 : { clock : Clock, reset : Reset}}}, bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 21:19] output reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 22:19] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] inst fbus_clock_groups of ClockGroupAggregator_fbus @[hardware/upstream/rocket-chip/src/main/scala/tilelink/BusWrapper.scala 52:48] inst clockGroup of ClockGroup_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/BusWrapper.scala 53:38] inst fixedClockNode of FixedClockBroadcast_1 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 115:114] inst broadcast of BundleBridgeNexus_NoOutput_2 @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/package.scala 25:31] inst fbus_xbar of TLXbar_fbus_i1_o1_a32d64s1k1z4u @[hardware/upstream/rocket-chip/src/main/scala/tilelink/BusWrapper.scala 240:32] connect fbus_xbar.clock, childClock connect fbus_xbar.reset, childReset inst buffer of TLBuffer_a32d64s1k1z4u @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 75:28] connect buffer.clock, childClock connect buffer.reset, childReset inst coupler_from_debug_sb of TLInterconnectCoupler_fbus_from_debug_sb @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyScope.scala 99:27] connect coupler_from_debug_sb.clock, childClock connect coupler_from_debug_sb.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate clockSinkNodeIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate clockSinkNodeIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate bus_xingOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate bus_xingIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect bus_xingOut, bus_xingIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect clockGroup.auto.in, fbus_clock_groups.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fixedClockNode.auto.anon_in, clockGroup.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect clockSinkNodeIn, fixedClockNode.auto.anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect buffer.auto.in, fbus_xbar.auto.anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect buffer.auto.out.d, bus_xingIn.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect bus_xingIn.a.bits, buffer.auto.out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect bus_xingIn.a.valid, buffer.auto.out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect buffer.auto.out.a.ready, bus_xingIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect fbus_xbar.auto.anon_in, coupler_from_debug_sb.auto.tl_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect auto.bus_xing_out, bus_xingOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect fbus_clock_groups.auto.in, auto.fbus_clock_groups_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect coupler_from_debug_sb.auto.widget_anon_in, auto.coupler_from_debug_sb_widget_anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect childClock, clockSinkNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 15:16] connect childReset, clockSinkNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 16:16] connect clock, clockSinkNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 23:11] connect reset, clockSinkNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 24:11] module ClockGroupAggregator_cbus : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 53:9] output auto : { flip in : { member : { cbus_1 : { clock : Clock, reset : Reset}, cbus_0 : { clock : Clock, reset : Reset}}}, out_1 : { member : { pbus_0 : { clock : Clock, reset : Reset}}}, out_0 : { member : { cbus_0 : { clock : Clock, reset : Reset}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeIn : { member : { cbus_1 : { clock : Clock, reset : Reset}, cbus_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.member.cbus_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.cbus_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.cbus_1.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.cbus_1.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { member : { cbus_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.member.cbus_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.member.cbus_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_nodeOut : { member : { pbus_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_nodeOut.member.pbus_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.member.pbus_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out_0, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.out_1, x1_nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut.member.cbus_0, nodeIn.member.cbus_0 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 60:65] connect x1_nodeOut.member.pbus_0, nodeIn.member.cbus_1 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 60:65] module ClockGroup_3 : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 24:9] output auto : { flip in : { member : { cbus_0 : { clock : Clock, reset : Reset}}}, out : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeOut : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire nodeIn : { member : { cbus_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.member.cbus_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.member.cbus_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut, nodeIn.member.cbus_0 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 31:57] module FixedClockBroadcast_5_1 : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 104:9] output auto : { flip anon_in : { clock : Clock, reset : Reset}, anon_out_4 : { clock : Clock, reset : Reset}, anon_out_3 : { clock : Clock, reset : Reset}, anon_out_2 : { clock : Clock, reset : Reset}, anon_out_1 : { clock : Clock, reset : Reset}, anon_out_0 : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire anonIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut_1 : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut_1.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut_2 : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut_2.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut_3 : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut_3.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out_0, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_1, x1_anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_2, x1_anonOut_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_3, x1_anonOut_2 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_4, x1_anonOut_3 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonOut, anonIn @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 109:21] connect x1_anonOut, anonIn @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 109:21] connect x1_anonOut_1, anonIn @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 109:21] connect x1_anonOut_2, anonIn @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 109:21] connect x1_anonOut_3, anonIn @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 109:21] module BundleBridgeNexus_NoOutput_3 : @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 21:9] output auto : { } @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] module TLFIFOFixer_2 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 50:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 50:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 50:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] node _a_notFIFO_T = xor(anonIn.a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_notFIFO_T_1 = cvt(_a_notFIFO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_notFIFO_T_2 = and(_a_notFIFO_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_notFIFO_T_3 = asSInt(_a_notFIFO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_notFIFO_T_4 = eq(_a_notFIFO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_id_T = xor(anonIn.a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_id_T_1 = cvt(_a_id_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_id_T_2 = and(_a_id_T_1, asSInt(UInt<33>(0h9a011000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_3 = asSInt(_a_id_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_4 = eq(_a_id_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_id_T_5 = xor(anonIn.a.bits.address, UInt<13>(0h1000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_id_T_6 = cvt(_a_id_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_id_T_7 = and(_a_id_T_6, asSInt(UInt<33>(0h9a011000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_8 = asSInt(_a_id_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_9 = eq(_a_id_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_id_T_10 = xor(anonIn.a.bits.address, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_id_T_11 = cvt(_a_id_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_id_T_12 = and(_a_id_T_11, asSInt(UInt<33>(0h9a010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_13 = asSInt(_a_id_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_14 = eq(_a_id_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_id_T_15 = xor(anonIn.a.bits.address, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_id_T_16 = cvt(_a_id_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_id_T_17 = and(_a_id_T_16, asSInt(UInt<33>(0h9a010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_18 = asSInt(_a_id_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_19 = eq(_a_id_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_id_T_20 = xor(anonIn.a.bits.address, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_id_T_21 = cvt(_a_id_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_id_T_22 = and(_a_id_T_21, asSInt(UInt<33>(0h98000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_23 = asSInt(_a_id_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_24 = eq(_a_id_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_id_T_25 = xor(anonIn.a.bits.address, UInt<29>(0h10000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_id_T_26 = cvt(_a_id_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_id_T_27 = and(_a_id_T_26, asSInt(UInt<33>(0h9a000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_28 = asSInt(_a_id_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_29 = eq(_a_id_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_id_T_30 = xor(anonIn.a.bits.address, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_id_T_31 = cvt(_a_id_T_30) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_id_T_32 = and(_a_id_T_31, asSInt(UInt<33>(0h9a000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_33 = asSInt(_a_id_T_32) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_id_T_34 = eq(_a_id_T_33, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_id_T_35 = mux(_a_id_T_4, UInt<3>(0h7), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _a_id_T_36 = mux(_a_id_T_9, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _a_id_T_37 = mux(_a_id_T_14, UInt<3>(0h4), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _a_id_T_38 = mux(_a_id_T_19, UInt<3>(0h5), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _a_id_T_39 = mux(_a_id_T_24, UInt<3>(0h6), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _a_id_T_40 = mux(_a_id_T_29, UInt<2>(0h3), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _a_id_T_41 = mux(_a_id_T_34, UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _a_id_T_42 = or(_a_id_T_35, _a_id_T_36) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _a_id_T_43 = or(_a_id_T_42, _a_id_T_37) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _a_id_T_44 = or(_a_id_T_43, _a_id_T_38) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _a_id_T_45 = or(_a_id_T_44, _a_id_T_39) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _a_id_T_46 = or(_a_id_T_45, _a_id_T_40) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _a_id_T_47 = or(_a_id_T_46, _a_id_T_41) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire a_id : UInt<3> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect a_id, _a_id_T_47 @[src/main/scala/chisel3/util/Mux.scala 30:73] node a_noDomain = eq(a_id, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 63:29] node _a_first_T = and(anonIn.a.ready, anonIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), anonIn.a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _a_first_beats1_opdata_T = bits(anonIn.a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node a_first_counter1 = tail(_a_first_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node a_first = eq(a_first_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node a_first_last = or(_a_first_last_T, _a_first_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node a_first_done = and(a_first_last, _a_first_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _a_first_count_T = not(a_first_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node a_first_count = and(a_first_beats1, _a_first_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _a_first_T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect a_first_counter, _a_first_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node _d_first_T = and(anonOut.d.ready, anonOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), anonOut.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node d_first_beats1_opdata = bits(anonOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node d_first_counter1 = tail(_d_first_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node d_first_first = eq(d_first_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node d_first_last = or(_d_first_last_T, _d_first_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node d_first_done = and(d_first_last, _d_first_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _d_first_count_T = not(d_first_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node d_first_count = and(d_first_beats1, _d_first_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _d_first_T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _d_first_counter_T = mux(d_first_first, d_first_beats1, d_first_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect d_first_counter, _d_first_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node _d_first_T_1 = neq(anonOut.d.bits.opcode, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 75:63] node d_first = and(d_first_first, _d_first_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 75:42] wire _flight_WIRE : UInt<1>[3] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 79:35] connect _flight_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 79:35] connect _flight_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 79:35] connect _flight_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 79:35] regreset flight : UInt<1>[3], clock, reset, _flight_WIRE @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 79:27] node _T = and(anonIn.a.ready, anonIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_1 = and(a_first, _T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 80:21] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 80:35] node _flight_T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 80:65] connect flight[anonIn.a.bits.source], _flight_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 80:62] node _T_2 = and(anonIn.d.ready, anonIn.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_3 = and(d_first, _T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 81:21] when _T_3 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 81:35] connect flight[anonIn.d.bits.source], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 81:62] connect anonOut.a, anonIn.a @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 93:13] connect anonIn.d, anonOut.d @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 94:12] node _anonOut_a_valid_T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 95:50] node _anonOut_a_valid_T_1 = or(UInt<1>(0h0), _anonOut_a_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 95:47] node _anonOut_a_valid_T_2 = and(anonIn.a.valid, _anonOut_a_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 95:33] connect anonOut.a.valid, _anonOut_a_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 95:19] node _anonIn_a_ready_T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 96:50] node _anonIn_a_ready_T_1 = or(UInt<1>(0h0), _anonIn_a_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 96:47] node _anonIn_a_ready_T_2 = and(anonOut.a.ready, _anonIn_a_ready_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 96:33] connect anonIn.a.ready, _anonIn_a_ready_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 96:18] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 103:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 104:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 105:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 106:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 107:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 108:21] node _T_4 = and(anonIn.a.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 113:33] regreset SourceIdFIFOed : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 115:35] wire SourceIdSet : UInt<3> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 116:36] connect SourceIdSet, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 116:36] wire SourceIdClear : UInt<3> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 117:38] connect SourceIdClear, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 117:38] node _T_5 = and(anonIn.a.ready, anonIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_6 = and(a_first, _T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 119:21] node _T_7 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 119:37] node _T_8 = and(_T_6, _T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 119:34] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 119:50] node _SourceIdSet_T = dshl(UInt<1>(0h1), anonIn.a.bits.source) @[src/main/scala/chisel3/util/OneHot.scala 58:35] connect SourceIdSet, _SourceIdSet_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 120:21] node _T_9 = and(anonIn.d.ready, anonIn.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_10 = and(d_first, _T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 122:21] when _T_10 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 122:36] node _SourceIdClear_T = dshl(UInt<1>(0h1), anonIn.d.bits.source) @[src/main/scala/chisel3/util/OneHot.scala 58:35] connect SourceIdClear, _SourceIdClear_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 123:23] node _SourceIdFIFOed_T = or(SourceIdFIFOed, SourceIdSet) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 126:40] connect SourceIdFIFOed, _SourceIdFIFOed_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 126:22] node _allIDs_FIFOed_T = mux(UInt<1>(0h1), UInt<3>(0h7), UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 127:48] node allIDs_FIFOed = eq(SourceIdFIFOed, _allIDs_FIFOed_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 127:41] node _T_11 = or(flight[0], flight[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 131:40] node _T_12 = or(_T_11, flight[2]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 131:40] node _T_13 = eq(_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 131:22] node _T_14 = gt(SourceIdSet, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 132:34] node _T_15 = gt(SourceIdClear, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 133:36] module TLXbar_cbus_in_i1_o1_a32d64s2k1z4u : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 159:18] invalidate in[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.data, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.mask, anonIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.address, anonIn.a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.source, anonIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.size, anonIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.param, anonIn.a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.opcode, anonIn.a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.valid, anonIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect anonIn.a.ready, in[0].a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:55] connect in[0].a.bits.source, _in_0_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:29] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_1.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_3.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 180:23] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 181:26] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_9.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_11.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.bits, _WIRE_12.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, _WIRE_12.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.ready, _WIRE_12.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 191:23] wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.bits, _WIRE_14.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.valid, _WIRE_14.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.ready, _WIRE_14.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 192:26] connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.data, in[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.denied, in[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.sink, in[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.source, in[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.size, in[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.param, in[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.opcode, in[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.valid, in[0].d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect in[0].d.ready, anonIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 156:69] connect anonIn.d.bits.source, _anonIn_d_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 197:32] wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.bits, _WIRE_16.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.valid, _WIRE_16.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.ready, _WIRE_16.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_17.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_17.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_17.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.bits, _WIRE_18.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.valid, _WIRE_18.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.ready, _WIRE_18.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_19.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_19.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_19.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.bits, _WIRE_20.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.valid, _WIRE_20.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.ready, _WIRE_20.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 210:23] wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.bits, _WIRE_22.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.valid, _WIRE_22.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, _WIRE_22.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 211:26] wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 216:19] invalidate out[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.data, out[0].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.mask, out[0].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.fetch, out[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.secure, out[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.privileged, out[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.writealloc, out[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.readalloc, out[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.modifiable, out[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.bufferable, out[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.address, out[0].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.source, out[0].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.size, out[0].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.param, out[0].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.opcode, out[0].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.valid, out[0].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[0].a.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.bits, _WIRE_24.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.valid, _WIRE_24.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.ready, _WIRE_24.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_25.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.bits, _WIRE_26.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.valid, _WIRE_26.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.ready, _WIRE_26.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_27.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.bits, _WIRE_28.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.valid, _WIRE_28.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.ready, _WIRE_28.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.bits, _WIRE_30.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.valid, _WIRE_30.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.ready, _WIRE_30.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.bits, _WIRE_32.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.valid, _WIRE_32.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.ready, _WIRE_32.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_33.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.bits, _WIRE_34.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.valid, _WIRE_34.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.ready, _WIRE_34.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_35.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.bits, _WIRE_36.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.valid, _WIRE_36.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.ready, _WIRE_36.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.bits, _WIRE_38.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.valid, _WIRE_38.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.ready, _WIRE_38.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.valid, anonOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect anonOut.d.ready, out[0].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[0].d.bits.sink, _out_0_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.bits, _WIRE_40.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.valid, _WIRE_40.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.ready, _WIRE_40.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_41.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_41.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_41.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.bits, _WIRE_42.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.valid, _WIRE_42.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.ready, _WIRE_42.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_43.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_43.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_43.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.bits, _WIRE_44.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.valid, _WIRE_44.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.ready, _WIRE_44.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.bits, _WIRE_46.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.valid, _WIRE_46.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.ready, _WIRE_46.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.bits, _addressC_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.valid, _addressC_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.ready, _addressC_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_1 = cvt(_requestAIO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_3 = asSInt(_requestAIO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_1 = cvt(_requestCIO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_3 = asSInt(_requestCIO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestDOI_T = shr(out[0].d.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 102:36] node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsAOI_filtered[0].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect in[0].a.ready, portsAOI_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.data, out[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.source, out[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.size, out[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.param, out[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect out[0].d.ready, portsDIO_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] connect out[0].a, portsAOI_filtered[0] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_49.bits, _WIRE_48.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_49.valid, _WIRE_48.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_49.ready, _WIRE_48.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_49.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_50.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_50.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_50.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_51.bits, _WIRE_50.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_51.valid, _WIRE_50.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_51.ready, _WIRE_50.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_51.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.bits, _WIRE_52.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.valid, _WIRE_52.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.ready, _WIRE_52.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_53.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect in[0].d, portsDIO_filtered[0] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] connect portsBIO_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] module TLXbar_cbus_out_i1_o7_a32d64s2k1z4u : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut_1.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_1.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut_2.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_2.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut_3.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_3.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut_4.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_4.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut_5.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut_5.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out_0, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_1, x1_anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_2, x1_anonOut_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_3, x1_anonOut_2 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_4, x1_anonOut_3 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_5, x1_anonOut_4 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_6, x1_anonOut_5 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 159:18] invalidate in[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.data, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.mask, anonIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.address, anonIn.a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.source, anonIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.size, anonIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.param, anonIn.a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.opcode, anonIn.a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.valid, anonIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect anonIn.a.ready, in[0].a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:55] connect in[0].a.bits.source, _in_0_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:29] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_1.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_3.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 180:23] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 181:26] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_9.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_11.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.bits, _WIRE_12.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, _WIRE_12.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.ready, _WIRE_12.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 191:23] wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.bits, _WIRE_14.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.valid, _WIRE_14.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.ready, _WIRE_14.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 192:26] connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.data, in[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.denied, in[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.sink, in[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.source, in[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.size, in[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.param, in[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.opcode, in[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.valid, in[0].d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect in[0].d.ready, anonIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 156:69] connect anonIn.d.bits.source, _anonIn_d_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 197:32] wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.bits, _WIRE_16.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.valid, _WIRE_16.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.ready, _WIRE_16.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_17.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_17.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_17.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.bits, _WIRE_18.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.valid, _WIRE_18.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.ready, _WIRE_18.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_19.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_19.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_19.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.bits, _WIRE_20.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.valid, _WIRE_20.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.ready, _WIRE_20.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 210:23] wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.bits, _WIRE_22.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.valid, _WIRE_22.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, _WIRE_22.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 211:26] wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[7] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 216:19] invalidate out[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.data, out[0].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.mask, out[0].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.address, out[0].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.source, out[0].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.size, out[0].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.param, out[0].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.opcode, out[0].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.valid, out[0].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[0].a.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.bits, _WIRE_24.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.valid, _WIRE_24.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.ready, _WIRE_24.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_25.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.address, UInt<14>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.bits, _WIRE_26.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.valid, _WIRE_26.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.ready, _WIRE_26.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_27.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.bits, _WIRE_28.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.valid, _WIRE_28.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.ready, _WIRE_28.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.address, UInt<14>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.bits, _WIRE_30.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.valid, _WIRE_30.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.ready, _WIRE_30.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.bits, _WIRE_32.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.valid, _WIRE_32.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.ready, _WIRE_32.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_33.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.address, UInt<14>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.bits, _WIRE_34.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.valid, _WIRE_34.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.ready, _WIRE_34.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_35.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.bits, _WIRE_36.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.valid, _WIRE_36.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.ready, _WIRE_36.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.address, UInt<14>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.bits, _WIRE_38.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.valid, _WIRE_38.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.ready, _WIRE_38.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.valid, anonOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect anonOut.d.ready, out[0].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[0].d.bits.sink, _out_0_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.bits, _WIRE_40.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.valid, _WIRE_40.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.ready, _WIRE_40.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_41.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_41.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_41.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.bits, _WIRE_42.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.valid, _WIRE_42.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.ready, _WIRE_42.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_43.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_43.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_43.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.bits, _WIRE_44.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.valid, _WIRE_44.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.ready, _WIRE_44.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.bits, _WIRE_46.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.valid, _WIRE_46.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.ready, _WIRE_46.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] invalidate out[1].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[1].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[1].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[1].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[1].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[1].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[1].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.data, out[1].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.mask, out[1].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.user.amba_prot.fetch, out[1].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.user.amba_prot.secure, out[1].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.user.amba_prot.privileged, out[1].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.user.amba_prot.writealloc, out[1].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.user.amba_prot.readalloc, out[1].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.user.amba_prot.modifiable, out[1].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.user.amba_prot.bufferable, out[1].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.address, out[1].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.source, out[1].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.size, out[1].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.param, out[1].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.valid, out[1].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[1].a.ready, x1_anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_49.bits, _WIRE_48.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_49.valid, _WIRE_48.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_49.ready, _WIRE_48.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_49.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_51.bits, _WIRE_50.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_51.valid, _WIRE_50.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_51.ready, _WIRE_50.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_51.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.bits, _WIRE_52.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.valid, _WIRE_52.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.ready, _WIRE_52.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.bits, _WIRE_54.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.valid, _WIRE_54.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.ready, _WIRE_54.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_57.bits, _WIRE_56.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_57.valid, _WIRE_56.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_57.ready, _WIRE_56.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_57.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_59.bits, _WIRE_58.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_59.valid, _WIRE_58.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_59.ready, _WIRE_58.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_59.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.bits, _WIRE_60.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.valid, _WIRE_60.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.ready, _WIRE_60.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.bits, _WIRE_62.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.valid, _WIRE_62.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.ready, _WIRE_62.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.data, x1_anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.denied, x1_anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.sink, x1_anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.source, x1_anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.size, x1_anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.param, x1_anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.valid, x1_anonOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect x1_anonOut.d.ready, out[1].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[1].d.bits.sink, _out_1_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_64.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_64.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_64.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_65.bits, _WIRE_64.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_65.valid, _WIRE_64.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_65.ready, _WIRE_64.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_65.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_65.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_65.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_66.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_66.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_66.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_67.bits, _WIRE_66.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_67.valid, _WIRE_66.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_67.ready, _WIRE_66.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_67.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_67.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_67.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_68.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_68.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_68.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.bits, _WIRE_68.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.valid, _WIRE_68.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.ready, _WIRE_68.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_70.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_70.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_70.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.bits, _WIRE_70.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.valid, _WIRE_70.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.ready, _WIRE_70.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] invalidate out[2].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[2].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[2].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[2].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[2].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[2].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[2].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] connect x1_anonOut_1.a.bits.corrupt, out[2].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_1.a.bits.data, out[2].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_1.a.bits.mask, out[2].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_1.a.bits.address, out[2].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_1.a.bits.source, out[2].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_1.a.bits.size, out[2].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_1.a.bits.param, out[2].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_1.a.bits.opcode, out[2].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_1.a.valid, out[2].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[2].a.ready, x1_anonOut_1.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_72.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_73.bits, _WIRE_72.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_73.valid, _WIRE_72.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_73.ready, _WIRE_72.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_73.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_73.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_73.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_73.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_73.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_73.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_73.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_73.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_73.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_73.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.bits.address, UInt<26>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_74.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_75.bits, _WIRE_74.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_75.valid, _WIRE_74.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_75.ready, _WIRE_74.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_75.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_75.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_75.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_75.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_75.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_75.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_75.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_75.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_75.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_75.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_77.bits, _WIRE_76.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_77.valid, _WIRE_76.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_77.ready, _WIRE_76.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_77.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.address, UInt<26>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_79.bits, _WIRE_78.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_79.valid, _WIRE_78.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_79.ready, _WIRE_78.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_79.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_80.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_81.bits, _WIRE_80.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_81.valid, _WIRE_80.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_81.ready, _WIRE_80.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_81.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_81.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_82 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_82.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_82.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_82.bits.address, UInt<26>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_82.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_82.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_82.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_82.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_82.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_82.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_83 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_83.bits, _WIRE_82.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_83.valid, _WIRE_82.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_83.ready, _WIRE_82.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_83.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_83.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_83.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_83.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_83.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_83.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_83.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_83.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_83.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_84 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_84.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_85 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_85.bits, _WIRE_84.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_85.valid, _WIRE_84.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_85.ready, _WIRE_84.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_85.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_86 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_86.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_86.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_86.bits.address, UInt<26>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_86.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_86.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_86.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_86.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_86.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_86.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_87 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_87.bits, _WIRE_86.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_87.valid, _WIRE_86.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_87.ready, _WIRE_86.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_87.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[2].d.bits.corrupt, x1_anonOut_1.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[2].d.bits.data, x1_anonOut_1.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[2].d.bits.denied, x1_anonOut_1.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[2].d.bits.sink, x1_anonOut_1.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[2].d.bits.source, x1_anonOut_1.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[2].d.bits.size, x1_anonOut_1.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[2].d.bits.param, x1_anonOut_1.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[2].d.bits.opcode, x1_anonOut_1.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[2].d.valid, x1_anonOut_1.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect x1_anonOut_1.d.ready, out[2].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_2_d_bits_sink_T = or(x1_anonOut_1.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[2].d.bits.sink, _out_2_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_88 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_88.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_88.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_88.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_89 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_89.bits, _WIRE_88.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_89.valid, _WIRE_88.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_89.ready, _WIRE_88.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_89.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_89.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_89.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_90 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_90.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_90.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_90.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_91 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_91.bits, _WIRE_90.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_91.valid, _WIRE_90.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_91.ready, _WIRE_90.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_91.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_91.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_91.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_92 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_92.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_92.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_92.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_93 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_93.bits, _WIRE_92.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_93.valid, _WIRE_92.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_93.ready, _WIRE_92.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_93.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_94 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_94.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_94.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_94.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_95 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_95.bits, _WIRE_94.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_95.valid, _WIRE_94.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_95.ready, _WIRE_94.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_95.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] invalidate out[3].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[3].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[3].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[3].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[3].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[3].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[3].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] connect x1_anonOut_2.a.bits.corrupt, out[3].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.data, out[3].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.mask, out[3].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.address, out[3].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.source, out[3].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.size, out[3].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.param, out[3].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.bits.opcode, out[3].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_2.a.valid, out[3].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[3].a.ready, x1_anonOut_2.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_96 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_96.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_97 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_97.bits, _WIRE_96.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_97.valid, _WIRE_96.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_97.ready, _WIRE_96.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_97.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_97.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_97.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_97.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_97.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_97.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_97.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_97.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_97.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_97.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_98 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.bits.address, UInt<28>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_98.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_99 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_99.bits, _WIRE_98.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_99.valid, _WIRE_98.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_99.ready, _WIRE_98.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_99.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_99.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_99.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_99.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_99.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_99.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_99.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_99.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_99.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_99.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_100 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_100.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_101 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_101.bits, _WIRE_100.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_101.valid, _WIRE_100.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_101.ready, _WIRE_100.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_101.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_102 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.bits.address, UInt<28>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_102.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_103 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_103.bits, _WIRE_102.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_103.valid, _WIRE_102.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_103.ready, _WIRE_102.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_103.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_104 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_104.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_105 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_105.bits, _WIRE_104.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_105.valid, _WIRE_104.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_105.ready, _WIRE_104.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_105.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_105.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_106 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.address, UInt<28>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_106.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_107 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_107.bits, _WIRE_106.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_107.valid, _WIRE_106.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_107.ready, _WIRE_106.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_107.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_107.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_108 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_108.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_109 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_109.bits, _WIRE_108.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_109.valid, _WIRE_108.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_109.ready, _WIRE_108.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_109.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_110 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.address, UInt<28>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_110.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_111 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_111.bits, _WIRE_110.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_111.valid, _WIRE_110.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_111.ready, _WIRE_110.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_111.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[3].d.bits.corrupt, x1_anonOut_2.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[3].d.bits.data, x1_anonOut_2.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[3].d.bits.denied, x1_anonOut_2.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[3].d.bits.sink, x1_anonOut_2.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[3].d.bits.source, x1_anonOut_2.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[3].d.bits.size, x1_anonOut_2.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[3].d.bits.param, x1_anonOut_2.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[3].d.bits.opcode, x1_anonOut_2.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[3].d.valid, x1_anonOut_2.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect x1_anonOut_2.d.ready, out[3].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_3_d_bits_sink_T = or(x1_anonOut_2.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[3].d.bits.sink, _out_3_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_112 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_112.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_112.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_112.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_113 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_113.bits, _WIRE_112.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_113.valid, _WIRE_112.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_113.ready, _WIRE_112.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_113.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_113.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_113.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_114 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_114.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_114.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_114.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_115 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_115.bits, _WIRE_114.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_115.valid, _WIRE_114.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_115.ready, _WIRE_114.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_115.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_115.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_115.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_116 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_116.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_116.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_116.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_117 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_117.bits, _WIRE_116.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_117.valid, _WIRE_116.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_117.ready, _WIRE_116.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_117.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_118 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_118.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_118.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_118.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_119 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_119.bits, _WIRE_118.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_119.valid, _WIRE_118.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_119.ready, _WIRE_118.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_119.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] invalidate out[4].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[4].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[4].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[4].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[4].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[4].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[4].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] connect x1_anonOut_3.a.bits.corrupt, out[4].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_3.a.bits.data, out[4].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_3.a.bits.mask, out[4].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_3.a.bits.address, out[4].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_3.a.bits.source, out[4].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_3.a.bits.size, out[4].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_3.a.bits.param, out[4].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_3.a.bits.opcode, out[4].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_3.a.valid, out[4].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[4].a.ready, x1_anonOut_3.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_120 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_120.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_120.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_120.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_120.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_120.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_120.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_120.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_120.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_120.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_120.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_121 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_121.bits, _WIRE_120.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_121.valid, _WIRE_120.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_121.ready, _WIRE_120.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_121.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_121.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_121.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_121.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_121.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_121.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_121.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_121.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_121.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_121.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_122 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_122.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_122.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_122.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_122.bits.address, UInt<12>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_122.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_122.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_122.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_122.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_122.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_122.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_123 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_123.bits, _WIRE_122.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_123.valid, _WIRE_122.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_123.ready, _WIRE_122.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_123.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_123.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_123.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_123.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_123.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_123.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_123.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_123.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_123.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_123.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_124 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_124.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_124.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_124.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_124.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_124.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_124.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_124.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_124.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_124.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_124.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_125 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_125.bits, _WIRE_124.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_125.valid, _WIRE_124.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_125.ready, _WIRE_124.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_125.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_126 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_126.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_126.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_126.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_126.bits.address, UInt<12>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_126.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_126.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_126.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_126.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_126.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_126.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_127 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_127.bits, _WIRE_126.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_127.valid, _WIRE_126.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_127.ready, _WIRE_126.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_127.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_128 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_128.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_129 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_129.bits, _WIRE_128.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_129.valid, _WIRE_128.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_129.ready, _WIRE_128.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_129.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_129.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_129.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_129.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_129.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_129.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_129.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_129.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_129.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_129.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_129.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_129.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_129.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_129.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_129.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_129.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_130 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_130.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_130.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_130.bits.address, UInt<12>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_130.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_130.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_130.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_130.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_130.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_130.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_131 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_131.bits, _WIRE_130.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_131.valid, _WIRE_130.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_131.ready, _WIRE_130.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_131.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_131.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_131.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_131.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_131.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_131.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_131.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_131.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_131.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_132 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_132.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_133 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_133.bits, _WIRE_132.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_133.valid, _WIRE_132.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_133.ready, _WIRE_132.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_133.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_134 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_134.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_134.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_134.bits.address, UInt<12>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_134.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_134.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_134.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_134.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_134.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_134.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_135 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_135.bits, _WIRE_134.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_135.valid, _WIRE_134.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_135.ready, _WIRE_134.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_135.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[4].d.bits.corrupt, x1_anonOut_3.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[4].d.bits.data, x1_anonOut_3.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[4].d.bits.denied, x1_anonOut_3.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[4].d.bits.sink, x1_anonOut_3.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[4].d.bits.source, x1_anonOut_3.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[4].d.bits.size, x1_anonOut_3.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[4].d.bits.param, x1_anonOut_3.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[4].d.bits.opcode, x1_anonOut_3.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[4].d.valid, x1_anonOut_3.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect x1_anonOut_3.d.ready, out[4].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_4_d_bits_sink_T = or(x1_anonOut_3.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[4].d.bits.sink, _out_4_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_136 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_136.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_136.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_136.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_137 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_137.bits, _WIRE_136.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_137.valid, _WIRE_136.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_137.ready, _WIRE_136.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_137.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_137.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_137.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_138 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_138.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_138.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_138.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_139 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_139.bits, _WIRE_138.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_139.valid, _WIRE_138.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_139.ready, _WIRE_138.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_139.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_139.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_139.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_140 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_140.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_140.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_140.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_141 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_141.bits, _WIRE_140.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_141.valid, _WIRE_140.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_141.ready, _WIRE_140.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_141.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_142 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_142.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_142.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_142.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_143 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_143.bits, _WIRE_142.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_143.valid, _WIRE_142.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_143.ready, _WIRE_142.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_143.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] invalidate out[5].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[5].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[5].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[5].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[5].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[5].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[5].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] connect x1_anonOut_4.a.bits.corrupt, out[5].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_4.a.bits.data, out[5].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_4.a.bits.mask, out[5].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_4.a.bits.address, out[5].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_4.a.bits.source, out[5].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_4.a.bits.size, out[5].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_4.a.bits.param, out[5].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_4.a.bits.opcode, out[5].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_4.a.valid, out[5].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[5].a.ready, x1_anonOut_4.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_144 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_144.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_144.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_144.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_144.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_144.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_144.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_144.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_144.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_144.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_144.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_145 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_145.bits, _WIRE_144.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_145.valid, _WIRE_144.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_145.ready, _WIRE_144.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_145.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_145.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_145.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_145.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_145.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_145.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_145.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_145.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_145.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_145.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_146 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_146.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_146.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_146.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_146.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_146.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_146.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_146.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_146.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_146.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_146.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_147 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_147.bits, _WIRE_146.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_147.valid, _WIRE_146.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_147.ready, _WIRE_146.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_147.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_147.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_147.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_147.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_147.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_147.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_147.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_147.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_147.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_147.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_148 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_148.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_148.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_148.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_148.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_148.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_148.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_148.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_148.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_148.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_148.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_149 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_149.bits, _WIRE_148.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_149.valid, _WIRE_148.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_149.ready, _WIRE_148.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_149.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_150 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_150.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_150.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_150.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_150.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_150.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_150.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_150.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_150.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_150.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_150.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_151 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_151.bits, _WIRE_150.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_151.valid, _WIRE_150.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_151.ready, _WIRE_150.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_151.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_152 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_152.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_152.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_152.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_152.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_152.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_152.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_152.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_152.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_152.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_152.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_152.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_152.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_152.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_152.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_152.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_152.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_153 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_153.bits, _WIRE_152.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_153.valid, _WIRE_152.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_153.ready, _WIRE_152.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_153.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_153.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_153.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_153.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_153.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_153.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_153.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_153.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_153.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_153.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_153.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_153.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_153.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_153.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_153.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_153.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_154 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_154.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_154.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_154.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_154.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_154.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_154.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_154.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_154.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_154.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_155 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_155.bits, _WIRE_154.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_155.valid, _WIRE_154.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_155.ready, _WIRE_154.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_155.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_155.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_155.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_155.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_155.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_155.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_155.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_155.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_155.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_156 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_156.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_156.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_156.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_156.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_156.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_156.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_156.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_156.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_156.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_156.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_156.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_156.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_156.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_156.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_156.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_156.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_157 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_157.bits, _WIRE_156.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_157.valid, _WIRE_156.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_157.ready, _WIRE_156.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_157.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_158 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_158.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_158.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_158.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_158.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_158.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_158.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_158.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_158.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_158.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_159 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_159.bits, _WIRE_158.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_159.valid, _WIRE_158.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_159.ready, _WIRE_158.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_159.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[5].d.bits.corrupt, x1_anonOut_4.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[5].d.bits.data, x1_anonOut_4.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[5].d.bits.denied, x1_anonOut_4.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[5].d.bits.sink, x1_anonOut_4.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[5].d.bits.source, x1_anonOut_4.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[5].d.bits.size, x1_anonOut_4.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[5].d.bits.param, x1_anonOut_4.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[5].d.bits.opcode, x1_anonOut_4.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[5].d.valid, x1_anonOut_4.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect x1_anonOut_4.d.ready, out[5].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_5_d_bits_sink_T = or(x1_anonOut_4.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[5].d.bits.sink, _out_5_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_160 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_160.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_160.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_160.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_161 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_161.bits, _WIRE_160.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_161.valid, _WIRE_160.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_161.ready, _WIRE_160.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_161.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_161.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_161.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_162 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_162.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_162.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_162.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_163 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_163.bits, _WIRE_162.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_163.valid, _WIRE_162.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_163.ready, _WIRE_162.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_163.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_163.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_163.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_164 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_164.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_164.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_164.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_165 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_165.bits, _WIRE_164.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_165.valid, _WIRE_164.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_165.ready, _WIRE_164.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_165.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_166 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_166.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_166.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_166.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_167 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_167.bits, _WIRE_166.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_167.valid, _WIRE_166.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_167.ready, _WIRE_166.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_167.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] invalidate out[6].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[6].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[6].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[6].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[6].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[6].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[6].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] connect x1_anonOut_5.a.bits.corrupt, out[6].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_5.a.bits.data, out[6].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_5.a.bits.mask, out[6].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_5.a.bits.address, out[6].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_5.a.bits.source, out[6].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_5.a.bits.size, out[6].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_5.a.bits.param, out[6].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_5.a.bits.opcode, out[6].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut_5.a.valid, out[6].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[6].a.ready, x1_anonOut_5.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_168 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_168.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_168.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_168.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_168.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_168.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_168.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_168.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_168.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_168.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_168.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_169 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_169.bits, _WIRE_168.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_169.valid, _WIRE_168.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_169.ready, _WIRE_168.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_169.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_169.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_169.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_169.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_169.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_169.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_169.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_169.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_169.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_169.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_170 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_170.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_170.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_170.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_170.bits.address, UInt<17>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_170.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_170.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_170.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_170.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_170.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_170.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_171 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_171.bits, _WIRE_170.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_171.valid, _WIRE_170.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_171.ready, _WIRE_170.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_171.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_171.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_171.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_171.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_171.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_171.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_171.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_171.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_171.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_171.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_172 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_172.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_172.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_172.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_172.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_172.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_172.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_172.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_172.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_172.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_172.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_173 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_173.bits, _WIRE_172.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_173.valid, _WIRE_172.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_173.ready, _WIRE_172.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_173.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_174 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_174.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_174.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_174.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_174.bits.address, UInt<17>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_174.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_174.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_174.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_174.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_174.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_174.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_175 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_175.bits, _WIRE_174.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_175.valid, _WIRE_174.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_175.ready, _WIRE_174.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_175.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_176 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_176.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_176.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_176.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_176.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_176.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_176.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_176.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_176.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_176.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_176.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_176.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_176.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_176.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_176.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_176.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_176.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_177 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_177.bits, _WIRE_176.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_177.valid, _WIRE_176.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_177.ready, _WIRE_176.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_177.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_177.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_177.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_177.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_177.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_177.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_177.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_177.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_177.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_177.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_177.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_177.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_177.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_177.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_177.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_177.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_178 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_178.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_178.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_178.bits.address, UInt<17>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_178.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_178.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_178.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_178.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_178.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_178.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_179 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_179.bits, _WIRE_178.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_179.valid, _WIRE_178.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_179.ready, _WIRE_178.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_179.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_179.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_179.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_179.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_179.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_179.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_179.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_179.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_179.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_180 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_180.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_180.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_180.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_180.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_180.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_180.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_180.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_180.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_180.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_180.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_180.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_180.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_180.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_180.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_180.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_180.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_181 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_181.bits, _WIRE_180.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_181.valid, _WIRE_180.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_181.ready, _WIRE_180.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_181.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_182 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_182.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_182.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_182.bits.address, UInt<17>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_182.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_182.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_182.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_182.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_182.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_182.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_183 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_183.bits, _WIRE_182.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_183.valid, _WIRE_182.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_183.ready, _WIRE_182.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_183.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[6].d.bits.corrupt, x1_anonOut_5.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[6].d.bits.data, x1_anonOut_5.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[6].d.bits.denied, x1_anonOut_5.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[6].d.bits.sink, x1_anonOut_5.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[6].d.bits.source, x1_anonOut_5.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[6].d.bits.size, x1_anonOut_5.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[6].d.bits.param, x1_anonOut_5.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[6].d.bits.opcode, x1_anonOut_5.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[6].d.valid, x1_anonOut_5.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect x1_anonOut_5.d.ready, out[6].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_6_d_bits_sink_T = or(x1_anonOut_5.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[6].d.bits.sink, _out_6_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_184 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_184.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_184.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_184.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_185 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_185.bits, _WIRE_184.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_185.valid, _WIRE_184.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_185.ready, _WIRE_184.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_185.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_185.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_185.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_186 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_186.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_186.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_186.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_187 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_187.bits, _WIRE_186.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_187.valid, _WIRE_186.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_187.ready, _WIRE_186.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_187.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_187.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_187.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_188 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_188.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_188.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_188.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_189 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_189.bits, _WIRE_188.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_189.valid, _WIRE_188.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_189.ready, _WIRE_188.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_189.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_190 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_190.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_190.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_190.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_191 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_191.bits, _WIRE_190.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_191.valid, _WIRE_190.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_191.ready, _WIRE_190.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_191.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.bits, _addressC_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.valid, _addressC_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.ready, _addressC_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _requestAIO_T = xor(in[0].a.bits.address, UInt<13>(0h1000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_1 = cvt(_requestAIO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<33>(0h9a011000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_3 = asSInt(_requestAIO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<29>(0h10000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_6 = cvt(_requestAIO_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<33>(0h9a000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_8 = asSInt(_requestAIO_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestAIO_T_10 = xor(in[0].a.bits.address, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_11 = cvt(_requestAIO_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<33>(0h9a010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_13 = asSInt(_requestAIO_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_0_2 = or(UInt<1>(0h0), _requestAIO_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestAIO_T_15 = xor(in[0].a.bits.address, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_16 = cvt(_requestAIO_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_17 = and(_requestAIO_T_16, asSInt(UInt<33>(0h98000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_18 = asSInt(_requestAIO_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_19 = eq(_requestAIO_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_0_3 = or(UInt<1>(0h0), _requestAIO_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestAIO_T_20 = xor(in[0].a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_21 = cvt(_requestAIO_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_22 = and(_requestAIO_T_21, asSInt(UInt<33>(0h9a011000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_23 = asSInt(_requestAIO_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_24 = eq(_requestAIO_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_0_4 = or(UInt<1>(0h0), _requestAIO_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestAIO_T_25 = xor(in[0].a.bits.address, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_26 = cvt(_requestAIO_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_27 = and(_requestAIO_T_26, asSInt(UInt<33>(0h9a000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_28 = asSInt(_requestAIO_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_29 = eq(_requestAIO_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_0_5 = or(UInt<1>(0h0), _requestAIO_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestAIO_T_30 = xor(in[0].a.bits.address, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_31 = cvt(_requestAIO_T_30) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_32 = and(_requestAIO_T_31, asSInt(UInt<33>(0h9a010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_33 = asSInt(_requestAIO_T_32) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_34 = eq(_requestAIO_T_33, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_0_6 = or(UInt<1>(0h0), _requestAIO_T_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_1 = cvt(_requestCIO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_3 = asSInt(_requestCIO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_6 = cvt(_requestCIO_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_8 = asSInt(_requestCIO_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] node _requestCIO_T_10 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_11 = cvt(_requestCIO_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_12 = and(_requestCIO_T_11, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_13 = asSInt(_requestCIO_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_14 = eq(_requestCIO_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_2 = or(UInt<1>(0h1), _requestCIO_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] node _requestCIO_T_15 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_16 = cvt(_requestCIO_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_17 = and(_requestCIO_T_16, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_18 = asSInt(_requestCIO_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_19 = eq(_requestCIO_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_3 = or(UInt<1>(0h1), _requestCIO_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] node _requestCIO_T_20 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_21 = cvt(_requestCIO_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_22 = and(_requestCIO_T_21, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_23 = asSInt(_requestCIO_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_24 = eq(_requestCIO_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_4 = or(UInt<1>(0h1), _requestCIO_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] node _requestCIO_T_25 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_26 = cvt(_requestCIO_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_27 = and(_requestCIO_T_26, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_28 = asSInt(_requestCIO_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_29 = eq(_requestCIO_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_5 = or(UInt<1>(0h1), _requestCIO_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] node _requestCIO_T_30 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_31 = cvt(_requestCIO_T_30) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_32 = and(_requestCIO_T_31, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_33 = asSInt(_requestCIO_T_32) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_34 = eq(_requestCIO_T_33, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_6 = or(UInt<1>(0h1), _requestCIO_T_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestBOI_1_0 = and(_requestBOI_T_8, _requestBOI_T_9) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] wire _requestBOI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_5.bits, _requestBOI_WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_5.valid, _requestBOI_WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_5.ready, _requestBOI_WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _requestBOI_uncommonBits_T_2 = or(_requestBOI_WIRE_5.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestBOI_uncommonBits_2 = bits(_requestBOI_uncommonBits_T_2, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestBOI_T_10 = shr(_requestBOI_WIRE_5.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestBOI_T_11 = eq(_requestBOI_T_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestBOI_T_12 = leq(UInt<1>(0h0), requestBOI_uncommonBits_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestBOI_T_13 = and(_requestBOI_T_11, _requestBOI_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestBOI_T_14 = leq(requestBOI_uncommonBits_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestBOI_2_0 = and(_requestBOI_T_13, _requestBOI_T_14) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] wire _requestBOI_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_7.bits, _requestBOI_WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_7.valid, _requestBOI_WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_7.ready, _requestBOI_WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _requestBOI_uncommonBits_T_3 = or(_requestBOI_WIRE_7.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestBOI_uncommonBits_3 = bits(_requestBOI_uncommonBits_T_3, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestBOI_T_15 = shr(_requestBOI_WIRE_7.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestBOI_T_16 = eq(_requestBOI_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestBOI_T_17 = leq(UInt<1>(0h0), requestBOI_uncommonBits_3) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestBOI_T_18 = and(_requestBOI_T_16, _requestBOI_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestBOI_T_19 = leq(requestBOI_uncommonBits_3, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestBOI_3_0 = and(_requestBOI_T_18, _requestBOI_T_19) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] wire _requestBOI_WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_8.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_8.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_9.bits, _requestBOI_WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_9.valid, _requestBOI_WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_9.ready, _requestBOI_WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _requestBOI_uncommonBits_T_4 = or(_requestBOI_WIRE_9.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestBOI_uncommonBits_4 = bits(_requestBOI_uncommonBits_T_4, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestBOI_T_20 = shr(_requestBOI_WIRE_9.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestBOI_T_21 = eq(_requestBOI_T_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestBOI_T_22 = leq(UInt<1>(0h0), requestBOI_uncommonBits_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestBOI_T_23 = and(_requestBOI_T_21, _requestBOI_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestBOI_T_24 = leq(requestBOI_uncommonBits_4, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestBOI_4_0 = and(_requestBOI_T_23, _requestBOI_T_24) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] wire _requestBOI_WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_10.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_10.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_10.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_10.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_10.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_10.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_10.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_10.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_11.bits, _requestBOI_WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_11.valid, _requestBOI_WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_11.ready, _requestBOI_WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _requestBOI_uncommonBits_T_5 = or(_requestBOI_WIRE_11.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestBOI_uncommonBits_5 = bits(_requestBOI_uncommonBits_T_5, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestBOI_T_25 = shr(_requestBOI_WIRE_11.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestBOI_T_26 = eq(_requestBOI_T_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestBOI_T_27 = leq(UInt<1>(0h0), requestBOI_uncommonBits_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestBOI_T_28 = and(_requestBOI_T_26, _requestBOI_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestBOI_T_29 = leq(requestBOI_uncommonBits_5, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestBOI_5_0 = and(_requestBOI_T_28, _requestBOI_T_29) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] wire _requestBOI_WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_12.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_12.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_12.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_12.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_12.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_12.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_12.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_12.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_12.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_12.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_13.bits, _requestBOI_WIRE_12.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_13.valid, _requestBOI_WIRE_12.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_13.ready, _requestBOI_WIRE_12.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _requestBOI_uncommonBits_T_6 = or(_requestBOI_WIRE_13.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestBOI_uncommonBits_6 = bits(_requestBOI_uncommonBits_T_6, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestBOI_T_30 = shr(_requestBOI_WIRE_13.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestBOI_T_31 = eq(_requestBOI_T_30, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestBOI_T_32 = leq(UInt<1>(0h0), requestBOI_uncommonBits_6) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestBOI_T_33 = and(_requestBOI_T_31, _requestBOI_T_32) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestBOI_T_34 = leq(requestBOI_uncommonBits_6, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestBOI_6_0 = and(_requestBOI_T_33, _requestBOI_T_34) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestDOI_T = shr(out[0].d.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] node _requestDOI_uncommonBits_T_1 = or(out[1].d.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestDOI_T_5 = shr(out[1].d.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestDOI_1_0 = and(_requestDOI_T_8, _requestDOI_T_9) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] node _requestDOI_uncommonBits_T_2 = or(out[2].d.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestDOI_uncommonBits_2 = bits(_requestDOI_uncommonBits_T_2, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestDOI_T_10 = shr(out[2].d.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestDOI_T_11 = eq(_requestDOI_T_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestDOI_T_12 = leq(UInt<1>(0h0), requestDOI_uncommonBits_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestDOI_T_13 = and(_requestDOI_T_11, _requestDOI_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestDOI_T_14 = leq(requestDOI_uncommonBits_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestDOI_2_0 = and(_requestDOI_T_13, _requestDOI_T_14) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] node _requestDOI_uncommonBits_T_3 = or(out[3].d.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestDOI_uncommonBits_3 = bits(_requestDOI_uncommonBits_T_3, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestDOI_T_15 = shr(out[3].d.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestDOI_T_16 = eq(_requestDOI_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestDOI_T_17 = leq(UInt<1>(0h0), requestDOI_uncommonBits_3) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestDOI_T_18 = and(_requestDOI_T_16, _requestDOI_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestDOI_T_19 = leq(requestDOI_uncommonBits_3, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestDOI_3_0 = and(_requestDOI_T_18, _requestDOI_T_19) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] node _requestDOI_uncommonBits_T_4 = or(out[4].d.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestDOI_uncommonBits_4 = bits(_requestDOI_uncommonBits_T_4, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestDOI_T_20 = shr(out[4].d.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestDOI_T_21 = eq(_requestDOI_T_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestDOI_T_22 = leq(UInt<1>(0h0), requestDOI_uncommonBits_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestDOI_T_23 = and(_requestDOI_T_21, _requestDOI_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestDOI_T_24 = leq(requestDOI_uncommonBits_4, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestDOI_4_0 = and(_requestDOI_T_23, _requestDOI_T_24) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] node _requestDOI_uncommonBits_T_5 = or(out[5].d.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestDOI_uncommonBits_5 = bits(_requestDOI_uncommonBits_T_5, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestDOI_T_25 = shr(out[5].d.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestDOI_T_26 = eq(_requestDOI_T_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestDOI_T_27 = leq(UInt<1>(0h0), requestDOI_uncommonBits_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestDOI_T_28 = and(_requestDOI_T_26, _requestDOI_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestDOI_T_29 = leq(requestDOI_uncommonBits_5, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestDOI_5_0 = and(_requestDOI_T_28, _requestDOI_T_29) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] node _requestDOI_uncommonBits_T_6 = or(out[6].d.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestDOI_uncommonBits_6 = bits(_requestDOI_uncommonBits_T_6, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestDOI_T_30 = shr(out[6].d.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestDOI_T_31 = eq(_requestDOI_T_30, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestDOI_T_32 = leq(UInt<1>(0h0), requestDOI_uncommonBits_6) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestDOI_T_33 = and(_requestDOI_T_31, _requestDOI_T_32) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestDOI_T_34 = leq(requestDOI_uncommonBits_6, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestDOI_6_0 = and(_requestDOI_T_33, _requestDOI_T_34) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire _requestEIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_5.bits, _requestEIO_WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_5.valid, _requestEIO_WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_5.ready, _requestEIO_WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire _requestEIO_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_6.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_7.bits, _requestEIO_WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_7.valid, _requestEIO_WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_7.ready, _requestEIO_WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire _requestEIO_WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_8.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_9.bits, _requestEIO_WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_9.valid, _requestEIO_WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_9.ready, _requestEIO_WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire _requestEIO_WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_11.bits, _requestEIO_WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_11.valid, _requestEIO_WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_11.ready, _requestEIO_WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire _requestEIO_WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_12.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_12.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_12.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_13.bits, _requestEIO_WIRE_12.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_13.valid, _requestEIO_WIRE_12.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_13.ready, _requestEIO_WIRE_12.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_5.bits, _beatsBO_WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_5.valid, _beatsBO_WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_5.ready, _beatsBO_WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T_6 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_5.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_7 = bits(_beatsBO_decode_T_6, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_8 = not(_beatsBO_decode_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode_2 = shr(_beatsBO_decode_T_8, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T_2 = bits(_beatsBO_WIRE_5.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata_2 = eq(_beatsBO_opdata_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_2 = mux(UInt<1>(0h0), beatsBO_decode_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_7.bits, _beatsBO_WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_7.valid, _beatsBO_WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_7.ready, _beatsBO_WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T_9 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_7.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_10 = bits(_beatsBO_decode_T_9, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_11 = not(_beatsBO_decode_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode_3 = shr(_beatsBO_decode_T_11, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T_3 = bits(_beatsBO_WIRE_7.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata_3 = eq(_beatsBO_opdata_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_3 = mux(UInt<1>(0h0), beatsBO_decode_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_8.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_8.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_9.bits, _beatsBO_WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_9.valid, _beatsBO_WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_9.ready, _beatsBO_WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T_12 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_9.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_13 = bits(_beatsBO_decode_T_12, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_14 = not(_beatsBO_decode_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode_4 = shr(_beatsBO_decode_T_14, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T_4 = bits(_beatsBO_WIRE_9.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata_4 = eq(_beatsBO_opdata_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_4 = mux(UInt<1>(0h0), beatsBO_decode_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_10.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_10.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_10.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_10.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_10.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_10.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_10.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_10.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_11.bits, _beatsBO_WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_11.valid, _beatsBO_WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_11.ready, _beatsBO_WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T_15 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_11.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_16 = bits(_beatsBO_decode_T_15, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_17 = not(_beatsBO_decode_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode_5 = shr(_beatsBO_decode_T_17, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T_5 = bits(_beatsBO_WIRE_11.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata_5 = eq(_beatsBO_opdata_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_5 = mux(UInt<1>(0h0), beatsBO_decode_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_12.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_12.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_12.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_12.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_12.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_12.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_12.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_12.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_12.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_12.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_13.bits, _beatsBO_WIRE_12.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_13.valid, _beatsBO_WIRE_12.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_13.ready, _beatsBO_WIRE_12.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T_18 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_13.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_19 = bits(_beatsBO_decode_T_18, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_20 = not(_beatsBO_decode_T_19) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode_6 = shr(_beatsBO_decode_T_20, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T_6 = bits(_beatsBO_WIRE_13.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata_6 = eq(_beatsBO_opdata_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_6 = mux(UInt<1>(0h0), beatsBO_decode_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 102:36] node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T_6 = dshl(UInt<6>(0h3f), out[2].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_7 = bits(_beatsDO_decode_T_6, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_8 = not(_beatsDO_decode_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode_2 = shr(_beatsDO_decode_T_8, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata_2 = bits(out[2].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_2 = mux(beatsDO_opdata_2, beatsDO_decode_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T_9 = dshl(UInt<6>(0h3f), out[3].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_10 = bits(_beatsDO_decode_T_9, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_11 = not(_beatsDO_decode_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode_3 = shr(_beatsDO_decode_T_11, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata_3 = bits(out[3].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_3 = mux(beatsDO_opdata_3, beatsDO_decode_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T_12 = dshl(UInt<6>(0h3f), out[4].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_13 = bits(_beatsDO_decode_T_12, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_14 = not(_beatsDO_decode_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode_4 = shr(_beatsDO_decode_T_14, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata_4 = bits(out[4].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_4 = mux(beatsDO_opdata_4, beatsDO_decode_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T_15 = dshl(UInt<6>(0h3f), out[5].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_16 = bits(_beatsDO_decode_T_15, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_17 = not(_beatsDO_decode_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode_5 = shr(_beatsDO_decode_T_17, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata_5 = bits(out[5].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_5 = mux(beatsDO_opdata_5, beatsDO_decode_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T_18 = dshl(UInt<6>(0h3f), out[6].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_19 = bits(_beatsDO_decode_T_18, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_20 = not(_beatsDO_decode_T_19) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode_6 = shr(_beatsDO_decode_T_20, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata_6 = bits(out[6].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_6 = mux(UInt<1>(0h1), beatsDO_decode_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[7] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsAOI_filtered[0].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsAOI_filtered[1].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsAOI_filtered[2].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_2_valid_T = or(requestAIO_0_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_2_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_2_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[2].valid, _portsAOI_filtered_2_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsAOI_filtered[3].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_3_valid_T = or(requestAIO_0_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_3_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_3_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[3].valid, _portsAOI_filtered_3_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsAOI_filtered[4].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_4_valid_T = or(requestAIO_0_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_4_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_4_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[4].valid, _portsAOI_filtered_4_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsAOI_filtered[5].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_5_valid_T = or(requestAIO_0_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_5_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_5_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[5].valid, _portsAOI_filtered_5_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsAOI_filtered[6].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_6_valid_T = or(requestAIO_0_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_6_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_6_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[6].valid, _portsAOI_filtered_6_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_2 = mux(requestAIO_0_2, portsAOI_filtered[2].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_3 = mux(requestAIO_0_3, portsAOI_filtered[3].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_4 = mux(requestAIO_0_4, portsAOI_filtered[4].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_5 = mux(requestAIO_0_5, portsAOI_filtered[5].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_6 = mux(requestAIO_0_6, portsAOI_filtered[6].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_7 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_8 = or(_portsAOI_in_0_a_ready_T_7, _portsAOI_in_0_a_ready_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_9 = or(_portsAOI_in_0_a_ready_T_8, _portsAOI_in_0_a_ready_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_10 = or(_portsAOI_in_0_a_ready_T_9, _portsAOI_in_0_a_ready_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_11 = or(_portsAOI_in_0_a_ready_T_10, _portsAOI_in_0_a_ready_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_12 = or(_portsAOI_in_0_a_ready_T_11, _portsAOI_in_0_a_ready_T_6) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _portsAOI_in_0_a_ready_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_12 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_3.bits, _portsBIO_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_3.valid, _portsBIO_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_3.ready, _portsBIO_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_3.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_3.valid, _portsBIO_filtered_0_valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsBIO_WIRE_3.ready, portsBIO_filtered_1[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_5.bits, _portsBIO_WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_5.valid, _portsBIO_WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_5.ready, _portsBIO_WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered_2[0].bits, _portsBIO_WIRE_5.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T_4 = or(requestBOI_2_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_5 = and(_portsBIO_WIRE_5.valid, _portsBIO_filtered_0_valid_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered_2[0].valid, _portsBIO_filtered_0_valid_T_5 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsBIO_WIRE_5.ready, portsBIO_filtered_2[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_7.bits, _portsBIO_WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_7.valid, _portsBIO_WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_7.ready, _portsBIO_WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered_3[0].bits, _portsBIO_WIRE_7.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T_6 = or(requestBOI_3_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_7 = and(_portsBIO_WIRE_7.valid, _portsBIO_filtered_0_valid_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered_3[0].valid, _portsBIO_filtered_0_valid_T_7 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsBIO_WIRE_7.ready, portsBIO_filtered_3[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_8.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_8.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_9.bits, _portsBIO_WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_9.valid, _portsBIO_WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_9.ready, _portsBIO_WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered_4[0].bits, _portsBIO_WIRE_9.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T_8 = or(requestBOI_4_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_9 = and(_portsBIO_WIRE_9.valid, _portsBIO_filtered_0_valid_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered_4[0].valid, _portsBIO_filtered_0_valid_T_9 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsBIO_WIRE_9.ready, portsBIO_filtered_4[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_10.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_10.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_10.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_10.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_10.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_10.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_10.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_10.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_11.bits, _portsBIO_WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_11.valid, _portsBIO_WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_11.ready, _portsBIO_WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered_5[0].bits, _portsBIO_WIRE_11.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T_10 = or(requestBOI_5_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_11 = and(_portsBIO_WIRE_11.valid, _portsBIO_filtered_0_valid_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered_5[0].valid, _portsBIO_filtered_0_valid_T_11 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsBIO_WIRE_11.ready, portsBIO_filtered_5[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_12.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_12.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_12.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_12.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_12.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_12.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_12.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_12.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_12.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_12.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_13.bits, _portsBIO_WIRE_12.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_13.valid, _portsBIO_WIRE_12.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_13.ready, _portsBIO_WIRE_12.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered_6[0].bits, _portsBIO_WIRE_13.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T_12 = or(requestBOI_6_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_13 = and(_portsBIO_WIRE_13.valid, _portsBIO_filtered_0_valid_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered_6[0].valid, _portsBIO_filtered_0_valid_T_13 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsBIO_WIRE_13.ready, portsBIO_filtered_6[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[7] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsCOI_filtered[2].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_2_valid_T = or(requestCIO_0_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_2_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_2_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[2].valid, _portsCOI_filtered_2_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsCOI_filtered[3].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_3_valid_T = or(requestCIO_0_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_3_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_3_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[3].valid, _portsCOI_filtered_3_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsCOI_filtered[4].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_4_valid_T = or(requestCIO_0_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_4_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_4_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[4].valid, _portsCOI_filtered_4_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsCOI_filtered[5].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_5_valid_T = or(requestCIO_0_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_5_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_5_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[5].valid, _portsCOI_filtered_5_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsCOI_filtered[6].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_6_valid_T = or(requestCIO_0_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_6_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_6_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[6].valid, _portsCOI_filtered_6_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_2 = mux(requestCIO_0_2, portsCOI_filtered[2].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_3 = mux(requestCIO_0_3, portsCOI_filtered[3].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_4 = mux(requestCIO_0_4, portsCOI_filtered[4].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_5 = mux(requestCIO_0_5, portsCOI_filtered[5].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_6 = mux(requestCIO_0_6, portsCOI_filtered[6].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_7 = or(_portsCOI_T, _portsCOI_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_8 = or(_portsCOI_T_7, _portsCOI_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_9 = or(_portsCOI_T_8, _portsCOI_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_10 = or(_portsCOI_T_9, _portsCOI_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_11 = or(_portsCOI_T_10, _portsCOI_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_12 = or(_portsCOI_T_11, _portsCOI_T_6) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _portsCOI_WIRE_2 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsCOI_WIRE_2, _portsCOI_T_12 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.data, out[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.source, out[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.size, out[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.param, out[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect out[0].d.ready, portsDIO_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect out[1].d.ready, portsDIO_filtered_1[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered_2[0].bits.corrupt, out[2].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_2[0].bits.data, out[2].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_2[0].bits.denied, out[2].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_2[0].bits.sink, out[2].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_2[0].bits.source, out[2].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_2[0].bits.size, out[2].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_2[0].bits.param, out[2].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_2[0].bits.opcode, out[2].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T_4 = or(requestDOI_2_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_5 = and(out[2].d.valid, _portsDIO_filtered_0_valid_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered_2[0].valid, _portsDIO_filtered_0_valid_T_5 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect out[2].d.ready, portsDIO_filtered_2[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered_3[0].bits.corrupt, out[3].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_3[0].bits.data, out[3].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_3[0].bits.denied, out[3].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_3[0].bits.sink, out[3].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_3[0].bits.source, out[3].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_3[0].bits.size, out[3].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_3[0].bits.param, out[3].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_3[0].bits.opcode, out[3].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T_6 = or(requestDOI_3_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_7 = and(out[3].d.valid, _portsDIO_filtered_0_valid_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered_3[0].valid, _portsDIO_filtered_0_valid_T_7 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect out[3].d.ready, portsDIO_filtered_3[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered_4[0].bits.corrupt, out[4].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_4[0].bits.data, out[4].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_4[0].bits.denied, out[4].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_4[0].bits.sink, out[4].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_4[0].bits.source, out[4].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_4[0].bits.size, out[4].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_4[0].bits.param, out[4].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_4[0].bits.opcode, out[4].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T_8 = or(requestDOI_4_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_9 = and(out[4].d.valid, _portsDIO_filtered_0_valid_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered_4[0].valid, _portsDIO_filtered_0_valid_T_9 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect out[4].d.ready, portsDIO_filtered_4[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered_5[0].bits.corrupt, out[5].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_5[0].bits.data, out[5].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_5[0].bits.denied, out[5].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_5[0].bits.sink, out[5].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_5[0].bits.source, out[5].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_5[0].bits.size, out[5].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_5[0].bits.param, out[5].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_5[0].bits.opcode, out[5].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T_10 = or(requestDOI_5_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_11 = and(out[5].d.valid, _portsDIO_filtered_0_valid_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered_5[0].valid, _portsDIO_filtered_0_valid_T_11 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect out[5].d.ready, portsDIO_filtered_5[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered_6[0].bits.corrupt, out[6].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_6[0].bits.data, out[6].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_6[0].bits.denied, out[6].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_6[0].bits.sink, out[6].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_6[0].bits.source, out[6].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_6[0].bits.size, out[6].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_6[0].bits.param, out[6].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_6[0].bits.opcode, out[6].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T_12 = or(requestDOI_6_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_13 = and(out[6].d.valid, _portsDIO_filtered_0_valid_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered_6[0].valid, _portsDIO_filtered_0_valid_T_13 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect out[6].d.ready, portsDIO_filtered_6[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[7] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsEOI_filtered[2].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_2_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_2_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_2_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[2].valid, _portsEOI_filtered_2_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsEOI_filtered[3].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_3_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_3_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_3_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[3].valid, _portsEOI_filtered_3_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsEOI_filtered[4].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_4_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_4_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_4_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[4].valid, _portsEOI_filtered_4_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsEOI_filtered[5].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_5_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_5_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_5_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[5].valid, _portsEOI_filtered_5_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsEOI_filtered[6].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_6_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_6_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_6_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[6].valid, _portsEOI_filtered_6_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_2 = mux(UInt<1>(0h0), portsEOI_filtered[2].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_3 = mux(UInt<1>(0h0), portsEOI_filtered[3].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_4 = mux(UInt<1>(0h0), portsEOI_filtered[4].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_5 = mux(UInt<1>(0h0), portsEOI_filtered[5].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_6 = mux(UInt<1>(0h0), portsEOI_filtered[6].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_7 = or(_portsEOI_T, _portsEOI_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_8 = or(_portsEOI_T_7, _portsEOI_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_9 = or(_portsEOI_T_8, _portsEOI_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_10 = or(_portsEOI_T_9, _portsEOI_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_11 = or(_portsEOI_T_10, _portsEOI_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_12 = or(_portsEOI_T_11, _portsEOI_T_6) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _portsEOI_WIRE_2 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsEOI_WIRE_2, _portsEOI_T_12 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] connect out[0].a, portsAOI_filtered[0] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] wire _WIRE_192 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_192.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_192.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_192.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_192.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_192.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_192.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_192.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_192.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_192.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_192.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_192.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_192.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_192.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_192.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_192.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_192.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_193 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_193.bits, _WIRE_192.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_193.valid, _WIRE_192.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_193.ready, _WIRE_192.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_193.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_193.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_193.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_193.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_193.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_193.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_193.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_193.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_193.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_193.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_193.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_193.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_193.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_193.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_194 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_194.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_194.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_194.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_195 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_195.bits, _WIRE_194.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_195.valid, _WIRE_194.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_195.ready, _WIRE_194.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_195.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] connect out[1].a, portsAOI_filtered[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] wire _WIRE_196 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_196.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_196.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_196.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_196.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_196.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_196.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_196.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_196.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_196.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_196.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_196.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_196.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_196.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_196.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_196.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_196.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_197 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_197.bits, _WIRE_196.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_197.valid, _WIRE_196.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_197.ready, _WIRE_196.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_197.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_197.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_197.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_197.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_197.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_197.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_197.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_197.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_197.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_197.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_197.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_197.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_197.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_197.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_198 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_198.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_198.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_198.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_199 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_199.bits, _WIRE_198.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_199.valid, _WIRE_198.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_199.ready, _WIRE_198.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_199.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[1].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[1].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] connect out[2].a, portsAOI_filtered[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] wire _WIRE_200 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_200.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_200.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_200.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_200.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_200.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_200.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_200.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_200.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_200.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_200.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_200.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_200.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_200.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_200.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_200.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_200.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_201 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_201.bits, _WIRE_200.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_201.valid, _WIRE_200.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_201.ready, _WIRE_200.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_201.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_201.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_201.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_201.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_201.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_201.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_201.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_201.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_201.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_201.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_201.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_201.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_201.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_201.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_202 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_202.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_202.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_202.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_203 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_203.bits, _WIRE_202.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_203.valid, _WIRE_202.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_203.ready, _WIRE_202.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_203.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[2].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[2].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] connect out[3].a, portsAOI_filtered[3] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] wire _WIRE_204 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_204.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_204.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_204.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_204.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_204.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_204.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_204.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_204.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_204.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_204.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_204.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_204.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_204.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_204.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_204.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_204.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_205 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_205.bits, _WIRE_204.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_205.valid, _WIRE_204.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_205.ready, _WIRE_204.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_205.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_205.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_205.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_205.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_205.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_205.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_205.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_205.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_205.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_205.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_205.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_205.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_205.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_205.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_206 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_206.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_206.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_206.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_207 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_207.bits, _WIRE_206.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_207.valid, _WIRE_206.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_207.ready, _WIRE_206.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_207.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[3].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[3].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] connect out[4].a, portsAOI_filtered[4] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] wire _WIRE_208 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_208.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_208.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_208.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_208.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_208.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_208.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_208.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_208.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_208.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_208.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_208.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_208.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_208.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_208.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_208.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_208.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_209 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_209.bits, _WIRE_208.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_209.valid, _WIRE_208.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_209.ready, _WIRE_208.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_209.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_209.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_209.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_209.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_209.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_209.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_209.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_209.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_209.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_209.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_209.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_209.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_209.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_209.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_210 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_210.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_210.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_210.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_211 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_211.bits, _WIRE_210.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_211.valid, _WIRE_210.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_211.ready, _WIRE_210.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_211.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[4].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[4].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] connect out[5].a, portsAOI_filtered[5] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] wire _WIRE_212 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_212.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_212.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_212.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_212.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_212.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_212.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_212.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_212.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_212.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_212.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_212.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_212.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_212.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_212.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_212.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_212.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_213 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_213.bits, _WIRE_212.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_213.valid, _WIRE_212.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_213.ready, _WIRE_212.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_213.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_213.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_213.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_213.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_213.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_213.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_213.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_213.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_213.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_213.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_213.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_213.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_213.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_213.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_214 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_214.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_214.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_214.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_215 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_215.bits, _WIRE_214.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_215.valid, _WIRE_214.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_215.ready, _WIRE_214.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_215.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[5].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[5].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] connect out[6].a, portsAOI_filtered[6] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] wire _WIRE_216 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_216.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_216.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_216.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_216.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_216.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_216.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_216.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_216.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_216.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_216.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_216.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_216.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_216.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_216.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_216.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_216.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_217 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_217.bits, _WIRE_216.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_217.valid, _WIRE_216.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_217.ready, _WIRE_216.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_217.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_217.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_217.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_217.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_217.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_217.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_217.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_217.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_217.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_217.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_217.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_217.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_217.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_217.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_218 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_218.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_218.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_218.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_219 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_219.bits, _WIRE_218.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_219.valid, _WIRE_218.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_219.ready, _WIRE_218.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_219.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[6].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[6].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] wire _WIRE_220 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_220.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_220.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_220.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_220.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_220.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_220.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_220.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_220.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_220.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_220.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_221 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_221.bits, _WIRE_220.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_221.valid, _WIRE_220.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_221.ready, _WIRE_220.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_221.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_221.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_221.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_221.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_221.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_221.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_221.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_221.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 60:30] node idle = eq(beatsLeft, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 61:28] node latch = and(idle, in[0].d.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 62:24] node readys_lo_hi = cat(portsDIO_filtered_2[0].valid, portsDIO_filtered_1[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:51] node readys_lo = cat(readys_lo_hi, portsDIO_filtered[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:51] node readys_hi_lo = cat(portsDIO_filtered_4[0].valid, portsDIO_filtered_3[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:51] node readys_hi_hi = cat(portsDIO_filtered_6[0].valid, portsDIO_filtered_5[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:51] node readys_hi = cat(readys_hi_hi, readys_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:51] node _readys_T = cat(readys_hi, readys_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:51] node readys_valid = bits(_readys_T, 6, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 21:23] node _readys_T_1 = eq(readys_valid, _readys_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:19] node _readys_T_2 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] when _readys_T_3 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] when _readys_T_4 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] regreset readys_mask : UInt<7>, clock, reset, UInt<7>(0h7f) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 23:23] node _readys_filter_T = not(readys_mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 24:30] node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 24:28] node readys_filter = cat(_readys_filter_T_1, readys_valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 24:21] node _readys_unready_T = shr(readys_filter, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 263:48] node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 263:43] node _readys_unready_T_2 = shr(_readys_unready_T_1, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 263:48] node _readys_unready_T_3 = or(_readys_unready_T_1, _readys_unready_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 263:43] node _readys_unready_T_4 = shr(_readys_unready_T_3, 4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 263:48] node _readys_unready_T_5 = or(_readys_unready_T_3, _readys_unready_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 263:43] node _readys_unready_T_6 = bits(_readys_unready_T_5, 13, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 264:17] node _readys_unready_T_7 = shr(_readys_unready_T_6, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 25:52] node _readys_unready_T_8 = shl(readys_mask, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 25:66] node readys_unready = or(_readys_unready_T_7, _readys_unready_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 25:58] node _readys_readys_T = shr(readys_unready, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:29] node _readys_readys_T_1 = bits(readys_unready, 6, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:48] node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:39] node readys_readys = not(_readys_readys_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:18] node _readys_T_5 = orr(readys_valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 27:27] node _readys_T_6 = and(latch, _readys_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 27:18] when _readys_T_6 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 27:32] node _readys_mask_T = and(readys_readys, readys_valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 28:29] node _readys_mask_T_1 = shl(_readys_mask_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _readys_mask_T_2 = bits(_readys_mask_T_1, 6, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _readys_mask_T_4 = shl(_readys_mask_T_3, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _readys_mask_T_5 = bits(_readys_mask_T_4, 6, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _readys_mask_T_6 = or(_readys_mask_T_3, _readys_mask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _readys_mask_T_7 = shl(_readys_mask_T_6, 4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _readys_mask_T_8 = bits(_readys_mask_T_7, 6, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _readys_mask_T_9 = or(_readys_mask_T_6, _readys_mask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _readys_mask_T_10 = bits(_readys_mask_T_9, 6, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 255:17] connect readys_mask, _readys_mask_T_10 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 28:12] node _readys_T_7 = bits(readys_readys, 6, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 30:11] node _readys_T_8 = bits(_readys_T_7, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] node _readys_T_9 = bits(_readys_T_7, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] node _readys_T_10 = bits(_readys_T_7, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] node _readys_T_11 = bits(_readys_T_7, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] node _readys_T_12 = bits(_readys_T_7, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] node _readys_T_13 = bits(_readys_T_7, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] node _readys_T_14 = bits(_readys_T_7, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] wire readys : UInt<1>[7] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[0], _readys_T_8 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[1], _readys_T_9 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[2], _readys_T_10 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[3], _readys_T_11 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[4], _readys_T_12 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[5], _readys_T_13 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[6], _readys_T_14 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] node _winner_T = and(readys[0], portsDIO_filtered[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] node _winner_T_1 = and(readys[1], portsDIO_filtered_1[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] node _winner_T_2 = and(readys[2], portsDIO_filtered_2[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] node _winner_T_3 = and(readys[3], portsDIO_filtered_3[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] node _winner_T_4 = and(readys[4], portsDIO_filtered_4[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] node _winner_T_5 = and(readys[5], portsDIO_filtered_5[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] node _winner_T_6 = and(readys[6], portsDIO_filtered_6[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] wire winner : UInt<1>[7] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[0], _winner_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[1], _winner_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[2], _winner_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[3], _winner_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[4], _winner_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[5], _winner_T_5 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[6], _winner_T_6 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] node prefixOR_1 = or(UInt<1>(0h0), winner[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node prefixOR_2 = or(prefixOR_1, winner[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node prefixOR_3 = or(prefixOR_2, winner[2]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node prefixOR_4 = or(prefixOR_3, winner[3]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node prefixOR_5 = or(prefixOR_4, winner[4]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node prefixOR_6 = or(prefixOR_5, winner[5]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node _prefixOR_T = or(prefixOR_6, winner[6]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_1 = eq(winner[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_2 = or(_T, _T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_4 = eq(winner[1], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_5 = or(_T_3, _T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_6 = eq(prefixOR_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_7 = eq(winner[2], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_8 = or(_T_6, _T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_9 = eq(prefixOR_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_10 = eq(winner[3], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_11 = or(_T_9, _T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_12 = eq(prefixOR_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_13 = eq(winner[4], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_14 = or(_T_12, _T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_15 = eq(prefixOR_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_16 = eq(winner[5], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_17 = or(_T_15, _T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_18 = eq(prefixOR_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_19 = eq(winner[6], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_20 = or(_T_18, _T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_21 = and(_T_2, _T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:77] node _T_22 = and(_T_21, _T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:77] node _T_23 = and(_T_22, _T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:77] node _T_24 = and(_T_23, _T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:77] node _T_25 = and(_T_24, _T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:77] node _T_26 = and(_T_25, _T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:77] node _T_27 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_28 = eq(_T_27, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] when _T_28 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_29 = eq(_T_26, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] when _T_29 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] assert(clock, _T_26, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_30 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:31] node _T_31 = or(_T_30, portsDIO_filtered_2[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:31] node _T_32 = or(_T_31, portsDIO_filtered_3[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:31] node _T_33 = or(_T_32, portsDIO_filtered_4[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:31] node _T_34 = or(_T_33, portsDIO_filtered_5[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:31] node _T_35 = or(_T_34, portsDIO_filtered_6[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:31] node _T_36 = eq(_T_35, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:15] node _T_37 = or(winner[0], winner[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:54] node _T_38 = or(_T_37, winner[2]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:54] node _T_39 = or(_T_38, winner[3]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:54] node _T_40 = or(_T_39, winner[4]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:54] node _T_41 = or(_T_40, winner[5]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:54] node _T_42 = or(_T_41, winner[6]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:54] node _T_43 = or(_T_36, _T_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:36] node _T_44 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node _T_45 = eq(_T_44, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] when _T_45 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node _T_46 = eq(_T_43, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] when _T_46 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] assert(clock, _T_43, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node maskedBeats_0 = mux(winner[0], beatsDO_0, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node maskedBeats_1 = mux(winner[1], beatsDO_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node maskedBeats_2 = mux(winner[2], beatsDO_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node maskedBeats_3 = mux(winner[3], beatsDO_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node maskedBeats_4 = mux(winner[4], beatsDO_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node maskedBeats_5 = mux(winner[5], beatsDO_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node maskedBeats_6 = mux(winner[6], beatsDO_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node _initBeats_T = or(maskedBeats_0, maskedBeats_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 84:44] node _initBeats_T_1 = or(_initBeats_T, maskedBeats_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 84:44] node _initBeats_T_2 = or(_initBeats_T_1, maskedBeats_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 84:44] node _initBeats_T_3 = or(_initBeats_T_2, maskedBeats_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 84:44] node _initBeats_T_4 = or(_initBeats_T_3, maskedBeats_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 84:44] node initBeats = or(_initBeats_T_4, maskedBeats_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 84:44] node _beatsLeft_T = and(in[0].d.ready, in[0].d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:52] node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:52] node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:23] connect beatsLeft, _beatsLeft_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:17] wire _state_WIRE : UInt<1>[7] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[4], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[5], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[6], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] regreset state : UInt<1>[7], clock, reset, _state_WIRE @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:26] node muxState = mux(idle, winner, state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 89:25] connect state, muxState @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 90:13] node allowed = mux(idle, readys, state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 92:24] node _filtered_0_ready_T = and(in[0].d.ready, allowed[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect portsDIO_filtered[0].ready, _filtered_0_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _filtered_0_ready_T_1 = and(in[0].d.ready, allowed[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _filtered_0_ready_T_2 = and(in[0].d.ready, allowed[2]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect portsDIO_filtered_2[0].ready, _filtered_0_ready_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _filtered_0_ready_T_3 = and(in[0].d.ready, allowed[3]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect portsDIO_filtered_3[0].ready, _filtered_0_ready_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _filtered_0_ready_T_4 = and(in[0].d.ready, allowed[4]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect portsDIO_filtered_4[0].ready, _filtered_0_ready_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _filtered_0_ready_T_5 = and(in[0].d.ready, allowed[5]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect portsDIO_filtered_5[0].ready, _filtered_0_ready_T_5 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _filtered_0_ready_T_6 = and(in[0].d.ready, allowed[6]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect portsDIO_filtered_6[0].ready, _filtered_0_ready_T_6 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:46] node _in_0_d_valid_T_1 = or(_in_0_d_valid_T, portsDIO_filtered_2[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:46] node _in_0_d_valid_T_2 = or(_in_0_d_valid_T_1, portsDIO_filtered_3[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:46] node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_2, portsDIO_filtered_4[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:46] node _in_0_d_valid_T_4 = or(_in_0_d_valid_T_3, portsDIO_filtered_5[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:46] node _in_0_d_valid_T_5 = or(_in_0_d_valid_T_4, portsDIO_filtered_6[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:46] node _in_0_d_valid_T_6 = mux(state[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_7 = mux(state[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_8 = mux(state[2], portsDIO_filtered_2[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_9 = mux(state[3], portsDIO_filtered_3[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_10 = mux(state[4], portsDIO_filtered_4[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_11 = mux(state[5], portsDIO_filtered_5[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_12 = mux(state[6], portsDIO_filtered_6[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_13 = or(_in_0_d_valid_T_6, _in_0_d_valid_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_14 = or(_in_0_d_valid_T_13, _in_0_d_valid_T_8) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_15 = or(_in_0_d_valid_T_14, _in_0_d_valid_T_9) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_16 = or(_in_0_d_valid_T_15, _in_0_d_valid_T_10) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_17 = or(_in_0_d_valid_T_16, _in_0_d_valid_T_11) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_18 = or(_in_0_d_valid_T_17, _in_0_d_valid_T_12) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_valid_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_valid_WIRE, _in_0_d_valid_T_18 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_19 = mux(idle, _in_0_d_valid_T_5, _in_0_d_valid_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:24] connect in[0].d.valid, _in_0_d_valid_T_19 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:18] wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T = mux(muxState[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_1 = mux(muxState[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_2 = mux(muxState[2], portsDIO_filtered_2[0].bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_3 = mux(muxState[3], portsDIO_filtered_3[0].bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_4 = mux(muxState[4], portsDIO_filtered_4[0].bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_5 = mux(muxState[5], portsDIO_filtered_5[0].bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_6 = mux(muxState[6], portsDIO_filtered_6[0].bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_7 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_7, _in_0_d_bits_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_9 = or(_in_0_d_bits_T_8, _in_0_d_bits_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_10 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_10, _in_0_d_bits_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_12 = or(_in_0_d_bits_T_11, _in_0_d_bits_T_6) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_1 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_12 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_13 = mux(muxState[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_14 = mux(muxState[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_15 = mux(muxState[2], portsDIO_filtered_2[0].bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_16 = mux(muxState[3], portsDIO_filtered_3[0].bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_17 = mux(muxState[4], portsDIO_filtered_4[0].bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_18 = mux(muxState[5], portsDIO_filtered_5[0].bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_19 = mux(muxState[6], portsDIO_filtered_6[0].bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_13, _in_0_d_bits_T_14) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_21 = or(_in_0_d_bits_T_20, _in_0_d_bits_T_15) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_22 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_16) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_22, _in_0_d_bits_T_17) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_24 = or(_in_0_d_bits_T_23, _in_0_d_bits_T_18) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_25 = or(_in_0_d_bits_T_24, _in_0_d_bits_T_19) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_2 : UInt<64> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_25 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_3 : { } @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_4 : { } @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_26 = mux(muxState[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_27 = mux(muxState[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_28 = mux(muxState[2], portsDIO_filtered_2[0].bits.denied, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_29 = mux(muxState[3], portsDIO_filtered_3[0].bits.denied, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_30 = mux(muxState[4], portsDIO_filtered_4[0].bits.denied, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_31 = mux(muxState[5], portsDIO_filtered_5[0].bits.denied, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_32 = mux(muxState[6], portsDIO_filtered_6[0].bits.denied, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_33 = or(_in_0_d_bits_T_26, _in_0_d_bits_T_27) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_34 = or(_in_0_d_bits_T_33, _in_0_d_bits_T_28) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_35 = or(_in_0_d_bits_T_34, _in_0_d_bits_T_29) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_36 = or(_in_0_d_bits_T_35, _in_0_d_bits_T_30) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_37 = or(_in_0_d_bits_T_36, _in_0_d_bits_T_31) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_38 = or(_in_0_d_bits_T_37, _in_0_d_bits_T_32) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_5 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_38 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_39 = mux(muxState[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_40 = mux(muxState[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_41 = mux(muxState[2], portsDIO_filtered_2[0].bits.sink, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_42 = mux(muxState[3], portsDIO_filtered_3[0].bits.sink, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_43 = mux(muxState[4], portsDIO_filtered_4[0].bits.sink, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_44 = mux(muxState[5], portsDIO_filtered_5[0].bits.sink, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_45 = mux(muxState[6], portsDIO_filtered_6[0].bits.sink, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_46 = or(_in_0_d_bits_T_39, _in_0_d_bits_T_40) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_47 = or(_in_0_d_bits_T_46, _in_0_d_bits_T_41) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_48 = or(_in_0_d_bits_T_47, _in_0_d_bits_T_42) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_49 = or(_in_0_d_bits_T_48, _in_0_d_bits_T_43) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_50 = or(_in_0_d_bits_T_49, _in_0_d_bits_T_44) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_51 = or(_in_0_d_bits_T_50, _in_0_d_bits_T_45) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_6 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_51 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_52 = mux(muxState[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_53 = mux(muxState[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_54 = mux(muxState[2], portsDIO_filtered_2[0].bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_55 = mux(muxState[3], portsDIO_filtered_3[0].bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_56 = mux(muxState[4], portsDIO_filtered_4[0].bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_57 = mux(muxState[5], portsDIO_filtered_5[0].bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_58 = mux(muxState[6], portsDIO_filtered_6[0].bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_59 = or(_in_0_d_bits_T_52, _in_0_d_bits_T_53) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_60 = or(_in_0_d_bits_T_59, _in_0_d_bits_T_54) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_61 = or(_in_0_d_bits_T_60, _in_0_d_bits_T_55) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_62 = or(_in_0_d_bits_T_61, _in_0_d_bits_T_56) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_63 = or(_in_0_d_bits_T_62, _in_0_d_bits_T_57) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_64 = or(_in_0_d_bits_T_63, _in_0_d_bits_T_58) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_7 : UInt<2> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_64 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_65 = mux(muxState[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_66 = mux(muxState[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_67 = mux(muxState[2], portsDIO_filtered_2[0].bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_68 = mux(muxState[3], portsDIO_filtered_3[0].bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_69 = mux(muxState[4], portsDIO_filtered_4[0].bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_70 = mux(muxState[5], portsDIO_filtered_5[0].bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_71 = mux(muxState[6], portsDIO_filtered_6[0].bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_72 = or(_in_0_d_bits_T_65, _in_0_d_bits_T_66) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_73 = or(_in_0_d_bits_T_72, _in_0_d_bits_T_67) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_74 = or(_in_0_d_bits_T_73, _in_0_d_bits_T_68) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_75 = or(_in_0_d_bits_T_74, _in_0_d_bits_T_69) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_76 = or(_in_0_d_bits_T_75, _in_0_d_bits_T_70) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_77 = or(_in_0_d_bits_T_76, _in_0_d_bits_T_71) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_8 : UInt<4> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_77 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_78 = mux(muxState[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_79 = mux(muxState[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_80 = mux(muxState[2], portsDIO_filtered_2[0].bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_81 = mux(muxState[3], portsDIO_filtered_3[0].bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_82 = mux(muxState[4], portsDIO_filtered_4[0].bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_83 = mux(muxState[5], portsDIO_filtered_5[0].bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_84 = mux(muxState[6], portsDIO_filtered_6[0].bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_85 = or(_in_0_d_bits_T_78, _in_0_d_bits_T_79) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_86 = or(_in_0_d_bits_T_85, _in_0_d_bits_T_80) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_87 = or(_in_0_d_bits_T_86, _in_0_d_bits_T_81) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_88 = or(_in_0_d_bits_T_87, _in_0_d_bits_T_82) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_89 = or(_in_0_d_bits_T_88, _in_0_d_bits_T_83) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_90 = or(_in_0_d_bits_T_89, _in_0_d_bits_T_84) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_9 : UInt<2> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_90 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_91 = mux(muxState[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_92 = mux(muxState[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_93 = mux(muxState[2], portsDIO_filtered_2[0].bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_94 = mux(muxState[3], portsDIO_filtered_3[0].bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_95 = mux(muxState[4], portsDIO_filtered_4[0].bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_96 = mux(muxState[5], portsDIO_filtered_5[0].bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_97 = mux(muxState[6], portsDIO_filtered_6[0].bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_98 = or(_in_0_d_bits_T_91, _in_0_d_bits_T_92) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_99 = or(_in_0_d_bits_T_98, _in_0_d_bits_T_93) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_100 = or(_in_0_d_bits_T_99, _in_0_d_bits_T_94) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_101 = or(_in_0_d_bits_T_100, _in_0_d_bits_T_95) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_102 = or(_in_0_d_bits_T_101, _in_0_d_bits_T_96) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_103 = or(_in_0_d_bits_T_102, _in_0_d_bits_T_97) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_10 : UInt<3> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_103 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.data, _in_0_d_bits_WIRE.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.source, _in_0_d_bits_WIRE.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.size, _in_0_d_bits_WIRE.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.param, _in_0_d_bits_WIRE.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect portsBIO_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] connect portsBIO_filtered_1[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] connect portsBIO_filtered_2[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] connect portsBIO_filtered_3[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] connect portsBIO_filtered_4[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] connect portsBIO_filtered_5[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] connect portsBIO_filtered_6[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] module Queue2_TLBundleA_a32d64s2k1z4u : @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input clock : Clock @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input reset : Reset @[src/main/scala/chisel3/util/Decoupled.scala 243:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, count : UInt<2>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} [2] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] regreset enq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset deq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] infer mport MPORT = ram[enq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 270:24] node wrap = eq(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T = add(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_1 = tail(_value_T, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect enq_ptr_value, _value_T_1 @[src/main/scala/chisel3/util/Counter.scala 77:15] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] node wrap_1 = eq(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_3 = tail(_value_T_2, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect deq_ptr_value, _value_T_3 @[src/main/scala/chisel3/util/Counter.scala 77:15] node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] infer mport io_deq_bits_MPORT = ram[deq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module Queue2_TLBundleD_a32d64s2k1z4u : @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input clock : Clock @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input reset : Reset @[src/main/scala/chisel3/util/Decoupled.scala 243:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, count : UInt<2>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} [2] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] regreset enq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset deq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] infer mport MPORT = ram[enq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 270:24] node wrap = eq(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T = add(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_1 = tail(_value_T, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect enq_ptr_value, _value_T_1 @[src/main/scala/chisel3/util/Counter.scala 77:15] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] node wrap_1 = eq(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_3 = tail(_value_T_2, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect deq_ptr_value, _value_T_3 @[src/main/scala/chisel3/util/Counter.scala 77:15] node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] infer mport io_deq_bits_MPORT = ram[deq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module TLBuffer_a32d64s2k1z4u : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] inst nodeOut_a_q of Queue2_TLBundleA_a32d64s2k1z4u @[src/main/scala/chisel3/util/Decoupled.scala 362:21] connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid @[src/main/scala/chisel3/util/Decoupled.scala 364:22] connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.fetch, nodeIn.a.bits.user.amba_prot.fetch @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.secure, nodeIn.a.bits.user.amba_prot.secure @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.privileged, nodeIn.a.bits.user.amba_prot.privileged @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.writealloc, nodeIn.a.bits.user.amba_prot.writealloc @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.readalloc, nodeIn.a.bits.user.amba_prot.readalloc @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.modifiable, nodeIn.a.bits.user.amba_prot.modifiable @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.bufferable, nodeIn.a.bits.user.amba_prot.bufferable @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready @[src/main/scala/chisel3/util/Decoupled.scala 366:17] connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] inst nodeIn_d_q of Queue2_TLBundleD_a32d64s2k1z4u @[src/main/scala/chisel3/util/Decoupled.scala 362:21] connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid @[src/main/scala/chisel3/util/Decoupled.scala 364:22] connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready @[src/main/scala/chisel3/util/Decoupled.scala 366:17] connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 52:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 53:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 54:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 55:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 56:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 57:21] module TLAtomicAutomata_cbus : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 36:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 36:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 36:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] wire initval : { state : UInt<2>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 80:27] connect initval.state, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 81:23] wire _cam_s_WIRE : { state : UInt<2>}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 82:50] connect _cam_s_WIRE[0], initval @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 82:50] regreset cam_s : { state : UInt<2>}[1], clock, reset, _cam_s_WIRE @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 82:28] reg cam_a : { bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, fifoId : UInt<1>, lut : UInt<4>}[1], clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 83:24] reg cam_d : { data : UInt<64>, denied : UInt<1>, corrupt : UInt<1>}[1], clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 84:24] node cam_free_0 = eq(cam_s[0].state, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 86:44] node cam_amo_0 = eq(cam_s[0].state, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 87:44] node _cam_abusy_T = eq(cam_s[0].state, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 88:49] node _cam_abusy_T_1 = eq(cam_s[0].state, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 88:68] node cam_abusy_0 = or(_cam_abusy_T, _cam_abusy_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 88:57] node cam_dmatch_0 = neq(cam_s[0].state, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 89:49] node _a_canLogical_T = leq(UInt<1>(0h0), nodeIn.a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _a_canLogical_T_1 = leq(nodeIn.a.bits.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _a_canLogical_T_2 = and(_a_canLogical_T, _a_canLogical_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _a_canLogical_T_3 = or(UInt<1>(0h0), _a_canLogical_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _a_canLogical_T_4 = xor(nodeIn.a.bits.address, UInt<13>(0h1000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canLogical_T_5 = cvt(_a_canLogical_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canLogical_T_6 = and(_a_canLogical_T_5, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_7 = asSInt(_a_canLogical_T_6) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_8 = eq(_a_canLogical_T_7, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canLogical_T_9 = xor(nodeIn.a.bits.address, UInt<29>(0h10000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canLogical_T_10 = cvt(_a_canLogical_T_9) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canLogical_T_11 = and(_a_canLogical_T_10, asSInt(UInt<33>(0hfa018000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_12 = asSInt(_a_canLogical_T_11) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_13 = eq(_a_canLogical_T_12, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canLogical_T_14 = xor(nodeIn.a.bits.address, UInt<29>(0h10008000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canLogical_T_15 = cvt(_a_canLogical_T_14) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canLogical_T_16 = and(_a_canLogical_T_15, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_17 = asSInt(_a_canLogical_T_16) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_18 = eq(_a_canLogical_T_17, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canLogical_T_19 = xor(nodeIn.a.bits.address, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canLogical_T_20 = cvt(_a_canLogical_T_19) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canLogical_T_21 = and(_a_canLogical_T_20, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_22 = asSInt(_a_canLogical_T_21) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_23 = eq(_a_canLogical_T_22, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canLogical_T_24 = xor(nodeIn.a.bits.address, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canLogical_T_25 = cvt(_a_canLogical_T_24) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canLogical_T_26 = and(_a_canLogical_T_25, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_27 = asSInt(_a_canLogical_T_26) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_28 = eq(_a_canLogical_T_27, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canLogical_T_29 = or(_a_canLogical_T_8, _a_canLogical_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _a_canLogical_T_30 = or(_a_canLogical_T_29, _a_canLogical_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _a_canLogical_T_31 = or(_a_canLogical_T_30, _a_canLogical_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _a_canLogical_T_32 = or(_a_canLogical_T_31, _a_canLogical_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _a_canLogical_T_33 = and(_a_canLogical_T_3, _a_canLogical_T_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _a_canLogical_T_34 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _a_canLogical_T_35 = xor(nodeIn.a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canLogical_T_36 = cvt(_a_canLogical_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canLogical_T_37 = and(_a_canLogical_T_36, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_38 = asSInt(_a_canLogical_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_39 = eq(_a_canLogical_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canLogical_T_40 = xor(nodeIn.a.bits.address, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canLogical_T_41 = cvt(_a_canLogical_T_40) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canLogical_T_42 = and(_a_canLogical_T_41, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_43 = asSInt(_a_canLogical_T_42) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_44 = eq(_a_canLogical_T_43, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canLogical_T_45 = xor(nodeIn.a.bits.address, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canLogical_T_46 = cvt(_a_canLogical_T_45) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canLogical_T_47 = and(_a_canLogical_T_46, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_48 = asSInt(_a_canLogical_T_47) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_49 = eq(_a_canLogical_T_48, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canLogical_T_50 = xor(nodeIn.a.bits.address, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canLogical_T_51 = cvt(_a_canLogical_T_50) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canLogical_T_52 = and(_a_canLogical_T_51, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_53 = asSInt(_a_canLogical_T_52) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_54 = eq(_a_canLogical_T_53, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canLogical_T_55 = or(_a_canLogical_T_39, _a_canLogical_T_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _a_canLogical_T_56 = or(_a_canLogical_T_55, _a_canLogical_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _a_canLogical_T_57 = or(_a_canLogical_T_56, _a_canLogical_T_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _a_canLogical_T_58 = and(_a_canLogical_T_34, _a_canLogical_T_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _a_canLogical_T_59 = leq(UInt<2>(0h2), nodeIn.a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _a_canLogical_T_60 = leq(nodeIn.a.bits.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _a_canLogical_T_61 = and(_a_canLogical_T_59, _a_canLogical_T_60) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _a_canLogical_T_62 = or(UInt<1>(0h0), _a_canLogical_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _a_canLogical_T_63 = xor(nodeIn.a.bits.address, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canLogical_T_64 = cvt(_a_canLogical_T_63) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canLogical_T_65 = and(_a_canLogical_T_64, asSInt(UInt<33>(0hfa000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_66 = asSInt(_a_canLogical_T_65) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canLogical_T_67 = eq(_a_canLogical_T_66, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canLogical_T_68 = and(_a_canLogical_T_62, _a_canLogical_T_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _a_canLogical_T_69 = or(UInt<1>(0h0), _a_canLogical_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node _a_canLogical_T_70 = or(_a_canLogical_T_69, _a_canLogical_T_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node _a_canLogical_T_71 = or(_a_canLogical_T_70, _a_canLogical_T_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node a_canLogical = and(UInt<1>(0h1), _a_canLogical_T_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 94:45] node _a_canArithmetic_T = leq(UInt<1>(0h0), nodeIn.a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _a_canArithmetic_T_1 = leq(nodeIn.a.bits.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _a_canArithmetic_T_2 = and(_a_canArithmetic_T, _a_canArithmetic_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _a_canArithmetic_T_3 = or(UInt<1>(0h0), _a_canArithmetic_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _a_canArithmetic_T_4 = xor(nodeIn.a.bits.address, UInt<13>(0h1000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canArithmetic_T_5 = cvt(_a_canArithmetic_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canArithmetic_T_6 = and(_a_canArithmetic_T_5, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_7 = asSInt(_a_canArithmetic_T_6) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_8 = eq(_a_canArithmetic_T_7, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canArithmetic_T_9 = xor(nodeIn.a.bits.address, UInt<29>(0h10000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canArithmetic_T_10 = cvt(_a_canArithmetic_T_9) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canArithmetic_T_11 = and(_a_canArithmetic_T_10, asSInt(UInt<33>(0hfa018000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_12 = asSInt(_a_canArithmetic_T_11) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_13 = eq(_a_canArithmetic_T_12, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canArithmetic_T_14 = xor(nodeIn.a.bits.address, UInt<29>(0h10008000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canArithmetic_T_15 = cvt(_a_canArithmetic_T_14) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canArithmetic_T_16 = and(_a_canArithmetic_T_15, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_17 = asSInt(_a_canArithmetic_T_16) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_18 = eq(_a_canArithmetic_T_17, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canArithmetic_T_19 = xor(nodeIn.a.bits.address, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canArithmetic_T_20 = cvt(_a_canArithmetic_T_19) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canArithmetic_T_21 = and(_a_canArithmetic_T_20, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_22 = asSInt(_a_canArithmetic_T_21) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_23 = eq(_a_canArithmetic_T_22, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canArithmetic_T_24 = xor(nodeIn.a.bits.address, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canArithmetic_T_25 = cvt(_a_canArithmetic_T_24) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canArithmetic_T_26 = and(_a_canArithmetic_T_25, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_27 = asSInt(_a_canArithmetic_T_26) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_28 = eq(_a_canArithmetic_T_27, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canArithmetic_T_29 = or(_a_canArithmetic_T_8, _a_canArithmetic_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _a_canArithmetic_T_30 = or(_a_canArithmetic_T_29, _a_canArithmetic_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _a_canArithmetic_T_31 = or(_a_canArithmetic_T_30, _a_canArithmetic_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _a_canArithmetic_T_32 = or(_a_canArithmetic_T_31, _a_canArithmetic_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _a_canArithmetic_T_33 = and(_a_canArithmetic_T_3, _a_canArithmetic_T_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _a_canArithmetic_T_34 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _a_canArithmetic_T_35 = xor(nodeIn.a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canArithmetic_T_36 = cvt(_a_canArithmetic_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canArithmetic_T_37 = and(_a_canArithmetic_T_36, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_38 = asSInt(_a_canArithmetic_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_39 = eq(_a_canArithmetic_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canArithmetic_T_40 = xor(nodeIn.a.bits.address, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canArithmetic_T_41 = cvt(_a_canArithmetic_T_40) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canArithmetic_T_42 = and(_a_canArithmetic_T_41, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_43 = asSInt(_a_canArithmetic_T_42) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_44 = eq(_a_canArithmetic_T_43, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canArithmetic_T_45 = xor(nodeIn.a.bits.address, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canArithmetic_T_46 = cvt(_a_canArithmetic_T_45) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canArithmetic_T_47 = and(_a_canArithmetic_T_46, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_48 = asSInt(_a_canArithmetic_T_47) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_49 = eq(_a_canArithmetic_T_48, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canArithmetic_T_50 = xor(nodeIn.a.bits.address, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canArithmetic_T_51 = cvt(_a_canArithmetic_T_50) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canArithmetic_T_52 = and(_a_canArithmetic_T_51, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_53 = asSInt(_a_canArithmetic_T_52) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_54 = eq(_a_canArithmetic_T_53, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canArithmetic_T_55 = or(_a_canArithmetic_T_39, _a_canArithmetic_T_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _a_canArithmetic_T_56 = or(_a_canArithmetic_T_55, _a_canArithmetic_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _a_canArithmetic_T_57 = or(_a_canArithmetic_T_56, _a_canArithmetic_T_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _a_canArithmetic_T_58 = and(_a_canArithmetic_T_34, _a_canArithmetic_T_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _a_canArithmetic_T_59 = leq(UInt<2>(0h2), nodeIn.a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _a_canArithmetic_T_60 = leq(nodeIn.a.bits.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _a_canArithmetic_T_61 = and(_a_canArithmetic_T_59, _a_canArithmetic_T_60) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _a_canArithmetic_T_62 = or(UInt<1>(0h0), _a_canArithmetic_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _a_canArithmetic_T_63 = xor(nodeIn.a.bits.address, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_canArithmetic_T_64 = cvt(_a_canArithmetic_T_63) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_canArithmetic_T_65 = and(_a_canArithmetic_T_64, asSInt(UInt<33>(0hfa000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_66 = asSInt(_a_canArithmetic_T_65) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_canArithmetic_T_67 = eq(_a_canArithmetic_T_66, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_canArithmetic_T_68 = and(_a_canArithmetic_T_62, _a_canArithmetic_T_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _a_canArithmetic_T_69 = or(UInt<1>(0h0), _a_canArithmetic_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node _a_canArithmetic_T_70 = or(_a_canArithmetic_T_69, _a_canArithmetic_T_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node _a_canArithmetic_T_71 = or(_a_canArithmetic_T_70, _a_canArithmetic_T_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node a_canArithmetic = and(UInt<1>(0h1), _a_canArithmetic_T_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 95:45] node a_isLogical = eq(nodeIn.a.bits.opcode, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 96:47] node a_isArithmetic = eq(nodeIn.a.bits.opcode, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 97:47] node _a_isSupported_T = mux(a_isArithmetic, a_canArithmetic, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 98:63] node a_isSupported = mux(a_isLogical, a_canLogical, _a_isSupported_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 98:32] node _a_cam_por_put_T = or(UInt<1>(0h0), cam_amo_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 102:56] node _a_cam_sel_put_T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 103:83] node a_cam_sel_put_0 = and(cam_amo_0, _a_cam_sel_put_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 103:80] node _a_fifoId_T = xor(nodeIn.a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _a_fifoId_T_1 = cvt(_a_fifoId_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _a_fifoId_T_2 = and(_a_fifoId_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_fifoId_T_3 = asSInt(_a_fifoId_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _a_fifoId_T_4 = eq(_a_fifoId_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _a_cam_busy_T = eq(cam_a[0].fifoId, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 111:60] node a_cam_busy = and(cam_abusy_0, _a_cam_busy_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 111:96] node _a_cam_por_free_T = or(UInt<1>(0h0), cam_free_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 115:58] node _a_cam_sel_free_T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 116:85] node a_cam_sel_free_0 = and(cam_free_0, _a_cam_sel_free_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 116:82] node _indexes_T = bits(cam_a[0].bits.data, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_1 = bits(cam_d[0].data, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_0 = cat(_indexes_T, _indexes_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_2 = bits(cam_a[0].bits.data, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_3 = bits(cam_d[0].data, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_1 = cat(_indexes_T_2, _indexes_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_4 = bits(cam_a[0].bits.data, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_5 = bits(cam_d[0].data, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_2 = cat(_indexes_T_4, _indexes_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_6 = bits(cam_a[0].bits.data, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_7 = bits(cam_d[0].data, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_3 = cat(_indexes_T_6, _indexes_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_8 = bits(cam_a[0].bits.data, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_9 = bits(cam_d[0].data, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_4 = cat(_indexes_T_8, _indexes_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_10 = bits(cam_a[0].bits.data, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_11 = bits(cam_d[0].data, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_5 = cat(_indexes_T_10, _indexes_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_12 = bits(cam_a[0].bits.data, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_13 = bits(cam_d[0].data, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_6 = cat(_indexes_T_12, _indexes_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_14 = bits(cam_a[0].bits.data, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_15 = bits(cam_d[0].data, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_7 = cat(_indexes_T_14, _indexes_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_16 = bits(cam_a[0].bits.data, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_17 = bits(cam_d[0].data, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_8 = cat(_indexes_T_16, _indexes_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_18 = bits(cam_a[0].bits.data, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_19 = bits(cam_d[0].data, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_9 = cat(_indexes_T_18, _indexes_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_20 = bits(cam_a[0].bits.data, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_21 = bits(cam_d[0].data, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_10 = cat(_indexes_T_20, _indexes_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_22 = bits(cam_a[0].bits.data, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_23 = bits(cam_d[0].data, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_11 = cat(_indexes_T_22, _indexes_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_24 = bits(cam_a[0].bits.data, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_25 = bits(cam_d[0].data, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_12 = cat(_indexes_T_24, _indexes_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_26 = bits(cam_a[0].bits.data, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_27 = bits(cam_d[0].data, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_13 = cat(_indexes_T_26, _indexes_T_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_28 = bits(cam_a[0].bits.data, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_29 = bits(cam_d[0].data, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_14 = cat(_indexes_T_28, _indexes_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_30 = bits(cam_a[0].bits.data, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_31 = bits(cam_d[0].data, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_15 = cat(_indexes_T_30, _indexes_T_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_32 = bits(cam_a[0].bits.data, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_33 = bits(cam_d[0].data, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_16 = cat(_indexes_T_32, _indexes_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_34 = bits(cam_a[0].bits.data, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_35 = bits(cam_d[0].data, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_17 = cat(_indexes_T_34, _indexes_T_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_36 = bits(cam_a[0].bits.data, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_37 = bits(cam_d[0].data, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_18 = cat(_indexes_T_36, _indexes_T_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_38 = bits(cam_a[0].bits.data, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_39 = bits(cam_d[0].data, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_19 = cat(_indexes_T_38, _indexes_T_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_40 = bits(cam_a[0].bits.data, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_41 = bits(cam_d[0].data, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_20 = cat(_indexes_T_40, _indexes_T_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_42 = bits(cam_a[0].bits.data, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_43 = bits(cam_d[0].data, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_21 = cat(_indexes_T_42, _indexes_T_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_44 = bits(cam_a[0].bits.data, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_45 = bits(cam_d[0].data, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_22 = cat(_indexes_T_44, _indexes_T_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_46 = bits(cam_a[0].bits.data, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_47 = bits(cam_d[0].data, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_23 = cat(_indexes_T_46, _indexes_T_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_48 = bits(cam_a[0].bits.data, 24, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_49 = bits(cam_d[0].data, 24, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_24 = cat(_indexes_T_48, _indexes_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_50 = bits(cam_a[0].bits.data, 25, 25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_51 = bits(cam_d[0].data, 25, 25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_25 = cat(_indexes_T_50, _indexes_T_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_52 = bits(cam_a[0].bits.data, 26, 26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_53 = bits(cam_d[0].data, 26, 26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_26 = cat(_indexes_T_52, _indexes_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_54 = bits(cam_a[0].bits.data, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_55 = bits(cam_d[0].data, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_27 = cat(_indexes_T_54, _indexes_T_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_56 = bits(cam_a[0].bits.data, 28, 28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_57 = bits(cam_d[0].data, 28, 28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_28 = cat(_indexes_T_56, _indexes_T_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_58 = bits(cam_a[0].bits.data, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_59 = bits(cam_d[0].data, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_29 = cat(_indexes_T_58, _indexes_T_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_60 = bits(cam_a[0].bits.data, 30, 30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_61 = bits(cam_d[0].data, 30, 30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_30 = cat(_indexes_T_60, _indexes_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_62 = bits(cam_a[0].bits.data, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_63 = bits(cam_d[0].data, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_31 = cat(_indexes_T_62, _indexes_T_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_64 = bits(cam_a[0].bits.data, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_65 = bits(cam_d[0].data, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_32 = cat(_indexes_T_64, _indexes_T_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_66 = bits(cam_a[0].bits.data, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_67 = bits(cam_d[0].data, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_33 = cat(_indexes_T_66, _indexes_T_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_68 = bits(cam_a[0].bits.data, 34, 34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_69 = bits(cam_d[0].data, 34, 34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_34 = cat(_indexes_T_68, _indexes_T_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_70 = bits(cam_a[0].bits.data, 35, 35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_71 = bits(cam_d[0].data, 35, 35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_35 = cat(_indexes_T_70, _indexes_T_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_72 = bits(cam_a[0].bits.data, 36, 36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_73 = bits(cam_d[0].data, 36, 36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_36 = cat(_indexes_T_72, _indexes_T_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_74 = bits(cam_a[0].bits.data, 37, 37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_75 = bits(cam_d[0].data, 37, 37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_37 = cat(_indexes_T_74, _indexes_T_75) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_76 = bits(cam_a[0].bits.data, 38, 38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_77 = bits(cam_d[0].data, 38, 38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_38 = cat(_indexes_T_76, _indexes_T_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_78 = bits(cam_a[0].bits.data, 39, 39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_79 = bits(cam_d[0].data, 39, 39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_39 = cat(_indexes_T_78, _indexes_T_79) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_80 = bits(cam_a[0].bits.data, 40, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_81 = bits(cam_d[0].data, 40, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_40 = cat(_indexes_T_80, _indexes_T_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_82 = bits(cam_a[0].bits.data, 41, 41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_83 = bits(cam_d[0].data, 41, 41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_41 = cat(_indexes_T_82, _indexes_T_83) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_84 = bits(cam_a[0].bits.data, 42, 42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_85 = bits(cam_d[0].data, 42, 42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_42 = cat(_indexes_T_84, _indexes_T_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_86 = bits(cam_a[0].bits.data, 43, 43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_87 = bits(cam_d[0].data, 43, 43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_43 = cat(_indexes_T_86, _indexes_T_87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_88 = bits(cam_a[0].bits.data, 44, 44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_89 = bits(cam_d[0].data, 44, 44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_44 = cat(_indexes_T_88, _indexes_T_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_90 = bits(cam_a[0].bits.data, 45, 45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_91 = bits(cam_d[0].data, 45, 45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_45 = cat(_indexes_T_90, _indexes_T_91) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_92 = bits(cam_a[0].bits.data, 46, 46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_93 = bits(cam_d[0].data, 46, 46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_46 = cat(_indexes_T_92, _indexes_T_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_94 = bits(cam_a[0].bits.data, 47, 47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_95 = bits(cam_d[0].data, 47, 47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_47 = cat(_indexes_T_94, _indexes_T_95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_96 = bits(cam_a[0].bits.data, 48, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_97 = bits(cam_d[0].data, 48, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_48 = cat(_indexes_T_96, _indexes_T_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_98 = bits(cam_a[0].bits.data, 49, 49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_99 = bits(cam_d[0].data, 49, 49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_49 = cat(_indexes_T_98, _indexes_T_99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_100 = bits(cam_a[0].bits.data, 50, 50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_101 = bits(cam_d[0].data, 50, 50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_50 = cat(_indexes_T_100, _indexes_T_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_102 = bits(cam_a[0].bits.data, 51, 51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_103 = bits(cam_d[0].data, 51, 51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_51 = cat(_indexes_T_102, _indexes_T_103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_104 = bits(cam_a[0].bits.data, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_105 = bits(cam_d[0].data, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_52 = cat(_indexes_T_104, _indexes_T_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_106 = bits(cam_a[0].bits.data, 53, 53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_107 = bits(cam_d[0].data, 53, 53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_53 = cat(_indexes_T_106, _indexes_T_107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_108 = bits(cam_a[0].bits.data, 54, 54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_109 = bits(cam_d[0].data, 54, 54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_54 = cat(_indexes_T_108, _indexes_T_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_110 = bits(cam_a[0].bits.data, 55, 55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_111 = bits(cam_d[0].data, 55, 55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_55 = cat(_indexes_T_110, _indexes_T_111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_112 = bits(cam_a[0].bits.data, 56, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_113 = bits(cam_d[0].data, 56, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_56 = cat(_indexes_T_112, _indexes_T_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_114 = bits(cam_a[0].bits.data, 57, 57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_115 = bits(cam_d[0].data, 57, 57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_57 = cat(_indexes_T_114, _indexes_T_115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_116 = bits(cam_a[0].bits.data, 58, 58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_117 = bits(cam_d[0].data, 58, 58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_58 = cat(_indexes_T_116, _indexes_T_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_118 = bits(cam_a[0].bits.data, 59, 59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_119 = bits(cam_d[0].data, 59, 59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_59 = cat(_indexes_T_118, _indexes_T_119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_120 = bits(cam_a[0].bits.data, 60, 60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_121 = bits(cam_d[0].data, 60, 60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_60 = cat(_indexes_T_120, _indexes_T_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_122 = bits(cam_a[0].bits.data, 61, 61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_123 = bits(cam_d[0].data, 61, 61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_61 = cat(_indexes_T_122, _indexes_T_123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_124 = bits(cam_a[0].bits.data, 62, 62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_125 = bits(cam_d[0].data, 62, 62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_62 = cat(_indexes_T_124, _indexes_T_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _indexes_T_126 = bits(cam_a[0].bits.data, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:63] node _indexes_T_127 = bits(cam_d[0].data, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:73] node indexes_63 = cat(_indexes_T_126, _indexes_T_127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 119:59] node _logic_out_T = dshr(cam_a[0].lut, indexes_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_1 = bits(_logic_out_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_2 = dshr(cam_a[0].lut, indexes_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_3 = bits(_logic_out_T_2, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_4 = dshr(cam_a[0].lut, indexes_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_5 = bits(_logic_out_T_4, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_6 = dshr(cam_a[0].lut, indexes_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_7 = bits(_logic_out_T_6, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_8 = dshr(cam_a[0].lut, indexes_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_9 = bits(_logic_out_T_8, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_10 = dshr(cam_a[0].lut, indexes_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_11 = bits(_logic_out_T_10, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_12 = dshr(cam_a[0].lut, indexes_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_13 = bits(_logic_out_T_12, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_14 = dshr(cam_a[0].lut, indexes_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_15 = bits(_logic_out_T_14, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_16 = dshr(cam_a[0].lut, indexes_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_17 = bits(_logic_out_T_16, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_18 = dshr(cam_a[0].lut, indexes_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_19 = bits(_logic_out_T_18, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_20 = dshr(cam_a[0].lut, indexes_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_21 = bits(_logic_out_T_20, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_22 = dshr(cam_a[0].lut, indexes_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_23 = bits(_logic_out_T_22, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_24 = dshr(cam_a[0].lut, indexes_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_25 = bits(_logic_out_T_24, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_26 = dshr(cam_a[0].lut, indexes_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_27 = bits(_logic_out_T_26, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_28 = dshr(cam_a[0].lut, indexes_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_29 = bits(_logic_out_T_28, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_30 = dshr(cam_a[0].lut, indexes_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_31 = bits(_logic_out_T_30, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_32 = dshr(cam_a[0].lut, indexes_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_33 = bits(_logic_out_T_32, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_34 = dshr(cam_a[0].lut, indexes_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_35 = bits(_logic_out_T_34, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_36 = dshr(cam_a[0].lut, indexes_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_37 = bits(_logic_out_T_36, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_38 = dshr(cam_a[0].lut, indexes_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_39 = bits(_logic_out_T_38, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_40 = dshr(cam_a[0].lut, indexes_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_41 = bits(_logic_out_T_40, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_42 = dshr(cam_a[0].lut, indexes_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_43 = bits(_logic_out_T_42, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_44 = dshr(cam_a[0].lut, indexes_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_45 = bits(_logic_out_T_44, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_46 = dshr(cam_a[0].lut, indexes_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_47 = bits(_logic_out_T_46, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_48 = dshr(cam_a[0].lut, indexes_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_49 = bits(_logic_out_T_48, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_50 = dshr(cam_a[0].lut, indexes_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_51 = bits(_logic_out_T_50, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_52 = dshr(cam_a[0].lut, indexes_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_53 = bits(_logic_out_T_52, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_54 = dshr(cam_a[0].lut, indexes_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_55 = bits(_logic_out_T_54, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_56 = dshr(cam_a[0].lut, indexes_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_57 = bits(_logic_out_T_56, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_58 = dshr(cam_a[0].lut, indexes_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_59 = bits(_logic_out_T_58, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_60 = dshr(cam_a[0].lut, indexes_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_61 = bits(_logic_out_T_60, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_62 = dshr(cam_a[0].lut, indexes_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_63 = bits(_logic_out_T_62, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_64 = dshr(cam_a[0].lut, indexes_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_65 = bits(_logic_out_T_64, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_66 = dshr(cam_a[0].lut, indexes_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_67 = bits(_logic_out_T_66, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_68 = dshr(cam_a[0].lut, indexes_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_69 = bits(_logic_out_T_68, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_70 = dshr(cam_a[0].lut, indexes_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_71 = bits(_logic_out_T_70, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_72 = dshr(cam_a[0].lut, indexes_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_73 = bits(_logic_out_T_72, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_74 = dshr(cam_a[0].lut, indexes_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_75 = bits(_logic_out_T_74, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_76 = dshr(cam_a[0].lut, indexes_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_77 = bits(_logic_out_T_76, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_78 = dshr(cam_a[0].lut, indexes_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_79 = bits(_logic_out_T_78, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_80 = dshr(cam_a[0].lut, indexes_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_81 = bits(_logic_out_T_80, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_82 = dshr(cam_a[0].lut, indexes_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_83 = bits(_logic_out_T_82, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_84 = dshr(cam_a[0].lut, indexes_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_85 = bits(_logic_out_T_84, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_86 = dshr(cam_a[0].lut, indexes_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_87 = bits(_logic_out_T_86, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_88 = dshr(cam_a[0].lut, indexes_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_89 = bits(_logic_out_T_88, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_90 = dshr(cam_a[0].lut, indexes_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_91 = bits(_logic_out_T_90, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_92 = dshr(cam_a[0].lut, indexes_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_93 = bits(_logic_out_T_92, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_94 = dshr(cam_a[0].lut, indexes_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_95 = bits(_logic_out_T_94, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_96 = dshr(cam_a[0].lut, indexes_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_97 = bits(_logic_out_T_96, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_98 = dshr(cam_a[0].lut, indexes_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_99 = bits(_logic_out_T_98, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_100 = dshr(cam_a[0].lut, indexes_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_101 = bits(_logic_out_T_100, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_102 = dshr(cam_a[0].lut, indexes_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_103 = bits(_logic_out_T_102, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_104 = dshr(cam_a[0].lut, indexes_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_105 = bits(_logic_out_T_104, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_106 = dshr(cam_a[0].lut, indexes_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_107 = bits(_logic_out_T_106, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_108 = dshr(cam_a[0].lut, indexes_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_109 = bits(_logic_out_T_108, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_110 = dshr(cam_a[0].lut, indexes_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_111 = bits(_logic_out_T_110, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_112 = dshr(cam_a[0].lut, indexes_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_113 = bits(_logic_out_T_112, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_114 = dshr(cam_a[0].lut, indexes_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_115 = bits(_logic_out_T_114, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_116 = dshr(cam_a[0].lut, indexes_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_117 = bits(_logic_out_T_116, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_118 = dshr(cam_a[0].lut, indexes_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_119 = bits(_logic_out_T_118, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_120 = dshr(cam_a[0].lut, indexes_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_121 = bits(_logic_out_T_120, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_122 = dshr(cam_a[0].lut, indexes_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_123 = bits(_logic_out_T_122, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_124 = dshr(cam_a[0].lut, indexes_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_125 = bits(_logic_out_T_124, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_126 = dshr(cam_a[0].lut, indexes_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node _logic_out_T_127 = bits(_logic_out_T_126, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:57] node logic_out_lo_lo_lo_lo_lo = cat(_logic_out_T_3, _logic_out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_lo_lo_hi = cat(_logic_out_T_7, _logic_out_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_lo_lo = cat(logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_lo_hi_lo = cat(_logic_out_T_11, _logic_out_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_lo_hi_hi = cat(_logic_out_T_15, _logic_out_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_lo_hi = cat(logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_lo = cat(logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_hi_lo_lo = cat(_logic_out_T_19, _logic_out_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_hi_lo_hi = cat(_logic_out_T_23, _logic_out_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_hi_lo = cat(logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_hi_hi_lo = cat(_logic_out_T_27, _logic_out_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_hi_hi_hi = cat(_logic_out_T_31, _logic_out_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_hi_hi = cat(logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo_hi = cat(logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_lo = cat(logic_out_lo_lo_hi, logic_out_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_lo_lo_lo = cat(_logic_out_T_35, _logic_out_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_lo_lo_hi = cat(_logic_out_T_39, _logic_out_T_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_lo_lo = cat(logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_lo_hi_lo = cat(_logic_out_T_43, _logic_out_T_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_lo_hi_hi = cat(_logic_out_T_47, _logic_out_T_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_lo_hi = cat(logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_lo = cat(logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_hi_lo_lo = cat(_logic_out_T_51, _logic_out_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_hi_lo_hi = cat(_logic_out_T_55, _logic_out_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_hi_lo = cat(logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_hi_hi_lo = cat(_logic_out_T_59, _logic_out_T_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_hi_hi_hi = cat(_logic_out_T_63, _logic_out_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_hi_hi = cat(logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi_hi = cat(logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo_hi = cat(logic_out_lo_hi_hi, logic_out_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_lo = cat(logic_out_lo_hi, logic_out_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_lo_lo_lo = cat(_logic_out_T_67, _logic_out_T_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_lo_lo_hi = cat(_logic_out_T_71, _logic_out_T_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_lo_lo = cat(logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_lo_hi_lo = cat(_logic_out_T_75, _logic_out_T_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_lo_hi_hi = cat(_logic_out_T_79, _logic_out_T_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_lo_hi = cat(logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_lo = cat(logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_hi_lo_lo = cat(_logic_out_T_83, _logic_out_T_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_hi_lo_hi = cat(_logic_out_T_87, _logic_out_T_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_hi_lo = cat(logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_hi_hi_lo = cat(_logic_out_T_91, _logic_out_T_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_hi_hi_hi = cat(_logic_out_T_95, _logic_out_T_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_hi_hi = cat(logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo_hi = cat(logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_lo = cat(logic_out_hi_lo_hi, logic_out_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_lo_lo_lo = cat(_logic_out_T_99, _logic_out_T_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_lo_lo_hi = cat(_logic_out_T_103, _logic_out_T_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_lo_lo = cat(logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_lo_hi_lo = cat(_logic_out_T_107, _logic_out_T_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_lo_hi_hi = cat(_logic_out_T_111, _logic_out_T_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_lo_hi = cat(logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_lo = cat(logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_hi_lo_lo = cat(_logic_out_T_115, _logic_out_T_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_hi_lo_hi = cat(_logic_out_T_119, _logic_out_T_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_hi_lo = cat(logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_hi_hi_lo = cat(_logic_out_T_123, _logic_out_T_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_hi_hi_hi = cat(_logic_out_T_127, _logic_out_T_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_hi_hi = cat(logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi_hi = cat(logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi_hi = cat(logic_out_hi_hi_hi, logic_out_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out_hi = cat(logic_out_hi_hi, logic_out_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node logic_out = cat(logic_out_hi, logic_out_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 120:28] node unsigned = bits(cam_a[0].bits.param, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 123:42] node take_max = bits(cam_a[0].bits.param, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 124:42] node adder = bits(cam_a[0].bits.param, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 125:39] node _signSel_T = not(cam_a[0].bits.mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 127:25] node _signSel_T_1 = shr(cam_a[0].bits.mask, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 127:39] node _signSel_T_2 = or(_signSel_T, _signSel_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 127:31] node signSel = not(_signSel_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 127:23] node _signbits_a_T = bits(cam_a[0].bits.data, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:64] node _signbits_a_T_1 = bits(cam_a[0].bits.data, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:64] node _signbits_a_T_2 = bits(cam_a[0].bits.data, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:64] node _signbits_a_T_3 = bits(cam_a[0].bits.data, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:64] node _signbits_a_T_4 = bits(cam_a[0].bits.data, 39, 39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:64] node _signbits_a_T_5 = bits(cam_a[0].bits.data, 47, 47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:64] node _signbits_a_T_6 = bits(cam_a[0].bits.data, 55, 55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:64] node _signbits_a_T_7 = bits(cam_a[0].bits.data, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:64] node signbits_a_lo_lo = cat(_signbits_a_T_1, _signbits_a_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:29] node signbits_a_lo_hi = cat(_signbits_a_T_3, _signbits_a_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:29] node signbits_a_lo = cat(signbits_a_lo_hi, signbits_a_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:29] node signbits_a_hi_lo = cat(_signbits_a_T_5, _signbits_a_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:29] node signbits_a_hi_hi = cat(_signbits_a_T_7, _signbits_a_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:29] node signbits_a_hi = cat(signbits_a_hi_hi, signbits_a_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:29] node signbits_a = cat(signbits_a_hi, signbits_a_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 128:29] node _signbits_d_T = bits(cam_d[0].data, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:64] node _signbits_d_T_1 = bits(cam_d[0].data, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:64] node _signbits_d_T_2 = bits(cam_d[0].data, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:64] node _signbits_d_T_3 = bits(cam_d[0].data, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:64] node _signbits_d_T_4 = bits(cam_d[0].data, 39, 39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:64] node _signbits_d_T_5 = bits(cam_d[0].data, 47, 47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:64] node _signbits_d_T_6 = bits(cam_d[0].data, 55, 55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:64] node _signbits_d_T_7 = bits(cam_d[0].data, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:64] node signbits_d_lo_lo = cat(_signbits_d_T_1, _signbits_d_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:29] node signbits_d_lo_hi = cat(_signbits_d_T_3, _signbits_d_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:29] node signbits_d_lo = cat(signbits_d_lo_hi, signbits_d_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:29] node signbits_d_hi_lo = cat(_signbits_d_T_5, _signbits_d_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:29] node signbits_d_hi_hi = cat(_signbits_d_T_7, _signbits_d_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:29] node signbits_d_hi = cat(signbits_d_hi_hi, signbits_d_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:29] node signbits_d = cat(signbits_d_hi, signbits_d_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 129:29] node _signbit_a_T = and(signbits_a, signSel) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 131:38] node _signbit_a_T_1 = shl(_signbit_a_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 131:49] node signbit_a = bits(_signbit_a_T_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 131:54] node _signbit_d_T = and(signbits_d, signSel) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 132:38] node _signbit_d_T_1 = shl(_signbit_d_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 132:49] node signbit_d = bits(_signbit_d_T_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 132:54] node _signext_a_T = shl(signbit_a, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _signext_a_T_1 = bits(_signext_a_T, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _signext_a_T_2 = or(signbit_a, _signext_a_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _signext_a_T_3 = shl(_signext_a_T_2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _signext_a_T_4 = bits(_signext_a_T_3, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _signext_a_T_5 = or(_signext_a_T_2, _signext_a_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _signext_a_T_6 = shl(_signext_a_T_5, 4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _signext_a_T_7 = bits(_signext_a_T_6, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _signext_a_T_8 = or(_signext_a_T_5, _signext_a_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _signext_a_T_9 = bits(_signext_a_T_8, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 255:17] node _signext_a_T_10 = bits(_signext_a_T_9, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_11 = bits(_signext_a_T_9, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_12 = bits(_signext_a_T_9, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_13 = bits(_signext_a_T_9, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_14 = bits(_signext_a_T_9, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_15 = bits(_signext_a_T_9, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_16 = bits(_signext_a_T_9, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_17 = bits(_signext_a_T_9, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_18 = mux(_signext_a_T_10, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_19 = mux(_signext_a_T_11, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_20 = mux(_signext_a_T_12, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_21 = mux(_signext_a_T_13, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_22 = mux(_signext_a_T_14, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_23 = mux(_signext_a_T_15, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_24 = mux(_signext_a_T_16, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_a_T_25 = mux(_signext_a_T_17, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node signext_a_lo_lo = cat(_signext_a_T_19, _signext_a_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node signext_a_lo_hi = cat(_signext_a_T_21, _signext_a_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node signext_a_lo = cat(signext_a_lo_hi, signext_a_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node signext_a_hi_lo = cat(_signext_a_T_23, _signext_a_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node signext_a_hi_hi = cat(_signext_a_T_25, _signext_a_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node signext_a_hi = cat(signext_a_hi_hi, signext_a_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node signext_a = cat(signext_a_hi, signext_a_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 133:40] node _signext_d_T = shl(signbit_d, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _signext_d_T_1 = bits(_signext_d_T, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _signext_d_T_2 = or(signbit_d, _signext_d_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _signext_d_T_3 = shl(_signext_d_T_2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _signext_d_T_4 = bits(_signext_d_T_3, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _signext_d_T_5 = or(_signext_d_T_2, _signext_d_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _signext_d_T_6 = shl(_signext_d_T_5, 4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _signext_d_T_7 = bits(_signext_d_T_6, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _signext_d_T_8 = or(_signext_d_T_5, _signext_d_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _signext_d_T_9 = bits(_signext_d_T_8, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 255:17] node _signext_d_T_10 = bits(_signext_d_T_9, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_11 = bits(_signext_d_T_9, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_12 = bits(_signext_d_T_9, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_13 = bits(_signext_d_T_9, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_14 = bits(_signext_d_T_9, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_15 = bits(_signext_d_T_9, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_16 = bits(_signext_d_T_9, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_17 = bits(_signext_d_T_9, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_18 = mux(_signext_d_T_10, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_19 = mux(_signext_d_T_11, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_20 = mux(_signext_d_T_12, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_21 = mux(_signext_d_T_13, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_22 = mux(_signext_d_T_14, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_23 = mux(_signext_d_T_15, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_24 = mux(_signext_d_T_16, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _signext_d_T_25 = mux(_signext_d_T_17, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node signext_d_lo_lo = cat(_signext_d_T_19, _signext_d_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node signext_d_lo_hi = cat(_signext_d_T_21, _signext_d_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node signext_d_lo = cat(signext_d_lo_hi, signext_d_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node signext_d_hi_lo = cat(_signext_d_T_23, _signext_d_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node signext_d_hi_hi = cat(_signext_d_T_25, _signext_d_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node signext_d_hi = cat(signext_d_hi_hi, signext_d_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node signext_d = cat(signext_d_hi, signext_d_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 134:40] node _wide_mask_T = bits(cam_a[0].bits.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_1 = bits(cam_a[0].bits.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_2 = bits(cam_a[0].bits.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_3 = bits(cam_a[0].bits.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_4 = bits(cam_a[0].bits.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_5 = bits(cam_a[0].bits.mask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_6 = bits(cam_a[0].bits.mask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_7 = bits(cam_a[0].bits.mask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_8 = mux(_wide_mask_T, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_9 = mux(_wide_mask_T_1, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_10 = mux(_wide_mask_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_11 = mux(_wide_mask_T_3, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_12 = mux(_wide_mask_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_13 = mux(_wide_mask_T_5, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_14 = mux(_wide_mask_T_6, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _wide_mask_T_15 = mux(_wide_mask_T_7, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node wide_mask_lo_lo = cat(_wide_mask_T_9, _wide_mask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node wide_mask_lo_hi = cat(_wide_mask_T_11, _wide_mask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node wide_mask_lo = cat(wide_mask_lo_hi, wide_mask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node wide_mask_hi_lo = cat(_wide_mask_T_13, _wide_mask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node wide_mask_hi_hi = cat(_wide_mask_T_15, _wide_mask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node wide_mask_hi = cat(wide_mask_hi_hi, wide_mask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node wide_mask = cat(wide_mask_hi, wide_mask_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 136:40] node _a_a_ext_T = and(cam_a[0].bits.data, wide_mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 137:28] node a_a_ext = or(_a_a_ext_T, signext_a) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 137:41] node _a_d_ext_T = and(cam_d[0].data, wide_mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 138:28] node a_d_ext = or(_a_d_ext_T, signext_d) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 138:41] node _a_d_inv_T = not(a_d_ext) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 139:43] node a_d_inv = mux(adder, a_d_ext, _a_d_inv_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 139:26] node _adder_out_T = add(a_a_ext, a_d_inv) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 140:33] node adder_out = tail(_adder_out_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 140:33] node _a_bigger_uneq_T = bits(a_a_ext, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 142:49] node a_bigger_uneq = eq(unsigned, _a_bigger_uneq_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 142:38] node _a_bigger_T = bits(a_a_ext, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 143:35] node _a_bigger_T_1 = bits(a_d_ext, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 143:50] node _a_bigger_T_2 = eq(_a_bigger_T, _a_bigger_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 143:39] node _a_bigger_T_3 = bits(adder_out, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 143:65] node _a_bigger_T_4 = eq(_a_bigger_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 143:55] node a_bigger = mux(_a_bigger_T_2, _a_bigger_T_4, a_bigger_uneq) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 143:27] node pick_a = eq(take_max, a_bigger) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 144:31] node _arith_out_T = mux(pick_a, cam_a[0].bits.data, cam_d[0].data) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 145:50] node arith_out = mux(adder, adder_out, _arith_out_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 145:28] node _amo_data_T = bits(cam_a[0].bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 151:34] node amo_data = mux(_amo_data_T, logic_out, arith_out) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 151:14] wire source_i : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 154:28] node _a_allow_T = eq(a_cam_busy, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 155:23] node _a_allow_T_1 = or(a_isSupported, cam_free_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 155:53] node a_allow = and(_a_allow_T, _a_allow_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 155:35] node _nodeIn_a_ready_T = and(source_i.ready, a_allow) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 156:38] connect nodeIn.a.ready, _nodeIn_a_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 156:20] node _source_i_valid_T = and(nodeIn.a.valid, a_allow) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 157:38] connect source_i.valid, _source_i_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 157:24] connect source_i.bits, nodeIn.a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 158:24] node _T = eq(a_isSupported, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 159:15] when _T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 159:31] connect source_i.bits.opcode, UInt<3>(0h4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 160:32] connect source_i.bits.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 161:32] wire source_c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 165:28] connect source_c.valid, cam_amo_0 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 166:24] node _source_c_bits_T = or(cam_a[0].bits.corrupt, cam_d[0].corrupt) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 172:45] node _source_c_bits_legal_T = leq(UInt<1>(0h0), cam_a[0].bits.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _source_c_bits_legal_T_1 = leq(cam_a[0].bits.size, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _source_c_bits_legal_T_2 = and(_source_c_bits_legal_T, _source_c_bits_legal_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _source_c_bits_legal_T_3 = or(UInt<1>(0h0), _source_c_bits_legal_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _source_c_bits_legal_T_4 = xor(cam_a[0].bits.address, UInt<14>(0h2000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _source_c_bits_legal_T_5 = cvt(_source_c_bits_legal_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _source_c_bits_legal_T_6 = and(_source_c_bits_legal_T_5, asSInt(UInt<33>(0hfa01e000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_7 = asSInt(_source_c_bits_legal_T_6) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_8 = eq(_source_c_bits_legal_T_7, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _source_c_bits_legal_T_9 = and(_source_c_bits_legal_T_3, _source_c_bits_legal_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _source_c_bits_legal_T_10 = leq(UInt<1>(0h0), cam_a[0].bits.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _source_c_bits_legal_T_11 = leq(cam_a[0].bits.size, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _source_c_bits_legal_T_12 = and(_source_c_bits_legal_T_10, _source_c_bits_legal_T_11) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _source_c_bits_legal_T_13 = or(UInt<1>(0h0), _source_c_bits_legal_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _source_c_bits_legal_T_14 = xor(cam_a[0].bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _source_c_bits_legal_T_15 = cvt(_source_c_bits_legal_T_14) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _source_c_bits_legal_T_16 = and(_source_c_bits_legal_T_15, asSInt(UInt<33>(0hfa01e000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_17 = asSInt(_source_c_bits_legal_T_16) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_18 = eq(_source_c_bits_legal_T_17, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _source_c_bits_legal_T_19 = xor(cam_a[0].bits.address, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _source_c_bits_legal_T_20 = cvt(_source_c_bits_legal_T_19) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _source_c_bits_legal_T_21 = and(_source_c_bits_legal_T_20, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_22 = asSInt(_source_c_bits_legal_T_21) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_23 = eq(_source_c_bits_legal_T_22, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _source_c_bits_legal_T_24 = xor(cam_a[0].bits.address, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _source_c_bits_legal_T_25 = cvt(_source_c_bits_legal_T_24) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _source_c_bits_legal_T_26 = and(_source_c_bits_legal_T_25, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_27 = asSInt(_source_c_bits_legal_T_26) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_28 = eq(_source_c_bits_legal_T_27, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _source_c_bits_legal_T_29 = xor(cam_a[0].bits.address, UInt<29>(0h10000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _source_c_bits_legal_T_30 = cvt(_source_c_bits_legal_T_29) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _source_c_bits_legal_T_31 = and(_source_c_bits_legal_T_30, asSInt(UInt<33>(0hfa018000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_32 = asSInt(_source_c_bits_legal_T_31) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_33 = eq(_source_c_bits_legal_T_32, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _source_c_bits_legal_T_34 = xor(cam_a[0].bits.address, UInt<29>(0h10008000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _source_c_bits_legal_T_35 = cvt(_source_c_bits_legal_T_34) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _source_c_bits_legal_T_36 = and(_source_c_bits_legal_T_35, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_37 = asSInt(_source_c_bits_legal_T_36) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_38 = eq(_source_c_bits_legal_T_37, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _source_c_bits_legal_T_39 = xor(cam_a[0].bits.address, UInt<29>(0h10012000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _source_c_bits_legal_T_40 = cvt(_source_c_bits_legal_T_39) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _source_c_bits_legal_T_41 = and(_source_c_bits_legal_T_40, asSInt(UInt<33>(0hfa01e000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_42 = asSInt(_source_c_bits_legal_T_41) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_43 = eq(_source_c_bits_legal_T_42, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _source_c_bits_legal_T_44 = xor(cam_a[0].bits.address, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _source_c_bits_legal_T_45 = cvt(_source_c_bits_legal_T_44) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _source_c_bits_legal_T_46 = and(_source_c_bits_legal_T_45, asSInt(UInt<33>(0hfa01e000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_47 = asSInt(_source_c_bits_legal_T_46) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_48 = eq(_source_c_bits_legal_T_47, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _source_c_bits_legal_T_49 = xor(cam_a[0].bits.address, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _source_c_bits_legal_T_50 = cvt(_source_c_bits_legal_T_49) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _source_c_bits_legal_T_51 = and(_source_c_bits_legal_T_50, asSInt(UInt<33>(0hfa000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_52 = asSInt(_source_c_bits_legal_T_51) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_53 = eq(_source_c_bits_legal_T_52, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _source_c_bits_legal_T_54 = or(_source_c_bits_legal_T_18, _source_c_bits_legal_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _source_c_bits_legal_T_55 = or(_source_c_bits_legal_T_54, _source_c_bits_legal_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _source_c_bits_legal_T_56 = or(_source_c_bits_legal_T_55, _source_c_bits_legal_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _source_c_bits_legal_T_57 = or(_source_c_bits_legal_T_56, _source_c_bits_legal_T_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _source_c_bits_legal_T_58 = or(_source_c_bits_legal_T_57, _source_c_bits_legal_T_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _source_c_bits_legal_T_59 = or(_source_c_bits_legal_T_58, _source_c_bits_legal_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _source_c_bits_legal_T_60 = or(_source_c_bits_legal_T_59, _source_c_bits_legal_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _source_c_bits_legal_T_61 = and(_source_c_bits_legal_T_13, _source_c_bits_legal_T_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _source_c_bits_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _source_c_bits_legal_T_63 = xor(cam_a[0].bits.address, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _source_c_bits_legal_T_64 = cvt(_source_c_bits_legal_T_63) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _source_c_bits_legal_T_65 = and(_source_c_bits_legal_T_64, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_66 = asSInt(_source_c_bits_legal_T_65) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _source_c_bits_legal_T_67 = eq(_source_c_bits_legal_T_66, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _source_c_bits_legal_T_68 = and(_source_c_bits_legal_T_62, _source_c_bits_legal_T_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _source_c_bits_legal_T_69 = or(UInt<1>(0h0), _source_c_bits_legal_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node _source_c_bits_legal_T_70 = or(_source_c_bits_legal_T_69, _source_c_bits_legal_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node source_c_bits_legal = or(_source_c_bits_legal_T_70, _source_c_bits_legal_T_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire source_c_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 480:17] connect source_c_bits_a.opcode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 481:15] connect source_c_bits_a.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 482:15] connect source_c_bits_a.size, cam_a[0].bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 483:15] connect source_c_bits_a.source, cam_a[0].bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 484:15] connect source_c_bits_a.address, cam_a[0].bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 485:15] invalidate source_c_bits_a.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate source_c_bits_a.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate source_c_bits_a.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate source_c_bits_a.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate source_c_bits_a.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate source_c_bits_a.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate source_c_bits_a.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] node _source_c_bits_a_mask_sizeOH_T = or(cam_a[0].bits.size, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node source_c_bits_a_mask_sizeOH_shiftAmount = bits(_source_c_bits_a_mask_sizeOH_T, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _source_c_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), source_c_bits_a_mask_sizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _source_c_bits_a_mask_sizeOH_T_2 = bits(_source_c_bits_a_mask_sizeOH_T_1, 2, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node source_c_bits_a_mask_sizeOH = or(_source_c_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] node source_c_bits_a_mask_sub_sub_sub_0_1 = geq(cam_a[0].bits.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 206:21] node source_c_bits_a_mask_sub_sub_size = bits(source_c_bits_a_mask_sizeOH, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node source_c_bits_a_mask_sub_sub_bit = bits(cam_a[0].bits.address, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node source_c_bits_a_mask_sub_sub_nbit = eq(source_c_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node source_c_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_sub_sub_acc_T = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_0_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_sub_sub_0_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_sub_sub_acc_T_1 = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_1_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_sub_sub_1_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_sub_size = bits(source_c_bits_a_mask_sizeOH, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node source_c_bits_a_mask_sub_bit = bits(cam_a[0].bits.address, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node source_c_bits_a_mask_sub_nbit = eq(source_c_bits_a_mask_sub_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node source_c_bits_a_mask_sub_0_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_sub_acc_T = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_0_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_sub_0_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_sub_1_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_sub_acc_T_1 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_1_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_sub_1_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_sub_2_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_sub_acc_T_2 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_2_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_sub_2_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_sub_3_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_sub_acc_T_3 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_3_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_sub_3_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_size = bits(source_c_bits_a_mask_sizeOH, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node source_c_bits_a_mask_bit = bits(cam_a[0].bits.address, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node source_c_bits_a_mask_nbit = eq(source_c_bits_a_mask_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node source_c_bits_a_mask_eq = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_acc_T = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_acc = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_eq_1 = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_acc_T_1 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_acc_1 = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_eq_2 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_acc_T_2 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_acc_2 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_eq_3 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_acc_T_3 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_acc_3 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_eq_4 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_acc_T_4 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_acc_4 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_eq_5 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_acc_T_5 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_acc_5 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_eq_6 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_acc_T_6 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_acc_6 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_eq_7 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _source_c_bits_a_mask_acc_T_7 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node source_c_bits_a_mask_acc_7 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node source_c_bits_a_mask_lo_lo = cat(source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node source_c_bits_a_mask_lo_hi = cat(source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node source_c_bits_a_mask_lo = cat(source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node source_c_bits_a_mask_hi_lo = cat(source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node source_c_bits_a_mask_hi_hi = cat(source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node source_c_bits_a_mask_hi = cat(source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node _source_c_bits_a_mask_T = cat(source_c_bits_a_mask_hi, source_c_bits_a_mask_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] connect source_c_bits_a.mask, _source_c_bits_a_mask_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 488:15] connect source_c_bits_a.data, amo_data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 489:15] connect source_c_bits_a.corrupt, _source_c_bits_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 490:15] connect source_c.bits, source_c_bits_a @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 167:23] connect source_c.bits.user.amba_prot.fetch, cam_a[0].bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 173:28] connect source_c.bits.user.amba_prot.secure, cam_a[0].bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 173:28] connect source_c.bits.user.amba_prot.privileged, cam_a[0].bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 173:28] connect source_c.bits.user.amba_prot.writealloc, cam_a[0].bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 173:28] connect source_c.bits.user.amba_prot.readalloc, cam_a[0].bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 173:28] connect source_c.bits.user.amba_prot.modifiable, cam_a[0].bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 173:28] connect source_c.bits.user.amba_prot.bufferable, cam_a[0].bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 173:28] node _decode_T = dshl(UInt<12>(0hfff), nodeIn.a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _decode_T_1 = bits(_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _decode_T_2 = not(_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node decode = shr(_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node opdata = eq(_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node _T_1 = mux(opdata, decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 60:30] node idle = eq(beatsLeft, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 61:28] node latch = and(idle, nodeOut.a.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 62:24] node _readys_T = cat(source_i.valid, source_c.valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:51] node _readys_T_1 = shl(_readys_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _readys_T_2 = bits(_readys_T_1, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _readys_T_3 = or(_readys_T, _readys_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _readys_T_4 = bits(_readys_T_3, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 255:17] node _readys_T_5 = shl(_readys_T_4, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 16:78] node _readys_T_6 = bits(_readys_T_5, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 16:83] node _readys_T_7 = not(_readys_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 16:61] node _readys_T_8 = bits(_readys_T_7, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] node _readys_T_9 = bits(_readys_T_7, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] wire readys : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[0], _readys_T_8 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[1], _readys_T_9 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] node _winner_T = and(readys[0], source_c.valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] node _winner_T_1 = and(readys[1], source_i.valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] wire winner : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[0], _winner_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[1], _winner_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] node prefixOR_1 = or(UInt<1>(0h0), winner[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node _prefixOR_T = or(prefixOR_1, winner[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node _T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_3 = eq(winner[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_4 = or(_T_2, _T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_5 = eq(prefixOR_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_6 = eq(winner[1], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_7 = or(_T_5, _T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_8 = and(_T_4, _T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:77] node _T_9 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_10 = eq(_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] when _T_10 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_11 = eq(_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] when _T_11 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] assert(clock, _T_8, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_12 = or(source_c.valid, source_i.valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:31] node _T_13 = eq(_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:15] node _T_14 = or(winner[0], winner[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:54] node _T_15 = or(_T_13, _T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:36] node _T_16 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node _T_17 = eq(_T_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] when _T_17 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node _T_18 = eq(_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] when _T_18 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] assert(clock, _T_15, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node maskedBeats_0 = mux(winner[0], UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node maskedBeats_1 = mux(winner[1], _T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node initBeats = or(maskedBeats_0, maskedBeats_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 84:44] node _beatsLeft_T = and(nodeOut.a.ready, nodeOut.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:52] node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:52] node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:23] connect beatsLeft, _beatsLeft_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:17] wire _state_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] regreset state : UInt<1>[2], clock, reset, _state_WIRE @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:26] node muxState = mux(idle, winner, state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 89:25] connect state, muxState @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 90:13] node allowed = mux(idle, readys, state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 92:24] node _source_c_ready_T = and(nodeOut.a.ready, allowed[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect source_c.ready, _source_c_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _source_i_ready_T = and(nodeOut.a.ready, allowed[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect source_i.ready, _source_i_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _nodeOut_a_valid_T = or(source_c.valid, source_i.valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:46] node _nodeOut_a_valid_T_1 = mux(state[0], source_c.valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_valid_T_2 = mux(state[1], source_i.valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_valid_T_3 = or(_nodeOut_a_valid_T_1, _nodeOut_a_valid_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_valid_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_valid_WIRE, _nodeOut_a_valid_T_3 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_valid_T_4 = mux(idle, _nodeOut_a_valid_T, _nodeOut_a_valid_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:24] connect nodeOut.a.valid, _nodeOut_a_valid_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:18] wire _nodeOut_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T = mux(muxState[0], source_c.bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_1 = mux(muxState[1], source_i.bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_2 = or(_nodeOut_a_bits_T, _nodeOut_a_bits_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_1 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_1, _nodeOut_a_bits_T_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.corrupt, _nodeOut_a_bits_WIRE_1 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_3 = mux(muxState[0], source_c.bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_4 = mux(muxState[1], source_i.bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_5 = or(_nodeOut_a_bits_T_3, _nodeOut_a_bits_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_2 : UInt<64> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_2, _nodeOut_a_bits_T_5 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.data, _nodeOut_a_bits_WIRE_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_6 = mux(muxState[0], source_c.bits.mask, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_7 = mux(muxState[1], source_i.bits.mask, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_8 = or(_nodeOut_a_bits_T_6, _nodeOut_a_bits_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_3 : UInt<8> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_3, _nodeOut_a_bits_T_8 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.mask, _nodeOut_a_bits_WIRE_3 @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_4 : { } @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.echo, _nodeOut_a_bits_WIRE_4 @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_5 : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}} @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_6 : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>} @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_9 = mux(muxState[0], source_c.bits.user.amba_prot.fetch, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_10 = mux(muxState[1], source_i.bits.user.amba_prot.fetch, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_11 = or(_nodeOut_a_bits_T_9, _nodeOut_a_bits_T_10) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_7 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_7, _nodeOut_a_bits_T_11 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_6.fetch, _nodeOut_a_bits_WIRE_7 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_12 = mux(muxState[0], source_c.bits.user.amba_prot.secure, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_13 = mux(muxState[1], source_i.bits.user.amba_prot.secure, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_14 = or(_nodeOut_a_bits_T_12, _nodeOut_a_bits_T_13) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_8 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_8, _nodeOut_a_bits_T_14 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_6.secure, _nodeOut_a_bits_WIRE_8 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_15 = mux(muxState[0], source_c.bits.user.amba_prot.privileged, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_16 = mux(muxState[1], source_i.bits.user.amba_prot.privileged, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_17 = or(_nodeOut_a_bits_T_15, _nodeOut_a_bits_T_16) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_9 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_9, _nodeOut_a_bits_T_17 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_6.privileged, _nodeOut_a_bits_WIRE_9 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_18 = mux(muxState[0], source_c.bits.user.amba_prot.writealloc, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_19 = mux(muxState[1], source_i.bits.user.amba_prot.writealloc, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_20 = or(_nodeOut_a_bits_T_18, _nodeOut_a_bits_T_19) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_10 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_10, _nodeOut_a_bits_T_20 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_6.writealloc, _nodeOut_a_bits_WIRE_10 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_21 = mux(muxState[0], source_c.bits.user.amba_prot.readalloc, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_22 = mux(muxState[1], source_i.bits.user.amba_prot.readalloc, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_23 = or(_nodeOut_a_bits_T_21, _nodeOut_a_bits_T_22) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_11 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_11, _nodeOut_a_bits_T_23 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_6.readalloc, _nodeOut_a_bits_WIRE_11 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_24 = mux(muxState[0], source_c.bits.user.amba_prot.modifiable, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_25 = mux(muxState[1], source_i.bits.user.amba_prot.modifiable, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_26 = or(_nodeOut_a_bits_T_24, _nodeOut_a_bits_T_25) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_12 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_12, _nodeOut_a_bits_T_26 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_6.modifiable, _nodeOut_a_bits_WIRE_12 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_27 = mux(muxState[0], source_c.bits.user.amba_prot.bufferable, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_28 = mux(muxState[1], source_i.bits.user.amba_prot.bufferable, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_29 = or(_nodeOut_a_bits_T_27, _nodeOut_a_bits_T_28) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_13 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_13, _nodeOut_a_bits_T_29 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_6.bufferable, _nodeOut_a_bits_WIRE_13 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_5.amba_prot, _nodeOut_a_bits_WIRE_6 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.user, _nodeOut_a_bits_WIRE_5 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_30 = mux(muxState[0], source_c.bits.address, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_31 = mux(muxState[1], source_i.bits.address, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_32 = or(_nodeOut_a_bits_T_30, _nodeOut_a_bits_T_31) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_14 : UInt<32> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_14, _nodeOut_a_bits_T_32 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.address, _nodeOut_a_bits_WIRE_14 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_33 = mux(muxState[0], source_c.bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_34 = mux(muxState[1], source_i.bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_35 = or(_nodeOut_a_bits_T_33, _nodeOut_a_bits_T_34) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_15 : UInt<2> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_15, _nodeOut_a_bits_T_35 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.source, _nodeOut_a_bits_WIRE_15 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_36 = mux(muxState[0], source_c.bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_37 = mux(muxState[1], source_i.bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_38 = or(_nodeOut_a_bits_T_36, _nodeOut_a_bits_T_37) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_16 : UInt<4> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_16, _nodeOut_a_bits_T_38 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.size, _nodeOut_a_bits_WIRE_16 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_39 = mux(muxState[0], source_c.bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_40 = mux(muxState[1], source_i.bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_41 = or(_nodeOut_a_bits_T_39, _nodeOut_a_bits_T_40) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_17 : UInt<3> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_17, _nodeOut_a_bits_T_41 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.param, _nodeOut_a_bits_WIRE_17 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_42 = mux(muxState[0], source_c.bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_43 = mux(muxState[1], source_i.bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeOut_a_bits_T_44 = or(_nodeOut_a_bits_T_42, _nodeOut_a_bits_T_43) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeOut_a_bits_WIRE_18 : UInt<3> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE_18, _nodeOut_a_bits_T_44 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeOut_a_bits_WIRE.opcode, _nodeOut_a_bits_WIRE_18 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect nodeOut.a.bits.corrupt, _nodeOut_a_bits_WIRE.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.data, _nodeOut_a_bits_WIRE.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.mask, _nodeOut_a_bits_WIRE.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.user.amba_prot.fetch, _nodeOut_a_bits_WIRE.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.user.amba_prot.secure, _nodeOut_a_bits_WIRE.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.user.amba_prot.privileged, _nodeOut_a_bits_WIRE.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.user.amba_prot.writealloc, _nodeOut_a_bits_WIRE.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.user.amba_prot.readalloc, _nodeOut_a_bits_WIRE.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.user.amba_prot.modifiable, _nodeOut_a_bits_WIRE.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.user.amba_prot.bufferable, _nodeOut_a_bits_WIRE.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.address, _nodeOut_a_bits_WIRE.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.source, _nodeOut_a_bits_WIRE.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.size, _nodeOut_a_bits_WIRE.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.param, _nodeOut_a_bits_WIRE.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeOut.a.bits.opcode, _nodeOut_a_bits_WIRE.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] node _T_19 = and(source_i.ready, source_i.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_20 = eq(a_isSupported, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 180:32] node _T_21 = and(_T_19, _T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 180:29] when _T_21 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 180:48] when a_cam_sel_free_0 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 182:23] connect cam_a[0].fifoId, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 183:24] connect cam_a[0].bits.corrupt, nodeIn.a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 184:24] connect cam_a[0].bits.data, nodeIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 184:24] connect cam_a[0].bits.mask, nodeIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 184:24] connect cam_a[0].bits.user, nodeIn.a.bits.user @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 184:24] connect cam_a[0].bits.address, nodeIn.a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 184:24] connect cam_a[0].bits.source, nodeIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 184:24] connect cam_a[0].bits.size, nodeIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 184:24] connect cam_a[0].bits.param, nodeIn.a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 184:24] connect cam_a[0].bits.opcode, nodeIn.a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 184:24] node _cam_a_0_lut_T = bits(nodeIn.a.bits.param, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 185:52] node _cam_a_0_lut_T_1 = eq(UInt<3>(0h1), _cam_a_0_lut_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 185:69] node _cam_a_0_lut_T_2 = mux(_cam_a_0_lut_T_1, UInt<4>(0he), UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 185:69] node _cam_a_0_lut_T_3 = eq(UInt<3>(0h0), _cam_a_0_lut_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 185:69] node _cam_a_0_lut_T_4 = mux(_cam_a_0_lut_T_3, UInt<3>(0h6), _cam_a_0_lut_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 185:69] node _cam_a_0_lut_T_5 = eq(UInt<3>(0h3), _cam_a_0_lut_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 185:69] node _cam_a_0_lut_T_6 = mux(_cam_a_0_lut_T_5, UInt<4>(0hc), _cam_a_0_lut_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 185:69] connect cam_a[0].lut, _cam_a_0_lut_T_6 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 185:24] when a_cam_sel_free_0 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 193:23] connect cam_s[0].state, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 194:23] node _T_22 = and(source_c.ready, source_c.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_22 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 200:30] when a_cam_sel_put_0 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 202:23] connect cam_s[0].state, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 203:23] node _d_first_T = and(nodeOut.d.ready, nodeOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node d_first_beats1_opdata = bits(nodeOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node d_first_counter1 = tail(_d_first_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node d_first = eq(d_first_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node d_first_last = or(_d_first_last_T, _d_first_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node d_first_done = and(d_first_last, _d_first_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _d_first_count_T = not(d_first_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node d_first_count = and(d_first_beats1, _d_first_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _d_first_T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect d_first_counter, _d_first_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node d_cam_sel_raw_0 = eq(cam_a[0].bits.source, nodeIn.d.bits.source) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 210:53] node d_cam_sel_match_0 = and(d_cam_sel_raw_0, cam_dmatch_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 211:83] node d_cam_sel_0 = mux(UInt<1>(0h0), a_cam_sel_free_0, d_cam_sel_match_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 217:85] node d_cam_sel_any = or(UInt<1>(0h0), d_cam_sel_match_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 218:46] node d_ackd = eq(nodeOut.d.bits.opcode, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 219:40] node d_ack = eq(nodeOut.d.bits.opcode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 220:40] node _T_23 = and(nodeOut.d.ready, nodeOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_24 = and(_T_23, d_first) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 222:26] when _T_24 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 222:38] node _T_25 = and(d_cam_sel_0, d_ackd) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 224:22] when _T_25 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 224:33] connect cam_d[0].data, nodeOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 225:22] connect cam_d[0].denied, nodeOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 226:24] connect cam_d[0].corrupt, nodeOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 227:25] when d_cam_sel_0 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 231:23] node _cam_s_0_state_T = mux(d_ackd, UInt<2>(0h2), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 233:29] connect cam_s[0].state, _cam_s_0_state_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 233:23] node _d_drop_T = and(d_first, d_ackd) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 238:30] node d_drop = and(_d_drop_T, d_cam_sel_any) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 238:40] node _d_replace_T = and(d_first, d_ack) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 239:33] node d_replace = and(_d_replace_T, d_cam_sel_match_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 239:42] node _nodeIn_d_valid_T = eq(d_drop, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 241:38] node _nodeIn_d_valid_T_1 = and(nodeOut.d.valid, _nodeIn_d_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 241:35] connect nodeIn.d.valid, _nodeIn_d_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 241:20] node _nodeOut_d_ready_T = or(nodeIn.d.ready, d_drop) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 242:35] connect nodeOut.d.ready, _nodeOut_d_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 242:21] connect nodeIn.d.bits.corrupt, nodeOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 244:19] connect nodeIn.d.bits.data, nodeOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 244:19] connect nodeIn.d.bits.denied, nodeOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 244:19] connect nodeIn.d.bits.sink, nodeOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 244:19] connect nodeIn.d.bits.source, nodeOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 244:19] connect nodeIn.d.bits.size, nodeOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 244:19] connect nodeIn.d.bits.param, nodeOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 244:19] connect nodeIn.d.bits.opcode, nodeOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 244:19] when d_replace : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 245:26] connect nodeIn.d.bits.opcode, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 246:28] connect nodeIn.d.bits.data, cam_d[0].data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 247:26] node _nodeIn_d_bits_corrupt_T = or(cam_d[0].corrupt, nodeOut.d.bits.denied) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 248:46] connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_corrupt_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 248:29] node _nodeIn_d_bits_denied_T = or(cam_d[0].denied, nodeOut.d.bits.denied) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 249:46] connect nodeIn.d.bits.denied, _nodeIn_d_bits_denied_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 249:29] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 274:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 275:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 276:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 277:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 278:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 279:21] module Queue1_TLBundleA_a14d64s2k1z4u : @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input clock : Clock @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input reset : Reset @[src/main/scala/chisel3/util/Decoupled.scala 243:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, count : UInt<1>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} [1] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] wire enq_ptr_value : UInt @[src/main/scala/chisel3/util/Counter.scala 61:73] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:73] wire deq_ptr_value : UInt @[src/main/scala/chisel3/util/Counter.scala 61:73] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:73] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] wire _WIRE : UInt @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect _WIRE, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 270:8] infer mport MPORT = ram[_WIRE], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 270:24] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] skip node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] wire _io_deq_bits_WIRE : UInt @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect _io_deq_bits_WIRE, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 293:23] infer mport io_deq_bits_MPORT = ram[_io_deq_bits_WIRE], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module TLError : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 21:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 21:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 21:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] inst a_q of Queue1_TLBundleA_a14d64s2k1z4u @[src/main/scala/chisel3/util/Decoupled.scala 362:21] connect a_q.clock, clock connect a_q.reset, reset connect a_q.io.enq.valid, nodeIn.a.valid @[src/main/scala/chisel3/util/Decoupled.scala 364:22] connect a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.data, nodeIn.a.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.mask, nodeIn.a.bits.mask @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.address, nodeIn.a.bits.address @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.source, nodeIn.a.bits.source @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.size, nodeIn.a.bits.size @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.param, nodeIn.a.bits.param @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn.a.ready, a_q.io.enq.ready @[src/main/scala/chisel3/util/Decoupled.scala 366:17] wire da : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 28:18] regreset idle : UInt<1>, clock, reset, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 29:23] node _a_last_T = and(a_q.io.deq.ready, a_q.io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _a_last_beats1_decode_T = dshl(UInt<12>(0hfff), a_q.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _a_last_beats1_decode_T_1 = bits(_a_last_beats1_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _a_last_beats1_decode_T_2 = not(_a_last_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node a_last_beats1_decode = shr(_a_last_beats1_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _a_last_beats1_opdata_T = bits(a_q.io.deq.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node a_last_beats1_opdata = eq(_a_last_beats1_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node a_last_beats1 = mux(a_last_beats1_opdata, a_last_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset a_last_counter : UInt<9>, clock, reset, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _a_last_counter1_T = sub(a_last_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node a_last_counter1 = tail(_a_last_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node a_last_first = eq(a_last_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _a_last_last_T = eq(a_last_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _a_last_last_T_1 = eq(a_last_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node a_last = or(_a_last_last_T, _a_last_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node a_last_done = and(a_last, _a_last_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _a_last_count_T = not(a_last_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node a_last_count = and(a_last_beats1, _a_last_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _a_last_T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _a_last_counter_T = mux(a_last_first, a_last_beats1, a_last_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect a_last_counter, _a_last_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node _T = and(da.ready, da.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _r_beats1_decode_T = dshl(UInt<12>(0hfff), da.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node r_beats1_decode = shr(_r_beats1_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node r_beats1_opdata = bits(da.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node r_counter1 = tail(_r_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node da_first = eq(r_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _r_last_T = eq(r_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node da_last = or(_r_last_T, _r_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node r_3 = and(da_last, _T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _r_count_T = not(r_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node r_4 = and(r_beats1, _r_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _r_counter_T = mux(da_first, r_beats1, r_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect r_counter, _r_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node _T_1 = or(idle, da_first) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 34:18] node _T_2 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 34:12] node _T_3 = eq(_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 34:12] when _T_3 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 34:12] node _T_4 = eq(_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 34:12] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 34:12] printf(clock, UInt<1>(0h1), "Assertion failed\n at Error.scala:34 assert (idle || da_first) // we only send Grant, never GrantData => simplified flow control below\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 34:12] assert(clock, _T_1, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 34:12] node _q_io_deq_ready_T = and(da.ready, da_last) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 35:26] node _q_io_deq_ready_T_1 = and(_q_io_deq_ready_T, idle) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 35:37] node _q_io_deq_ready_T_2 = eq(a_last, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 35:49] node _q_io_deq_ready_T_3 = or(_q_io_deq_ready_T_1, _q_io_deq_ready_T_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 35:46] connect a_q.io.deq.ready, _q_io_deq_ready_T_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 35:13] node _da_valid_T = and(a_q.io.deq.valid, a_last) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 36:25] node _da_valid_T_1 = and(_da_valid_T, idle) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 36:35] connect da.valid, _da_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 36:14] wire _da_bits_opcode_WIRE : UInt<3>[8] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 47:27] connect _da_bits_opcode_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 47:27] connect _da_bits_opcode_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 47:27] connect _da_bits_opcode_WIRE[2], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 47:27] connect _da_bits_opcode_WIRE[3], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 47:27] connect _da_bits_opcode_WIRE[4], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 47:27] connect _da_bits_opcode_WIRE[5], UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 47:27] connect _da_bits_opcode_WIRE[6], UInt<3>(0h4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 47:27] connect _da_bits_opcode_WIRE[7], UInt<3>(0h4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 47:27] connect da.bits.opcode, _da_bits_opcode_WIRE[a_q.io.deq.bits.opcode] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 38:21] connect da.bits.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 39:21] connect da.bits.size, a_q.io.deq.bits.size @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 40:21] connect da.bits.source, a_q.io.deq.bits.source @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 41:21] connect da.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 42:21] connect da.bits.denied, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 43:21] connect da.bits.data, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 44:21] node da_bits_corrupt_opdata = bits(da.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] connect da.bits.corrupt, da_bits_corrupt_opdata @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 45:21] connect nodeIn.d, da @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 74:12] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<14>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 78:16] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_2.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 81:16] module Queue2_TLBundleA_a14d64s2k1z4u : @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input clock : Clock @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input reset : Reset @[src/main/scala/chisel3/util/Decoupled.scala 243:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, count : UInt<2>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} [2] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] regreset enq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset deq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] infer mport MPORT = ram[enq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 270:24] node wrap = eq(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T = add(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_1 = tail(_value_T, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect enq_ptr_value, _value_T_1 @[src/main/scala/chisel3/util/Counter.scala 77:15] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] node wrap_1 = eq(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_3 = tail(_value_T_2, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect deq_ptr_value, _value_T_3 @[src/main/scala/chisel3/util/Counter.scala 77:15] node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] infer mport io_deq_bits_MPORT = ram[deq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module Queue2_TLBundleD_a14d64s2k1z4u : @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input clock : Clock @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input reset : Reset @[src/main/scala/chisel3/util/Decoupled.scala 243:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, count : UInt<2>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} [2] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] regreset enq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset deq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] infer mport MPORT = ram[enq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 270:24] node wrap = eq(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T = add(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_1 = tail(_value_T, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect enq_ptr_value, _value_T_1 @[src/main/scala/chisel3/util/Counter.scala 77:15] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] node wrap_1 = eq(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_3 = tail(_value_T_2, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect deq_ptr_value, _value_T_3 @[src/main/scala/chisel3/util/Counter.scala 77:15] node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] infer mport io_deq_bits_MPORT = ram[deq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module TLBuffer_a14d64s2k1z4u : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] inst nodeOut_a_q of Queue2_TLBundleA_a14d64s2k1z4u @[src/main/scala/chisel3/util/Decoupled.scala 362:21] connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid @[src/main/scala/chisel3/util/Decoupled.scala 364:22] connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready @[src/main/scala/chisel3/util/Decoupled.scala 366:17] connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] inst nodeIn_d_q of Queue2_TLBundleD_a14d64s2k1z4u @[src/main/scala/chisel3/util/Decoupled.scala 362:21] connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid @[src/main/scala/chisel3/util/Decoupled.scala 364:22] connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready @[src/main/scala/chisel3/util/Decoupled.scala 366:17] connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<14>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 52:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<14>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 53:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 54:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<14>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 55:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<14>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 56:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 57:21] module ErrorDeviceWrapper : @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input clock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input reset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] output auto : { flip buffer_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] inst error of TLError @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala 40:29] connect error.clock, clock connect error.reset, reset inst buffer of TLBuffer_a14d64s2k1z4u @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 75:28] connect buffer.clock, clock connect buffer.reset, reset connect error.auto.in, buffer.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect buffer.auto.in, auto.buffer_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] module TLBuffer_a32d64s2k1z4u_1 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut.a, nodeIn.a @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] connect nodeIn.d, nodeOut.d @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 52:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 53:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 54:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 55:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 56:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 57:21] module TLWidthWidget8_3 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonOut.a.bits, anonIn.a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonOut.a.valid, anonIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 155:19] connect anonIn.a.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 156:18] connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.valid, anonOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 155:19] connect anonOut.d.ready, anonIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 156:18] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 215:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 216:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 217:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 218:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 219:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 220:21] module TLInterconnectCoupler_cbus_to_bus_named_pbus : @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input clock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input reset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] output auto : { flip widget_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] inst widget of TLWidthWidget8_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 230:28] connect widget.clock, clock connect widget.reset, reset wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate bus_xingOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate bus_xingIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect bus_xingOut, bus_xingIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect widget.auto.anon_out.d, bus_xingIn.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect bus_xingIn.a.bits, widget.auto.anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect bus_xingIn.a.valid, widget.auto.anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect widget.auto.anon_out.a.ready, bus_xingIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect auto.bus_xing_out, bus_xingOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect widget.auto.anon_in, auto.widget_anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] module Repeater_TLBundleA_a26d64s2k1z3u : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 13:14] regreset full : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 20:21] reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 21:18] node _io_deq_valid_T = or(io.enq.valid, full) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:32] connect io.deq.valid, _io_deq_valid_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:35] node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:32] connect io.enq.ready, _io_enq_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:16] node _io_deq_bits_T = mux(full, saved, io.enq.bits) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:21] connect io.deq.bits, _io_deq_bits_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:15] connect io.full, full @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 27:11] node _T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_1 = and(_T, io.repeat) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:21] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:36] connect full, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:43] connect saved, io.enq.bits @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] node _T_2 = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_3 = eq(io.repeat, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:24] node _T_4 = and(_T_2, _T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:21] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:36] connect full, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:43] module TLFragmenter_CLINT : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 201:29] reg dOrig : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 202:24] regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 203:30] node dFragnum = bits(anonOut.d.bits.source, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 204:41] node dFirst = eq(acknum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 205:29] node dLast = eq(dFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 206:30] node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node dsizeOH = bits(_dsizeOH_T, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node dsizeOH1 = not(_dsizeOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node dHasData = bits(anonOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node acknum_fragment = shl(dFragnum, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 212:40] node acknum_size = shr(dsizeOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 213:36] node _T = eq(anonOut.d.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:17] node _T_1 = and(acknum_fragment, acknum_size) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:50] node _T_2 = eq(_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:65] node _T_3 = or(_T, _T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:30] node _T_4 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _T_5 = eq(_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _T_6 = eq(_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] when _T_6 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] assert(clock, _T_3, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 215:50] node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 215:45] node _ack_decrement_T = shr(dsizeOH, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 216:56] node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 216:32] node _dFirst_size_T = shl(dFragnum, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 218:47] node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 218:69] node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:35] node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:40] node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:53] node _dFirst_size_T_5 = not(_dFirst_size_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:49] node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:47] node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _dFirst_size_T_7 = orr(dFirst_size_hi) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _dFirst_size_T_9 = orr(dFirst_size_hi_1) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) @[src/main/scala/chisel3/util/CircuitMath.scala 28:8] node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node _T_7 = and(anonOut.d.ready, anonOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_7 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 220:27] node _acknum_T = sub(acknum, ack_decrement) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:55] node _acknum_T_1 = tail(_acknum_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:55] node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:24] connect acknum, _acknum_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:18] when dFirst : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 222:25] connect dOrig, dFirst_size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 223:19] node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 224:41] connect dToggle, _dToggle_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 224:21] node _drop_T = eq(dHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:20] node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:37] node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:33] node drop = and(_drop_T, _drop_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:30] node _anonOut_d_ready_T = or(anonIn.d.ready, drop) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 235:35] connect anonOut.d.ready, _anonOut_d_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 235:21] node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:39] node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:36] connect anonIn.d.valid, _anonIn_d_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:21] connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 238:47] connect anonIn.d.bits.source, _anonIn_d_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 238:26] node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 239:32] connect anonIn.d.bits.size, _anonIn_d_bits_size_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 239:26] inst repeater of Repeater_TLBundleA_a26d64s2k1z3u @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 274:30] connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 275:25] node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_1 = cvt(_find_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_3 = asSInt(_find_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] wire find : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[0], _find_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _aFrag_T = gt(repeater.io.deq.bits.size, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 297:31] node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 297:24] node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node aOrigOH1 = not(_aOrigOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node aFragOH1 = not(_aFragOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 301:24] regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 303:29] node aFirst = eq(gennum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 304:29] node _old_gennum1_T = shr(aOrigOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:48] node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:79] node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:79] node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:30] node _new_gennum_T = not(old_gennum1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:28] node _new_gennum_T_1 = shr(aMask, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:50] node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:41] node new_gennum = not(_new_gennum_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:26] node _aFragnum_T = shr(old_gennum1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:40] node _aFragnum_T_1 = not(_aFragnum_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:26] node _aFragnum_T_2 = shr(aFragOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:84] node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:72] node aFragnum = not(_aFragnum_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:24] node aLast = eq(aFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 308:30] reg aToggle_r : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] when aFirst : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] connect aToggle_r, dToggle @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] node _aToggle_T = mux(aFirst, dToggle, aToggle_r) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:27] node aToggle = eq(_aToggle_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:23] node _T_8 = and(anonOut.a.ready, anonOut.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 312:27] connect gennum, new_gennum @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 312:36] node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:31] node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:53] node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:41] connect repeater.io.repeat, _repeater_io_repeat_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:28] connect anonOut.a.bits, repeater.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] connect anonOut.a.valid, repeater.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] connect repeater.io.deq.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] node _anonOut_a_bits_address_T = shl(old_gennum1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:65] node _anonOut_a_bits_address_T_1 = not(aOrigOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:90] node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:88] node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:100] node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:111] node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:51] node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:49] connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:28] node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] connect anonOut.a.bits.source, _anonOut_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:27] connect anonOut.a.bits.size, aFrag @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 318:25] node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:17] node _T_10 = eq(aHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:38] node _T_11 = or(_T_9, _T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:35] node _T_12 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] node _T_13 = eq(_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] when _T_13 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] node _T_14 = eq(_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] when _T_14 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] connect anonOut.a.bits.data, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 322:25] node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:17] node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:53] node _T_17 = or(_T_15, _T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:35] node _T_18 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _T_19 = eq(_T_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] when _T_19 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _T_20 = eq(_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] when _T_20 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 325:31] connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 325:25] wire anonOut_a_bits_user_out : { } @[hardware/upstream/rocket-chip/src/main/scala/util/BundleMap.scala 114:19] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<26>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 329:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<26>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 330:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 331:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<26>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 332:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<26>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 333:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 334:21] module TLInterconnectCoupler_cbus_to_clint : @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input clock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input reset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] inst fragmenter of TLFragmenter_CLINT @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 345:34] connect fragmenter.clock, clock connect fragmenter.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate tlOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tlIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect tlOut, tlIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect fragmenter.auto.anon_in, tlOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect tlIn, auto.tl_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] module Repeater_TLBundleA_a28d64s2k1z3u : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 13:14] regreset full : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 20:21] reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 21:18] node _io_deq_valid_T = or(io.enq.valid, full) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:32] connect io.deq.valid, _io_deq_valid_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:35] node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:32] connect io.enq.ready, _io_enq_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:16] node _io_deq_bits_T = mux(full, saved, io.enq.bits) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:21] connect io.deq.bits, _io_deq_bits_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:15] connect io.full, full @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 27:11] node _T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_1 = and(_T, io.repeat) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:21] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:36] connect full, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:43] connect saved, io.enq.bits @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] node _T_2 = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_3 = eq(io.repeat, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:24] node _T_4 = and(_T_2, _T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:21] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:36] connect full, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:43] module TLFragmenter_PLIC : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 201:29] reg dOrig : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 202:24] regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 203:30] node dFragnum = bits(anonOut.d.bits.source, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 204:41] node dFirst = eq(acknum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 205:29] node dLast = eq(dFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 206:30] node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node dsizeOH = bits(_dsizeOH_T, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node dsizeOH1 = not(_dsizeOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node dHasData = bits(anonOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node acknum_fragment = shl(dFragnum, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 212:40] node acknum_size = shr(dsizeOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 213:36] node _T = eq(anonOut.d.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:17] node _T_1 = and(acknum_fragment, acknum_size) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:50] node _T_2 = eq(_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:65] node _T_3 = or(_T, _T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:30] node _T_4 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _T_5 = eq(_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _T_6 = eq(_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] when _T_6 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] assert(clock, _T_3, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 215:50] node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 215:45] node _ack_decrement_T = shr(dsizeOH, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 216:56] node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 216:32] node _dFirst_size_T = shl(dFragnum, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 218:47] node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 218:69] node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:35] node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:40] node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:53] node _dFirst_size_T_5 = not(_dFirst_size_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:49] node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:47] node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _dFirst_size_T_7 = orr(dFirst_size_hi) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _dFirst_size_T_9 = orr(dFirst_size_hi_1) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) @[src/main/scala/chisel3/util/CircuitMath.scala 28:8] node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node _T_7 = and(anonOut.d.ready, anonOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_7 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 220:27] node _acknum_T = sub(acknum, ack_decrement) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:55] node _acknum_T_1 = tail(_acknum_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:55] node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:24] connect acknum, _acknum_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:18] when dFirst : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 222:25] connect dOrig, dFirst_size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 223:19] node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 224:41] connect dToggle, _dToggle_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 224:21] node _drop_T = eq(dHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:20] node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:37] node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:33] node drop = and(_drop_T, _drop_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:30] node _anonOut_d_ready_T = or(anonIn.d.ready, drop) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 235:35] connect anonOut.d.ready, _anonOut_d_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 235:21] node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:39] node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:36] connect anonIn.d.valid, _anonIn_d_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:21] connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 238:47] connect anonIn.d.bits.source, _anonIn_d_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 238:26] node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 239:32] connect anonIn.d.bits.size, _anonIn_d_bits_size_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 239:26] inst repeater of Repeater_TLBundleA_a28d64s2k1z3u @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 274:30] connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 275:25] node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_1 = cvt(_find_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_3 = asSInt(_find_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] wire find : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[0], _find_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _aFrag_T = gt(repeater.io.deq.bits.size, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 297:31] node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 297:24] node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node aOrigOH1 = not(_aOrigOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node aFragOH1 = not(_aFragOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 301:24] regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 303:29] node aFirst = eq(gennum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 304:29] node _old_gennum1_T = shr(aOrigOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:48] node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:79] node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:79] node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:30] node _new_gennum_T = not(old_gennum1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:28] node _new_gennum_T_1 = shr(aMask, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:50] node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:41] node new_gennum = not(_new_gennum_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:26] node _aFragnum_T = shr(old_gennum1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:40] node _aFragnum_T_1 = not(_aFragnum_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:26] node _aFragnum_T_2 = shr(aFragOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:84] node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:72] node aFragnum = not(_aFragnum_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:24] node aLast = eq(aFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 308:30] reg aToggle_r : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] when aFirst : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] connect aToggle_r, dToggle @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] node _aToggle_T = mux(aFirst, dToggle, aToggle_r) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:27] node aToggle = eq(_aToggle_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:23] node _T_8 = and(anonOut.a.ready, anonOut.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 312:27] connect gennum, new_gennum @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 312:36] node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:31] node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:53] node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:41] connect repeater.io.repeat, _repeater_io_repeat_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:28] connect anonOut.a.bits, repeater.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] connect anonOut.a.valid, repeater.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] connect repeater.io.deq.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] node _anonOut_a_bits_address_T = shl(old_gennum1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:65] node _anonOut_a_bits_address_T_1 = not(aOrigOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:90] node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:88] node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:100] node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:111] node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:51] node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:49] connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:28] node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] connect anonOut.a.bits.source, _anonOut_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:27] connect anonOut.a.bits.size, aFrag @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 318:25] node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:17] node _T_10 = eq(aHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:38] node _T_11 = or(_T_9, _T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:35] node _T_12 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] node _T_13 = eq(_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] when _T_13 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] node _T_14 = eq(_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] when _T_14 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] connect anonOut.a.bits.data, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 322:25] node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:17] node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:53] node _T_17 = or(_T_15, _T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:35] node _T_18 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _T_19 = eq(_T_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] when _T_19 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _T_20 = eq(_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] when _T_20 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 325:31] connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 325:25] wire anonOut_a_bits_user_out : { } @[hardware/upstream/rocket-chip/src/main/scala/util/BundleMap.scala 114:19] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<28>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 329:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<28>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 330:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 331:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<28>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 332:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<28>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 333:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 334:21] module TLInterconnectCoupler_cbus_to_plic : @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input clock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input reset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] inst fragmenter of TLFragmenter_PLIC @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 345:34] connect fragmenter.clock, clock connect fragmenter.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate tlOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tlIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect tlOut, tlIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect fragmenter.auto.anon_in, tlOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect tlIn, auto.tl_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] module Repeater_TLBundleA_a12d64s2k1z3u : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 13:14] regreset full : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 20:21] reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 21:18] node _io_deq_valid_T = or(io.enq.valid, full) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:32] connect io.deq.valid, _io_deq_valid_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:35] node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:32] connect io.enq.ready, _io_enq_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:16] node _io_deq_bits_T = mux(full, saved, io.enq.bits) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:21] connect io.deq.bits, _io_deq_bits_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:15] connect io.full, full @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 27:11] node _T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_1 = and(_T, io.repeat) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:21] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:36] connect full, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:43] connect saved, io.enq.bits @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] node _T_2 = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_3 = eq(io.repeat, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:24] node _T_4 = and(_T_2, _T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:21] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:36] connect full, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:43] module TLFragmenter_Debug : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 201:29] reg dOrig : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 202:24] regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 203:30] node dFragnum = bits(anonOut.d.bits.source, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 204:41] node dFirst = eq(acknum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 205:29] node dLast = eq(dFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 206:30] node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node dsizeOH = bits(_dsizeOH_T, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node dsizeOH1 = not(_dsizeOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node dHasData = bits(anonOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node acknum_fragment = shl(dFragnum, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 212:40] node acknum_size = shr(dsizeOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 213:36] node _T = eq(anonOut.d.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:17] node _T_1 = and(acknum_fragment, acknum_size) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:50] node _T_2 = eq(_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:65] node _T_3 = or(_T, _T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:30] node _T_4 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _T_5 = eq(_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _T_6 = eq(_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] when _T_6 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] assert(clock, _T_3, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 215:50] node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 215:45] node _ack_decrement_T = shr(dsizeOH, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 216:56] node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 216:32] node _dFirst_size_T = shl(dFragnum, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 218:47] node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 218:69] node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:35] node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:40] node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:53] node _dFirst_size_T_5 = not(_dFirst_size_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:49] node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:47] node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _dFirst_size_T_7 = orr(dFirst_size_hi) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _dFirst_size_T_9 = orr(dFirst_size_hi_1) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) @[src/main/scala/chisel3/util/CircuitMath.scala 28:8] node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node _T_7 = and(anonOut.d.ready, anonOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_7 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 220:27] node _acknum_T = sub(acknum, ack_decrement) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:55] node _acknum_T_1 = tail(_acknum_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:55] node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:24] connect acknum, _acknum_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:18] when dFirst : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 222:25] connect dOrig, dFirst_size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 223:19] node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 224:41] connect dToggle, _dToggle_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 224:21] node _drop_T = eq(dHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:20] node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:37] node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:33] node drop = and(_drop_T, _drop_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:30] node _anonOut_d_ready_T = or(anonIn.d.ready, drop) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 235:35] connect anonOut.d.ready, _anonOut_d_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 235:21] node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:39] node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:36] connect anonIn.d.valid, _anonIn_d_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:21] connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 238:47] connect anonIn.d.bits.source, _anonIn_d_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 238:26] node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 239:32] connect anonIn.d.bits.size, _anonIn_d_bits_size_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 239:26] inst repeater of Repeater_TLBundleA_a12d64s2k1z3u @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 274:30] connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 275:25] node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_1 = cvt(_find_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_3 = asSInt(_find_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] wire find : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[0], _find_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _aFrag_T = gt(repeater.io.deq.bits.size, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 297:31] node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 297:24] node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node aOrigOH1 = not(_aOrigOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node aFragOH1 = not(_aFragOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 301:24] regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 303:29] node aFirst = eq(gennum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 304:29] node _old_gennum1_T = shr(aOrigOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:48] node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:79] node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:79] node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:30] node _new_gennum_T = not(old_gennum1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:28] node _new_gennum_T_1 = shr(aMask, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:50] node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:41] node new_gennum = not(_new_gennum_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:26] node _aFragnum_T = shr(old_gennum1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:40] node _aFragnum_T_1 = not(_aFragnum_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:26] node _aFragnum_T_2 = shr(aFragOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:84] node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:72] node aFragnum = not(_aFragnum_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:24] node aLast = eq(aFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 308:30] reg aToggle_r : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] when aFirst : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] connect aToggle_r, dToggle @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] node _aToggle_T = mux(aFirst, dToggle, aToggle_r) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:27] node aToggle = eq(_aToggle_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:23] node _T_8 = and(anonOut.a.ready, anonOut.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 312:27] connect gennum, new_gennum @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 312:36] node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:31] node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:53] node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:41] connect repeater.io.repeat, _repeater_io_repeat_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:28] connect anonOut.a.bits, repeater.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] connect anonOut.a.valid, repeater.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] connect repeater.io.deq.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] node _anonOut_a_bits_address_T = shl(old_gennum1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:65] node _anonOut_a_bits_address_T_1 = not(aOrigOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:90] node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:88] node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:100] node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:111] node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:51] node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:49] connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:28] node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] connect anonOut.a.bits.source, _anonOut_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:27] connect anonOut.a.bits.size, aFrag @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 318:25] node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:17] node _T_10 = eq(aHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:38] node _T_11 = or(_T_9, _T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:35] node _T_12 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] node _T_13 = eq(_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] when _T_13 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] node _T_14 = eq(_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] when _T_14 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] connect anonOut.a.bits.data, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 322:25] node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:17] node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:53] node _T_17 = or(_T_15, _T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:35] node _T_18 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _T_19 = eq(_T_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] when _T_19 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _T_20 = eq(_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] when _T_20 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 325:31] connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 325:25] wire anonOut_a_bits_user_out : { } @[hardware/upstream/rocket-chip/src/main/scala/util/BundleMap.scala 114:19] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<12>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 329:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<12>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 330:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 331:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<12>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 332:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<12>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 333:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 334:21] module TLInterconnectCoupler_cbus_to_debug : @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input clock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input reset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] inst fragmenter of TLFragmenter_Debug @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 345:34] connect fragmenter.clock, clock connect fragmenter.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate tlOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tlIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect tlOut, tlIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect fragmenter.auto.anon_in, tlOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect tlIn, auto.tl_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] module TLWidthWidget8_4 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonOut.a.bits, anonIn.a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonOut.a.valid, anonIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 155:19] connect anonIn.a.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 156:18] connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.valid, anonOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 155:19] connect anonOut.d.ready, anonIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 156:18] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 215:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 216:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 217:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 218:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 219:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 220:21] module TLInterconnectCoupler_cbus_to_rockettile : @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input clock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input reset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] output auto : { tl_slave_clock_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] inst widget of TLWidthWidget8_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 230:28] connect widget.clock, clock connect widget.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate tlOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tlIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect tlOut, tlIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire tlSlaveClockXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate tlSlaveClockXingOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire tlSlaveClockXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tlSlaveClockXingIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect tlSlaveClockXingOut, tlSlaveClockXingIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire no_bufferOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate no_bufferOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate no_bufferOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire no_bufferIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate no_bufferIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate no_bufferIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect no_bufferOut, no_bufferIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect widget.auto.anon_in, tlOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect tlSlaveClockXingIn, no_bufferOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect widget.auto.anon_out.d, no_bufferIn.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect no_bufferIn.a.bits, widget.auto.anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect no_bufferIn.a.valid, widget.auto.anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect widget.auto.anon_out.a.ready, no_bufferIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tlIn, auto.tl_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.tl_slave_clock_xing_out, tlSlaveClockXingOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] module Repeater_TLBundleA_a17d64s2k1z3u : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 13:14] regreset full : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 20:21] reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 21:18] node _io_deq_valid_T = or(io.enq.valid, full) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:32] connect io.deq.valid, _io_deq_valid_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:35] node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:32] connect io.enq.ready, _io_enq_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:16] node _io_deq_bits_T = mux(full, saved, io.enq.bits) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:21] connect io.deq.bits, _io_deq_bits_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:15] connect io.full, full @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 27:11] node _T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_1 = and(_T, io.repeat) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:21] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:36] connect full, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:43] connect saved, io.enq.bits @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] node _T_2 = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_3 = eq(io.repeat, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:24] node _T_4 = and(_T_2, _T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:21] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:36] connect full, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:43] module TLFragmenter_bootrom : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 201:29] reg dOrig : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 202:24] regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 203:30] node dFragnum = bits(anonOut.d.bits.source, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 204:41] node dFirst = eq(acknum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 205:29] node dLast = eq(dFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 206:30] node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node dsizeOH = bits(_dsizeOH_T, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node dsizeOH1 = not(_dsizeOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node dHasData_opdata = bits(anonOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node acknum_fragment = shl(dFragnum, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 212:40] node acknum_size = shr(dsizeOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 213:36] node _T = eq(anonOut.d.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:17] node _T_1 = and(acknum_fragment, acknum_size) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:50] node _T_2 = eq(_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:65] node _T_3 = or(_T, _T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:30] node _T_4 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _T_5 = eq(_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _T_6 = eq(_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] when _T_6 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] assert(clock, _T_3, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _dFirst_acknum_T = mux(UInt<1>(0h1), acknum_size, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 215:50] node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 215:45] node _ack_decrement_T = shr(dsizeOH, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 216:56] node ack_decrement = mux(UInt<1>(0h1), UInt<1>(0h1), _ack_decrement_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 216:32] node _dFirst_size_T = shl(dFragnum, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 218:47] node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 218:69] node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:35] node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:40] node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:53] node _dFirst_size_T_5 = not(_dFirst_size_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:49] node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:47] node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _dFirst_size_T_7 = orr(dFirst_size_hi) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _dFirst_size_T_9 = orr(dFirst_size_hi_1) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) @[src/main/scala/chisel3/util/CircuitMath.scala 28:8] node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node _T_7 = and(anonOut.d.ready, anonOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_7 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 220:27] node _acknum_T = sub(acknum, ack_decrement) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:55] node _acknum_T_1 = tail(_acknum_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:55] node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:24] connect acknum, _acknum_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:18] when dFirst : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 222:25] connect dOrig, dFirst_size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 223:19] node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 224:41] connect dToggle, _dToggle_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 224:21] node _drop_T = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:20] node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:37] node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:33] node drop = and(_drop_T, _drop_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:30] node _anonOut_d_ready_T = or(anonIn.d.ready, drop) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 235:35] connect anonOut.d.ready, _anonOut_d_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 235:21] node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:39] node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:36] connect anonIn.d.valid, _anonIn_d_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:21] connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 238:47] connect anonIn.d.bits.source, _anonIn_d_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 238:26] node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 239:32] connect anonIn.d.bits.size, _anonIn_d_bits_size_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 239:26] inst repeater of Repeater_TLBundleA_a17d64s2k1z3u @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 274:30] connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 275:25] node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_1 = cvt(_find_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_3 = asSInt(_find_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] wire find : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[0], _find_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _aFrag_T = gt(repeater.io.deq.bits.size, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 297:31] node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 297:24] node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node aOrigOH1 = not(_aOrigOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node aFragOH1 = not(_aFragOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node aHasData_opdata = eq(_aHasData_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node aMask = mux(UInt<1>(0h0), UInt<1>(0h0), aFragOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 301:24] regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 303:29] node aFirst = eq(gennum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 304:29] node _old_gennum1_T = shr(aOrigOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:48] node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:79] node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:79] node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:30] node _new_gennum_T = not(old_gennum1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:28] node _new_gennum_T_1 = shr(aMask, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:50] node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:41] node new_gennum = not(_new_gennum_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:26] node _aFragnum_T = shr(old_gennum1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:40] node _aFragnum_T_1 = not(_aFragnum_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:26] node _aFragnum_T_2 = shr(aFragOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:84] node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:72] node aFragnum = not(_aFragnum_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:24] node aLast = eq(aFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 308:30] reg aToggle_r : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] when aFirst : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] connect aToggle_r, dToggle @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] node _aToggle_T = mux(aFirst, dToggle, aToggle_r) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:27] node aToggle = eq(_aToggle_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:23] node _T_8 = and(anonOut.a.ready, anonOut.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 312:27] connect gennum, new_gennum @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 312:36] node _repeater_io_repeat_T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:31] node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:53] node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:41] connect repeater.io.repeat, _repeater_io_repeat_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:28] connect anonOut.a.bits, repeater.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] connect anonOut.a.valid, repeater.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] connect repeater.io.deq.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] node _anonOut_a_bits_address_T = shl(old_gennum1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:65] node _anonOut_a_bits_address_T_1 = not(aOrigOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:90] node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:88] node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:100] node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:111] node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:51] node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:49] connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:28] node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] connect anonOut.a.bits.source, _anonOut_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:27] connect anonOut.a.bits.size, aFrag @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 318:25] node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:17] node _T_10 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:38] node _T_11 = or(_T_9, _T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:35] node _T_12 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] node _T_13 = eq(_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] when _T_13 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] node _T_14 = eq(_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] when _T_14 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] connect anonOut.a.bits.data, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 322:25] node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:17] node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:53] node _T_17 = or(_T_15, _T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:35] node _T_18 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _T_19 = eq(_T_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] when _T_19 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _T_20 = eq(_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] when _T_20 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 325:31] connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 325:25] wire anonOut_a_bits_user_out : { } @[hardware/upstream/rocket-chip/src/main/scala/util/BundleMap.scala 114:19] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<17>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 329:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<17>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 330:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 331:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<17>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 332:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<17>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 333:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 334:21] module TLInterconnectCoupler_cbus_to_bootrom : @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input clock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] input reset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 136:7] output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] inst fragmenter of TLFragmenter_bootrom @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 345:34] connect fragmenter.clock, clock connect fragmenter.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate tlOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tlIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect tlOut, tlIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect fragmenter.auto.anon_in, tlOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect tlIn, auto.tl_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] module PeripheryBus_cbus : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 14:9] output auto : { coupler_to_bootrom_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_rockettile_tl_slave_clock_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_debug_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_plic_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_clint_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_pbus_bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out_3 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_2 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip cbus_clock_groups_in : { member : { cbus_1 : { clock : Clock, reset : Reset}, cbus_0 : { clock : Clock, reset : Reset}}}, cbus_clock_groups_out : { member : { pbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 21:19] output reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 22:19] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] inst cbus_clock_groups of ClockGroupAggregator_cbus @[hardware/upstream/rocket-chip/src/main/scala/tilelink/BusWrapper.scala 52:48] inst clockGroup of ClockGroup_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/BusWrapper.scala 53:38] inst fixedClockNode of FixedClockBroadcast_5_1 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 115:114] inst broadcast of BundleBridgeNexus_NoOutput_3 @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/package.scala 25:31] inst fixer of TLFIFOFixer_2 @[hardware/upstream/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala 54:33] connect fixer.clock, childClock connect fixer.reset, childReset inst in_xbar of TLXbar_cbus_in_i1_o1_a32d64s2k1z4u @[hardware/upstream/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala 56:29] connect in_xbar.clock, childClock connect in_xbar.reset, childReset inst out_xbar of TLXbar_cbus_out_i1_o7_a32d64s2k1z4u @[hardware/upstream/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala 57:30] connect out_xbar.clock, childClock connect out_xbar.reset, childReset inst buffer of TLBuffer_a32d64s2k1z4u @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 75:28] connect buffer.clock, childClock connect buffer.reset, childReset inst atomics of TLAtomicAutomata_cbus @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AtomicAutomata.scala 289:29] connect atomics.clock, childClock connect atomics.reset, childReset inst wrapped_error_device of ErrorDeviceWrapper @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyScope.scala 99:27] connect wrapped_error_device.clock, childClock connect wrapped_error_device.reset, childReset inst buffer_1 of TLBuffer_a32d64s2k1z4u_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 75:28] connect buffer_1.clock, childClock connect buffer_1.reset, childReset inst coupler_to_bus_named_pbus of TLInterconnectCoupler_cbus_to_bus_named_pbus @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyScope.scala 99:27] connect coupler_to_bus_named_pbus.clock, childClock connect coupler_to_bus_named_pbus.reset, childReset inst coupler_to_clint of TLInterconnectCoupler_cbus_to_clint @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyScope.scala 99:27] connect coupler_to_clint.clock, childClock connect coupler_to_clint.reset, childReset inst coupler_to_plic of TLInterconnectCoupler_cbus_to_plic @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyScope.scala 99:27] connect coupler_to_plic.clock, childClock connect coupler_to_plic.reset, childReset inst coupler_to_debug of TLInterconnectCoupler_cbus_to_debug @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyScope.scala 99:27] connect coupler_to_debug.clock, childClock connect coupler_to_debug.reset, childReset inst coupler_to_rockettile of TLInterconnectCoupler_cbus_to_rockettile @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyScope.scala 99:27] connect coupler_to_rockettile.clock, childClock connect coupler_to_rockettile.reset, childReset inst coupler_to_bootrom of TLInterconnectCoupler_cbus_to_bootrom @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyScope.scala 99:27] connect coupler_to_bootrom.clock, childClock connect coupler_to_bootrom.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate clockSinkNodeIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate clockSinkNodeIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate bus_xingOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bus_xingOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate bus_xingIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate bus_xingIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect bus_xingOut, bus_xingIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect clockGroup.auto.in, cbus_clock_groups.auto.out_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fixedClockNode.auto.anon_in, clockGroup.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect out_xbar.auto.anon_in, fixer.auto.anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect atomics.auto.in, in_xbar.auto.anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect wrapped_error_device.auto.buffer_in, out_xbar.auto.anon_out_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect coupler_to_bus_named_pbus.auto.widget_anon_in, out_xbar.auto.anon_out_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect coupler_to_clint.auto.tl_in, out_xbar.auto.anon_out_2 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect coupler_to_plic.auto.tl_in, out_xbar.auto.anon_out_3 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect coupler_to_debug.auto.tl_in, out_xbar.auto.anon_out_4 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect coupler_to_rockettile.auto.tl_in, out_xbar.auto.anon_out_5 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect coupler_to_bootrom.auto.tl_in, out_xbar.auto.anon_out_6 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fixer.auto.anon_in, buffer.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect buffer.auto.in, atomics.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect in_xbar.auto.anon_in, buffer_1.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect buffer_1.auto.in, bus_xingOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect bus_xingIn, auto.bus_xing_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.cbus_clock_groups_out, cbus_clock_groups.auto.out_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect cbus_clock_groups.auto.in, auto.cbus_clock_groups_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fixedClockNode_anon_out_2, fixedClockNode.auto.anon_out_3 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.fixedClockNode_anon_out_3, fixedClockNode.auto.anon_out_4 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_bus_named_pbus.auto.bus_xing_out.d, auto.coupler_to_bus_named_pbus_bus_xing_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_bus_named_pbus_bus_xing_out.a.bits, coupler_to_bus_named_pbus.auto.bus_xing_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_bus_named_pbus_bus_xing_out.a.valid, coupler_to_bus_named_pbus.auto.bus_xing_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_bus_named_pbus.auto.bus_xing_out.a.ready, auto.coupler_to_bus_named_pbus_bus_xing_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_clint.auto.fragmenter_anon_out.d, auto.coupler_to_clint_fragmenter_anon_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_clint_fragmenter_anon_out.a.bits, coupler_to_clint.auto.fragmenter_anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_clint_fragmenter_anon_out.a.valid, coupler_to_clint.auto.fragmenter_anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_clint.auto.fragmenter_anon_out.a.ready, auto.coupler_to_clint_fragmenter_anon_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_plic.auto.fragmenter_anon_out.d, auto.coupler_to_plic_fragmenter_anon_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_plic_fragmenter_anon_out.a.bits, coupler_to_plic.auto.fragmenter_anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_plic_fragmenter_anon_out.a.valid, coupler_to_plic.auto.fragmenter_anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_plic.auto.fragmenter_anon_out.a.ready, auto.coupler_to_plic_fragmenter_anon_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_debug.auto.fragmenter_anon_out.d, auto.coupler_to_debug_fragmenter_anon_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_debug_fragmenter_anon_out.a.bits, coupler_to_debug.auto.fragmenter_anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_debug_fragmenter_anon_out.a.valid, coupler_to_debug.auto.fragmenter_anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_debug.auto.fragmenter_anon_out.a.ready, auto.coupler_to_debug_fragmenter_anon_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_rockettile.auto.tl_slave_clock_xing_out.d, auto.coupler_to_rockettile_tl_slave_clock_xing_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_rockettile_tl_slave_clock_xing_out.a.bits, coupler_to_rockettile.auto.tl_slave_clock_xing_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_rockettile_tl_slave_clock_xing_out.a.valid, coupler_to_rockettile.auto.tl_slave_clock_xing_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_rockettile.auto.tl_slave_clock_xing_out.a.ready, auto.coupler_to_rockettile_tl_slave_clock_xing_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_bootrom.auto.fragmenter_anon_out.d, auto.coupler_to_bootrom_fragmenter_anon_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_bootrom_fragmenter_anon_out.a.bits, coupler_to_bootrom.auto.fragmenter_anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.coupler_to_bootrom_fragmenter_anon_out.a.valid, coupler_to_bootrom.auto.fragmenter_anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect coupler_to_bootrom.auto.fragmenter_anon_out.a.ready, auto.coupler_to_bootrom_fragmenter_anon_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect childClock, clockSinkNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 15:16] connect childReset, clockSinkNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 16:16] connect clock, clockSinkNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 23:11] connect reset, clockSinkNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 24:11] module TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn_1.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonIn_1, auto.anon_in_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 159:18] invalidate in[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.data, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.mask, anonIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.address, anonIn.a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.source, anonIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.size, anonIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.param, anonIn.a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.opcode, anonIn.a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.valid, anonIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect anonIn.a.ready, in[0].a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:55] connect in[0].a.bits.source, _in_0_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:29] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_1.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_3.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 180:23] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 181:26] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_9.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_11.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.bits, _WIRE_12.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, _WIRE_12.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.ready, _WIRE_12.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 191:23] wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.bits, _WIRE_14.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.valid, _WIRE_14.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.ready, _WIRE_14.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 192:26] connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.data, in[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.denied, in[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.sink, in[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.source, in[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.size, in[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.param, in[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.opcode, in[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.valid, in[0].d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect in[0].d.ready, anonIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 197:32] wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.bits, _WIRE_16.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.valid, _WIRE_16.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.ready, _WIRE_16.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_17.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_17.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_17.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.bits, _WIRE_18.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.valid, _WIRE_18.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.ready, _WIRE_18.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_19.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_19.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_19.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.bits, _WIRE_20.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.valid, _WIRE_20.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.ready, _WIRE_20.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 210:23] wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.bits, _WIRE_22.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.valid, _WIRE_22.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, _WIRE_22.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 211:26] invalidate in[1].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[1].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[1].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[1].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[1].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[1].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] invalidate in[1].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 164:27] connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.data, anonIn_1.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.mask, anonIn_1.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.user.amba_prot.fetch, anonIn_1.a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.user.amba_prot.secure, anonIn_1.a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.user.amba_prot.privileged, anonIn_1.a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.user.amba_prot.writealloc, anonIn_1.a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.user.amba_prot.readalloc, anonIn_1.a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.user.amba_prot.modifiable, anonIn_1.a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.user.amba_prot.bufferable, anonIn_1.a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.address, anonIn_1.a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.source, anonIn_1.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.size, anonIn_1.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.param, anonIn_1.a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[1].a.valid, anonIn_1.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect anonIn_1.a.ready, in[1].a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:55] connect in[1].a.bits.source, _in_1_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:29] wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.bits, _WIRE_24.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.valid, _WIRE_24.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.ready, _WIRE_24.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_25.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_25.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_25.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_25.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_25.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_25.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_25.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_25.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_25.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_25.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.bits, _WIRE_26.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.valid, _WIRE_26.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.ready, _WIRE_26.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_27.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_27.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_27.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_27.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_27.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_27.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_27.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_27.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_27.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_27.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.bits, _WIRE_28.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.valid, _WIRE_28.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.ready, _WIRE_28.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 180:23] wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.bits, _WIRE_30.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.valid, _WIRE_30.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.ready, _WIRE_30.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 181:26] wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.bits, _WIRE_32.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.valid, _WIRE_32.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.ready, _WIRE_32.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_33.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_33.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.bits, _WIRE_34.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.valid, _WIRE_34.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.ready, _WIRE_34.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_35.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_35.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.bits, _WIRE_36.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.valid, _WIRE_36.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.ready, _WIRE_36.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 191:23] wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.bits, _WIRE_38.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.valid, _WIRE_38.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.ready, _WIRE_38.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 192:26] connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn_1.d.bits.data, in[1].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn_1.d.bits.denied, in[1].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn_1.d.bits.sink, in[1].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn_1.d.bits.source, in[1].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn_1.d.bits.size, in[1].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn_1.d.bits.param, in[1].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn_1.d.valid, in[1].d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect in[1].d.ready, anonIn_1.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn_1.d.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 197:32] wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.bits, _WIRE_40.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.valid, _WIRE_40.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.ready, _WIRE_40.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_41.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_41.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_41.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.bits, _WIRE_42.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.valid, _WIRE_42.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.ready, _WIRE_42.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_43.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_43.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_43.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.bits, _WIRE_44.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.valid, _WIRE_44.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.ready, _WIRE_44.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 210:23] wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.bits, _WIRE_46.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.valid, _WIRE_46.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.ready, _WIRE_46.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 211:26] wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 216:19] invalidate out[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] invalidate out[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 221:28] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.data, out[0].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.mask, out[0].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.fetch, out[0].a.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.secure, out[0].a.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.privileged, out[0].a.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.writealloc, out[0].a.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.readalloc, out[0].a.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.modifiable, out[0].a.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.user.amba_prot.bufferable, out[0].a.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.address, out[0].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.source, out[0].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.size, out[0].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.param, out[0].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.opcode, out[0].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.valid, out[0].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[0].a.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_49.bits, _WIRE_48.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_49.valid, _WIRE_48.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_49.ready, _WIRE_48.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_49.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_51.bits, _WIRE_50.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_51.valid, _WIRE_50.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_51.ready, _WIRE_50.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_51.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.bits, _WIRE_52.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.valid, _WIRE_52.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.ready, _WIRE_52.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.bits, _WIRE_54.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.valid, _WIRE_54.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.ready, _WIRE_54.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_57.bits, _WIRE_56.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_57.valid, _WIRE_56.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_57.ready, _WIRE_56.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_57.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_59.bits, _WIRE_58.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_59.valid, _WIRE_58.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_59.ready, _WIRE_58.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_59.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.bits, _WIRE_60.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.valid, _WIRE_60.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.ready, _WIRE_60.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.bits, _WIRE_62.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.valid, _WIRE_62.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.ready, _WIRE_62.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.valid, anonOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect anonOut.d.ready, out[0].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[0].d.bits.sink, _out_0_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_64.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_64.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_64.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_65.bits, _WIRE_64.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_65.valid, _WIRE_64.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_65.ready, _WIRE_64.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_65.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_65.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_65.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_66.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_66.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_66.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_67.bits, _WIRE_66.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_67.valid, _WIRE_66.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_67.ready, _WIRE_66.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_67.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_67.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_67.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_68.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_68.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_68.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.bits, _WIRE_68.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.valid, _WIRE_68.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.ready, _WIRE_68.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_70.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_70.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_70.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.bits, _WIRE_70.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.valid, _WIRE_70.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.ready, _WIRE_70.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.bits, _addressC_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.valid, _addressC_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.ready, _addressC_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] wire _addressC_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _addressC_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_3.bits, _addressC_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_3.valid, _addressC_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_3.ready, _addressC_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_1 = cvt(_requestAIO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_3 = asSInt(_requestAIO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_6 = cvt(_requestAIO_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_8 = asSInt(_requestAIO_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_1 = cvt(_requestCIO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_3 = asSInt(_requestCIO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] node _requestCIO_T_5 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_6 = cvt(_requestCIO_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_8 = asSInt(_requestCIO_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node requestBOI_0_0 = eq(_requestBOI_WIRE_1.bits.source, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 48:9] wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node requestBOI_0_1 = eq(_requestBOI_WIRE_3.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 48:9] node requestDOI_0_0 = eq(out[0].d.bits.source, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 48:9] node requestDOI_0_1 = eq(out[0].d.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 48:9] wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 102:36] node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsCI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _beatsCI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_3.bits, _beatsCI_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_3.valid, _beatsCI_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_3.ready, _beatsCI_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), _beatsCI_WIRE_3.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsCI_opdata_1 = bits(_beatsCI_WIRE_3.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 102:36] node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire _beatsEI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE_2.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _beatsEI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_3.bits, _beatsEI_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_3.valid, _beatsEI_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_3.ready, _beatsEI_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsAOI_filtered[0].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect in[0].a.ready, portsAOI_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsAOI_filtered_1[0].bits, in[1].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect in[1].a.ready, portsAOI_filtered_1[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsBIO_filtered[1].bits, _portsBIO_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_1_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_1_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] node _portsBIO_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsBIO_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsBIO_T_2 = or(_portsBIO_T, _portsBIO_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _portsBIO_WIRE_2 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsBIO_WIRE_2, _portsBIO_T_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsCOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _portsCOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_3.bits, _portsCOI_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_3.valid, _portsCOI_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_3.ready, _portsCOI_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsCOI_filtered_1[0].bits, _portsCOI_WIRE_3.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_0_valid_T_3 = and(_portsCOI_WIRE_3.valid, _portsCOI_filtered_0_valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsCOI_WIRE_3.ready, portsCOI_filtered_1[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.data, out[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.source, out[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.size, out[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.param, out[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[1].bits.data, out[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[1].bits.source, out[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[1].bits.size, out[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[1].bits.param, out[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _portsDIO_out_0_d_ready_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsEOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE_2.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _portsEOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_3.bits, _portsEOI_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_3.valid, _portsEOI_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_3.ready, _portsEOI_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsEOI_filtered_1[0].bits, _portsEOI_WIRE_3.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_0_valid_T_3 = and(_portsEOI_WIRE_3.valid, _portsEOI_filtered_0_valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsEOI_WIRE_3.ready, portsEOI_filtered_1[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 60:30] node idle = eq(beatsLeft, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 61:28] node latch = and(idle, out[0].a.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 62:24] node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:51] node readys_valid = bits(_readys_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 21:23] node _readys_T_1 = eq(readys_valid, _readys_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:19] node _readys_T_2 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] when _readys_T_3 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] when _readys_T_4 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 23:23] node _readys_filter_T = not(readys_mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 24:30] node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 24:28] node readys_filter = cat(_readys_filter_T_1, readys_valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 24:21] node _readys_unready_T = shr(readys_filter, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 263:48] node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 263:43] node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 264:17] node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 25:52] node _readys_unready_T_4 = shl(readys_mask, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 25:66] node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 25:58] node _readys_readys_T = shr(readys_unready, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:29] node _readys_readys_T_1 = bits(readys_unready, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:48] node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:39] node readys_readys = not(_readys_readys_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:18] node _readys_T_5 = orr(readys_valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 27:27] node _readys_T_6 = and(latch, _readys_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 27:18] when _readys_T_6 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 27:32] node _readys_mask_T = and(readys_readys, readys_valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 28:29] node _readys_mask_T_1 = shl(_readys_mask_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 255:17] connect readys_mask, _readys_mask_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 28:12] node _readys_T_7 = bits(readys_readys, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 30:11] node _readys_T_8 = bits(_readys_T_7, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] node _readys_T_9 = bits(_readys_T_7, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] wire readys : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[0], _readys_T_8 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[1], _readys_T_9 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] node _winner_T = and(readys[0], portsAOI_filtered[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] wire winner : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[0], _winner_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[1], _winner_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] node prefixOR_1 = or(UInt<1>(0h0), winner[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node _prefixOR_T = or(prefixOR_1, winner[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_1 = eq(winner[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_2 = or(_T, _T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_4 = eq(winner[1], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_5 = or(_T_3, _T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_6 = and(_T_2, _T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:77] node _T_7 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_8 = eq(_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_9 = eq(_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] when _T_9 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] assert(clock, _T_6, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:31] node _T_11 = eq(_T_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:15] node _T_12 = or(winner[0], winner[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:54] node _T_13 = or(_T_11, _T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:36] node _T_14 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node _T_15 = eq(_T_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] when _T_15 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node _T_16 = eq(_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] when _T_16 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node initBeats = or(maskedBeats_0, maskedBeats_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 84:44] node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:52] node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:52] node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:23] connect beatsLeft, _beatsLeft_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:17] wire _state_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] regreset state : UInt<1>[2], clock, reset, _state_WIRE @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:26] node muxState = mux(idle, winner, state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 89:25] connect state, muxState @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 90:13] node allowed = mux(idle, readys, state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 92:24] node _filtered_0_ready_T = and(out[0].a.ready, allowed[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect portsAOI_filtered[0].ready, _filtered_0_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:46] node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_valid_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:24] connect out[0].a.valid, _out_0_a_valid_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:18] wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_1 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_2 : UInt<64> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_3 : UInt<8> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3 @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_4 : { } @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4 @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_5 : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}} @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_6 : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>} @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.fetch, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.fetch, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_7 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_11 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_6.fetch, _out_0_a_bits_WIRE_7 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.secure, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.secure, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_8 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_14 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_6.secure, _out_0_a_bits_WIRE_8 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.privileged, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.privileged, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_9 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_17 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_6.privileged, _out_0_a_bits_WIRE_9 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.writealloc, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.writealloc, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_10 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_20 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_6.writealloc, _out_0_a_bits_WIRE_10 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.readalloc, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.readalloc, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_11 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_11, _out_0_a_bits_T_23 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_6.readalloc, _out_0_a_bits_WIRE_11 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_24 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.modifiable, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_25 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.modifiable, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_26 = or(_out_0_a_bits_T_24, _out_0_a_bits_T_25) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_12 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_12, _out_0_a_bits_T_26 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_6.modifiable, _out_0_a_bits_WIRE_12 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_27 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.bufferable, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_28 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.bufferable, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_29 = or(_out_0_a_bits_T_27, _out_0_a_bits_T_28) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_13 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_13, _out_0_a_bits_T_29 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_6.bufferable, _out_0_a_bits_WIRE_13 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_5.amba_prot, _out_0_a_bits_WIRE_6 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_30 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_31 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_32 = or(_out_0_a_bits_T_30, _out_0_a_bits_T_31) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_14 : UInt<32> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_14, _out_0_a_bits_T_32 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_14 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_33 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_34 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_35 = or(_out_0_a_bits_T_33, _out_0_a_bits_T_34) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_15 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_15, _out_0_a_bits_T_35 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_15 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_36 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_37 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_38 = or(_out_0_a_bits_T_36, _out_0_a_bits_T_37) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_16 : UInt<4> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_16, _out_0_a_bits_T_38 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_16 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_39 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_40 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_41 = or(_out_0_a_bits_T_39, _out_0_a_bits_T_40) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_17 : UInt<3> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_17, _out_0_a_bits_T_41 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_17 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_42 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_43 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _out_0_a_bits_T_44 = or(_out_0_a_bits_T_42, _out_0_a_bits_T_43) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _out_0_a_bits_WIRE_18 : UInt<3> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE_18, _out_0_a_bits_T_44 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_18 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.data, _out_0_a_bits_WIRE.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.user.amba_prot.fetch, _out_0_a_bits_WIRE.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.user.amba_prot.secure, _out_0_a_bits_WIRE.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.user.amba_prot.privileged, _out_0_a_bits_WIRE.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.user.amba_prot.writealloc, _out_0_a_bits_WIRE.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.user.amba_prot.readalloc, _out_0_a_bits_WIRE.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.user.amba_prot.modifiable, _out_0_a_bits_WIRE.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.user.amba_prot.bufferable, _out_0_a_bits_WIRE.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.address, _out_0_a_bits_WIRE.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.source, _out_0_a_bits_WIRE.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.size, _out_0_a_bits_WIRE.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.param, _out_0_a_bits_WIRE.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_73.bits, _WIRE_72.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_73.valid, _WIRE_72.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_73.ready, _WIRE_72.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_73.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_74.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_74.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_74.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_75.bits, _WIRE_74.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_75.valid, _WIRE_74.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_75.ready, _WIRE_74.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_75.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsCOI_filtered_1[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] connect portsEOI_filtered_1[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_76.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_77.bits, _WIRE_76.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_77.valid, _WIRE_76.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_77.ready, _WIRE_76.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_77.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect in[0].d, portsDIO_filtered[0] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] connect portsBIO_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_78.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_79.bits, _WIRE_78.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_79.valid, _WIRE_78.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_79.ready, _WIRE_78.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_79.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_79.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_79.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_79.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_79.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_79.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_79.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_79.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect in[1].d, portsDIO_filtered[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] connect portsBIO_filtered[1].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] module TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 159:18] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.data, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.mask, anonIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.address, anonIn.a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.source, anonIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.size, anonIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.param, anonIn.a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.opcode, anonIn.a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.valid, anonIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect anonIn.a.ready, in[0].a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:55] connect in[0].a.bits.source, _in_0_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:29] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_1.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_3.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 180:23] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 181:26] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_9.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_11.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.bits, _WIRE_12.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, _WIRE_12.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.ready, _WIRE_12.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 191:23] wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.bits, _WIRE_14.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.valid, _WIRE_14.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.ready, _WIRE_14.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 192:26] connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.data, in[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.denied, in[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.sink, in[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.source, in[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.size, in[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.param, in[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.opcode, in[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.valid, in[0].d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect in[0].d.ready, anonIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 156:69] connect anonIn.d.bits.source, _anonIn_d_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 197:32] wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.bits, _WIRE_16.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.valid, _WIRE_16.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.ready, _WIRE_16.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_17.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_17.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_17.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.bits, _WIRE_18.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.valid, _WIRE_18.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.ready, _WIRE_18.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_19.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_19.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_19.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.bits, _WIRE_20.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.valid, _WIRE_20.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.ready, _WIRE_20.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 210:23] wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.bits, _WIRE_22.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.valid, _WIRE_22.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, _WIRE_22.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 211:26] wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 216:19] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.data, out[0].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.mask, out[0].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.address, out[0].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.source, out[0].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.size, out[0].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.param, out[0].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.opcode, out[0].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.valid, out[0].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[0].a.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.bits, _WIRE_24.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.valid, _WIRE_24.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.ready, _WIRE_24.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_25.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.bits, _WIRE_26.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.valid, _WIRE_26.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.ready, _WIRE_26.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_27.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.bits, _WIRE_28.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.valid, _WIRE_28.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.ready, _WIRE_28.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.bits, _WIRE_30.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.valid, _WIRE_30.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.ready, _WIRE_30.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.bits, _WIRE_32.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.valid, _WIRE_32.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.ready, _WIRE_32.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_33.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.bits, _WIRE_34.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.valid, _WIRE_34.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.ready, _WIRE_34.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_35.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.bits, _WIRE_36.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.valid, _WIRE_36.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.ready, _WIRE_36.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.bits, _WIRE_38.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.valid, _WIRE_38.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.ready, _WIRE_38.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.valid, anonOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect anonOut.d.ready, out[0].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[0].d.bits.sink, _out_0_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.bits, _WIRE_40.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.valid, _WIRE_40.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.ready, _WIRE_40.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_41.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_41.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_41.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.bits, _WIRE_42.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.valid, _WIRE_42.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.ready, _WIRE_42.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_43.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_43.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_43.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.bits, _WIRE_44.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.valid, _WIRE_44.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.ready, _WIRE_44.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.bits, _WIRE_46.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.valid, _WIRE_46.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.ready, _WIRE_46.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.bits, _addressC_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.valid, _addressC_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.ready, _addressC_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_1 = cvt(_requestAIO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_3 = asSInt(_requestAIO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_1 = cvt(_requestCIO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_3 = asSInt(_requestCIO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:29] node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 54:56] node _requestDOI_T = shr(out[0].d.bits.source, 2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:10] node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:32] node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:32] node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 56:67] node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 59:20] node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 58:48] wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] node _beatsAI_decode_T = dshl(UInt<6>(0h3f), in[0].a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T = dshl(UInt<6>(0h3f), _beatsBO_WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _beatsCI_decode_T = dshl(UInt<6>(0h3f), _beatsCI_WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 102:36] node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T = dshl(UInt<6>(0h3f), out[0].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsAOI_filtered[0].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect in[0].a.ready, portsAOI_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.data, out[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.source, out[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.size, out[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.param, out[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect out[0].d.ready, portsDIO_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] connect out[0].a, portsAOI_filtered[0] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_48.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_49.bits, _WIRE_48.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_49.valid, _WIRE_48.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_49.ready, _WIRE_48.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_49.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_49.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_50.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_50.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_50.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_51.bits, _WIRE_50.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_51.valid, _WIRE_50.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_51.ready, _WIRE_50.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_51.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.bits, _WIRE_52.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.valid, _WIRE_52.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.ready, _WIRE_52.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_53.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_53.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect in[0].d, portsDIO_filtered[0] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] connect portsBIO_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] module IntXbar_i3_o1 : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 22:9] output auto : { flip anon_in_2 : UInt<1>[1], flip anon_in_1 : UInt<1>[2], flip anon_in_0 : UInt<1>[1], anon_out : UInt<1>[4]} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire anonIn : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonIn_1 : UInt<1>[2] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn_1[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn_1[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonIn_2 : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn_2[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : UInt<1>[4] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut[2] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut[3] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonIn_1, auto.anon_in_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonIn_2, auto.anon_in_2 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonOut[0], anonIn[0] @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 25:44] connect anonOut[1], anonIn_1[0] @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 25:44] connect anonOut[2], anonIn_1[1] @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 25:44] connect anonOut[3], anonIn_2[0] @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 25:44] module BundleBridgeNexus_UInt1 : @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 21:9] output auto : { flip in : UInt<1>, out_1 : UInt<1>, out_0 : UInt<1>} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeIn : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_nodeOut : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out_0, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.out_1, x1_nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut, nodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 59:67] connect x1_nodeOut, nodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 59:67] module BundleBridgeNexus_UInt32 : @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 21:9] output auto : { flip in : UInt<32>, out_1 : UInt<32>, out_0 : UInt<32>} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeIn : UInt<32> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : UInt<32> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_nodeOut : UInt<32> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out_0, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.out_1, x1_nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut, nodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 59:67] connect x1_nodeOut, nodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 59:67] module BundleBridgeNexus_UInt1_1 : @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 21:9] output auto : { out : UInt<1>} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeOut : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeOut, UInt<1>(0h0) @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 59:67] module BundleBridgeNexus_TraceAux : @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 21:9] output auto : { out : { enable : UInt<1>, stall : UInt<1>}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire x1_bundleOut_x_sourceOpt : { enable : UInt<1>, stall : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tile/BaseTile.scala 311:19] connect x1_bundleOut_x_sourceOpt.stall, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/BaseTile.scala 312:16] connect x1_bundleOut_x_sourceOpt.enable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/BaseTile.scala 313:16] wire nodeOut : { enable : UInt<1>, stall : UInt<1>} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.stall @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.enable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] wire defaultWireOpt : { enable : UInt<1>, stall : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tile/BaseTile.scala 311:19] connect defaultWireOpt.stall, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/BaseTile.scala 312:16] connect defaultWireOpt.enable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/BaseTile.scala 313:16] connect nodeOut, defaultWireOpt @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 59:67] module BundleBridgeNexus_NoOutput_4 : @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 21:9] output auto : { flip in : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeIn : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn[0].action @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn[0].ivalid[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn[0].wvalid[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn[0].rvalid[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn[0].valid[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] module TLWidthWidget8_5 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonOut.a.bits, anonIn.a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonOut.a.valid, anonIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 155:19] connect anonIn.a.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 156:18] connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.valid, anonOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 155:19] connect anonOut.d.ready, anonIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 156:18] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 215:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 216:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 217:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 218:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 219:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 220:21] module OptimizationBarrier_TLBEntryData : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module PMPChecker_s3 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 143:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 143:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 143:7] output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 146:14] node default = gt(io.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 156:56] wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.mask, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.addr, UInt<30>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.cfg.r, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.cfg.w, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.cfg.x, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.cfg.a, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.cfg.res, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.cfg.l, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:22] connect pmp0, _pmp0_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:22] connect pmp0.cfg.r, default @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 158:14] connect pmp0.cfg.w, default @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 159:14] connect pmp0.cfg.x, default @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 160:14] node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_lsbMask_T = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_lsbMask_T_1 = bits(_res_hit_lsbMask_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_lsbMask_T_2 = not(_res_hit_lsbMask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node res_hit_lsbMask = or(io.pmp[7].mask, _res_hit_lsbMask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 68:26] node _res_hit_msbMatch_T = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:29] node _res_hit_msbMatch_T_1 = shl(io.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbMatch_T_2 = not(_res_hit_msbMatch_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbMatch_T_3 = or(_res_hit_msbMatch_T_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbMatch_T_4 = not(_res_hit_msbMatch_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbMatch_T_5 = shr(_res_hit_msbMatch_T_4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:53] node _res_hit_msbMatch_T_6 = shr(io.pmp[7].mask, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:72] node _res_hit_msbMatch_T_7 = xor(_res_hit_msbMatch_T, _res_hit_msbMatch_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_msbMatch_T_8 = not(_res_hit_msbMatch_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_msbMatch_T_9 = and(_res_hit_msbMatch_T_7, _res_hit_msbMatch_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_msbMatch = eq(_res_hit_msbMatch_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_lsbMatch_T = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:28] node _res_hit_lsbMatch_T_1 = shl(io.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbMatch_T_2 = not(_res_hit_lsbMatch_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbMatch_T_3 = or(_res_hit_lsbMatch_T_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbMatch_T_4 = not(_res_hit_lsbMatch_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbMatch_T_5 = bits(_res_hit_lsbMatch_T_4, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:55] node _res_hit_lsbMatch_T_6 = bits(res_hit_lsbMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:80] node _res_hit_lsbMatch_T_7 = xor(_res_hit_lsbMatch_T, _res_hit_lsbMatch_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_lsbMatch_T_8 = not(_res_hit_lsbMatch_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_lsbMatch_T_9 = and(_res_hit_lsbMatch_T_7, _res_hit_lsbMatch_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_lsbMatch = eq(_res_hit_lsbMatch_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_1 = and(res_hit_msbMatch, res_hit_lsbMatch) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 71:16] node _res_hit_T_2 = bits(io.pmp[7].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_3 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_4 = bits(_res_hit_T_3, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_5 = not(_res_hit_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_msbsLess_T = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_1 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_2 = not(_res_hit_msbsLess_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_3 = or(_res_hit_msbsLess_T_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_4 = not(_res_hit_msbsLess_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_5 = shr(_res_hit_msbsLess_T_4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess = lt(_res_hit_msbsLess_T, _res_hit_msbsLess_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_1 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_2 = not(_res_hit_msbsEqual_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_3 = or(_res_hit_msbsEqual_T_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_4 = not(_res_hit_msbsEqual_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_5 = shr(_res_hit_msbsEqual_T_4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_6 = xor(_res_hit_msbsEqual_T, _res_hit_msbsEqual_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual = eq(_res_hit_msbsEqual_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_1 = or(_res_hit_lsbsLess_T, _res_hit_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_2 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_3 = not(_res_hit_lsbsLess_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_4 = or(_res_hit_lsbsLess_T_3, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_5 = not(_res_hit_lsbsLess_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_6 = bits(_res_hit_lsbsLess_T_5, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess = lt(_res_hit_lsbsLess_T_1, _res_hit_lsbsLess_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_6 = and(res_hit_msbsEqual, res_hit_lsbsLess) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_7 = or(res_hit_msbsLess, _res_hit_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_msbsLess_T_6 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_7 = shl(io.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_8 = not(_res_hit_msbsLess_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_9 = or(_res_hit_msbsLess_T_8, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_10 = not(_res_hit_msbsLess_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_11 = shr(_res_hit_msbsLess_T_10, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_1 = lt(_res_hit_msbsLess_T_6, _res_hit_msbsLess_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_7 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_8 = shl(io.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_9 = not(_res_hit_msbsEqual_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_10 = or(_res_hit_msbsEqual_T_9, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_11 = not(_res_hit_msbsEqual_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_12 = shr(_res_hit_msbsEqual_T_11, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_13 = xor(_res_hit_msbsEqual_T_7, _res_hit_msbsEqual_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_1 = eq(_res_hit_msbsEqual_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_7 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_8 = or(_res_hit_lsbsLess_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_9 = shl(io.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_10 = not(_res_hit_lsbsLess_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_11 = or(_res_hit_lsbsLess_T_10, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_12 = not(_res_hit_lsbsLess_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_13 = bits(_res_hit_lsbsLess_T_12, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_1 = lt(_res_hit_lsbsLess_T_8, _res_hit_lsbsLess_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_9 = and(res_hit_msbsEqual_1, res_hit_lsbsLess_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_10 = or(res_hit_msbsLess_1, _res_hit_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_11 = and(_res_hit_T_8, _res_hit_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_12 = and(_res_hit_T_2, _res_hit_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit = mux(_res_hit_T, _res_hit_T_1, _res_hit_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore = and(default, _res_ignore_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_aligned_lsbMask_T = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_aligned_lsbMask_T_1 = bits(_res_aligned_lsbMask_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node res_aligned_lsbMask = not(_res_aligned_lsbMask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_aligned_straddlesLowerBound_T = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:35] node _res_aligned_straddlesLowerBound_T_1 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_2 = not(_res_aligned_straddlesLowerBound_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_3 = or(_res_aligned_straddlesLowerBound_T_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_4 = not(_res_aligned_straddlesLowerBound_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_5 = shr(_res_aligned_straddlesLowerBound_T_4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:67] node _res_aligned_straddlesLowerBound_T_6 = xor(_res_aligned_straddlesLowerBound_T, _res_aligned_straddlesLowerBound_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:49] node _res_aligned_straddlesLowerBound_T_7 = eq(_res_aligned_straddlesLowerBound_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:82] node _res_aligned_straddlesLowerBound_T_8 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_9 = not(_res_aligned_straddlesLowerBound_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_10 = or(_res_aligned_straddlesLowerBound_T_9, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_11 = not(_res_aligned_straddlesLowerBound_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_12 = bits(_res_aligned_straddlesLowerBound_T_11, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:108] node _res_aligned_straddlesLowerBound_T_13 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:129] node _res_aligned_straddlesLowerBound_T_14 = not(_res_aligned_straddlesLowerBound_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:127] node _res_aligned_straddlesLowerBound_T_15 = and(_res_aligned_straddlesLowerBound_T_12, _res_aligned_straddlesLowerBound_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:125] node _res_aligned_straddlesLowerBound_T_16 = neq(_res_aligned_straddlesLowerBound_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:147] node res_aligned_straddlesLowerBound = and(_res_aligned_straddlesLowerBound_T_7, _res_aligned_straddlesLowerBound_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:90] node _res_aligned_straddlesUpperBound_T = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:35] node _res_aligned_straddlesUpperBound_T_1 = shl(io.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_2 = not(_res_aligned_straddlesUpperBound_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_3 = or(_res_aligned_straddlesUpperBound_T_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_4 = not(_res_aligned_straddlesUpperBound_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_5 = shr(_res_aligned_straddlesUpperBound_T_4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:62] node _res_aligned_straddlesUpperBound_T_6 = xor(_res_aligned_straddlesUpperBound_T, _res_aligned_straddlesUpperBound_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:49] node _res_aligned_straddlesUpperBound_T_7 = eq(_res_aligned_straddlesUpperBound_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:77] node _res_aligned_straddlesUpperBound_T_8 = shl(io.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_9 = not(_res_aligned_straddlesUpperBound_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_10 = or(_res_aligned_straddlesUpperBound_T_9, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_11 = not(_res_aligned_straddlesUpperBound_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_12 = bits(_res_aligned_straddlesUpperBound_T_11, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:98] node _res_aligned_straddlesUpperBound_T_13 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:119] node _res_aligned_straddlesUpperBound_T_14 = or(_res_aligned_straddlesUpperBound_T_13, res_aligned_lsbMask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:136] node _res_aligned_straddlesUpperBound_T_15 = and(_res_aligned_straddlesUpperBound_T_12, _res_aligned_straddlesUpperBound_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:115] node _res_aligned_straddlesUpperBound_T_16 = neq(_res_aligned_straddlesUpperBound_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:148] node res_aligned_straddlesUpperBound = and(_res_aligned_straddlesUpperBound_T_7, _res_aligned_straddlesUpperBound_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:85] node _res_aligned_rangeAligned_T = or(res_aligned_straddlesLowerBound, res_aligned_straddlesUpperBound) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:46] node res_aligned_rangeAligned = eq(_res_aligned_rangeAligned_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:24] node _res_aligned_pow2Aligned_T = bits(io.pmp[7].mask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:39] node _res_aligned_pow2Aligned_T_1 = not(_res_aligned_pow2Aligned_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:34] node _res_aligned_pow2Aligned_T_2 = and(res_aligned_lsbMask, _res_aligned_pow2Aligned_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:32] node res_aligned_pow2Aligned = eq(_res_aligned_pow2Aligned_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:57] node _res_aligned_T = bits(io.pmp[7].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node res_aligned = mux(_res_aligned_T, res_aligned_pow2Aligned, res_aligned_rangeAligned) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 127:8] node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_6 = eq(_res_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_8 = eq(_res_T_7, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_10 = eq(_res_T_9, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_12 = eq(_res_T_11, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_14 = eq(_res_T_13, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_16 = eq(_res_T_15, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_17 = eq(res_ignore, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_18 = and(_res_T_17, res_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_19 = and(_res_T_18, res_aligned) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_21 = and(_res_T_19, _res_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_22 = and(io.pmp[7].cfg.l, res_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_23 = and(_res_T_22, res_aligned) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_25 = and(_res_T_23, _res_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_26 = eq(res_ignore, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_27 = and(_res_T_26, res_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_28 = and(_res_T_27, res_aligned) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_30 = and(_res_T_28, _res_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_31 = and(io.pmp[7].cfg.l, res_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_32 = and(_res_T_31, res_aligned) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_34 = and(_res_T_32, _res_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_35 = eq(res_ignore, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_36 = and(_res_T_35, res_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_37 = and(_res_T_36, res_aligned) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_39 = and(_res_T_37, _res_T_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_40 = and(io.pmp[7].cfg.l, res_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_41 = and(_res_T_40, res_aligned) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_43 = and(_res_T_41, _res_T_42) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur, io.pmp[7] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_1 = and(res_aligned, _res_cur_cfg_r_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur.cfg.r, _res_cur_cfg_r_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_1 = and(res_aligned, _res_cur_cfg_w_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur.cfg.w, _res_cur_cfg_w_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_1 = and(res_aligned, _res_cur_cfg_x_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur.cfg.x, _res_cur_cfg_x_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_44 = mux(res_hit, res_cur, pmp0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_13 = bits(io.pmp[6].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_lsbMask_T_3 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_lsbMask_T_4 = bits(_res_hit_lsbMask_T_3, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_lsbMask_T_5 = not(_res_hit_lsbMask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node res_hit_lsbMask_1 = or(io.pmp[6].mask, _res_hit_lsbMask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 68:26] node _res_hit_msbMatch_T_10 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:29] node _res_hit_msbMatch_T_11 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbMatch_T_12 = not(_res_hit_msbMatch_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbMatch_T_13 = or(_res_hit_msbMatch_T_12, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbMatch_T_14 = not(_res_hit_msbMatch_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbMatch_T_15 = shr(_res_hit_msbMatch_T_14, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:53] node _res_hit_msbMatch_T_16 = shr(io.pmp[6].mask, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:72] node _res_hit_msbMatch_T_17 = xor(_res_hit_msbMatch_T_10, _res_hit_msbMatch_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_msbMatch_T_18 = not(_res_hit_msbMatch_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_msbMatch_T_19 = and(_res_hit_msbMatch_T_17, _res_hit_msbMatch_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_msbMatch_1 = eq(_res_hit_msbMatch_T_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_lsbMatch_T_10 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:28] node _res_hit_lsbMatch_T_11 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbMatch_T_12 = not(_res_hit_lsbMatch_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbMatch_T_13 = or(_res_hit_lsbMatch_T_12, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbMatch_T_14 = not(_res_hit_lsbMatch_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbMatch_T_15 = bits(_res_hit_lsbMatch_T_14, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:55] node _res_hit_lsbMatch_T_16 = bits(res_hit_lsbMask_1, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:80] node _res_hit_lsbMatch_T_17 = xor(_res_hit_lsbMatch_T_10, _res_hit_lsbMatch_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_lsbMatch_T_18 = not(_res_hit_lsbMatch_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_lsbMatch_T_19 = and(_res_hit_lsbMatch_T_17, _res_hit_lsbMatch_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_lsbMatch_1 = eq(_res_hit_lsbMatch_T_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_14 = and(res_hit_msbMatch_1, res_hit_lsbMatch_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 71:16] node _res_hit_T_15 = bits(io.pmp[6].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_16 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_17 = bits(_res_hit_T_16, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_18 = not(_res_hit_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_msbsLess_T_12 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_13 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_14 = not(_res_hit_msbsLess_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_15 = or(_res_hit_msbsLess_T_14, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_16 = not(_res_hit_msbsLess_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_17 = shr(_res_hit_msbsLess_T_16, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_2 = lt(_res_hit_msbsLess_T_12, _res_hit_msbsLess_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_14 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_15 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_16 = not(_res_hit_msbsEqual_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_17 = or(_res_hit_msbsEqual_T_16, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_18 = not(_res_hit_msbsEqual_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_19 = shr(_res_hit_msbsEqual_T_18, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_20 = xor(_res_hit_msbsEqual_T_14, _res_hit_msbsEqual_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_2 = eq(_res_hit_msbsEqual_T_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_14 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_15 = or(_res_hit_lsbsLess_T_14, _res_hit_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_16 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_17 = not(_res_hit_lsbsLess_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_18 = or(_res_hit_lsbsLess_T_17, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_19 = not(_res_hit_lsbsLess_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_20 = bits(_res_hit_lsbsLess_T_19, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_2 = lt(_res_hit_lsbsLess_T_15, _res_hit_lsbsLess_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_19 = and(res_hit_msbsEqual_2, res_hit_lsbsLess_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_20 = or(res_hit_msbsLess_2, _res_hit_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_21 = eq(_res_hit_T_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_msbsLess_T_18 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_19 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_20 = not(_res_hit_msbsLess_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_21 = or(_res_hit_msbsLess_T_20, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_22 = not(_res_hit_msbsLess_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_23 = shr(_res_hit_msbsLess_T_22, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_3 = lt(_res_hit_msbsLess_T_18, _res_hit_msbsLess_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_21 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_22 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_23 = not(_res_hit_msbsEqual_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_24 = or(_res_hit_msbsEqual_T_23, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_25 = not(_res_hit_msbsEqual_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_26 = shr(_res_hit_msbsEqual_T_25, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_27 = xor(_res_hit_msbsEqual_T_21, _res_hit_msbsEqual_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_3 = eq(_res_hit_msbsEqual_T_27, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_21 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_22 = or(_res_hit_lsbsLess_T_21, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_23 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_24 = not(_res_hit_lsbsLess_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_25 = or(_res_hit_lsbsLess_T_24, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_26 = not(_res_hit_lsbsLess_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_27 = bits(_res_hit_lsbsLess_T_26, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_3 = lt(_res_hit_lsbsLess_T_22, _res_hit_lsbsLess_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_22 = and(res_hit_msbsEqual_3, res_hit_lsbsLess_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_23 = or(res_hit_msbsLess_3, _res_hit_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_24 = and(_res_hit_T_21, _res_hit_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_25 = and(_res_hit_T_15, _res_hit_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_1 = mux(_res_hit_T_13, _res_hit_T_14, _res_hit_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_1 = and(default, _res_ignore_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_aligned_lsbMask_T_2 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_aligned_lsbMask_T_3 = bits(_res_aligned_lsbMask_T_2, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node res_aligned_lsbMask_1 = not(_res_aligned_lsbMask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_aligned_straddlesLowerBound_T_17 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:35] node _res_aligned_straddlesLowerBound_T_18 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_19 = not(_res_aligned_straddlesLowerBound_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_20 = or(_res_aligned_straddlesLowerBound_T_19, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_21 = not(_res_aligned_straddlesLowerBound_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_22 = shr(_res_aligned_straddlesLowerBound_T_21, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:67] node _res_aligned_straddlesLowerBound_T_23 = xor(_res_aligned_straddlesLowerBound_T_17, _res_aligned_straddlesLowerBound_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:49] node _res_aligned_straddlesLowerBound_T_24 = eq(_res_aligned_straddlesLowerBound_T_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:82] node _res_aligned_straddlesLowerBound_T_25 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_26 = not(_res_aligned_straddlesLowerBound_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_27 = or(_res_aligned_straddlesLowerBound_T_26, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_28 = not(_res_aligned_straddlesLowerBound_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_29 = bits(_res_aligned_straddlesLowerBound_T_28, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:108] node _res_aligned_straddlesLowerBound_T_30 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:129] node _res_aligned_straddlesLowerBound_T_31 = not(_res_aligned_straddlesLowerBound_T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:127] node _res_aligned_straddlesLowerBound_T_32 = and(_res_aligned_straddlesLowerBound_T_29, _res_aligned_straddlesLowerBound_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:125] node _res_aligned_straddlesLowerBound_T_33 = neq(_res_aligned_straddlesLowerBound_T_32, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:147] node res_aligned_straddlesLowerBound_1 = and(_res_aligned_straddlesLowerBound_T_24, _res_aligned_straddlesLowerBound_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:90] node _res_aligned_straddlesUpperBound_T_17 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:35] node _res_aligned_straddlesUpperBound_T_18 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_19 = not(_res_aligned_straddlesUpperBound_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_20 = or(_res_aligned_straddlesUpperBound_T_19, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_21 = not(_res_aligned_straddlesUpperBound_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_22 = shr(_res_aligned_straddlesUpperBound_T_21, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:62] node _res_aligned_straddlesUpperBound_T_23 = xor(_res_aligned_straddlesUpperBound_T_17, _res_aligned_straddlesUpperBound_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:49] node _res_aligned_straddlesUpperBound_T_24 = eq(_res_aligned_straddlesUpperBound_T_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:77] node _res_aligned_straddlesUpperBound_T_25 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_26 = not(_res_aligned_straddlesUpperBound_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_27 = or(_res_aligned_straddlesUpperBound_T_26, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_28 = not(_res_aligned_straddlesUpperBound_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_29 = bits(_res_aligned_straddlesUpperBound_T_28, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:98] node _res_aligned_straddlesUpperBound_T_30 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:119] node _res_aligned_straddlesUpperBound_T_31 = or(_res_aligned_straddlesUpperBound_T_30, res_aligned_lsbMask_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:136] node _res_aligned_straddlesUpperBound_T_32 = and(_res_aligned_straddlesUpperBound_T_29, _res_aligned_straddlesUpperBound_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:115] node _res_aligned_straddlesUpperBound_T_33 = neq(_res_aligned_straddlesUpperBound_T_32, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:148] node res_aligned_straddlesUpperBound_1 = and(_res_aligned_straddlesUpperBound_T_24, _res_aligned_straddlesUpperBound_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:85] node _res_aligned_rangeAligned_T_1 = or(res_aligned_straddlesLowerBound_1, res_aligned_straddlesUpperBound_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:46] node res_aligned_rangeAligned_1 = eq(_res_aligned_rangeAligned_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:24] node _res_aligned_pow2Aligned_T_3 = bits(io.pmp[6].mask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:39] node _res_aligned_pow2Aligned_T_4 = not(_res_aligned_pow2Aligned_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:34] node _res_aligned_pow2Aligned_T_5 = and(res_aligned_lsbMask_1, _res_aligned_pow2Aligned_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:32] node res_aligned_pow2Aligned_1 = eq(_res_aligned_pow2Aligned_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:57] node _res_aligned_T_1 = bits(io.pmp[6].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node res_aligned_1 = mux(_res_aligned_T_1, res_aligned_pow2Aligned_1, res_aligned_rangeAligned_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 127:8] node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_51 = eq(_res_T_50, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_53 = eq(_res_T_52, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_55 = eq(_res_T_54, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_57 = eq(_res_T_56, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_59 = eq(_res_T_58, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_61 = eq(_res_T_60, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_63 = and(_res_T_62, res_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_64 = and(_res_T_63, res_aligned_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_66 = and(_res_T_64, _res_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_68 = and(_res_T_67, res_aligned_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_70 = and(_res_T_68, _res_T_69) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_72 = and(_res_T_71, res_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_73 = and(_res_T_72, res_aligned_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_75 = and(_res_T_73, _res_T_74) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_77 = and(_res_T_76, res_aligned_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_79 = and(_res_T_77, _res_T_78) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_81 = and(_res_T_80, res_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_82 = and(_res_T_81, res_aligned_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_84 = and(_res_T_82, _res_T_83) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_86 = and(_res_T_85, res_aligned_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_88 = and(_res_T_86, _res_T_87) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_1, io.pmp[6] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_3 = and(res_aligned_1, _res_cur_cfg_r_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_3 = and(res_aligned_1, _res_cur_cfg_w_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_3 = and(res_aligned_1, _res_cur_cfg_x_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_26 = bits(io.pmp[5].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_lsbMask_T_7 = bits(_res_hit_lsbMask_T_6, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_lsbMask_T_8 = not(_res_hit_lsbMask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node res_hit_lsbMask_2 = or(io.pmp[5].mask, _res_hit_lsbMask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 68:26] node _res_hit_msbMatch_T_20 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:29] node _res_hit_msbMatch_T_21 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbMatch_T_22 = not(_res_hit_msbMatch_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbMatch_T_23 = or(_res_hit_msbMatch_T_22, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbMatch_T_24 = not(_res_hit_msbMatch_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbMatch_T_25 = shr(_res_hit_msbMatch_T_24, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:53] node _res_hit_msbMatch_T_26 = shr(io.pmp[5].mask, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:72] node _res_hit_msbMatch_T_27 = xor(_res_hit_msbMatch_T_20, _res_hit_msbMatch_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_msbMatch_T_28 = not(_res_hit_msbMatch_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_msbMatch_T_29 = and(_res_hit_msbMatch_T_27, _res_hit_msbMatch_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_msbMatch_2 = eq(_res_hit_msbMatch_T_29, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_lsbMatch_T_20 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:28] node _res_hit_lsbMatch_T_21 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbMatch_T_22 = not(_res_hit_lsbMatch_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbMatch_T_23 = or(_res_hit_lsbMatch_T_22, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbMatch_T_24 = not(_res_hit_lsbMatch_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbMatch_T_25 = bits(_res_hit_lsbMatch_T_24, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:55] node _res_hit_lsbMatch_T_26 = bits(res_hit_lsbMask_2, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:80] node _res_hit_lsbMatch_T_27 = xor(_res_hit_lsbMatch_T_20, _res_hit_lsbMatch_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_lsbMatch_T_28 = not(_res_hit_lsbMatch_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_lsbMatch_T_29 = and(_res_hit_lsbMatch_T_27, _res_hit_lsbMatch_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_lsbMatch_2 = eq(_res_hit_lsbMatch_T_29, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_27 = and(res_hit_msbMatch_2, res_hit_lsbMatch_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 71:16] node _res_hit_T_28 = bits(io.pmp[5].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_29 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_30 = bits(_res_hit_T_29, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_31 = not(_res_hit_T_30) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_msbsLess_T_24 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_25 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_26 = not(_res_hit_msbsLess_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_27 = or(_res_hit_msbsLess_T_26, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_28 = not(_res_hit_msbsLess_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_29 = shr(_res_hit_msbsLess_T_28, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_4 = lt(_res_hit_msbsLess_T_24, _res_hit_msbsLess_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_28 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_29 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_30 = not(_res_hit_msbsEqual_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_31 = or(_res_hit_msbsEqual_T_30, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_32 = not(_res_hit_msbsEqual_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_33 = shr(_res_hit_msbsEqual_T_32, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_34 = xor(_res_hit_msbsEqual_T_28, _res_hit_msbsEqual_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_4 = eq(_res_hit_msbsEqual_T_34, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_28 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_29 = or(_res_hit_lsbsLess_T_28, _res_hit_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_30 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_31 = not(_res_hit_lsbsLess_T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_32 = or(_res_hit_lsbsLess_T_31, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_33 = not(_res_hit_lsbsLess_T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_34 = bits(_res_hit_lsbsLess_T_33, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_4 = lt(_res_hit_lsbsLess_T_29, _res_hit_lsbsLess_T_34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_32 = and(res_hit_msbsEqual_4, res_hit_lsbsLess_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_33 = or(res_hit_msbsLess_4, _res_hit_T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_msbsLess_T_30 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_31 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_32 = not(_res_hit_msbsLess_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_33 = or(_res_hit_msbsLess_T_32, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_34 = not(_res_hit_msbsLess_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_35 = shr(_res_hit_msbsLess_T_34, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_5 = lt(_res_hit_msbsLess_T_30, _res_hit_msbsLess_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_35 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_36 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_37 = not(_res_hit_msbsEqual_T_36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_38 = or(_res_hit_msbsEqual_T_37, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_39 = not(_res_hit_msbsEqual_T_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_40 = shr(_res_hit_msbsEqual_T_39, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_41 = xor(_res_hit_msbsEqual_T_35, _res_hit_msbsEqual_T_40) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_5 = eq(_res_hit_msbsEqual_T_41, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_35 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_36 = or(_res_hit_lsbsLess_T_35, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_37 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_38 = not(_res_hit_lsbsLess_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_39 = or(_res_hit_lsbsLess_T_38, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_40 = not(_res_hit_lsbsLess_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_41 = bits(_res_hit_lsbsLess_T_40, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_5 = lt(_res_hit_lsbsLess_T_36, _res_hit_lsbsLess_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_35 = and(res_hit_msbsEqual_5, res_hit_lsbsLess_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_36 = or(res_hit_msbsLess_5, _res_hit_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_37 = and(_res_hit_T_34, _res_hit_T_36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_38 = and(_res_hit_T_28, _res_hit_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_2 = mux(_res_hit_T_26, _res_hit_T_27, _res_hit_T_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_2 = and(default, _res_ignore_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_aligned_lsbMask_T_4 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_aligned_lsbMask_T_5 = bits(_res_aligned_lsbMask_T_4, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node res_aligned_lsbMask_2 = not(_res_aligned_lsbMask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_aligned_straddlesLowerBound_T_34 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:35] node _res_aligned_straddlesLowerBound_T_35 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_36 = not(_res_aligned_straddlesLowerBound_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_37 = or(_res_aligned_straddlesLowerBound_T_36, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_38 = not(_res_aligned_straddlesLowerBound_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_39 = shr(_res_aligned_straddlesLowerBound_T_38, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:67] node _res_aligned_straddlesLowerBound_T_40 = xor(_res_aligned_straddlesLowerBound_T_34, _res_aligned_straddlesLowerBound_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:49] node _res_aligned_straddlesLowerBound_T_41 = eq(_res_aligned_straddlesLowerBound_T_40, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:82] node _res_aligned_straddlesLowerBound_T_42 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_43 = not(_res_aligned_straddlesLowerBound_T_42) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_44 = or(_res_aligned_straddlesLowerBound_T_43, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_45 = not(_res_aligned_straddlesLowerBound_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_46 = bits(_res_aligned_straddlesLowerBound_T_45, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:108] node _res_aligned_straddlesLowerBound_T_47 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:129] node _res_aligned_straddlesLowerBound_T_48 = not(_res_aligned_straddlesLowerBound_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:127] node _res_aligned_straddlesLowerBound_T_49 = and(_res_aligned_straddlesLowerBound_T_46, _res_aligned_straddlesLowerBound_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:125] node _res_aligned_straddlesLowerBound_T_50 = neq(_res_aligned_straddlesLowerBound_T_49, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:147] node res_aligned_straddlesLowerBound_2 = and(_res_aligned_straddlesLowerBound_T_41, _res_aligned_straddlesLowerBound_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:90] node _res_aligned_straddlesUpperBound_T_34 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:35] node _res_aligned_straddlesUpperBound_T_35 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_36 = not(_res_aligned_straddlesUpperBound_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_37 = or(_res_aligned_straddlesUpperBound_T_36, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_38 = not(_res_aligned_straddlesUpperBound_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_39 = shr(_res_aligned_straddlesUpperBound_T_38, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:62] node _res_aligned_straddlesUpperBound_T_40 = xor(_res_aligned_straddlesUpperBound_T_34, _res_aligned_straddlesUpperBound_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:49] node _res_aligned_straddlesUpperBound_T_41 = eq(_res_aligned_straddlesUpperBound_T_40, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:77] node _res_aligned_straddlesUpperBound_T_42 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_43 = not(_res_aligned_straddlesUpperBound_T_42) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_44 = or(_res_aligned_straddlesUpperBound_T_43, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_45 = not(_res_aligned_straddlesUpperBound_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_46 = bits(_res_aligned_straddlesUpperBound_T_45, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:98] node _res_aligned_straddlesUpperBound_T_47 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:119] node _res_aligned_straddlesUpperBound_T_48 = or(_res_aligned_straddlesUpperBound_T_47, res_aligned_lsbMask_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:136] node _res_aligned_straddlesUpperBound_T_49 = and(_res_aligned_straddlesUpperBound_T_46, _res_aligned_straddlesUpperBound_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:115] node _res_aligned_straddlesUpperBound_T_50 = neq(_res_aligned_straddlesUpperBound_T_49, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:148] node res_aligned_straddlesUpperBound_2 = and(_res_aligned_straddlesUpperBound_T_41, _res_aligned_straddlesUpperBound_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:85] node _res_aligned_rangeAligned_T_2 = or(res_aligned_straddlesLowerBound_2, res_aligned_straddlesUpperBound_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:46] node res_aligned_rangeAligned_2 = eq(_res_aligned_rangeAligned_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:24] node _res_aligned_pow2Aligned_T_6 = bits(io.pmp[5].mask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:39] node _res_aligned_pow2Aligned_T_7 = not(_res_aligned_pow2Aligned_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:34] node _res_aligned_pow2Aligned_T_8 = and(res_aligned_lsbMask_2, _res_aligned_pow2Aligned_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:32] node res_aligned_pow2Aligned_2 = eq(_res_aligned_pow2Aligned_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:57] node _res_aligned_T_2 = bits(io.pmp[5].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node res_aligned_2 = mux(_res_aligned_T_2, res_aligned_pow2Aligned_2, res_aligned_rangeAligned_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 127:8] node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_96 = eq(_res_T_95, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_98 = eq(_res_T_97, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_100 = eq(_res_T_99, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_102 = eq(_res_T_101, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_104 = eq(_res_T_103, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_106 = eq(_res_T_105, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_108 = and(_res_T_107, res_hit_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_109 = and(_res_T_108, res_aligned_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_111 = and(_res_T_109, _res_T_110) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_113 = and(_res_T_112, res_aligned_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_115 = and(_res_T_113, _res_T_114) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_117 = and(_res_T_116, res_hit_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_118 = and(_res_T_117, res_aligned_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_120 = and(_res_T_118, _res_T_119) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_122 = and(_res_T_121, res_aligned_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_124 = and(_res_T_122, _res_T_123) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_126 = and(_res_T_125, res_hit_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_127 = and(_res_T_126, res_aligned_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_129 = and(_res_T_127, _res_T_128) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_131 = and(_res_T_130, res_aligned_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_133 = and(_res_T_131, _res_T_132) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_2, io.pmp[5] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_5 = and(res_aligned_2, _res_cur_cfg_r_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_5 = and(res_aligned_2, _res_cur_cfg_w_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_5 = and(res_aligned_2, _res_cur_cfg_x_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_39 = bits(io.pmp[4].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_lsbMask_T_9 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_lsbMask_T_10 = bits(_res_hit_lsbMask_T_9, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_lsbMask_T_11 = not(_res_hit_lsbMask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node res_hit_lsbMask_3 = or(io.pmp[4].mask, _res_hit_lsbMask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 68:26] node _res_hit_msbMatch_T_30 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:29] node _res_hit_msbMatch_T_31 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbMatch_T_32 = not(_res_hit_msbMatch_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbMatch_T_33 = or(_res_hit_msbMatch_T_32, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbMatch_T_34 = not(_res_hit_msbMatch_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbMatch_T_35 = shr(_res_hit_msbMatch_T_34, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:53] node _res_hit_msbMatch_T_36 = shr(io.pmp[4].mask, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:72] node _res_hit_msbMatch_T_37 = xor(_res_hit_msbMatch_T_30, _res_hit_msbMatch_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_msbMatch_T_38 = not(_res_hit_msbMatch_T_36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_msbMatch_T_39 = and(_res_hit_msbMatch_T_37, _res_hit_msbMatch_T_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_msbMatch_3 = eq(_res_hit_msbMatch_T_39, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_lsbMatch_T_30 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:28] node _res_hit_lsbMatch_T_31 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbMatch_T_32 = not(_res_hit_lsbMatch_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbMatch_T_33 = or(_res_hit_lsbMatch_T_32, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbMatch_T_34 = not(_res_hit_lsbMatch_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbMatch_T_35 = bits(_res_hit_lsbMatch_T_34, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:55] node _res_hit_lsbMatch_T_36 = bits(res_hit_lsbMask_3, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:80] node _res_hit_lsbMatch_T_37 = xor(_res_hit_lsbMatch_T_30, _res_hit_lsbMatch_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_lsbMatch_T_38 = not(_res_hit_lsbMatch_T_36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_lsbMatch_T_39 = and(_res_hit_lsbMatch_T_37, _res_hit_lsbMatch_T_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_lsbMatch_3 = eq(_res_hit_lsbMatch_T_39, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_40 = and(res_hit_msbMatch_3, res_hit_lsbMatch_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 71:16] node _res_hit_T_41 = bits(io.pmp[4].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_42 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_43 = bits(_res_hit_T_42, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_44 = not(_res_hit_T_43) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_msbsLess_T_36 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_37 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_38 = not(_res_hit_msbsLess_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_39 = or(_res_hit_msbsLess_T_38, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_40 = not(_res_hit_msbsLess_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_41 = shr(_res_hit_msbsLess_T_40, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_6 = lt(_res_hit_msbsLess_T_36, _res_hit_msbsLess_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_42 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_43 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_44 = not(_res_hit_msbsEqual_T_43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_45 = or(_res_hit_msbsEqual_T_44, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_46 = not(_res_hit_msbsEqual_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_47 = shr(_res_hit_msbsEqual_T_46, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_48 = xor(_res_hit_msbsEqual_T_42, _res_hit_msbsEqual_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_6 = eq(_res_hit_msbsEqual_T_48, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_42 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_43 = or(_res_hit_lsbsLess_T_42, _res_hit_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_44 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_45 = not(_res_hit_lsbsLess_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_46 = or(_res_hit_lsbsLess_T_45, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_47 = not(_res_hit_lsbsLess_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_48 = bits(_res_hit_lsbsLess_T_47, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_6 = lt(_res_hit_lsbsLess_T_43, _res_hit_lsbsLess_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_45 = and(res_hit_msbsEqual_6, res_hit_lsbsLess_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_46 = or(res_hit_msbsLess_6, _res_hit_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_47 = eq(_res_hit_T_46, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_msbsLess_T_42 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_43 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_44 = not(_res_hit_msbsLess_T_43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_45 = or(_res_hit_msbsLess_T_44, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_46 = not(_res_hit_msbsLess_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_47 = shr(_res_hit_msbsLess_T_46, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_7 = lt(_res_hit_msbsLess_T_42, _res_hit_msbsLess_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_49 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_50 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_51 = not(_res_hit_msbsEqual_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_52 = or(_res_hit_msbsEqual_T_51, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_53 = not(_res_hit_msbsEqual_T_52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_54 = shr(_res_hit_msbsEqual_T_53, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_55 = xor(_res_hit_msbsEqual_T_49, _res_hit_msbsEqual_T_54) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_7 = eq(_res_hit_msbsEqual_T_55, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_49 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_50 = or(_res_hit_lsbsLess_T_49, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_51 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_52 = not(_res_hit_lsbsLess_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_53 = or(_res_hit_lsbsLess_T_52, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_54 = not(_res_hit_lsbsLess_T_53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_55 = bits(_res_hit_lsbsLess_T_54, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_7 = lt(_res_hit_lsbsLess_T_50, _res_hit_lsbsLess_T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_48 = and(res_hit_msbsEqual_7, res_hit_lsbsLess_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_49 = or(res_hit_msbsLess_7, _res_hit_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_50 = and(_res_hit_T_47, _res_hit_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_51 = and(_res_hit_T_41, _res_hit_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_3 = mux(_res_hit_T_39, _res_hit_T_40, _res_hit_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_3 = and(default, _res_ignore_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_aligned_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_aligned_lsbMask_T_7 = bits(_res_aligned_lsbMask_T_6, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node res_aligned_lsbMask_3 = not(_res_aligned_lsbMask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_aligned_straddlesLowerBound_T_51 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:35] node _res_aligned_straddlesLowerBound_T_52 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_53 = not(_res_aligned_straddlesLowerBound_T_52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_54 = or(_res_aligned_straddlesLowerBound_T_53, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_55 = not(_res_aligned_straddlesLowerBound_T_54) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_56 = shr(_res_aligned_straddlesLowerBound_T_55, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:67] node _res_aligned_straddlesLowerBound_T_57 = xor(_res_aligned_straddlesLowerBound_T_51, _res_aligned_straddlesLowerBound_T_56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:49] node _res_aligned_straddlesLowerBound_T_58 = eq(_res_aligned_straddlesLowerBound_T_57, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:82] node _res_aligned_straddlesLowerBound_T_59 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_60 = not(_res_aligned_straddlesLowerBound_T_59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_61 = or(_res_aligned_straddlesLowerBound_T_60, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_62 = not(_res_aligned_straddlesLowerBound_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_63 = bits(_res_aligned_straddlesLowerBound_T_62, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:108] node _res_aligned_straddlesLowerBound_T_64 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:129] node _res_aligned_straddlesLowerBound_T_65 = not(_res_aligned_straddlesLowerBound_T_64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:127] node _res_aligned_straddlesLowerBound_T_66 = and(_res_aligned_straddlesLowerBound_T_63, _res_aligned_straddlesLowerBound_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:125] node _res_aligned_straddlesLowerBound_T_67 = neq(_res_aligned_straddlesLowerBound_T_66, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:147] node res_aligned_straddlesLowerBound_3 = and(_res_aligned_straddlesLowerBound_T_58, _res_aligned_straddlesLowerBound_T_67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:90] node _res_aligned_straddlesUpperBound_T_51 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:35] node _res_aligned_straddlesUpperBound_T_52 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_53 = not(_res_aligned_straddlesUpperBound_T_52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_54 = or(_res_aligned_straddlesUpperBound_T_53, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_55 = not(_res_aligned_straddlesUpperBound_T_54) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_56 = shr(_res_aligned_straddlesUpperBound_T_55, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:62] node _res_aligned_straddlesUpperBound_T_57 = xor(_res_aligned_straddlesUpperBound_T_51, _res_aligned_straddlesUpperBound_T_56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:49] node _res_aligned_straddlesUpperBound_T_58 = eq(_res_aligned_straddlesUpperBound_T_57, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:77] node _res_aligned_straddlesUpperBound_T_59 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_60 = not(_res_aligned_straddlesUpperBound_T_59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_61 = or(_res_aligned_straddlesUpperBound_T_60, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_62 = not(_res_aligned_straddlesUpperBound_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_63 = bits(_res_aligned_straddlesUpperBound_T_62, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:98] node _res_aligned_straddlesUpperBound_T_64 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:119] node _res_aligned_straddlesUpperBound_T_65 = or(_res_aligned_straddlesUpperBound_T_64, res_aligned_lsbMask_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:136] node _res_aligned_straddlesUpperBound_T_66 = and(_res_aligned_straddlesUpperBound_T_63, _res_aligned_straddlesUpperBound_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:115] node _res_aligned_straddlesUpperBound_T_67 = neq(_res_aligned_straddlesUpperBound_T_66, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:148] node res_aligned_straddlesUpperBound_3 = and(_res_aligned_straddlesUpperBound_T_58, _res_aligned_straddlesUpperBound_T_67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:85] node _res_aligned_rangeAligned_T_3 = or(res_aligned_straddlesLowerBound_3, res_aligned_straddlesUpperBound_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:46] node res_aligned_rangeAligned_3 = eq(_res_aligned_rangeAligned_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:24] node _res_aligned_pow2Aligned_T_9 = bits(io.pmp[4].mask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:39] node _res_aligned_pow2Aligned_T_10 = not(_res_aligned_pow2Aligned_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:34] node _res_aligned_pow2Aligned_T_11 = and(res_aligned_lsbMask_3, _res_aligned_pow2Aligned_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:32] node res_aligned_pow2Aligned_3 = eq(_res_aligned_pow2Aligned_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:57] node _res_aligned_T_3 = bits(io.pmp[4].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node res_aligned_3 = mux(_res_aligned_T_3, res_aligned_pow2Aligned_3, res_aligned_rangeAligned_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 127:8] node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_141 = eq(_res_T_140, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_143 = eq(_res_T_142, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_145 = eq(_res_T_144, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_147 = eq(_res_T_146, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_149 = eq(_res_T_148, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_151 = eq(_res_T_150, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_153 = and(_res_T_152, res_hit_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_154 = and(_res_T_153, res_aligned_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_156 = and(_res_T_154, _res_T_155) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_158 = and(_res_T_157, res_aligned_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_160 = and(_res_T_158, _res_T_159) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_162 = and(_res_T_161, res_hit_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_163 = and(_res_T_162, res_aligned_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_165 = and(_res_T_163, _res_T_164) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_167 = and(_res_T_166, res_aligned_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_169 = and(_res_T_167, _res_T_168) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_171 = and(_res_T_170, res_hit_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_172 = and(_res_T_171, res_aligned_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_174 = and(_res_T_172, _res_T_173) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_176 = and(_res_T_175, res_aligned_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_178 = and(_res_T_176, _res_T_177) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_3, io.pmp[4] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_7 = and(res_aligned_3, _res_cur_cfg_r_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_7 = and(res_aligned_3, _res_cur_cfg_w_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_7 = and(res_aligned_3, _res_cur_cfg_x_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_52 = bits(io.pmp[3].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_lsbMask_T_13 = bits(_res_hit_lsbMask_T_12, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_lsbMask_T_14 = not(_res_hit_lsbMask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node res_hit_lsbMask_4 = or(io.pmp[3].mask, _res_hit_lsbMask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 68:26] node _res_hit_msbMatch_T_40 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:29] node _res_hit_msbMatch_T_41 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbMatch_T_42 = not(_res_hit_msbMatch_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbMatch_T_43 = or(_res_hit_msbMatch_T_42, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbMatch_T_44 = not(_res_hit_msbMatch_T_43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbMatch_T_45 = shr(_res_hit_msbMatch_T_44, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:53] node _res_hit_msbMatch_T_46 = shr(io.pmp[3].mask, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:72] node _res_hit_msbMatch_T_47 = xor(_res_hit_msbMatch_T_40, _res_hit_msbMatch_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_msbMatch_T_48 = not(_res_hit_msbMatch_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_msbMatch_T_49 = and(_res_hit_msbMatch_T_47, _res_hit_msbMatch_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_msbMatch_4 = eq(_res_hit_msbMatch_T_49, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_lsbMatch_T_40 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:28] node _res_hit_lsbMatch_T_41 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbMatch_T_42 = not(_res_hit_lsbMatch_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbMatch_T_43 = or(_res_hit_lsbMatch_T_42, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbMatch_T_44 = not(_res_hit_lsbMatch_T_43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbMatch_T_45 = bits(_res_hit_lsbMatch_T_44, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:55] node _res_hit_lsbMatch_T_46 = bits(res_hit_lsbMask_4, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:80] node _res_hit_lsbMatch_T_47 = xor(_res_hit_lsbMatch_T_40, _res_hit_lsbMatch_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_lsbMatch_T_48 = not(_res_hit_lsbMatch_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_lsbMatch_T_49 = and(_res_hit_lsbMatch_T_47, _res_hit_lsbMatch_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_lsbMatch_4 = eq(_res_hit_lsbMatch_T_49, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_53 = and(res_hit_msbMatch_4, res_hit_lsbMatch_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 71:16] node _res_hit_T_54 = bits(io.pmp[3].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_55 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_56 = bits(_res_hit_T_55, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_57 = not(_res_hit_T_56) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_msbsLess_T_48 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_49 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_50 = not(_res_hit_msbsLess_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_51 = or(_res_hit_msbsLess_T_50, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_52 = not(_res_hit_msbsLess_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_53 = shr(_res_hit_msbsLess_T_52, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_8 = lt(_res_hit_msbsLess_T_48, _res_hit_msbsLess_T_53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_56 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_57 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_58 = not(_res_hit_msbsEqual_T_57) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_59 = or(_res_hit_msbsEqual_T_58, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_60 = not(_res_hit_msbsEqual_T_59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_61 = shr(_res_hit_msbsEqual_T_60, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_62 = xor(_res_hit_msbsEqual_T_56, _res_hit_msbsEqual_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_8 = eq(_res_hit_msbsEqual_T_62, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_56 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_57 = or(_res_hit_lsbsLess_T_56, _res_hit_T_57) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_58 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_59 = not(_res_hit_lsbsLess_T_58) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_60 = or(_res_hit_lsbsLess_T_59, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_61 = not(_res_hit_lsbsLess_T_60) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_62 = bits(_res_hit_lsbsLess_T_61, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_8 = lt(_res_hit_lsbsLess_T_57, _res_hit_lsbsLess_T_62) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_58 = and(res_hit_msbsEqual_8, res_hit_lsbsLess_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_59 = or(res_hit_msbsLess_8, _res_hit_T_58) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_msbsLess_T_54 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_55 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_56 = not(_res_hit_msbsLess_T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_57 = or(_res_hit_msbsLess_T_56, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_58 = not(_res_hit_msbsLess_T_57) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_59 = shr(_res_hit_msbsLess_T_58, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_9 = lt(_res_hit_msbsLess_T_54, _res_hit_msbsLess_T_59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_63 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_64 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_65 = not(_res_hit_msbsEqual_T_64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_66 = or(_res_hit_msbsEqual_T_65, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_67 = not(_res_hit_msbsEqual_T_66) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_68 = shr(_res_hit_msbsEqual_T_67, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_69 = xor(_res_hit_msbsEqual_T_63, _res_hit_msbsEqual_T_68) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_9 = eq(_res_hit_msbsEqual_T_69, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_63 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_64 = or(_res_hit_lsbsLess_T_63, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_65 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_66 = not(_res_hit_lsbsLess_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_67 = or(_res_hit_lsbsLess_T_66, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_68 = not(_res_hit_lsbsLess_T_67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_69 = bits(_res_hit_lsbsLess_T_68, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_9 = lt(_res_hit_lsbsLess_T_64, _res_hit_lsbsLess_T_69) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_61 = and(res_hit_msbsEqual_9, res_hit_lsbsLess_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_62 = or(res_hit_msbsLess_9, _res_hit_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_63 = and(_res_hit_T_60, _res_hit_T_62) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_64 = and(_res_hit_T_54, _res_hit_T_63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_4 = mux(_res_hit_T_52, _res_hit_T_53, _res_hit_T_64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_4 = and(default, _res_ignore_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_aligned_lsbMask_T_8 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_aligned_lsbMask_T_9 = bits(_res_aligned_lsbMask_T_8, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node res_aligned_lsbMask_4 = not(_res_aligned_lsbMask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_aligned_straddlesLowerBound_T_68 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:35] node _res_aligned_straddlesLowerBound_T_69 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_70 = not(_res_aligned_straddlesLowerBound_T_69) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_71 = or(_res_aligned_straddlesLowerBound_T_70, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_72 = not(_res_aligned_straddlesLowerBound_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_73 = shr(_res_aligned_straddlesLowerBound_T_72, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:67] node _res_aligned_straddlesLowerBound_T_74 = xor(_res_aligned_straddlesLowerBound_T_68, _res_aligned_straddlesLowerBound_T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:49] node _res_aligned_straddlesLowerBound_T_75 = eq(_res_aligned_straddlesLowerBound_T_74, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:82] node _res_aligned_straddlesLowerBound_T_76 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_77 = not(_res_aligned_straddlesLowerBound_T_76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_78 = or(_res_aligned_straddlesLowerBound_T_77, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_79 = not(_res_aligned_straddlesLowerBound_T_78) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_80 = bits(_res_aligned_straddlesLowerBound_T_79, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:108] node _res_aligned_straddlesLowerBound_T_81 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:129] node _res_aligned_straddlesLowerBound_T_82 = not(_res_aligned_straddlesLowerBound_T_81) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:127] node _res_aligned_straddlesLowerBound_T_83 = and(_res_aligned_straddlesLowerBound_T_80, _res_aligned_straddlesLowerBound_T_82) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:125] node _res_aligned_straddlesLowerBound_T_84 = neq(_res_aligned_straddlesLowerBound_T_83, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:147] node res_aligned_straddlesLowerBound_4 = and(_res_aligned_straddlesLowerBound_T_75, _res_aligned_straddlesLowerBound_T_84) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:90] node _res_aligned_straddlesUpperBound_T_68 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:35] node _res_aligned_straddlesUpperBound_T_69 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_70 = not(_res_aligned_straddlesUpperBound_T_69) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_71 = or(_res_aligned_straddlesUpperBound_T_70, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_72 = not(_res_aligned_straddlesUpperBound_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_73 = shr(_res_aligned_straddlesUpperBound_T_72, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:62] node _res_aligned_straddlesUpperBound_T_74 = xor(_res_aligned_straddlesUpperBound_T_68, _res_aligned_straddlesUpperBound_T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:49] node _res_aligned_straddlesUpperBound_T_75 = eq(_res_aligned_straddlesUpperBound_T_74, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:77] node _res_aligned_straddlesUpperBound_T_76 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_77 = not(_res_aligned_straddlesUpperBound_T_76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_78 = or(_res_aligned_straddlesUpperBound_T_77, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_79 = not(_res_aligned_straddlesUpperBound_T_78) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_80 = bits(_res_aligned_straddlesUpperBound_T_79, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:98] node _res_aligned_straddlesUpperBound_T_81 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:119] node _res_aligned_straddlesUpperBound_T_82 = or(_res_aligned_straddlesUpperBound_T_81, res_aligned_lsbMask_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:136] node _res_aligned_straddlesUpperBound_T_83 = and(_res_aligned_straddlesUpperBound_T_80, _res_aligned_straddlesUpperBound_T_82) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:115] node _res_aligned_straddlesUpperBound_T_84 = neq(_res_aligned_straddlesUpperBound_T_83, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:148] node res_aligned_straddlesUpperBound_4 = and(_res_aligned_straddlesUpperBound_T_75, _res_aligned_straddlesUpperBound_T_84) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:85] node _res_aligned_rangeAligned_T_4 = or(res_aligned_straddlesLowerBound_4, res_aligned_straddlesUpperBound_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:46] node res_aligned_rangeAligned_4 = eq(_res_aligned_rangeAligned_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:24] node _res_aligned_pow2Aligned_T_12 = bits(io.pmp[3].mask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:39] node _res_aligned_pow2Aligned_T_13 = not(_res_aligned_pow2Aligned_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:34] node _res_aligned_pow2Aligned_T_14 = and(res_aligned_lsbMask_4, _res_aligned_pow2Aligned_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:32] node res_aligned_pow2Aligned_4 = eq(_res_aligned_pow2Aligned_T_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:57] node _res_aligned_T_4 = bits(io.pmp[3].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node res_aligned_4 = mux(_res_aligned_T_4, res_aligned_pow2Aligned_4, res_aligned_rangeAligned_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 127:8] node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_186 = eq(_res_T_185, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_188 = eq(_res_T_187, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_190 = eq(_res_T_189, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_192 = eq(_res_T_191, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_194 = eq(_res_T_193, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_196 = eq(_res_T_195, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_198 = and(_res_T_197, res_hit_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_199 = and(_res_T_198, res_aligned_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_201 = and(_res_T_199, _res_T_200) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_203 = and(_res_T_202, res_aligned_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_205 = and(_res_T_203, _res_T_204) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_207 = and(_res_T_206, res_hit_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_208 = and(_res_T_207, res_aligned_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_210 = and(_res_T_208, _res_T_209) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_212 = and(_res_T_211, res_aligned_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_214 = and(_res_T_212, _res_T_213) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_216 = and(_res_T_215, res_hit_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_217 = and(_res_T_216, res_aligned_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_219 = and(_res_T_217, _res_T_218) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_221 = and(_res_T_220, res_aligned_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_223 = and(_res_T_221, _res_T_222) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_4, io.pmp[3] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_9 = and(res_aligned_4, _res_cur_cfg_r_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_9 = and(res_aligned_4, _res_cur_cfg_w_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_9 = and(res_aligned_4, _res_cur_cfg_x_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_65 = bits(io.pmp[2].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_lsbMask_T_15 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_lsbMask_T_16 = bits(_res_hit_lsbMask_T_15, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_lsbMask_T_17 = not(_res_hit_lsbMask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node res_hit_lsbMask_5 = or(io.pmp[2].mask, _res_hit_lsbMask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 68:26] node _res_hit_msbMatch_T_50 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:29] node _res_hit_msbMatch_T_51 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbMatch_T_52 = not(_res_hit_msbMatch_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbMatch_T_53 = or(_res_hit_msbMatch_T_52, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbMatch_T_54 = not(_res_hit_msbMatch_T_53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbMatch_T_55 = shr(_res_hit_msbMatch_T_54, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:53] node _res_hit_msbMatch_T_56 = shr(io.pmp[2].mask, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:72] node _res_hit_msbMatch_T_57 = xor(_res_hit_msbMatch_T_50, _res_hit_msbMatch_T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_msbMatch_T_58 = not(_res_hit_msbMatch_T_56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_msbMatch_T_59 = and(_res_hit_msbMatch_T_57, _res_hit_msbMatch_T_58) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_msbMatch_5 = eq(_res_hit_msbMatch_T_59, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_lsbMatch_T_50 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:28] node _res_hit_lsbMatch_T_51 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbMatch_T_52 = not(_res_hit_lsbMatch_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbMatch_T_53 = or(_res_hit_lsbMatch_T_52, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbMatch_T_54 = not(_res_hit_lsbMatch_T_53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbMatch_T_55 = bits(_res_hit_lsbMatch_T_54, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:55] node _res_hit_lsbMatch_T_56 = bits(res_hit_lsbMask_5, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:80] node _res_hit_lsbMatch_T_57 = xor(_res_hit_lsbMatch_T_50, _res_hit_lsbMatch_T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_lsbMatch_T_58 = not(_res_hit_lsbMatch_T_56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_lsbMatch_T_59 = and(_res_hit_lsbMatch_T_57, _res_hit_lsbMatch_T_58) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_lsbMatch_5 = eq(_res_hit_lsbMatch_T_59, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_66 = and(res_hit_msbMatch_5, res_hit_lsbMatch_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 71:16] node _res_hit_T_67 = bits(io.pmp[2].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_68 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_69 = bits(_res_hit_T_68, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_70 = not(_res_hit_T_69) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_msbsLess_T_60 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_61 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_62 = not(_res_hit_msbsLess_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_63 = or(_res_hit_msbsLess_T_62, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_64 = not(_res_hit_msbsLess_T_63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_65 = shr(_res_hit_msbsLess_T_64, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_10 = lt(_res_hit_msbsLess_T_60, _res_hit_msbsLess_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_70 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_71 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_72 = not(_res_hit_msbsEqual_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_73 = or(_res_hit_msbsEqual_T_72, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_74 = not(_res_hit_msbsEqual_T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_75 = shr(_res_hit_msbsEqual_T_74, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_76 = xor(_res_hit_msbsEqual_T_70, _res_hit_msbsEqual_T_75) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_10 = eq(_res_hit_msbsEqual_T_76, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_70 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_71 = or(_res_hit_lsbsLess_T_70, _res_hit_T_70) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_72 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_73 = not(_res_hit_lsbsLess_T_72) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_74 = or(_res_hit_lsbsLess_T_73, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_75 = not(_res_hit_lsbsLess_T_74) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_76 = bits(_res_hit_lsbsLess_T_75, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_10 = lt(_res_hit_lsbsLess_T_71, _res_hit_lsbsLess_T_76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_71 = and(res_hit_msbsEqual_10, res_hit_lsbsLess_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_72 = or(res_hit_msbsLess_10, _res_hit_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_73 = eq(_res_hit_T_72, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_msbsLess_T_66 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_67 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_68 = not(_res_hit_msbsLess_T_67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_69 = or(_res_hit_msbsLess_T_68, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_70 = not(_res_hit_msbsLess_T_69) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_71 = shr(_res_hit_msbsLess_T_70, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_11 = lt(_res_hit_msbsLess_T_66, _res_hit_msbsLess_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_77 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_78 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_79 = not(_res_hit_msbsEqual_T_78) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_80 = or(_res_hit_msbsEqual_T_79, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_81 = not(_res_hit_msbsEqual_T_80) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_82 = shr(_res_hit_msbsEqual_T_81, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_83 = xor(_res_hit_msbsEqual_T_77, _res_hit_msbsEqual_T_82) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_11 = eq(_res_hit_msbsEqual_T_83, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_77 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_78 = or(_res_hit_lsbsLess_T_77, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_79 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_80 = not(_res_hit_lsbsLess_T_79) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_81 = or(_res_hit_lsbsLess_T_80, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_82 = not(_res_hit_lsbsLess_T_81) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_83 = bits(_res_hit_lsbsLess_T_82, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_11 = lt(_res_hit_lsbsLess_T_78, _res_hit_lsbsLess_T_83) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_74 = and(res_hit_msbsEqual_11, res_hit_lsbsLess_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_75 = or(res_hit_msbsLess_11, _res_hit_T_74) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_76 = and(_res_hit_T_73, _res_hit_T_75) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_77 = and(_res_hit_T_67, _res_hit_T_76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_5 = mux(_res_hit_T_65, _res_hit_T_66, _res_hit_T_77) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_5 = and(default, _res_ignore_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_aligned_lsbMask_T_10 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_aligned_lsbMask_T_11 = bits(_res_aligned_lsbMask_T_10, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node res_aligned_lsbMask_5 = not(_res_aligned_lsbMask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_aligned_straddlesLowerBound_T_85 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:35] node _res_aligned_straddlesLowerBound_T_86 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_87 = not(_res_aligned_straddlesLowerBound_T_86) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_88 = or(_res_aligned_straddlesLowerBound_T_87, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_89 = not(_res_aligned_straddlesLowerBound_T_88) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_90 = shr(_res_aligned_straddlesLowerBound_T_89, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:67] node _res_aligned_straddlesLowerBound_T_91 = xor(_res_aligned_straddlesLowerBound_T_85, _res_aligned_straddlesLowerBound_T_90) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:49] node _res_aligned_straddlesLowerBound_T_92 = eq(_res_aligned_straddlesLowerBound_T_91, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:82] node _res_aligned_straddlesLowerBound_T_93 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_94 = not(_res_aligned_straddlesLowerBound_T_93) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_95 = or(_res_aligned_straddlesLowerBound_T_94, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_96 = not(_res_aligned_straddlesLowerBound_T_95) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_97 = bits(_res_aligned_straddlesLowerBound_T_96, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:108] node _res_aligned_straddlesLowerBound_T_98 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:129] node _res_aligned_straddlesLowerBound_T_99 = not(_res_aligned_straddlesLowerBound_T_98) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:127] node _res_aligned_straddlesLowerBound_T_100 = and(_res_aligned_straddlesLowerBound_T_97, _res_aligned_straddlesLowerBound_T_99) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:125] node _res_aligned_straddlesLowerBound_T_101 = neq(_res_aligned_straddlesLowerBound_T_100, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:147] node res_aligned_straddlesLowerBound_5 = and(_res_aligned_straddlesLowerBound_T_92, _res_aligned_straddlesLowerBound_T_101) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:90] node _res_aligned_straddlesUpperBound_T_85 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:35] node _res_aligned_straddlesUpperBound_T_86 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_87 = not(_res_aligned_straddlesUpperBound_T_86) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_88 = or(_res_aligned_straddlesUpperBound_T_87, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_89 = not(_res_aligned_straddlesUpperBound_T_88) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_90 = shr(_res_aligned_straddlesUpperBound_T_89, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:62] node _res_aligned_straddlesUpperBound_T_91 = xor(_res_aligned_straddlesUpperBound_T_85, _res_aligned_straddlesUpperBound_T_90) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:49] node _res_aligned_straddlesUpperBound_T_92 = eq(_res_aligned_straddlesUpperBound_T_91, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:77] node _res_aligned_straddlesUpperBound_T_93 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_94 = not(_res_aligned_straddlesUpperBound_T_93) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_95 = or(_res_aligned_straddlesUpperBound_T_94, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_96 = not(_res_aligned_straddlesUpperBound_T_95) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_97 = bits(_res_aligned_straddlesUpperBound_T_96, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:98] node _res_aligned_straddlesUpperBound_T_98 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:119] node _res_aligned_straddlesUpperBound_T_99 = or(_res_aligned_straddlesUpperBound_T_98, res_aligned_lsbMask_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:136] node _res_aligned_straddlesUpperBound_T_100 = and(_res_aligned_straddlesUpperBound_T_97, _res_aligned_straddlesUpperBound_T_99) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:115] node _res_aligned_straddlesUpperBound_T_101 = neq(_res_aligned_straddlesUpperBound_T_100, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:148] node res_aligned_straddlesUpperBound_5 = and(_res_aligned_straddlesUpperBound_T_92, _res_aligned_straddlesUpperBound_T_101) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:85] node _res_aligned_rangeAligned_T_5 = or(res_aligned_straddlesLowerBound_5, res_aligned_straddlesUpperBound_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:46] node res_aligned_rangeAligned_5 = eq(_res_aligned_rangeAligned_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:24] node _res_aligned_pow2Aligned_T_15 = bits(io.pmp[2].mask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:39] node _res_aligned_pow2Aligned_T_16 = not(_res_aligned_pow2Aligned_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:34] node _res_aligned_pow2Aligned_T_17 = and(res_aligned_lsbMask_5, _res_aligned_pow2Aligned_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:32] node res_aligned_pow2Aligned_5 = eq(_res_aligned_pow2Aligned_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:57] node _res_aligned_T_5 = bits(io.pmp[2].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node res_aligned_5 = mux(_res_aligned_T_5, res_aligned_pow2Aligned_5, res_aligned_rangeAligned_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 127:8] node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_231 = eq(_res_T_230, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_233 = eq(_res_T_232, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_235 = eq(_res_T_234, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_237 = eq(_res_T_236, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_239 = eq(_res_T_238, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_241 = eq(_res_T_240, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_243 = and(_res_T_242, res_hit_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_244 = and(_res_T_243, res_aligned_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_246 = and(_res_T_244, _res_T_245) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_248 = and(_res_T_247, res_aligned_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_250 = and(_res_T_248, _res_T_249) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_252 = and(_res_T_251, res_hit_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_253 = and(_res_T_252, res_aligned_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_255 = and(_res_T_253, _res_T_254) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_257 = and(_res_T_256, res_aligned_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_259 = and(_res_T_257, _res_T_258) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_261 = and(_res_T_260, res_hit_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_262 = and(_res_T_261, res_aligned_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_264 = and(_res_T_262, _res_T_263) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_266 = and(_res_T_265, res_aligned_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_268 = and(_res_T_266, _res_T_267) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_5, io.pmp[2] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_11 = and(res_aligned_5, _res_cur_cfg_r_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_11 = and(res_aligned_5, _res_cur_cfg_w_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_11 = and(res_aligned_5, _res_cur_cfg_x_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_78 = bits(io.pmp[1].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_lsbMask_T_18 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_lsbMask_T_19 = bits(_res_hit_lsbMask_T_18, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_lsbMask_T_20 = not(_res_hit_lsbMask_T_19) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node res_hit_lsbMask_6 = or(io.pmp[1].mask, _res_hit_lsbMask_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 68:26] node _res_hit_msbMatch_T_60 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:29] node _res_hit_msbMatch_T_61 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbMatch_T_62 = not(_res_hit_msbMatch_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbMatch_T_63 = or(_res_hit_msbMatch_T_62, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbMatch_T_64 = not(_res_hit_msbMatch_T_63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbMatch_T_65 = shr(_res_hit_msbMatch_T_64, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:53] node _res_hit_msbMatch_T_66 = shr(io.pmp[1].mask, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:72] node _res_hit_msbMatch_T_67 = xor(_res_hit_msbMatch_T_60, _res_hit_msbMatch_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_msbMatch_T_68 = not(_res_hit_msbMatch_T_66) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_msbMatch_T_69 = and(_res_hit_msbMatch_T_67, _res_hit_msbMatch_T_68) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_msbMatch_6 = eq(_res_hit_msbMatch_T_69, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_lsbMatch_T_60 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:28] node _res_hit_lsbMatch_T_61 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbMatch_T_62 = not(_res_hit_lsbMatch_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbMatch_T_63 = or(_res_hit_lsbMatch_T_62, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbMatch_T_64 = not(_res_hit_lsbMatch_T_63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbMatch_T_65 = bits(_res_hit_lsbMatch_T_64, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:55] node _res_hit_lsbMatch_T_66 = bits(res_hit_lsbMask_6, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:80] node _res_hit_lsbMatch_T_67 = xor(_res_hit_lsbMatch_T_60, _res_hit_lsbMatch_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_lsbMatch_T_68 = not(_res_hit_lsbMatch_T_66) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_lsbMatch_T_69 = and(_res_hit_lsbMatch_T_67, _res_hit_lsbMatch_T_68) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_lsbMatch_6 = eq(_res_hit_lsbMatch_T_69, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_79 = and(res_hit_msbMatch_6, res_hit_lsbMatch_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 71:16] node _res_hit_T_80 = bits(io.pmp[1].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_81 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_82 = bits(_res_hit_T_81, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_83 = not(_res_hit_T_82) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_msbsLess_T_72 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_73 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_74 = not(_res_hit_msbsLess_T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_75 = or(_res_hit_msbsLess_T_74, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_76 = not(_res_hit_msbsLess_T_75) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_77 = shr(_res_hit_msbsLess_T_76, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_12 = lt(_res_hit_msbsLess_T_72, _res_hit_msbsLess_T_77) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_84 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_85 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_86 = not(_res_hit_msbsEqual_T_85) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_87 = or(_res_hit_msbsEqual_T_86, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_88 = not(_res_hit_msbsEqual_T_87) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_89 = shr(_res_hit_msbsEqual_T_88, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_90 = xor(_res_hit_msbsEqual_T_84, _res_hit_msbsEqual_T_89) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_12 = eq(_res_hit_msbsEqual_T_90, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_84 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_85 = or(_res_hit_lsbsLess_T_84, _res_hit_T_83) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_86 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_87 = not(_res_hit_lsbsLess_T_86) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_88 = or(_res_hit_lsbsLess_T_87, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_89 = not(_res_hit_lsbsLess_T_88) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_90 = bits(_res_hit_lsbsLess_T_89, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_12 = lt(_res_hit_lsbsLess_T_85, _res_hit_lsbsLess_T_90) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_84 = and(res_hit_msbsEqual_12, res_hit_lsbsLess_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_85 = or(res_hit_msbsLess_12, _res_hit_T_84) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_msbsLess_T_78 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_79 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_80 = not(_res_hit_msbsLess_T_79) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_81 = or(_res_hit_msbsLess_T_80, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_82 = not(_res_hit_msbsLess_T_81) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_83 = shr(_res_hit_msbsLess_T_82, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_13 = lt(_res_hit_msbsLess_T_78, _res_hit_msbsLess_T_83) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_91 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_92 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_93 = not(_res_hit_msbsEqual_T_92) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_94 = or(_res_hit_msbsEqual_T_93, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_95 = not(_res_hit_msbsEqual_T_94) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_96 = shr(_res_hit_msbsEqual_T_95, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_97 = xor(_res_hit_msbsEqual_T_91, _res_hit_msbsEqual_T_96) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_13 = eq(_res_hit_msbsEqual_T_97, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_91 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_92 = or(_res_hit_lsbsLess_T_91, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_93 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_94 = not(_res_hit_lsbsLess_T_93) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_95 = or(_res_hit_lsbsLess_T_94, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_96 = not(_res_hit_lsbsLess_T_95) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_97 = bits(_res_hit_lsbsLess_T_96, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_13 = lt(_res_hit_lsbsLess_T_92, _res_hit_lsbsLess_T_97) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_87 = and(res_hit_msbsEqual_13, res_hit_lsbsLess_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_88 = or(res_hit_msbsLess_13, _res_hit_T_87) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_89 = and(_res_hit_T_86, _res_hit_T_88) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_90 = and(_res_hit_T_80, _res_hit_T_89) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_6 = mux(_res_hit_T_78, _res_hit_T_79, _res_hit_T_90) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_6 = and(default, _res_ignore_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_aligned_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_aligned_lsbMask_T_13 = bits(_res_aligned_lsbMask_T_12, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node res_aligned_lsbMask_6 = not(_res_aligned_lsbMask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_aligned_straddlesLowerBound_T_102 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:35] node _res_aligned_straddlesLowerBound_T_103 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_104 = not(_res_aligned_straddlesLowerBound_T_103) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_105 = or(_res_aligned_straddlesLowerBound_T_104, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_106 = not(_res_aligned_straddlesLowerBound_T_105) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_107 = shr(_res_aligned_straddlesLowerBound_T_106, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:67] node _res_aligned_straddlesLowerBound_T_108 = xor(_res_aligned_straddlesLowerBound_T_102, _res_aligned_straddlesLowerBound_T_107) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:49] node _res_aligned_straddlesLowerBound_T_109 = eq(_res_aligned_straddlesLowerBound_T_108, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:82] node _res_aligned_straddlesLowerBound_T_110 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_111 = not(_res_aligned_straddlesLowerBound_T_110) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_112 = or(_res_aligned_straddlesLowerBound_T_111, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_113 = not(_res_aligned_straddlesLowerBound_T_112) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_114 = bits(_res_aligned_straddlesLowerBound_T_113, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:108] node _res_aligned_straddlesLowerBound_T_115 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:129] node _res_aligned_straddlesLowerBound_T_116 = not(_res_aligned_straddlesLowerBound_T_115) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:127] node _res_aligned_straddlesLowerBound_T_117 = and(_res_aligned_straddlesLowerBound_T_114, _res_aligned_straddlesLowerBound_T_116) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:125] node _res_aligned_straddlesLowerBound_T_118 = neq(_res_aligned_straddlesLowerBound_T_117, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:147] node res_aligned_straddlesLowerBound_6 = and(_res_aligned_straddlesLowerBound_T_109, _res_aligned_straddlesLowerBound_T_118) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:90] node _res_aligned_straddlesUpperBound_T_102 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:35] node _res_aligned_straddlesUpperBound_T_103 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_104 = not(_res_aligned_straddlesUpperBound_T_103) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_105 = or(_res_aligned_straddlesUpperBound_T_104, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_106 = not(_res_aligned_straddlesUpperBound_T_105) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_107 = shr(_res_aligned_straddlesUpperBound_T_106, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:62] node _res_aligned_straddlesUpperBound_T_108 = xor(_res_aligned_straddlesUpperBound_T_102, _res_aligned_straddlesUpperBound_T_107) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:49] node _res_aligned_straddlesUpperBound_T_109 = eq(_res_aligned_straddlesUpperBound_T_108, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:77] node _res_aligned_straddlesUpperBound_T_110 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_111 = not(_res_aligned_straddlesUpperBound_T_110) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_112 = or(_res_aligned_straddlesUpperBound_T_111, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_113 = not(_res_aligned_straddlesUpperBound_T_112) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_114 = bits(_res_aligned_straddlesUpperBound_T_113, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:98] node _res_aligned_straddlesUpperBound_T_115 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:119] node _res_aligned_straddlesUpperBound_T_116 = or(_res_aligned_straddlesUpperBound_T_115, res_aligned_lsbMask_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:136] node _res_aligned_straddlesUpperBound_T_117 = and(_res_aligned_straddlesUpperBound_T_114, _res_aligned_straddlesUpperBound_T_116) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:115] node _res_aligned_straddlesUpperBound_T_118 = neq(_res_aligned_straddlesUpperBound_T_117, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:148] node res_aligned_straddlesUpperBound_6 = and(_res_aligned_straddlesUpperBound_T_109, _res_aligned_straddlesUpperBound_T_118) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:85] node _res_aligned_rangeAligned_T_6 = or(res_aligned_straddlesLowerBound_6, res_aligned_straddlesUpperBound_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:46] node res_aligned_rangeAligned_6 = eq(_res_aligned_rangeAligned_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:24] node _res_aligned_pow2Aligned_T_18 = bits(io.pmp[1].mask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:39] node _res_aligned_pow2Aligned_T_19 = not(_res_aligned_pow2Aligned_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:34] node _res_aligned_pow2Aligned_T_20 = and(res_aligned_lsbMask_6, _res_aligned_pow2Aligned_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:32] node res_aligned_pow2Aligned_6 = eq(_res_aligned_pow2Aligned_T_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:57] node _res_aligned_T_6 = bits(io.pmp[1].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node res_aligned_6 = mux(_res_aligned_T_6, res_aligned_pow2Aligned_6, res_aligned_rangeAligned_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 127:8] node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_276 = eq(_res_T_275, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_278 = eq(_res_T_277, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_280 = eq(_res_T_279, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_282 = eq(_res_T_281, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_284 = eq(_res_T_283, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_286 = eq(_res_T_285, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_288 = and(_res_T_287, res_hit_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_289 = and(_res_T_288, res_aligned_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_291 = and(_res_T_289, _res_T_290) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_293 = and(_res_T_292, res_aligned_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_295 = and(_res_T_293, _res_T_294) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_297 = and(_res_T_296, res_hit_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_298 = and(_res_T_297, res_aligned_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_300 = and(_res_T_298, _res_T_299) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_302 = and(_res_T_301, res_aligned_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_304 = and(_res_T_302, _res_T_303) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_306 = and(_res_T_305, res_hit_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_307 = and(_res_T_306, res_aligned_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_309 = and(_res_T_307, _res_T_308) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_311 = and(_res_T_310, res_aligned_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_313 = and(_res_T_311, _res_T_312) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_6, io.pmp[1] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_13 = and(res_aligned_6, _res_cur_cfg_r_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_13 = and(res_aligned_6, _res_cur_cfg_w_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_13 = and(res_aligned_6, _res_cur_cfg_x_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_91 = bits(io.pmp[0].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_lsbMask_T_21 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_lsbMask_T_22 = bits(_res_hit_lsbMask_T_21, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_lsbMask_T_23 = not(_res_hit_lsbMask_T_22) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node res_hit_lsbMask_7 = or(io.pmp[0].mask, _res_hit_lsbMask_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 68:26] node _res_hit_msbMatch_T_70 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:29] node _res_hit_msbMatch_T_71 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbMatch_T_72 = not(_res_hit_msbMatch_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbMatch_T_73 = or(_res_hit_msbMatch_T_72, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbMatch_T_74 = not(_res_hit_msbMatch_T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbMatch_T_75 = shr(_res_hit_msbMatch_T_74, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:53] node _res_hit_msbMatch_T_76 = shr(io.pmp[0].mask, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:72] node _res_hit_msbMatch_T_77 = xor(_res_hit_msbMatch_T_70, _res_hit_msbMatch_T_75) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_msbMatch_T_78 = not(_res_hit_msbMatch_T_76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_msbMatch_T_79 = and(_res_hit_msbMatch_T_77, _res_hit_msbMatch_T_78) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_msbMatch_7 = eq(_res_hit_msbMatch_T_79, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_lsbMatch_T_70 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:28] node _res_hit_lsbMatch_T_71 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbMatch_T_72 = not(_res_hit_lsbMatch_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbMatch_T_73 = or(_res_hit_lsbMatch_T_72, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbMatch_T_74 = not(_res_hit_lsbMatch_T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbMatch_T_75 = bits(_res_hit_lsbMatch_T_74, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:55] node _res_hit_lsbMatch_T_76 = bits(res_hit_lsbMask_7, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:80] node _res_hit_lsbMatch_T_77 = xor(_res_hit_lsbMatch_T_70, _res_hit_lsbMatch_T_75) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_lsbMatch_T_78 = not(_res_hit_lsbMatch_T_76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_lsbMatch_T_79 = and(_res_hit_lsbMatch_T_77, _res_hit_lsbMatch_T_78) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_lsbMatch_7 = eq(_res_hit_lsbMatch_T_79, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_92 = and(res_hit_msbMatch_7, res_hit_lsbMatch_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 71:16] node _res_hit_T_93 = bits(io.pmp[0].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_94 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_95 = bits(_res_hit_T_94, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_96 = not(_res_hit_T_95) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_msbsLess_T_84 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_85 = shl(pmp0.addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_86 = not(_res_hit_msbsLess_T_85) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_87 = or(_res_hit_msbsLess_T_86, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_88 = not(_res_hit_msbsLess_T_87) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_89 = shr(_res_hit_msbsLess_T_88, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_14 = lt(_res_hit_msbsLess_T_84, _res_hit_msbsLess_T_89) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_98 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_99 = shl(pmp0.addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_100 = not(_res_hit_msbsEqual_T_99) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_101 = or(_res_hit_msbsEqual_T_100, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_102 = not(_res_hit_msbsEqual_T_101) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_103 = shr(_res_hit_msbsEqual_T_102, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_104 = xor(_res_hit_msbsEqual_T_98, _res_hit_msbsEqual_T_103) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_14 = eq(_res_hit_msbsEqual_T_104, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_98 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_99 = or(_res_hit_lsbsLess_T_98, _res_hit_T_96) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_100 = shl(pmp0.addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_101 = not(_res_hit_lsbsLess_T_100) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_102 = or(_res_hit_lsbsLess_T_101, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_103 = not(_res_hit_lsbsLess_T_102) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_104 = bits(_res_hit_lsbsLess_T_103, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_14 = lt(_res_hit_lsbsLess_T_99, _res_hit_lsbsLess_T_104) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_97 = and(res_hit_msbsEqual_14, res_hit_lsbsLess_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_98 = or(res_hit_msbsLess_14, _res_hit_T_97) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_99 = eq(_res_hit_T_98, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_msbsLess_T_90 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_91 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_92 = not(_res_hit_msbsLess_T_91) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_93 = or(_res_hit_msbsLess_T_92, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_94 = not(_res_hit_msbsLess_T_93) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_95 = shr(_res_hit_msbsLess_T_94, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_15 = lt(_res_hit_msbsLess_T_90, _res_hit_msbsLess_T_95) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_105 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_106 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_107 = not(_res_hit_msbsEqual_T_106) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_108 = or(_res_hit_msbsEqual_T_107, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_109 = not(_res_hit_msbsEqual_T_108) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_110 = shr(_res_hit_msbsEqual_T_109, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_111 = xor(_res_hit_msbsEqual_T_105, _res_hit_msbsEqual_T_110) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_15 = eq(_res_hit_msbsEqual_T_111, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_105 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_106 = or(_res_hit_lsbsLess_T_105, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_107 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_108 = not(_res_hit_lsbsLess_T_107) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_109 = or(_res_hit_lsbsLess_T_108, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_110 = not(_res_hit_lsbsLess_T_109) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_111 = bits(_res_hit_lsbsLess_T_110, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_15 = lt(_res_hit_lsbsLess_T_106, _res_hit_lsbsLess_T_111) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_100 = and(res_hit_msbsEqual_15, res_hit_lsbsLess_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_101 = or(res_hit_msbsLess_15, _res_hit_T_100) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_102 = and(_res_hit_T_99, _res_hit_T_101) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_103 = and(_res_hit_T_93, _res_hit_T_102) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_7 = mux(_res_hit_T_91, _res_hit_T_92, _res_hit_T_103) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_7 = and(default, _res_ignore_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_aligned_lsbMask_T_14 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_aligned_lsbMask_T_15 = bits(_res_aligned_lsbMask_T_14, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node res_aligned_lsbMask_7 = not(_res_aligned_lsbMask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_aligned_straddlesLowerBound_T_119 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:35] node _res_aligned_straddlesLowerBound_T_120 = shl(pmp0.addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_121 = not(_res_aligned_straddlesLowerBound_T_120) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_122 = or(_res_aligned_straddlesLowerBound_T_121, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_123 = not(_res_aligned_straddlesLowerBound_T_122) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_124 = shr(_res_aligned_straddlesLowerBound_T_123, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:67] node _res_aligned_straddlesLowerBound_T_125 = xor(_res_aligned_straddlesLowerBound_T_119, _res_aligned_straddlesLowerBound_T_124) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:49] node _res_aligned_straddlesLowerBound_T_126 = eq(_res_aligned_straddlesLowerBound_T_125, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:82] node _res_aligned_straddlesLowerBound_T_127 = shl(pmp0.addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_128 = not(_res_aligned_straddlesLowerBound_T_127) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_129 = or(_res_aligned_straddlesLowerBound_T_128, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_130 = not(_res_aligned_straddlesLowerBound_T_129) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_131 = bits(_res_aligned_straddlesLowerBound_T_130, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:108] node _res_aligned_straddlesLowerBound_T_132 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:129] node _res_aligned_straddlesLowerBound_T_133 = not(_res_aligned_straddlesLowerBound_T_132) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:127] node _res_aligned_straddlesLowerBound_T_134 = and(_res_aligned_straddlesLowerBound_T_131, _res_aligned_straddlesLowerBound_T_133) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:125] node _res_aligned_straddlesLowerBound_T_135 = neq(_res_aligned_straddlesLowerBound_T_134, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:147] node res_aligned_straddlesLowerBound_7 = and(_res_aligned_straddlesLowerBound_T_126, _res_aligned_straddlesLowerBound_T_135) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:90] node _res_aligned_straddlesUpperBound_T_119 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:35] node _res_aligned_straddlesUpperBound_T_120 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_121 = not(_res_aligned_straddlesUpperBound_T_120) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_122 = or(_res_aligned_straddlesUpperBound_T_121, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_123 = not(_res_aligned_straddlesUpperBound_T_122) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_124 = shr(_res_aligned_straddlesUpperBound_T_123, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:62] node _res_aligned_straddlesUpperBound_T_125 = xor(_res_aligned_straddlesUpperBound_T_119, _res_aligned_straddlesUpperBound_T_124) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:49] node _res_aligned_straddlesUpperBound_T_126 = eq(_res_aligned_straddlesUpperBound_T_125, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:77] node _res_aligned_straddlesUpperBound_T_127 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_128 = not(_res_aligned_straddlesUpperBound_T_127) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_129 = or(_res_aligned_straddlesUpperBound_T_128, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_130 = not(_res_aligned_straddlesUpperBound_T_129) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_131 = bits(_res_aligned_straddlesUpperBound_T_130, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:98] node _res_aligned_straddlesUpperBound_T_132 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:119] node _res_aligned_straddlesUpperBound_T_133 = or(_res_aligned_straddlesUpperBound_T_132, res_aligned_lsbMask_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:136] node _res_aligned_straddlesUpperBound_T_134 = and(_res_aligned_straddlesUpperBound_T_131, _res_aligned_straddlesUpperBound_T_133) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:115] node _res_aligned_straddlesUpperBound_T_135 = neq(_res_aligned_straddlesUpperBound_T_134, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:148] node res_aligned_straddlesUpperBound_7 = and(_res_aligned_straddlesUpperBound_T_126, _res_aligned_straddlesUpperBound_T_135) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:85] node _res_aligned_rangeAligned_T_7 = or(res_aligned_straddlesLowerBound_7, res_aligned_straddlesUpperBound_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:46] node res_aligned_rangeAligned_7 = eq(_res_aligned_rangeAligned_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:24] node _res_aligned_pow2Aligned_T_21 = bits(io.pmp[0].mask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:39] node _res_aligned_pow2Aligned_T_22 = not(_res_aligned_pow2Aligned_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:34] node _res_aligned_pow2Aligned_T_23 = and(res_aligned_lsbMask_7, _res_aligned_pow2Aligned_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:32] node res_aligned_pow2Aligned_7 = eq(_res_aligned_pow2Aligned_T_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:57] node _res_aligned_T_7 = bits(io.pmp[0].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node res_aligned_7 = mux(_res_aligned_T_7, res_aligned_pow2Aligned_7, res_aligned_rangeAligned_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 127:8] node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_321 = eq(_res_T_320, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_323 = eq(_res_T_322, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_325 = eq(_res_T_324, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_327 = eq(_res_T_326, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_329 = eq(_res_T_328, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_331 = eq(_res_T_330, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_333 = and(_res_T_332, res_hit_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_334 = and(_res_T_333, res_aligned_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_336 = and(_res_T_334, _res_T_335) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_338 = and(_res_T_337, res_aligned_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_340 = and(_res_T_338, _res_T_339) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_342 = and(_res_T_341, res_hit_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_343 = and(_res_T_342, res_aligned_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_345 = and(_res_T_343, _res_T_344) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_347 = and(_res_T_346, res_aligned_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_349 = and(_res_T_347, _res_T_348) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_351 = and(_res_T_350, res_hit_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_352 = and(_res_T_351, res_aligned_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_354 = and(_res_T_352, _res_T_353) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_356 = and(_res_T_355, res_aligned_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_358 = and(_res_T_356, _res_T_357) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_7, io.pmp[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_15 = and(res_aligned_7, _res_cur_cfg_r_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_15 = and(res_aligned_7, _res_cur_cfg_w_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_15 = and(res_aligned_7, _res_cur_cfg_x_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node res = mux(res_hit_7, res_cur_7, _res_T_314) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] connect io.r, res.cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 188:8] connect io.w, res.cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 189:8] connect io.x, res.cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 190:8] module PMAChecker : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 18:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 18:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 18:7] output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 19:14] node _legal_address_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_1 = cvt(_legal_address_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_3 = asSInt(_legal_address_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_5 = xor(io.paddr, UInt<14>(0h3000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_6 = cvt(_legal_address_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_8 = asSInt(_legal_address_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_10 = xor(io.paddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_11 = cvt(_legal_address_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<17>(0h10000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_13 = asSInt(_legal_address_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_15 = xor(io.paddr, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_16 = cvt(_legal_address_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_18 = asSInt(_legal_address_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_20 = xor(io.paddr, UInt<28>(0hc000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_21 = cvt(_legal_address_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<27>(0h4000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_23 = asSInt(_legal_address_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_25 = xor(io.paddr, UInt<29>(0h10013000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_26 = cvt(_legal_address_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_28 = asSInt(_legal_address_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_30 = xor(io.paddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_31 = cvt(_legal_address_T_30) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_33 = asSInt(_legal_address_T_32) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_35 = xor(io.paddr, UInt<29>(0h10015000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_36 = cvt(_legal_address_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_38 = asSInt(_legal_address_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_40 = xor(io.paddr, UInt<29>(0h10020000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_41 = cvt(_legal_address_T_40) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_43 = asSInt(_legal_address_T_42) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_45 = xor(io.paddr, UInt<29>(0h10021000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_46 = cvt(_legal_address_T_45) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_48 = asSInt(_legal_address_T_47) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_50 = xor(io.paddr, UInt<29>(0h10022000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_51 = cvt(_legal_address_T_50) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_53 = asSInt(_legal_address_T_52) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_55 = xor(io.paddr, UInt<29>(0h10023000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_56 = cvt(_legal_address_T_55) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_58 = asSInt(_legal_address_T_57) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_60 = xor(io.paddr, UInt<29>(0h10024000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_61 = cvt(_legal_address_T_60) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_62 = and(_legal_address_T_61, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_63 = asSInt(_legal_address_T_62) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_64 = eq(_legal_address_T_63, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_65 = xor(io.paddr, UInt<29>(0h10025000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_66 = cvt(_legal_address_T_65) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_67 = and(_legal_address_T_66, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_68 = asSInt(_legal_address_T_67) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_69 = eq(_legal_address_T_68, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_70 = xor(io.paddr, UInt<29>(0h10026000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_71 = cvt(_legal_address_T_70) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_72 = and(_legal_address_T_71, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_73 = asSInt(_legal_address_T_72) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_74 = eq(_legal_address_T_73, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_75 = xor(io.paddr, UInt<29>(0h10027000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_76 = cvt(_legal_address_T_75) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_77 = and(_legal_address_T_76, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_78 = asSInt(_legal_address_T_77) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_79 = eq(_legal_address_T_78, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_80 = xor(io.paddr, UInt<29>(0h10028000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_81 = cvt(_legal_address_T_80) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_82 = and(_legal_address_T_81, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_83 = asSInt(_legal_address_T_82) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_84 = eq(_legal_address_T_83, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_85 = xor(io.paddr, UInt<29>(0h10029000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_86 = cvt(_legal_address_T_85) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_87 = and(_legal_address_T_86, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_88 = asSInt(_legal_address_T_87) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_89 = eq(_legal_address_T_88, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_90 = xor(io.paddr, UInt<29>(0h1002a000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_91 = cvt(_legal_address_T_90) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_92 = and(_legal_address_T_91, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_93 = asSInt(_legal_address_T_92) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_94 = eq(_legal_address_T_93, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_95 = xor(io.paddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_96 = cvt(_legal_address_T_95) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_97 = and(_legal_address_T_96, asSInt(UInt<21>(0h100000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_98 = asSInt(_legal_address_T_97) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_99 = eq(_legal_address_T_98, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] wire _legal_address_WIRE : UInt<1>[20] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[0], _legal_address_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[1], _legal_address_T_9 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[2], _legal_address_T_14 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[3], _legal_address_T_19 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[4], _legal_address_T_24 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[5], _legal_address_T_29 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[6], _legal_address_T_34 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[7], _legal_address_T_39 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[8], _legal_address_T_44 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[9], _legal_address_T_49 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[10], _legal_address_T_54 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[11], _legal_address_T_59 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[12], _legal_address_T_64 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[13], _legal_address_T_69 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[14], _legal_address_T_74 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[15], _legal_address_T_79 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[16], _legal_address_T_84 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[17], _legal_address_T_89 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[18], _legal_address_T_94 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[19], _legal_address_T_99 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] node _legal_address_T_100 = or(_legal_address_WIRE[0], _legal_address_WIRE[1]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_101 = or(_legal_address_T_100, _legal_address_WIRE[2]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_102 = or(_legal_address_T_101, _legal_address_WIRE[3]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_103 = or(_legal_address_T_102, _legal_address_WIRE[4]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_104 = or(_legal_address_T_103, _legal_address_WIRE[5]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_105 = or(_legal_address_T_104, _legal_address_WIRE[6]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_106 = or(_legal_address_T_105, _legal_address_WIRE[7]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_107 = or(_legal_address_T_106, _legal_address_WIRE[8]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_108 = or(_legal_address_T_107, _legal_address_WIRE[9]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_109 = or(_legal_address_T_108, _legal_address_WIRE[10]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_110 = or(_legal_address_T_109, _legal_address_WIRE[11]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_111 = or(_legal_address_T_110, _legal_address_WIRE[12]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_112 = or(_legal_address_T_111, _legal_address_WIRE[13]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_113 = or(_legal_address_T_112, _legal_address_WIRE[14]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_114 = or(_legal_address_T_113, _legal_address_WIRE[15]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_115 = or(_legal_address_T_114, _legal_address_WIRE[16]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_116 = or(_legal_address_T_115, _legal_address_WIRE[17]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_117 = or(_legal_address_T_116, _legal_address_WIRE[18]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node legal_address = or(_legal_address_T_117, _legal_address_WIRE[19]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_cacheable_T_5 = and(legal_address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.cacheable, _io_resp_cacheable_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 41:21] node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_r_T_1 = cvt(_io_resp_r_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.r, _io_resp_r_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 42:13] node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_1 = cvt(_io_resp_w_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_5 = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_6 = cvt(_io_resp_w_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_10 = xor(io.paddr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_11 = cvt(_io_resp_w_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_15 = xor(io.paddr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_16 = cvt(_io_resp_w_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_20 = xor(io.paddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_21 = cvt(_io_resp_w_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_25 = xor(io.paddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_26 = cvt(_io_resp_w_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_30 = or(_io_resp_w_T_4, _io_resp_w_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_w_T_31 = or(_io_resp_w_T_30, _io_resp_w_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_w_T_32 = or(_io_resp_w_T_31, _io_resp_w_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_w_T_33 = or(_io_resp_w_T_32, _io_resp_w_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_w_T_34 = or(_io_resp_w_T_33, _io_resp_w_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_w_T_35 = xor(io.paddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_36 = cvt(_io_resp_w_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_37 = and(_io_resp_w_T_36, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_38 = asSInt(_io_resp_w_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_39 = eq(_io_resp_w_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_40 = mux(_io_resp_w_T_34, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_w_T_41 = mux(_io_resp_w_T_39, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_w_T_42 = or(_io_resp_w_T_40, _io_resp_w_T_41) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_resp_w_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_resp_w_WIRE, _io_resp_w_T_42 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_w_T_43 = and(legal_address, _io_resp_w_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.w, _io_resp_w_T_43 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 43:13] node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_1 = cvt(_io_resp_pp_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_5 = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_10 = xor(io.paddr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_15 = xor(io.paddr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_20 = xor(io.paddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_25 = xor(io.paddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_30 = or(_io_resp_pp_T_4, _io_resp_pp_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_pp_T_31 = or(_io_resp_pp_T_30, _io_resp_pp_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_pp_T_32 = or(_io_resp_pp_T_31, _io_resp_pp_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_pp_T_33 = or(_io_resp_pp_T_32, _io_resp_pp_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_pp_T_34 = or(_io_resp_pp_T_33, _io_resp_pp_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_pp_T_35 = xor(io.paddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_36 = cvt(_io_resp_pp_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_37 = and(_io_resp_pp_T_36, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_38 = asSInt(_io_resp_pp_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_39 = eq(_io_resp_pp_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_40 = mux(_io_resp_pp_T_34, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_pp_T_41 = mux(_io_resp_pp_T_39, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_pp_T_42 = or(_io_resp_pp_T_40, _io_resp_pp_T_41) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_resp_pp_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_resp_pp_WIRE, _io_resp_pp_T_42 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_pp_T_43 = and(legal_address, _io_resp_pp_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.pp, _io_resp_pp_T_43 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 44:14] node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_1 = cvt(_io_resp_al_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_5 = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_6 = cvt(_io_resp_al_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_10 = xor(io.paddr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_11 = cvt(_io_resp_al_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_15 = xor(io.paddr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_16 = cvt(_io_resp_al_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_20 = xor(io.paddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_21 = cvt(_io_resp_al_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_25 = xor(io.paddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_26 = cvt(_io_resp_al_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_30 = or(_io_resp_al_T_4, _io_resp_al_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_al_T_31 = or(_io_resp_al_T_30, _io_resp_al_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_al_T_32 = or(_io_resp_al_T_31, _io_resp_al_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_al_T_33 = or(_io_resp_al_T_32, _io_resp_al_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_al_T_34 = or(_io_resp_al_T_33, _io_resp_al_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_al_T_35 = xor(io.paddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_36 = cvt(_io_resp_al_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_37 = and(_io_resp_al_T_36, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_38 = asSInt(_io_resp_al_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_39 = eq(_io_resp_al_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_40 = mux(_io_resp_al_T_34, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_al_T_41 = mux(_io_resp_al_T_39, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_al_T_42 = or(_io_resp_al_T_40, _io_resp_al_T_41) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_resp_al_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_resp_al_WIRE, _io_resp_al_T_42 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_al_T_43 = and(legal_address, _io_resp_al_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.al, _io_resp_al_T_43 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 45:14] node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_1 = cvt(_io_resp_aa_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_5 = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_10 = xor(io.paddr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_15 = xor(io.paddr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_20 = xor(io.paddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_25 = xor(io.paddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_30 = or(_io_resp_aa_T_4, _io_resp_aa_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_aa_T_31 = or(_io_resp_aa_T_30, _io_resp_aa_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_aa_T_32 = or(_io_resp_aa_T_31, _io_resp_aa_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_aa_T_33 = or(_io_resp_aa_T_32, _io_resp_aa_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_aa_T_34 = or(_io_resp_aa_T_33, _io_resp_aa_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_aa_T_35 = xor(io.paddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_36 = cvt(_io_resp_aa_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_37 = and(_io_resp_aa_T_36, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_38 = asSInt(_io_resp_aa_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_39 = eq(_io_resp_aa_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_40 = mux(_io_resp_aa_T_34, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_aa_T_41 = mux(_io_resp_aa_T_39, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_aa_T_42 = or(_io_resp_aa_T_40, _io_resp_aa_T_41) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_resp_aa_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_resp_aa_WIRE, _io_resp_aa_T_42 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_aa_T_43 = and(legal_address, _io_resp_aa_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.aa, _io_resp_aa_T_43 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 46:14] node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_x_T_1 = cvt(_io_resp_x_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<32>(0h7a000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_x_T_5 = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_x_T_6 = cvt(_io_resp_x_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0hfa004000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_x_T_10 = or(_io_resp_x_T_4, _io_resp_x_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_x_T_11 = xor(io.paddr, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_x_T_12 = cvt(_io_resp_x_T_11) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_x_T_13 = and(_io_resp_x_T_12, asSInt(UInt<33>(0hfa000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_14 = asSInt(_io_resp_x_T_13) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_15 = eq(_io_resp_x_T_14, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_x_T_16 = xor(io.paddr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_x_T_17 = cvt(_io_resp_x_T_16) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_x_T_18 = and(_io_resp_x_T_17, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_19 = asSInt(_io_resp_x_T_18) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_20 = eq(_io_resp_x_T_19, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_x_T_21 = xor(io.paddr, UInt<29>(0h10000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_x_T_22 = cvt(_io_resp_x_T_21) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_x_T_23 = and(_io_resp_x_T_22, asSInt(UInt<33>(0hfa000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_24 = asSInt(_io_resp_x_T_23) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_25 = eq(_io_resp_x_T_24, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_x_T_26 = or(_io_resp_x_T_15, _io_resp_x_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_x_T_28 = mux(_io_resp_x_T_10, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_x_T_29 = mux(_io_resp_x_T_27, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_x_T_30 = or(_io_resp_x_T_28, _io_resp_x_T_29) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_resp_x_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_resp_x_WIRE, _io_resp_x_T_30 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_x_T_31 = and(legal_address, _io_resp_x_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.x, _io_resp_x_T_31 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 47:13] node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_1 = cvt(_io_resp_eff_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_5 = xor(io.paddr, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_10 = xor(io.paddr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_15 = xor(io.paddr, UInt<29>(0h10000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0hfa018000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_20 = xor(io.paddr, UInt<29>(0h10008000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_25 = xor(io.paddr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_30 = xor(io.paddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_31 = cvt(_io_resp_eff_T_30) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_32 = and(_io_resp_eff_T_31, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_33 = asSInt(_io_resp_eff_T_32) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_34 = eq(_io_resp_eff_T_33, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_35 = or(_io_resp_eff_T_4, _io_resp_eff_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_36 = or(_io_resp_eff_T_35, _io_resp_eff_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_37 = or(_io_resp_eff_T_36, _io_resp_eff_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_38 = or(_io_resp_eff_T_37, _io_resp_eff_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_39 = or(_io_resp_eff_T_38, _io_resp_eff_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_40 = or(_io_resp_eff_T_39, _io_resp_eff_T_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_41 = xor(io.paddr, UInt<13>(0h1000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_42 = cvt(_io_resp_eff_T_41) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_43 = and(_io_resp_eff_T_42, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_44 = asSInt(_io_resp_eff_T_43) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_45 = eq(_io_resp_eff_T_44, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_46 = xor(io.paddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_47 = cvt(_io_resp_eff_T_46) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_48 = and(_io_resp_eff_T_47, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_49 = asSInt(_io_resp_eff_T_48) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_50 = eq(_io_resp_eff_T_49, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_51 = xor(io.paddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_52 = cvt(_io_resp_eff_T_51) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_53 = and(_io_resp_eff_T_52, asSInt(UInt<33>(0hfa000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_54 = asSInt(_io_resp_eff_T_53) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_55 = eq(_io_resp_eff_T_54, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_56 = or(_io_resp_eff_T_45, _io_resp_eff_T_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_57 = or(_io_resp_eff_T_56, _io_resp_eff_T_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_58 = mux(_io_resp_eff_T_40, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_eff_T_59 = mux(_io_resp_eff_T_57, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_eff_T_60 = or(_io_resp_eff_T_58, _io_resp_eff_T_59) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_resp_eff_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_resp_eff_WIRE, _io_resp_eff_T_60 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_eff_T_61 = and(legal_address, _io_resp_eff_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.eff, _io_resp_eff_T_61 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 48:15] module OptimizationBarrier_TLBEntryData_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module OptimizationBarrier_TLBEntryData_2 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module OptimizationBarrier_TLBEntryData_3 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module OptimizationBarrier_TLBEntryData_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module OptimizationBarrier_TLBEntryData_5 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module OptimizationBarrier_TLBEntryData_6 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module DTLB : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 318:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 318:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 318:7] output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<34>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<34>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<33>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<21>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<33>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 320:14] invalidate io.ptw.customCSRs.csrs[0].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[0].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[0].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[0].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[0].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[0].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[0].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] node vpn = bits(io.req.bits.vaddr, 32, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 335:30] reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<21>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[1][1], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 339:29] reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<21>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 341:30] reg special_entry : { level : UInt<2>, tag_vpn : UInt<21>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 346:56] regreset state : UInt<2>, clock, reset, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 352:22] reg r_refill_tag : UInt<21>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 354:25] reg r_superpage_repl_addr : UInt<2>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 355:34] reg r_sectored_repl_addr : UInt<0>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 356:33] reg r_sectored_hit : { valid : UInt<1>, bits : UInt<0>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 357:27] reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 358:28] reg r_vstage1_en : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 359:25] reg r_stage2_en : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 360:24] reg r_need_gpa : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 361:23] reg r_gpa_valid : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 362:24] reg r_gpa : UInt<33>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 363:18] reg r_gpa_vpn : UInt<21>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 364:22] reg r_gpa_is_pte : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 365:25] node priv_v = and(UInt<1>(0h0), io.req.bits.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 369:34] node priv_s = bits(io.req.bits.prv, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 370:20] node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 372:27] node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 373:17] node _stage1_en_T = bits(satp.mode, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 374:41] node stage1_en = and(UInt<1>(0h0), _stage1_en_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 374:29] node _vstage1_en_T = and(UInt<1>(0h0), priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 376:38] node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 376:68] node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 376:48] node _stage2_en_T = and(UInt<1>(0h0), priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 378:38] node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 378:68] node stage2_en = and(_stage2_en_T, _stage2_en_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 378:48] node _vm_enabled_T = or(stage1_en, stage2_en) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 399:31] node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 399:45] node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 399:64] node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 399:61] regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 402:37] node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 403:52] node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 403:37] node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 403:81] node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 403:78] node do_refill = and(UInt<1>(0h0), io.ptw.resp.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 408:29] node _invalidate_refill_T = eq(state, UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 410:88] node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 413:32] wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _mpu_ppn_WIRE_1 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE_1, special_entry.data[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect mpu_ppn_barrier.clock, clock connect mpu_ppn_barrier.reset, reset connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] node _mpu_ppn_T_24 = shr(io.req.bits.vaddr, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 413:146] node _mpu_ppn_T_25 = mux(_mpu_ppn_T, mpu_ppn_barrier.io.y.ppn, _mpu_ppn_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 413:20] node mpu_ppn = mux(do_refill, UInt<1>(0h0), _mpu_ppn_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 412:20] node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 414:52] node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 414:25] node _mpu_priv_T = or(do_refill, io.req.bits.passthrough) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 415:52] node _mpu_priv_T_1 = and(UInt<1>(0h0), _mpu_priv_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 415:38] node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 415:103] node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 415:27] inst pmp of PMPChecker_s3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 416:19] connect pmp.clock, clock connect pmp.reset, reset connect pmp.io.addr, mpu_physaddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 417:15] connect pmp.io.size, io.req.bits.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 418:15] connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.prv, mpu_priv @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 420:14] inst pma of PMAChecker @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 422:19] connect pma.clock, clock connect pma.reset, reset connect pma.io.paddr, mpu_physaddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 423:16] node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 425:41] node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_1 = cvt(_homogeneous_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_3 = asSInt(_homogeneous_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_6 = cvt(_homogeneous_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_8 = asSInt(_homogeneous_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_11 = cvt(_homogeneous_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_13 = asSInt(_homogeneous_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_15 = xor(mpu_physaddr, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_16 = cvt(_homogeneous_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<17>(0h10000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_18 = asSInt(_homogeneous_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_20 = xor(mpu_physaddr, UInt<28>(0hc000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_21 = cvt(_homogeneous_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<27>(0h4000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_23 = asSInt(_homogeneous_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_25 = xor(mpu_physaddr, UInt<29>(0h10013000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_26 = cvt(_homogeneous_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_28 = asSInt(_homogeneous_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_30 = xor(mpu_physaddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_31 = cvt(_homogeneous_T_30) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<14>(0h2000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_33 = asSInt(_homogeneous_T_32) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_35 = xor(mpu_physaddr, UInt<29>(0h10020000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_36 = cvt(_homogeneous_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<16>(0h8000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_38 = asSInt(_homogeneous_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10028000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_41 = cvt(_homogeneous_T_40) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<14>(0h2000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_43 = asSInt(_homogeneous_T_42) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_45 = xor(mpu_physaddr, UInt<29>(0h1002a000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_46 = cvt(_homogeneous_T_45) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_48 = asSInt(_homogeneous_T_47) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_50 = xor(mpu_physaddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_51 = cvt(_homogeneous_T_50) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_52 = and(_homogeneous_T_51, asSInt(UInt<21>(0h100000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_53 = asSInt(_homogeneous_T_52) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_54 = eq(_homogeneous_T_53, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_55 = or(UInt<1>(0h0), _homogeneous_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_59 = or(_homogeneous_T_58, _homogeneous_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_60 = or(_homogeneous_T_59, _homogeneous_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_61 = or(_homogeneous_T_60, _homogeneous_T_34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_62 = or(_homogeneous_T_61, _homogeneous_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_63 = or(_homogeneous_T_62, _homogeneous_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_64 = or(_homogeneous_T_63, _homogeneous_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node homogeneous = or(_homogeneous_T_64, _homogeneous_T_54) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_65 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _homogeneous_T_66 = xor(mpu_physaddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_67 = cvt(_homogeneous_T_66) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_68 = and(_homogeneous_T_67, asSInt(UInt<33>(0h98010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_69 = asSInt(_homogeneous_T_68) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_70 = eq(_homogeneous_T_69, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_71 = or(UInt<1>(0h0), _homogeneous_T_70) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:66] node _homogeneous_T_72 = eq(_homogeneous_T_71, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _homogeneous_T_73 = xor(mpu_physaddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_74 = cvt(_homogeneous_T_73) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_75 = and(_homogeneous_T_74, asSInt(UInt<30>(0h1a000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_76 = asSInt(_homogeneous_T_75) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_77 = eq(_homogeneous_T_76, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_78 = or(UInt<1>(0h0), _homogeneous_T_77) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 85:66] node _homogeneous_T_79 = xor(mpu_physaddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_80 = cvt(_homogeneous_T_79) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_81 = and(_homogeneous_T_80, asSInt(UInt<33>(0h98010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_82 = asSInt(_homogeneous_T_81) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_83 = eq(_homogeneous_T_82, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_84 = or(UInt<1>(0h0), _homogeneous_T_83) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:66] node _homogeneous_T_85 = eq(_homogeneous_T_84, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _homogeneous_T_86 = xor(mpu_physaddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_87 = cvt(_homogeneous_T_86) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_88 = and(_homogeneous_T_87, asSInt(UInt<33>(0h98010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_89 = asSInt(_homogeneous_T_88) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_90 = eq(_homogeneous_T_89, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_91 = or(UInt<1>(0h0), _homogeneous_T_90) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:66] node _homogeneous_T_92 = eq(_homogeneous_T_91, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 428:39] node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 428:50] node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 429:33] node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 429:30] node prot_r = and(_prot_r_T_1, pmp.io.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 429:55] node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 430:33] node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 430:30] node prot_w = and(_prot_w_T_1, pmp.io.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 430:55] node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 434:33] node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 434:30] node prot_x = and(_prot_x_T_1, pmp.io.x) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 434:55] node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _sector_hits_T_4 = shr(_sector_hits_T_3, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 172:55] node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _superpage_hits_T_1 = shr(_superpage_hits_T, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _superpage_hits_T_3 = eq(superpage_entries[0].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _superpage_hits_T_4 = and(_superpage_hits_T_2, _superpage_hits_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node superpage_hits_0 = and(superpage_entries[0].valid[0], _superpage_hits_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node _superpage_hits_T_5 = xor(superpage_entries[1].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _superpage_hits_T_6 = shr(_superpage_hits_T_5, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _superpage_hits_T_8 = eq(superpage_entries[1].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _superpage_hits_T_9 = and(_superpage_hits_T_7, _superpage_hits_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node superpage_hits_1 = and(superpage_entries[1].valid[0], _superpage_hits_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node _superpage_hits_T_10 = xor(superpage_entries[2].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _superpage_hits_T_11 = shr(_superpage_hits_T_10, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _superpage_hits_T_13 = eq(superpage_entries[2].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _superpage_hits_T_14 = and(_superpage_hits_T_12, _superpage_hits_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node superpage_hits_2 = and(superpage_entries[2].valid[0], _superpage_hits_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node _superpage_hits_T_15 = xor(superpage_entries[3].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _superpage_hits_T_16 = shr(_superpage_hits_T_15, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _superpage_hits_T_17 = eq(_superpage_hits_T_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _superpage_hits_T_18 = eq(superpage_entries[3].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _superpage_hits_T_19 = and(_superpage_hits_T_17, _superpage_hits_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node superpage_hits_3 = and(superpage_entries[3].valid[0], _superpage_hits_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_idx = bits(vpn, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _hitsVec_T_1 = shr(_hitsVec_T, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_0 = and(vm_enabled, _hitsVec_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 440:44] node _hitsVec_T_6 = xor(superpage_entries[0].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _hitsVec_T_7 = shr(_hitsVec_T_6, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _hitsVec_T_9 = eq(superpage_entries[0].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node _hitsVec_T_11 = and(superpage_entries[0].valid[0], _hitsVec_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_1 = and(vm_enabled, _hitsVec_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 440:44] node _hitsVec_T_12 = xor(superpage_entries[1].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _hitsVec_T_13 = shr(_hitsVec_T_12, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _hitsVec_T_15 = eq(superpage_entries[1].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node _hitsVec_T_17 = and(superpage_entries[1].valid[0], _hitsVec_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_2 = and(vm_enabled, _hitsVec_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 440:44] node _hitsVec_T_18 = xor(superpage_entries[2].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _hitsVec_T_19 = shr(_hitsVec_T_18, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _hitsVec_T_21 = eq(superpage_entries[2].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node _hitsVec_T_23 = and(superpage_entries[2].valid[0], _hitsVec_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_3 = and(vm_enabled, _hitsVec_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 440:44] node _hitsVec_T_24 = xor(superpage_entries[3].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _hitsVec_T_25 = shr(_hitsVec_T_24, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _hitsVec_T_27 = eq(superpage_entries[3].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _hitsVec_T_28 = and(_hitsVec_T_26, _hitsVec_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node _hitsVec_T_29 = and(superpage_entries[3].valid[0], _hitsVec_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_4 = and(vm_enabled, _hitsVec_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 440:44] node _hitsVec_T_30 = xor(special_entry.tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _hitsVec_T_31 = shr(_hitsVec_T_30, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _hitsVec_T_33 = eq(special_entry.tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _hitsVec_T_34 = and(_hitsVec_T_32, _hitsVec_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node _hitsVec_T_35 = and(special_entry.valid[0], _hitsVec_T_34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_5 = and(vm_enabled, _hitsVec_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 440:44] node real_hits_lo_hi = cat(hitsVec_2, hitsVec_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node real_hits_lo = cat(real_hits_lo_hi, hitsVec_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node real_hits_hi_hi = cat(hitsVec_5, hitsVec_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node real_hits_hi = cat(real_hits_hi_hi, hitsVec_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node real_hits = cat(real_hits_hi, real_hits_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hits_T = eq(vm_enabled, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 442:18] node hits = cat(_hits_T, real_hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 442:17] when do_refill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 446:20] node refill_v = or(r_vstage1_en, r_stage2_en) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 448:33] wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 449:24] connect newEntry.ppn, io.ptw.resp.bits.pte.ppn @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 450:18] connect newEntry.c, cacheable @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 451:16] connect newEntry.u, io.ptw.resp.bits.pte.u @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 452:16] node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 453:25] connect newEntry.g, _newEntry_g_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 453:16] connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 454:21] connect newEntry.ae_final, io.ptw.resp.bits.ae_final @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 455:23] node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 456:53] node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 456:84] connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 456:24] connect newEntry.pf, io.ptw.resp.bits.pf @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 457:17] connect newEntry.gf, io.ptw.resp.bits.gf @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 458:17] connect newEntry.hr, io.ptw.resp.bits.hr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 459:17] connect newEntry.hw, io.ptw.resp.bits.hw @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 460:17] connect newEntry.hx, io.ptw.resp.bits.hx @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 461:17] node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:47] node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:44] node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:38] node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:32] node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:52] node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 149:35] connect newEntry.sr, _newEntry_sr_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 462:17] node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:47] node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:44] node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:38] node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:32] node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:52] node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 151:35] node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 151:40] connect newEntry.sw, _newEntry_sw_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 463:17] node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:47] node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:44] node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:38] node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:32] node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:52] node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 153:35] connect newEntry.sx, _newEntry_sx_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 464:17] connect newEntry.pr, prot_r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 465:17] connect newEntry.pw, prot_w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 466:17] connect newEntry.px, prot_x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 467:17] connect newEntry.ppp, pma.io.resp.pp @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 468:18] connect newEntry.pal, pma.io.resp.al @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 469:18] connect newEntry.paa, pma.io.resp.aa @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 470:18] connect newEntry.eff, pma.io.resp.eff @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 471:18] connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 472:35] node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 474:39] node _T_1 = and(UInt<1>(0h1), _T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 474:36] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 474:70] connect special_entry.tag_vpn, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 211:18] connect special_entry.tag_v, refill_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 212:16] node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect special_entry.level, _special_entry_level_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 213:16] connect special_entry.valid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 216:16] node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] connect special_entry.data[0], _special_entry_data_0_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:15] else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 476:40] when _T_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 476:58] node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 477:45] node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 477:22] node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:82] when _T_3 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:91] connect superpage_entries[0].tag_vpn, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 211:18] connect superpage_entries[0].tag_v, refill_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 212:16] node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect superpage_entries[0].level, _superpage_entries_0_level_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 213:16] connect superpage_entries[0].valid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 216:16] node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:15] when invalidate_refill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 480:34] connect superpage_entries[0].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:82] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:91] connect superpage_entries[1].tag_vpn, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 211:18] connect superpage_entries[1].tag_v, refill_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 212:16] node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect superpage_entries[1].level, _superpage_entries_1_level_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 213:16] connect superpage_entries[1].valid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 216:16] node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:15] when invalidate_refill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 480:34] connect superpage_entries[1].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:82] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:91] connect superpage_entries[2].tag_vpn, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 211:18] connect superpage_entries[2].tag_v, refill_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 212:16] node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect superpage_entries[2].level, _superpage_entries_2_level_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 213:16] connect superpage_entries[2].valid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 216:16] node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:15] when invalidate_refill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 480:34] connect superpage_entries[2].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:82] when _T_6 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:91] connect superpage_entries[3].tag_vpn, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 211:18] connect superpage_entries[3].tag_v, refill_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 212:16] node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect superpage_entries[3].level, _superpage_entries_3_level_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 213:16] connect superpage_entries[3].valid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 216:16] node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:15] when invalidate_refill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 480:34] connect superpage_entries[3].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] else : node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 485:22] node _T_7 = eq(waddr_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 486:75] when _T_7 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 486:84] node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 487:15] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 487:38] connect sectored_entries[0][0].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].valid[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].valid[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].valid[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].tag_vpn, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 211:18] connect sectored_entries[0][0].tag_v, refill_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 212:16] connect sectored_entries[0][0].level, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 213:16] node idx = bits(r_refill_tag, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect sectored_entries[0][0].valid[idx], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 216:16] node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:15] when invalidate_refill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 489:34] connect sectored_entries[0][0].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].valid[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].valid[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].valid[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect r_gpa_valid, io.ptw.resp.bits.gpa.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 493:17] connect r_gpa, io.ptw.resp.bits.gpa.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 494:11] connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 495:18] node _entries_T = bits(vpn, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _entries_WIRE_1 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_1 = bits(_entries_WIRE_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.fragmented_superpage, _entries_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_2 = bits(_entries_WIRE_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.c, _entries_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_3 = bits(_entries_WIRE_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.eff, _entries_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_4 = bits(_entries_WIRE_1, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.paa, _entries_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_5 = bits(_entries_WIRE_1, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.pal, _entries_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_6 = bits(_entries_WIRE_1, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.ppp, _entries_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_7 = bits(_entries_WIRE_1, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.pr, _entries_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_8 = bits(_entries_WIRE_1, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.px, _entries_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_9 = bits(_entries_WIRE_1, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.pw, _entries_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_10 = bits(_entries_WIRE_1, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.hr, _entries_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_11 = bits(_entries_WIRE_1, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.hx, _entries_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_12 = bits(_entries_WIRE_1, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.hw, _entries_T_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_13 = bits(_entries_WIRE_1, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.sr, _entries_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_14 = bits(_entries_WIRE_1, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.sx, _entries_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_15 = bits(_entries_WIRE_1, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.sw, _entries_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_16 = bits(_entries_WIRE_1, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.gf, _entries_T_16 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_17 = bits(_entries_WIRE_1, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.pf, _entries_T_17 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_18 = bits(_entries_WIRE_1, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.ae_stage2, _entries_T_18 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_19 = bits(_entries_WIRE_1, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.ae_final, _entries_T_19 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_20 = bits(_entries_WIRE_1, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.ae_ptw, _entries_T_20 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_21 = bits(_entries_WIRE_1, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.g, _entries_T_21 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_22 = bits(_entries_WIRE_1, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.u, _entries_T_22 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_23 = bits(_entries_WIRE_1, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.ppn, _entries_T_23 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst entries_barrier of OptimizationBarrier_TLBEntryData_1 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.c, _entries_WIRE.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.eff, _entries_WIRE.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.paa, _entries_WIRE.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.pal, _entries_WIRE.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.ppp, _entries_WIRE.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.pr, _entries_WIRE.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.px, _entries_WIRE.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.pw, _entries_WIRE.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.hr, _entries_WIRE.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.hx, _entries_WIRE.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.hw, _entries_WIRE.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.sr, _entries_WIRE.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.sx, _entries_WIRE.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.sw, _entries_WIRE.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.gf, _entries_WIRE.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.pf, _entries_WIRE.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.g, _entries_WIRE.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.u, _entries_WIRE.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.ppn, _entries_WIRE.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _entries_WIRE_3 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_3, superpage_entries[0].data[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_24 = bits(_entries_WIRE_3, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.fragmented_superpage, _entries_T_24 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_25 = bits(_entries_WIRE_3, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.c, _entries_T_25 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_26 = bits(_entries_WIRE_3, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.eff, _entries_T_26 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_27 = bits(_entries_WIRE_3, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.paa, _entries_T_27 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_28 = bits(_entries_WIRE_3, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.pal, _entries_T_28 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_29 = bits(_entries_WIRE_3, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.ppp, _entries_T_29 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_30 = bits(_entries_WIRE_3, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.pr, _entries_T_30 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_31 = bits(_entries_WIRE_3, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.px, _entries_T_31 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_32 = bits(_entries_WIRE_3, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.pw, _entries_T_32 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_33 = bits(_entries_WIRE_3, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.hr, _entries_T_33 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_34 = bits(_entries_WIRE_3, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.hx, _entries_T_34 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_35 = bits(_entries_WIRE_3, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.hw, _entries_T_35 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_36 = bits(_entries_WIRE_3, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.sr, _entries_T_36 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_37 = bits(_entries_WIRE_3, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.sx, _entries_T_37 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_38 = bits(_entries_WIRE_3, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.sw, _entries_T_38 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_39 = bits(_entries_WIRE_3, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.gf, _entries_T_39 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_40 = bits(_entries_WIRE_3, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.pf, _entries_T_40 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_41 = bits(_entries_WIRE_3, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.ae_stage2, _entries_T_41 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_42 = bits(_entries_WIRE_3, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.ae_final, _entries_T_42 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_43 = bits(_entries_WIRE_3, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.ae_ptw, _entries_T_43 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_44 = bits(_entries_WIRE_3, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.g, _entries_T_44 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_45 = bits(_entries_WIRE_3, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.u, _entries_T_45 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_46 = bits(_entries_WIRE_3, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.ppn, _entries_T_46 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.c, _entries_WIRE_2.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.px, _entries_WIRE_2.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.g, _entries_WIRE_2.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.u, _entries_WIRE_2.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _entries_WIRE_5 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_5, superpage_entries[1].data[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_47 = bits(_entries_WIRE_5, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.fragmented_superpage, _entries_T_47 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_48 = bits(_entries_WIRE_5, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.c, _entries_T_48 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_49 = bits(_entries_WIRE_5, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.eff, _entries_T_49 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_50 = bits(_entries_WIRE_5, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.paa, _entries_T_50 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_51 = bits(_entries_WIRE_5, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.pal, _entries_T_51 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_52 = bits(_entries_WIRE_5, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.ppp, _entries_T_52 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_53 = bits(_entries_WIRE_5, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.pr, _entries_T_53 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_54 = bits(_entries_WIRE_5, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.px, _entries_T_54 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_55 = bits(_entries_WIRE_5, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.pw, _entries_T_55 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_56 = bits(_entries_WIRE_5, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.hr, _entries_T_56 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_57 = bits(_entries_WIRE_5, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.hx, _entries_T_57 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_58 = bits(_entries_WIRE_5, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.hw, _entries_T_58 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_59 = bits(_entries_WIRE_5, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.sr, _entries_T_59 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_60 = bits(_entries_WIRE_5, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.sx, _entries_T_60 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_61 = bits(_entries_WIRE_5, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.sw, _entries_T_61 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_62 = bits(_entries_WIRE_5, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.gf, _entries_T_62 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_63 = bits(_entries_WIRE_5, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.pf, _entries_T_63 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_64 = bits(_entries_WIRE_5, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.ae_stage2, _entries_T_64 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_65 = bits(_entries_WIRE_5, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.ae_final, _entries_T_65 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_66 = bits(_entries_WIRE_5, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.ae_ptw, _entries_T_66 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_67 = bits(_entries_WIRE_5, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.g, _entries_T_67 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_68 = bits(_entries_WIRE_5, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.u, _entries_T_68 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_69 = bits(_entries_WIRE_5, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.ppn, _entries_T_69 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_3 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.c, _entries_WIRE_4.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.px, _entries_WIRE_4.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.g, _entries_WIRE_4.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.u, _entries_WIRE_4.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _entries_WIRE_7 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_7, superpage_entries[2].data[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_70 = bits(_entries_WIRE_7, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.fragmented_superpage, _entries_T_70 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_71 = bits(_entries_WIRE_7, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.c, _entries_T_71 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_72 = bits(_entries_WIRE_7, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.eff, _entries_T_72 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_73 = bits(_entries_WIRE_7, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.paa, _entries_T_73 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_74 = bits(_entries_WIRE_7, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.pal, _entries_T_74 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_75 = bits(_entries_WIRE_7, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.ppp, _entries_T_75 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_76 = bits(_entries_WIRE_7, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.pr, _entries_T_76 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_77 = bits(_entries_WIRE_7, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.px, _entries_T_77 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_78 = bits(_entries_WIRE_7, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.pw, _entries_T_78 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_79 = bits(_entries_WIRE_7, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.hr, _entries_T_79 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_80 = bits(_entries_WIRE_7, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.hx, _entries_T_80 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_81 = bits(_entries_WIRE_7, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.hw, _entries_T_81 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_82 = bits(_entries_WIRE_7, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.sr, _entries_T_82 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_83 = bits(_entries_WIRE_7, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.sx, _entries_T_83 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_84 = bits(_entries_WIRE_7, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.sw, _entries_T_84 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_85 = bits(_entries_WIRE_7, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.gf, _entries_T_85 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_86 = bits(_entries_WIRE_7, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.pf, _entries_T_86 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_87 = bits(_entries_WIRE_7, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.ae_stage2, _entries_T_87 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_88 = bits(_entries_WIRE_7, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.ae_final, _entries_T_88 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_89 = bits(_entries_WIRE_7, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.ae_ptw, _entries_T_89 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_90 = bits(_entries_WIRE_7, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.g, _entries_T_90 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_91 = bits(_entries_WIRE_7, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.u, _entries_T_91 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_92 = bits(_entries_WIRE_7, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.ppn, _entries_T_92 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_4 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.c, _entries_WIRE_6.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.px, _entries_WIRE_6.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.g, _entries_WIRE_6.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.u, _entries_WIRE_6.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _entries_WIRE_9 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_9, superpage_entries[3].data[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_93 = bits(_entries_WIRE_9, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.fragmented_superpage, _entries_T_93 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_94 = bits(_entries_WIRE_9, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.c, _entries_T_94 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_95 = bits(_entries_WIRE_9, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.eff, _entries_T_95 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_96 = bits(_entries_WIRE_9, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.paa, _entries_T_96 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_97 = bits(_entries_WIRE_9, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.pal, _entries_T_97 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_98 = bits(_entries_WIRE_9, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.ppp, _entries_T_98 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_99 = bits(_entries_WIRE_9, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.pr, _entries_T_99 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_100 = bits(_entries_WIRE_9, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.px, _entries_T_100 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_101 = bits(_entries_WIRE_9, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.pw, _entries_T_101 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_102 = bits(_entries_WIRE_9, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.hr, _entries_T_102 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_103 = bits(_entries_WIRE_9, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.hx, _entries_T_103 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_104 = bits(_entries_WIRE_9, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.hw, _entries_T_104 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_105 = bits(_entries_WIRE_9, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.sr, _entries_T_105 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_106 = bits(_entries_WIRE_9, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.sx, _entries_T_106 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_107 = bits(_entries_WIRE_9, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.sw, _entries_T_107 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_108 = bits(_entries_WIRE_9, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.gf, _entries_T_108 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_109 = bits(_entries_WIRE_9, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.pf, _entries_T_109 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_110 = bits(_entries_WIRE_9, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.ae_stage2, _entries_T_110 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_111 = bits(_entries_WIRE_9, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.ae_final, _entries_T_111 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_112 = bits(_entries_WIRE_9, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.ae_ptw, _entries_T_112 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_113 = bits(_entries_WIRE_9, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.g, _entries_T_113 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_114 = bits(_entries_WIRE_9, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.u, _entries_T_114 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_115 = bits(_entries_WIRE_9, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.ppn, _entries_T_115 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_5 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.c, _entries_WIRE_8.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.px, _entries_WIRE_8.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.g, _entries_WIRE_8.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.u, _entries_WIRE_8.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _entries_WIRE_11 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_11, special_entry.data[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_116 = bits(_entries_WIRE_11, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.fragmented_superpage, _entries_T_116 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_117 = bits(_entries_WIRE_11, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.c, _entries_T_117 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_118 = bits(_entries_WIRE_11, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.eff, _entries_T_118 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_119 = bits(_entries_WIRE_11, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.paa, _entries_T_119 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_120 = bits(_entries_WIRE_11, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.pal, _entries_T_120 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_121 = bits(_entries_WIRE_11, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.ppp, _entries_T_121 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_122 = bits(_entries_WIRE_11, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.pr, _entries_T_122 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_123 = bits(_entries_WIRE_11, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.px, _entries_T_123 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_124 = bits(_entries_WIRE_11, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.pw, _entries_T_124 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_125 = bits(_entries_WIRE_11, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.hr, _entries_T_125 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_126 = bits(_entries_WIRE_11, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.hx, _entries_T_126 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_127 = bits(_entries_WIRE_11, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.hw, _entries_T_127 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_128 = bits(_entries_WIRE_11, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.sr, _entries_T_128 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_129 = bits(_entries_WIRE_11, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.sx, _entries_T_129 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_130 = bits(_entries_WIRE_11, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.sw, _entries_T_130 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_131 = bits(_entries_WIRE_11, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.gf, _entries_T_131 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_132 = bits(_entries_WIRE_11, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.pf, _entries_T_132 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_133 = bits(_entries_WIRE_11, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.ae_stage2, _entries_T_133 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_134 = bits(_entries_WIRE_11, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.ae_final, _entries_T_134 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_135 = bits(_entries_WIRE_11, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.ae_ptw, _entries_T_135 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_136 = bits(_entries_WIRE_11, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.g, _entries_T_136 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_137 = bits(_entries_WIRE_11, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.u, _entries_T_137 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_138 = bits(_entries_WIRE_11, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.ppn, _entries_T_138 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_6 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.c, _entries_WIRE_10.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.px, _entries_WIRE_10.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.g, _entries_WIRE_10.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.u, _entries_WIRE_10.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] node _ppn_T = eq(vm_enabled, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 502:30] node _ppn_T_1 = bits(vpn, 19, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 502:125] node _ppn_T_2 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_3 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_4 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_5 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_6 = mux(hitsVec_4, entries_barrier_4.io.y.ppn, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_7 = mux(hitsVec_5, entries_barrier_5.io.y.ppn, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_8 = mux(_ppn_T, _ppn_T_1, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_9 = or(_ppn_T_2, _ppn_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_10 = or(_ppn_T_9, _ppn_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_11 = or(_ppn_T_10, _ppn_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_12 = or(_ppn_T_11, _ppn_T_6) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_13 = or(_ppn_T_12, _ppn_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_14 = or(_ppn_T_13, _ppn_T_8) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire ppn : UInt<20> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect ppn, _ppn_T_14 @[src/main/scala/chisel3/util/Mux.scala 30:73] node ptw_ae_array_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, entries_barrier.io.y.ae_ptw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_ae_array_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, entries_barrier_3.io.y.ae_ptw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 506:25] node final_ae_array_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node final_ae_array_lo = cat(final_ae_array_lo_hi, entries_barrier.io.y.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node final_ae_array_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node final_ae_array_hi = cat(final_ae_array_hi_hi, entries_barrier_3.io.y.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 507:27] node ptw_pf_array_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, entries_barrier.io.y.pf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_pf_array_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, entries_barrier_3.io.y.pf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 508:25] node ptw_gf_array_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, entries_barrier.io.y.gf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_gf_array_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, entries_barrier_3.io.y.gf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 509:25] node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 510:16] node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 513:24] node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 513:32] node priv_rw_ok_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, entries_barrier.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_rw_ok_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, entries_barrier_3.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 513:23] node priv_rw_ok_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, entries_barrier.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_rw_ok_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, entries_barrier_3.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 513:84] node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 513:75] node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 513:70] node priv_x_ok_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok_lo = cat(priv_x_ok_lo_hi, entries_barrier.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok_hi = cat(priv_x_ok_hi_hi, entries_barrier_3.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_x_ok_T_1 = not(_priv_x_ok_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 516:31] node priv_x_ok_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, entries_barrier.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, entries_barrier_3.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 516:22] node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<6>(0h3f), UInt<6>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 517:27] node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 517:83] node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<6>(0h3f), UInt<6>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 517:68] node stage1_bypass_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node stage1_bypass_lo = cat(stage1_bypass_lo_hi, entries_barrier.io.y.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node stage1_bypass_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node stage1_bypass_hi = cat(stage1_bypass_hi_hi, entries_barrier_3.io.y.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 517:95] node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 517:61] node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 518:36] node mxr = or(io.ptw.status.mxr, _mxr_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 518:31] node r_array_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_lo = cat(r_array_lo_hi, entries_barrier.io.y.sr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_hi = cat(r_array_hi_hi, entries_barrier_3.io.y.sr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _r_array_T = cat(r_array_hi, r_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_lo_1 = cat(r_array_lo_hi_1, entries_barrier.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_hi_1 = cat(r_array_hi_hi_1, entries_barrier_3.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 520:74] node _r_array_T_3 = or(_r_array_T, _r_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 520:69] node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 520:41] node _r_array_T_5 = or(_r_array_T_4, stage1_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 520:113] node r_array = cat(UInt<1>(0h1), _r_array_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 520:20] node w_array_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node w_array_lo = cat(w_array_lo_hi, entries_barrier.io.y.sw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node w_array_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node w_array_hi = cat(w_array_hi_hi, entries_barrier_3.io.y.sw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _w_array_T = cat(w_array_hi, w_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _w_array_T_1 = and(priv_rw_ok, _w_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 521:41] node _w_array_T_2 = or(_w_array_T_1, stage1_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 521:69] node w_array = cat(UInt<1>(0h1), _w_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 521:20] node x_array_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node x_array_lo = cat(x_array_lo_hi, entries_barrier.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node x_array_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node x_array_hi = cat(x_array_hi_hi, entries_barrier_3.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _x_array_T = cat(x_array_hi, x_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _x_array_T_1 = and(priv_x_ok, _x_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 522:40] node _x_array_T_2 = or(_x_array_T_1, stage1_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 522:68] node x_array = cat(UInt<1>(0h1), _x_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 522:20] node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 523:42] node stage2_bypass = mux(_stage2_bypass_T, UInt<6>(0h3f), UInt<6>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 523:27] node hr_array_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_lo = cat(hr_array_lo_hi, entries_barrier.io.y.hr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_hi = cat(hr_array_hi_hi, entries_barrier_3.io.y.hr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hr_array_T = cat(hr_array_hi, hr_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_lo_1 = cat(hr_array_lo_hi_1, entries_barrier.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_hi_1 = cat(hr_array_hi_hi_1, entries_barrier_3.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 524:60] node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 524:55] node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 524:111] node hr_array = cat(UInt<1>(0h1), _hr_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 524:21] node hw_array_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hw_array_lo = cat(hw_array_lo_hi, entries_barrier.io.y.hw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hw_array_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hw_array_hi = cat(hw_array_hi_hi, entries_barrier_3.io.y.hw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hw_array_T = cat(hw_array_hi, hw_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hw_array_T_1 = or(_hw_array_T, stage2_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 525:55] node hw_array = cat(UInt<1>(0h1), _hw_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 525:21] node hx_array_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hx_array_lo = cat(hx_array_lo_hi, entries_barrier.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hx_array_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hx_array_hi = cat(hx_array_hi_hi, entries_barrier_3.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hx_array_T = cat(hx_array_hi, hx_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hx_array_T_1 = or(_hx_array_T, stage2_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 526:55] node hx_array = cat(UInt<1>(0h1), _hx_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 526:21] node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 529:26] node pr_array_lo = cat(entries_barrier_1.io.y.pr, entries_barrier.io.y.pr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pr_array_hi_hi = cat(entries_barrier_4.io.y.pr, entries_barrier_3.io.y.pr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pr_array_hi = cat(pr_array_hi_hi, entries_barrier_2.io.y.pr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 529:21] node _pr_array_T_3 = or(ptw_ae_array, final_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 529:104] node _pr_array_T_4 = not(_pr_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 529:89] node pr_array = and(_pr_array_T_2, _pr_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 529:87] node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 531:26] node pw_array_lo = cat(entries_barrier_1.io.y.pw, entries_barrier.io.y.pw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pw_array_hi_hi = cat(entries_barrier_4.io.y.pw, entries_barrier_3.io.y.pw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pw_array_hi = cat(pw_array_hi_hi, entries_barrier_2.io.y.pw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 531:21] node _pw_array_T_3 = or(ptw_ae_array, final_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 531:104] node _pw_array_T_4 = not(_pw_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 531:89] node pw_array = and(_pw_array_T_2, _pw_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 531:87] node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 533:26] node px_array_lo = cat(entries_barrier_1.io.y.px, entries_barrier.io.y.px) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node px_array_hi_hi = cat(entries_barrier_4.io.y.px, entries_barrier_3.io.y.px) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node px_array_hi = cat(px_array_hi_hi, entries_barrier_2.io.y.px) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _px_array_T_1 = cat(px_array_hi, px_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 533:21] node _px_array_T_3 = or(ptw_ae_array, final_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 533:104] node _px_array_T_4 = not(_px_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 533:89] node px_array = and(_px_array_T_2, _px_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 533:87] node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 535:27] node eff_array_lo = cat(entries_barrier_1.io.y.eff, entries_barrier.io.y.eff) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node eff_array_hi_hi = cat(entries_barrier_4.io.y.eff, entries_barrier_3.io.y.eff) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node eff_array_hi = cat(eff_array_hi_hi, entries_barrier_2.io.y.eff) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node eff_array = cat(_eff_array_T, _eff_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 535:22] node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 537:25] node c_array_lo = cat(entries_barrier_1.io.y.c, entries_barrier.io.y.c) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node c_array_hi_hi = cat(entries_barrier_4.io.y.c, entries_barrier_3.io.y.c) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node c_array_hi = cat(c_array_hi_hi, entries_barrier_2.io.y.c) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _c_array_T_1 = cat(c_array_hi, c_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node c_array = cat(_c_array_T, _c_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 537:20] node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 539:27] node ppp_array_lo = cat(entries_barrier_1.io.y.ppp, entries_barrier.io.y.ppp) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ppp_array_hi_hi = cat(entries_barrier_4.io.y.ppp, entries_barrier_3.io.y.ppp) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ppp_array_hi = cat(ppp_array_hi_hi, entries_barrier_2.io.y.ppp) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ppp_array = cat(_ppp_array_T, _ppp_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 539:22] node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 541:27] node paa_array_lo = cat(entries_barrier_1.io.y.paa, entries_barrier.io.y.paa) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node paa_array_hi_hi = cat(entries_barrier_4.io.y.paa, entries_barrier_3.io.y.paa) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node paa_array_hi = cat(paa_array_hi_hi, entries_barrier_2.io.y.paa) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node paa_array = cat(_paa_array_T, _paa_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 541:22] node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 543:27] node pal_array_lo = cat(entries_barrier_1.io.y.pal, entries_barrier.io.y.pal) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pal_array_hi_hi = cat(entries_barrier_4.io.y.pal, entries_barrier_3.io.y.pal) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pal_array_hi = cat(pal_array_hi_hi, entries_barrier_2.io.y.pal) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pal_array = cat(_pal_array_T, _pal_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 543:22] node ppp_array_if_cached = or(ppp_array, c_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 544:39] node paa_array_if_cached = or(paa_array, c_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 545:39] node pal_array_if_cached = or(pal_array, c_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 546:39] node _prefetchable_array_T = and(cacheable, homogeneous) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 547:43] node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 547:59] node prefetchable_array_lo = cat(entries_barrier_1.io.y.c, entries_barrier.io.y.c) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node prefetchable_array_hi_hi = cat(entries_barrier_4.io.y.c, entries_barrier_3.io.y.c) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node prefetchable_array_hi = cat(prefetchable_array_hi_hi, entries_barrier_2.io.y.c) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 547:31] node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 550:69] node _misaligned_T_2 = tail(_misaligned_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 550:69] node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 550:39] node misaligned = orr(_misaligned_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 550:77] node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 570:33] node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 571:40] node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 572:43] node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 573:41] node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 89:68] node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 575:56] node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 575:37] node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:32] node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:49] node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:42] node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:66] node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:59] node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:76] node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 577:35] node lrscAllowed = mux(UInt<1>(0h1), UInt<1>(0h0), c_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 580:24] node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 582:8] node _ae_array_T_1 = not(lrscAllowed) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 583:19] node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 583:8] node ae_array = or(_ae_array_T, _ae_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 582:37] node _ae_ld_array_T = and(pr_array, px_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 586:71] node _ae_ld_array_T_1 = mux(cmd_readx, _ae_ld_array_T, pr_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 586:50] node _ae_ld_array_T_2 = not(_ae_ld_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 586:46] node _ae_ld_array_T_3 = or(ae_array, _ae_ld_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 586:44] node ae_ld_array = mux(cmd_read, _ae_ld_array_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 586:24] node _ae_st_array_T = not(pw_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 588:37] node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 588:35] node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 588:8] node _ae_st_array_T_3 = not(ppp_array_if_cached) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 589:26] node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 589:8] node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 588:53] node _ae_st_array_T_6 = not(pal_array_if_cached) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 590:26] node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 590:8] node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 589:53] node _ae_st_array_T_9 = not(paa_array_if_cached) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 591:29] node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 591:8] node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 590:53] node _must_alloc_array_T = not(ppp_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 593:26] node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 593:8] node _must_alloc_array_T_2 = not(pal_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 594:26] node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 594:8] node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 593:43] node _must_alloc_array_T_5 = not(paa_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 595:29] node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 595:8] node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 594:43] node _must_alloc_array_T_8 = not(UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 596:19] node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 596:8] node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 595:46] node _pf_ld_array_T = mux(cmd_readx, x_array, r_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:41] node _pf_ld_array_T_1 = not(_pf_ld_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:37] node _pf_ld_array_T_2 = not(ptw_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:73] node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:71] node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:88] node _pf_ld_array_T_5 = not(ptw_gf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:106] node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:104] node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:24] node _pf_st_array_T = not(w_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:44] node _pf_st_array_T_1 = not(ptw_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:55] node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:53] node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:70] node _pf_st_array_T_4 = not(ptw_gf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:88] node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:86] node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:24] node _pf_inst_array_T = not(x_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 599:25] node _pf_inst_array_T_1 = not(ptw_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 599:36] node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 599:34] node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 599:51] node _pf_inst_array_T_4 = not(ptw_gf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 599:69] node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 599:67] node _gf_ld_array_T = and(priv_v, cmd_read) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:32] node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:50] node _gf_ld_array_T_2 = not(_gf_ld_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:46] node _gf_ld_array_T_3 = not(ptw_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:84] node _gf_ld_array_T_4 = and(_gf_ld_array_T_2, _gf_ld_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:82] node _gf_ld_array_T_5 = or(_gf_ld_array_T_4, ptw_gf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:99] node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:24] node _gf_st_array_T = and(priv_v, cmd_write_perms) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 601:32] node _gf_st_array_T_1 = not(hw_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 601:53] node _gf_st_array_T_2 = not(ptw_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 601:65] node _gf_st_array_T_3 = and(_gf_st_array_T_1, _gf_st_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 601:63] node _gf_st_array_T_4 = or(_gf_st_array_T_3, ptw_gf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 601:80] node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 601:24] node _gf_inst_array_T = not(hx_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 602:36] node _gf_inst_array_T_1 = not(ptw_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 602:48] node _gf_inst_array_T_2 = and(_gf_inst_array_T, _gf_inst_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 602:46] node _gf_inst_array_T_3 = or(_gf_inst_array_T_2, ptw_gf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 602:63] node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 602:26] node gpa_hits_need_gpa_mask = or(gf_ld_array, gf_st_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 605:73] node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 606:73] node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 606:60] node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<5>(0h1f), UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 606:24] node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 606:107] node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<6>(0h3f), UInt<6>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 606:88] node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 606:82] node _gpa_hits_T = bits(gpa_hits_need_gpa_mask, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 607:30] node _gpa_hits_T_1 = not(_gpa_hits_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 607:16] node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 607:14] node tlb_hit_if_not_gpa_miss = orr(real_hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 610:43] node _tlb_hit_T = and(real_hits, gpa_hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 611:28] node tlb_hit = orr(_tlb_hit_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 611:40] node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 613:32] node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 613:29] node _tlb_miss_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 613:56] node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 613:53] node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 613:67] node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 613:64] reg state_reg : UInt<0>, clock @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 168:46] reg state_vec : UInt<0>[1], clock @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 304:30] regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 168:70] node _T_9 = and(io.req.valid, vm_enabled) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 617:22] when _T_9 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 617:37] when sector_hits_0 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 619:28] connect state_vec[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 308:20] node _T_10 = or(superpage_hits_0, superpage_hits_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_11 = or(_T_10, superpage_hits_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_12 = or(_T_11, superpage_hits_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] when _T_12 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 620:31] node lo = cat(superpage_hits_1, superpage_hits_0) @[src/main/scala/chisel3/util/OneHot.scala 21:45] node hi = cat(superpage_hits_3, superpage_hits_2) @[src/main/scala/chisel3/util/OneHot.scala 21:45] node _T_13 = cat(hi, lo) @[src/main/scala/chisel3/util/OneHot.scala 21:45] node hi_1 = bits(_T_13, 3, 2) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node lo_1 = bits(_T_13, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _T_14 = orr(hi_1) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _T_15 = or(hi_1, lo_1) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node _T_16 = bits(_T_15, 1, 1) @[src/main/scala/chisel3/util/CircuitMath.scala 28:8] node _T_17 = cat(_T_14, _T_16) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node state_reg_touch_way_sized = bits(_T_17, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:43] node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:33] node state_reg_left_subtree_state = bits(state_reg_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node state_reg_right_subtree_state = bits(state_reg_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 198:38] node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_T_1 = bits(_state_reg_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 203:16] node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 207:62] node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 206:16] node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] connect state_reg_1, _state_reg_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 172:15] node _multipleHits_T = bits(real_hits, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 181:37] node _multipleHits_T_1 = bits(_multipleHits_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 181:37] node multipleHits_leftOne = bits(_multipleHits_T_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 178:18] node _multipleHits_T_2 = bits(_multipleHits_T, 2, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 182:39] node _multipleHits_T_3 = bits(_multipleHits_T_2, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 181:37] node multipleHits_leftOne_1 = bits(_multipleHits_T_3, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 178:18] node _multipleHits_T_4 = bits(_multipleHits_T_2, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 182:39] node multipleHits_rightOne = bits(_multipleHits_T_4, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 178:18] node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:16] node _multipleHits_T_5 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:37] node _multipleHits_T_6 = and(multipleHits_leftOne_1, multipleHits_rightOne) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:61] node multipleHits_rightTwo = or(_multipleHits_T_5, _multipleHits_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:49] node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:16] node _multipleHits_T_7 = or(UInt<1>(0h0), multipleHits_rightTwo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:37] node _multipleHits_T_8 = and(multipleHits_leftOne, multipleHits_rightOne_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:61] node multipleHits_leftTwo = or(_multipleHits_T_7, _multipleHits_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:49] node _multipleHits_T_9 = bits(real_hits, 5, 3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 182:39] node _multipleHits_T_10 = bits(_multipleHits_T_9, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 181:37] node multipleHits_leftOne_3 = bits(_multipleHits_T_10, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 178:18] node _multipleHits_T_11 = bits(_multipleHits_T_9, 2, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 182:39] node _multipleHits_T_12 = bits(_multipleHits_T_11, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 181:37] node multipleHits_leftOne_4 = bits(_multipleHits_T_12, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 178:18] node _multipleHits_T_13 = bits(_multipleHits_T_11, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 182:39] node multipleHits_rightOne_2 = bits(_multipleHits_T_13, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 178:18] node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:16] node _multipleHits_T_14 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:37] node _multipleHits_T_15 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:61] node multipleHits_rightTwo_1 = or(_multipleHits_T_14, _multipleHits_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:49] node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:16] node _multipleHits_T_16 = or(UInt<1>(0h0), multipleHits_rightTwo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:37] node _multipleHits_T_17 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:61] node multipleHits_rightTwo_2 = or(_multipleHits_T_16, _multipleHits_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:49] node _multipleHits_T_18 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:16] node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:37] node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:61] node multipleHits = or(_multipleHits_T_19, _multipleHits_T_20) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:49] node _io_req_ready_T = eq(state, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 631:25] connect io.req.ready, _io_req_ready_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 631:16] node _io_resp_pf_ld_T = and(UInt<1>(0h0), cmd_read) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 633:28] node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 633:57] node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 633:65] node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 633:41] connect io.resp.pf.ld, _io_resp_pf_ld_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 633:17] node _io_resp_pf_st_T = and(UInt<1>(0h0), cmd_write_perms) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 634:28] node _io_resp_pf_st_T_1 = and(pf_st_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 634:64] node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 634:72] node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 634:48] connect io.resp.pf.st, _io_resp_pf_st_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 634:17] node _io_resp_pf_inst_T = and(pf_inst_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 635:47] node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 635:55] node _io_resp_pf_inst_T_2 = or(UInt<1>(0h0), _io_resp_pf_inst_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 635:29] connect io.resp.pf.inst, _io_resp_pf_inst_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 635:19] node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 637:29] node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 637:58] node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 637:66] node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 637:42] connect io.resp.gf.ld, _io_resp_gf_ld_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 637:17] node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 638:29] node _io_resp_gf_st_T_1 = and(gf_st_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 638:65] node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 638:73] node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 638:49] connect io.resp.gf.st, _io_resp_gf_st_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 638:17] node _io_resp_gf_inst_T = and(gf_inst_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 639:48] node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 639:56] node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 639:30] connect io.resp.gf.inst, _io_resp_gf_inst_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 639:19] node _io_resp_ae_ld_T = and(ae_ld_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 641:33] node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 641:41] connect io.resp.ae.ld, _io_resp_ae_ld_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 641:17] node _io_resp_ae_st_T = and(ae_st_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 642:33] node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 642:41] connect io.resp.ae.st, _io_resp_ae_st_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 642:17] node _io_resp_ae_inst_T = not(px_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 643:23] node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 643:33] node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 643:41] connect io.resp.ae.inst, _io_resp_ae_inst_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 643:19] node _io_resp_ma_ld_T = and(misaligned, cmd_read) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 645:31] connect io.resp.ma.ld, _io_resp_ma_ld_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 645:17] node _io_resp_ma_st_T = and(misaligned, cmd_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 646:31] connect io.resp.ma.st, _io_resp_ma_st_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 646:17] connect io.resp.ma.inst, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 647:19] node _io_resp_cacheable_T = and(c_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 648:33] node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 648:41] connect io.resp.cacheable, _io_resp_cacheable_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 648:21] node _io_resp_must_alloc_T = and(must_alloc_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 649:43] node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 649:51] connect io.resp.must_alloc, _io_resp_must_alloc_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 649:22] node _io_resp_prefetchable_T = and(prefetchable_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 650:47] node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 650:55] node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 650:59] connect io.resp.prefetchable, _io_resp_prefetchable_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 650:24] node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 651:29] node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 651:52] node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 651:64] connect io.resp.miss, _io_resp_miss_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 651:16] node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 652:46] node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 652:23] connect io.resp.paddr, _io_resp_paddr_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 652:17] connect io.resp.size, io.req.bits.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 653:16] connect io.resp.cmd, io.req.bits.cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 654:15] node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 655:36] connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 655:22] node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 657:20] node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 657:36] node _io_resp_gpa_page_T_2 = shr(r_gpa, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 657:58] node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 657:19] node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 658:47] node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 658:82] node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 658:21] node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 659:8] connect io.resp.gpa, _io_resp_gpa_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 656:15] node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 662:29] connect io.ptw.req.valid, _io_ptw_req_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 662:20] node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 663:28] connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 663:25] connect io.ptw.req.bits.bits.addr, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 664:29] connect io.ptw.req.bits.bits.vstage1, r_vstage1_en @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 665:32] connect io.ptw.req.bits.bits.stage2, r_stage2_en @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 666:31] connect io.ptw.req.bits.bits.need_gpa, r_need_gpa @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 667:33] module OptimizationBarrier_TLBEntryData_7 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module PMPChecker_s3_1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 143:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 143:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 143:7] output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 146:14] node default = gt(io.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 156:56] wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.mask, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.addr, UInt<30>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.cfg.r, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.cfg.w, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.cfg.x, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.cfg.a, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.cfg.res, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.cfg.l, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:22] connect pmp0, _pmp0_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:22] connect pmp0.cfg.r, default @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 158:14] connect pmp0.cfg.w, default @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 159:14] connect pmp0.cfg.x, default @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 160:14] node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_lsbMask_T = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_lsbMask_T_1 = bits(_res_hit_lsbMask_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_lsbMask_T_2 = not(_res_hit_lsbMask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node res_hit_lsbMask = or(io.pmp[7].mask, _res_hit_lsbMask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 68:26] node _res_hit_msbMatch_T = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:29] node _res_hit_msbMatch_T_1 = shl(io.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbMatch_T_2 = not(_res_hit_msbMatch_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbMatch_T_3 = or(_res_hit_msbMatch_T_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbMatch_T_4 = not(_res_hit_msbMatch_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbMatch_T_5 = shr(_res_hit_msbMatch_T_4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:53] node _res_hit_msbMatch_T_6 = shr(io.pmp[7].mask, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:72] node _res_hit_msbMatch_T_7 = xor(_res_hit_msbMatch_T, _res_hit_msbMatch_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_msbMatch_T_8 = not(_res_hit_msbMatch_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_msbMatch_T_9 = and(_res_hit_msbMatch_T_7, _res_hit_msbMatch_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_msbMatch = eq(_res_hit_msbMatch_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_lsbMatch_T = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:28] node _res_hit_lsbMatch_T_1 = shl(io.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbMatch_T_2 = not(_res_hit_lsbMatch_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbMatch_T_3 = or(_res_hit_lsbMatch_T_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbMatch_T_4 = not(_res_hit_lsbMatch_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbMatch_T_5 = bits(_res_hit_lsbMatch_T_4, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:55] node _res_hit_lsbMatch_T_6 = bits(res_hit_lsbMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:80] node _res_hit_lsbMatch_T_7 = xor(_res_hit_lsbMatch_T, _res_hit_lsbMatch_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_lsbMatch_T_8 = not(_res_hit_lsbMatch_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_lsbMatch_T_9 = and(_res_hit_lsbMatch_T_7, _res_hit_lsbMatch_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_lsbMatch = eq(_res_hit_lsbMatch_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_1 = and(res_hit_msbMatch, res_hit_lsbMatch) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 71:16] node _res_hit_T_2 = bits(io.pmp[7].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_3 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_4 = bits(_res_hit_T_3, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_5 = not(_res_hit_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_msbsLess_T = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_1 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_2 = not(_res_hit_msbsLess_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_3 = or(_res_hit_msbsLess_T_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_4 = not(_res_hit_msbsLess_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_5 = shr(_res_hit_msbsLess_T_4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess = lt(_res_hit_msbsLess_T, _res_hit_msbsLess_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_1 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_2 = not(_res_hit_msbsEqual_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_3 = or(_res_hit_msbsEqual_T_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_4 = not(_res_hit_msbsEqual_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_5 = shr(_res_hit_msbsEqual_T_4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_6 = xor(_res_hit_msbsEqual_T, _res_hit_msbsEqual_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual = eq(_res_hit_msbsEqual_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_1 = or(_res_hit_lsbsLess_T, _res_hit_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_2 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_3 = not(_res_hit_lsbsLess_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_4 = or(_res_hit_lsbsLess_T_3, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_5 = not(_res_hit_lsbsLess_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_6 = bits(_res_hit_lsbsLess_T_5, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess = lt(_res_hit_lsbsLess_T_1, _res_hit_lsbsLess_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_6 = and(res_hit_msbsEqual, res_hit_lsbsLess) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_7 = or(res_hit_msbsLess, _res_hit_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_msbsLess_T_6 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_7 = shl(io.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_8 = not(_res_hit_msbsLess_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_9 = or(_res_hit_msbsLess_T_8, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_10 = not(_res_hit_msbsLess_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_11 = shr(_res_hit_msbsLess_T_10, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_1 = lt(_res_hit_msbsLess_T_6, _res_hit_msbsLess_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_7 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_8 = shl(io.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_9 = not(_res_hit_msbsEqual_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_10 = or(_res_hit_msbsEqual_T_9, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_11 = not(_res_hit_msbsEqual_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_12 = shr(_res_hit_msbsEqual_T_11, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_13 = xor(_res_hit_msbsEqual_T_7, _res_hit_msbsEqual_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_1 = eq(_res_hit_msbsEqual_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_7 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_8 = or(_res_hit_lsbsLess_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_9 = shl(io.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_10 = not(_res_hit_lsbsLess_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_11 = or(_res_hit_lsbsLess_T_10, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_12 = not(_res_hit_lsbsLess_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_13 = bits(_res_hit_lsbsLess_T_12, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_1 = lt(_res_hit_lsbsLess_T_8, _res_hit_lsbsLess_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_9 = and(res_hit_msbsEqual_1, res_hit_lsbsLess_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_10 = or(res_hit_msbsLess_1, _res_hit_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_11 = and(_res_hit_T_8, _res_hit_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_12 = and(_res_hit_T_2, _res_hit_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit = mux(_res_hit_T, _res_hit_T_1, _res_hit_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore = and(default, _res_ignore_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_aligned_lsbMask_T = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_aligned_lsbMask_T_1 = bits(_res_aligned_lsbMask_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node res_aligned_lsbMask = not(_res_aligned_lsbMask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_aligned_straddlesLowerBound_T = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:35] node _res_aligned_straddlesLowerBound_T_1 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_2 = not(_res_aligned_straddlesLowerBound_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_3 = or(_res_aligned_straddlesLowerBound_T_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_4 = not(_res_aligned_straddlesLowerBound_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_5 = shr(_res_aligned_straddlesLowerBound_T_4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:67] node _res_aligned_straddlesLowerBound_T_6 = xor(_res_aligned_straddlesLowerBound_T, _res_aligned_straddlesLowerBound_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:49] node _res_aligned_straddlesLowerBound_T_7 = eq(_res_aligned_straddlesLowerBound_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:82] node _res_aligned_straddlesLowerBound_T_8 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_9 = not(_res_aligned_straddlesLowerBound_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_10 = or(_res_aligned_straddlesLowerBound_T_9, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_11 = not(_res_aligned_straddlesLowerBound_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_12 = bits(_res_aligned_straddlesLowerBound_T_11, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:108] node _res_aligned_straddlesLowerBound_T_13 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:129] node _res_aligned_straddlesLowerBound_T_14 = not(_res_aligned_straddlesLowerBound_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:127] node _res_aligned_straddlesLowerBound_T_15 = and(_res_aligned_straddlesLowerBound_T_12, _res_aligned_straddlesLowerBound_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:125] node _res_aligned_straddlesLowerBound_T_16 = neq(_res_aligned_straddlesLowerBound_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:147] node res_aligned_straddlesLowerBound = and(_res_aligned_straddlesLowerBound_T_7, _res_aligned_straddlesLowerBound_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:90] node _res_aligned_straddlesUpperBound_T = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:35] node _res_aligned_straddlesUpperBound_T_1 = shl(io.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_2 = not(_res_aligned_straddlesUpperBound_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_3 = or(_res_aligned_straddlesUpperBound_T_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_4 = not(_res_aligned_straddlesUpperBound_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_5 = shr(_res_aligned_straddlesUpperBound_T_4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:62] node _res_aligned_straddlesUpperBound_T_6 = xor(_res_aligned_straddlesUpperBound_T, _res_aligned_straddlesUpperBound_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:49] node _res_aligned_straddlesUpperBound_T_7 = eq(_res_aligned_straddlesUpperBound_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:77] node _res_aligned_straddlesUpperBound_T_8 = shl(io.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_9 = not(_res_aligned_straddlesUpperBound_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_10 = or(_res_aligned_straddlesUpperBound_T_9, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_11 = not(_res_aligned_straddlesUpperBound_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_12 = bits(_res_aligned_straddlesUpperBound_T_11, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:98] node _res_aligned_straddlesUpperBound_T_13 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:119] node _res_aligned_straddlesUpperBound_T_14 = or(_res_aligned_straddlesUpperBound_T_13, res_aligned_lsbMask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:136] node _res_aligned_straddlesUpperBound_T_15 = and(_res_aligned_straddlesUpperBound_T_12, _res_aligned_straddlesUpperBound_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:115] node _res_aligned_straddlesUpperBound_T_16 = neq(_res_aligned_straddlesUpperBound_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:148] node res_aligned_straddlesUpperBound = and(_res_aligned_straddlesUpperBound_T_7, _res_aligned_straddlesUpperBound_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:85] node _res_aligned_rangeAligned_T = or(res_aligned_straddlesLowerBound, res_aligned_straddlesUpperBound) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:46] node res_aligned_rangeAligned = eq(_res_aligned_rangeAligned_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:24] node _res_aligned_pow2Aligned_T = bits(io.pmp[7].mask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:39] node _res_aligned_pow2Aligned_T_1 = not(_res_aligned_pow2Aligned_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:34] node _res_aligned_pow2Aligned_T_2 = and(res_aligned_lsbMask, _res_aligned_pow2Aligned_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:32] node res_aligned_pow2Aligned = eq(_res_aligned_pow2Aligned_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:57] node _res_aligned_T = bits(io.pmp[7].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node res_aligned = mux(_res_aligned_T, res_aligned_pow2Aligned, res_aligned_rangeAligned) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 127:8] node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_6 = eq(_res_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_8 = eq(_res_T_7, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_10 = eq(_res_T_9, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_12 = eq(_res_T_11, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_14 = eq(_res_T_13, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_16 = eq(_res_T_15, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_17 = eq(res_ignore, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_18 = and(_res_T_17, res_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_19 = and(_res_T_18, res_aligned) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_21 = and(_res_T_19, _res_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_22 = and(io.pmp[7].cfg.l, res_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_23 = and(_res_T_22, res_aligned) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_25 = and(_res_T_23, _res_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_26 = eq(res_ignore, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_27 = and(_res_T_26, res_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_28 = and(_res_T_27, res_aligned) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_30 = and(_res_T_28, _res_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_31 = and(io.pmp[7].cfg.l, res_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_32 = and(_res_T_31, res_aligned) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_34 = and(_res_T_32, _res_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_35 = eq(res_ignore, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_36 = and(_res_T_35, res_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_37 = and(_res_T_36, res_aligned) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_39 = and(_res_T_37, _res_T_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_40 = and(io.pmp[7].cfg.l, res_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_41 = and(_res_T_40, res_aligned) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_43 = and(_res_T_41, _res_T_42) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur, io.pmp[7] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_1 = and(res_aligned, _res_cur_cfg_r_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur.cfg.r, _res_cur_cfg_r_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_1 = and(res_aligned, _res_cur_cfg_w_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur.cfg.w, _res_cur_cfg_w_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_1 = and(res_aligned, _res_cur_cfg_x_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur.cfg.x, _res_cur_cfg_x_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_44 = mux(res_hit, res_cur, pmp0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_13 = bits(io.pmp[6].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_lsbMask_T_3 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_lsbMask_T_4 = bits(_res_hit_lsbMask_T_3, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_lsbMask_T_5 = not(_res_hit_lsbMask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node res_hit_lsbMask_1 = or(io.pmp[6].mask, _res_hit_lsbMask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 68:26] node _res_hit_msbMatch_T_10 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:29] node _res_hit_msbMatch_T_11 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbMatch_T_12 = not(_res_hit_msbMatch_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbMatch_T_13 = or(_res_hit_msbMatch_T_12, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbMatch_T_14 = not(_res_hit_msbMatch_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbMatch_T_15 = shr(_res_hit_msbMatch_T_14, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:53] node _res_hit_msbMatch_T_16 = shr(io.pmp[6].mask, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:72] node _res_hit_msbMatch_T_17 = xor(_res_hit_msbMatch_T_10, _res_hit_msbMatch_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_msbMatch_T_18 = not(_res_hit_msbMatch_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_msbMatch_T_19 = and(_res_hit_msbMatch_T_17, _res_hit_msbMatch_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_msbMatch_1 = eq(_res_hit_msbMatch_T_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_lsbMatch_T_10 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:28] node _res_hit_lsbMatch_T_11 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbMatch_T_12 = not(_res_hit_lsbMatch_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbMatch_T_13 = or(_res_hit_lsbMatch_T_12, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbMatch_T_14 = not(_res_hit_lsbMatch_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbMatch_T_15 = bits(_res_hit_lsbMatch_T_14, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:55] node _res_hit_lsbMatch_T_16 = bits(res_hit_lsbMask_1, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:80] node _res_hit_lsbMatch_T_17 = xor(_res_hit_lsbMatch_T_10, _res_hit_lsbMatch_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_lsbMatch_T_18 = not(_res_hit_lsbMatch_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_lsbMatch_T_19 = and(_res_hit_lsbMatch_T_17, _res_hit_lsbMatch_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_lsbMatch_1 = eq(_res_hit_lsbMatch_T_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_14 = and(res_hit_msbMatch_1, res_hit_lsbMatch_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 71:16] node _res_hit_T_15 = bits(io.pmp[6].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_16 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_17 = bits(_res_hit_T_16, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_18 = not(_res_hit_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_msbsLess_T_12 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_13 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_14 = not(_res_hit_msbsLess_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_15 = or(_res_hit_msbsLess_T_14, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_16 = not(_res_hit_msbsLess_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_17 = shr(_res_hit_msbsLess_T_16, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_2 = lt(_res_hit_msbsLess_T_12, _res_hit_msbsLess_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_14 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_15 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_16 = not(_res_hit_msbsEqual_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_17 = or(_res_hit_msbsEqual_T_16, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_18 = not(_res_hit_msbsEqual_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_19 = shr(_res_hit_msbsEqual_T_18, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_20 = xor(_res_hit_msbsEqual_T_14, _res_hit_msbsEqual_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_2 = eq(_res_hit_msbsEqual_T_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_14 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_15 = or(_res_hit_lsbsLess_T_14, _res_hit_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_16 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_17 = not(_res_hit_lsbsLess_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_18 = or(_res_hit_lsbsLess_T_17, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_19 = not(_res_hit_lsbsLess_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_20 = bits(_res_hit_lsbsLess_T_19, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_2 = lt(_res_hit_lsbsLess_T_15, _res_hit_lsbsLess_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_19 = and(res_hit_msbsEqual_2, res_hit_lsbsLess_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_20 = or(res_hit_msbsLess_2, _res_hit_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_21 = eq(_res_hit_T_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_msbsLess_T_18 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_19 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_20 = not(_res_hit_msbsLess_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_21 = or(_res_hit_msbsLess_T_20, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_22 = not(_res_hit_msbsLess_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_23 = shr(_res_hit_msbsLess_T_22, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_3 = lt(_res_hit_msbsLess_T_18, _res_hit_msbsLess_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_21 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_22 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_23 = not(_res_hit_msbsEqual_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_24 = or(_res_hit_msbsEqual_T_23, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_25 = not(_res_hit_msbsEqual_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_26 = shr(_res_hit_msbsEqual_T_25, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_27 = xor(_res_hit_msbsEqual_T_21, _res_hit_msbsEqual_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_3 = eq(_res_hit_msbsEqual_T_27, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_21 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_22 = or(_res_hit_lsbsLess_T_21, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_23 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_24 = not(_res_hit_lsbsLess_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_25 = or(_res_hit_lsbsLess_T_24, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_26 = not(_res_hit_lsbsLess_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_27 = bits(_res_hit_lsbsLess_T_26, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_3 = lt(_res_hit_lsbsLess_T_22, _res_hit_lsbsLess_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_22 = and(res_hit_msbsEqual_3, res_hit_lsbsLess_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_23 = or(res_hit_msbsLess_3, _res_hit_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_24 = and(_res_hit_T_21, _res_hit_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_25 = and(_res_hit_T_15, _res_hit_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_1 = mux(_res_hit_T_13, _res_hit_T_14, _res_hit_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_1 = and(default, _res_ignore_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_aligned_lsbMask_T_2 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_aligned_lsbMask_T_3 = bits(_res_aligned_lsbMask_T_2, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node res_aligned_lsbMask_1 = not(_res_aligned_lsbMask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_aligned_straddlesLowerBound_T_17 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:35] node _res_aligned_straddlesLowerBound_T_18 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_19 = not(_res_aligned_straddlesLowerBound_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_20 = or(_res_aligned_straddlesLowerBound_T_19, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_21 = not(_res_aligned_straddlesLowerBound_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_22 = shr(_res_aligned_straddlesLowerBound_T_21, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:67] node _res_aligned_straddlesLowerBound_T_23 = xor(_res_aligned_straddlesLowerBound_T_17, _res_aligned_straddlesLowerBound_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:49] node _res_aligned_straddlesLowerBound_T_24 = eq(_res_aligned_straddlesLowerBound_T_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:82] node _res_aligned_straddlesLowerBound_T_25 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_26 = not(_res_aligned_straddlesLowerBound_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_27 = or(_res_aligned_straddlesLowerBound_T_26, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_28 = not(_res_aligned_straddlesLowerBound_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_29 = bits(_res_aligned_straddlesLowerBound_T_28, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:108] node _res_aligned_straddlesLowerBound_T_30 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:129] node _res_aligned_straddlesLowerBound_T_31 = not(_res_aligned_straddlesLowerBound_T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:127] node _res_aligned_straddlesLowerBound_T_32 = and(_res_aligned_straddlesLowerBound_T_29, _res_aligned_straddlesLowerBound_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:125] node _res_aligned_straddlesLowerBound_T_33 = neq(_res_aligned_straddlesLowerBound_T_32, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:147] node res_aligned_straddlesLowerBound_1 = and(_res_aligned_straddlesLowerBound_T_24, _res_aligned_straddlesLowerBound_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:90] node _res_aligned_straddlesUpperBound_T_17 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:35] node _res_aligned_straddlesUpperBound_T_18 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_19 = not(_res_aligned_straddlesUpperBound_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_20 = or(_res_aligned_straddlesUpperBound_T_19, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_21 = not(_res_aligned_straddlesUpperBound_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_22 = shr(_res_aligned_straddlesUpperBound_T_21, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:62] node _res_aligned_straddlesUpperBound_T_23 = xor(_res_aligned_straddlesUpperBound_T_17, _res_aligned_straddlesUpperBound_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:49] node _res_aligned_straddlesUpperBound_T_24 = eq(_res_aligned_straddlesUpperBound_T_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:77] node _res_aligned_straddlesUpperBound_T_25 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_26 = not(_res_aligned_straddlesUpperBound_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_27 = or(_res_aligned_straddlesUpperBound_T_26, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_28 = not(_res_aligned_straddlesUpperBound_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_29 = bits(_res_aligned_straddlesUpperBound_T_28, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:98] node _res_aligned_straddlesUpperBound_T_30 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:119] node _res_aligned_straddlesUpperBound_T_31 = or(_res_aligned_straddlesUpperBound_T_30, res_aligned_lsbMask_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:136] node _res_aligned_straddlesUpperBound_T_32 = and(_res_aligned_straddlesUpperBound_T_29, _res_aligned_straddlesUpperBound_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:115] node _res_aligned_straddlesUpperBound_T_33 = neq(_res_aligned_straddlesUpperBound_T_32, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:148] node res_aligned_straddlesUpperBound_1 = and(_res_aligned_straddlesUpperBound_T_24, _res_aligned_straddlesUpperBound_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:85] node _res_aligned_rangeAligned_T_1 = or(res_aligned_straddlesLowerBound_1, res_aligned_straddlesUpperBound_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:46] node res_aligned_rangeAligned_1 = eq(_res_aligned_rangeAligned_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:24] node _res_aligned_pow2Aligned_T_3 = bits(io.pmp[6].mask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:39] node _res_aligned_pow2Aligned_T_4 = not(_res_aligned_pow2Aligned_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:34] node _res_aligned_pow2Aligned_T_5 = and(res_aligned_lsbMask_1, _res_aligned_pow2Aligned_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:32] node res_aligned_pow2Aligned_1 = eq(_res_aligned_pow2Aligned_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:57] node _res_aligned_T_1 = bits(io.pmp[6].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node res_aligned_1 = mux(_res_aligned_T_1, res_aligned_pow2Aligned_1, res_aligned_rangeAligned_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 127:8] node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_51 = eq(_res_T_50, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_53 = eq(_res_T_52, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_55 = eq(_res_T_54, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_57 = eq(_res_T_56, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_59 = eq(_res_T_58, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_61 = eq(_res_T_60, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_63 = and(_res_T_62, res_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_64 = and(_res_T_63, res_aligned_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_66 = and(_res_T_64, _res_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_68 = and(_res_T_67, res_aligned_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_70 = and(_res_T_68, _res_T_69) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_72 = and(_res_T_71, res_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_73 = and(_res_T_72, res_aligned_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_75 = and(_res_T_73, _res_T_74) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_77 = and(_res_T_76, res_aligned_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_79 = and(_res_T_77, _res_T_78) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_81 = and(_res_T_80, res_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_82 = and(_res_T_81, res_aligned_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_84 = and(_res_T_82, _res_T_83) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_86 = and(_res_T_85, res_aligned_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_88 = and(_res_T_86, _res_T_87) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_1, io.pmp[6] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_3 = and(res_aligned_1, _res_cur_cfg_r_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_3 = and(res_aligned_1, _res_cur_cfg_w_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_3 = and(res_aligned_1, _res_cur_cfg_x_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_26 = bits(io.pmp[5].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_lsbMask_T_7 = bits(_res_hit_lsbMask_T_6, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_lsbMask_T_8 = not(_res_hit_lsbMask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node res_hit_lsbMask_2 = or(io.pmp[5].mask, _res_hit_lsbMask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 68:26] node _res_hit_msbMatch_T_20 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:29] node _res_hit_msbMatch_T_21 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbMatch_T_22 = not(_res_hit_msbMatch_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbMatch_T_23 = or(_res_hit_msbMatch_T_22, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbMatch_T_24 = not(_res_hit_msbMatch_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbMatch_T_25 = shr(_res_hit_msbMatch_T_24, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:53] node _res_hit_msbMatch_T_26 = shr(io.pmp[5].mask, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:72] node _res_hit_msbMatch_T_27 = xor(_res_hit_msbMatch_T_20, _res_hit_msbMatch_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_msbMatch_T_28 = not(_res_hit_msbMatch_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_msbMatch_T_29 = and(_res_hit_msbMatch_T_27, _res_hit_msbMatch_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_msbMatch_2 = eq(_res_hit_msbMatch_T_29, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_lsbMatch_T_20 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:28] node _res_hit_lsbMatch_T_21 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbMatch_T_22 = not(_res_hit_lsbMatch_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbMatch_T_23 = or(_res_hit_lsbMatch_T_22, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbMatch_T_24 = not(_res_hit_lsbMatch_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbMatch_T_25 = bits(_res_hit_lsbMatch_T_24, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:55] node _res_hit_lsbMatch_T_26 = bits(res_hit_lsbMask_2, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:80] node _res_hit_lsbMatch_T_27 = xor(_res_hit_lsbMatch_T_20, _res_hit_lsbMatch_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_lsbMatch_T_28 = not(_res_hit_lsbMatch_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_lsbMatch_T_29 = and(_res_hit_lsbMatch_T_27, _res_hit_lsbMatch_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_lsbMatch_2 = eq(_res_hit_lsbMatch_T_29, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_27 = and(res_hit_msbMatch_2, res_hit_lsbMatch_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 71:16] node _res_hit_T_28 = bits(io.pmp[5].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_29 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_30 = bits(_res_hit_T_29, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_31 = not(_res_hit_T_30) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_msbsLess_T_24 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_25 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_26 = not(_res_hit_msbsLess_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_27 = or(_res_hit_msbsLess_T_26, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_28 = not(_res_hit_msbsLess_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_29 = shr(_res_hit_msbsLess_T_28, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_4 = lt(_res_hit_msbsLess_T_24, _res_hit_msbsLess_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_28 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_29 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_30 = not(_res_hit_msbsEqual_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_31 = or(_res_hit_msbsEqual_T_30, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_32 = not(_res_hit_msbsEqual_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_33 = shr(_res_hit_msbsEqual_T_32, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_34 = xor(_res_hit_msbsEqual_T_28, _res_hit_msbsEqual_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_4 = eq(_res_hit_msbsEqual_T_34, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_28 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_29 = or(_res_hit_lsbsLess_T_28, _res_hit_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_30 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_31 = not(_res_hit_lsbsLess_T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_32 = or(_res_hit_lsbsLess_T_31, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_33 = not(_res_hit_lsbsLess_T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_34 = bits(_res_hit_lsbsLess_T_33, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_4 = lt(_res_hit_lsbsLess_T_29, _res_hit_lsbsLess_T_34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_32 = and(res_hit_msbsEqual_4, res_hit_lsbsLess_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_33 = or(res_hit_msbsLess_4, _res_hit_T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_msbsLess_T_30 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_31 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_32 = not(_res_hit_msbsLess_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_33 = or(_res_hit_msbsLess_T_32, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_34 = not(_res_hit_msbsLess_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_35 = shr(_res_hit_msbsLess_T_34, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_5 = lt(_res_hit_msbsLess_T_30, _res_hit_msbsLess_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_35 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_36 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_37 = not(_res_hit_msbsEqual_T_36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_38 = or(_res_hit_msbsEqual_T_37, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_39 = not(_res_hit_msbsEqual_T_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_40 = shr(_res_hit_msbsEqual_T_39, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_41 = xor(_res_hit_msbsEqual_T_35, _res_hit_msbsEqual_T_40) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_5 = eq(_res_hit_msbsEqual_T_41, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_35 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_36 = or(_res_hit_lsbsLess_T_35, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_37 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_38 = not(_res_hit_lsbsLess_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_39 = or(_res_hit_lsbsLess_T_38, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_40 = not(_res_hit_lsbsLess_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_41 = bits(_res_hit_lsbsLess_T_40, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_5 = lt(_res_hit_lsbsLess_T_36, _res_hit_lsbsLess_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_35 = and(res_hit_msbsEqual_5, res_hit_lsbsLess_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_36 = or(res_hit_msbsLess_5, _res_hit_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_37 = and(_res_hit_T_34, _res_hit_T_36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_38 = and(_res_hit_T_28, _res_hit_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_2 = mux(_res_hit_T_26, _res_hit_T_27, _res_hit_T_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_2 = and(default, _res_ignore_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_aligned_lsbMask_T_4 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_aligned_lsbMask_T_5 = bits(_res_aligned_lsbMask_T_4, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node res_aligned_lsbMask_2 = not(_res_aligned_lsbMask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_aligned_straddlesLowerBound_T_34 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:35] node _res_aligned_straddlesLowerBound_T_35 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_36 = not(_res_aligned_straddlesLowerBound_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_37 = or(_res_aligned_straddlesLowerBound_T_36, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_38 = not(_res_aligned_straddlesLowerBound_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_39 = shr(_res_aligned_straddlesLowerBound_T_38, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:67] node _res_aligned_straddlesLowerBound_T_40 = xor(_res_aligned_straddlesLowerBound_T_34, _res_aligned_straddlesLowerBound_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:49] node _res_aligned_straddlesLowerBound_T_41 = eq(_res_aligned_straddlesLowerBound_T_40, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:82] node _res_aligned_straddlesLowerBound_T_42 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_43 = not(_res_aligned_straddlesLowerBound_T_42) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_44 = or(_res_aligned_straddlesLowerBound_T_43, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_45 = not(_res_aligned_straddlesLowerBound_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_46 = bits(_res_aligned_straddlesLowerBound_T_45, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:108] node _res_aligned_straddlesLowerBound_T_47 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:129] node _res_aligned_straddlesLowerBound_T_48 = not(_res_aligned_straddlesLowerBound_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:127] node _res_aligned_straddlesLowerBound_T_49 = and(_res_aligned_straddlesLowerBound_T_46, _res_aligned_straddlesLowerBound_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:125] node _res_aligned_straddlesLowerBound_T_50 = neq(_res_aligned_straddlesLowerBound_T_49, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:147] node res_aligned_straddlesLowerBound_2 = and(_res_aligned_straddlesLowerBound_T_41, _res_aligned_straddlesLowerBound_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:90] node _res_aligned_straddlesUpperBound_T_34 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:35] node _res_aligned_straddlesUpperBound_T_35 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_36 = not(_res_aligned_straddlesUpperBound_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_37 = or(_res_aligned_straddlesUpperBound_T_36, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_38 = not(_res_aligned_straddlesUpperBound_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_39 = shr(_res_aligned_straddlesUpperBound_T_38, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:62] node _res_aligned_straddlesUpperBound_T_40 = xor(_res_aligned_straddlesUpperBound_T_34, _res_aligned_straddlesUpperBound_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:49] node _res_aligned_straddlesUpperBound_T_41 = eq(_res_aligned_straddlesUpperBound_T_40, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:77] node _res_aligned_straddlesUpperBound_T_42 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_43 = not(_res_aligned_straddlesUpperBound_T_42) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_44 = or(_res_aligned_straddlesUpperBound_T_43, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_45 = not(_res_aligned_straddlesUpperBound_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_46 = bits(_res_aligned_straddlesUpperBound_T_45, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:98] node _res_aligned_straddlesUpperBound_T_47 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:119] node _res_aligned_straddlesUpperBound_T_48 = or(_res_aligned_straddlesUpperBound_T_47, res_aligned_lsbMask_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:136] node _res_aligned_straddlesUpperBound_T_49 = and(_res_aligned_straddlesUpperBound_T_46, _res_aligned_straddlesUpperBound_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:115] node _res_aligned_straddlesUpperBound_T_50 = neq(_res_aligned_straddlesUpperBound_T_49, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:148] node res_aligned_straddlesUpperBound_2 = and(_res_aligned_straddlesUpperBound_T_41, _res_aligned_straddlesUpperBound_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:85] node _res_aligned_rangeAligned_T_2 = or(res_aligned_straddlesLowerBound_2, res_aligned_straddlesUpperBound_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:46] node res_aligned_rangeAligned_2 = eq(_res_aligned_rangeAligned_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:24] node _res_aligned_pow2Aligned_T_6 = bits(io.pmp[5].mask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:39] node _res_aligned_pow2Aligned_T_7 = not(_res_aligned_pow2Aligned_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:34] node _res_aligned_pow2Aligned_T_8 = and(res_aligned_lsbMask_2, _res_aligned_pow2Aligned_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:32] node res_aligned_pow2Aligned_2 = eq(_res_aligned_pow2Aligned_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:57] node _res_aligned_T_2 = bits(io.pmp[5].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node res_aligned_2 = mux(_res_aligned_T_2, res_aligned_pow2Aligned_2, res_aligned_rangeAligned_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 127:8] node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_96 = eq(_res_T_95, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_98 = eq(_res_T_97, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_100 = eq(_res_T_99, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_102 = eq(_res_T_101, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_104 = eq(_res_T_103, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_106 = eq(_res_T_105, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_108 = and(_res_T_107, res_hit_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_109 = and(_res_T_108, res_aligned_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_111 = and(_res_T_109, _res_T_110) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_113 = and(_res_T_112, res_aligned_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_115 = and(_res_T_113, _res_T_114) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_117 = and(_res_T_116, res_hit_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_118 = and(_res_T_117, res_aligned_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_120 = and(_res_T_118, _res_T_119) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_122 = and(_res_T_121, res_aligned_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_124 = and(_res_T_122, _res_T_123) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_126 = and(_res_T_125, res_hit_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_127 = and(_res_T_126, res_aligned_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_129 = and(_res_T_127, _res_T_128) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_131 = and(_res_T_130, res_aligned_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_133 = and(_res_T_131, _res_T_132) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_2, io.pmp[5] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_5 = and(res_aligned_2, _res_cur_cfg_r_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_5 = and(res_aligned_2, _res_cur_cfg_w_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_5 = and(res_aligned_2, _res_cur_cfg_x_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_39 = bits(io.pmp[4].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_lsbMask_T_9 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_lsbMask_T_10 = bits(_res_hit_lsbMask_T_9, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_lsbMask_T_11 = not(_res_hit_lsbMask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node res_hit_lsbMask_3 = or(io.pmp[4].mask, _res_hit_lsbMask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 68:26] node _res_hit_msbMatch_T_30 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:29] node _res_hit_msbMatch_T_31 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbMatch_T_32 = not(_res_hit_msbMatch_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbMatch_T_33 = or(_res_hit_msbMatch_T_32, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbMatch_T_34 = not(_res_hit_msbMatch_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbMatch_T_35 = shr(_res_hit_msbMatch_T_34, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:53] node _res_hit_msbMatch_T_36 = shr(io.pmp[4].mask, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:72] node _res_hit_msbMatch_T_37 = xor(_res_hit_msbMatch_T_30, _res_hit_msbMatch_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_msbMatch_T_38 = not(_res_hit_msbMatch_T_36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_msbMatch_T_39 = and(_res_hit_msbMatch_T_37, _res_hit_msbMatch_T_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_msbMatch_3 = eq(_res_hit_msbMatch_T_39, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_lsbMatch_T_30 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:28] node _res_hit_lsbMatch_T_31 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbMatch_T_32 = not(_res_hit_lsbMatch_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbMatch_T_33 = or(_res_hit_lsbMatch_T_32, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbMatch_T_34 = not(_res_hit_lsbMatch_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbMatch_T_35 = bits(_res_hit_lsbMatch_T_34, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:55] node _res_hit_lsbMatch_T_36 = bits(res_hit_lsbMask_3, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:80] node _res_hit_lsbMatch_T_37 = xor(_res_hit_lsbMatch_T_30, _res_hit_lsbMatch_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_lsbMatch_T_38 = not(_res_hit_lsbMatch_T_36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_lsbMatch_T_39 = and(_res_hit_lsbMatch_T_37, _res_hit_lsbMatch_T_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_lsbMatch_3 = eq(_res_hit_lsbMatch_T_39, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_40 = and(res_hit_msbMatch_3, res_hit_lsbMatch_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 71:16] node _res_hit_T_41 = bits(io.pmp[4].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_42 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_43 = bits(_res_hit_T_42, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_44 = not(_res_hit_T_43) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_msbsLess_T_36 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_37 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_38 = not(_res_hit_msbsLess_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_39 = or(_res_hit_msbsLess_T_38, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_40 = not(_res_hit_msbsLess_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_41 = shr(_res_hit_msbsLess_T_40, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_6 = lt(_res_hit_msbsLess_T_36, _res_hit_msbsLess_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_42 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_43 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_44 = not(_res_hit_msbsEqual_T_43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_45 = or(_res_hit_msbsEqual_T_44, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_46 = not(_res_hit_msbsEqual_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_47 = shr(_res_hit_msbsEqual_T_46, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_48 = xor(_res_hit_msbsEqual_T_42, _res_hit_msbsEqual_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_6 = eq(_res_hit_msbsEqual_T_48, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_42 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_43 = or(_res_hit_lsbsLess_T_42, _res_hit_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_44 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_45 = not(_res_hit_lsbsLess_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_46 = or(_res_hit_lsbsLess_T_45, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_47 = not(_res_hit_lsbsLess_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_48 = bits(_res_hit_lsbsLess_T_47, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_6 = lt(_res_hit_lsbsLess_T_43, _res_hit_lsbsLess_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_45 = and(res_hit_msbsEqual_6, res_hit_lsbsLess_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_46 = or(res_hit_msbsLess_6, _res_hit_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_47 = eq(_res_hit_T_46, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_msbsLess_T_42 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_43 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_44 = not(_res_hit_msbsLess_T_43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_45 = or(_res_hit_msbsLess_T_44, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_46 = not(_res_hit_msbsLess_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_47 = shr(_res_hit_msbsLess_T_46, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_7 = lt(_res_hit_msbsLess_T_42, _res_hit_msbsLess_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_49 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_50 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_51 = not(_res_hit_msbsEqual_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_52 = or(_res_hit_msbsEqual_T_51, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_53 = not(_res_hit_msbsEqual_T_52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_54 = shr(_res_hit_msbsEqual_T_53, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_55 = xor(_res_hit_msbsEqual_T_49, _res_hit_msbsEqual_T_54) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_7 = eq(_res_hit_msbsEqual_T_55, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_49 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_50 = or(_res_hit_lsbsLess_T_49, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_51 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_52 = not(_res_hit_lsbsLess_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_53 = or(_res_hit_lsbsLess_T_52, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_54 = not(_res_hit_lsbsLess_T_53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_55 = bits(_res_hit_lsbsLess_T_54, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_7 = lt(_res_hit_lsbsLess_T_50, _res_hit_lsbsLess_T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_48 = and(res_hit_msbsEqual_7, res_hit_lsbsLess_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_49 = or(res_hit_msbsLess_7, _res_hit_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_50 = and(_res_hit_T_47, _res_hit_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_51 = and(_res_hit_T_41, _res_hit_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_3 = mux(_res_hit_T_39, _res_hit_T_40, _res_hit_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_3 = and(default, _res_ignore_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_aligned_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_aligned_lsbMask_T_7 = bits(_res_aligned_lsbMask_T_6, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node res_aligned_lsbMask_3 = not(_res_aligned_lsbMask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_aligned_straddlesLowerBound_T_51 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:35] node _res_aligned_straddlesLowerBound_T_52 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_53 = not(_res_aligned_straddlesLowerBound_T_52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_54 = or(_res_aligned_straddlesLowerBound_T_53, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_55 = not(_res_aligned_straddlesLowerBound_T_54) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_56 = shr(_res_aligned_straddlesLowerBound_T_55, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:67] node _res_aligned_straddlesLowerBound_T_57 = xor(_res_aligned_straddlesLowerBound_T_51, _res_aligned_straddlesLowerBound_T_56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:49] node _res_aligned_straddlesLowerBound_T_58 = eq(_res_aligned_straddlesLowerBound_T_57, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:82] node _res_aligned_straddlesLowerBound_T_59 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_60 = not(_res_aligned_straddlesLowerBound_T_59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_61 = or(_res_aligned_straddlesLowerBound_T_60, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_62 = not(_res_aligned_straddlesLowerBound_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_63 = bits(_res_aligned_straddlesLowerBound_T_62, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:108] node _res_aligned_straddlesLowerBound_T_64 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:129] node _res_aligned_straddlesLowerBound_T_65 = not(_res_aligned_straddlesLowerBound_T_64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:127] node _res_aligned_straddlesLowerBound_T_66 = and(_res_aligned_straddlesLowerBound_T_63, _res_aligned_straddlesLowerBound_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:125] node _res_aligned_straddlesLowerBound_T_67 = neq(_res_aligned_straddlesLowerBound_T_66, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:147] node res_aligned_straddlesLowerBound_3 = and(_res_aligned_straddlesLowerBound_T_58, _res_aligned_straddlesLowerBound_T_67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:90] node _res_aligned_straddlesUpperBound_T_51 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:35] node _res_aligned_straddlesUpperBound_T_52 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_53 = not(_res_aligned_straddlesUpperBound_T_52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_54 = or(_res_aligned_straddlesUpperBound_T_53, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_55 = not(_res_aligned_straddlesUpperBound_T_54) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_56 = shr(_res_aligned_straddlesUpperBound_T_55, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:62] node _res_aligned_straddlesUpperBound_T_57 = xor(_res_aligned_straddlesUpperBound_T_51, _res_aligned_straddlesUpperBound_T_56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:49] node _res_aligned_straddlesUpperBound_T_58 = eq(_res_aligned_straddlesUpperBound_T_57, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:77] node _res_aligned_straddlesUpperBound_T_59 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_60 = not(_res_aligned_straddlesUpperBound_T_59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_61 = or(_res_aligned_straddlesUpperBound_T_60, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_62 = not(_res_aligned_straddlesUpperBound_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_63 = bits(_res_aligned_straddlesUpperBound_T_62, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:98] node _res_aligned_straddlesUpperBound_T_64 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:119] node _res_aligned_straddlesUpperBound_T_65 = or(_res_aligned_straddlesUpperBound_T_64, res_aligned_lsbMask_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:136] node _res_aligned_straddlesUpperBound_T_66 = and(_res_aligned_straddlesUpperBound_T_63, _res_aligned_straddlesUpperBound_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:115] node _res_aligned_straddlesUpperBound_T_67 = neq(_res_aligned_straddlesUpperBound_T_66, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:148] node res_aligned_straddlesUpperBound_3 = and(_res_aligned_straddlesUpperBound_T_58, _res_aligned_straddlesUpperBound_T_67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:85] node _res_aligned_rangeAligned_T_3 = or(res_aligned_straddlesLowerBound_3, res_aligned_straddlesUpperBound_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:46] node res_aligned_rangeAligned_3 = eq(_res_aligned_rangeAligned_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:24] node _res_aligned_pow2Aligned_T_9 = bits(io.pmp[4].mask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:39] node _res_aligned_pow2Aligned_T_10 = not(_res_aligned_pow2Aligned_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:34] node _res_aligned_pow2Aligned_T_11 = and(res_aligned_lsbMask_3, _res_aligned_pow2Aligned_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:32] node res_aligned_pow2Aligned_3 = eq(_res_aligned_pow2Aligned_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:57] node _res_aligned_T_3 = bits(io.pmp[4].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node res_aligned_3 = mux(_res_aligned_T_3, res_aligned_pow2Aligned_3, res_aligned_rangeAligned_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 127:8] node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_141 = eq(_res_T_140, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_143 = eq(_res_T_142, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_145 = eq(_res_T_144, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_147 = eq(_res_T_146, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_149 = eq(_res_T_148, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_151 = eq(_res_T_150, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_153 = and(_res_T_152, res_hit_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_154 = and(_res_T_153, res_aligned_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_156 = and(_res_T_154, _res_T_155) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_158 = and(_res_T_157, res_aligned_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_160 = and(_res_T_158, _res_T_159) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_162 = and(_res_T_161, res_hit_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_163 = and(_res_T_162, res_aligned_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_165 = and(_res_T_163, _res_T_164) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_167 = and(_res_T_166, res_aligned_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_169 = and(_res_T_167, _res_T_168) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_171 = and(_res_T_170, res_hit_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_172 = and(_res_T_171, res_aligned_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_174 = and(_res_T_172, _res_T_173) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_176 = and(_res_T_175, res_aligned_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_178 = and(_res_T_176, _res_T_177) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_3, io.pmp[4] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_7 = and(res_aligned_3, _res_cur_cfg_r_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_7 = and(res_aligned_3, _res_cur_cfg_w_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_7 = and(res_aligned_3, _res_cur_cfg_x_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_52 = bits(io.pmp[3].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_lsbMask_T_13 = bits(_res_hit_lsbMask_T_12, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_lsbMask_T_14 = not(_res_hit_lsbMask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node res_hit_lsbMask_4 = or(io.pmp[3].mask, _res_hit_lsbMask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 68:26] node _res_hit_msbMatch_T_40 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:29] node _res_hit_msbMatch_T_41 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbMatch_T_42 = not(_res_hit_msbMatch_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbMatch_T_43 = or(_res_hit_msbMatch_T_42, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbMatch_T_44 = not(_res_hit_msbMatch_T_43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbMatch_T_45 = shr(_res_hit_msbMatch_T_44, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:53] node _res_hit_msbMatch_T_46 = shr(io.pmp[3].mask, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:72] node _res_hit_msbMatch_T_47 = xor(_res_hit_msbMatch_T_40, _res_hit_msbMatch_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_msbMatch_T_48 = not(_res_hit_msbMatch_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_msbMatch_T_49 = and(_res_hit_msbMatch_T_47, _res_hit_msbMatch_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_msbMatch_4 = eq(_res_hit_msbMatch_T_49, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_lsbMatch_T_40 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:28] node _res_hit_lsbMatch_T_41 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbMatch_T_42 = not(_res_hit_lsbMatch_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbMatch_T_43 = or(_res_hit_lsbMatch_T_42, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbMatch_T_44 = not(_res_hit_lsbMatch_T_43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbMatch_T_45 = bits(_res_hit_lsbMatch_T_44, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:55] node _res_hit_lsbMatch_T_46 = bits(res_hit_lsbMask_4, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:80] node _res_hit_lsbMatch_T_47 = xor(_res_hit_lsbMatch_T_40, _res_hit_lsbMatch_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_lsbMatch_T_48 = not(_res_hit_lsbMatch_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_lsbMatch_T_49 = and(_res_hit_lsbMatch_T_47, _res_hit_lsbMatch_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_lsbMatch_4 = eq(_res_hit_lsbMatch_T_49, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_53 = and(res_hit_msbMatch_4, res_hit_lsbMatch_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 71:16] node _res_hit_T_54 = bits(io.pmp[3].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_55 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_56 = bits(_res_hit_T_55, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_57 = not(_res_hit_T_56) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_msbsLess_T_48 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_49 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_50 = not(_res_hit_msbsLess_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_51 = or(_res_hit_msbsLess_T_50, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_52 = not(_res_hit_msbsLess_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_53 = shr(_res_hit_msbsLess_T_52, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_8 = lt(_res_hit_msbsLess_T_48, _res_hit_msbsLess_T_53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_56 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_57 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_58 = not(_res_hit_msbsEqual_T_57) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_59 = or(_res_hit_msbsEqual_T_58, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_60 = not(_res_hit_msbsEqual_T_59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_61 = shr(_res_hit_msbsEqual_T_60, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_62 = xor(_res_hit_msbsEqual_T_56, _res_hit_msbsEqual_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_8 = eq(_res_hit_msbsEqual_T_62, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_56 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_57 = or(_res_hit_lsbsLess_T_56, _res_hit_T_57) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_58 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_59 = not(_res_hit_lsbsLess_T_58) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_60 = or(_res_hit_lsbsLess_T_59, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_61 = not(_res_hit_lsbsLess_T_60) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_62 = bits(_res_hit_lsbsLess_T_61, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_8 = lt(_res_hit_lsbsLess_T_57, _res_hit_lsbsLess_T_62) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_58 = and(res_hit_msbsEqual_8, res_hit_lsbsLess_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_59 = or(res_hit_msbsLess_8, _res_hit_T_58) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_msbsLess_T_54 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_55 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_56 = not(_res_hit_msbsLess_T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_57 = or(_res_hit_msbsLess_T_56, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_58 = not(_res_hit_msbsLess_T_57) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_59 = shr(_res_hit_msbsLess_T_58, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_9 = lt(_res_hit_msbsLess_T_54, _res_hit_msbsLess_T_59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_63 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_64 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_65 = not(_res_hit_msbsEqual_T_64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_66 = or(_res_hit_msbsEqual_T_65, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_67 = not(_res_hit_msbsEqual_T_66) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_68 = shr(_res_hit_msbsEqual_T_67, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_69 = xor(_res_hit_msbsEqual_T_63, _res_hit_msbsEqual_T_68) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_9 = eq(_res_hit_msbsEqual_T_69, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_63 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_64 = or(_res_hit_lsbsLess_T_63, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_65 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_66 = not(_res_hit_lsbsLess_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_67 = or(_res_hit_lsbsLess_T_66, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_68 = not(_res_hit_lsbsLess_T_67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_69 = bits(_res_hit_lsbsLess_T_68, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_9 = lt(_res_hit_lsbsLess_T_64, _res_hit_lsbsLess_T_69) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_61 = and(res_hit_msbsEqual_9, res_hit_lsbsLess_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_62 = or(res_hit_msbsLess_9, _res_hit_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_63 = and(_res_hit_T_60, _res_hit_T_62) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_64 = and(_res_hit_T_54, _res_hit_T_63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_4 = mux(_res_hit_T_52, _res_hit_T_53, _res_hit_T_64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_4 = and(default, _res_ignore_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_aligned_lsbMask_T_8 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_aligned_lsbMask_T_9 = bits(_res_aligned_lsbMask_T_8, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node res_aligned_lsbMask_4 = not(_res_aligned_lsbMask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_aligned_straddlesLowerBound_T_68 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:35] node _res_aligned_straddlesLowerBound_T_69 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_70 = not(_res_aligned_straddlesLowerBound_T_69) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_71 = or(_res_aligned_straddlesLowerBound_T_70, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_72 = not(_res_aligned_straddlesLowerBound_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_73 = shr(_res_aligned_straddlesLowerBound_T_72, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:67] node _res_aligned_straddlesLowerBound_T_74 = xor(_res_aligned_straddlesLowerBound_T_68, _res_aligned_straddlesLowerBound_T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:49] node _res_aligned_straddlesLowerBound_T_75 = eq(_res_aligned_straddlesLowerBound_T_74, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:82] node _res_aligned_straddlesLowerBound_T_76 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_77 = not(_res_aligned_straddlesLowerBound_T_76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_78 = or(_res_aligned_straddlesLowerBound_T_77, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_79 = not(_res_aligned_straddlesLowerBound_T_78) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_80 = bits(_res_aligned_straddlesLowerBound_T_79, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:108] node _res_aligned_straddlesLowerBound_T_81 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:129] node _res_aligned_straddlesLowerBound_T_82 = not(_res_aligned_straddlesLowerBound_T_81) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:127] node _res_aligned_straddlesLowerBound_T_83 = and(_res_aligned_straddlesLowerBound_T_80, _res_aligned_straddlesLowerBound_T_82) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:125] node _res_aligned_straddlesLowerBound_T_84 = neq(_res_aligned_straddlesLowerBound_T_83, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:147] node res_aligned_straddlesLowerBound_4 = and(_res_aligned_straddlesLowerBound_T_75, _res_aligned_straddlesLowerBound_T_84) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:90] node _res_aligned_straddlesUpperBound_T_68 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:35] node _res_aligned_straddlesUpperBound_T_69 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_70 = not(_res_aligned_straddlesUpperBound_T_69) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_71 = or(_res_aligned_straddlesUpperBound_T_70, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_72 = not(_res_aligned_straddlesUpperBound_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_73 = shr(_res_aligned_straddlesUpperBound_T_72, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:62] node _res_aligned_straddlesUpperBound_T_74 = xor(_res_aligned_straddlesUpperBound_T_68, _res_aligned_straddlesUpperBound_T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:49] node _res_aligned_straddlesUpperBound_T_75 = eq(_res_aligned_straddlesUpperBound_T_74, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:77] node _res_aligned_straddlesUpperBound_T_76 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_77 = not(_res_aligned_straddlesUpperBound_T_76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_78 = or(_res_aligned_straddlesUpperBound_T_77, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_79 = not(_res_aligned_straddlesUpperBound_T_78) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_80 = bits(_res_aligned_straddlesUpperBound_T_79, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:98] node _res_aligned_straddlesUpperBound_T_81 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:119] node _res_aligned_straddlesUpperBound_T_82 = or(_res_aligned_straddlesUpperBound_T_81, res_aligned_lsbMask_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:136] node _res_aligned_straddlesUpperBound_T_83 = and(_res_aligned_straddlesUpperBound_T_80, _res_aligned_straddlesUpperBound_T_82) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:115] node _res_aligned_straddlesUpperBound_T_84 = neq(_res_aligned_straddlesUpperBound_T_83, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:148] node res_aligned_straddlesUpperBound_4 = and(_res_aligned_straddlesUpperBound_T_75, _res_aligned_straddlesUpperBound_T_84) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:85] node _res_aligned_rangeAligned_T_4 = or(res_aligned_straddlesLowerBound_4, res_aligned_straddlesUpperBound_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:46] node res_aligned_rangeAligned_4 = eq(_res_aligned_rangeAligned_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:24] node _res_aligned_pow2Aligned_T_12 = bits(io.pmp[3].mask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:39] node _res_aligned_pow2Aligned_T_13 = not(_res_aligned_pow2Aligned_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:34] node _res_aligned_pow2Aligned_T_14 = and(res_aligned_lsbMask_4, _res_aligned_pow2Aligned_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:32] node res_aligned_pow2Aligned_4 = eq(_res_aligned_pow2Aligned_T_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:57] node _res_aligned_T_4 = bits(io.pmp[3].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node res_aligned_4 = mux(_res_aligned_T_4, res_aligned_pow2Aligned_4, res_aligned_rangeAligned_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 127:8] node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_186 = eq(_res_T_185, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_188 = eq(_res_T_187, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_190 = eq(_res_T_189, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_192 = eq(_res_T_191, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_194 = eq(_res_T_193, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_196 = eq(_res_T_195, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_198 = and(_res_T_197, res_hit_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_199 = and(_res_T_198, res_aligned_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_201 = and(_res_T_199, _res_T_200) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_203 = and(_res_T_202, res_aligned_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_205 = and(_res_T_203, _res_T_204) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_207 = and(_res_T_206, res_hit_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_208 = and(_res_T_207, res_aligned_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_210 = and(_res_T_208, _res_T_209) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_212 = and(_res_T_211, res_aligned_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_214 = and(_res_T_212, _res_T_213) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_216 = and(_res_T_215, res_hit_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_217 = and(_res_T_216, res_aligned_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_219 = and(_res_T_217, _res_T_218) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_221 = and(_res_T_220, res_aligned_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_223 = and(_res_T_221, _res_T_222) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_4, io.pmp[3] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_9 = and(res_aligned_4, _res_cur_cfg_r_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_9 = and(res_aligned_4, _res_cur_cfg_w_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_9 = and(res_aligned_4, _res_cur_cfg_x_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_65 = bits(io.pmp[2].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_lsbMask_T_15 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_lsbMask_T_16 = bits(_res_hit_lsbMask_T_15, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_lsbMask_T_17 = not(_res_hit_lsbMask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node res_hit_lsbMask_5 = or(io.pmp[2].mask, _res_hit_lsbMask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 68:26] node _res_hit_msbMatch_T_50 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:29] node _res_hit_msbMatch_T_51 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbMatch_T_52 = not(_res_hit_msbMatch_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbMatch_T_53 = or(_res_hit_msbMatch_T_52, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbMatch_T_54 = not(_res_hit_msbMatch_T_53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbMatch_T_55 = shr(_res_hit_msbMatch_T_54, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:53] node _res_hit_msbMatch_T_56 = shr(io.pmp[2].mask, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:72] node _res_hit_msbMatch_T_57 = xor(_res_hit_msbMatch_T_50, _res_hit_msbMatch_T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_msbMatch_T_58 = not(_res_hit_msbMatch_T_56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_msbMatch_T_59 = and(_res_hit_msbMatch_T_57, _res_hit_msbMatch_T_58) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_msbMatch_5 = eq(_res_hit_msbMatch_T_59, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_lsbMatch_T_50 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:28] node _res_hit_lsbMatch_T_51 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbMatch_T_52 = not(_res_hit_lsbMatch_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbMatch_T_53 = or(_res_hit_lsbMatch_T_52, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbMatch_T_54 = not(_res_hit_lsbMatch_T_53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbMatch_T_55 = bits(_res_hit_lsbMatch_T_54, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:55] node _res_hit_lsbMatch_T_56 = bits(res_hit_lsbMask_5, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:80] node _res_hit_lsbMatch_T_57 = xor(_res_hit_lsbMatch_T_50, _res_hit_lsbMatch_T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_lsbMatch_T_58 = not(_res_hit_lsbMatch_T_56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_lsbMatch_T_59 = and(_res_hit_lsbMatch_T_57, _res_hit_lsbMatch_T_58) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_lsbMatch_5 = eq(_res_hit_lsbMatch_T_59, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_66 = and(res_hit_msbMatch_5, res_hit_lsbMatch_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 71:16] node _res_hit_T_67 = bits(io.pmp[2].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_68 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_69 = bits(_res_hit_T_68, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_70 = not(_res_hit_T_69) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_msbsLess_T_60 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_61 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_62 = not(_res_hit_msbsLess_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_63 = or(_res_hit_msbsLess_T_62, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_64 = not(_res_hit_msbsLess_T_63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_65 = shr(_res_hit_msbsLess_T_64, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_10 = lt(_res_hit_msbsLess_T_60, _res_hit_msbsLess_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_70 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_71 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_72 = not(_res_hit_msbsEqual_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_73 = or(_res_hit_msbsEqual_T_72, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_74 = not(_res_hit_msbsEqual_T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_75 = shr(_res_hit_msbsEqual_T_74, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_76 = xor(_res_hit_msbsEqual_T_70, _res_hit_msbsEqual_T_75) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_10 = eq(_res_hit_msbsEqual_T_76, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_70 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_71 = or(_res_hit_lsbsLess_T_70, _res_hit_T_70) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_72 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_73 = not(_res_hit_lsbsLess_T_72) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_74 = or(_res_hit_lsbsLess_T_73, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_75 = not(_res_hit_lsbsLess_T_74) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_76 = bits(_res_hit_lsbsLess_T_75, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_10 = lt(_res_hit_lsbsLess_T_71, _res_hit_lsbsLess_T_76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_71 = and(res_hit_msbsEqual_10, res_hit_lsbsLess_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_72 = or(res_hit_msbsLess_10, _res_hit_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_73 = eq(_res_hit_T_72, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_msbsLess_T_66 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_67 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_68 = not(_res_hit_msbsLess_T_67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_69 = or(_res_hit_msbsLess_T_68, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_70 = not(_res_hit_msbsLess_T_69) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_71 = shr(_res_hit_msbsLess_T_70, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_11 = lt(_res_hit_msbsLess_T_66, _res_hit_msbsLess_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_77 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_78 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_79 = not(_res_hit_msbsEqual_T_78) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_80 = or(_res_hit_msbsEqual_T_79, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_81 = not(_res_hit_msbsEqual_T_80) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_82 = shr(_res_hit_msbsEqual_T_81, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_83 = xor(_res_hit_msbsEqual_T_77, _res_hit_msbsEqual_T_82) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_11 = eq(_res_hit_msbsEqual_T_83, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_77 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_78 = or(_res_hit_lsbsLess_T_77, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_79 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_80 = not(_res_hit_lsbsLess_T_79) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_81 = or(_res_hit_lsbsLess_T_80, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_82 = not(_res_hit_lsbsLess_T_81) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_83 = bits(_res_hit_lsbsLess_T_82, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_11 = lt(_res_hit_lsbsLess_T_78, _res_hit_lsbsLess_T_83) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_74 = and(res_hit_msbsEqual_11, res_hit_lsbsLess_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_75 = or(res_hit_msbsLess_11, _res_hit_T_74) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_76 = and(_res_hit_T_73, _res_hit_T_75) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_77 = and(_res_hit_T_67, _res_hit_T_76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_5 = mux(_res_hit_T_65, _res_hit_T_66, _res_hit_T_77) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_5 = and(default, _res_ignore_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_aligned_lsbMask_T_10 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_aligned_lsbMask_T_11 = bits(_res_aligned_lsbMask_T_10, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node res_aligned_lsbMask_5 = not(_res_aligned_lsbMask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_aligned_straddlesLowerBound_T_85 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:35] node _res_aligned_straddlesLowerBound_T_86 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_87 = not(_res_aligned_straddlesLowerBound_T_86) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_88 = or(_res_aligned_straddlesLowerBound_T_87, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_89 = not(_res_aligned_straddlesLowerBound_T_88) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_90 = shr(_res_aligned_straddlesLowerBound_T_89, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:67] node _res_aligned_straddlesLowerBound_T_91 = xor(_res_aligned_straddlesLowerBound_T_85, _res_aligned_straddlesLowerBound_T_90) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:49] node _res_aligned_straddlesLowerBound_T_92 = eq(_res_aligned_straddlesLowerBound_T_91, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:82] node _res_aligned_straddlesLowerBound_T_93 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_94 = not(_res_aligned_straddlesLowerBound_T_93) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_95 = or(_res_aligned_straddlesLowerBound_T_94, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_96 = not(_res_aligned_straddlesLowerBound_T_95) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_97 = bits(_res_aligned_straddlesLowerBound_T_96, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:108] node _res_aligned_straddlesLowerBound_T_98 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:129] node _res_aligned_straddlesLowerBound_T_99 = not(_res_aligned_straddlesLowerBound_T_98) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:127] node _res_aligned_straddlesLowerBound_T_100 = and(_res_aligned_straddlesLowerBound_T_97, _res_aligned_straddlesLowerBound_T_99) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:125] node _res_aligned_straddlesLowerBound_T_101 = neq(_res_aligned_straddlesLowerBound_T_100, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:147] node res_aligned_straddlesLowerBound_5 = and(_res_aligned_straddlesLowerBound_T_92, _res_aligned_straddlesLowerBound_T_101) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:90] node _res_aligned_straddlesUpperBound_T_85 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:35] node _res_aligned_straddlesUpperBound_T_86 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_87 = not(_res_aligned_straddlesUpperBound_T_86) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_88 = or(_res_aligned_straddlesUpperBound_T_87, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_89 = not(_res_aligned_straddlesUpperBound_T_88) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_90 = shr(_res_aligned_straddlesUpperBound_T_89, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:62] node _res_aligned_straddlesUpperBound_T_91 = xor(_res_aligned_straddlesUpperBound_T_85, _res_aligned_straddlesUpperBound_T_90) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:49] node _res_aligned_straddlesUpperBound_T_92 = eq(_res_aligned_straddlesUpperBound_T_91, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:77] node _res_aligned_straddlesUpperBound_T_93 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_94 = not(_res_aligned_straddlesUpperBound_T_93) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_95 = or(_res_aligned_straddlesUpperBound_T_94, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_96 = not(_res_aligned_straddlesUpperBound_T_95) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_97 = bits(_res_aligned_straddlesUpperBound_T_96, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:98] node _res_aligned_straddlesUpperBound_T_98 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:119] node _res_aligned_straddlesUpperBound_T_99 = or(_res_aligned_straddlesUpperBound_T_98, res_aligned_lsbMask_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:136] node _res_aligned_straddlesUpperBound_T_100 = and(_res_aligned_straddlesUpperBound_T_97, _res_aligned_straddlesUpperBound_T_99) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:115] node _res_aligned_straddlesUpperBound_T_101 = neq(_res_aligned_straddlesUpperBound_T_100, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:148] node res_aligned_straddlesUpperBound_5 = and(_res_aligned_straddlesUpperBound_T_92, _res_aligned_straddlesUpperBound_T_101) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:85] node _res_aligned_rangeAligned_T_5 = or(res_aligned_straddlesLowerBound_5, res_aligned_straddlesUpperBound_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:46] node res_aligned_rangeAligned_5 = eq(_res_aligned_rangeAligned_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:24] node _res_aligned_pow2Aligned_T_15 = bits(io.pmp[2].mask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:39] node _res_aligned_pow2Aligned_T_16 = not(_res_aligned_pow2Aligned_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:34] node _res_aligned_pow2Aligned_T_17 = and(res_aligned_lsbMask_5, _res_aligned_pow2Aligned_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:32] node res_aligned_pow2Aligned_5 = eq(_res_aligned_pow2Aligned_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:57] node _res_aligned_T_5 = bits(io.pmp[2].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node res_aligned_5 = mux(_res_aligned_T_5, res_aligned_pow2Aligned_5, res_aligned_rangeAligned_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 127:8] node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_231 = eq(_res_T_230, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_233 = eq(_res_T_232, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_235 = eq(_res_T_234, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_237 = eq(_res_T_236, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_239 = eq(_res_T_238, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_241 = eq(_res_T_240, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_243 = and(_res_T_242, res_hit_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_244 = and(_res_T_243, res_aligned_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_246 = and(_res_T_244, _res_T_245) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_248 = and(_res_T_247, res_aligned_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_250 = and(_res_T_248, _res_T_249) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_252 = and(_res_T_251, res_hit_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_253 = and(_res_T_252, res_aligned_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_255 = and(_res_T_253, _res_T_254) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_257 = and(_res_T_256, res_aligned_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_259 = and(_res_T_257, _res_T_258) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_261 = and(_res_T_260, res_hit_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_262 = and(_res_T_261, res_aligned_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_264 = and(_res_T_262, _res_T_263) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_266 = and(_res_T_265, res_aligned_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_268 = and(_res_T_266, _res_T_267) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_5, io.pmp[2] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_11 = and(res_aligned_5, _res_cur_cfg_r_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_11 = and(res_aligned_5, _res_cur_cfg_w_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_11 = and(res_aligned_5, _res_cur_cfg_x_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_78 = bits(io.pmp[1].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_lsbMask_T_18 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_lsbMask_T_19 = bits(_res_hit_lsbMask_T_18, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_lsbMask_T_20 = not(_res_hit_lsbMask_T_19) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node res_hit_lsbMask_6 = or(io.pmp[1].mask, _res_hit_lsbMask_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 68:26] node _res_hit_msbMatch_T_60 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:29] node _res_hit_msbMatch_T_61 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbMatch_T_62 = not(_res_hit_msbMatch_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbMatch_T_63 = or(_res_hit_msbMatch_T_62, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbMatch_T_64 = not(_res_hit_msbMatch_T_63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbMatch_T_65 = shr(_res_hit_msbMatch_T_64, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:53] node _res_hit_msbMatch_T_66 = shr(io.pmp[1].mask, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:72] node _res_hit_msbMatch_T_67 = xor(_res_hit_msbMatch_T_60, _res_hit_msbMatch_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_msbMatch_T_68 = not(_res_hit_msbMatch_T_66) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_msbMatch_T_69 = and(_res_hit_msbMatch_T_67, _res_hit_msbMatch_T_68) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_msbMatch_6 = eq(_res_hit_msbMatch_T_69, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_lsbMatch_T_60 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:28] node _res_hit_lsbMatch_T_61 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbMatch_T_62 = not(_res_hit_lsbMatch_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbMatch_T_63 = or(_res_hit_lsbMatch_T_62, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbMatch_T_64 = not(_res_hit_lsbMatch_T_63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbMatch_T_65 = bits(_res_hit_lsbMatch_T_64, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:55] node _res_hit_lsbMatch_T_66 = bits(res_hit_lsbMask_6, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:80] node _res_hit_lsbMatch_T_67 = xor(_res_hit_lsbMatch_T_60, _res_hit_lsbMatch_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_lsbMatch_T_68 = not(_res_hit_lsbMatch_T_66) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_lsbMatch_T_69 = and(_res_hit_lsbMatch_T_67, _res_hit_lsbMatch_T_68) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_lsbMatch_6 = eq(_res_hit_lsbMatch_T_69, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_79 = and(res_hit_msbMatch_6, res_hit_lsbMatch_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 71:16] node _res_hit_T_80 = bits(io.pmp[1].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_81 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_82 = bits(_res_hit_T_81, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_83 = not(_res_hit_T_82) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_msbsLess_T_72 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_73 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_74 = not(_res_hit_msbsLess_T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_75 = or(_res_hit_msbsLess_T_74, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_76 = not(_res_hit_msbsLess_T_75) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_77 = shr(_res_hit_msbsLess_T_76, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_12 = lt(_res_hit_msbsLess_T_72, _res_hit_msbsLess_T_77) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_84 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_85 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_86 = not(_res_hit_msbsEqual_T_85) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_87 = or(_res_hit_msbsEqual_T_86, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_88 = not(_res_hit_msbsEqual_T_87) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_89 = shr(_res_hit_msbsEqual_T_88, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_90 = xor(_res_hit_msbsEqual_T_84, _res_hit_msbsEqual_T_89) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_12 = eq(_res_hit_msbsEqual_T_90, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_84 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_85 = or(_res_hit_lsbsLess_T_84, _res_hit_T_83) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_86 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_87 = not(_res_hit_lsbsLess_T_86) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_88 = or(_res_hit_lsbsLess_T_87, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_89 = not(_res_hit_lsbsLess_T_88) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_90 = bits(_res_hit_lsbsLess_T_89, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_12 = lt(_res_hit_lsbsLess_T_85, _res_hit_lsbsLess_T_90) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_84 = and(res_hit_msbsEqual_12, res_hit_lsbsLess_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_85 = or(res_hit_msbsLess_12, _res_hit_T_84) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_msbsLess_T_78 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_79 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_80 = not(_res_hit_msbsLess_T_79) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_81 = or(_res_hit_msbsLess_T_80, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_82 = not(_res_hit_msbsLess_T_81) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_83 = shr(_res_hit_msbsLess_T_82, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_13 = lt(_res_hit_msbsLess_T_78, _res_hit_msbsLess_T_83) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_91 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_92 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_93 = not(_res_hit_msbsEqual_T_92) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_94 = or(_res_hit_msbsEqual_T_93, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_95 = not(_res_hit_msbsEqual_T_94) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_96 = shr(_res_hit_msbsEqual_T_95, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_97 = xor(_res_hit_msbsEqual_T_91, _res_hit_msbsEqual_T_96) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_13 = eq(_res_hit_msbsEqual_T_97, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_91 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_92 = or(_res_hit_lsbsLess_T_91, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_93 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_94 = not(_res_hit_lsbsLess_T_93) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_95 = or(_res_hit_lsbsLess_T_94, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_96 = not(_res_hit_lsbsLess_T_95) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_97 = bits(_res_hit_lsbsLess_T_96, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_13 = lt(_res_hit_lsbsLess_T_92, _res_hit_lsbsLess_T_97) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_87 = and(res_hit_msbsEqual_13, res_hit_lsbsLess_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_88 = or(res_hit_msbsLess_13, _res_hit_T_87) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_89 = and(_res_hit_T_86, _res_hit_T_88) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_90 = and(_res_hit_T_80, _res_hit_T_89) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_6 = mux(_res_hit_T_78, _res_hit_T_79, _res_hit_T_90) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_6 = and(default, _res_ignore_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_aligned_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_aligned_lsbMask_T_13 = bits(_res_aligned_lsbMask_T_12, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node res_aligned_lsbMask_6 = not(_res_aligned_lsbMask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_aligned_straddlesLowerBound_T_102 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:35] node _res_aligned_straddlesLowerBound_T_103 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_104 = not(_res_aligned_straddlesLowerBound_T_103) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_105 = or(_res_aligned_straddlesLowerBound_T_104, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_106 = not(_res_aligned_straddlesLowerBound_T_105) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_107 = shr(_res_aligned_straddlesLowerBound_T_106, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:67] node _res_aligned_straddlesLowerBound_T_108 = xor(_res_aligned_straddlesLowerBound_T_102, _res_aligned_straddlesLowerBound_T_107) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:49] node _res_aligned_straddlesLowerBound_T_109 = eq(_res_aligned_straddlesLowerBound_T_108, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:82] node _res_aligned_straddlesLowerBound_T_110 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_111 = not(_res_aligned_straddlesLowerBound_T_110) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_112 = or(_res_aligned_straddlesLowerBound_T_111, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_113 = not(_res_aligned_straddlesLowerBound_T_112) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_114 = bits(_res_aligned_straddlesLowerBound_T_113, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:108] node _res_aligned_straddlesLowerBound_T_115 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:129] node _res_aligned_straddlesLowerBound_T_116 = not(_res_aligned_straddlesLowerBound_T_115) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:127] node _res_aligned_straddlesLowerBound_T_117 = and(_res_aligned_straddlesLowerBound_T_114, _res_aligned_straddlesLowerBound_T_116) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:125] node _res_aligned_straddlesLowerBound_T_118 = neq(_res_aligned_straddlesLowerBound_T_117, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:147] node res_aligned_straddlesLowerBound_6 = and(_res_aligned_straddlesLowerBound_T_109, _res_aligned_straddlesLowerBound_T_118) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:90] node _res_aligned_straddlesUpperBound_T_102 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:35] node _res_aligned_straddlesUpperBound_T_103 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_104 = not(_res_aligned_straddlesUpperBound_T_103) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_105 = or(_res_aligned_straddlesUpperBound_T_104, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_106 = not(_res_aligned_straddlesUpperBound_T_105) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_107 = shr(_res_aligned_straddlesUpperBound_T_106, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:62] node _res_aligned_straddlesUpperBound_T_108 = xor(_res_aligned_straddlesUpperBound_T_102, _res_aligned_straddlesUpperBound_T_107) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:49] node _res_aligned_straddlesUpperBound_T_109 = eq(_res_aligned_straddlesUpperBound_T_108, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:77] node _res_aligned_straddlesUpperBound_T_110 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_111 = not(_res_aligned_straddlesUpperBound_T_110) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_112 = or(_res_aligned_straddlesUpperBound_T_111, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_113 = not(_res_aligned_straddlesUpperBound_T_112) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_114 = bits(_res_aligned_straddlesUpperBound_T_113, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:98] node _res_aligned_straddlesUpperBound_T_115 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:119] node _res_aligned_straddlesUpperBound_T_116 = or(_res_aligned_straddlesUpperBound_T_115, res_aligned_lsbMask_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:136] node _res_aligned_straddlesUpperBound_T_117 = and(_res_aligned_straddlesUpperBound_T_114, _res_aligned_straddlesUpperBound_T_116) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:115] node _res_aligned_straddlesUpperBound_T_118 = neq(_res_aligned_straddlesUpperBound_T_117, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:148] node res_aligned_straddlesUpperBound_6 = and(_res_aligned_straddlesUpperBound_T_109, _res_aligned_straddlesUpperBound_T_118) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:85] node _res_aligned_rangeAligned_T_6 = or(res_aligned_straddlesLowerBound_6, res_aligned_straddlesUpperBound_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:46] node res_aligned_rangeAligned_6 = eq(_res_aligned_rangeAligned_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:24] node _res_aligned_pow2Aligned_T_18 = bits(io.pmp[1].mask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:39] node _res_aligned_pow2Aligned_T_19 = not(_res_aligned_pow2Aligned_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:34] node _res_aligned_pow2Aligned_T_20 = and(res_aligned_lsbMask_6, _res_aligned_pow2Aligned_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:32] node res_aligned_pow2Aligned_6 = eq(_res_aligned_pow2Aligned_T_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:57] node _res_aligned_T_6 = bits(io.pmp[1].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node res_aligned_6 = mux(_res_aligned_T_6, res_aligned_pow2Aligned_6, res_aligned_rangeAligned_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 127:8] node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_276 = eq(_res_T_275, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_278 = eq(_res_T_277, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_280 = eq(_res_T_279, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_282 = eq(_res_T_281, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_284 = eq(_res_T_283, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_286 = eq(_res_T_285, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_288 = and(_res_T_287, res_hit_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_289 = and(_res_T_288, res_aligned_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_291 = and(_res_T_289, _res_T_290) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_293 = and(_res_T_292, res_aligned_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_295 = and(_res_T_293, _res_T_294) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_297 = and(_res_T_296, res_hit_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_298 = and(_res_T_297, res_aligned_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_300 = and(_res_T_298, _res_T_299) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_302 = and(_res_T_301, res_aligned_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_304 = and(_res_T_302, _res_T_303) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_306 = and(_res_T_305, res_hit_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_307 = and(_res_T_306, res_aligned_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_309 = and(_res_T_307, _res_T_308) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_311 = and(_res_T_310, res_aligned_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_313 = and(_res_T_311, _res_T_312) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_6, io.pmp[1] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_13 = and(res_aligned_6, _res_cur_cfg_r_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_13 = and(res_aligned_6, _res_cur_cfg_w_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_13 = and(res_aligned_6, _res_cur_cfg_x_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_91 = bits(io.pmp[0].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_lsbMask_T_21 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_lsbMask_T_22 = bits(_res_hit_lsbMask_T_21, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_lsbMask_T_23 = not(_res_hit_lsbMask_T_22) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node res_hit_lsbMask_7 = or(io.pmp[0].mask, _res_hit_lsbMask_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 68:26] node _res_hit_msbMatch_T_70 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:29] node _res_hit_msbMatch_T_71 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbMatch_T_72 = not(_res_hit_msbMatch_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbMatch_T_73 = or(_res_hit_msbMatch_T_72, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbMatch_T_74 = not(_res_hit_msbMatch_T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbMatch_T_75 = shr(_res_hit_msbMatch_T_74, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:53] node _res_hit_msbMatch_T_76 = shr(io.pmp[0].mask, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 69:72] node _res_hit_msbMatch_T_77 = xor(_res_hit_msbMatch_T_70, _res_hit_msbMatch_T_75) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_msbMatch_T_78 = not(_res_hit_msbMatch_T_76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_msbMatch_T_79 = and(_res_hit_msbMatch_T_77, _res_hit_msbMatch_T_78) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_msbMatch_7 = eq(_res_hit_msbMatch_T_79, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_lsbMatch_T_70 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:28] node _res_hit_lsbMatch_T_71 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbMatch_T_72 = not(_res_hit_lsbMatch_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbMatch_T_73 = or(_res_hit_lsbMatch_T_72, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbMatch_T_74 = not(_res_hit_lsbMatch_T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbMatch_T_75 = bits(_res_hit_lsbMatch_T_74, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:55] node _res_hit_lsbMatch_T_76 = bits(res_hit_lsbMask_7, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 70:80] node _res_hit_lsbMatch_T_77 = xor(_res_hit_lsbMatch_T_70, _res_hit_lsbMatch_T_75) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_lsbMatch_T_78 = not(_res_hit_lsbMatch_T_76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_lsbMatch_T_79 = and(_res_hit_lsbMatch_T_77, _res_hit_lsbMatch_T_78) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node res_hit_lsbMatch_7 = eq(_res_hit_lsbMatch_T_79, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_92 = and(res_hit_msbMatch_7, res_hit_lsbMatch_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 71:16] node _res_hit_T_93 = bits(io.pmp[0].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_94 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_95 = bits(_res_hit_T_94, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_96 = not(_res_hit_T_95) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_msbsLess_T_84 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_85 = shl(pmp0.addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_86 = not(_res_hit_msbsLess_T_85) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_87 = or(_res_hit_msbsLess_T_86, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_88 = not(_res_hit_msbsLess_T_87) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_89 = shr(_res_hit_msbsLess_T_88, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_14 = lt(_res_hit_msbsLess_T_84, _res_hit_msbsLess_T_89) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_98 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_99 = shl(pmp0.addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_100 = not(_res_hit_msbsEqual_T_99) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_101 = or(_res_hit_msbsEqual_T_100, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_102 = not(_res_hit_msbsEqual_T_101) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_103 = shr(_res_hit_msbsEqual_T_102, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_104 = xor(_res_hit_msbsEqual_T_98, _res_hit_msbsEqual_T_103) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_14 = eq(_res_hit_msbsEqual_T_104, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_98 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_99 = or(_res_hit_lsbsLess_T_98, _res_hit_T_96) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_100 = shl(pmp0.addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_101 = not(_res_hit_lsbsLess_T_100) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_102 = or(_res_hit_lsbsLess_T_101, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_103 = not(_res_hit_lsbsLess_T_102) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_104 = bits(_res_hit_lsbsLess_T_103, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_14 = lt(_res_hit_lsbsLess_T_99, _res_hit_lsbsLess_T_104) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_97 = and(res_hit_msbsEqual_14, res_hit_lsbsLess_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_98 = or(res_hit_msbsLess_14, _res_hit_T_97) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_99 = eq(_res_hit_T_98, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_msbsLess_T_90 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:25] node _res_hit_msbsLess_T_91 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsLess_T_92 = not(_res_hit_msbsLess_T_91) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsLess_T_93 = or(_res_hit_msbsLess_T_92, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsLess_T_94 = not(_res_hit_msbsLess_T_93) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsLess_T_95 = shr(_res_hit_msbsLess_T_94, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:52] node res_hit_msbsLess_15 = lt(_res_hit_msbsLess_T_90, _res_hit_msbsLess_T_95) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 80:39] node _res_hit_msbsEqual_T_105 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:27] node _res_hit_msbsEqual_T_106 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_msbsEqual_T_107 = not(_res_hit_msbsEqual_T_106) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_msbsEqual_T_108 = or(_res_hit_msbsEqual_T_107, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_msbsEqual_T_109 = not(_res_hit_msbsEqual_T_108) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_msbsEqual_T_110 = shr(_res_hit_msbsEqual_T_109, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:54] node _res_hit_msbsEqual_T_111 = xor(_res_hit_msbsEqual_T_105, _res_hit_msbsEqual_T_110) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:41] node res_hit_msbsEqual_15 = eq(_res_hit_msbsEqual_T_111, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 81:69] node _res_hit_lsbsLess_T_105 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:25] node _res_hit_lsbsLess_T_106 = or(_res_hit_lsbsLess_T_105, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:42] node _res_hit_lsbsLess_T_107 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_lsbsLess_T_108 = not(_res_hit_lsbsLess_T_107) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_lsbsLess_T_109 = or(_res_hit_lsbsLess_T_108, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_lsbsLess_T_110 = not(_res_hit_lsbsLess_T_109) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_lsbsLess_T_111 = bits(_res_hit_lsbsLess_T_110, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:64] node res_hit_lsbsLess_15 = lt(_res_hit_lsbsLess_T_106, _res_hit_lsbsLess_T_111) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 82:53] node _res_hit_T_100 = and(res_hit_msbsEqual_15, res_hit_lsbsLess_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:30] node _res_hit_T_101 = or(res_hit_msbsLess_15, _res_hit_T_100) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 83:16] node _res_hit_T_102 = and(_res_hit_T_99, _res_hit_T_101) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_103 = and(_res_hit_T_93, _res_hit_T_102) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_7 = mux(_res_hit_T_91, _res_hit_T_92, _res_hit_T_103) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_7 = and(default, _res_ignore_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_aligned_lsbMask_T_14 = dshl(UInt<3>(0h7), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_aligned_lsbMask_T_15 = bits(_res_aligned_lsbMask_T_14, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node res_aligned_lsbMask_7 = not(_res_aligned_lsbMask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_aligned_straddlesLowerBound_T_119 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:35] node _res_aligned_straddlesLowerBound_T_120 = shl(pmp0.addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_121 = not(_res_aligned_straddlesLowerBound_T_120) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_122 = or(_res_aligned_straddlesLowerBound_T_121, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_123 = not(_res_aligned_straddlesLowerBound_T_122) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_124 = shr(_res_aligned_straddlesLowerBound_T_123, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:67] node _res_aligned_straddlesLowerBound_T_125 = xor(_res_aligned_straddlesLowerBound_T_119, _res_aligned_straddlesLowerBound_T_124) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:49] node _res_aligned_straddlesLowerBound_T_126 = eq(_res_aligned_straddlesLowerBound_T_125, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:82] node _res_aligned_straddlesLowerBound_T_127 = shl(pmp0.addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesLowerBound_T_128 = not(_res_aligned_straddlesLowerBound_T_127) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesLowerBound_T_129 = or(_res_aligned_straddlesLowerBound_T_128, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesLowerBound_T_130 = not(_res_aligned_straddlesLowerBound_T_129) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesLowerBound_T_131 = bits(_res_aligned_straddlesLowerBound_T_130, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:108] node _res_aligned_straddlesLowerBound_T_132 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:129] node _res_aligned_straddlesLowerBound_T_133 = not(_res_aligned_straddlesLowerBound_T_132) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:127] node _res_aligned_straddlesLowerBound_T_134 = and(_res_aligned_straddlesLowerBound_T_131, _res_aligned_straddlesLowerBound_T_133) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:125] node _res_aligned_straddlesLowerBound_T_135 = neq(_res_aligned_straddlesLowerBound_T_134, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:147] node res_aligned_straddlesLowerBound_7 = and(_res_aligned_straddlesLowerBound_T_126, _res_aligned_straddlesLowerBound_T_135) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 123:90] node _res_aligned_straddlesUpperBound_T_119 = shr(io.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:35] node _res_aligned_straddlesUpperBound_T_120 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_121 = not(_res_aligned_straddlesUpperBound_T_120) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_122 = or(_res_aligned_straddlesUpperBound_T_121, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_123 = not(_res_aligned_straddlesUpperBound_T_122) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_124 = shr(_res_aligned_straddlesUpperBound_T_123, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:62] node _res_aligned_straddlesUpperBound_T_125 = xor(_res_aligned_straddlesUpperBound_T_119, _res_aligned_straddlesUpperBound_T_124) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:49] node _res_aligned_straddlesUpperBound_T_126 = eq(_res_aligned_straddlesUpperBound_T_125, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:77] node _res_aligned_straddlesUpperBound_T_127 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_aligned_straddlesUpperBound_T_128 = not(_res_aligned_straddlesUpperBound_T_127) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_aligned_straddlesUpperBound_T_129 = or(_res_aligned_straddlesUpperBound_T_128, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_aligned_straddlesUpperBound_T_130 = not(_res_aligned_straddlesUpperBound_T_129) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_aligned_straddlesUpperBound_T_131 = bits(_res_aligned_straddlesUpperBound_T_130, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:98] node _res_aligned_straddlesUpperBound_T_132 = bits(io.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:119] node _res_aligned_straddlesUpperBound_T_133 = or(_res_aligned_straddlesUpperBound_T_132, res_aligned_lsbMask_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:136] node _res_aligned_straddlesUpperBound_T_134 = and(_res_aligned_straddlesUpperBound_T_131, _res_aligned_straddlesUpperBound_T_133) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:115] node _res_aligned_straddlesUpperBound_T_135 = neq(_res_aligned_straddlesUpperBound_T_134, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:148] node res_aligned_straddlesUpperBound_7 = and(_res_aligned_straddlesUpperBound_T_126, _res_aligned_straddlesUpperBound_T_135) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 124:85] node _res_aligned_rangeAligned_T_7 = or(res_aligned_straddlesLowerBound_7, res_aligned_straddlesUpperBound_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:46] node res_aligned_rangeAligned_7 = eq(_res_aligned_rangeAligned_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 125:24] node _res_aligned_pow2Aligned_T_21 = bits(io.pmp[0].mask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:39] node _res_aligned_pow2Aligned_T_22 = not(_res_aligned_pow2Aligned_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:34] node _res_aligned_pow2Aligned_T_23 = and(res_aligned_lsbMask_7, _res_aligned_pow2Aligned_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:32] node res_aligned_pow2Aligned_7 = eq(_res_aligned_pow2Aligned_T_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 126:57] node _res_aligned_T_7 = bits(io.pmp[0].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node res_aligned_7 = mux(_res_aligned_T_7, res_aligned_pow2Aligned_7, res_aligned_rangeAligned_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 127:8] node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_321 = eq(_res_T_320, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_323 = eq(_res_T_322, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_325 = eq(_res_T_324, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_327 = eq(_res_T_326, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_329 = eq(_res_T_328, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_331 = eq(_res_T_330, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_333 = and(_res_T_332, res_hit_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_334 = and(_res_T_333, res_aligned_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_336 = and(_res_T_334, _res_T_335) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_338 = and(_res_T_337, res_aligned_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_340 = and(_res_T_338, _res_T_339) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_342 = and(_res_T_341, res_hit_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_343 = and(_res_T_342, res_aligned_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_345 = and(_res_T_343, _res_T_344) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_347 = and(_res_T_346, res_aligned_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_349 = and(_res_T_347, _res_T_348) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_351 = and(_res_T_350, res_hit_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_352 = and(_res_T_351, res_aligned_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_354 = and(_res_T_352, _res_T_353) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_356 = and(_res_T_355, res_aligned_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_358 = and(_res_T_356, _res_T_357) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_7, io.pmp[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_15 = and(res_aligned_7, _res_cur_cfg_r_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_15 = and(res_aligned_7, _res_cur_cfg_w_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_15 = and(res_aligned_7, _res_cur_cfg_x_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node res = mux(res_hit_7, res_cur_7, _res_T_314) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] connect io.r, res.cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 188:8] connect io.w, res.cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 189:8] connect io.x, res.cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 190:8] module PMAChecker_1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 18:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 18:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 18:7] output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 19:14] node _legal_address_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_1 = cvt(_legal_address_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_3 = asSInt(_legal_address_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_5 = xor(io.paddr, UInt<14>(0h3000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_6 = cvt(_legal_address_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_8 = asSInt(_legal_address_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_10 = xor(io.paddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_11 = cvt(_legal_address_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<17>(0h10000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_13 = asSInt(_legal_address_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_15 = xor(io.paddr, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_16 = cvt(_legal_address_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_18 = asSInt(_legal_address_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_20 = xor(io.paddr, UInt<28>(0hc000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_21 = cvt(_legal_address_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<27>(0h4000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_23 = asSInt(_legal_address_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_25 = xor(io.paddr, UInt<29>(0h10013000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_26 = cvt(_legal_address_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_28 = asSInt(_legal_address_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_30 = xor(io.paddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_31 = cvt(_legal_address_T_30) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_33 = asSInt(_legal_address_T_32) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_35 = xor(io.paddr, UInt<29>(0h10015000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_36 = cvt(_legal_address_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_38 = asSInt(_legal_address_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_40 = xor(io.paddr, UInt<29>(0h10020000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_41 = cvt(_legal_address_T_40) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_43 = asSInt(_legal_address_T_42) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_45 = xor(io.paddr, UInt<29>(0h10021000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_46 = cvt(_legal_address_T_45) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_48 = asSInt(_legal_address_T_47) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_50 = xor(io.paddr, UInt<29>(0h10022000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_51 = cvt(_legal_address_T_50) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_53 = asSInt(_legal_address_T_52) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_55 = xor(io.paddr, UInt<29>(0h10023000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_56 = cvt(_legal_address_T_55) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_58 = asSInt(_legal_address_T_57) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_60 = xor(io.paddr, UInt<29>(0h10024000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_61 = cvt(_legal_address_T_60) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_62 = and(_legal_address_T_61, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_63 = asSInt(_legal_address_T_62) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_64 = eq(_legal_address_T_63, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_65 = xor(io.paddr, UInt<29>(0h10025000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_66 = cvt(_legal_address_T_65) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_67 = and(_legal_address_T_66, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_68 = asSInt(_legal_address_T_67) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_69 = eq(_legal_address_T_68, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_70 = xor(io.paddr, UInt<29>(0h10026000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_71 = cvt(_legal_address_T_70) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_72 = and(_legal_address_T_71, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_73 = asSInt(_legal_address_T_72) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_74 = eq(_legal_address_T_73, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_75 = xor(io.paddr, UInt<29>(0h10027000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_76 = cvt(_legal_address_T_75) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_77 = and(_legal_address_T_76, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_78 = asSInt(_legal_address_T_77) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_79 = eq(_legal_address_T_78, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_80 = xor(io.paddr, UInt<29>(0h10028000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_81 = cvt(_legal_address_T_80) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_82 = and(_legal_address_T_81, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_83 = asSInt(_legal_address_T_82) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_84 = eq(_legal_address_T_83, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_85 = xor(io.paddr, UInt<29>(0h10029000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_86 = cvt(_legal_address_T_85) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_87 = and(_legal_address_T_86, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_88 = asSInt(_legal_address_T_87) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_89 = eq(_legal_address_T_88, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_90 = xor(io.paddr, UInt<29>(0h1002a000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_91 = cvt(_legal_address_T_90) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_92 = and(_legal_address_T_91, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_93 = asSInt(_legal_address_T_92) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_94 = eq(_legal_address_T_93, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_95 = xor(io.paddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_96 = cvt(_legal_address_T_95) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_97 = and(_legal_address_T_96, asSInt(UInt<21>(0h100000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_98 = asSInt(_legal_address_T_97) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_99 = eq(_legal_address_T_98, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] wire _legal_address_WIRE : UInt<1>[20] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[0], _legal_address_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[1], _legal_address_T_9 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[2], _legal_address_T_14 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[3], _legal_address_T_19 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[4], _legal_address_T_24 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[5], _legal_address_T_29 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[6], _legal_address_T_34 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[7], _legal_address_T_39 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[8], _legal_address_T_44 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[9], _legal_address_T_49 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[10], _legal_address_T_54 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[11], _legal_address_T_59 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[12], _legal_address_T_64 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[13], _legal_address_T_69 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[14], _legal_address_T_74 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[15], _legal_address_T_79 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[16], _legal_address_T_84 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[17], _legal_address_T_89 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[18], _legal_address_T_94 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[19], _legal_address_T_99 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] node _legal_address_T_100 = or(_legal_address_WIRE[0], _legal_address_WIRE[1]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_101 = or(_legal_address_T_100, _legal_address_WIRE[2]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_102 = or(_legal_address_T_101, _legal_address_WIRE[3]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_103 = or(_legal_address_T_102, _legal_address_WIRE[4]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_104 = or(_legal_address_T_103, _legal_address_WIRE[5]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_105 = or(_legal_address_T_104, _legal_address_WIRE[6]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_106 = or(_legal_address_T_105, _legal_address_WIRE[7]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_107 = or(_legal_address_T_106, _legal_address_WIRE[8]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_108 = or(_legal_address_T_107, _legal_address_WIRE[9]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_109 = or(_legal_address_T_108, _legal_address_WIRE[10]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_110 = or(_legal_address_T_109, _legal_address_WIRE[11]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_111 = or(_legal_address_T_110, _legal_address_WIRE[12]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_112 = or(_legal_address_T_111, _legal_address_WIRE[13]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_113 = or(_legal_address_T_112, _legal_address_WIRE[14]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_114 = or(_legal_address_T_113, _legal_address_WIRE[15]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_115 = or(_legal_address_T_114, _legal_address_WIRE[16]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_116 = or(_legal_address_T_115, _legal_address_WIRE[17]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_117 = or(_legal_address_T_116, _legal_address_WIRE[18]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node legal_address = or(_legal_address_T_117, _legal_address_WIRE[19]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_cacheable_T_5 = and(legal_address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.cacheable, _io_resp_cacheable_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 41:21] node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_r_T_1 = cvt(_io_resp_r_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.r, _io_resp_r_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 42:13] node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_1 = cvt(_io_resp_w_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_5 = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_6 = cvt(_io_resp_w_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_10 = xor(io.paddr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_11 = cvt(_io_resp_w_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_15 = xor(io.paddr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_16 = cvt(_io_resp_w_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_20 = xor(io.paddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_21 = cvt(_io_resp_w_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_25 = xor(io.paddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_26 = cvt(_io_resp_w_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_30 = or(_io_resp_w_T_4, _io_resp_w_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_w_T_31 = or(_io_resp_w_T_30, _io_resp_w_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_w_T_32 = or(_io_resp_w_T_31, _io_resp_w_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_w_T_33 = or(_io_resp_w_T_32, _io_resp_w_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_w_T_34 = or(_io_resp_w_T_33, _io_resp_w_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_w_T_35 = xor(io.paddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_36 = cvt(_io_resp_w_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_37 = and(_io_resp_w_T_36, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_38 = asSInt(_io_resp_w_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_39 = eq(_io_resp_w_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_40 = mux(_io_resp_w_T_34, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_w_T_41 = mux(_io_resp_w_T_39, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_w_T_42 = or(_io_resp_w_T_40, _io_resp_w_T_41) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_resp_w_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_resp_w_WIRE, _io_resp_w_T_42 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_w_T_43 = and(legal_address, _io_resp_w_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.w, _io_resp_w_T_43 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 43:13] node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_1 = cvt(_io_resp_pp_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_5 = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_10 = xor(io.paddr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_15 = xor(io.paddr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_20 = xor(io.paddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_25 = xor(io.paddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_30 = or(_io_resp_pp_T_4, _io_resp_pp_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_pp_T_31 = or(_io_resp_pp_T_30, _io_resp_pp_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_pp_T_32 = or(_io_resp_pp_T_31, _io_resp_pp_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_pp_T_33 = or(_io_resp_pp_T_32, _io_resp_pp_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_pp_T_34 = or(_io_resp_pp_T_33, _io_resp_pp_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_pp_T_35 = xor(io.paddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_36 = cvt(_io_resp_pp_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_37 = and(_io_resp_pp_T_36, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_38 = asSInt(_io_resp_pp_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_39 = eq(_io_resp_pp_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_40 = mux(_io_resp_pp_T_34, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_pp_T_41 = mux(_io_resp_pp_T_39, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_pp_T_42 = or(_io_resp_pp_T_40, _io_resp_pp_T_41) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_resp_pp_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_resp_pp_WIRE, _io_resp_pp_T_42 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_pp_T_43 = and(legal_address, _io_resp_pp_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.pp, _io_resp_pp_T_43 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 44:14] node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_1 = cvt(_io_resp_al_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_5 = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_6 = cvt(_io_resp_al_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_10 = xor(io.paddr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_11 = cvt(_io_resp_al_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_15 = xor(io.paddr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_16 = cvt(_io_resp_al_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_20 = xor(io.paddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_21 = cvt(_io_resp_al_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_25 = xor(io.paddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_26 = cvt(_io_resp_al_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_30 = or(_io_resp_al_T_4, _io_resp_al_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_al_T_31 = or(_io_resp_al_T_30, _io_resp_al_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_al_T_32 = or(_io_resp_al_T_31, _io_resp_al_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_al_T_33 = or(_io_resp_al_T_32, _io_resp_al_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_al_T_34 = or(_io_resp_al_T_33, _io_resp_al_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_al_T_35 = xor(io.paddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_36 = cvt(_io_resp_al_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_37 = and(_io_resp_al_T_36, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_38 = asSInt(_io_resp_al_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_39 = eq(_io_resp_al_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_40 = mux(_io_resp_al_T_34, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_al_T_41 = mux(_io_resp_al_T_39, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_al_T_42 = or(_io_resp_al_T_40, _io_resp_al_T_41) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_resp_al_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_resp_al_WIRE, _io_resp_al_T_42 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_al_T_43 = and(legal_address, _io_resp_al_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.al, _io_resp_al_T_43 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 45:14] node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_1 = cvt(_io_resp_aa_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_5 = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_10 = xor(io.paddr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_15 = xor(io.paddr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_20 = xor(io.paddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_25 = xor(io.paddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_30 = or(_io_resp_aa_T_4, _io_resp_aa_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_aa_T_31 = or(_io_resp_aa_T_30, _io_resp_aa_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_aa_T_32 = or(_io_resp_aa_T_31, _io_resp_aa_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_aa_T_33 = or(_io_resp_aa_T_32, _io_resp_aa_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_aa_T_34 = or(_io_resp_aa_T_33, _io_resp_aa_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_aa_T_35 = xor(io.paddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_36 = cvt(_io_resp_aa_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_37 = and(_io_resp_aa_T_36, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_38 = asSInt(_io_resp_aa_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_39 = eq(_io_resp_aa_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_40 = mux(_io_resp_aa_T_34, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_aa_T_41 = mux(_io_resp_aa_T_39, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_aa_T_42 = or(_io_resp_aa_T_40, _io_resp_aa_T_41) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_resp_aa_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_resp_aa_WIRE, _io_resp_aa_T_42 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_aa_T_43 = and(legal_address, _io_resp_aa_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.aa, _io_resp_aa_T_43 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 46:14] node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_x_T_1 = cvt(_io_resp_x_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<32>(0h7a000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_x_T_5 = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_x_T_6 = cvt(_io_resp_x_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0hfa004000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_x_T_10 = or(_io_resp_x_T_4, _io_resp_x_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_x_T_11 = xor(io.paddr, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_x_T_12 = cvt(_io_resp_x_T_11) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_x_T_13 = and(_io_resp_x_T_12, asSInt(UInt<33>(0hfa000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_14 = asSInt(_io_resp_x_T_13) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_15 = eq(_io_resp_x_T_14, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_x_T_16 = xor(io.paddr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_x_T_17 = cvt(_io_resp_x_T_16) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_x_T_18 = and(_io_resp_x_T_17, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_19 = asSInt(_io_resp_x_T_18) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_20 = eq(_io_resp_x_T_19, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_x_T_21 = xor(io.paddr, UInt<29>(0h10000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_x_T_22 = cvt(_io_resp_x_T_21) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_x_T_23 = and(_io_resp_x_T_22, asSInt(UInt<33>(0hfa000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_24 = asSInt(_io_resp_x_T_23) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_25 = eq(_io_resp_x_T_24, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_x_T_26 = or(_io_resp_x_T_15, _io_resp_x_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_x_T_28 = mux(_io_resp_x_T_10, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_x_T_29 = mux(_io_resp_x_T_27, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_x_T_30 = or(_io_resp_x_T_28, _io_resp_x_T_29) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_resp_x_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_resp_x_WIRE, _io_resp_x_T_30 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_x_T_31 = and(legal_address, _io_resp_x_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.x, _io_resp_x_T_31 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 47:13] node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_1 = cvt(_io_resp_eff_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_5 = xor(io.paddr, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_10 = xor(io.paddr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_15 = xor(io.paddr, UInt<29>(0h10000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0hfa018000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_20 = xor(io.paddr, UInt<29>(0h10008000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_25 = xor(io.paddr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_30 = xor(io.paddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_31 = cvt(_io_resp_eff_T_30) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_32 = and(_io_resp_eff_T_31, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_33 = asSInt(_io_resp_eff_T_32) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_34 = eq(_io_resp_eff_T_33, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_35 = or(_io_resp_eff_T_4, _io_resp_eff_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_36 = or(_io_resp_eff_T_35, _io_resp_eff_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_37 = or(_io_resp_eff_T_36, _io_resp_eff_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_38 = or(_io_resp_eff_T_37, _io_resp_eff_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_39 = or(_io_resp_eff_T_38, _io_resp_eff_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_40 = or(_io_resp_eff_T_39, _io_resp_eff_T_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_41 = xor(io.paddr, UInt<13>(0h1000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_42 = cvt(_io_resp_eff_T_41) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_43 = and(_io_resp_eff_T_42, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_44 = asSInt(_io_resp_eff_T_43) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_45 = eq(_io_resp_eff_T_44, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_46 = xor(io.paddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_47 = cvt(_io_resp_eff_T_46) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_48 = and(_io_resp_eff_T_47, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_49 = asSInt(_io_resp_eff_T_48) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_50 = eq(_io_resp_eff_T_49, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_51 = xor(io.paddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_52 = cvt(_io_resp_eff_T_51) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_53 = and(_io_resp_eff_T_52, asSInt(UInt<33>(0hfa000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_54 = asSInt(_io_resp_eff_T_53) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_55 = eq(_io_resp_eff_T_54, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_56 = or(_io_resp_eff_T_45, _io_resp_eff_T_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_57 = or(_io_resp_eff_T_56, _io_resp_eff_T_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_58 = mux(_io_resp_eff_T_40, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_eff_T_59 = mux(_io_resp_eff_T_57, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_eff_T_60 = or(_io_resp_eff_T_58, _io_resp_eff_T_59) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_resp_eff_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_resp_eff_WIRE, _io_resp_eff_T_60 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_eff_T_61 = and(legal_address, _io_resp_eff_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.eff, _io_resp_eff_T_61 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 48:15] module OptimizationBarrier_TLBEntryData_8 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module OptimizationBarrier_TLBEntryData_9 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module OptimizationBarrier_TLBEntryData_10 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module OptimizationBarrier_TLBEntryData_11 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module OptimizationBarrier_TLBEntryData_12 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module OptimizationBarrier_TLBEntryData_13 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module DTLB_1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 118:32] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 118:32] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 118:32] output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<34>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<34>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<33>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<21>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<33>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 320:14] invalidate io.ptw.customCSRs.csrs[0].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[0].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[0].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[0].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[0].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[0].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[0].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] node vpn = bits(io.req.bits.vaddr, 32, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 335:30] reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<21>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[1][1], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 339:29] reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<21>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 341:30] reg special_entry : { level : UInt<2>, tag_vpn : UInt<21>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 346:56] regreset state : UInt<2>, clock, reset, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 352:22] reg r_refill_tag : UInt<21>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 354:25] reg r_superpage_repl_addr : UInt<2>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 355:34] reg r_sectored_repl_addr : UInt<0>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 356:33] reg r_sectored_hit : { valid : UInt<1>, bits : UInt<0>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 357:27] reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 358:28] reg r_vstage1_en : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 359:25] reg r_stage2_en : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 360:24] reg r_need_gpa : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 361:23] reg r_gpa_valid : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 362:24] reg r_gpa : UInt<33>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 363:18] reg r_gpa_vpn : UInt<21>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 364:22] reg r_gpa_is_pte : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 365:25] node priv_v = and(UInt<1>(0h0), io.req.bits.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 369:34] node priv_s = bits(io.req.bits.prv, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 370:20] node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 372:27] node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 373:17] node _stage1_en_T = bits(satp.mode, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 374:41] node stage1_en = and(UInt<1>(0h0), _stage1_en_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 374:29] node _vstage1_en_T = and(UInt<1>(0h0), priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 376:38] node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 376:68] node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 376:48] node _stage2_en_T = and(UInt<1>(0h0), priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 378:38] node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 378:68] node stage2_en = and(_stage2_en_T, _stage2_en_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 378:48] node _vm_enabled_T = or(stage1_en, stage2_en) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 399:31] node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 399:45] node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 399:64] node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 399:61] regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 402:37] node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 403:52] node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 403:37] node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 403:81] node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 403:78] node do_refill = and(UInt<1>(0h0), io.ptw.resp.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 408:29] node _invalidate_refill_T = eq(state, UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 410:88] node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 413:32] wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _mpu_ppn_WIRE_1 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE_1, special_entry.data[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_7 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect mpu_ppn_barrier.clock, clock connect mpu_ppn_barrier.reset, reset connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] node _mpu_ppn_T_24 = shr(io.req.bits.vaddr, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 413:146] node _mpu_ppn_T_25 = mux(_mpu_ppn_T, mpu_ppn_barrier.io.y.ppn, _mpu_ppn_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 413:20] node mpu_ppn = mux(do_refill, UInt<1>(0h0), _mpu_ppn_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 412:20] node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 414:52] node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 414:25] node _mpu_priv_T = or(do_refill, io.req.bits.passthrough) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 415:52] node _mpu_priv_T_1 = and(UInt<1>(0h0), _mpu_priv_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 415:38] node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 415:103] node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 415:27] inst pmp of PMPChecker_s3_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 416:19] connect pmp.clock, clock connect pmp.reset, reset connect pmp.io.addr, mpu_physaddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 417:15] connect pmp.io.size, io.req.bits.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 418:15] connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.prv, mpu_priv @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 420:14] inst pma of PMAChecker_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 422:19] connect pma.clock, clock connect pma.reset, reset connect pma.io.paddr, mpu_physaddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 423:16] node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 425:41] node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_1 = cvt(_homogeneous_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_3 = asSInt(_homogeneous_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_6 = cvt(_homogeneous_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_8 = asSInt(_homogeneous_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_11 = cvt(_homogeneous_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_13 = asSInt(_homogeneous_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_15 = xor(mpu_physaddr, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_16 = cvt(_homogeneous_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<17>(0h10000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_18 = asSInt(_homogeneous_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_20 = xor(mpu_physaddr, UInt<28>(0hc000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_21 = cvt(_homogeneous_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<27>(0h4000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_23 = asSInt(_homogeneous_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_25 = xor(mpu_physaddr, UInt<29>(0h10013000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_26 = cvt(_homogeneous_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_28 = asSInt(_homogeneous_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_30 = xor(mpu_physaddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_31 = cvt(_homogeneous_T_30) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<14>(0h2000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_33 = asSInt(_homogeneous_T_32) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_35 = xor(mpu_physaddr, UInt<29>(0h10020000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_36 = cvt(_homogeneous_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<16>(0h8000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_38 = asSInt(_homogeneous_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10028000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_41 = cvt(_homogeneous_T_40) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<14>(0h2000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_43 = asSInt(_homogeneous_T_42) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_45 = xor(mpu_physaddr, UInt<29>(0h1002a000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_46 = cvt(_homogeneous_T_45) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_48 = asSInt(_homogeneous_T_47) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_50 = xor(mpu_physaddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_51 = cvt(_homogeneous_T_50) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_52 = and(_homogeneous_T_51, asSInt(UInt<21>(0h100000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_53 = asSInt(_homogeneous_T_52) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_54 = eq(_homogeneous_T_53, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_55 = or(UInt<1>(0h0), _homogeneous_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_59 = or(_homogeneous_T_58, _homogeneous_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_60 = or(_homogeneous_T_59, _homogeneous_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_61 = or(_homogeneous_T_60, _homogeneous_T_34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_62 = or(_homogeneous_T_61, _homogeneous_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_63 = or(_homogeneous_T_62, _homogeneous_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_64 = or(_homogeneous_T_63, _homogeneous_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node homogeneous = or(_homogeneous_T_64, _homogeneous_T_54) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_65 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _homogeneous_T_66 = xor(mpu_physaddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_67 = cvt(_homogeneous_T_66) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_68 = and(_homogeneous_T_67, asSInt(UInt<33>(0h98010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_69 = asSInt(_homogeneous_T_68) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_70 = eq(_homogeneous_T_69, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_71 = or(UInt<1>(0h0), _homogeneous_T_70) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:66] node _homogeneous_T_72 = eq(_homogeneous_T_71, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _homogeneous_T_73 = xor(mpu_physaddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_74 = cvt(_homogeneous_T_73) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_75 = and(_homogeneous_T_74, asSInt(UInt<30>(0h1a000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_76 = asSInt(_homogeneous_T_75) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_77 = eq(_homogeneous_T_76, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_78 = or(UInt<1>(0h0), _homogeneous_T_77) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 85:66] node _homogeneous_T_79 = xor(mpu_physaddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_80 = cvt(_homogeneous_T_79) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_81 = and(_homogeneous_T_80, asSInt(UInt<33>(0h98010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_82 = asSInt(_homogeneous_T_81) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_83 = eq(_homogeneous_T_82, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_84 = or(UInt<1>(0h0), _homogeneous_T_83) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:66] node _homogeneous_T_85 = eq(_homogeneous_T_84, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _homogeneous_T_86 = xor(mpu_physaddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_87 = cvt(_homogeneous_T_86) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_88 = and(_homogeneous_T_87, asSInt(UInt<33>(0h98010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_89 = asSInt(_homogeneous_T_88) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_90 = eq(_homogeneous_T_89, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_91 = or(UInt<1>(0h0), _homogeneous_T_90) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:66] node _homogeneous_T_92 = eq(_homogeneous_T_91, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 428:39] node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 428:50] node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 429:33] node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 429:30] node prot_r = and(_prot_r_T_1, pmp.io.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 429:55] node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 430:33] node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 430:30] node prot_w = and(_prot_w_T_1, pmp.io.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 430:55] node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 434:33] node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 434:30] node prot_x = and(_prot_x_T_1, pmp.io.x) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 434:55] node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _sector_hits_T_4 = shr(_sector_hits_T_3, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 172:55] node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _superpage_hits_T_1 = shr(_superpage_hits_T, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _superpage_hits_T_3 = eq(superpage_entries[0].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _superpage_hits_T_4 = and(_superpage_hits_T_2, _superpage_hits_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node superpage_hits_0 = and(superpage_entries[0].valid[0], _superpage_hits_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node _superpage_hits_T_5 = xor(superpage_entries[1].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _superpage_hits_T_6 = shr(_superpage_hits_T_5, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _superpage_hits_T_8 = eq(superpage_entries[1].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _superpage_hits_T_9 = and(_superpage_hits_T_7, _superpage_hits_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node superpage_hits_1 = and(superpage_entries[1].valid[0], _superpage_hits_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node _superpage_hits_T_10 = xor(superpage_entries[2].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _superpage_hits_T_11 = shr(_superpage_hits_T_10, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _superpage_hits_T_13 = eq(superpage_entries[2].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _superpage_hits_T_14 = and(_superpage_hits_T_12, _superpage_hits_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node superpage_hits_2 = and(superpage_entries[2].valid[0], _superpage_hits_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node _superpage_hits_T_15 = xor(superpage_entries[3].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _superpage_hits_T_16 = shr(_superpage_hits_T_15, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _superpage_hits_T_17 = eq(_superpage_hits_T_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _superpage_hits_T_18 = eq(superpage_entries[3].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _superpage_hits_T_19 = and(_superpage_hits_T_17, _superpage_hits_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node superpage_hits_3 = and(superpage_entries[3].valid[0], _superpage_hits_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_idx = bits(vpn, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _hitsVec_T_1 = shr(_hitsVec_T, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_0 = and(vm_enabled, _hitsVec_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 440:44] node _hitsVec_T_6 = xor(superpage_entries[0].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _hitsVec_T_7 = shr(_hitsVec_T_6, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _hitsVec_T_9 = eq(superpage_entries[0].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node _hitsVec_T_11 = and(superpage_entries[0].valid[0], _hitsVec_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_1 = and(vm_enabled, _hitsVec_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 440:44] node _hitsVec_T_12 = xor(superpage_entries[1].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _hitsVec_T_13 = shr(_hitsVec_T_12, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _hitsVec_T_15 = eq(superpage_entries[1].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node _hitsVec_T_17 = and(superpage_entries[1].valid[0], _hitsVec_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_2 = and(vm_enabled, _hitsVec_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 440:44] node _hitsVec_T_18 = xor(superpage_entries[2].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _hitsVec_T_19 = shr(_hitsVec_T_18, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _hitsVec_T_21 = eq(superpage_entries[2].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node _hitsVec_T_23 = and(superpage_entries[2].valid[0], _hitsVec_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_3 = and(vm_enabled, _hitsVec_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 440:44] node _hitsVec_T_24 = xor(superpage_entries[3].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _hitsVec_T_25 = shr(_hitsVec_T_24, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _hitsVec_T_27 = eq(superpage_entries[3].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _hitsVec_T_28 = and(_hitsVec_T_26, _hitsVec_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node _hitsVec_T_29 = and(superpage_entries[3].valid[0], _hitsVec_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_4 = and(vm_enabled, _hitsVec_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 440:44] node _hitsVec_T_30 = xor(special_entry.tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _hitsVec_T_31 = shr(_hitsVec_T_30, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _hitsVec_T_33 = eq(special_entry.tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _hitsVec_T_34 = and(_hitsVec_T_32, _hitsVec_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node _hitsVec_T_35 = and(special_entry.valid[0], _hitsVec_T_34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_5 = and(vm_enabled, _hitsVec_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 440:44] node real_hits_lo_hi = cat(hitsVec_2, hitsVec_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node real_hits_lo = cat(real_hits_lo_hi, hitsVec_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node real_hits_hi_hi = cat(hitsVec_5, hitsVec_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node real_hits_hi = cat(real_hits_hi_hi, hitsVec_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node real_hits = cat(real_hits_hi, real_hits_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hits_T = eq(vm_enabled, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 442:18] node hits = cat(_hits_T, real_hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 442:17] when do_refill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 446:20] node refill_v = or(r_vstage1_en, r_stage2_en) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 448:33] wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 449:24] connect newEntry.ppn, io.ptw.resp.bits.pte.ppn @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 450:18] connect newEntry.c, cacheable @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 451:16] connect newEntry.u, io.ptw.resp.bits.pte.u @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 452:16] node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 453:25] connect newEntry.g, _newEntry_g_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 453:16] connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 454:21] connect newEntry.ae_final, io.ptw.resp.bits.ae_final @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 455:23] node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 456:53] node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 456:84] connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 456:24] connect newEntry.pf, io.ptw.resp.bits.pf @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 457:17] connect newEntry.gf, io.ptw.resp.bits.gf @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 458:17] connect newEntry.hr, io.ptw.resp.bits.hr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 459:17] connect newEntry.hw, io.ptw.resp.bits.hw @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 460:17] connect newEntry.hx, io.ptw.resp.bits.hx @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 461:17] node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:47] node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:44] node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:38] node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:32] node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:52] node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 149:35] connect newEntry.sr, _newEntry_sr_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 462:17] node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:47] node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:44] node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:38] node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:32] node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:52] node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 151:35] node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 151:40] connect newEntry.sw, _newEntry_sw_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 463:17] node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:47] node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:44] node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:38] node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:32] node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:52] node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 153:35] connect newEntry.sx, _newEntry_sx_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 464:17] connect newEntry.pr, prot_r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 465:17] connect newEntry.pw, prot_w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 466:17] connect newEntry.px, prot_x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 467:17] connect newEntry.ppp, pma.io.resp.pp @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 468:18] connect newEntry.pal, pma.io.resp.al @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 469:18] connect newEntry.paa, pma.io.resp.aa @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 470:18] connect newEntry.eff, pma.io.resp.eff @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 471:18] connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 472:35] node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 474:39] node _T_1 = and(UInt<1>(0h1), _T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 474:36] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 474:70] connect special_entry.tag_vpn, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 211:18] connect special_entry.tag_v, refill_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 212:16] node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect special_entry.level, _special_entry_level_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 213:16] connect special_entry.valid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 216:16] node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] connect special_entry.data[0], _special_entry_data_0_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:15] else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 476:40] when _T_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 476:58] node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 477:45] node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 477:22] node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:82] when _T_3 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:91] connect superpage_entries[0].tag_vpn, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 211:18] connect superpage_entries[0].tag_v, refill_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 212:16] node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect superpage_entries[0].level, _superpage_entries_0_level_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 213:16] connect superpage_entries[0].valid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 216:16] node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:15] when invalidate_refill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 480:34] connect superpage_entries[0].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:82] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:91] connect superpage_entries[1].tag_vpn, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 211:18] connect superpage_entries[1].tag_v, refill_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 212:16] node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect superpage_entries[1].level, _superpage_entries_1_level_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 213:16] connect superpage_entries[1].valid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 216:16] node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:15] when invalidate_refill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 480:34] connect superpage_entries[1].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:82] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:91] connect superpage_entries[2].tag_vpn, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 211:18] connect superpage_entries[2].tag_v, refill_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 212:16] node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect superpage_entries[2].level, _superpage_entries_2_level_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 213:16] connect superpage_entries[2].valid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 216:16] node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:15] when invalidate_refill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 480:34] connect superpage_entries[2].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:82] when _T_6 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:91] connect superpage_entries[3].tag_vpn, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 211:18] connect superpage_entries[3].tag_v, refill_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 212:16] node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect superpage_entries[3].level, _superpage_entries_3_level_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 213:16] connect superpage_entries[3].valid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 216:16] node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:15] when invalidate_refill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 480:34] connect superpage_entries[3].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] else : node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 485:22] node _T_7 = eq(waddr_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 486:75] when _T_7 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 486:84] node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 487:15] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 487:38] connect sectored_entries[0][0].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].valid[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].valid[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].valid[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].tag_vpn, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 211:18] connect sectored_entries[0][0].tag_v, refill_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 212:16] connect sectored_entries[0][0].level, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 213:16] node idx = bits(r_refill_tag, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect sectored_entries[0][0].valid[idx], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 216:16] node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:15] when invalidate_refill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 489:34] connect sectored_entries[0][0].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].valid[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].valid[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].valid[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect r_gpa_valid, io.ptw.resp.bits.gpa.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 493:17] connect r_gpa, io.ptw.resp.bits.gpa.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 494:11] connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 495:18] node _entries_T = bits(vpn, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _entries_WIRE_1 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_1 = bits(_entries_WIRE_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.fragmented_superpage, _entries_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_2 = bits(_entries_WIRE_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.c, _entries_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_3 = bits(_entries_WIRE_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.eff, _entries_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_4 = bits(_entries_WIRE_1, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.paa, _entries_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_5 = bits(_entries_WIRE_1, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.pal, _entries_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_6 = bits(_entries_WIRE_1, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.ppp, _entries_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_7 = bits(_entries_WIRE_1, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.pr, _entries_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_8 = bits(_entries_WIRE_1, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.px, _entries_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_9 = bits(_entries_WIRE_1, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.pw, _entries_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_10 = bits(_entries_WIRE_1, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.hr, _entries_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_11 = bits(_entries_WIRE_1, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.hx, _entries_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_12 = bits(_entries_WIRE_1, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.hw, _entries_T_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_13 = bits(_entries_WIRE_1, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.sr, _entries_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_14 = bits(_entries_WIRE_1, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.sx, _entries_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_15 = bits(_entries_WIRE_1, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.sw, _entries_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_16 = bits(_entries_WIRE_1, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.gf, _entries_T_16 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_17 = bits(_entries_WIRE_1, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.pf, _entries_T_17 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_18 = bits(_entries_WIRE_1, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.ae_stage2, _entries_T_18 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_19 = bits(_entries_WIRE_1, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.ae_final, _entries_T_19 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_20 = bits(_entries_WIRE_1, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.ae_ptw, _entries_T_20 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_21 = bits(_entries_WIRE_1, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.g, _entries_T_21 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_22 = bits(_entries_WIRE_1, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.u, _entries_T_22 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_23 = bits(_entries_WIRE_1, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.ppn, _entries_T_23 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst entries_barrier of OptimizationBarrier_TLBEntryData_8 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.c, _entries_WIRE.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.eff, _entries_WIRE.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.paa, _entries_WIRE.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.pal, _entries_WIRE.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.ppp, _entries_WIRE.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.pr, _entries_WIRE.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.px, _entries_WIRE.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.pw, _entries_WIRE.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.hr, _entries_WIRE.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.hx, _entries_WIRE.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.hw, _entries_WIRE.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.sr, _entries_WIRE.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.sx, _entries_WIRE.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.sw, _entries_WIRE.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.gf, _entries_WIRE.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.pf, _entries_WIRE.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.g, _entries_WIRE.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.u, _entries_WIRE.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.ppn, _entries_WIRE.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _entries_WIRE_3 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_3, superpage_entries[0].data[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_24 = bits(_entries_WIRE_3, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.fragmented_superpage, _entries_T_24 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_25 = bits(_entries_WIRE_3, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.c, _entries_T_25 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_26 = bits(_entries_WIRE_3, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.eff, _entries_T_26 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_27 = bits(_entries_WIRE_3, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.paa, _entries_T_27 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_28 = bits(_entries_WIRE_3, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.pal, _entries_T_28 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_29 = bits(_entries_WIRE_3, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.ppp, _entries_T_29 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_30 = bits(_entries_WIRE_3, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.pr, _entries_T_30 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_31 = bits(_entries_WIRE_3, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.px, _entries_T_31 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_32 = bits(_entries_WIRE_3, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.pw, _entries_T_32 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_33 = bits(_entries_WIRE_3, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.hr, _entries_T_33 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_34 = bits(_entries_WIRE_3, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.hx, _entries_T_34 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_35 = bits(_entries_WIRE_3, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.hw, _entries_T_35 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_36 = bits(_entries_WIRE_3, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.sr, _entries_T_36 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_37 = bits(_entries_WIRE_3, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.sx, _entries_T_37 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_38 = bits(_entries_WIRE_3, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.sw, _entries_T_38 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_39 = bits(_entries_WIRE_3, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.gf, _entries_T_39 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_40 = bits(_entries_WIRE_3, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.pf, _entries_T_40 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_41 = bits(_entries_WIRE_3, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.ae_stage2, _entries_T_41 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_42 = bits(_entries_WIRE_3, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.ae_final, _entries_T_42 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_43 = bits(_entries_WIRE_3, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.ae_ptw, _entries_T_43 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_44 = bits(_entries_WIRE_3, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.g, _entries_T_44 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_45 = bits(_entries_WIRE_3, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.u, _entries_T_45 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_46 = bits(_entries_WIRE_3, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.ppn, _entries_T_46 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_9 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.c, _entries_WIRE_2.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.px, _entries_WIRE_2.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.g, _entries_WIRE_2.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.u, _entries_WIRE_2.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _entries_WIRE_5 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_5, superpage_entries[1].data[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_47 = bits(_entries_WIRE_5, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.fragmented_superpage, _entries_T_47 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_48 = bits(_entries_WIRE_5, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.c, _entries_T_48 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_49 = bits(_entries_WIRE_5, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.eff, _entries_T_49 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_50 = bits(_entries_WIRE_5, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.paa, _entries_T_50 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_51 = bits(_entries_WIRE_5, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.pal, _entries_T_51 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_52 = bits(_entries_WIRE_5, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.ppp, _entries_T_52 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_53 = bits(_entries_WIRE_5, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.pr, _entries_T_53 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_54 = bits(_entries_WIRE_5, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.px, _entries_T_54 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_55 = bits(_entries_WIRE_5, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.pw, _entries_T_55 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_56 = bits(_entries_WIRE_5, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.hr, _entries_T_56 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_57 = bits(_entries_WIRE_5, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.hx, _entries_T_57 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_58 = bits(_entries_WIRE_5, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.hw, _entries_T_58 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_59 = bits(_entries_WIRE_5, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.sr, _entries_T_59 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_60 = bits(_entries_WIRE_5, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.sx, _entries_T_60 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_61 = bits(_entries_WIRE_5, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.sw, _entries_T_61 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_62 = bits(_entries_WIRE_5, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.gf, _entries_T_62 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_63 = bits(_entries_WIRE_5, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.pf, _entries_T_63 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_64 = bits(_entries_WIRE_5, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.ae_stage2, _entries_T_64 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_65 = bits(_entries_WIRE_5, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.ae_final, _entries_T_65 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_66 = bits(_entries_WIRE_5, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.ae_ptw, _entries_T_66 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_67 = bits(_entries_WIRE_5, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.g, _entries_T_67 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_68 = bits(_entries_WIRE_5, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.u, _entries_T_68 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_69 = bits(_entries_WIRE_5, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.ppn, _entries_T_69 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_10 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.c, _entries_WIRE_4.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.px, _entries_WIRE_4.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.g, _entries_WIRE_4.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.u, _entries_WIRE_4.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _entries_WIRE_7 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_7, superpage_entries[2].data[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_70 = bits(_entries_WIRE_7, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.fragmented_superpage, _entries_T_70 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_71 = bits(_entries_WIRE_7, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.c, _entries_T_71 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_72 = bits(_entries_WIRE_7, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.eff, _entries_T_72 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_73 = bits(_entries_WIRE_7, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.paa, _entries_T_73 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_74 = bits(_entries_WIRE_7, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.pal, _entries_T_74 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_75 = bits(_entries_WIRE_7, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.ppp, _entries_T_75 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_76 = bits(_entries_WIRE_7, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.pr, _entries_T_76 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_77 = bits(_entries_WIRE_7, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.px, _entries_T_77 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_78 = bits(_entries_WIRE_7, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.pw, _entries_T_78 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_79 = bits(_entries_WIRE_7, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.hr, _entries_T_79 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_80 = bits(_entries_WIRE_7, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.hx, _entries_T_80 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_81 = bits(_entries_WIRE_7, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.hw, _entries_T_81 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_82 = bits(_entries_WIRE_7, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.sr, _entries_T_82 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_83 = bits(_entries_WIRE_7, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.sx, _entries_T_83 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_84 = bits(_entries_WIRE_7, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.sw, _entries_T_84 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_85 = bits(_entries_WIRE_7, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.gf, _entries_T_85 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_86 = bits(_entries_WIRE_7, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.pf, _entries_T_86 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_87 = bits(_entries_WIRE_7, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.ae_stage2, _entries_T_87 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_88 = bits(_entries_WIRE_7, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.ae_final, _entries_T_88 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_89 = bits(_entries_WIRE_7, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.ae_ptw, _entries_T_89 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_90 = bits(_entries_WIRE_7, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.g, _entries_T_90 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_91 = bits(_entries_WIRE_7, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.u, _entries_T_91 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_92 = bits(_entries_WIRE_7, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.ppn, _entries_T_92 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_11 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.c, _entries_WIRE_6.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.px, _entries_WIRE_6.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.g, _entries_WIRE_6.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.u, _entries_WIRE_6.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _entries_WIRE_9 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_9, superpage_entries[3].data[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_93 = bits(_entries_WIRE_9, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.fragmented_superpage, _entries_T_93 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_94 = bits(_entries_WIRE_9, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.c, _entries_T_94 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_95 = bits(_entries_WIRE_9, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.eff, _entries_T_95 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_96 = bits(_entries_WIRE_9, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.paa, _entries_T_96 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_97 = bits(_entries_WIRE_9, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.pal, _entries_T_97 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_98 = bits(_entries_WIRE_9, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.ppp, _entries_T_98 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_99 = bits(_entries_WIRE_9, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.pr, _entries_T_99 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_100 = bits(_entries_WIRE_9, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.px, _entries_T_100 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_101 = bits(_entries_WIRE_9, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.pw, _entries_T_101 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_102 = bits(_entries_WIRE_9, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.hr, _entries_T_102 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_103 = bits(_entries_WIRE_9, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.hx, _entries_T_103 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_104 = bits(_entries_WIRE_9, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.hw, _entries_T_104 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_105 = bits(_entries_WIRE_9, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.sr, _entries_T_105 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_106 = bits(_entries_WIRE_9, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.sx, _entries_T_106 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_107 = bits(_entries_WIRE_9, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.sw, _entries_T_107 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_108 = bits(_entries_WIRE_9, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.gf, _entries_T_108 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_109 = bits(_entries_WIRE_9, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.pf, _entries_T_109 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_110 = bits(_entries_WIRE_9, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.ae_stage2, _entries_T_110 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_111 = bits(_entries_WIRE_9, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.ae_final, _entries_T_111 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_112 = bits(_entries_WIRE_9, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.ae_ptw, _entries_T_112 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_113 = bits(_entries_WIRE_9, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.g, _entries_T_113 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_114 = bits(_entries_WIRE_9, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.u, _entries_T_114 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_115 = bits(_entries_WIRE_9, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.ppn, _entries_T_115 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_12 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.c, _entries_WIRE_8.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.px, _entries_WIRE_8.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.g, _entries_WIRE_8.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.u, _entries_WIRE_8.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _entries_WIRE_11 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_11, special_entry.data[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_116 = bits(_entries_WIRE_11, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.fragmented_superpage, _entries_T_116 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_117 = bits(_entries_WIRE_11, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.c, _entries_T_117 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_118 = bits(_entries_WIRE_11, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.eff, _entries_T_118 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_119 = bits(_entries_WIRE_11, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.paa, _entries_T_119 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_120 = bits(_entries_WIRE_11, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.pal, _entries_T_120 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_121 = bits(_entries_WIRE_11, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.ppp, _entries_T_121 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_122 = bits(_entries_WIRE_11, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.pr, _entries_T_122 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_123 = bits(_entries_WIRE_11, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.px, _entries_T_123 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_124 = bits(_entries_WIRE_11, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.pw, _entries_T_124 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_125 = bits(_entries_WIRE_11, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.hr, _entries_T_125 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_126 = bits(_entries_WIRE_11, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.hx, _entries_T_126 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_127 = bits(_entries_WIRE_11, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.hw, _entries_T_127 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_128 = bits(_entries_WIRE_11, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.sr, _entries_T_128 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_129 = bits(_entries_WIRE_11, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.sx, _entries_T_129 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_130 = bits(_entries_WIRE_11, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.sw, _entries_T_130 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_131 = bits(_entries_WIRE_11, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.gf, _entries_T_131 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_132 = bits(_entries_WIRE_11, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.pf, _entries_T_132 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_133 = bits(_entries_WIRE_11, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.ae_stage2, _entries_T_133 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_134 = bits(_entries_WIRE_11, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.ae_final, _entries_T_134 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_135 = bits(_entries_WIRE_11, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.ae_ptw, _entries_T_135 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_136 = bits(_entries_WIRE_11, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.g, _entries_T_136 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_137 = bits(_entries_WIRE_11, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.u, _entries_T_137 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_138 = bits(_entries_WIRE_11, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.ppn, _entries_T_138 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_13 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.c, _entries_WIRE_10.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.px, _entries_WIRE_10.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.g, _entries_WIRE_10.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.u, _entries_WIRE_10.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] node _ppn_T = eq(vm_enabled, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 502:30] node _ppn_T_1 = bits(vpn, 19, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 502:125] node _ppn_T_2 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_3 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_4 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_5 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_6 = mux(hitsVec_4, entries_barrier_4.io.y.ppn, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_7 = mux(hitsVec_5, entries_barrier_5.io.y.ppn, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_8 = mux(_ppn_T, _ppn_T_1, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_9 = or(_ppn_T_2, _ppn_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_10 = or(_ppn_T_9, _ppn_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_11 = or(_ppn_T_10, _ppn_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_12 = or(_ppn_T_11, _ppn_T_6) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_13 = or(_ppn_T_12, _ppn_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_14 = or(_ppn_T_13, _ppn_T_8) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire ppn : UInt<20> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect ppn, _ppn_T_14 @[src/main/scala/chisel3/util/Mux.scala 30:73] node ptw_ae_array_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, entries_barrier.io.y.ae_ptw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_ae_array_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, entries_barrier_3.io.y.ae_ptw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 506:25] node final_ae_array_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node final_ae_array_lo = cat(final_ae_array_lo_hi, entries_barrier.io.y.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node final_ae_array_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node final_ae_array_hi = cat(final_ae_array_hi_hi, entries_barrier_3.io.y.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 507:27] node ptw_pf_array_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, entries_barrier.io.y.pf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_pf_array_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, entries_barrier_3.io.y.pf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 508:25] node ptw_gf_array_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, entries_barrier.io.y.gf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_gf_array_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, entries_barrier_3.io.y.gf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 509:25] node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 510:16] node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 513:24] node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 513:32] node priv_rw_ok_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, entries_barrier.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_rw_ok_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, entries_barrier_3.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 513:23] node priv_rw_ok_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, entries_barrier.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_rw_ok_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, entries_barrier_3.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 513:84] node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 513:75] node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 513:70] node priv_x_ok_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok_lo = cat(priv_x_ok_lo_hi, entries_barrier.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok_hi = cat(priv_x_ok_hi_hi, entries_barrier_3.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_x_ok_T_1 = not(_priv_x_ok_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 516:31] node priv_x_ok_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, entries_barrier.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, entries_barrier_3.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 516:22] node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<6>(0h3f), UInt<6>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 517:27] node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 517:83] node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<6>(0h3f), UInt<6>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 517:68] node stage1_bypass_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node stage1_bypass_lo = cat(stage1_bypass_lo_hi, entries_barrier.io.y.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node stage1_bypass_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node stage1_bypass_hi = cat(stage1_bypass_hi_hi, entries_barrier_3.io.y.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 517:95] node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 517:61] node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 518:36] node mxr = or(io.ptw.status.mxr, _mxr_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 518:31] node r_array_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_lo = cat(r_array_lo_hi, entries_barrier.io.y.sr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_hi = cat(r_array_hi_hi, entries_barrier_3.io.y.sr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _r_array_T = cat(r_array_hi, r_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_lo_1 = cat(r_array_lo_hi_1, entries_barrier.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_hi_1 = cat(r_array_hi_hi_1, entries_barrier_3.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 520:74] node _r_array_T_3 = or(_r_array_T, _r_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 520:69] node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 520:41] node _r_array_T_5 = or(_r_array_T_4, stage1_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 520:113] node r_array = cat(UInt<1>(0h1), _r_array_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 520:20] node w_array_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node w_array_lo = cat(w_array_lo_hi, entries_barrier.io.y.sw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node w_array_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node w_array_hi = cat(w_array_hi_hi, entries_barrier_3.io.y.sw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _w_array_T = cat(w_array_hi, w_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _w_array_T_1 = and(priv_rw_ok, _w_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 521:41] node _w_array_T_2 = or(_w_array_T_1, stage1_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 521:69] node w_array = cat(UInt<1>(0h1), _w_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 521:20] node x_array_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node x_array_lo = cat(x_array_lo_hi, entries_barrier.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node x_array_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node x_array_hi = cat(x_array_hi_hi, entries_barrier_3.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _x_array_T = cat(x_array_hi, x_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _x_array_T_1 = and(priv_x_ok, _x_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 522:40] node _x_array_T_2 = or(_x_array_T_1, stage1_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 522:68] node x_array = cat(UInt<1>(0h1), _x_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 522:20] node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 523:42] node stage2_bypass = mux(_stage2_bypass_T, UInt<6>(0h3f), UInt<6>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 523:27] node hr_array_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_lo = cat(hr_array_lo_hi, entries_barrier.io.y.hr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_hi = cat(hr_array_hi_hi, entries_barrier_3.io.y.hr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hr_array_T = cat(hr_array_hi, hr_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_lo_1 = cat(hr_array_lo_hi_1, entries_barrier.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_hi_1 = cat(hr_array_hi_hi_1, entries_barrier_3.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 524:60] node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 524:55] node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 524:111] node hr_array = cat(UInt<1>(0h1), _hr_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 524:21] node hw_array_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hw_array_lo = cat(hw_array_lo_hi, entries_barrier.io.y.hw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hw_array_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hw_array_hi = cat(hw_array_hi_hi, entries_barrier_3.io.y.hw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hw_array_T = cat(hw_array_hi, hw_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hw_array_T_1 = or(_hw_array_T, stage2_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 525:55] node hw_array = cat(UInt<1>(0h1), _hw_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 525:21] node hx_array_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hx_array_lo = cat(hx_array_lo_hi, entries_barrier.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hx_array_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hx_array_hi = cat(hx_array_hi_hi, entries_barrier_3.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hx_array_T = cat(hx_array_hi, hx_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hx_array_T_1 = or(_hx_array_T, stage2_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 526:55] node hx_array = cat(UInt<1>(0h1), _hx_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 526:21] node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 529:26] node pr_array_lo = cat(entries_barrier_1.io.y.pr, entries_barrier.io.y.pr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pr_array_hi_hi = cat(entries_barrier_4.io.y.pr, entries_barrier_3.io.y.pr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pr_array_hi = cat(pr_array_hi_hi, entries_barrier_2.io.y.pr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 529:21] node _pr_array_T_3 = or(ptw_ae_array, final_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 529:104] node _pr_array_T_4 = not(_pr_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 529:89] node pr_array = and(_pr_array_T_2, _pr_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 529:87] node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 531:26] node pw_array_lo = cat(entries_barrier_1.io.y.pw, entries_barrier.io.y.pw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pw_array_hi_hi = cat(entries_barrier_4.io.y.pw, entries_barrier_3.io.y.pw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pw_array_hi = cat(pw_array_hi_hi, entries_barrier_2.io.y.pw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 531:21] node _pw_array_T_3 = or(ptw_ae_array, final_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 531:104] node _pw_array_T_4 = not(_pw_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 531:89] node pw_array = and(_pw_array_T_2, _pw_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 531:87] node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 533:26] node px_array_lo = cat(entries_barrier_1.io.y.px, entries_barrier.io.y.px) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node px_array_hi_hi = cat(entries_barrier_4.io.y.px, entries_barrier_3.io.y.px) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node px_array_hi = cat(px_array_hi_hi, entries_barrier_2.io.y.px) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _px_array_T_1 = cat(px_array_hi, px_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 533:21] node _px_array_T_3 = or(ptw_ae_array, final_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 533:104] node _px_array_T_4 = not(_px_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 533:89] node px_array = and(_px_array_T_2, _px_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 533:87] node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 535:27] node eff_array_lo = cat(entries_barrier_1.io.y.eff, entries_barrier.io.y.eff) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node eff_array_hi_hi = cat(entries_barrier_4.io.y.eff, entries_barrier_3.io.y.eff) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node eff_array_hi = cat(eff_array_hi_hi, entries_barrier_2.io.y.eff) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node eff_array = cat(_eff_array_T, _eff_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 535:22] node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 537:25] node c_array_lo = cat(entries_barrier_1.io.y.c, entries_barrier.io.y.c) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node c_array_hi_hi = cat(entries_barrier_4.io.y.c, entries_barrier_3.io.y.c) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node c_array_hi = cat(c_array_hi_hi, entries_barrier_2.io.y.c) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _c_array_T_1 = cat(c_array_hi, c_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node c_array = cat(_c_array_T, _c_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 537:20] node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 539:27] node ppp_array_lo = cat(entries_barrier_1.io.y.ppp, entries_barrier.io.y.ppp) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ppp_array_hi_hi = cat(entries_barrier_4.io.y.ppp, entries_barrier_3.io.y.ppp) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ppp_array_hi = cat(ppp_array_hi_hi, entries_barrier_2.io.y.ppp) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ppp_array = cat(_ppp_array_T, _ppp_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 539:22] node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 541:27] node paa_array_lo = cat(entries_barrier_1.io.y.paa, entries_barrier.io.y.paa) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node paa_array_hi_hi = cat(entries_barrier_4.io.y.paa, entries_barrier_3.io.y.paa) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node paa_array_hi = cat(paa_array_hi_hi, entries_barrier_2.io.y.paa) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node paa_array = cat(_paa_array_T, _paa_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 541:22] node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 543:27] node pal_array_lo = cat(entries_barrier_1.io.y.pal, entries_barrier.io.y.pal) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pal_array_hi_hi = cat(entries_barrier_4.io.y.pal, entries_barrier_3.io.y.pal) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pal_array_hi = cat(pal_array_hi_hi, entries_barrier_2.io.y.pal) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pal_array = cat(_pal_array_T, _pal_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 543:22] node ppp_array_if_cached = or(ppp_array, c_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 544:39] node paa_array_if_cached = or(paa_array, c_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 545:39] node pal_array_if_cached = or(pal_array, c_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 546:39] node _prefetchable_array_T = and(cacheable, homogeneous) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 547:43] node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 547:59] node prefetchable_array_lo = cat(entries_barrier_1.io.y.c, entries_barrier.io.y.c) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node prefetchable_array_hi_hi = cat(entries_barrier_4.io.y.c, entries_barrier_3.io.y.c) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node prefetchable_array_hi = cat(prefetchable_array_hi_hi, entries_barrier_2.io.y.c) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 547:31] node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 550:69] node _misaligned_T_2 = tail(_misaligned_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 550:69] node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 550:39] node misaligned = orr(_misaligned_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 550:77] node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 570:33] node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 571:40] node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 572:43] node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 573:41] node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 89:68] node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 575:56] node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 575:37] node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:32] node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:49] node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:42] node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:66] node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:59] node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:76] node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 577:35] node lrscAllowed = mux(UInt<1>(0h1), UInt<1>(0h0), c_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 580:24] node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 582:8] node _ae_array_T_1 = not(lrscAllowed) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 583:19] node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 583:8] node ae_array = or(_ae_array_T, _ae_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 582:37] node _ae_ld_array_T = and(pr_array, px_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 586:71] node _ae_ld_array_T_1 = mux(cmd_readx, _ae_ld_array_T, pr_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 586:50] node _ae_ld_array_T_2 = not(_ae_ld_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 586:46] node _ae_ld_array_T_3 = or(ae_array, _ae_ld_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 586:44] node ae_ld_array = mux(cmd_read, _ae_ld_array_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 586:24] node _ae_st_array_T = not(pw_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 588:37] node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 588:35] node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 588:8] node _ae_st_array_T_3 = not(ppp_array_if_cached) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 589:26] node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 589:8] node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 588:53] node _ae_st_array_T_6 = not(pal_array_if_cached) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 590:26] node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 590:8] node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 589:53] node _ae_st_array_T_9 = not(paa_array_if_cached) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 591:29] node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 591:8] node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 590:53] node _must_alloc_array_T = not(ppp_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 593:26] node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 593:8] node _must_alloc_array_T_2 = not(pal_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 594:26] node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 594:8] node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 593:43] node _must_alloc_array_T_5 = not(paa_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 595:29] node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 595:8] node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 594:43] node _must_alloc_array_T_8 = not(UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 596:19] node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 596:8] node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 595:46] node _pf_ld_array_T = mux(cmd_readx, x_array, r_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:41] node _pf_ld_array_T_1 = not(_pf_ld_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:37] node _pf_ld_array_T_2 = not(ptw_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:73] node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:71] node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:88] node _pf_ld_array_T_5 = not(ptw_gf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:106] node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:104] node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:24] node _pf_st_array_T = not(w_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:44] node _pf_st_array_T_1 = not(ptw_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:55] node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:53] node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:70] node _pf_st_array_T_4 = not(ptw_gf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:88] node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:86] node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:24] node _pf_inst_array_T = not(x_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 599:25] node _pf_inst_array_T_1 = not(ptw_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 599:36] node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 599:34] node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 599:51] node _pf_inst_array_T_4 = not(ptw_gf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 599:69] node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 599:67] node _gf_ld_array_T = and(priv_v, cmd_read) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:32] node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:50] node _gf_ld_array_T_2 = not(_gf_ld_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:46] node _gf_ld_array_T_3 = not(ptw_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:84] node _gf_ld_array_T_4 = and(_gf_ld_array_T_2, _gf_ld_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:82] node _gf_ld_array_T_5 = or(_gf_ld_array_T_4, ptw_gf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:99] node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:24] node _gf_st_array_T = and(priv_v, cmd_write_perms) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 601:32] node _gf_st_array_T_1 = not(hw_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 601:53] node _gf_st_array_T_2 = not(ptw_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 601:65] node _gf_st_array_T_3 = and(_gf_st_array_T_1, _gf_st_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 601:63] node _gf_st_array_T_4 = or(_gf_st_array_T_3, ptw_gf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 601:80] node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 601:24] node _gf_inst_array_T = not(hx_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 602:36] node _gf_inst_array_T_1 = not(ptw_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 602:48] node _gf_inst_array_T_2 = and(_gf_inst_array_T, _gf_inst_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 602:46] node _gf_inst_array_T_3 = or(_gf_inst_array_T_2, ptw_gf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 602:63] node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 602:26] node gpa_hits_need_gpa_mask = or(gf_ld_array, gf_st_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 605:73] node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 606:73] node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 606:60] node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<5>(0h1f), UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 606:24] node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 606:107] node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<6>(0h3f), UInt<6>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 606:88] node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 606:82] node _gpa_hits_T = bits(gpa_hits_need_gpa_mask, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 607:30] node _gpa_hits_T_1 = not(_gpa_hits_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 607:16] node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 607:14] node tlb_hit_if_not_gpa_miss = orr(real_hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 610:43] node _tlb_hit_T = and(real_hits, gpa_hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 611:28] node tlb_hit = orr(_tlb_hit_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 611:40] node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 613:32] node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 613:29] node _tlb_miss_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 613:56] node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 613:53] node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 613:67] node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 613:64] reg state_reg : UInt<0>, clock @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 168:46] reg state_vec : UInt<0>[1], clock @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 304:30] regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 168:70] node _T_9 = and(io.req.valid, vm_enabled) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 617:22] when _T_9 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 617:37] when sector_hits_0 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 619:28] connect state_vec[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 308:20] node _T_10 = or(superpage_hits_0, superpage_hits_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_11 = or(_T_10, superpage_hits_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_12 = or(_T_11, superpage_hits_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] when _T_12 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 620:31] node lo = cat(superpage_hits_1, superpage_hits_0) @[src/main/scala/chisel3/util/OneHot.scala 21:45] node hi = cat(superpage_hits_3, superpage_hits_2) @[src/main/scala/chisel3/util/OneHot.scala 21:45] node _T_13 = cat(hi, lo) @[src/main/scala/chisel3/util/OneHot.scala 21:45] node hi_1 = bits(_T_13, 3, 2) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node lo_1 = bits(_T_13, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _T_14 = orr(hi_1) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _T_15 = or(hi_1, lo_1) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node _T_16 = bits(_T_15, 1, 1) @[src/main/scala/chisel3/util/CircuitMath.scala 28:8] node _T_17 = cat(_T_14, _T_16) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node state_reg_touch_way_sized = bits(_T_17, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:43] node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:33] node state_reg_left_subtree_state = bits(state_reg_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node state_reg_right_subtree_state = bits(state_reg_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 198:38] node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_T_1 = bits(_state_reg_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 203:16] node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 207:62] node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 206:16] node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] connect state_reg_1, _state_reg_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 172:15] node _multipleHits_T = bits(real_hits, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 181:37] node _multipleHits_T_1 = bits(_multipleHits_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 181:37] node multipleHits_leftOne = bits(_multipleHits_T_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 178:18] node _multipleHits_T_2 = bits(_multipleHits_T, 2, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 182:39] node _multipleHits_T_3 = bits(_multipleHits_T_2, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 181:37] node multipleHits_leftOne_1 = bits(_multipleHits_T_3, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 178:18] node _multipleHits_T_4 = bits(_multipleHits_T_2, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 182:39] node multipleHits_rightOne = bits(_multipleHits_T_4, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 178:18] node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:16] node _multipleHits_T_5 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:37] node _multipleHits_T_6 = and(multipleHits_leftOne_1, multipleHits_rightOne) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:61] node multipleHits_rightTwo = or(_multipleHits_T_5, _multipleHits_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:49] node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:16] node _multipleHits_T_7 = or(UInt<1>(0h0), multipleHits_rightTwo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:37] node _multipleHits_T_8 = and(multipleHits_leftOne, multipleHits_rightOne_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:61] node multipleHits_leftTwo = or(_multipleHits_T_7, _multipleHits_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:49] node _multipleHits_T_9 = bits(real_hits, 5, 3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 182:39] node _multipleHits_T_10 = bits(_multipleHits_T_9, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 181:37] node multipleHits_leftOne_3 = bits(_multipleHits_T_10, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 178:18] node _multipleHits_T_11 = bits(_multipleHits_T_9, 2, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 182:39] node _multipleHits_T_12 = bits(_multipleHits_T_11, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 181:37] node multipleHits_leftOne_4 = bits(_multipleHits_T_12, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 178:18] node _multipleHits_T_13 = bits(_multipleHits_T_11, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 182:39] node multipleHits_rightOne_2 = bits(_multipleHits_T_13, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 178:18] node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:16] node _multipleHits_T_14 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:37] node _multipleHits_T_15 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:61] node multipleHits_rightTwo_1 = or(_multipleHits_T_14, _multipleHits_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:49] node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:16] node _multipleHits_T_16 = or(UInt<1>(0h0), multipleHits_rightTwo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:37] node _multipleHits_T_17 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:61] node multipleHits_rightTwo_2 = or(_multipleHits_T_16, _multipleHits_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:49] node _multipleHits_T_18 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:16] node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:37] node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:61] node multipleHits = or(_multipleHits_T_19, _multipleHits_T_20) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:49] node _io_req_ready_T = eq(state, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 631:25] connect io.req.ready, _io_req_ready_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 631:16] node _io_resp_pf_ld_T = and(UInt<1>(0h0), cmd_read) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 633:28] node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 633:57] node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 633:65] node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 633:41] connect io.resp.pf.ld, _io_resp_pf_ld_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 633:17] node _io_resp_pf_st_T = and(UInt<1>(0h0), cmd_write_perms) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 634:28] node _io_resp_pf_st_T_1 = and(pf_st_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 634:64] node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 634:72] node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 634:48] connect io.resp.pf.st, _io_resp_pf_st_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 634:17] node _io_resp_pf_inst_T = and(pf_inst_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 635:47] node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 635:55] node _io_resp_pf_inst_T_2 = or(UInt<1>(0h0), _io_resp_pf_inst_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 635:29] connect io.resp.pf.inst, _io_resp_pf_inst_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 635:19] node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 637:29] node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 637:58] node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 637:66] node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 637:42] connect io.resp.gf.ld, _io_resp_gf_ld_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 637:17] node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 638:29] node _io_resp_gf_st_T_1 = and(gf_st_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 638:65] node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 638:73] node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 638:49] connect io.resp.gf.st, _io_resp_gf_st_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 638:17] node _io_resp_gf_inst_T = and(gf_inst_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 639:48] node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 639:56] node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 639:30] connect io.resp.gf.inst, _io_resp_gf_inst_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 639:19] node _io_resp_ae_ld_T = and(ae_ld_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 641:33] node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 641:41] connect io.resp.ae.ld, _io_resp_ae_ld_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 641:17] node _io_resp_ae_st_T = and(ae_st_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 642:33] node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 642:41] connect io.resp.ae.st, _io_resp_ae_st_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 642:17] node _io_resp_ae_inst_T = not(px_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 643:23] node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 643:33] node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 643:41] connect io.resp.ae.inst, _io_resp_ae_inst_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 643:19] node _io_resp_ma_ld_T = and(misaligned, cmd_read) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 645:31] connect io.resp.ma.ld, _io_resp_ma_ld_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 645:17] node _io_resp_ma_st_T = and(misaligned, cmd_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 646:31] connect io.resp.ma.st, _io_resp_ma_st_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 646:17] connect io.resp.ma.inst, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 647:19] node _io_resp_cacheable_T = and(c_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 648:33] node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 648:41] connect io.resp.cacheable, _io_resp_cacheable_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 648:21] node _io_resp_must_alloc_T = and(must_alloc_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 649:43] node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 649:51] connect io.resp.must_alloc, _io_resp_must_alloc_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 649:22] node _io_resp_prefetchable_T = and(prefetchable_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 650:47] node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 650:55] node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 650:59] connect io.resp.prefetchable, _io_resp_prefetchable_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 650:24] node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 651:29] node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 651:52] node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 651:64] connect io.resp.miss, _io_resp_miss_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 651:16] node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 652:46] node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 652:23] connect io.resp.paddr, _io_resp_paddr_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 652:17] connect io.resp.size, io.req.bits.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 653:16] connect io.resp.cmd, io.req.bits.cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 654:15] node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 655:36] connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 655:22] node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 657:20] node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 657:36] node _io_resp_gpa_page_T_2 = shr(r_gpa, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 657:58] node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 657:19] node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 658:47] node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 658:82] node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 658:21] node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 659:8] connect io.resp.gpa, _io_resp_gpa_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 656:15] node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 662:29] connect io.ptw.req.valid, _io_ptw_req_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 662:20] node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 663:28] connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 663:25] connect io.ptw.req.bits.bits.addr, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 664:29] connect io.ptw.req.bits.bits.vstage1, r_vstage1_en @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 665:32] connect io.ptw.req.bits.bits.stage2, r_stage2_en @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 666:31] connect io.ptw.req.bits.bits.need_gpa, r_need_gpa @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 667:33] module MaxPeriodFibonacciLFSR : @[src/main/scala/chisel3/util/random/FibonacciLFSR.scala 65:7] input clock : Clock @[src/main/scala/chisel3/util/random/FibonacciLFSR.scala 65:7] input reset : Reset @[src/main/scala/chisel3/util/random/FibonacciLFSR.scala 65:7] output io : { flip seed : { valid : UInt<1>, bits : UInt<1>[16]}, flip increment : UInt<1>, out : UInt<1>[16]} @[src/main/scala/chisel3/util/random/PRNG.scala 42:22] wire _state_WIRE : UInt<1>[16] @[src/main/scala/chisel3/util/random/PRNG.scala 46:28] connect _state_WIRE[0], UInt<1>(0h1) @[src/main/scala/chisel3/util/random/PRNG.scala 46:28] connect _state_WIRE[1], UInt<1>(0h0) @[src/main/scala/chisel3/util/random/PRNG.scala 46:28] connect _state_WIRE[2], UInt<1>(0h0) @[src/main/scala/chisel3/util/random/PRNG.scala 46:28] connect _state_WIRE[3], UInt<1>(0h0) @[src/main/scala/chisel3/util/random/PRNG.scala 46:28] connect _state_WIRE[4], UInt<1>(0h0) @[src/main/scala/chisel3/util/random/PRNG.scala 46:28] connect _state_WIRE[5], UInt<1>(0h0) @[src/main/scala/chisel3/util/random/PRNG.scala 46:28] connect _state_WIRE[6], UInt<1>(0h0) @[src/main/scala/chisel3/util/random/PRNG.scala 46:28] connect _state_WIRE[7], UInt<1>(0h0) @[src/main/scala/chisel3/util/random/PRNG.scala 46:28] connect _state_WIRE[8], UInt<1>(0h0) @[src/main/scala/chisel3/util/random/PRNG.scala 46:28] connect _state_WIRE[9], UInt<1>(0h0) @[src/main/scala/chisel3/util/random/PRNG.scala 46:28] connect _state_WIRE[10], UInt<1>(0h0) @[src/main/scala/chisel3/util/random/PRNG.scala 46:28] connect _state_WIRE[11], UInt<1>(0h0) @[src/main/scala/chisel3/util/random/PRNG.scala 46:28] connect _state_WIRE[12], UInt<1>(0h0) @[src/main/scala/chisel3/util/random/PRNG.scala 46:28] connect _state_WIRE[13], UInt<1>(0h0) @[src/main/scala/chisel3/util/random/PRNG.scala 46:28] connect _state_WIRE[14], UInt<1>(0h0) @[src/main/scala/chisel3/util/random/PRNG.scala 46:28] connect _state_WIRE[15], UInt<1>(0h0) @[src/main/scala/chisel3/util/random/PRNG.scala 46:28] regreset state : UInt<1>[16], clock, reset, _state_WIRE @[src/main/scala/chisel3/util/random/PRNG.scala 55:49] when io.increment : @[src/main/scala/chisel3/util/random/PRNG.scala 69:22] node _T = xor(state[10], state[12]) @[src/main/scala/chisel3/util/random/LFSR.scala 15:41] node _T_1 = xor(_T, state[13]) @[src/main/scala/chisel3/util/random/LFSR.scala 15:41] node _T_2 = xor(_T_1, state[15]) @[src/main/scala/chisel3/util/random/LFSR.scala 15:41] connect state[0], _T_2 @[src/main/scala/chisel3/util/random/PRNG.scala 70:11] connect state[1], state[0] @[src/main/scala/chisel3/util/random/PRNG.scala 70:11] connect state[2], state[1] @[src/main/scala/chisel3/util/random/PRNG.scala 70:11] connect state[3], state[2] @[src/main/scala/chisel3/util/random/PRNG.scala 70:11] connect state[4], state[3] @[src/main/scala/chisel3/util/random/PRNG.scala 70:11] connect state[5], state[4] @[src/main/scala/chisel3/util/random/PRNG.scala 70:11] connect state[6], state[5] @[src/main/scala/chisel3/util/random/PRNG.scala 70:11] connect state[7], state[6] @[src/main/scala/chisel3/util/random/PRNG.scala 70:11] connect state[8], state[7] @[src/main/scala/chisel3/util/random/PRNG.scala 70:11] connect state[9], state[8] @[src/main/scala/chisel3/util/random/PRNG.scala 70:11] connect state[10], state[9] @[src/main/scala/chisel3/util/random/PRNG.scala 70:11] connect state[11], state[10] @[src/main/scala/chisel3/util/random/PRNG.scala 70:11] connect state[12], state[11] @[src/main/scala/chisel3/util/random/PRNG.scala 70:11] connect state[13], state[12] @[src/main/scala/chisel3/util/random/PRNG.scala 70:11] connect state[14], state[13] @[src/main/scala/chisel3/util/random/PRNG.scala 70:11] connect state[15], state[14] @[src/main/scala/chisel3/util/random/PRNG.scala 70:11] when io.seed.valid : @[src/main/scala/chisel3/util/random/PRNG.scala 73:22] connect state[0], io.seed.bits[0] @[src/main/scala/chisel3/util/random/PRNG.scala 74:11] connect state[1], io.seed.bits[1] @[src/main/scala/chisel3/util/random/PRNG.scala 74:11] connect state[2], io.seed.bits[2] @[src/main/scala/chisel3/util/random/PRNG.scala 74:11] connect state[3], io.seed.bits[3] @[src/main/scala/chisel3/util/random/PRNG.scala 74:11] connect state[4], io.seed.bits[4] @[src/main/scala/chisel3/util/random/PRNG.scala 74:11] connect state[5], io.seed.bits[5] @[src/main/scala/chisel3/util/random/PRNG.scala 74:11] connect state[6], io.seed.bits[6] @[src/main/scala/chisel3/util/random/PRNG.scala 74:11] connect state[7], io.seed.bits[7] @[src/main/scala/chisel3/util/random/PRNG.scala 74:11] connect state[8], io.seed.bits[8] @[src/main/scala/chisel3/util/random/PRNG.scala 74:11] connect state[9], io.seed.bits[9] @[src/main/scala/chisel3/util/random/PRNG.scala 74:11] connect state[10], io.seed.bits[10] @[src/main/scala/chisel3/util/random/PRNG.scala 74:11] connect state[11], io.seed.bits[11] @[src/main/scala/chisel3/util/random/PRNG.scala 74:11] connect state[12], io.seed.bits[12] @[src/main/scala/chisel3/util/random/PRNG.scala 74:11] connect state[13], io.seed.bits[13] @[src/main/scala/chisel3/util/random/PRNG.scala 74:11] connect state[14], io.seed.bits[14] @[src/main/scala/chisel3/util/random/PRNG.scala 74:11] connect state[15], io.seed.bits[15] @[src/main/scala/chisel3/util/random/PRNG.scala 74:11] connect io.out, state @[src/main/scala/chisel3/util/random/PRNG.scala 78:10] module Arbiter8_DCacheMetadataReq : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 133:28] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 133:28] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 133:28] output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { write : UInt<1>, addr : UInt<34>, idx : UInt<14>, way_en : UInt<1>, data : UInt<14>}}[8], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { write : UInt<1>, addr : UInt<34>, idx : UInt<14>, way_en : UInt<1>, data : UInt<14>}}, chosen : UInt<3>} @[src/main/scala/chisel3/util/Arbiter.scala 140:14] connect io.chosen, UInt<3>(0h7) @[src/main/scala/chisel3/util/Arbiter.scala 142:13] connect io.out.bits, io.in[7].bits @[src/main/scala/chisel3/util/Arbiter.scala 143:15] when io.in[6].valid : @[src/main/scala/chisel3/util/Arbiter.scala 145:26] connect io.chosen, UInt<3>(0h6) @[src/main/scala/chisel3/util/Arbiter.scala 146:17] connect io.out.bits, io.in[6].bits @[src/main/scala/chisel3/util/Arbiter.scala 147:19] when io.in[5].valid : @[src/main/scala/chisel3/util/Arbiter.scala 145:26] connect io.chosen, UInt<3>(0h5) @[src/main/scala/chisel3/util/Arbiter.scala 146:17] connect io.out.bits, io.in[5].bits @[src/main/scala/chisel3/util/Arbiter.scala 147:19] when io.in[4].valid : @[src/main/scala/chisel3/util/Arbiter.scala 145:26] connect io.chosen, UInt<3>(0h4) @[src/main/scala/chisel3/util/Arbiter.scala 146:17] connect io.out.bits, io.in[4].bits @[src/main/scala/chisel3/util/Arbiter.scala 147:19] when io.in[3].valid : @[src/main/scala/chisel3/util/Arbiter.scala 145:26] connect io.chosen, UInt<2>(0h3) @[src/main/scala/chisel3/util/Arbiter.scala 146:17] connect io.out.bits, io.in[3].bits @[src/main/scala/chisel3/util/Arbiter.scala 147:19] when io.in[2].valid : @[src/main/scala/chisel3/util/Arbiter.scala 145:26] connect io.chosen, UInt<2>(0h2) @[src/main/scala/chisel3/util/Arbiter.scala 146:17] connect io.out.bits, io.in[2].bits @[src/main/scala/chisel3/util/Arbiter.scala 147:19] when io.in[1].valid : @[src/main/scala/chisel3/util/Arbiter.scala 145:26] connect io.chosen, UInt<1>(0h1) @[src/main/scala/chisel3/util/Arbiter.scala 146:17] connect io.out.bits, io.in[1].bits @[src/main/scala/chisel3/util/Arbiter.scala 147:19] when io.in[0].valid : @[src/main/scala/chisel3/util/Arbiter.scala 145:26] connect io.chosen, UInt<1>(0h0) @[src/main/scala/chisel3/util/Arbiter.scala 146:17] connect io.out.bits, io.in[0].bits @[src/main/scala/chisel3/util/Arbiter.scala 147:19] node _grant_T = or(io.in[0].valid, io.in[1].valid) @[src/main/scala/chisel3/util/Arbiter.scala 45:68] node _grant_T_1 = or(_grant_T, io.in[2].valid) @[src/main/scala/chisel3/util/Arbiter.scala 45:68] node _grant_T_2 = or(_grant_T_1, io.in[3].valid) @[src/main/scala/chisel3/util/Arbiter.scala 45:68] node _grant_T_3 = or(_grant_T_2, io.in[4].valid) @[src/main/scala/chisel3/util/Arbiter.scala 45:68] node _grant_T_4 = or(_grant_T_3, io.in[5].valid) @[src/main/scala/chisel3/util/Arbiter.scala 45:68] node _grant_T_5 = or(_grant_T_4, io.in[6].valid) @[src/main/scala/chisel3/util/Arbiter.scala 45:68] node grant_1 = eq(io.in[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Arbiter.scala 45:78] node grant_2 = eq(_grant_T, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Arbiter.scala 45:78] node grant_3 = eq(_grant_T_1, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Arbiter.scala 45:78] node grant_4 = eq(_grant_T_2, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Arbiter.scala 45:78] node grant_5 = eq(_grant_T_3, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Arbiter.scala 45:78] node grant_6 = eq(_grant_T_4, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Arbiter.scala 45:78] node grant_7 = eq(_grant_T_5, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Arbiter.scala 45:78] node _io_in_0_ready_T = and(UInt<1>(0h1), io.out.ready) @[src/main/scala/chisel3/util/Arbiter.scala 153:19] connect io.in[0].ready, _io_in_0_ready_T @[src/main/scala/chisel3/util/Arbiter.scala 153:14] node _io_in_1_ready_T = and(grant_1, io.out.ready) @[src/main/scala/chisel3/util/Arbiter.scala 153:19] connect io.in[1].ready, _io_in_1_ready_T @[src/main/scala/chisel3/util/Arbiter.scala 153:14] node _io_in_2_ready_T = and(grant_2, io.out.ready) @[src/main/scala/chisel3/util/Arbiter.scala 153:19] connect io.in[2].ready, _io_in_2_ready_T @[src/main/scala/chisel3/util/Arbiter.scala 153:14] node _io_in_3_ready_T = and(grant_3, io.out.ready) @[src/main/scala/chisel3/util/Arbiter.scala 153:19] connect io.in[3].ready, _io_in_3_ready_T @[src/main/scala/chisel3/util/Arbiter.scala 153:14] node _io_in_4_ready_T = and(grant_4, io.out.ready) @[src/main/scala/chisel3/util/Arbiter.scala 153:19] connect io.in[4].ready, _io_in_4_ready_T @[src/main/scala/chisel3/util/Arbiter.scala 153:14] node _io_in_5_ready_T = and(grant_5, io.out.ready) @[src/main/scala/chisel3/util/Arbiter.scala 153:19] connect io.in[5].ready, _io_in_5_ready_T @[src/main/scala/chisel3/util/Arbiter.scala 153:14] node _io_in_6_ready_T = and(grant_6, io.out.ready) @[src/main/scala/chisel3/util/Arbiter.scala 153:19] connect io.in[6].ready, _io_in_6_ready_T @[src/main/scala/chisel3/util/Arbiter.scala 153:14] node _io_in_7_ready_T = and(grant_7, io.out.ready) @[src/main/scala/chisel3/util/Arbiter.scala 153:19] connect io.in[7].ready, _io_in_7_ready_T @[src/main/scala/chisel3/util/Arbiter.scala 153:14] node _io_out_valid_T = eq(grant_7, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Arbiter.scala 154:19] node _io_out_valid_T_1 = or(_io_out_valid_T, io.in[7].valid) @[src/main/scala/chisel3/util/Arbiter.scala 154:31] connect io.out.valid, _io_out_valid_T_1 @[src/main/scala/chisel3/util/Arbiter.scala 154:16] module DCacheDataArray : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 47:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 47:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 47:7] output io : { flip req : { valid : UInt<1>, bits : { addr : UInt<20>, write : UInt<1>, wdata : UInt<64>, wordMask : UInt<1>, eccMask : UInt<8>, way_en : UInt<1>}}, resp : UInt<64>[1]} @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 48:14] node eccMask_0 = bits(io.req.bits.eccMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 54:82] node eccMask_1 = bits(io.req.bits.eccMask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 54:82] node eccMask_2 = bits(io.req.bits.eccMask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 54:82] node eccMask_3 = bits(io.req.bits.eccMask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 54:82] node eccMask_4 = bits(io.req.bits.eccMask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 54:82] node eccMask_5 = bits(io.req.bits.eccMask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 54:82] node eccMask_6 = bits(io.req.bits.eccMask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 54:82] node eccMask_7 = bits(io.req.bits.eccMask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 54:82] node wWords_0 = bits(io.req.bits.wdata, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node addr = shr(io.req.bits.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 57:31] smem rockettile_dcache_data_arrays_0 : UInt<8>[8] [131072] @[hardware/upstream/rocket-chip/src/main/scala/util/DescribedSRAM.scala 17:26] node _rdata_valid_T = bits(io.req.bits.wordMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 69:83] node _rdata_valid_T_1 = or(UInt<1>(0h1), _rdata_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 69:60] node rdata_valid = and(io.req.valid, _rdata_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 69:30] node _rdata_T = and(rdata_valid, io.req.bits.write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 70:17] when _rdata_T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 70:39] node rdata_wData_0 = bits(wWords_0, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node rdata_wData_1 = bits(wWords_0, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node rdata_wData_2 = bits(wWords_0, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node rdata_wData_3 = bits(wWords_0, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node rdata_wData_4 = bits(wWords_0, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node rdata_wData_5 = bits(wWords_0, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node rdata_wData_6 = bits(wWords_0, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node rdata_wData_7 = bits(wWords_0, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] wire _rdata_WIRE : UInt<8>[8] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:32] connect _rdata_WIRE[0], rdata_wData_0 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:32] connect _rdata_WIRE[1], rdata_wData_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:32] connect _rdata_WIRE[2], rdata_wData_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:32] connect _rdata_WIRE[3], rdata_wData_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:32] connect _rdata_WIRE[4], rdata_wData_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:32] connect _rdata_WIRE[5], rdata_wData_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:32] connect _rdata_WIRE[6], rdata_wData_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:32] connect _rdata_WIRE[7], rdata_wData_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:32] write mport rdata_MPORT = rockettile_dcache_data_arrays_0[addr], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:18] when eccMask_0 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:18] connect rdata_MPORT[0], _rdata_WIRE[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:18] when eccMask_1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:18] connect rdata_MPORT[1], _rdata_WIRE[1] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:18] when eccMask_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:18] connect rdata_MPORT[2], _rdata_WIRE[2] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:18] when eccMask_3 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:18] connect rdata_MPORT[3], _rdata_WIRE[3] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:18] when eccMask_4 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:18] connect rdata_MPORT[4], _rdata_WIRE[4] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:18] when eccMask_5 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:18] connect rdata_MPORT[5], _rdata_WIRE[5] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:18] when eccMask_6 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:18] connect rdata_MPORT[6], _rdata_WIRE[6] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:18] when eccMask_7 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:18] connect rdata_MPORT[7], _rdata_WIRE[7] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 73:18] node _rdata_data_T = eq(io.req.bits.write, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 75:42] node _rdata_data_T_1 = and(rdata_valid, _rdata_data_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 75:39] wire _rdata_data_WIRE : UInt<17> @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 75:26] invalidate _rdata_data_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 75:26] when _rdata_data_T_1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 75:26] connect _rdata_data_WIRE, addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 75:26] read mport rdata_data = rockettile_dcache_data_arrays_0[_rdata_data_WIRE], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 75:26] node rdata_lo_lo = cat(rdata_data[1], rdata_data[0]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node rdata_lo_hi = cat(rdata_data[3], rdata_data[2]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node rdata_lo = cat(rdata_lo_hi, rdata_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node rdata_hi_lo = cat(rdata_data[5], rdata_data[4]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node rdata_hi_hi = cat(rdata_data[7], rdata_data[6]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node rdata_hi = cat(rdata_hi_hi, rdata_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node rdata_0_0 = cat(rdata_hi, rdata_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] connect io.resp[0], rdata_0_0 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 78:69] module Arbiter4_DCacheDataReq : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 150:28] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 150:28] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 150:28] output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<20>, write : UInt<1>, wdata : UInt<64>, wordMask : UInt<1>, eccMask : UInt<8>, way_en : UInt<1>}}[4], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<20>, write : UInt<1>, wdata : UInt<64>, wordMask : UInt<1>, eccMask : UInt<8>, way_en : UInt<1>}}, chosen : UInt<2>} @[src/main/scala/chisel3/util/Arbiter.scala 140:14] connect io.chosen, UInt<2>(0h3) @[src/main/scala/chisel3/util/Arbiter.scala 142:13] connect io.out.bits, io.in[3].bits @[src/main/scala/chisel3/util/Arbiter.scala 143:15] when io.in[2].valid : @[src/main/scala/chisel3/util/Arbiter.scala 145:26] connect io.chosen, UInt<2>(0h2) @[src/main/scala/chisel3/util/Arbiter.scala 146:17] connect io.out.bits, io.in[2].bits @[src/main/scala/chisel3/util/Arbiter.scala 147:19] when io.in[1].valid : @[src/main/scala/chisel3/util/Arbiter.scala 145:26] connect io.chosen, UInt<1>(0h1) @[src/main/scala/chisel3/util/Arbiter.scala 146:17] connect io.out.bits, io.in[1].bits @[src/main/scala/chisel3/util/Arbiter.scala 147:19] when io.in[0].valid : @[src/main/scala/chisel3/util/Arbiter.scala 145:26] connect io.chosen, UInt<1>(0h0) @[src/main/scala/chisel3/util/Arbiter.scala 146:17] connect io.out.bits, io.in[0].bits @[src/main/scala/chisel3/util/Arbiter.scala 147:19] node _grant_T = or(io.in[0].valid, io.in[1].valid) @[src/main/scala/chisel3/util/Arbiter.scala 45:68] node _grant_T_1 = or(_grant_T, io.in[2].valid) @[src/main/scala/chisel3/util/Arbiter.scala 45:68] node grant_1 = eq(io.in[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Arbiter.scala 45:78] node grant_2 = eq(_grant_T, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Arbiter.scala 45:78] node grant_3 = eq(_grant_T_1, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Arbiter.scala 45:78] node _io_in_0_ready_T = and(UInt<1>(0h1), io.out.ready) @[src/main/scala/chisel3/util/Arbiter.scala 153:19] connect io.in[0].ready, _io_in_0_ready_T @[src/main/scala/chisel3/util/Arbiter.scala 153:14] node _io_in_1_ready_T = and(grant_1, io.out.ready) @[src/main/scala/chisel3/util/Arbiter.scala 153:19] connect io.in[1].ready, _io_in_1_ready_T @[src/main/scala/chisel3/util/Arbiter.scala 153:14] node _io_in_2_ready_T = and(grant_2, io.out.ready) @[src/main/scala/chisel3/util/Arbiter.scala 153:19] connect io.in[2].ready, _io_in_2_ready_T @[src/main/scala/chisel3/util/Arbiter.scala 153:14] node _io_in_3_ready_T = and(grant_3, io.out.ready) @[src/main/scala/chisel3/util/Arbiter.scala 153:19] connect io.in[3].ready, _io_in_3_ready_T @[src/main/scala/chisel3/util/Arbiter.scala 153:14] node _io_out_valid_T = eq(grant_3, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Arbiter.scala 154:19] node _io_out_valid_T_1 = or(_io_out_valid_T, io.in[3].valid) @[src/main/scala/chisel3/util/Arbiter.scala 154:31] connect io.out.valid, _io_out_valid_T_1 @[src/main/scala/chisel3/util/Arbiter.scala 154:16] module AMOALU : @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 54:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 54:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 54:7] output io : { flip mask : UInt<8>, flip cmd : UInt<5>, flip lhs : UInt<64>, flip rhs : UInt<64>, out : UInt<64>, out_unmasked : UInt<64>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 58:14] node _max_T = eq(io.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 67:20] node _max_T_1 = eq(io.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 67:43] node max = or(_max_T, _max_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 67:33] node _min_T = eq(io.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 68:20] node _min_T_1 = eq(io.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 68:43] node min = or(_min_T, _min_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 68:33] node add = eq(io.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 69:20] node _logic_and_T = eq(io.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 70:26] node _logic_and_T_1 = eq(io.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 70:48] node logic_and = or(_logic_and_T, _logic_and_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 70:38] node _logic_xor_T = eq(io.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 71:26] node _logic_xor_T_1 = eq(io.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 71:49] node logic_xor = or(_logic_xor_T, _logic_xor_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 71:39] node _adder_out_mask_T = bits(io.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 75:69] node _adder_out_mask_T_1 = eq(_adder_out_mask_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 75:61] node _adder_out_mask_T_2 = shl(_adder_out_mask_T_1, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 75:77] node _adder_out_mask_T_3 = or(UInt<64>(0h0), _adder_out_mask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 75:96] node adder_out_mask = not(_adder_out_mask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 75:16] node _adder_out_T = and(io.lhs, adder_out_mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 76:13] node _adder_out_T_1 = and(io.rhs, adder_out_mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 76:31] node _adder_out_T_2 = add(_adder_out_T, _adder_out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 76:21] node adder_out = tail(_adder_out_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 76:21] node _less_T = bits(io.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 94:49] node less_signed_mask = xor(UInt<4>(0hc), UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 88:29] node _less_signed_T = and(io.cmd, less_signed_mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 89:17] node _less_signed_T_1 = and(UInt<4>(0hc), less_signed_mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 89:39] node less_signed = eq(_less_signed_T, _less_signed_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 89:25] node _less_T_1 = bits(io.lhs, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 91:12] node _less_T_2 = bits(io.rhs, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 91:23] node _less_T_3 = eq(_less_T_1, _less_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 91:18] node _less_T_4 = bits(io.lhs, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 83:13] node _less_T_5 = bits(io.rhs, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 83:27] node _less_T_6 = lt(_less_T_4, _less_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 83:24] node _less_T_7 = bits(io.lhs, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 83:42] node _less_T_8 = bits(io.rhs, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 83:58] node _less_T_9 = eq(_less_T_7, _less_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 83:53] node _less_T_10 = bits(io.lhs, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 82:26] node _less_T_11 = bits(io.rhs, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 82:38] node _less_T_12 = lt(_less_T_10, _less_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 82:35] node _less_T_13 = and(_less_T_9, _less_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 83:69] node _less_T_14 = or(_less_T_6, _less_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 83:38] node _less_T_15 = bits(io.lhs, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 91:68] node _less_T_16 = bits(io.rhs, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 91:76] node _less_T_17 = mux(less_signed, _less_T_15, _less_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 91:58] node _less_T_18 = mux(_less_T_3, _less_T_14, _less_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 91:10] node _less_T_19 = bits(io.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 94:49] node less_signed_mask_1 = xor(UInt<4>(0hc), UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 88:29] node _less_signed_T_2 = and(io.cmd, less_signed_mask_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 89:17] node _less_signed_T_3 = and(UInt<4>(0hc), less_signed_mask_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 89:39] node less_signed_1 = eq(_less_signed_T_2, _less_signed_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 89:25] node _less_T_20 = bits(io.lhs, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 91:12] node _less_T_21 = bits(io.rhs, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 91:23] node _less_T_22 = eq(_less_T_20, _less_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 91:18] node _less_T_23 = bits(io.lhs, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 82:26] node _less_T_24 = bits(io.rhs, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 82:38] node _less_T_25 = lt(_less_T_23, _less_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 82:35] node _less_T_26 = bits(io.lhs, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 91:68] node _less_T_27 = bits(io.rhs, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 91:76] node _less_T_28 = mux(less_signed_1, _less_T_26, _less_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 91:58] node _less_T_29 = mux(_less_T_22, _less_T_25, _less_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 91:10] node less = mux(_less_T, _less_T_18, _less_T_29) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _minmax_T = mux(less, min, max) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 97:23] node minmax = mux(_minmax_T, io.lhs, io.rhs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 97:19] node _logic_T = and(io.lhs, io.rhs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 99:27] node _logic_T_1 = mux(logic_and, _logic_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 99:8] node _logic_T_2 = xor(io.lhs, io.rhs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 100:27] node _logic_T_3 = mux(logic_xor, _logic_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 100:8] node logic = or(_logic_T_1, _logic_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 99:42] node _out_T = or(logic_and, logic_xor) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 103:19] node _out_T_1 = mux(_out_T, logic, minmax) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 103:8] node out = mux(add, adder_out, _out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 102:8] node _wmask_T = bits(io.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node _wmask_T_1 = bits(io.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node _wmask_T_2 = bits(io.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node _wmask_T_3 = bits(io.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node _wmask_T_4 = bits(io.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node _wmask_T_5 = bits(io.mask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node _wmask_T_6 = bits(io.mask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node _wmask_T_7 = bits(io.mask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node _wmask_T_8 = mux(_wmask_T, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node _wmask_T_9 = mux(_wmask_T_1, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node _wmask_T_10 = mux(_wmask_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node _wmask_T_11 = mux(_wmask_T_3, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node _wmask_T_12 = mux(_wmask_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node _wmask_T_13 = mux(_wmask_T_5, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node _wmask_T_14 = mux(_wmask_T_6, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node _wmask_T_15 = mux(_wmask_T_7, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node wmask_lo_lo = cat(_wmask_T_9, _wmask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node wmask_lo_hi = cat(_wmask_T_11, _wmask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node wmask_lo = cat(wmask_lo_hi, wmask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node wmask_hi_lo = cat(_wmask_T_13, _wmask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node wmask_hi_hi = cat(_wmask_T_15, _wmask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node wmask_hi = cat(wmask_hi_hi, wmask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node wmask = cat(wmask_hi, wmask_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 106:30] node _io_out_T = and(wmask, out) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 107:19] node _io_out_T_1 = not(wmask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 107:27] node _io_out_T_2 = and(_io_out_T_1, io.lhs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 107:34] node _io_out_T_3 = or(_io_out_T, _io_out_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 107:25] connect io.out, _io_out_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 107:10] connect io.out_unmasked, out @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 108:19] module DCache : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 99:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 99:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 99:7] output auto : { flip mmio_address_prefix_sink_in : UInt<1>, flip hart_id_sink_in : UInt<1>, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output io : { flip cpu : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<34>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<21>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<33>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, errors : { bus : { valid : UInt<1>, bits : UInt<32>}}, tlb_port : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<34>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, s1_resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<34>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip s2_kill : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 243:14] wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire hartIdSinkNodeOptIn : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate hartIdSinkNodeOptIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire mmioAddressPrefixSinkNodeOptIn : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate mmioAddressPrefixSinkNodeOptIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect hartIdSinkNodeOptIn, auto.hart_id_sink_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect mmioAddressPrefixSinkNodeOptIn, auto.mmio_address_prefix_sink_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] reg clock_en_reg : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 109:25] connect io.cpu.clock_enabled, clock_en_reg @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 110:24] inst tlb of DTLB @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 117:19] connect tlb.clock, clock connect tlb.reset, reset inst pma_checker of DTLB_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 118:27] connect pma_checker.clock, clock connect pma_checker.reset, reset wire replace : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 37:29] connect replace, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 38:11] inst lfsr_prng of MaxPeriodFibonacciLFSR @[src/main/scala/chisel3/util/random/PRNG.scala 91:22] connect lfsr_prng.clock, clock connect lfsr_prng.reset, reset connect lfsr_prng.io.seed.valid, UInt<1>(0h0) @[src/main/scala/chisel3/util/random/PRNG.scala 92:24] invalidate lfsr_prng.io.seed.bits[0] @[src/main/scala/chisel3/util/random/PRNG.scala 93:23] invalidate lfsr_prng.io.seed.bits[1] @[src/main/scala/chisel3/util/random/PRNG.scala 93:23] invalidate lfsr_prng.io.seed.bits[2] @[src/main/scala/chisel3/util/random/PRNG.scala 93:23] invalidate lfsr_prng.io.seed.bits[3] @[src/main/scala/chisel3/util/random/PRNG.scala 93:23] invalidate lfsr_prng.io.seed.bits[4] @[src/main/scala/chisel3/util/random/PRNG.scala 93:23] invalidate lfsr_prng.io.seed.bits[5] @[src/main/scala/chisel3/util/random/PRNG.scala 93:23] invalidate lfsr_prng.io.seed.bits[6] @[src/main/scala/chisel3/util/random/PRNG.scala 93:23] invalidate lfsr_prng.io.seed.bits[7] @[src/main/scala/chisel3/util/random/PRNG.scala 93:23] invalidate lfsr_prng.io.seed.bits[8] @[src/main/scala/chisel3/util/random/PRNG.scala 93:23] invalidate lfsr_prng.io.seed.bits[9] @[src/main/scala/chisel3/util/random/PRNG.scala 93:23] invalidate lfsr_prng.io.seed.bits[10] @[src/main/scala/chisel3/util/random/PRNG.scala 93:23] invalidate lfsr_prng.io.seed.bits[11] @[src/main/scala/chisel3/util/random/PRNG.scala 93:23] invalidate lfsr_prng.io.seed.bits[12] @[src/main/scala/chisel3/util/random/PRNG.scala 93:23] invalidate lfsr_prng.io.seed.bits[13] @[src/main/scala/chisel3/util/random/PRNG.scala 93:23] invalidate lfsr_prng.io.seed.bits[14] @[src/main/scala/chisel3/util/random/PRNG.scala 93:23] invalidate lfsr_prng.io.seed.bits[15] @[src/main/scala/chisel3/util/random/PRNG.scala 93:23] connect lfsr_prng.io.increment, replace @[src/main/scala/chisel3/util/random/PRNG.scala 94:23] node lfsr_lo_lo_lo = cat(lfsr_prng.io.out[1], lfsr_prng.io.out[0]) @[src/main/scala/chisel3/util/random/PRNG.scala 95:17] node lfsr_lo_lo_hi = cat(lfsr_prng.io.out[3], lfsr_prng.io.out[2]) @[src/main/scala/chisel3/util/random/PRNG.scala 95:17] node lfsr_lo_lo = cat(lfsr_lo_lo_hi, lfsr_lo_lo_lo) @[src/main/scala/chisel3/util/random/PRNG.scala 95:17] node lfsr_lo_hi_lo = cat(lfsr_prng.io.out[5], lfsr_prng.io.out[4]) @[src/main/scala/chisel3/util/random/PRNG.scala 95:17] node lfsr_lo_hi_hi = cat(lfsr_prng.io.out[7], lfsr_prng.io.out[6]) @[src/main/scala/chisel3/util/random/PRNG.scala 95:17] node lfsr_lo_hi = cat(lfsr_lo_hi_hi, lfsr_lo_hi_lo) @[src/main/scala/chisel3/util/random/PRNG.scala 95:17] node lfsr_lo = cat(lfsr_lo_hi, lfsr_lo_lo) @[src/main/scala/chisel3/util/random/PRNG.scala 95:17] node lfsr_hi_lo_lo = cat(lfsr_prng.io.out[9], lfsr_prng.io.out[8]) @[src/main/scala/chisel3/util/random/PRNG.scala 95:17] node lfsr_hi_lo_hi = cat(lfsr_prng.io.out[11], lfsr_prng.io.out[10]) @[src/main/scala/chisel3/util/random/PRNG.scala 95:17] node lfsr_hi_lo = cat(lfsr_hi_lo_hi, lfsr_hi_lo_lo) @[src/main/scala/chisel3/util/random/PRNG.scala 95:17] node lfsr_hi_hi_lo = cat(lfsr_prng.io.out[13], lfsr_prng.io.out[12]) @[src/main/scala/chisel3/util/random/PRNG.scala 95:17] node lfsr_hi_hi_hi = cat(lfsr_prng.io.out[15], lfsr_prng.io.out[14]) @[src/main/scala/chisel3/util/random/PRNG.scala 95:17] node lfsr_hi_hi = cat(lfsr_hi_hi_hi, lfsr_hi_hi_lo) @[src/main/scala/chisel3/util/random/PRNG.scala 95:17] node lfsr_hi = cat(lfsr_hi_hi, lfsr_hi_lo) @[src/main/scala/chisel3/util/random/PRNG.scala 95:17] node lfsr = cat(lfsr_hi, lfsr_lo) @[src/main/scala/chisel3/util/random/PRNG.scala 95:17] inst metaArb of Arbiter8_DCacheMetadataReq @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 133:23] connect metaArb.clock, clock connect metaArb.reset, reset smem rockettile_dcache_tag_array : UInt<14>[1] [16384] @[hardware/upstream/rocket-chip/src/main/scala/util/DescribedSRAM.scala 17:26] inst data of DCacheDataArray @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 143:20] connect data.clock, clock connect data.reset, reset inst dataArb of Arbiter4_DCacheDataReq @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 150:23] connect dataArb.clock, clock connect dataArb.reset, reset connect dataArb.io.in[1].bits.wdata, dataArb.io.in[0].bits.wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 151:43] connect dataArb.io.in[2].bits.wdata, dataArb.io.in[0].bits.wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 151:43] connect dataArb.io.in[3].bits.wdata, dataArb.io.in[0].bits.wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 151:43] connect data.io.req.bits, dataArb.io.out.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 152:20] connect data.io.req.valid, dataArb.io.out.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 153:21] connect dataArb.io.out.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 154:24] connect metaArb.io.out.ready, clock_en_reg @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 155:24] wire tl_out_a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 157:22] wire nodeOut_a_deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[src/main/scala/chisel3/util/Decoupled.scala 356:21] connect nodeOut_a_deq.valid, tl_out_a.valid @[src/main/scala/chisel3/util/Decoupled.scala 357:17] connect nodeOut_a_deq.bits, tl_out_a.bits @[src/main/scala/chisel3/util/Decoupled.scala 358:16] connect tl_out_a.ready, nodeOut_a_deq.ready @[src/main/scala/chisel3/util/Decoupled.scala 359:17] connect nodeOut.a, nodeOut_a_deq @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 158:12] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire tl_out_c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect tl_out_c.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect tl_out_c.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect tl_out_c.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _s1_valid_T = and(io.cpu.req.ready, io.cpu.req.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] regreset s1_valid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 180:25] connect s1_valid, _s1_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 180:25] wire _s1_probe_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _s1_probe_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _s1_probe_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _s1_probe_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _s1_probe_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _s1_probe_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _s1_probe_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _s1_probe_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _s1_probe_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _s1_probe_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _s1_probe_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _s1_probe_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _s1_probe_WIRE_1.bits, _s1_probe_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _s1_probe_WIRE_1.valid, _s1_probe_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _s1_probe_WIRE_1.ready, _s1_probe_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _s1_probe_T = and(_s1_probe_WIRE_1.ready, _s1_probe_WIRE_1.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] regreset s1_probe : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 181:25] connect s1_probe, _s1_probe_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 181:25] wire _probe_bits_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _probe_bits_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _probe_bits_WIRE_1.bits, _probe_bits_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _probe_bits_WIRE_1.valid, _probe_bits_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _probe_bits_WIRE_1.ready, _probe_bits_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire _probe_bits_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE_2.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _probe_bits_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _probe_bits_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _probe_bits_WIRE_3.bits, _probe_bits_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _probe_bits_WIRE_3.valid, _probe_bits_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _probe_bits_WIRE_3.ready, _probe_bits_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _probe_bits_T = and(_probe_bits_WIRE_3.ready, _probe_bits_WIRE_3.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] reg probe_bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 182:29] when _probe_bits_T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 182:29] connect probe_bits, _probe_bits_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 182:29] wire s1_nack : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 183:28] connect s1_nack, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 183:28] node _s1_valid_masked_T = eq(io.cpu.s1_kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 184:37] node s1_valid_masked = and(s1_valid, _s1_valid_masked_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 184:34] node _s1_valid_not_nacked_T = eq(s1_nack, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 185:41] node s1_valid_not_nacked = and(s1_valid, _s1_valid_not_nacked_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 185:38] node _s1_tlb_req_valid_T = and(io.tlb_port.req.ready, io.tlb_port.req.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] regreset s1_tlb_req_valid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 186:33] connect s1_tlb_req_valid, _s1_tlb_req_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 186:33] regreset s2_tlb_req_valid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 187:33] connect s2_tlb_req_valid, s1_tlb_req_valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 187:33] node _s0_clk_en_T = eq(metaArb.io.out.bits.write, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 188:43] node s0_clk_en = and(metaArb.io.out.valid, _s0_clk_en_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 188:40] wire s0_req : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 190:24] connect s0_req, io.cpu.req.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 190:24] node _s0_req_addr_T = shr(metaArb.io.out.bits.addr, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 191:47] node _s0_req_addr_T_1 = bits(io.cpu.req.bits.addr, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 191:84] node _s0_req_addr_T_2 = cat(_s0_req_addr_T, _s0_req_addr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 191:21] connect s0_req.addr, _s0_req_addr_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 191:15] node _T = eq(metaArb.io.in[7].ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 193:9] when _T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 193:34] connect s0_req.phys, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 193:48] reg s1_req : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 194:25] when s0_clk_en : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 194:25] connect s1_req, s0_req @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 194:25] node _s1_vaddr_T = shr(s1_req.addr, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 195:56] node _s1_vaddr_T_1 = bits(s1_req.addr, 19, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 195:78] node s1_vaddr = cat(_s1_vaddr_T, _s1_vaddr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 195:21] wire s0_tlb_req : { vaddr : UInt<34>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 197:28] connect s0_tlb_req, io.tlb_port.req.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 197:28] node _T_1 = and(io.tlb_port.req.ready, io.tlb_port.req.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_2 = eq(_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 198:9] when _T_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 198:32] connect s0_tlb_req.passthrough, s0_req.phys @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 199:28] connect s0_tlb_req.vaddr, s0_req.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 200:22] connect s0_tlb_req.size, s0_req.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 201:21] connect s0_tlb_req.cmd, s0_req.cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 202:20] connect s0_tlb_req.prv, s0_req.dprv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 203:20] connect s0_tlb_req.v, s0_req.dv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 204:18] node _s1_tlb_req_T = or(s0_clk_en, io.tlb_port.req.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 206:52] reg s1_tlb_req : { vaddr : UInt<34>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 206:29] when _s1_tlb_req_T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 206:29] connect s1_tlb_req, s0_tlb_req @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 206:29] node _s1_read_T = eq(s1_req.cmd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_read_T_1 = eq(s1_req.cmd, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_read_T_2 = eq(s1_req.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_read_T_3 = eq(s1_req.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_read_T_4 = or(_s1_read_T, _s1_read_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_read_T_5 = or(_s1_read_T_4, _s1_read_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_read_T_6 = or(_s1_read_T_5, _s1_read_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_read_T_7 = eq(s1_req.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_read_T_8 = eq(s1_req.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_read_T_9 = eq(s1_req.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_read_T_10 = eq(s1_req.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_read_T_11 = or(_s1_read_T_7, _s1_read_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_read_T_12 = or(_s1_read_T_11, _s1_read_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_read_T_13 = or(_s1_read_T_12, _s1_read_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_read_T_14 = eq(s1_req.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_read_T_15 = eq(s1_req.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_read_T_16 = eq(s1_req.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_read_T_17 = eq(s1_req.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_read_T_18 = eq(s1_req.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_read_T_19 = or(_s1_read_T_14, _s1_read_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_read_T_20 = or(_s1_read_T_19, _s1_read_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_read_T_21 = or(_s1_read_T_20, _s1_read_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_read_T_22 = or(_s1_read_T_21, _s1_read_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_read_T_23 = or(_s1_read_T_13, _s1_read_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node s1_read = or(_s1_read_T_6, _s1_read_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 89:68] node _s1_write_T = eq(s1_req.cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:32] node _s1_write_T_1 = eq(s1_req.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:49] node _s1_write_T_2 = or(_s1_write_T, _s1_write_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:42] node _s1_write_T_3 = eq(s1_req.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:66] node _s1_write_T_4 = or(_s1_write_T_2, _s1_write_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:59] node _s1_write_T_5 = eq(s1_req.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_write_T_6 = eq(s1_req.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_write_T_7 = eq(s1_req.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_write_T_8 = eq(s1_req.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_write_T_9 = or(_s1_write_T_5, _s1_write_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_write_T_10 = or(_s1_write_T_9, _s1_write_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_write_T_11 = or(_s1_write_T_10, _s1_write_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_write_T_12 = eq(s1_req.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_write_T_13 = eq(s1_req.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_write_T_14 = eq(s1_req.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_write_T_15 = eq(s1_req.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_write_T_16 = eq(s1_req.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_write_T_17 = or(_s1_write_T_12, _s1_write_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_write_T_18 = or(_s1_write_T_17, _s1_write_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_write_T_19 = or(_s1_write_T_18, _s1_write_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_write_T_20 = or(_s1_write_T_19, _s1_write_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_write_T_21 = or(_s1_write_T_11, _s1_write_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node s1_write = or(_s1_write_T_4, _s1_write_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:76] node s1_readwrite = or(s1_read, s1_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 210:30] node _s1_sfence_T = eq(s1_req.cmd, UInt<5>(0h14)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 211:30] node _s1_sfence_T_1 = eq(s1_req.cmd, UInt<5>(0h15)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 211:57] node _s1_sfence_T_2 = or(_s1_sfence_T, _s1_sfence_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 211:43] node _s1_sfence_T_3 = eq(s1_req.cmd, UInt<5>(0h16)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 211:85] node s1_sfence = or(_s1_sfence_T_2, _s1_sfence_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 211:71] node _s1_flush_line_T = eq(s1_req.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 212:34] node _s1_flush_line_T_1 = bits(s1_req.size, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 212:64] node s1_flush_line = and(_s1_flush_line_T, _s1_flush_line_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 212:50] reg s1_flush_valid : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 213:27] wire s1_waw_hazard : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 214:27] regreset flushed : UInt<1>, clock, reset, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 218:24] regreset flushing : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 219:25] reg flushing_req : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 220:25] regreset cached_grant_wait : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 221:34] regreset resetting : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 222:26] regreset flushCounter : UInt<14>, clock, reset, UInt<14>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 223:29] regreset release_ack_wait : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 224:33] reg release_ack_addr : UInt<32>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 225:29] regreset release_state : UInt<4>, clock, reset, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 226:30] reg refill_way : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 227:23] wire any_pstore_valid : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 228:30] node _inWriteback_T = eq(release_state, UInt<4>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _inWriteback_T_1 = eq(release_state, UInt<4>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node inWriteback = or(_inWriteback_T, _inWriteback_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] wire releaseWay : UInt @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 230:24] node _io_cpu_req_ready_T = eq(release_state, UInt<4>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 231:38] node _io_cpu_req_ready_T_1 = eq(cached_grant_wait, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 231:54] node _io_cpu_req_ready_T_2 = and(_io_cpu_req_ready_T, _io_cpu_req_ready_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 231:51] node _io_cpu_req_ready_T_3 = eq(s1_nack, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 231:76] node _io_cpu_req_ready_T_4 = and(_io_cpu_req_ready_T_2, _io_cpu_req_ready_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 231:73] connect io.cpu.req.ready, _io_cpu_req_ready_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 231:20] wire _uncachedInFlight_WIRE : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 234:41] connect _uncachedInFlight_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 234:41] regreset uncachedInFlight : UInt<1>[1], clock, reset, _uncachedInFlight_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 234:33] reg uncachedReqs : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}[1], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 235:25] wire uncachedResp : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 236:30] invalidate uncachedResp.mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 236:30] invalidate uncachedResp.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 236:30] invalidate uncachedResp.no_xcpt @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 236:30] invalidate uncachedResp.no_alloc @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 236:30] invalidate uncachedResp.no_resp @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 236:30] invalidate uncachedResp.phys @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 236:30] invalidate uncachedResp.dv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 236:30] invalidate uncachedResp.dprv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 236:30] invalidate uncachedResp.signed @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 236:30] invalidate uncachedResp.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 236:30] invalidate uncachedResp.cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 236:30] invalidate uncachedResp.tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 236:30] invalidate uncachedResp.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 236:30] node _s0_read_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s0_read_T_1 = eq(io.cpu.req.bits.cmd, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s0_read_T_2 = eq(io.cpu.req.bits.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s0_read_T_3 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s0_read_T_4 = or(_s0_read_T, _s0_read_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s0_read_T_5 = or(_s0_read_T_4, _s0_read_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s0_read_T_6 = or(_s0_read_T_5, _s0_read_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s0_read_T_7 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s0_read_T_8 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s0_read_T_9 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s0_read_T_10 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s0_read_T_11 = or(_s0_read_T_7, _s0_read_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s0_read_T_12 = or(_s0_read_T_11, _s0_read_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s0_read_T_13 = or(_s0_read_T_12, _s0_read_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s0_read_T_14 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s0_read_T_15 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s0_read_T_16 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s0_read_T_17 = eq(io.cpu.req.bits.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s0_read_T_18 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s0_read_T_19 = or(_s0_read_T_14, _s0_read_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s0_read_T_20 = or(_s0_read_T_19, _s0_read_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s0_read_T_21 = or(_s0_read_T_20, _s0_read_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s0_read_T_22 = or(_s0_read_T_21, _s0_read_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s0_read_T_23 = or(_s0_read_T_13, _s0_read_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node s0_read = or(_s0_read_T_6, _s0_read_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 89:68] node _dataArb_io_in_3_valid_res_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_res_T_1 = eq(io.cpu.req.bits.cmd, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_res_T_2 = or(_dataArb_io_in_3_valid_res_T, _dataArb_io_in_3_valid_res_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_3_valid_res_T_3 = eq(_dataArb_io_in_3_valid_res_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1183:15] node _dataArb_io_in_3_valid_res_T_4 = lt(io.cpu.req.bits.size, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1183:58] node dataArb_io_in_3_valid_res = or(_dataArb_io_in_3_valid_res_T_3, _dataArb_io_in_3_valid_res_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1183:46] node _dataArb_io_in_3_valid_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_1 = eq(io.cpu.req.bits.cmd, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_2 = eq(io.cpu.req.bits.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_3 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_4 = or(_dataArb_io_in_3_valid_T, _dataArb_io_in_3_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_3_valid_T_5 = or(_dataArb_io_in_3_valid_T_4, _dataArb_io_in_3_valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_3_valid_T_6 = or(_dataArb_io_in_3_valid_T_5, _dataArb_io_in_3_valid_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_3_valid_T_7 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_8 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_9 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_10 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_11 = or(_dataArb_io_in_3_valid_T_7, _dataArb_io_in_3_valid_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_3_valid_T_12 = or(_dataArb_io_in_3_valid_T_11, _dataArb_io_in_3_valid_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_3_valid_T_13 = or(_dataArb_io_in_3_valid_T_12, _dataArb_io_in_3_valid_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_3_valid_T_14 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_15 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_16 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_17 = eq(io.cpu.req.bits.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_18 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_19 = or(_dataArb_io_in_3_valid_T_14, _dataArb_io_in_3_valid_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_3_valid_T_20 = or(_dataArb_io_in_3_valid_T_19, _dataArb_io_in_3_valid_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_3_valid_T_21 = or(_dataArb_io_in_3_valid_T_20, _dataArb_io_in_3_valid_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_3_valid_T_22 = or(_dataArb_io_in_3_valid_T_21, _dataArb_io_in_3_valid_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_3_valid_T_23 = or(_dataArb_io_in_3_valid_T_13, _dataArb_io_in_3_valid_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node _dataArb_io_in_3_valid_T_24 = or(_dataArb_io_in_3_valid_T_6, _dataArb_io_in_3_valid_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 89:68] node _dataArb_io_in_3_valid_T_25 = eq(io.cpu.req.bits.cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:32] node _dataArb_io_in_3_valid_T_26 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:49] node _dataArb_io_in_3_valid_T_27 = or(_dataArb_io_in_3_valid_T_25, _dataArb_io_in_3_valid_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:42] node _dataArb_io_in_3_valid_T_28 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:66] node _dataArb_io_in_3_valid_T_29 = or(_dataArb_io_in_3_valid_T_27, _dataArb_io_in_3_valid_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:59] node _dataArb_io_in_3_valid_T_30 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_31 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_32 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_33 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_34 = or(_dataArb_io_in_3_valid_T_30, _dataArb_io_in_3_valid_T_31) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_3_valid_T_35 = or(_dataArb_io_in_3_valid_T_34, _dataArb_io_in_3_valid_T_32) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_3_valid_T_36 = or(_dataArb_io_in_3_valid_T_35, _dataArb_io_in_3_valid_T_33) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_3_valid_T_37 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_38 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_39 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_40 = eq(io.cpu.req.bits.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_41 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _dataArb_io_in_3_valid_T_42 = or(_dataArb_io_in_3_valid_T_37, _dataArb_io_in_3_valid_T_38) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_3_valid_T_43 = or(_dataArb_io_in_3_valid_T_42, _dataArb_io_in_3_valid_T_39) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_3_valid_T_44 = or(_dataArb_io_in_3_valid_T_43, _dataArb_io_in_3_valid_T_40) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_3_valid_T_45 = or(_dataArb_io_in_3_valid_T_44, _dataArb_io_in_3_valid_T_41) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_3_valid_T_46 = or(_dataArb_io_in_3_valid_T_36, _dataArb_io_in_3_valid_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node _dataArb_io_in_3_valid_T_47 = or(_dataArb_io_in_3_valid_T_29, _dataArb_io_in_3_valid_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:76] node _dataArb_io_in_3_valid_T_48 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:35] node _dataArb_io_in_3_valid_T_49 = lt(io.cpu.req.bits.size, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:57] node _dataArb_io_in_3_valid_T_50 = or(_dataArb_io_in_3_valid_T_48, _dataArb_io_in_3_valid_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:45] node _dataArb_io_in_3_valid_T_51 = and(_dataArb_io_in_3_valid_T_47, _dataArb_io_in_3_valid_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:23] node _dataArb_io_in_3_valid_T_52 = or(_dataArb_io_in_3_valid_T_24, _dataArb_io_in_3_valid_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1188:21] node _dataArb_io_in_3_valid_T_53 = eq(_dataArb_io_in_3_valid_T_52, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1184:12] node _dataArb_io_in_3_valid_T_54 = or(_dataArb_io_in_3_valid_T_53, dataArb_io_in_3_valid_res) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1184:28] node _dataArb_io_in_3_valid_T_55 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1184:11] node _dataArb_io_in_3_valid_T_56 = eq(_dataArb_io_in_3_valid_T_55, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1184:11] when _dataArb_io_in_3_valid_T_56 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1184:11] node _dataArb_io_in_3_valid_T_57 = eq(_dataArb_io_in_3_valid_T_54, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1184:11] when _dataArb_io_in_3_valid_T_57 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1184:11] printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:1184 assert(!needsRead(req) || res)\n") : dataArb_io_in_3_valid_printf @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1184:11] assert(clock, _dataArb_io_in_3_valid_T_54, UInt<1>(0h1), "") : dataArb_io_in_3_valid_assert @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1184:11] node _dataArb_io_in_3_valid_T_58 = and(io.cpu.req.valid, dataArb_io_in_3_valid_res) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 240:46] connect dataArb.io.in[3].valid, _dataArb_io_in_3_valid_T_58 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 240:26] connect dataArb.io.in[3].bits.way_en, dataArb.io.in[1].bits.way_en @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 241:25] connect dataArb.io.in[3].bits.eccMask, dataArb.io.in[1].bits.eccMask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 241:25] connect dataArb.io.in[3].bits.wordMask, dataArb.io.in[1].bits.wordMask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 241:25] connect dataArb.io.in[3].bits.wdata, dataArb.io.in[1].bits.wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 241:25] connect dataArb.io.in[3].bits.write, dataArb.io.in[1].bits.write @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 241:25] connect dataArb.io.in[3].bits.addr, dataArb.io.in[1].bits.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 241:25] connect dataArb.io.in[3].bits.write, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 242:31] node _dataArb_io_in_3_bits_addr_T = shr(io.cpu.req.bits.addr, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 243:89] node _dataArb_io_in_3_bits_addr_T_1 = bits(io.cpu.req.bits.addr, 19, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 243:120] node _dataArb_io_in_3_bits_addr_T_2 = cat(_dataArb_io_in_3_bits_addr_T, _dataArb_io_in_3_bits_addr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 243:36] connect dataArb.io.in[3].bits.addr, _dataArb_io_in_3_bits_addr_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 243:30] node _dataArb_io_in_3_bits_wordMask_T = mux(UInt<1>(0h1), UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 252:9] connect dataArb.io.in[3].bits.wordMask, _dataArb_io_in_3_bits_wordMask_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 244:34] node _dataArb_io_in_3_bits_eccMask_T = not(UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 254:36] connect dataArb.io.in[3].bits.eccMask, _dataArb_io_in_3_bits_eccMask_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 254:33] node _dataArb_io_in_3_bits_way_en_T = not(UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 255:35] connect dataArb.io.in[3].bits.way_en, _dataArb_io_in_3_bits_way_en_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 255:32] node _T_3 = eq(dataArb.io.in[3].ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 256:9] node _T_4 = and(_T_3, s0_read) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 256:33] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 256:45] connect io.cpu.req.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 256:64] node _s1_did_read_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_1 = eq(io.cpu.req.bits.cmd, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_2 = eq(io.cpu.req.bits.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_3 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_4 = or(_s1_did_read_T, _s1_did_read_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_did_read_T_5 = or(_s1_did_read_T_4, _s1_did_read_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_did_read_T_6 = or(_s1_did_read_T_5, _s1_did_read_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_did_read_T_7 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_8 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_9 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_10 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_11 = or(_s1_did_read_T_7, _s1_did_read_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_did_read_T_12 = or(_s1_did_read_T_11, _s1_did_read_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_did_read_T_13 = or(_s1_did_read_T_12, _s1_did_read_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_did_read_T_14 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_15 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_16 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_17 = eq(io.cpu.req.bits.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_18 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_19 = or(_s1_did_read_T_14, _s1_did_read_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_did_read_T_20 = or(_s1_did_read_T_19, _s1_did_read_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_did_read_T_21 = or(_s1_did_read_T_20, _s1_did_read_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_did_read_T_22 = or(_s1_did_read_T_21, _s1_did_read_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_did_read_T_23 = or(_s1_did_read_T_13, _s1_did_read_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node _s1_did_read_T_24 = or(_s1_did_read_T_6, _s1_did_read_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 89:68] node _s1_did_read_T_25 = eq(io.cpu.req.bits.cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:32] node _s1_did_read_T_26 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:49] node _s1_did_read_T_27 = or(_s1_did_read_T_25, _s1_did_read_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:42] node _s1_did_read_T_28 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:66] node _s1_did_read_T_29 = or(_s1_did_read_T_27, _s1_did_read_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:59] node _s1_did_read_T_30 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_31 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_32 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_33 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_34 = or(_s1_did_read_T_30, _s1_did_read_T_31) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_did_read_T_35 = or(_s1_did_read_T_34, _s1_did_read_T_32) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_did_read_T_36 = or(_s1_did_read_T_35, _s1_did_read_T_33) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_did_read_T_37 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_38 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_39 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_40 = eq(io.cpu.req.bits.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_41 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s1_did_read_T_42 = or(_s1_did_read_T_37, _s1_did_read_T_38) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_did_read_T_43 = or(_s1_did_read_T_42, _s1_did_read_T_39) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_did_read_T_44 = or(_s1_did_read_T_43, _s1_did_read_T_40) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_did_read_T_45 = or(_s1_did_read_T_44, _s1_did_read_T_41) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s1_did_read_T_46 = or(_s1_did_read_T_36, _s1_did_read_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node _s1_did_read_T_47 = or(_s1_did_read_T_29, _s1_did_read_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:76] node _s1_did_read_T_48 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:35] node _s1_did_read_T_49 = lt(io.cpu.req.bits.size, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:57] node _s1_did_read_T_50 = or(_s1_did_read_T_48, _s1_did_read_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:45] node _s1_did_read_T_51 = and(_s1_did_read_T_47, _s1_did_read_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:23] node _s1_did_read_T_52 = or(_s1_did_read_T_24, _s1_did_read_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1188:21] node _s1_did_read_T_53 = and(io.cpu.req.valid, _s1_did_read_T_52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 257:75] node _s1_did_read_T_54 = and(dataArb.io.in[3].ready, _s1_did_read_T_53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 257:54] reg s1_did_read : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 257:30] when s0_clk_en : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 257:30] connect s1_did_read, _s1_did_read_T_54 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 257:30] reg s1_read_mask : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 258:31] when s0_clk_en : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 258:31] connect s1_read_mask, dataArb.io.in[3].bits.wordMask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 258:31] connect metaArb.io.in[7].valid, io.cpu.req.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 259:26] connect metaArb.io.in[7].bits.write, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 260:31] node _metaArb_io_in_7_bits_idx_T = bits(dataArb.io.in[3].bits.addr, 19, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 261:58] connect metaArb.io.in[7].bits.idx, _metaArb_io_in_7_bits_idx_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 261:29] connect metaArb.io.in[7].bits.addr, io.cpu.req.bits.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 262:30] connect metaArb.io.in[7].bits.way_en, metaArb.io.in[4].bits.way_en @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 263:32] connect metaArb.io.in[7].bits.data, metaArb.io.in[4].bits.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 264:30] node _T_5 = eq(metaArb.io.in[7].ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 265:9] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 265:34] connect io.cpu.req.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 265:53] node _s1_cmd_uses_tlb_T = or(s1_readwrite, s1_flush_line) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 268:38] node _s1_cmd_uses_tlb_T_1 = eq(s1_req.cmd, UInt<5>(0h17)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 268:69] node s1_cmd_uses_tlb = or(_s1_cmd_uses_tlb_T, _s1_cmd_uses_tlb_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 268:55] connect tlb.io.ptw.customCSRs, io.ptw.customCSRs @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] connect tlb.io.ptw.pmp[0], io.ptw.pmp[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] connect tlb.io.ptw.pmp[1], io.ptw.pmp[1] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] connect tlb.io.ptw.pmp[2], io.ptw.pmp[2] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] connect tlb.io.ptw.pmp[3], io.ptw.pmp[3] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] connect tlb.io.ptw.pmp[4], io.ptw.pmp[4] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] connect tlb.io.ptw.pmp[5], io.ptw.pmp[5] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] connect tlb.io.ptw.pmp[6], io.ptw.pmp[6] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] connect tlb.io.ptw.pmp[7], io.ptw.pmp[7] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] connect tlb.io.ptw.gstatus, io.ptw.gstatus @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] connect tlb.io.ptw.hstatus, io.ptw.hstatus @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] connect tlb.io.ptw.status, io.ptw.status @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] connect tlb.io.ptw.vsatp, io.ptw.vsatp @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] connect tlb.io.ptw.hgatp, io.ptw.hgatp @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] connect tlb.io.ptw.ptbr, io.ptw.ptbr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] connect tlb.io.ptw.resp, io.ptw.resp @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] connect io.ptw.req.bits, tlb.io.ptw.req.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] connect io.ptw.req.valid, tlb.io.ptw.req.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] connect tlb.io.ptw.req.ready, io.ptw.req.ready @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 269:10] node _tlb_io_kill_T = and(s2_tlb_req_valid, io.tlb_port.s2_kill) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 270:53] node _tlb_io_kill_T_1 = or(io.cpu.s2_kill, _tlb_io_kill_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 270:33] connect tlb.io.kill, _tlb_io_kill_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 270:15] node _tlb_io_req_valid_T = eq(io.cpu.s1_kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 271:55] node _tlb_io_req_valid_T_1 = and(s1_valid, _tlb_io_req_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 271:52] node _tlb_io_req_valid_T_2 = and(_tlb_io_req_valid_T_1, s1_cmd_uses_tlb) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 271:71] node _tlb_io_req_valid_T_3 = or(s1_tlb_req_valid, _tlb_io_req_valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 271:40] connect tlb.io.req.valid, _tlb_io_req_valid_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 271:20] connect tlb.io.req.bits.v, s1_tlb_req.v @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 272:19] connect tlb.io.req.bits.prv, s1_tlb_req.prv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 272:19] connect tlb.io.req.bits.cmd, s1_tlb_req.cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 272:19] connect tlb.io.req.bits.size, s1_tlb_req.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 272:19] connect tlb.io.req.bits.passthrough, s1_tlb_req.passthrough @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 272:19] connect tlb.io.req.bits.vaddr, s1_tlb_req.vaddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 272:19] node _T_6 = eq(tlb.io.req.ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 273:9] node _T_7 = eq(tlb.io.ptw.resp.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 273:30] node _T_8 = and(_T_6, _T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 273:27] node _T_9 = eq(io.cpu.req.bits.phys, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 273:56] node _T_10 = and(_T_8, _T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 273:53] when _T_10 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 273:79] connect io.cpu.req.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 273:98] node _T_11 = eq(s1_tlb_req_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 274:9] node _T_12 = and(_T_11, s1_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 274:27] node _T_13 = and(_T_12, s1_cmd_uses_tlb) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 274:39] node _T_14 = and(_T_13, tlb.io.resp.miss) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 274:58] when _T_14 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 274:79] connect s1_nack, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 274:89] node _tlb_io_sfence_valid_T = eq(io.cpu.s1_kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 276:38] node _tlb_io_sfence_valid_T_1 = and(s1_valid, _tlb_io_sfence_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 276:35] node _tlb_io_sfence_valid_T_2 = and(_tlb_io_sfence_valid_T_1, s1_sfence) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 276:54] connect tlb.io.sfence.valid, _tlb_io_sfence_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 276:23] node _tlb_io_sfence_bits_rs1_T = bits(s1_req.size, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 277:40] connect tlb.io.sfence.bits.rs1, _tlb_io_sfence_bits_rs1_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 277:26] node _tlb_io_sfence_bits_rs2_T = bits(s1_req.size, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 278:40] connect tlb.io.sfence.bits.rs2, _tlb_io_sfence_bits_rs2_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 278:26] connect tlb.io.sfence.bits.asid, io.cpu.s1_data.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 279:27] connect tlb.io.sfence.bits.addr, s1_req.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 280:27] node _tlb_io_sfence_bits_hv_T = eq(s1_req.cmd, UInt<5>(0h15)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 281:39] connect tlb.io.sfence.bits.hv, _tlb_io_sfence_bits_hv_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 281:25] node _tlb_io_sfence_bits_hg_T = eq(s1_req.cmd, UInt<5>(0h16)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 282:39] connect tlb.io.sfence.bits.hg, _tlb_io_sfence_bits_hg_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 282:25] connect io.tlb_port.req.ready, clock_en_reg @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 284:25] connect io.tlb_port.s1_resp, tlb.io.resp @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 285:23] node _T_15 = and(s1_tlb_req_valid, s1_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 286:26] node _T_16 = and(s1_req.phys, s1_req.no_xcpt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 286:55] node _T_17 = eq(_T_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 286:41] node _T_18 = and(_T_15, _T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 286:38] when _T_18 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 286:75] connect s1_nack, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 286:85] invalidate pma_checker.io.kill @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[0].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[0].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[0].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[0].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[0].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[0].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[0].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[1].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[1].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[1].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[1].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[1].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[1].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[1].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[2].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[2].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[2].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[2].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[2].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[2].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[2].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[3].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[3].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[3].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[3].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[3].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[3].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.customCSRs.csrs[3].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[0].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[0].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[0].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[0].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[0].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[0].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[0].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[0].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[1].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[1].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[1].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[1].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[1].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[1].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[1].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[1].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[2].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[2].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[2].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[2].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[2].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[2].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[2].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[2].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[3].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[3].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[3].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[3].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[3].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[3].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[3].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[3].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[4].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[4].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[4].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[4].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[4].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[4].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[4].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[4].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[5].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[5].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[5].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[5].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[5].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[5].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[5].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[5].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[6].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[6].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[6].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[6].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[6].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[6].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[6].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[6].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[7].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[7].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[7].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[7].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[7].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[7].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[7].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.pmp[7].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.uie @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.sie @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.hie @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.mie @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.upie @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.spie @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.ube @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.mpie @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.spp @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.vs @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.mpp @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.fs @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.xs @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.mprv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.sum @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.mxr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.tvm @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.tw @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.tsr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.zero1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.sd_rv32 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.uxl @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.sxl @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.sbe @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.mbe @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.gva @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.mpv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.zero2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.sd @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.v @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.prv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.dv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.dprv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.isa @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.wfi @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.cease @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.gstatus.debug @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.hstatus.zero1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.hstatus.vsbe @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.hstatus.gva @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.hstatus.spv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.hstatus.spvp @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.hstatus.hu @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.hstatus.zero2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.hstatus.vgein @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.hstatus.zero3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.hstatus.vtvm @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.hstatus.vtw @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.hstatus.vtsr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.hstatus.zero5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.hstatus.vsxl @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.hstatus.zero6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.uie @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.sie @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.hie @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.mie @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.upie @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.spie @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.ube @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.mpie @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.spp @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.vs @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.mpp @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.fs @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.xs @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.mprv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.sum @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.mxr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.tvm @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.tw @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.tsr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.zero1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.sd_rv32 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.uxl @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.sxl @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.sbe @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.mbe @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.gva @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.mpv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.zero2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.sd @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.v @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.prv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.dv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.dprv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.isa @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.wfi @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.cease @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.status.debug @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.vsatp.ppn @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.vsatp.asid @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.vsatp.mode @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.hgatp.ppn @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.hgatp.asid @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.hgatp.mode @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.ptbr.ppn @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.ptbr.asid @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.ptbr.mode @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.gpa_is_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.gpa.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.gpa.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.homogeneous @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.level @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.pte.v @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.pte.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.pte.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.pte.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.pte.u @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.pte.g @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.pte.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.pte.d @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.pte.reserved_for_software @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.pte.ppn @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.pte.reserved_for_future @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.hx @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.hw @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.hr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.gf @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.pf @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.ae_final @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.bits.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.resp.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.req.bits.bits.stage2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.req.bits.bits.vstage1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.req.bits.bits.need_gpa @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.req.bits.bits.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.req.bits.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.req.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.ptw.req.ready @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.sfence.bits.hg @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.sfence.bits.hv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.sfence.bits.asid @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.sfence.bits.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.sfence.bits.rs2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.sfence.bits.rs1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.sfence.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.prefetchable @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.must_alloc @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.cacheable @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.ma.inst @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.ma.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.ma.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.ae.inst @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.ae.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.ae.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.gf.inst @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.gf.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.gf.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.pf.inst @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.pf.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.pf.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.gpa_is_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.gpa @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.paddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.resp.miss @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.req.bits.v @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.req.bits.prv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.req.bits.cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.req.bits.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.req.bits.passthrough @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.req.bits.vaddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.req.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] invalidate pma_checker.io.req.ready @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 288:18] connect pma_checker.io.req.bits.passthrough, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 289:39] connect pma_checker.io.req.bits.vaddr, s1_req.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 290:33] connect pma_checker.io.req.bits.size, s1_req.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 291:32] connect pma_checker.io.req.bits.cmd, s1_req.cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 292:31] connect pma_checker.io.req.bits.prv, s1_req.dprv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 293:31] connect pma_checker.io.req.bits.v, s1_req.dv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 294:29] node _s1_paddr_T = bits(s1_req.addr, 31, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 296:55] node _s1_paddr_T_1 = shr(tlb.io.resp.paddr, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 296:99] node _s1_paddr_T_2 = mux(s1_tlb_req_valid, _s1_paddr_T, _s1_paddr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 296:25] node _s1_paddr_T_3 = bits(s1_req.addr, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 296:125] node s1_paddr = cat(_s1_paddr_T_2, _s1_paddr_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 296:21] wire s1_victim_way : UInt @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 297:27] node _baseAddr_T = eq(UInt<1>(0h0), hartIdSinkNodeOptIn) @[hardware/upstream/rocket-chip/src/main/scala/tile/LookupByHartId.scala 18:71] node baseAddr = or(UInt<32>(0h80000000), mmioAddressPrefixSinkNodeOptIn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 300:93] node _inScratchpad_T = geq(s1_paddr, baseAddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 301:35] node _inScratchpad_T_1 = add(baseAddr, UInt<21>(0h100000)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 301:70] node _inScratchpad_T_2 = tail(_inScratchpad_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 301:70] node _inScratchpad_T_3 = lt(s1_paddr, _inScratchpad_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 301:59] node s1_hit_way = and(_inScratchpad_T, _inScratchpad_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 301:47] wire hitState_meta : { state : UInt<2>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 160:20] connect hitState_meta.state, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 161:16] wire hitState_meta_1 : { state : UInt<2>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 160:20] connect hitState_meta_1.state, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 161:16] node s1_hit_state = mux(s1_hit_way, hitState_meta, hitState_meta_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 302:25] wire dummyMeta_meta : { state : UInt<2>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 160:20] connect dummyMeta_meta.state, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 161:16] wire dummyMeta : { coh : { state : UInt<2>}, tag : UInt<12>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 305:20] connect dummyMeta.tag, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 306:14] connect dummyMeta.coh, dummyMeta_meta @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 307:14] node s1_meta_0 = cat(dummyMeta.coh.state, dummyMeta.tag) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 304:58] wire s1_data_way : UInt @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 321:32] connect s1_data_way, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 321:32] node _tl_d_data_encoded_T = bits(nodeOut.d.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _tl_d_data_encoded_T_1 = bits(nodeOut.d.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _tl_d_data_encoded_T_2 = bits(nodeOut.d.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _tl_d_data_encoded_T_3 = bits(nodeOut.d.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _tl_d_data_encoded_T_4 = bits(nodeOut.d.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _tl_d_data_encoded_T_5 = bits(nodeOut.d.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _tl_d_data_encoded_T_6 = bits(nodeOut.d.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _tl_d_data_encoded_T_7 = bits(nodeOut.d.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node tl_d_data_encoded_lo_lo = cat(_tl_d_data_encoded_T_1, _tl_d_data_encoded_T) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node tl_d_data_encoded_lo_hi = cat(_tl_d_data_encoded_T_3, _tl_d_data_encoded_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node tl_d_data_encoded_lo = cat(tl_d_data_encoded_lo_hi, tl_d_data_encoded_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node tl_d_data_encoded_hi_lo = cat(_tl_d_data_encoded_T_5, _tl_d_data_encoded_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node tl_d_data_encoded_hi_hi = cat(_tl_d_data_encoded_T_7, _tl_d_data_encoded_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node tl_d_data_encoded_hi = cat(tl_d_data_encoded_hi_hi, tl_d_data_encoded_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _tl_d_data_encoded_T_8 = cat(tl_d_data_encoded_hi, tl_d_data_encoded_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] wire tl_d_data_encoded : UInt<64> @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 322:31] wire s1_all_data_ways : UInt<64>[2] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 323:33] connect s1_all_data_ways[0], data.io.resp[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 323:33] connect s1_all_data_ways[1], tl_d_data_encoded @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 323:33] wire s1_mask_xwr_size : UInt<2> @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 11:18] connect s1_mask_xwr_size, s1_req.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 12:8] node _s1_mask_xwr_upper_T = bits(s1_req.addr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:27] node _s1_mask_xwr_upper_T_1 = mux(_s1_mask_xwr_upper_T, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:22] node _s1_mask_xwr_upper_T_2 = geq(s1_mask_xwr_size, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:53] node _s1_mask_xwr_upper_T_3 = mux(_s1_mask_xwr_upper_T_2, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:47] node s1_mask_xwr_upper = or(_s1_mask_xwr_upper_T_1, _s1_mask_xwr_upper_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:42] node _s1_mask_xwr_lower_T = bits(s1_req.addr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 21:27] node s1_mask_xwr_lower = mux(_s1_mask_xwr_lower_T, UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 21:22] node _s1_mask_xwr_T = cat(s1_mask_xwr_upper, s1_mask_xwr_lower) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 22:16] node _s1_mask_xwr_upper_T_4 = bits(s1_req.addr, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:27] node _s1_mask_xwr_upper_T_5 = mux(_s1_mask_xwr_upper_T_4, _s1_mask_xwr_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:22] node _s1_mask_xwr_upper_T_6 = geq(s1_mask_xwr_size, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:53] node _s1_mask_xwr_upper_T_7 = mux(_s1_mask_xwr_upper_T_6, UInt<2>(0h3), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:47] node s1_mask_xwr_upper_1 = or(_s1_mask_xwr_upper_T_5, _s1_mask_xwr_upper_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:42] node _s1_mask_xwr_lower_T_1 = bits(s1_req.addr, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 21:27] node s1_mask_xwr_lower_1 = mux(_s1_mask_xwr_lower_T_1, UInt<1>(0h0), _s1_mask_xwr_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 21:22] node _s1_mask_xwr_T_1 = cat(s1_mask_xwr_upper_1, s1_mask_xwr_lower_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 22:16] node _s1_mask_xwr_upper_T_8 = bits(s1_req.addr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:27] node _s1_mask_xwr_upper_T_9 = mux(_s1_mask_xwr_upper_T_8, _s1_mask_xwr_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:22] node _s1_mask_xwr_upper_T_10 = geq(s1_mask_xwr_size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:53] node _s1_mask_xwr_upper_T_11 = mux(_s1_mask_xwr_upper_T_10, UInt<4>(0hf), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:47] node s1_mask_xwr_upper_2 = or(_s1_mask_xwr_upper_T_9, _s1_mask_xwr_upper_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:42] node _s1_mask_xwr_lower_T_2 = bits(s1_req.addr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 21:27] node s1_mask_xwr_lower_2 = mux(_s1_mask_xwr_lower_T_2, UInt<1>(0h0), _s1_mask_xwr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 21:22] node s1_mask_xwr = cat(s1_mask_xwr_upper_2, s1_mask_xwr_lower_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 22:16] node _s1_mask_T = eq(s1_req.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 325:32] node s1_mask = mux(_s1_mask_T, io.cpu.s1_data.mask, s1_mask_xwr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 325:20] node _T_19 = eq(s1_req.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 327:42] node _T_20 = and(s1_valid_masked, _T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 327:28] node _T_21 = eq(_T_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 327:10] node _T_22 = not(io.cpu.s1_data.mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 327:71] node _T_23 = or(s1_mask_xwr, _T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 327:69] node _T_24 = andr(_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 327:93] node _T_25 = or(_T_21, _T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 327:53] node _T_26 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 327:9] node _T_27 = eq(_T_26, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 327:9] when _T_27 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 327:9] node _T_28 = eq(_T_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 327:9] when _T_28 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 327:9] printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:327 assert(!(s1_valid_masked && s1_req.cmd === M_PWR) || (s1_mask_xwr | ~io.cpu.s1_data.mask).andR)\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 327:9] assert(clock, _T_25, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 327:9] node _s2_valid_T = eq(s1_sfence, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 329:45] node _s2_valid_T_1 = and(s1_valid_masked, _s2_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 329:42] regreset s2_valid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 329:25] connect s2_valid, _s2_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 329:25] node _s2_valid_no_xcpt_T = cat(io.cpu.s2_xcpt.ae.ld, io.cpu.s2_xcpt.ae.st) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 330:54] node _s2_valid_no_xcpt_T_1 = cat(io.cpu.s2_xcpt.gf.ld, io.cpu.s2_xcpt.gf.st) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 330:54] node _s2_valid_no_xcpt_T_2 = cat(io.cpu.s2_xcpt.pf.ld, io.cpu.s2_xcpt.pf.st) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 330:54] node _s2_valid_no_xcpt_T_3 = cat(io.cpu.s2_xcpt.ma.ld, io.cpu.s2_xcpt.ma.st) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 330:54] node s2_valid_no_xcpt_lo = cat(_s2_valid_no_xcpt_T_1, _s2_valid_no_xcpt_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 330:54] node s2_valid_no_xcpt_hi = cat(_s2_valid_no_xcpt_T_3, _s2_valid_no_xcpt_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 330:54] node _s2_valid_no_xcpt_T_4 = cat(s2_valid_no_xcpt_hi, s2_valid_no_xcpt_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 330:54] node _s2_valid_no_xcpt_T_5 = orr(_s2_valid_no_xcpt_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 330:61] node _s2_valid_no_xcpt_T_6 = eq(_s2_valid_no_xcpt_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 330:38] node s2_valid_no_xcpt = and(s2_valid, _s2_valid_no_xcpt_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 330:35] regreset s2_probe : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 331:25] connect s2_probe, s1_probe @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 331:25] node _releaseInFlight_T = or(s1_probe, s2_probe) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 332:34] node _releaseInFlight_T_1 = neq(release_state, UInt<4>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 332:63] node releaseInFlight = or(_releaseInFlight_T, _releaseInFlight_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 332:46] node _s2_not_nacked_in_s1_T = eq(s1_nack, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 333:37] reg s2_not_nacked_in_s1 : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 333:36] connect s2_not_nacked_in_s1, _s2_not_nacked_in_s1_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 333:36] node s2_valid_not_nacked_in_s1 = and(s2_valid, s2_not_nacked_in_s1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 334:44] node s2_valid_masked = and(s2_valid_no_xcpt, s2_not_nacked_in_s1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 335:42] node _s2_valid_not_killed_T = eq(io.cpu.s2_kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 336:48] node s2_valid_not_killed = and(s2_valid_masked, _s2_valid_not_killed_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 336:45] reg s2_req : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 337:19] node _s2_cmd_flush_all_T = eq(s2_req.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 338:37] node _s2_cmd_flush_all_T_1 = bits(s2_req.size, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 338:68] node _s2_cmd_flush_all_T_2 = eq(_s2_cmd_flush_all_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 338:56] node s2_cmd_flush_all = and(_s2_cmd_flush_all_T, _s2_cmd_flush_all_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 338:53] node _s2_cmd_flush_line_T = eq(s2_req.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 339:38] node _s2_cmd_flush_line_T_1 = bits(s2_req.size, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 339:68] node s2_cmd_flush_line = and(_s2_cmd_flush_line_T, _s2_cmd_flush_line_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 339:54] reg s2_tlb_xcpt : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<34>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 340:24] reg s2_pma : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<34>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 341:19] reg s2_uncached_resp_addr : UInt<34>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 342:34] node _T_29 = or(s1_valid_not_nacked, s1_flush_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 343:29] when _T_29 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 343:48] connect s2_req, s1_req @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 344:12] connect s2_req.addr, s1_paddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 345:17] connect s2_tlb_xcpt, tlb.io.resp @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 346:17] node _s2_pma_T = mux(s1_tlb_req_valid, pma_checker.io.resp, tlb.io.resp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 347:18] connect s2_pma, _s2_pma_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 347:12] node _s2_vaddr_T = or(s1_valid_not_nacked, s1_flush_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 349:62] reg s2_vaddr_r : UInt<34>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 349:31] when _s2_vaddr_T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 349:31] connect s2_vaddr_r, s1_vaddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 349:31] node _s2_vaddr_T_1 = shr(s2_vaddr_r, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 349:81] node _s2_vaddr_T_2 = bits(s2_req.addr, 19, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 349:103] node s2_vaddr = cat(_s2_vaddr_T_1, _s2_vaddr_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 349:21] node _s2_read_T = eq(s2_req.cmd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_read_T_1 = eq(s2_req.cmd, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_read_T_2 = eq(s2_req.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_read_T_3 = eq(s2_req.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_read_T_4 = or(_s2_read_T, _s2_read_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_read_T_5 = or(_s2_read_T_4, _s2_read_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_read_T_6 = or(_s2_read_T_5, _s2_read_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_read_T_7 = eq(s2_req.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_read_T_8 = eq(s2_req.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_read_T_9 = eq(s2_req.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_read_T_10 = eq(s2_req.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_read_T_11 = or(_s2_read_T_7, _s2_read_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_read_T_12 = or(_s2_read_T_11, _s2_read_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_read_T_13 = or(_s2_read_T_12, _s2_read_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_read_T_14 = eq(s2_req.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_read_T_15 = eq(s2_req.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_read_T_16 = eq(s2_req.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_read_T_17 = eq(s2_req.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_read_T_18 = eq(s2_req.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_read_T_19 = or(_s2_read_T_14, _s2_read_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_read_T_20 = or(_s2_read_T_19, _s2_read_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_read_T_21 = or(_s2_read_T_20, _s2_read_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_read_T_22 = or(_s2_read_T_21, _s2_read_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_read_T_23 = or(_s2_read_T_13, _s2_read_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node s2_read = or(_s2_read_T_6, _s2_read_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 89:68] node _s2_write_T = eq(s2_req.cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:32] node _s2_write_T_1 = eq(s2_req.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:49] node _s2_write_T_2 = or(_s2_write_T, _s2_write_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:42] node _s2_write_T_3 = eq(s2_req.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:66] node _s2_write_T_4 = or(_s2_write_T_2, _s2_write_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:59] node _s2_write_T_5 = eq(s2_req.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_write_T_6 = eq(s2_req.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_write_T_7 = eq(s2_req.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_write_T_8 = eq(s2_req.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_write_T_9 = or(_s2_write_T_5, _s2_write_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_write_T_10 = or(_s2_write_T_9, _s2_write_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_write_T_11 = or(_s2_write_T_10, _s2_write_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_write_T_12 = eq(s2_req.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_write_T_13 = eq(s2_req.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_write_T_14 = eq(s2_req.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_write_T_15 = eq(s2_req.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_write_T_16 = eq(s2_req.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _s2_write_T_17 = or(_s2_write_T_12, _s2_write_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_write_T_18 = or(_s2_write_T_17, _s2_write_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_write_T_19 = or(_s2_write_T_18, _s2_write_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_write_T_20 = or(_s2_write_T_19, _s2_write_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_write_T_21 = or(_s2_write_T_11, _s2_write_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node s2_write = or(_s2_write_T_4, _s2_write_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:76] node s2_readwrite = or(s2_read, s2_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 352:30] reg s2_flush_valid_pre_tag_ecc : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 353:43] connect s2_flush_valid_pre_tag_ecc, s1_flush_valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 353:43] node _s1_meta_clk_en_T = or(s1_valid_not_nacked, s1_flush_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 355:44] node s1_meta_clk_en = or(_s1_meta_clk_en_T, s1_probe) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 355:62] reg s2_meta_correctable_errors : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 356:70] when s1_meta_clk_en : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 356:70] connect s2_meta_correctable_errors, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 356:70] reg s2_meta_uncorrectable_errors : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 357:72] when s1_meta_clk_en : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 357:72] connect s2_meta_uncorrectable_errors, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 357:72] node s2_meta_error_uncorrectable = orr(s2_meta_uncorrectable_errors) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 358:66] reg s2_meta_corrected_r : UInt<14>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 359:61] when s1_meta_clk_en : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 359:61] connect s2_meta_corrected_r, s1_meta_0 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 359:61] wire s2_meta_corrected_0 : { coh : { state : UInt<2>}, tag : UInt<12>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 359:99] wire _s2_meta_corrected_WIRE : UInt<14> @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 359:99] connect _s2_meta_corrected_WIRE, s2_meta_corrected_r @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 359:99] node _s2_meta_corrected_T = bits(_s2_meta_corrected_WIRE, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 359:99] connect s2_meta_corrected_0.tag, _s2_meta_corrected_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 359:99] node _s2_meta_corrected_T_1 = bits(_s2_meta_corrected_WIRE, 13, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 359:99] connect s2_meta_corrected_0.coh.state, _s2_meta_corrected_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 359:99] node _s2_meta_error_T = or(s2_meta_uncorrectable_errors, s2_meta_correctable_errors) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 360:53] node s2_meta_error = orr(_s2_meta_error_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 360:83] node _s2_flush_valid_T = eq(s2_meta_error, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 361:54] node s2_flush_valid = and(s2_flush_valid_pre_tag_ecc, _s2_flush_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 361:51] node _s2_data_en_T = or(s1_valid, inWriteback) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 364:23] node s2_data_en = or(_s2_data_en_T, io.cpu.replay_next) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 364:38] node _s2_data_word_en_T = mux(s1_did_read, s1_read_mask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 365:63] node s2_data_word_en = mux(inWriteback, UInt<1>(0h1), _s2_data_word_en_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 365:22] node s2_data_s1_way_words_0_0 = bits(s1_all_data_ways[0], 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node s2_data_s1_way_words_1_0 = bits(s1_all_data_ways[1], 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s2_data_s1_word_en_T = eq(io.cpu.replay_next, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 375:28] node s2_data_s1_word_en = mux(_s2_data_s1_word_en_T, s2_data_word_en, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 375:27] node _s2_data_T = bits(s2_data_s1_word_en, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 377:39] node _s2_data_T_1 = mux(_s2_data_T, s1_data_way, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 377:28] node _s2_data_T_2 = bits(_s2_data_T_1, 0, 0) @[src/main/scala/chisel3/util/Mux.scala 32:36] node _s2_data_T_3 = bits(_s2_data_T_1, 1, 1) @[src/main/scala/chisel3/util/Mux.scala 32:36] node _s2_data_T_4 = mux(_s2_data_T_2, s2_data_s1_way_words_0_0, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _s2_data_T_5 = mux(_s2_data_T_3, s2_data_s1_way_words_1_0, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _s2_data_T_6 = or(_s2_data_T_4, _s2_data_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _s2_data_WIRE : UInt<64> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _s2_data_WIRE, _s2_data_T_6 @[src/main/scala/chisel3/util/Mux.scala 30:73] reg s2_data : UInt<64>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 377:18] when s2_data_en : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 377:18] connect s2_data, _s2_data_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 377:18] reg s2_probe_way : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 381:31] when s1_probe : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 381:31] connect s2_probe_way, s1_hit_way @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 381:31] reg s2_probe_state : { state : UInt<2>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 382:33] when s1_probe : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 382:33] connect s2_probe_state, s1_hit_state @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 382:33] reg s2_hit_way : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 383:29] when s1_valid_not_nacked : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 383:29] connect s2_hit_way, s1_hit_way @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 383:29] node _s2_hit_state_T = or(s1_valid_not_nacked, s1_flush_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 384:66] reg s2_hit_state : { state : UInt<2>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 384:31] when _s2_hit_state_T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 384:31] connect s2_hit_state, s1_hit_state @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 384:31] reg s2_waw_hazard : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 385:32] when s1_valid_not_nacked : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 385:32] connect s2_waw_hazard, s1_waw_hazard @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 385:32] wire s2_store_merge : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 386:28] node s2_hit_valid = gt(s2_hit_state.state, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 50:45] node _r_c_cat_T = eq(s2_req.cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:32] node _r_c_cat_T_1 = eq(s2_req.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:49] node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:42] node _r_c_cat_T_3 = eq(s2_req.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:66] node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:59] node _r_c_cat_T_5 = eq(s2_req.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _r_c_cat_T_6 = eq(s2_req.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _r_c_cat_T_7 = eq(s2_req.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _r_c_cat_T_8 = eq(s2_req.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _r_c_cat_T_12 = eq(s2_req.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _r_c_cat_T_13 = eq(s2_req.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _r_c_cat_T_14 = eq(s2_req.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _r_c_cat_T_15 = eq(s2_req.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _r_c_cat_T_16 = eq(s2_req.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:76] node _r_c_cat_T_23 = eq(s2_req.cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:32] node _r_c_cat_T_24 = eq(s2_req.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:49] node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:42] node _r_c_cat_T_26 = eq(s2_req.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:66] node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:59] node _r_c_cat_T_28 = eq(s2_req.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _r_c_cat_T_29 = eq(s2_req.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _r_c_cat_T_30 = eq(s2_req.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _r_c_cat_T_31 = eq(s2_req.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _r_c_cat_T_35 = eq(s2_req.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _r_c_cat_T_36 = eq(s2_req.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _r_c_cat_T_37 = eq(s2_req.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _r_c_cat_T_38 = eq(s2_req.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _r_c_cat_T_39 = eq(s2_req.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:76] node _r_c_cat_T_46 = eq(s2_req.cmd, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 91:54] node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 91:47] node _r_c_cat_T_48 = eq(s2_req.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 91:71] node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 91:64] node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 29:18] node _r_T = cat(r_c, s2_hit_state.state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 58:19] node _r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 26:15] node _r_T_2 = cat(_r_T_1, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 60:10] node _r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 26:15] node _r_T_4 = cat(_r_T_3, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 61:10] node _r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 26:15] node _r_T_6 = cat(_r_T_5, UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 62:10] node _r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 25:15] node _r_T_8 = cat(_r_T_7, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 63:10] node _r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 25:15] node _r_T_10 = cat(_r_T_9, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 64:10] node _r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 24:15] node _r_T_12 = cat(_r_T_11, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 65:10] node _r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 24:15] node _r_T_14 = cat(_r_T_13, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 66:10] node _r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 26:15] node _r_T_16 = cat(_r_T_15, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 68:10] node _r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 25:15] node _r_T_18 = cat(_r_T_17, UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 69:10] node _r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 25:15] node _r_T_20 = cat(_r_T_19, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 70:10] node _r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 24:15] node _r_T_22 = cat(_r_T_21, UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 71:10] node _r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 24:15] node _r_T_24 = cat(_r_T_23, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 72:10] node _r_T_25 = eq(_r_T_24, _r_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 49:20] node _r_T_26 = mux(_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node _r_T_27 = mux(_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _r_T_28 = eq(_r_T_22, _r_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 49:20] node _r_T_29 = mux(_r_T_28, UInt<1>(0h0), _r_T_26) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node _r_T_30 = mux(_r_T_28, UInt<2>(0h2), _r_T_27) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _r_T_31 = eq(_r_T_20, _r_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 49:20] node _r_T_32 = mux(_r_T_31, UInt<1>(0h0), _r_T_29) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node _r_T_33 = mux(_r_T_31, UInt<2>(0h1), _r_T_30) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _r_T_34 = eq(_r_T_18, _r_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 49:20] node _r_T_35 = mux(_r_T_34, UInt<1>(0h0), _r_T_32) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node _r_T_36 = mux(_r_T_34, UInt<2>(0h2), _r_T_33) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _r_T_37 = eq(_r_T_16, _r_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 49:20] node _r_T_38 = mux(_r_T_37, UInt<1>(0h0), _r_T_35) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node _r_T_39 = mux(_r_T_37, UInt<2>(0h0), _r_T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _r_T_40 = eq(_r_T_14, _r_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 49:20] node _r_T_41 = mux(_r_T_40, UInt<1>(0h1), _r_T_38) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node _r_T_42 = mux(_r_T_40, UInt<2>(0h3), _r_T_39) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _r_T_43 = eq(_r_T_12, _r_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 49:20] node _r_T_44 = mux(_r_T_43, UInt<1>(0h1), _r_T_41) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node _r_T_45 = mux(_r_T_43, UInt<2>(0h3), _r_T_42) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _r_T_46 = eq(_r_T_10, _r_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 49:20] node _r_T_47 = mux(_r_T_46, UInt<1>(0h1), _r_T_44) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node _r_T_48 = mux(_r_T_46, UInt<2>(0h2), _r_T_45) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _r_T_49 = eq(_r_T_8, _r_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 49:20] node _r_T_50 = mux(_r_T_49, UInt<1>(0h1), _r_T_47) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node _r_T_51 = mux(_r_T_49, UInt<2>(0h3), _r_T_48) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _r_T_52 = eq(_r_T_6, _r_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 49:20] node _r_T_53 = mux(_r_T_52, UInt<1>(0h1), _r_T_50) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node _r_T_54 = mux(_r_T_52, UInt<2>(0h1), _r_T_51) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _r_T_55 = eq(_r_T_4, _r_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 49:20] node _r_T_56 = mux(_r_T_55, UInt<1>(0h1), _r_T_53) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node _r_T_57 = mux(_r_T_55, UInt<2>(0h2), _r_T_54) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _r_T_58 = eq(_r_T_2, _r_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 49:20] node s2_hit = mux(_r_T_58, UInt<1>(0h1), _r_T_56) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node s2_grow_param = mux(_r_T_58, UInt<2>(0h3), _r_T_57) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] wire s2_new_hit_state : { state : UInt<2>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 160:20] connect s2_new_hit_state.state, s2_grow_param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 161:16] node _T_30 = bits(s2_data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _T_31 = bits(s2_data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _T_32 = bits(s2_data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _T_33 = bits(s2_data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _T_34 = bits(s2_data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _T_35 = bits(s2_data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _T_36 = bits(s2_data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _T_37 = bits(s2_data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s2_data_error_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/ECC.scala 15:27] node _s2_data_error_T_1 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/ECC.scala 15:27] node _s2_data_error_T_2 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/ECC.scala 15:27] node _s2_data_error_T_3 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/ECC.scala 15:27] node _s2_data_error_T_4 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/ECC.scala 15:27] node _s2_data_error_T_5 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/ECC.scala 15:27] node _s2_data_error_T_6 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/ECC.scala 15:27] node _s2_data_error_T_7 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/ECC.scala 15:27] node _s2_data_error_T_8 = or(_s2_data_error_T, _s2_data_error_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_data_error_T_9 = or(_s2_data_error_T_8, _s2_data_error_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_data_error_T_10 = or(_s2_data_error_T_9, _s2_data_error_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_data_error_T_11 = or(_s2_data_error_T_10, _s2_data_error_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_data_error_T_12 = or(_s2_data_error_T_11, _s2_data_error_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_data_error_T_13 = or(_s2_data_error_T_12, _s2_data_error_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node s2_data_error = or(_s2_data_error_T_13, _s2_data_error_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_data_error_uncorrectable_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_data_error_uncorrectable_T_1 = or(_s2_data_error_uncorrectable_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_data_error_uncorrectable_T_2 = or(_s2_data_error_uncorrectable_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_data_error_uncorrectable_T_3 = or(_s2_data_error_uncorrectable_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_data_error_uncorrectable_T_4 = or(_s2_data_error_uncorrectable_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _s2_data_error_uncorrectable_T_5 = or(_s2_data_error_uncorrectable_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node s2_data_error_uncorrectable = or(_s2_data_error_uncorrectable_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node s2_data_corrected_lo_lo = cat(_T_31, _T_30) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s2_data_corrected_lo_hi = cat(_T_33, _T_32) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s2_data_corrected_lo = cat(s2_data_corrected_lo_hi, s2_data_corrected_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s2_data_corrected_hi_lo = cat(_T_35, _T_34) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s2_data_corrected_hi_hi = cat(_T_37, _T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s2_data_corrected_hi = cat(s2_data_corrected_hi_hi, s2_data_corrected_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s2_data_corrected = cat(s2_data_corrected_hi, s2_data_corrected_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s2_data_uncorrected_lo_lo = cat(_T_31, _T_30) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s2_data_uncorrected_lo_hi = cat(_T_33, _T_32) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s2_data_uncorrected_lo = cat(s2_data_uncorrected_lo_hi, s2_data_uncorrected_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s2_data_uncorrected_hi_lo = cat(_T_35, _T_34) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s2_data_uncorrected_hi_hi = cat(_T_37, _T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s2_data_uncorrected_hi = cat(s2_data_uncorrected_hi_hi, s2_data_uncorrected_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s2_data_uncorrected = cat(s2_data_uncorrected_hi, s2_data_uncorrected_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T = eq(s2_meta_error, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 395:74] node _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 = and(s2_valid_masked, _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 395:71] node s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = and(_s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1, s2_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 395:89] node _s2_valid_hit_pre_data_ecc_and_waw_T = and(s2_valid_hit_maybe_flush_pre_data_ecc_and_waw, s2_readwrite) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 416:89] node _s2_valid_hit_pre_data_ecc_and_waw_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 416:108] node s2_valid_hit_pre_data_ecc_and_waw = and(_s2_valid_hit_pre_data_ecc_and_waw_T, _s2_valid_hit_pre_data_ecc_and_waw_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 416:105] node s2_valid_flush_line = and(s2_valid_hit_maybe_flush_pre_data_ecc_and_waw, s2_cmd_flush_line) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 417:75] node _s2_valid_hit_pre_data_ecc_T = eq(s2_waw_hazard, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 418:73] node _s2_valid_hit_pre_data_ecc_T_1 = or(_s2_valid_hit_pre_data_ecc_T, s2_store_merge) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 418:88] node s2_valid_hit_pre_data_ecc = and(s2_valid_hit_pre_data_ecc_and_waw, _s2_valid_hit_pre_data_ecc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 418:69] node s2_valid_data_error = and(s2_valid_hit_pre_data_ecc_and_waw, s2_data_error) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 419:63] node _s2_valid_hit_T = eq(s2_data_error, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 420:51] node s2_valid_hit = and(s2_valid_hit_pre_data_ecc, _s2_valid_hit_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 420:48] node _s2_valid_miss_T = and(s2_valid_masked, s2_readwrite) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 421:39] node _s2_valid_miss_T_1 = eq(s2_meta_error, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 421:58] node _s2_valid_miss_T_2 = and(_s2_valid_miss_T, _s2_valid_miss_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 421:55] node _s2_valid_miss_T_3 = eq(s2_hit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 421:76] node s2_valid_miss = and(_s2_valid_miss_T_2, _s2_valid_miss_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 421:73] node _s2_uncached_T = eq(s2_pma.cacheable, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 422:21] node _s2_uncached_T_1 = eq(s2_pma.must_alloc, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 422:61] node _s2_uncached_T_2 = and(s2_req.no_alloc, _s2_uncached_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 422:58] node _s2_uncached_T_3 = eq(s2_hit_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 422:83] node _s2_uncached_T_4 = and(_s2_uncached_T_2, _s2_uncached_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 422:80] node s2_uncached = or(_s2_uncached_T, _s2_uncached_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 422:39] node _s2_valid_cached_miss_T = eq(s2_uncached, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 423:47] node _s2_valid_cached_miss_T_1 = and(s2_valid_miss, _s2_valid_cached_miss_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 423:44] node _s2_valid_cached_miss_T_2 = orr(uncachedInFlight[0]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 423:88] node _s2_valid_cached_miss_T_3 = eq(_s2_valid_cached_miss_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 423:63] node s2_valid_cached_miss = and(_s2_valid_cached_miss_T_1, _s2_valid_cached_miss_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 423:60] node _s2_want_victimize_T = or(s2_valid_cached_miss, s2_valid_flush_line) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 425:77] node _s2_want_victimize_T_1 = or(_s2_want_victimize_T, s2_valid_data_error) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 425:100] node _s2_want_victimize_T_2 = or(_s2_want_victimize_T_1, s2_flush_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 425:123] node s2_want_victimize = and(UInt<1>(0h0), _s2_want_victimize_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 425:52] node _s2_cannot_victimize_T = eq(s2_flush_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 426:29] node s2_cannot_victimize = and(_s2_cannot_victimize_T, io.cpu.s2_kill) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 426:45] node _s2_victimize_T = eq(s2_cannot_victimize, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 427:43] node s2_victimize = and(s2_want_victimize, _s2_victimize_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 427:40] node _s2_valid_uncached_pending_T = and(s2_valid_miss, s2_uncached) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 428:49] node _s2_valid_uncached_pending_T_1 = andr(uncachedInFlight[0]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 428:92] node _s2_valid_uncached_pending_T_2 = eq(_s2_valid_uncached_pending_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 428:67] node s2_valid_uncached_pending = and(_s2_valid_uncached_pending_T, _s2_valid_uncached_pending_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 428:64] node _s2_victim_way_T = or(s1_valid_not_nacked, s1_flush_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 429:77] reg s2_victim_way_r : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 429:41] when _s2_victim_way_T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 429:41] connect s2_victim_way_r, s1_victim_way @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 429:41] node s2_victim_way = dshl(UInt<1>(0h1), s2_victim_way_r) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node s2_victim_or_hit_way = mux(s2_hit_valid, s2_hit_way, s2_victim_way) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 430:33] node _s2_victim_tag_T = or(s2_valid_data_error, s2_valid_flush_line) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 431:47] node _s2_victim_tag_T_1 = bits(s2_req.addr, 31, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 431:82] node _s2_victim_tag_T_2 = bits(s2_victim_way, 0, 0) @[src/main/scala/chisel3/util/Mux.scala 32:36] node s2_victim_tag = mux(_s2_victim_tag_T, _s2_victim_tag_T_1, s2_meta_corrected_0.tag) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 431:26] node _s2_victim_state_T = bits(s2_victim_way, 0, 0) @[src/main/scala/chisel3/util/Mux.scala 32:36] node s2_victim_state = mux(s2_hit_valid, s2_hit_state, s2_meta_corrected_0.coh) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 432:28] node _r_T_59 = cat(probe_bits.param, s2_probe_state.state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 120:19] node _r_T_60 = cat(UInt<2>(0h0), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 122:10] node _r_T_61 = cat(UInt<2>(0h0), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 123:10] node _r_T_62 = cat(UInt<2>(0h0), UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 124:10] node _r_T_63 = cat(UInt<2>(0h0), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 125:10] node _r_T_64 = cat(UInt<2>(0h1), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 126:10] node _r_T_65 = cat(UInt<2>(0h1), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 127:10] node _r_T_66 = cat(UInt<2>(0h1), UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 128:10] node _r_T_67 = cat(UInt<2>(0h1), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 129:10] node _r_T_68 = cat(UInt<2>(0h2), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 130:10] node _r_T_69 = cat(UInt<2>(0h2), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 131:10] node _r_T_70 = cat(UInt<2>(0h2), UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 132:10] node _r_T_71 = cat(UInt<2>(0h2), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 133:10] node _r_T_72 = eq(_r_T_71, _r_T_59) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_73 = mux(_r_T_72, UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_74 = mux(_r_T_72, UInt<3>(0h5), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_75 = mux(_r_T_72, UInt<2>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_76 = eq(_r_T_70, _r_T_59) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_77 = mux(_r_T_76, UInt<1>(0h0), _r_T_73) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_78 = mux(_r_T_76, UInt<3>(0h2), _r_T_74) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_79 = mux(_r_T_76, UInt<2>(0h0), _r_T_75) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_80 = eq(_r_T_69, _r_T_59) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_81 = mux(_r_T_80, UInt<1>(0h0), _r_T_77) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_82 = mux(_r_T_80, UInt<3>(0h1), _r_T_78) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_83 = mux(_r_T_80, UInt<2>(0h0), _r_T_79) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_84 = eq(_r_T_68, _r_T_59) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_85 = mux(_r_T_84, UInt<1>(0h1), _r_T_81) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_86 = mux(_r_T_84, UInt<3>(0h1), _r_T_82) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_87 = mux(_r_T_84, UInt<2>(0h0), _r_T_83) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_88 = eq(_r_T_67, _r_T_59) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_89 = mux(_r_T_88, UInt<1>(0h0), _r_T_85) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_90 = mux(_r_T_88, UInt<3>(0h5), _r_T_86) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_91 = mux(_r_T_88, UInt<2>(0h0), _r_T_87) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_92 = eq(_r_T_66, _r_T_59) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_89) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_94 = mux(_r_T_92, UInt<3>(0h4), _r_T_90) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_95 = mux(_r_T_92, UInt<2>(0h1), _r_T_91) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_96 = eq(_r_T_65, _r_T_59) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_97 = mux(_r_T_96, UInt<1>(0h0), _r_T_93) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_98 = mux(_r_T_96, UInt<3>(0h0), _r_T_94) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_99 = mux(_r_T_96, UInt<2>(0h1), _r_T_95) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_100 = eq(_r_T_64, _r_T_59) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_101 = mux(_r_T_100, UInt<1>(0h1), _r_T_97) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_102 = mux(_r_T_100, UInt<3>(0h0), _r_T_98) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_103 = mux(_r_T_100, UInt<2>(0h1), _r_T_99) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_104 = eq(_r_T_63, _r_T_59) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_105 = mux(_r_T_104, UInt<1>(0h0), _r_T_101) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_106 = mux(_r_T_104, UInt<3>(0h5), _r_T_102) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_107 = mux(_r_T_104, UInt<2>(0h0), _r_T_103) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_108 = eq(_r_T_62, _r_T_59) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_109 = mux(_r_T_108, UInt<1>(0h0), _r_T_105) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_110 = mux(_r_T_108, UInt<3>(0h4), _r_T_106) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_111 = mux(_r_T_108, UInt<2>(0h1), _r_T_107) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_112 = eq(_r_T_61, _r_T_59) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_113 = mux(_r_T_112, UInt<1>(0h0), _r_T_109) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_114 = mux(_r_T_112, UInt<3>(0h3), _r_T_110) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_115 = mux(_r_T_112, UInt<2>(0h2), _r_T_111) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_116 = eq(_r_T_60, _r_T_59) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node s2_prb_ack_data = mux(_r_T_116, UInt<1>(0h1), _r_T_113) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node s2_report_param = mux(_r_T_116, UInt<3>(0h3), _r_T_114) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node r_3 = mux(_r_T_116, UInt<2>(0h2), _r_T_115) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] wire probeNewCoh : { state : UInt<2>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 160:20] connect probeNewCoh.state, r_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 161:16] node _r_T_117 = eq(UInt<5>(0h10), UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 140:24] node _r_T_118 = mux(_r_T_117, UInt<2>(0h2), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 140:24] node _r_T_119 = eq(UInt<5>(0h12), UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 140:24] node _r_T_120 = mux(_r_T_119, UInt<2>(0h1), _r_T_118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 140:24] node _r_T_121 = eq(UInt<5>(0h13), UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 140:24] node _r_T_122 = mux(_r_T_121, UInt<2>(0h0), _r_T_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 140:24] node _r_T_123 = cat(_r_T_122, s2_victim_state.state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 120:19] node _r_T_124 = cat(UInt<2>(0h0), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 122:10] node _r_T_125 = cat(UInt<2>(0h0), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 123:10] node _r_T_126 = cat(UInt<2>(0h0), UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 124:10] node _r_T_127 = cat(UInt<2>(0h0), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 125:10] node _r_T_128 = cat(UInt<2>(0h1), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 126:10] node _r_T_129 = cat(UInt<2>(0h1), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 127:10] node _r_T_130 = cat(UInt<2>(0h1), UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 128:10] node _r_T_131 = cat(UInt<2>(0h1), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 129:10] node _r_T_132 = cat(UInt<2>(0h2), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 130:10] node _r_T_133 = cat(UInt<2>(0h2), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 131:10] node _r_T_134 = cat(UInt<2>(0h2), UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 132:10] node _r_T_135 = cat(UInt<2>(0h2), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 133:10] node _r_T_136 = eq(_r_T_135, _r_T_123) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_137 = mux(_r_T_136, UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_138 = mux(_r_T_136, UInt<3>(0h5), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_139 = mux(_r_T_136, UInt<2>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_140 = eq(_r_T_134, _r_T_123) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_141 = mux(_r_T_140, UInt<1>(0h0), _r_T_137) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_142 = mux(_r_T_140, UInt<3>(0h2), _r_T_138) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_143 = mux(_r_T_140, UInt<2>(0h0), _r_T_139) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_144 = eq(_r_T_133, _r_T_123) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_145 = mux(_r_T_144, UInt<1>(0h0), _r_T_141) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_146 = mux(_r_T_144, UInt<3>(0h1), _r_T_142) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_147 = mux(_r_T_144, UInt<2>(0h0), _r_T_143) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_148 = eq(_r_T_132, _r_T_123) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_149 = mux(_r_T_148, UInt<1>(0h1), _r_T_145) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_150 = mux(_r_T_148, UInt<3>(0h1), _r_T_146) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_151 = mux(_r_T_148, UInt<2>(0h0), _r_T_147) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_152 = eq(_r_T_131, _r_T_123) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_153 = mux(_r_T_152, UInt<1>(0h0), _r_T_149) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_154 = mux(_r_T_152, UInt<3>(0h5), _r_T_150) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_155 = mux(_r_T_152, UInt<2>(0h0), _r_T_151) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_156 = eq(_r_T_130, _r_T_123) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_157 = mux(_r_T_156, UInt<1>(0h0), _r_T_153) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_158 = mux(_r_T_156, UInt<3>(0h4), _r_T_154) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_159 = mux(_r_T_156, UInt<2>(0h1), _r_T_155) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_160 = eq(_r_T_129, _r_T_123) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_157) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_162 = mux(_r_T_160, UInt<3>(0h0), _r_T_158) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_163 = mux(_r_T_160, UInt<2>(0h1), _r_T_159) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_164 = eq(_r_T_128, _r_T_123) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_165 = mux(_r_T_164, UInt<1>(0h1), _r_T_161) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_166 = mux(_r_T_164, UInt<3>(0h0), _r_T_162) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_167 = mux(_r_T_164, UInt<2>(0h1), _r_T_163) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_168 = eq(_r_T_127, _r_T_123) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_169 = mux(_r_T_168, UInt<1>(0h0), _r_T_165) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_170 = mux(_r_T_168, UInt<3>(0h5), _r_T_166) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_171 = mux(_r_T_168, UInt<2>(0h0), _r_T_167) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_172 = eq(_r_T_126, _r_T_123) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_173 = mux(_r_T_172, UInt<1>(0h0), _r_T_169) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_174 = mux(_r_T_172, UInt<3>(0h4), _r_T_170) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_175 = mux(_r_T_172, UInt<2>(0h1), _r_T_171) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_176 = eq(_r_T_125, _r_T_123) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node _r_T_177 = mux(_r_T_176, UInt<1>(0h0), _r_T_173) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node _r_T_178 = mux(_r_T_176, UInt<3>(0h3), _r_T_174) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node _r_T_179 = mux(_r_T_176, UInt<2>(0h2), _r_T_175) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] node _r_T_180 = eq(_r_T_124, _r_T_123) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 56:20] node s2_victim_dirty = mux(_r_T_180, UInt<1>(0h1), _r_T_177) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:9] node s2_shrink_param = mux(_r_T_180, UInt<3>(0h3), _r_T_178) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:36] node r_3_1 = mux(_r_T_180, UInt<2>(0h2), _r_T_179) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 38:63] wire voluntaryNewCoh : { state : UInt<2>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 160:20] connect voluntaryNewCoh.state, r_3_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 161:16] node _s2_update_meta_T = eq(s2_hit_state.state, s2_new_hit_state.state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 46:46] node s2_update_meta = eq(_s2_update_meta_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 47:40] node s2_dont_nack_uncached = and(s2_valid_uncached_pending, tl_out_a.ready) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 438:57] node _s2_dont_nack_misc_T = eq(s2_meta_error, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 439:46] node _s2_dont_nack_misc_T_1 = and(s2_valid_masked, _s2_dont_nack_misc_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 439:43] node _s2_dont_nack_misc_T_2 = and(UInt<1>(0h0), s2_cmd_flush_all) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 440:23] node _s2_dont_nack_misc_T_3 = and(_s2_dont_nack_misc_T_2, flushed) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 440:43] node _s2_dont_nack_misc_T_4 = eq(flushing, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 440:57] node _s2_dont_nack_misc_T_5 = and(_s2_dont_nack_misc_T_3, _s2_dont_nack_misc_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 440:54] node _s2_dont_nack_misc_T_6 = and(UInt<1>(0h0), s2_cmd_flush_line) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 441:23] node _s2_dont_nack_misc_T_7 = eq(s2_hit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 441:47] node _s2_dont_nack_misc_T_8 = and(_s2_dont_nack_misc_T_6, _s2_dont_nack_misc_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 441:44] node _s2_dont_nack_misc_T_9 = or(_s2_dont_nack_misc_T_5, _s2_dont_nack_misc_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 440:67] node _s2_dont_nack_misc_T_10 = eq(s2_req.cmd, UInt<5>(0h17)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 442:17] node _s2_dont_nack_misc_T_11 = or(_s2_dont_nack_misc_T_9, _s2_dont_nack_misc_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 441:55] node s2_dont_nack_misc = and(_s2_dont_nack_misc_T_1, _s2_dont_nack_misc_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 439:61] node _io_cpu_s2_nack_T = eq(s2_dont_nack_uncached, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 443:41] node _io_cpu_s2_nack_T_1 = and(s2_valid_no_xcpt, _io_cpu_s2_nack_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 443:38] node _io_cpu_s2_nack_T_2 = eq(s2_dont_nack_misc, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 443:67] node _io_cpu_s2_nack_T_3 = and(_io_cpu_s2_nack_T_1, _io_cpu_s2_nack_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 443:64] node _io_cpu_s2_nack_T_4 = eq(s2_valid_hit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 443:89] node _io_cpu_s2_nack_T_5 = and(_io_cpu_s2_nack_T_3, _io_cpu_s2_nack_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 443:86] connect io.cpu.s2_nack, _io_cpu_s2_nack_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 443:18] node _T_38 = and(s2_valid_hit_pre_data_ecc_and_waw, s2_update_meta) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 444:62] node _T_39 = or(io.cpu.s2_nack, _T_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 444:24] when _T_39 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 444:82] connect s1_nack, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 444:92] node _s2_first_meta_corrected_T = bits(s2_meta_correctable_errors, 0, 0) @[src/main/scala/chisel3/util/Mux.scala 52:83] node _metaArb_io_in_1_valid_T = or(s2_valid_masked, s2_flush_valid_pre_tag_ecc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 448:63] node _metaArb_io_in_1_valid_T_1 = or(_metaArb_io_in_1_valid_T, s2_probe) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 448:93] node _metaArb_io_in_1_valid_T_2 = and(s2_meta_error, _metaArb_io_in_1_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 448:43] connect metaArb.io.in[1].valid, _metaArb_io_in_1_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 448:26] connect metaArb.io.in[1].bits.write, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 449:31] node _metaArb_io_in_1_bits_way_en_T = bits(s2_meta_correctable_errors, 0, 0) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _metaArb_io_in_1_bits_way_en_T_1 = mux(_metaArb_io_in_1_bits_way_en_T, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _metaArb_io_in_1_bits_way_en_T_2 = mux(s2_meta_error_uncorrectable, UInt<1>(0h0), _metaArb_io_in_1_bits_way_en_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 450:69] node _metaArb_io_in_1_bits_way_en_T_3 = or(s2_meta_uncorrectable_errors, _metaArb_io_in_1_bits_way_en_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 450:64] connect metaArb.io.in[1].bits.way_en, _metaArb_io_in_1_bits_way_en_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 450:32] node _metaArb_io_in_1_bits_idx_T = bits(probe_bits.address, 19, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1198:47] node _metaArb_io_in_1_bits_idx_T_1 = bits(s2_vaddr, 19, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 451:76] node _metaArb_io_in_1_bits_idx_T_2 = mux(s2_probe, _metaArb_io_in_1_bits_idx_T, _metaArb_io_in_1_bits_idx_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 451:35] connect metaArb.io.in[1].bits.idx, _metaArb_io_in_1_bits_idx_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 451:29] node _metaArb_io_in_1_bits_addr_T = shr(io.cpu.req.bits.addr, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 452:58] node _metaArb_io_in_1_bits_addr_T_1 = shl(metaArb.io.in[1].bits.idx, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 452:98] node _metaArb_io_in_1_bits_addr_T_2 = cat(_metaArb_io_in_1_bits_addr_T, _metaArb_io_in_1_bits_addr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 452:36] connect metaArb.io.in[1].bits.addr, _metaArb_io_in_1_bits_addr_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 452:30] wire metaArb_io_in_1_bits_data_new_meta : { coh : { state : UInt<2>}, tag : UInt<12>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 454:31] connect metaArb_io_in_1_bits_data_new_meta, s2_meta_corrected_0 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 454:31] when s2_meta_error_uncorrectable : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 455:40] wire metaArb_io_in_1_bits_data_new_meta_coh_meta : { state : UInt<2>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 160:20] connect metaArb_io_in_1_bits_data_new_meta_coh_meta.state, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 161:16] connect metaArb_io_in_1_bits_data_new_meta.coh, metaArb_io_in_1_bits_data_new_meta_coh_meta @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 455:55] node _metaArb_io_in_1_bits_data_T = cat(metaArb_io_in_1_bits_data_new_meta.coh.state, metaArb_io_in_1_bits_data_new_meta.tag) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 456:14] connect metaArb.io.in[1].bits.data, _metaArb_io_in_1_bits_data_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 453:30] node _metaArb_io_in_2_valid_T = and(s2_valid_hit_pre_data_ecc_and_waw, s2_update_meta) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 460:63] connect metaArb.io.in[2].valid, _metaArb_io_in_2_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 460:26] node _metaArb_io_in_2_bits_write_T = eq(io.cpu.s2_kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 461:34] connect metaArb.io.in[2].bits.write, _metaArb_io_in_2_bits_write_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 461:31] connect metaArb.io.in[2].bits.way_en, s2_victim_or_hit_way @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 462:32] node _metaArb_io_in_2_bits_idx_T = bits(s2_vaddr, 19, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 463:40] connect metaArb.io.in[2].bits.idx, _metaArb_io_in_2_bits_idx_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 463:29] node _metaArb_io_in_2_bits_addr_T = shr(io.cpu.req.bits.addr, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 464:58] node _metaArb_io_in_2_bits_addr_T_1 = bits(s2_vaddr, 19, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 464:80] node _metaArb_io_in_2_bits_addr_T_2 = cat(_metaArb_io_in_2_bits_addr_T, _metaArb_io_in_2_bits_addr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 464:36] connect metaArb.io.in[2].bits.addr, _metaArb_io_in_2_bits_addr_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 464:30] node _metaArb_io_in_2_bits_data_T = shr(s2_req.addr, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 465:68] wire metaArb_io_in_2_bits_data_meta : { coh : { state : UInt<2>}, tag : UInt<12>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 305:20] connect metaArb_io_in_2_bits_data_meta.tag, _metaArb_io_in_2_bits_data_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 306:14] connect metaArb_io_in_2_bits_data_meta.coh, s2_new_hit_state @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 307:14] node _metaArb_io_in_2_bits_data_T_1 = cat(metaArb_io_in_2_bits_data_meta.coh.state, metaArb_io_in_2_bits_data_meta.tag) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 465:97] connect metaArb.io.in[2].bits.data, _metaArb_io_in_2_bits_data_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 465:30] node _s2_lr_T = eq(s2_req.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 468:70] node s2_lr = and(UInt<1>(0h0), _s2_lr_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 468:56] node _s2_sc_T = eq(s2_req.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 469:70] node s2_sc = and(UInt<1>(0h0), _s2_sc_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 469:56] regreset lrscCount : UInt, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 470:26] node lrscValid = gt(lrscCount, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 471:29] node _lrscBackingOff_T = gt(lrscCount, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 472:34] node _lrscBackingOff_T_1 = eq(lrscValid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 472:43] node lrscBackingOff = and(_lrscBackingOff_T, _lrscBackingOff_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 472:40] reg lrscAddr : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 473:21] node _lrscAddrMatch_T = shr(s2_req.addr, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 474:49] node lrscAddrMatch = eq(lrscAddr, _lrscAddrMatch_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 474:32] node _s2_sc_fail_T = and(lrscValid, lrscAddrMatch) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 475:41] node _s2_sc_fail_T_1 = eq(_s2_sc_fail_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 475:29] node s2_sc_fail = and(s2_sc, _s2_sc_fail_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 475:26] node _T_40 = and(s2_valid_hit, s2_lr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 476:23] node _T_41 = eq(cached_grant_wait, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 476:35] node _T_42 = and(_T_40, _T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 476:32] node _T_43 = or(_T_42, s2_valid_cached_miss) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 476:54] node _T_44 = eq(io.cpu.s2_kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 476:82] node _T_45 = and(_T_43, _T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 476:79] when _T_45 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 476:99] node _lrscCount_T = mux(s2_hit, UInt<7>(0h4f), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 477:21] connect lrscCount, _lrscCount_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 477:15] node _lrscAddr_T = shr(s2_req.addr, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 478:29] connect lrscAddr, _lrscAddr_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 478:14] node _T_46 = gt(lrscCount, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 480:19] when _T_46 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 480:26] node _lrscCount_T_1 = sub(lrscCount, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 480:51] node _lrscCount_T_2 = tail(_lrscCount_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 480:51] connect lrscCount, _lrscCount_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 480:38] node _T_47 = and(s2_valid_not_killed, lrscValid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 481:29] when _T_47 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 481:43] connect lrscCount, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 481:55] when s1_probe : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 482:19] connect lrscCount, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 482:31] node _s2_correct_T = eq(any_pstore_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 485:37] node _s2_correct_T_1 = and(s2_data_error, _s2_correct_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 485:34] node _s2_correct_T_2 = or(any_pstore_valid, s2_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 485:84] reg s2_correct_REG : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 485:66] connect s2_correct_REG, _s2_correct_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 485:66] node _s2_correct_T_3 = eq(s2_correct_REG, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 485:58] node _s2_correct_T_4 = and(_s2_correct_T_1, _s2_correct_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 485:55] node s2_correct = and(_s2_correct_T_4, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 485:97] node _s2_valid_correct_T = and(s2_valid_hit_pre_data_ecc_and_waw, s2_correct) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 487:60] node _s2_valid_correct_T_1 = eq(io.cpu.s2_kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 487:77] node s2_valid_correct = and(_s2_valid_correct_T, _s2_valid_correct_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 487:74] node _pstore1_cmd_T = and(s1_valid_not_nacked, s1_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 490:63] reg pstore1_cmd : UInt<5>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 490:30] when _pstore1_cmd_T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 490:30] connect pstore1_cmd, s1_req.cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 490:30] node _pstore1_addr_T = and(s1_valid_not_nacked, s1_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 491:62] reg pstore1_addr : UInt<34>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 491:31] when _pstore1_addr_T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 491:31] connect pstore1_addr, s1_vaddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 491:31] node _pstore1_data_T = and(s1_valid_not_nacked, s1_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 492:73] reg pstore1_data : UInt<64>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 492:31] when _pstore1_data_T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 492:31] connect pstore1_data, io.cpu.s1_data.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 492:31] node _pstore1_way_T = and(s1_valid_not_nacked, s1_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 493:63] reg pstore1_way : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 493:30] when _pstore1_way_T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 493:30] connect pstore1_way, s1_hit_way @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 493:30] node _pstore1_mask_T = and(s1_valid_not_nacked, s1_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 494:61] reg pstore1_mask : UInt<8>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 494:31] when _pstore1_mask_T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 494:31] connect pstore1_mask, s1_mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 494:31] wire pstore1_storegen_data : UInt @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 495:42] connect pstore1_storegen_data, pstore1_data @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 495:42] node _pstore1_rmw_T = eq(s1_req.cmd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_1 = eq(s1_req.cmd, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_2 = eq(s1_req.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_3 = eq(s1_req.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_4 = or(_pstore1_rmw_T, _pstore1_rmw_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore1_rmw_T_5 = or(_pstore1_rmw_T_4, _pstore1_rmw_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore1_rmw_T_6 = or(_pstore1_rmw_T_5, _pstore1_rmw_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore1_rmw_T_7 = eq(s1_req.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_8 = eq(s1_req.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_9 = eq(s1_req.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_10 = eq(s1_req.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_11 = or(_pstore1_rmw_T_7, _pstore1_rmw_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore1_rmw_T_12 = or(_pstore1_rmw_T_11, _pstore1_rmw_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore1_rmw_T_13 = or(_pstore1_rmw_T_12, _pstore1_rmw_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore1_rmw_T_14 = eq(s1_req.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_15 = eq(s1_req.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_16 = eq(s1_req.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_17 = eq(s1_req.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_18 = eq(s1_req.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_19 = or(_pstore1_rmw_T_14, _pstore1_rmw_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore1_rmw_T_20 = or(_pstore1_rmw_T_19, _pstore1_rmw_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore1_rmw_T_21 = or(_pstore1_rmw_T_20, _pstore1_rmw_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore1_rmw_T_22 = or(_pstore1_rmw_T_21, _pstore1_rmw_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore1_rmw_T_23 = or(_pstore1_rmw_T_13, _pstore1_rmw_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node _pstore1_rmw_T_24 = or(_pstore1_rmw_T_6, _pstore1_rmw_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 89:68] node _pstore1_rmw_T_25 = eq(s1_req.cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:32] node _pstore1_rmw_T_26 = eq(s1_req.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:49] node _pstore1_rmw_T_27 = or(_pstore1_rmw_T_25, _pstore1_rmw_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:42] node _pstore1_rmw_T_28 = eq(s1_req.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:66] node _pstore1_rmw_T_29 = or(_pstore1_rmw_T_27, _pstore1_rmw_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:59] node _pstore1_rmw_T_30 = eq(s1_req.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_31 = eq(s1_req.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_32 = eq(s1_req.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_33 = eq(s1_req.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_34 = or(_pstore1_rmw_T_30, _pstore1_rmw_T_31) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore1_rmw_T_35 = or(_pstore1_rmw_T_34, _pstore1_rmw_T_32) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore1_rmw_T_36 = or(_pstore1_rmw_T_35, _pstore1_rmw_T_33) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore1_rmw_T_37 = eq(s1_req.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_38 = eq(s1_req.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_39 = eq(s1_req.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_40 = eq(s1_req.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_41 = eq(s1_req.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore1_rmw_T_42 = or(_pstore1_rmw_T_37, _pstore1_rmw_T_38) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore1_rmw_T_43 = or(_pstore1_rmw_T_42, _pstore1_rmw_T_39) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore1_rmw_T_44 = or(_pstore1_rmw_T_43, _pstore1_rmw_T_40) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore1_rmw_T_45 = or(_pstore1_rmw_T_44, _pstore1_rmw_T_41) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore1_rmw_T_46 = or(_pstore1_rmw_T_36, _pstore1_rmw_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node _pstore1_rmw_T_47 = or(_pstore1_rmw_T_29, _pstore1_rmw_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:76] node _pstore1_rmw_T_48 = eq(s1_req.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:35] node _pstore1_rmw_T_49 = lt(s1_req.size, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:57] node _pstore1_rmw_T_50 = or(_pstore1_rmw_T_48, _pstore1_rmw_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:45] node _pstore1_rmw_T_51 = and(_pstore1_rmw_T_47, _pstore1_rmw_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:23] node _pstore1_rmw_T_52 = or(_pstore1_rmw_T_24, _pstore1_rmw_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1188:21] node _pstore1_rmw_T_53 = and(s1_valid_not_nacked, s1_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 496:84] reg pstore1_rmw_r : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 496:44] when _pstore1_rmw_T_53 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 496:44] connect pstore1_rmw_r, _pstore1_rmw_T_52 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 496:44] node pstore1_rmw = and(UInt<1>(0h1), pstore1_rmw_r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 496:32] node _pstore1_merge_likely_T = and(s2_valid_not_nacked_in_s1, s2_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 497:56] node pstore1_merge_likely = and(_pstore1_merge_likely_T, s2_store_merge) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 497:68] node _pstore1_merge_T = and(s2_valid_hit, s2_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 488:46] node _pstore1_merge_T_1 = eq(s2_sc_fail, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 488:61] node _pstore1_merge_T_2 = and(_pstore1_merge_T, _pstore1_merge_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 488:58] node _pstore1_merge_T_3 = eq(io.cpu.s2_kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 489:51] node _pstore1_merge_T_4 = and(_pstore1_merge_T_2, _pstore1_merge_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 489:48] node pstore1_merge = and(_pstore1_merge_T_4, s2_store_merge) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 498:38] regreset pstore2_valid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 499:30] node _pstore_drain_opportunistic_res_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_res_T_1 = eq(io.cpu.req.bits.cmd, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_res_T_2 = or(_pstore_drain_opportunistic_res_T, _pstore_drain_opportunistic_res_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore_drain_opportunistic_res_T_3 = eq(_pstore_drain_opportunistic_res_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1183:15] node _pstore_drain_opportunistic_res_T_4 = lt(io.cpu.req.bits.size, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1183:58] node pstore_drain_opportunistic_res = or(_pstore_drain_opportunistic_res_T_3, _pstore_drain_opportunistic_res_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1183:46] node _pstore_drain_opportunistic_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_1 = eq(io.cpu.req.bits.cmd, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_2 = eq(io.cpu.req.bits.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_3 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_4 = or(_pstore_drain_opportunistic_T, _pstore_drain_opportunistic_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore_drain_opportunistic_T_5 = or(_pstore_drain_opportunistic_T_4, _pstore_drain_opportunistic_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore_drain_opportunistic_T_6 = or(_pstore_drain_opportunistic_T_5, _pstore_drain_opportunistic_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore_drain_opportunistic_T_7 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_8 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_9 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_10 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_11 = or(_pstore_drain_opportunistic_T_7, _pstore_drain_opportunistic_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore_drain_opportunistic_T_12 = or(_pstore_drain_opportunistic_T_11, _pstore_drain_opportunistic_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore_drain_opportunistic_T_13 = or(_pstore_drain_opportunistic_T_12, _pstore_drain_opportunistic_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore_drain_opportunistic_T_14 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_15 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_16 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_17 = eq(io.cpu.req.bits.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_18 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_19 = or(_pstore_drain_opportunistic_T_14, _pstore_drain_opportunistic_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore_drain_opportunistic_T_20 = or(_pstore_drain_opportunistic_T_19, _pstore_drain_opportunistic_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore_drain_opportunistic_T_21 = or(_pstore_drain_opportunistic_T_20, _pstore_drain_opportunistic_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore_drain_opportunistic_T_22 = or(_pstore_drain_opportunistic_T_21, _pstore_drain_opportunistic_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore_drain_opportunistic_T_23 = or(_pstore_drain_opportunistic_T_13, _pstore_drain_opportunistic_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node _pstore_drain_opportunistic_T_24 = or(_pstore_drain_opportunistic_T_6, _pstore_drain_opportunistic_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 89:68] node _pstore_drain_opportunistic_T_25 = eq(io.cpu.req.bits.cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:32] node _pstore_drain_opportunistic_T_26 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:49] node _pstore_drain_opportunistic_T_27 = or(_pstore_drain_opportunistic_T_25, _pstore_drain_opportunistic_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:42] node _pstore_drain_opportunistic_T_28 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:66] node _pstore_drain_opportunistic_T_29 = or(_pstore_drain_opportunistic_T_27, _pstore_drain_opportunistic_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:59] node _pstore_drain_opportunistic_T_30 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_31 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_32 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_33 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_34 = or(_pstore_drain_opportunistic_T_30, _pstore_drain_opportunistic_T_31) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore_drain_opportunistic_T_35 = or(_pstore_drain_opportunistic_T_34, _pstore_drain_opportunistic_T_32) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore_drain_opportunistic_T_36 = or(_pstore_drain_opportunistic_T_35, _pstore_drain_opportunistic_T_33) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore_drain_opportunistic_T_37 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_38 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_39 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_40 = eq(io.cpu.req.bits.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_41 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _pstore_drain_opportunistic_T_42 = or(_pstore_drain_opportunistic_T_37, _pstore_drain_opportunistic_T_38) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore_drain_opportunistic_T_43 = or(_pstore_drain_opportunistic_T_42, _pstore_drain_opportunistic_T_39) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore_drain_opportunistic_T_44 = or(_pstore_drain_opportunistic_T_43, _pstore_drain_opportunistic_T_40) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore_drain_opportunistic_T_45 = or(_pstore_drain_opportunistic_T_44, _pstore_drain_opportunistic_T_41) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _pstore_drain_opportunistic_T_46 = or(_pstore_drain_opportunistic_T_36, _pstore_drain_opportunistic_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node _pstore_drain_opportunistic_T_47 = or(_pstore_drain_opportunistic_T_29, _pstore_drain_opportunistic_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:76] node _pstore_drain_opportunistic_T_48 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:35] node _pstore_drain_opportunistic_T_49 = lt(io.cpu.req.bits.size, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:57] node _pstore_drain_opportunistic_T_50 = or(_pstore_drain_opportunistic_T_48, _pstore_drain_opportunistic_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:45] node _pstore_drain_opportunistic_T_51 = and(_pstore_drain_opportunistic_T_47, _pstore_drain_opportunistic_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:23] node _pstore_drain_opportunistic_T_52 = or(_pstore_drain_opportunistic_T_24, _pstore_drain_opportunistic_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1188:21] node _pstore_drain_opportunistic_T_53 = eq(_pstore_drain_opportunistic_T_52, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1184:12] node _pstore_drain_opportunistic_T_54 = or(_pstore_drain_opportunistic_T_53, pstore_drain_opportunistic_res) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1184:28] node _pstore_drain_opportunistic_T_55 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1184:11] node _pstore_drain_opportunistic_T_56 = eq(_pstore_drain_opportunistic_T_55, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1184:11] when _pstore_drain_opportunistic_T_56 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1184:11] node _pstore_drain_opportunistic_T_57 = eq(_pstore_drain_opportunistic_T_54, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1184:11] when _pstore_drain_opportunistic_T_57 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1184:11] printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:1184 assert(!needsRead(req) || res)\n") : pstore_drain_opportunistic_printf @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1184:11] assert(clock, _pstore_drain_opportunistic_T_54, UInt<1>(0h1), "") : pstore_drain_opportunistic_assert @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1184:11] node _pstore_drain_opportunistic_T_58 = and(io.cpu.req.valid, pstore_drain_opportunistic_res) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 500:55] node _pstore_drain_opportunistic_T_59 = eq(_pstore_drain_opportunistic_T_58, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 500:36] node _pstore_drain_opportunistic_T_60 = and(s1_valid, s1_waw_hazard) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 500:106] node _pstore_drain_opportunistic_T_61 = eq(_pstore_drain_opportunistic_T_60, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 500:95] node pstore_drain_opportunistic = and(_pstore_drain_opportunistic_T_59, _pstore_drain_opportunistic_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 500:92] reg pstore_drain_on_miss_REG : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 501:56] connect pstore_drain_on_miss_REG, io.cpu.s2_nack @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 501:56] node pstore_drain_on_miss = or(releaseInFlight, pstore_drain_on_miss_REG) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 501:46] regreset pstore1_held : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 502:29] node _pstore1_valid_likely_T = and(s2_valid, s2_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 503:39] node pstore1_valid_likely = or(_pstore1_valid_likely_T, pstore1_held) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 503:51] node _pstore1_valid_T = and(s2_valid_hit, s2_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 488:46] node _pstore1_valid_T_1 = eq(s2_sc_fail, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 488:61] node _pstore1_valid_T_2 = and(_pstore1_valid_T, _pstore1_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 488:58] node _pstore1_valid_T_3 = eq(io.cpu.s2_kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 489:51] node _pstore1_valid_T_4 = and(_pstore1_valid_T_2, _pstore1_valid_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 489:48] node pstore1_valid = or(_pstore1_valid_T_4, pstore1_held) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 505:38] node _any_pstore_valid_T = or(pstore1_held, pstore2_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 506:36] connect any_pstore_valid, _any_pstore_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 506:20] node _pstore_drain_structural_T = and(pstore1_valid_likely, pstore2_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 507:54] node _pstore_drain_structural_T_1 = and(s1_valid, s1_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 507:85] node _pstore_drain_structural_T_2 = or(_pstore_drain_structural_T_1, pstore1_rmw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 507:98] node pstore_drain_structural = and(_pstore_drain_structural_T, _pstore_drain_structural_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 507:71] node _T_48 = and(s2_valid_hit_pre_data_ecc, s2_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 504:72] node _T_49 = eq(io.cpu.s2_kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 504:87] node _T_50 = and(_T_48, _T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 504:84] node _T_51 = or(_T_50, pstore1_held) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 504:96] node _T_52 = eq(_T_51, pstore1_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 508:63] node _T_53 = or(pstore1_rmw, _T_52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 508:22] node _T_54 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 508:9] node _T_55 = eq(_T_54, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 508:9] when _T_55 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 508:9] node _T_56 = eq(_T_53, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 508:9] when _T_56 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 508:9] printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:508 assert(pstore1_rmw || pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid)\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 508:9] assert(clock, _T_53, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 508:9] node _T_57 = and(pstore1_valid, pstore_drain_on_miss) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 510:24] node _T_58 = and(s1_valid_not_nacked, s1_waw_hazard) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 511:30] node pstore_drain_s2_kill = and(UInt<1>(0h1), io.cpu.s2_kill) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 513:25] node _pstore_drain_T = eq(pstore1_merge_likely, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 514:5] node _pstore_drain_T_1 = and(UInt<1>(0h1), pstore_drain_structural) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 515:17] node _pstore_drain_T_2 = and(s2_valid_hit_pre_data_ecc, s2_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 504:72] node _pstore_drain_T_3 = eq(pstore_drain_s2_kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 504:87] node _pstore_drain_T_4 = and(_pstore_drain_T_2, _pstore_drain_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 504:84] node _pstore_drain_T_5 = or(_pstore_drain_T_4, pstore1_held) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 504:96] node _pstore_drain_T_6 = eq(pstore1_rmw, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 516:44] node _pstore_drain_T_7 = and(_pstore_drain_T_5, _pstore_drain_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 516:41] node _pstore_drain_T_8 = or(_pstore_drain_T_7, pstore2_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 516:58] node _pstore_drain_T_9 = or(pstore_drain_opportunistic, pstore_drain_on_miss) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 516:107] node _pstore_drain_T_10 = and(_pstore_drain_T_8, _pstore_drain_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 516:76] node _pstore_drain_T_11 = or(_pstore_drain_T_1, _pstore_drain_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 515:44] node pstore_drain = and(_pstore_drain_T, _pstore_drain_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 514:27] node _pstore1_held_T = and(s2_valid_hit, s2_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 488:46] node _pstore1_held_T_1 = eq(s2_sc_fail, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 488:61] node _pstore1_held_T_2 = and(_pstore1_held_T, _pstore1_held_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 488:58] node _pstore1_held_T_3 = eq(io.cpu.s2_kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 489:51] node _pstore1_held_T_4 = and(_pstore1_held_T_2, _pstore1_held_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 489:48] node _pstore1_held_T_5 = eq(s2_store_merge, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 519:38] node _pstore1_held_T_6 = and(_pstore1_held_T_4, _pstore1_held_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 519:35] node _pstore1_held_T_7 = or(_pstore1_held_T_6, pstore1_held) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 519:54] node _pstore1_held_T_8 = and(_pstore1_held_T_7, pstore2_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 519:71] node _pstore1_held_T_9 = eq(pstore_drain, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 519:91] node _pstore1_held_T_10 = and(_pstore1_held_T_8, _pstore1_held_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 519:88] connect pstore1_held, _pstore1_held_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 519:16] node _advance_pstore1_T = or(pstore1_valid, s2_valid_correct) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 520:40] node _advance_pstore1_T_1 = eq(pstore2_valid, pstore_drain) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 520:79] node advance_pstore1 = and(_advance_pstore1_T, _advance_pstore1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 520:61] node _pstore2_valid_T = eq(pstore_drain, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 521:37] node _pstore2_valid_T_1 = and(pstore2_valid, _pstore2_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 521:34] node _pstore2_valid_T_2 = or(_pstore2_valid_T_1, advance_pstore1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 521:51] connect pstore2_valid, _pstore2_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 521:17] node _pstore2_addr_T = mux(s2_correct, s2_vaddr, pstore1_addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 522:35] reg pstore2_addr : UInt<34>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 522:31] when advance_pstore1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 522:31] connect pstore2_addr, _pstore2_addr_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 522:31] node _pstore2_way_T = mux(s2_correct, s2_hit_way, pstore1_way) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 523:34] reg pstore2_way : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 523:30] when advance_pstore1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 523:30] connect pstore2_way, _pstore2_way_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 523:30] node _pstore2_storegen_data_T = bits(pstore1_storegen_data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:44] node _pstore2_storegen_data_T_1 = bits(pstore1_mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:110] node _pstore2_storegen_data_T_2 = and(pstore1_merge, _pstore2_storegen_data_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:95] node _pstore2_storegen_data_T_3 = or(advance_pstore1, _pstore2_storegen_data_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:78] reg pstore2_storegen_data_r : UInt<8>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] when _pstore2_storegen_data_T_3 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] connect pstore2_storegen_data_r, _pstore2_storegen_data_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] node _pstore2_storegen_data_T_4 = bits(pstore1_storegen_data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:44] node _pstore2_storegen_data_T_5 = bits(pstore1_mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:110] node _pstore2_storegen_data_T_6 = and(pstore1_merge, _pstore2_storegen_data_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:95] node _pstore2_storegen_data_T_7 = or(advance_pstore1, _pstore2_storegen_data_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:78] reg pstore2_storegen_data_r_1 : UInt<8>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] when _pstore2_storegen_data_T_7 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] connect pstore2_storegen_data_r_1, _pstore2_storegen_data_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] node _pstore2_storegen_data_T_8 = bits(pstore1_storegen_data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:44] node _pstore2_storegen_data_T_9 = bits(pstore1_mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:110] node _pstore2_storegen_data_T_10 = and(pstore1_merge, _pstore2_storegen_data_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:95] node _pstore2_storegen_data_T_11 = or(advance_pstore1, _pstore2_storegen_data_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:78] reg pstore2_storegen_data_r_2 : UInt<8>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] when _pstore2_storegen_data_T_11 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] connect pstore2_storegen_data_r_2, _pstore2_storegen_data_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] node _pstore2_storegen_data_T_12 = bits(pstore1_storegen_data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:44] node _pstore2_storegen_data_T_13 = bits(pstore1_mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:110] node _pstore2_storegen_data_T_14 = and(pstore1_merge, _pstore2_storegen_data_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:95] node _pstore2_storegen_data_T_15 = or(advance_pstore1, _pstore2_storegen_data_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:78] reg pstore2_storegen_data_r_3 : UInt<8>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] when _pstore2_storegen_data_T_15 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] connect pstore2_storegen_data_r_3, _pstore2_storegen_data_T_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] node _pstore2_storegen_data_T_16 = bits(pstore1_storegen_data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:44] node _pstore2_storegen_data_T_17 = bits(pstore1_mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:110] node _pstore2_storegen_data_T_18 = and(pstore1_merge, _pstore2_storegen_data_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:95] node _pstore2_storegen_data_T_19 = or(advance_pstore1, _pstore2_storegen_data_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:78] reg pstore2_storegen_data_r_4 : UInt<8>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] when _pstore2_storegen_data_T_19 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] connect pstore2_storegen_data_r_4, _pstore2_storegen_data_T_16 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] node _pstore2_storegen_data_T_20 = bits(pstore1_storegen_data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:44] node _pstore2_storegen_data_T_21 = bits(pstore1_mask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:110] node _pstore2_storegen_data_T_22 = and(pstore1_merge, _pstore2_storegen_data_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:95] node _pstore2_storegen_data_T_23 = or(advance_pstore1, _pstore2_storegen_data_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:78] reg pstore2_storegen_data_r_5 : UInt<8>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] when _pstore2_storegen_data_T_23 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] connect pstore2_storegen_data_r_5, _pstore2_storegen_data_T_20 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] node _pstore2_storegen_data_T_24 = bits(pstore1_storegen_data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:44] node _pstore2_storegen_data_T_25 = bits(pstore1_mask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:110] node _pstore2_storegen_data_T_26 = and(pstore1_merge, _pstore2_storegen_data_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:95] node _pstore2_storegen_data_T_27 = or(advance_pstore1, _pstore2_storegen_data_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:78] reg pstore2_storegen_data_r_6 : UInt<8>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] when _pstore2_storegen_data_T_27 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] connect pstore2_storegen_data_r_6, _pstore2_storegen_data_T_24 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] node _pstore2_storegen_data_T_28 = bits(pstore1_storegen_data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:44] node _pstore2_storegen_data_T_29 = bits(pstore1_mask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:110] node _pstore2_storegen_data_T_30 = and(pstore1_merge, _pstore2_storegen_data_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:95] node _pstore2_storegen_data_T_31 = or(advance_pstore1, _pstore2_storegen_data_T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:78] reg pstore2_storegen_data_r_7 : UInt<8>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] when _pstore2_storegen_data_T_31 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] connect pstore2_storegen_data_r_7, _pstore2_storegen_data_T_28 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 526:22] node pstore2_storegen_data_lo_lo = cat(pstore2_storegen_data_r_1, pstore2_storegen_data_r) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pstore2_storegen_data_lo_hi = cat(pstore2_storegen_data_r_3, pstore2_storegen_data_r_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pstore2_storegen_data_lo = cat(pstore2_storegen_data_lo_hi, pstore2_storegen_data_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pstore2_storegen_data_hi_lo = cat(pstore2_storegen_data_r_5, pstore2_storegen_data_r_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pstore2_storegen_data_hi_hi = cat(pstore2_storegen_data_r_7, pstore2_storegen_data_r_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pstore2_storegen_data_hi = cat(pstore2_storegen_data_hi_hi, pstore2_storegen_data_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pstore2_storegen_data = cat(pstore2_storegen_data_hi, pstore2_storegen_data_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] reg pstore2_storegen_mask : UInt<8>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 529:19] node _pstore2_storegen_mask_T = or(advance_pstore1, pstore1_merge) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 530:27] when _pstore2_storegen_mask_T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 530:45] node _pstore2_storegen_mask_mergedMask_T = mux(pstore1_merge, pstore2_storegen_mask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 531:42] node pstore2_storegen_mask_mergedMask = or(pstore1_mask, _pstore2_storegen_mask_mergedMask_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 531:37] node _pstore2_storegen_mask_mask_T = not(pstore2_storegen_mask_mergedMask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 532:37] node _pstore2_storegen_mask_mask_T_1 = mux(s2_correct, UInt<1>(0h0), _pstore2_storegen_mask_mask_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 532:19] node _pstore2_storegen_mask_mask_T_2 = not(_pstore2_storegen_mask_mask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 532:15] connect pstore2_storegen_mask, _pstore2_storegen_mask_mask_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 532:12] connect s2_store_merge, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 536:18] node dataArb_io_in_0_valid_s2_kill = and(UInt<1>(0h0), io.cpu.s2_kill) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 513:25] node _dataArb_io_in_0_valid_T = eq(pstore1_merge_likely, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 514:5] node _dataArb_io_in_0_valid_T_1 = and(UInt<1>(0h1), pstore_drain_structural) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 515:17] node _dataArb_io_in_0_valid_T_2 = and(s2_valid_hit_pre_data_ecc, s2_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 504:72] node _dataArb_io_in_0_valid_T_3 = eq(dataArb_io_in_0_valid_s2_kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 504:87] node _dataArb_io_in_0_valid_T_4 = and(_dataArb_io_in_0_valid_T_2, _dataArb_io_in_0_valid_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 504:84] node _dataArb_io_in_0_valid_T_5 = or(_dataArb_io_in_0_valid_T_4, pstore1_held) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 504:96] node _dataArb_io_in_0_valid_T_6 = eq(pstore1_rmw, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 516:44] node _dataArb_io_in_0_valid_T_7 = and(_dataArb_io_in_0_valid_T_5, _dataArb_io_in_0_valid_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 516:41] node _dataArb_io_in_0_valid_T_8 = or(_dataArb_io_in_0_valid_T_7, pstore2_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 516:58] node _dataArb_io_in_0_valid_T_9 = or(pstore_drain_opportunistic, pstore_drain_on_miss) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 516:107] node _dataArb_io_in_0_valid_T_10 = and(_dataArb_io_in_0_valid_T_8, _dataArb_io_in_0_valid_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 516:76] node _dataArb_io_in_0_valid_T_11 = or(_dataArb_io_in_0_valid_T_1, _dataArb_io_in_0_valid_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 515:44] node _dataArb_io_in_0_valid_T_12 = and(_dataArb_io_in_0_valid_T, _dataArb_io_in_0_valid_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 514:27] connect dataArb.io.in[0].valid, _dataArb_io_in_0_valid_T_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 545:26] connect dataArb.io.in[0].bits.write, pstore_drain @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 546:31] node _dataArb_io_in_0_bits_addr_T = mux(pstore2_valid, pstore2_addr, pstore1_addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 547:36] connect dataArb.io.in[0].bits.addr, _dataArb_io_in_0_bits_addr_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 547:30] node _dataArb_io_in_0_bits_way_en_T = mux(pstore2_valid, pstore2_way, pstore1_way) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 548:38] connect dataArb.io.in[0].bits.way_en, _dataArb_io_in_0_bits_way_en_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 548:32] node _dataArb_io_in_0_bits_wdata_T = mux(pstore2_valid, pstore2_storegen_data, pstore1_data) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 549:63] node _dataArb_io_in_0_bits_wdata_T_1 = bits(_dataArb_io_in_0_bits_wdata_T, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _dataArb_io_in_0_bits_wdata_T_2 = bits(_dataArb_io_in_0_bits_wdata_T, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _dataArb_io_in_0_bits_wdata_T_3 = bits(_dataArb_io_in_0_bits_wdata_T, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _dataArb_io_in_0_bits_wdata_T_4 = bits(_dataArb_io_in_0_bits_wdata_T, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _dataArb_io_in_0_bits_wdata_T_5 = bits(_dataArb_io_in_0_bits_wdata_T, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _dataArb_io_in_0_bits_wdata_T_6 = bits(_dataArb_io_in_0_bits_wdata_T, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _dataArb_io_in_0_bits_wdata_T_7 = bits(_dataArb_io_in_0_bits_wdata_T, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _dataArb_io_in_0_bits_wdata_T_8 = bits(_dataArb_io_in_0_bits_wdata_T, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node dataArb_io_in_0_bits_wdata_lo_lo = cat(_dataArb_io_in_0_bits_wdata_T_2, _dataArb_io_in_0_bits_wdata_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node dataArb_io_in_0_bits_wdata_lo_hi = cat(_dataArb_io_in_0_bits_wdata_T_4, _dataArb_io_in_0_bits_wdata_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node dataArb_io_in_0_bits_wdata_lo = cat(dataArb_io_in_0_bits_wdata_lo_hi, dataArb_io_in_0_bits_wdata_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node dataArb_io_in_0_bits_wdata_hi_lo = cat(_dataArb_io_in_0_bits_wdata_T_6, _dataArb_io_in_0_bits_wdata_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node dataArb_io_in_0_bits_wdata_hi_hi = cat(_dataArb_io_in_0_bits_wdata_T_8, _dataArb_io_in_0_bits_wdata_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node dataArb_io_in_0_bits_wdata_hi = cat(dataArb_io_in_0_bits_wdata_hi_hi, dataArb_io_in_0_bits_wdata_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _dataArb_io_in_0_bits_wdata_T_9 = cat(dataArb_io_in_0_bits_wdata_hi, dataArb_io_in_0_bits_wdata_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] connect dataArb.io.in[0].bits.wdata, _dataArb_io_in_0_bits_wdata_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 549:31] node _dataArb_io_in_0_bits_wordMask_eccMask_T = bits(dataArb.io.in[0].bits.eccMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 551:49] node _dataArb_io_in_0_bits_wordMask_eccMask_T_1 = bits(dataArb.io.in[0].bits.eccMask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 551:49] node _dataArb_io_in_0_bits_wordMask_eccMask_T_2 = bits(dataArb.io.in[0].bits.eccMask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 551:49] node _dataArb_io_in_0_bits_wordMask_eccMask_T_3 = bits(dataArb.io.in[0].bits.eccMask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 551:49] node _dataArb_io_in_0_bits_wordMask_eccMask_T_4 = bits(dataArb.io.in[0].bits.eccMask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 551:49] node _dataArb_io_in_0_bits_wordMask_eccMask_T_5 = bits(dataArb.io.in[0].bits.eccMask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 551:49] node _dataArb_io_in_0_bits_wordMask_eccMask_T_6 = bits(dataArb.io.in[0].bits.eccMask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 551:49] node _dataArb_io_in_0_bits_wordMask_eccMask_T_7 = bits(dataArb.io.in[0].bits.eccMask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 551:49] node _dataArb_io_in_0_bits_wordMask_eccMask_T_8 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T, _dataArb_io_in_0_bits_wordMask_eccMask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_0_bits_wordMask_eccMask_T_9 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_8, _dataArb_io_in_0_bits_wordMask_eccMask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_0_bits_wordMask_eccMask_T_10 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_9, _dataArb_io_in_0_bits_wordMask_eccMask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_0_bits_wordMask_eccMask_T_11 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_10, _dataArb_io_in_0_bits_wordMask_eccMask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_0_bits_wordMask_eccMask_T_12 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_11, _dataArb_io_in_0_bits_wordMask_eccMask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_0_bits_wordMask_eccMask_T_13 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_12, _dataArb_io_in_0_bits_wordMask_eccMask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node dataArb_io_in_0_bits_wordMask_eccMask = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_13, _dataArb_io_in_0_bits_wordMask_eccMask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _dataArb_io_in_0_bits_wordMask_wordMask_T = mux(pstore2_valid, pstore2_addr, pstore1_addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 552:32] node dataArb_io_in_0_bits_wordMask_wordMask = dshl(UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node _dataArb_io_in_0_bits_wordMask_T = bits(dataArb_io_in_0_bits_wordMask_wordMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 553:20] node _dataArb_io_in_0_bits_wordMask_T_1 = bits(dataArb_io_in_0_bits_wordMask_wordMask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 553:20] node _dataArb_io_in_0_bits_wordMask_T_2 = cat(_dataArb_io_in_0_bits_wordMask_T_1, _dataArb_io_in_0_bits_wordMask_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 553:20] node _dataArb_io_in_0_bits_wordMask_T_3 = and(_dataArb_io_in_0_bits_wordMask_T_2, dataArb_io_in_0_bits_wordMask_eccMask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 553:55] connect dataArb.io.in[0].bits.wordMask, _dataArb_io_in_0_bits_wordMask_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 550:34] node _dataArb_io_in_0_bits_eccMask_T = mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 555:47] node _dataArb_io_in_0_bits_eccMask_T_1 = bits(_dataArb_io_in_0_bits_eccMask_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _dataArb_io_in_0_bits_eccMask_T_2 = bits(_dataArb_io_in_0_bits_eccMask_T, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _dataArb_io_in_0_bits_eccMask_T_3 = bits(_dataArb_io_in_0_bits_eccMask_T, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _dataArb_io_in_0_bits_eccMask_T_4 = bits(_dataArb_io_in_0_bits_eccMask_T, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _dataArb_io_in_0_bits_eccMask_T_5 = bits(_dataArb_io_in_0_bits_eccMask_T, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _dataArb_io_in_0_bits_eccMask_T_6 = bits(_dataArb_io_in_0_bits_eccMask_T, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _dataArb_io_in_0_bits_eccMask_T_7 = bits(_dataArb_io_in_0_bits_eccMask_T, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _dataArb_io_in_0_bits_eccMask_T_8 = bits(_dataArb_io_in_0_bits_eccMask_T, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _dataArb_io_in_0_bits_eccMask_T_9 = orr(_dataArb_io_in_0_bits_eccMask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _dataArb_io_in_0_bits_eccMask_T_10 = orr(_dataArb_io_in_0_bits_eccMask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _dataArb_io_in_0_bits_eccMask_T_11 = orr(_dataArb_io_in_0_bits_eccMask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _dataArb_io_in_0_bits_eccMask_T_12 = orr(_dataArb_io_in_0_bits_eccMask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _dataArb_io_in_0_bits_eccMask_T_13 = orr(_dataArb_io_in_0_bits_eccMask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _dataArb_io_in_0_bits_eccMask_T_14 = orr(_dataArb_io_in_0_bits_eccMask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _dataArb_io_in_0_bits_eccMask_T_15 = orr(_dataArb_io_in_0_bits_eccMask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _dataArb_io_in_0_bits_eccMask_T_16 = orr(_dataArb_io_in_0_bits_eccMask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node dataArb_io_in_0_bits_eccMask_lo_lo = cat(_dataArb_io_in_0_bits_eccMask_T_10, _dataArb_io_in_0_bits_eccMask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node dataArb_io_in_0_bits_eccMask_lo_hi = cat(_dataArb_io_in_0_bits_eccMask_T_12, _dataArb_io_in_0_bits_eccMask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node dataArb_io_in_0_bits_eccMask_lo = cat(dataArb_io_in_0_bits_eccMask_lo_hi, dataArb_io_in_0_bits_eccMask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node dataArb_io_in_0_bits_eccMask_hi_lo = cat(_dataArb_io_in_0_bits_eccMask_T_14, _dataArb_io_in_0_bits_eccMask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node dataArb_io_in_0_bits_eccMask_hi_hi = cat(_dataArb_io_in_0_bits_eccMask_T_16, _dataArb_io_in_0_bits_eccMask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node dataArb_io_in_0_bits_eccMask_hi = cat(dataArb_io_in_0_bits_eccMask_hi_hi, dataArb_io_in_0_bits_eccMask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _dataArb_io_in_0_bits_eccMask_T_17 = cat(dataArb_io_in_0_bits_eccMask_hi, dataArb_io_in_0_bits_eccMask_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] connect dataArb.io.in[0].bits.eccMask, _dataArb_io_in_0_bits_eccMask_T_17 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 555:33] node _s1_hazard_T = bits(pstore1_addr, 19, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 559:9] node _s1_hazard_T_1 = bits(s1_vaddr, 19, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 559:43] node _s1_hazard_T_2 = eq(_s1_hazard_T, _s1_hazard_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 559:31] node _s1_hazard_T_3 = bits(pstore1_mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_4 = bits(pstore1_mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_5 = bits(pstore1_mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_6 = bits(pstore1_mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_7 = bits(pstore1_mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_8 = bits(pstore1_mask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_9 = bits(pstore1_mask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_10 = bits(pstore1_mask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_11 = orr(_s1_hazard_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_12 = orr(_s1_hazard_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_13 = orr(_s1_hazard_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_14 = orr(_s1_hazard_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_15 = orr(_s1_hazard_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_16 = orr(_s1_hazard_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_17 = orr(_s1_hazard_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_18 = orr(_s1_hazard_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node s1_hazard_lo_lo = cat(_s1_hazard_T_12, _s1_hazard_T_11) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_lo_hi = cat(_s1_hazard_T_14, _s1_hazard_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_lo = cat(s1_hazard_lo_hi, s1_hazard_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_hi_lo = cat(_s1_hazard_T_16, _s1_hazard_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_hi_hi = cat(_s1_hazard_T_18, _s1_hazard_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_hi = cat(s1_hazard_hi_hi, s1_hazard_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _s1_hazard_T_19 = cat(s1_hazard_hi, s1_hazard_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _s1_hazard_T_20 = bits(_s1_hazard_T_19, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_21 = bits(_s1_hazard_T_19, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_22 = bits(_s1_hazard_T_19, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_23 = bits(_s1_hazard_T_19, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_24 = bits(_s1_hazard_T_19, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_25 = bits(_s1_hazard_T_19, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_26 = bits(_s1_hazard_T_19, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_27 = bits(_s1_hazard_T_19, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_lo_lo_1 = cat(_s1_hazard_T_21, _s1_hazard_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_lo_hi_1 = cat(_s1_hazard_T_23, _s1_hazard_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_lo_1 = cat(s1_hazard_lo_hi_1, s1_hazard_lo_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_hi_lo_1 = cat(_s1_hazard_T_25, _s1_hazard_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_hi_hi_1 = cat(_s1_hazard_T_27, _s1_hazard_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_hi_1 = cat(s1_hazard_hi_hi_1, s1_hazard_hi_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_28 = cat(s1_hazard_hi_1, s1_hazard_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_29 = bits(s1_mask_xwr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_30 = bits(s1_mask_xwr, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_31 = bits(s1_mask_xwr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_32 = bits(s1_mask_xwr, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_33 = bits(s1_mask_xwr, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_34 = bits(s1_mask_xwr, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_35 = bits(s1_mask_xwr, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_36 = bits(s1_mask_xwr, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_37 = orr(_s1_hazard_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_38 = orr(_s1_hazard_T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_39 = orr(_s1_hazard_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_40 = orr(_s1_hazard_T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_41 = orr(_s1_hazard_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_42 = orr(_s1_hazard_T_34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_43 = orr(_s1_hazard_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_44 = orr(_s1_hazard_T_36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node s1_hazard_lo_lo_2 = cat(_s1_hazard_T_38, _s1_hazard_T_37) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_lo_hi_2 = cat(_s1_hazard_T_40, _s1_hazard_T_39) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_lo_2 = cat(s1_hazard_lo_hi_2, s1_hazard_lo_lo_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_hi_lo_2 = cat(_s1_hazard_T_42, _s1_hazard_T_41) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_hi_hi_2 = cat(_s1_hazard_T_44, _s1_hazard_T_43) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_hi_2 = cat(s1_hazard_hi_hi_2, s1_hazard_hi_lo_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _s1_hazard_T_45 = cat(s1_hazard_hi_2, s1_hazard_lo_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _s1_hazard_T_46 = bits(_s1_hazard_T_45, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_47 = bits(_s1_hazard_T_45, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_48 = bits(_s1_hazard_T_45, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_49 = bits(_s1_hazard_T_45, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_50 = bits(_s1_hazard_T_45, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_51 = bits(_s1_hazard_T_45, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_52 = bits(_s1_hazard_T_45, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_53 = bits(_s1_hazard_T_45, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_lo_lo_3 = cat(_s1_hazard_T_47, _s1_hazard_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_lo_hi_3 = cat(_s1_hazard_T_49, _s1_hazard_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_lo_3 = cat(s1_hazard_lo_hi_3, s1_hazard_lo_lo_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_hi_lo_3 = cat(_s1_hazard_T_51, _s1_hazard_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_hi_hi_3 = cat(_s1_hazard_T_53, _s1_hazard_T_52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_hi_3 = cat(s1_hazard_hi_hi_3, s1_hazard_hi_lo_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_54 = cat(s1_hazard_hi_3, s1_hazard_lo_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_55 = and(_s1_hazard_T_28, _s1_hazard_T_54) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 560:38] node _s1_hazard_T_56 = orr(_s1_hazard_T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 560:66] node _s1_hazard_T_57 = and(pstore1_mask, s1_mask_xwr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 560:77] node _s1_hazard_T_58 = orr(_s1_hazard_T_57) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 560:92] node _s1_hazard_T_59 = mux(s1_write, _s1_hazard_T_56, _s1_hazard_T_58) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 560:8] node _s1_hazard_T_60 = and(_s1_hazard_T_2, _s1_hazard_T_59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 559:65] node _s1_hazard_T_61 = and(pstore1_valid_likely, _s1_hazard_T_60) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 562:27] node _s1_hazard_T_62 = bits(pstore2_addr, 19, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 559:9] node _s1_hazard_T_63 = bits(s1_vaddr, 19, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 559:43] node _s1_hazard_T_64 = eq(_s1_hazard_T_62, _s1_hazard_T_63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 559:31] node _s1_hazard_T_65 = bits(pstore2_storegen_mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_66 = bits(pstore2_storegen_mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_67 = bits(pstore2_storegen_mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_68 = bits(pstore2_storegen_mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_69 = bits(pstore2_storegen_mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_70 = bits(pstore2_storegen_mask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_71 = bits(pstore2_storegen_mask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_72 = bits(pstore2_storegen_mask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_73 = orr(_s1_hazard_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_74 = orr(_s1_hazard_T_66) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_75 = orr(_s1_hazard_T_67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_76 = orr(_s1_hazard_T_68) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_77 = orr(_s1_hazard_T_69) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_78 = orr(_s1_hazard_T_70) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_79 = orr(_s1_hazard_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_80 = orr(_s1_hazard_T_72) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node s1_hazard_lo_lo_4 = cat(_s1_hazard_T_74, _s1_hazard_T_73) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_lo_hi_4 = cat(_s1_hazard_T_76, _s1_hazard_T_75) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_lo_4 = cat(s1_hazard_lo_hi_4, s1_hazard_lo_lo_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_hi_lo_4 = cat(_s1_hazard_T_78, _s1_hazard_T_77) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_hi_hi_4 = cat(_s1_hazard_T_80, _s1_hazard_T_79) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_hi_4 = cat(s1_hazard_hi_hi_4, s1_hazard_hi_lo_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _s1_hazard_T_81 = cat(s1_hazard_hi_4, s1_hazard_lo_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _s1_hazard_T_82 = bits(_s1_hazard_T_81, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_83 = bits(_s1_hazard_T_81, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_84 = bits(_s1_hazard_T_81, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_85 = bits(_s1_hazard_T_81, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_86 = bits(_s1_hazard_T_81, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_87 = bits(_s1_hazard_T_81, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_88 = bits(_s1_hazard_T_81, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_89 = bits(_s1_hazard_T_81, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_lo_lo_5 = cat(_s1_hazard_T_83, _s1_hazard_T_82) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_lo_hi_5 = cat(_s1_hazard_T_85, _s1_hazard_T_84) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_lo_5 = cat(s1_hazard_lo_hi_5, s1_hazard_lo_lo_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_hi_lo_5 = cat(_s1_hazard_T_87, _s1_hazard_T_86) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_hi_hi_5 = cat(_s1_hazard_T_89, _s1_hazard_T_88) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_hi_5 = cat(s1_hazard_hi_hi_5, s1_hazard_hi_lo_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_90 = cat(s1_hazard_hi_5, s1_hazard_lo_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_91 = bits(s1_mask_xwr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_92 = bits(s1_mask_xwr, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_93 = bits(s1_mask_xwr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_94 = bits(s1_mask_xwr, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_95 = bits(s1_mask_xwr, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_96 = bits(s1_mask_xwr, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_97 = bits(s1_mask_xwr, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_98 = bits(s1_mask_xwr, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _s1_hazard_T_99 = orr(_s1_hazard_T_91) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_100 = orr(_s1_hazard_T_92) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_101 = orr(_s1_hazard_T_93) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_102 = orr(_s1_hazard_T_94) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_103 = orr(_s1_hazard_T_95) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_104 = orr(_s1_hazard_T_96) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_105 = orr(_s1_hazard_T_97) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node _s1_hazard_T_106 = orr(_s1_hazard_T_98) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1179:66] node s1_hazard_lo_lo_6 = cat(_s1_hazard_T_100, _s1_hazard_T_99) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_lo_hi_6 = cat(_s1_hazard_T_102, _s1_hazard_T_101) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_lo_6 = cat(s1_hazard_lo_hi_6, s1_hazard_lo_lo_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_hi_lo_6 = cat(_s1_hazard_T_104, _s1_hazard_T_103) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_hi_hi_6 = cat(_s1_hazard_T_106, _s1_hazard_T_105) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node s1_hazard_hi_6 = cat(s1_hazard_hi_hi_6, s1_hazard_hi_lo_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _s1_hazard_T_107 = cat(s1_hazard_hi_6, s1_hazard_lo_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _s1_hazard_T_108 = bits(_s1_hazard_T_107, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_109 = bits(_s1_hazard_T_107, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_110 = bits(_s1_hazard_T_107, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_111 = bits(_s1_hazard_T_107, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_112 = bits(_s1_hazard_T_107, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_113 = bits(_s1_hazard_T_107, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_114 = bits(_s1_hazard_T_107, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_115 = bits(_s1_hazard_T_107, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_lo_lo_7 = cat(_s1_hazard_T_109, _s1_hazard_T_108) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_lo_hi_7 = cat(_s1_hazard_T_111, _s1_hazard_T_110) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_lo_7 = cat(s1_hazard_lo_hi_7, s1_hazard_lo_lo_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_hi_lo_7 = cat(_s1_hazard_T_113, _s1_hazard_T_112) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_hi_hi_7 = cat(_s1_hazard_T_115, _s1_hazard_T_114) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node s1_hazard_hi_7 = cat(s1_hazard_hi_hi_7, s1_hazard_hi_lo_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_116 = cat(s1_hazard_hi_7, s1_hazard_lo_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1180:52] node _s1_hazard_T_117 = and(_s1_hazard_T_90, _s1_hazard_T_116) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 560:38] node _s1_hazard_T_118 = orr(_s1_hazard_T_117) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 560:66] node _s1_hazard_T_119 = and(pstore2_storegen_mask, s1_mask_xwr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 560:77] node _s1_hazard_T_120 = orr(_s1_hazard_T_119) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 560:92] node _s1_hazard_T_121 = mux(s1_write, _s1_hazard_T_118, _s1_hazard_T_120) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 560:8] node _s1_hazard_T_122 = and(_s1_hazard_T_64, _s1_hazard_T_121) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 559:65] node _s1_hazard_T_123 = and(pstore2_valid, _s1_hazard_T_122) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 563:21] node s1_hazard = or(_s1_hazard_T_61, _s1_hazard_T_123) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 562:69] node s1_raw_hazard = and(s1_read, s1_hazard) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 564:31] connect s1_waw_hazard, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 565:17] node _T_59 = and(s1_valid, s1_raw_hazard) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 569:18] when _T_59 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 569:36] connect s1_nack, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 569:46] reg io_cpu_s2_nack_cause_raw_REG : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 572:38] connect io_cpu_s2_nack_cause_raw_REG, s1_raw_hazard @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 572:38] node _io_cpu_s2_nack_cause_raw_T = eq(s2_waw_hazard, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 572:59] node _io_cpu_s2_nack_cause_raw_T_1 = or(_io_cpu_s2_nack_cause_raw_T, s2_store_merge) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 572:74] node _io_cpu_s2_nack_cause_raw_T_2 = eq(_io_cpu_s2_nack_cause_raw_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 572:57] node _io_cpu_s2_nack_cause_raw_T_3 = or(io_cpu_s2_nack_cause_raw_REG, _io_cpu_s2_nack_cause_raw_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 572:54] connect io.cpu.s2_nack_cause_raw, _io_cpu_s2_nack_cause_raw_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 572:28] node _a_source_T = not(uncachedInFlight[0]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 575:34] node _a_source_T_1 = shl(_a_source_T, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 575:59] node _a_source_T_2 = bits(_a_source_T_1, 0, 0) @[src/main/scala/chisel3/util/OneHot.scala 48:45] node _acquire_address_T = shr(s2_req.addr, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 576:38] node acquire_address = shl(_acquire_address_T, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 576:49] node _a_mask_T = shl(UInt<1>(0h0), 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 580:90] node a_mask = dshl(pstore1_mask, _a_mask_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 580:29] node _get_legal_T = leq(UInt<1>(0h0), s2_req.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _get_legal_T_1 = leq(s2_req.size, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _get_legal_T_2 = and(_get_legal_T, _get_legal_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _get_legal_T_3 = or(UInt<1>(0h0), _get_legal_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _get_legal_T_4 = xor(s2_req.addr, UInt<13>(0h1000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _get_legal_T_5 = cvt(_get_legal_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _get_legal_T_6 = and(_get_legal_T_5, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_7 = asSInt(_get_legal_T_6) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_8 = eq(_get_legal_T_7, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _get_legal_T_9 = and(_get_legal_T_3, _get_legal_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _get_legal_T_10 = leq(UInt<1>(0h0), s2_req.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _get_legal_T_11 = leq(s2_req.size, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _get_legal_T_12 = and(_get_legal_T_10, _get_legal_T_11) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _get_legal_T_13 = or(UInt<1>(0h0), _get_legal_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _get_legal_T_14 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _get_legal_T_15 = cvt(_get_legal_T_14) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _get_legal_T_16 = and(_get_legal_T_15, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_17 = asSInt(_get_legal_T_16) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_18 = eq(_get_legal_T_17, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _get_legal_T_19 = xor(s2_req.addr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _get_legal_T_20 = cvt(_get_legal_T_19) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _get_legal_T_21 = and(_get_legal_T_20, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_22 = asSInt(_get_legal_T_21) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_23 = eq(_get_legal_T_22, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _get_legal_T_24 = xor(s2_req.addr, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _get_legal_T_25 = cvt(_get_legal_T_24) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _get_legal_T_26 = and(_get_legal_T_25, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_27 = asSInt(_get_legal_T_26) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_28 = eq(_get_legal_T_27, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _get_legal_T_29 = xor(s2_req.addr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _get_legal_T_30 = cvt(_get_legal_T_29) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _get_legal_T_31 = and(_get_legal_T_30, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_32 = asSInt(_get_legal_T_31) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_33 = eq(_get_legal_T_32, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _get_legal_T_34 = xor(s2_req.addr, UInt<29>(0h10000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _get_legal_T_35 = cvt(_get_legal_T_34) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _get_legal_T_36 = and(_get_legal_T_35, asSInt(UInt<33>(0hfa018000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_37 = asSInt(_get_legal_T_36) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_38 = eq(_get_legal_T_37, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _get_legal_T_39 = xor(s2_req.addr, UInt<29>(0h10008000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _get_legal_T_40 = cvt(_get_legal_T_39) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _get_legal_T_41 = and(_get_legal_T_40, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_42 = asSInt(_get_legal_T_41) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_43 = eq(_get_legal_T_42, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _get_legal_T_44 = xor(s2_req.addr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _get_legal_T_45 = cvt(_get_legal_T_44) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _get_legal_T_46 = and(_get_legal_T_45, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_47 = asSInt(_get_legal_T_46) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_48 = eq(_get_legal_T_47, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _get_legal_T_49 = xor(s2_req.addr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _get_legal_T_50 = cvt(_get_legal_T_49) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _get_legal_T_51 = and(_get_legal_T_50, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_52 = asSInt(_get_legal_T_51) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_53 = eq(_get_legal_T_52, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _get_legal_T_54 = xor(s2_req.addr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _get_legal_T_55 = cvt(_get_legal_T_54) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _get_legal_T_56 = and(_get_legal_T_55, asSInt(UInt<33>(0hfa000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_57 = asSInt(_get_legal_T_56) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _get_legal_T_58 = eq(_get_legal_T_57, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _get_legal_T_59 = or(_get_legal_T_18, _get_legal_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _get_legal_T_60 = or(_get_legal_T_59, _get_legal_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _get_legal_T_61 = or(_get_legal_T_60, _get_legal_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _get_legal_T_62 = or(_get_legal_T_61, _get_legal_T_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _get_legal_T_63 = or(_get_legal_T_62, _get_legal_T_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _get_legal_T_64 = or(_get_legal_T_63, _get_legal_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _get_legal_T_65 = or(_get_legal_T_64, _get_legal_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _get_legal_T_66 = or(_get_legal_T_65, _get_legal_T_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _get_legal_T_67 = and(_get_legal_T_13, _get_legal_T_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _get_legal_T_68 = or(UInt<1>(0h0), _get_legal_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node get_legal = or(_get_legal_T_68, _get_legal_T_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire get : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 460:17] connect get.opcode, UInt<3>(0h4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 461:15] connect get.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 462:15] connect get.size, s2_req.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 463:15] connect get.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 464:15] connect get.address, s2_req.addr @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 465:15] invalidate get.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] invalidate get.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] invalidate get.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] invalidate get.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] invalidate get.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] invalidate get.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] invalidate get.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] node _get_a_mask_sizeOH_T = or(s2_req.size, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node get_a_mask_sizeOH_shiftAmount = bits(_get_a_mask_sizeOH_T, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _get_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), get_a_mask_sizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _get_a_mask_sizeOH_T_2 = bits(_get_a_mask_sizeOH_T_1, 2, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node get_a_mask_sizeOH = or(_get_a_mask_sizeOH_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] node get_a_mask_sub_sub_sub_0_1 = geq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 206:21] node get_a_mask_sub_sub_size = bits(get_a_mask_sizeOH, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node get_a_mask_sub_sub_bit = bits(s2_req.addr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node get_a_mask_sub_sub_nbit = eq(get_a_mask_sub_sub_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node get_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _get_a_mask_sub_sub_acc_T = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_0_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node get_a_mask_sub_sub_0_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node get_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _get_a_mask_sub_sub_acc_T_1 = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_1_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node get_a_mask_sub_sub_1_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node get_a_mask_sub_size = bits(get_a_mask_sizeOH, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node get_a_mask_sub_bit = bits(s2_req.addr, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node get_a_mask_sub_nbit = eq(get_a_mask_sub_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node get_a_mask_sub_0_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _get_a_mask_sub_acc_T = and(get_a_mask_sub_size, get_a_mask_sub_0_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node get_a_mask_sub_0_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node get_a_mask_sub_1_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _get_a_mask_sub_acc_T_1 = and(get_a_mask_sub_size, get_a_mask_sub_1_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node get_a_mask_sub_1_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node get_a_mask_sub_2_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _get_a_mask_sub_acc_T_2 = and(get_a_mask_sub_size, get_a_mask_sub_2_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node get_a_mask_sub_2_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node get_a_mask_sub_3_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _get_a_mask_sub_acc_T_3 = and(get_a_mask_sub_size, get_a_mask_sub_3_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node get_a_mask_sub_3_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node get_a_mask_size = bits(get_a_mask_sizeOH, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node get_a_mask_bit = bits(s2_req.addr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node get_a_mask_nbit = eq(get_a_mask_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node get_a_mask_eq = and(get_a_mask_sub_0_2, get_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _get_a_mask_acc_T = and(get_a_mask_size, get_a_mask_eq) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node get_a_mask_acc = or(get_a_mask_sub_0_1, _get_a_mask_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node get_a_mask_eq_1 = and(get_a_mask_sub_0_2, get_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _get_a_mask_acc_T_1 = and(get_a_mask_size, get_a_mask_eq_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node get_a_mask_acc_1 = or(get_a_mask_sub_0_1, _get_a_mask_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node get_a_mask_eq_2 = and(get_a_mask_sub_1_2, get_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _get_a_mask_acc_T_2 = and(get_a_mask_size, get_a_mask_eq_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node get_a_mask_acc_2 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node get_a_mask_eq_3 = and(get_a_mask_sub_1_2, get_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _get_a_mask_acc_T_3 = and(get_a_mask_size, get_a_mask_eq_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node get_a_mask_acc_3 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node get_a_mask_eq_4 = and(get_a_mask_sub_2_2, get_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _get_a_mask_acc_T_4 = and(get_a_mask_size, get_a_mask_eq_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node get_a_mask_acc_4 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node get_a_mask_eq_5 = and(get_a_mask_sub_2_2, get_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _get_a_mask_acc_T_5 = and(get_a_mask_size, get_a_mask_eq_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node get_a_mask_acc_5 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node get_a_mask_eq_6 = and(get_a_mask_sub_3_2, get_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _get_a_mask_acc_T_6 = and(get_a_mask_size, get_a_mask_eq_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node get_a_mask_acc_6 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node get_a_mask_eq_7 = and(get_a_mask_sub_3_2, get_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _get_a_mask_acc_T_7 = and(get_a_mask_size, get_a_mask_eq_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node get_a_mask_acc_7 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node get_a_mask_lo_lo = cat(get_a_mask_acc_1, get_a_mask_acc) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node get_a_mask_lo_hi = cat(get_a_mask_acc_3, get_a_mask_acc_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node get_a_mask_lo = cat(get_a_mask_lo_hi, get_a_mask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node get_a_mask_hi_lo = cat(get_a_mask_acc_5, get_a_mask_acc_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node get_a_mask_hi_hi = cat(get_a_mask_acc_7, get_a_mask_acc_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node get_a_mask_hi = cat(get_a_mask_hi_hi, get_a_mask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node _get_a_mask_T = cat(get_a_mask_hi, get_a_mask_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] connect get.mask, _get_a_mask_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 468:15] invalidate get.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 469:15] connect get.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 470:15] node _put_legal_T = leq(UInt<1>(0h0), s2_req.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _put_legal_T_1 = leq(s2_req.size, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _put_legal_T_2 = and(_put_legal_T, _put_legal_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _put_legal_T_3 = or(UInt<1>(0h0), _put_legal_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _put_legal_T_4 = xor(s2_req.addr, UInt<14>(0h2000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _put_legal_T_5 = cvt(_put_legal_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _put_legal_T_6 = and(_put_legal_T_5, asSInt(UInt<33>(0hfa01e000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_7 = asSInt(_put_legal_T_6) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_8 = eq(_put_legal_T_7, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _put_legal_T_9 = and(_put_legal_T_3, _put_legal_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _put_legal_T_10 = leq(UInt<1>(0h0), s2_req.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _put_legal_T_11 = leq(s2_req.size, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _put_legal_T_12 = and(_put_legal_T_10, _put_legal_T_11) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _put_legal_T_13 = or(UInt<1>(0h0), _put_legal_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _put_legal_T_14 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _put_legal_T_15 = cvt(_put_legal_T_14) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _put_legal_T_16 = and(_put_legal_T_15, asSInt(UInt<33>(0hfa01e000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_17 = asSInt(_put_legal_T_16) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_18 = eq(_put_legal_T_17, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _put_legal_T_19 = xor(s2_req.addr, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _put_legal_T_20 = cvt(_put_legal_T_19) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _put_legal_T_21 = and(_put_legal_T_20, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_22 = asSInt(_put_legal_T_21) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_23 = eq(_put_legal_T_22, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _put_legal_T_24 = xor(s2_req.addr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _put_legal_T_25 = cvt(_put_legal_T_24) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _put_legal_T_26 = and(_put_legal_T_25, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_27 = asSInt(_put_legal_T_26) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_28 = eq(_put_legal_T_27, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _put_legal_T_29 = xor(s2_req.addr, UInt<29>(0h10000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _put_legal_T_30 = cvt(_put_legal_T_29) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _put_legal_T_31 = and(_put_legal_T_30, asSInt(UInt<33>(0hfa018000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_32 = asSInt(_put_legal_T_31) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_33 = eq(_put_legal_T_32, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _put_legal_T_34 = xor(s2_req.addr, UInt<29>(0h10008000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _put_legal_T_35 = cvt(_put_legal_T_34) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _put_legal_T_36 = and(_put_legal_T_35, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_37 = asSInt(_put_legal_T_36) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_38 = eq(_put_legal_T_37, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _put_legal_T_39 = xor(s2_req.addr, UInt<29>(0h10012000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _put_legal_T_40 = cvt(_put_legal_T_39) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _put_legal_T_41 = and(_put_legal_T_40, asSInt(UInt<33>(0hfa01e000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_42 = asSInt(_put_legal_T_41) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_43 = eq(_put_legal_T_42, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _put_legal_T_44 = xor(s2_req.addr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _put_legal_T_45 = cvt(_put_legal_T_44) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _put_legal_T_46 = and(_put_legal_T_45, asSInt(UInt<33>(0hfa01e000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_47 = asSInt(_put_legal_T_46) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_48 = eq(_put_legal_T_47, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _put_legal_T_49 = xor(s2_req.addr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _put_legal_T_50 = cvt(_put_legal_T_49) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _put_legal_T_51 = and(_put_legal_T_50, asSInt(UInt<33>(0hfa000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_52 = asSInt(_put_legal_T_51) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_53 = eq(_put_legal_T_52, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _put_legal_T_54 = or(_put_legal_T_18, _put_legal_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _put_legal_T_55 = or(_put_legal_T_54, _put_legal_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _put_legal_T_56 = or(_put_legal_T_55, _put_legal_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _put_legal_T_57 = or(_put_legal_T_56, _put_legal_T_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _put_legal_T_58 = or(_put_legal_T_57, _put_legal_T_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _put_legal_T_59 = or(_put_legal_T_58, _put_legal_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _put_legal_T_60 = or(_put_legal_T_59, _put_legal_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _put_legal_T_61 = and(_put_legal_T_13, _put_legal_T_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _put_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _put_legal_T_63 = xor(s2_req.addr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _put_legal_T_64 = cvt(_put_legal_T_63) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _put_legal_T_65 = and(_put_legal_T_64, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_66 = asSInt(_put_legal_T_65) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _put_legal_T_67 = eq(_put_legal_T_66, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _put_legal_T_68 = and(_put_legal_T_62, _put_legal_T_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _put_legal_T_69 = or(UInt<1>(0h0), _put_legal_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node _put_legal_T_70 = or(_put_legal_T_69, _put_legal_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node put_legal = or(_put_legal_T_70, _put_legal_T_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire put : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 480:17] connect put.opcode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 481:15] connect put.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 482:15] connect put.size, s2_req.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 483:15] connect put.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 484:15] connect put.address, s2_req.addr @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 485:15] invalidate put.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate put.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate put.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate put.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate put.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate put.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate put.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] node _put_a_mask_sizeOH_T = or(s2_req.size, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node put_a_mask_sizeOH_shiftAmount = bits(_put_a_mask_sizeOH_T, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _put_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), put_a_mask_sizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _put_a_mask_sizeOH_T_2 = bits(_put_a_mask_sizeOH_T_1, 2, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node put_a_mask_sizeOH = or(_put_a_mask_sizeOH_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] node put_a_mask_sub_sub_sub_0_1 = geq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 206:21] node put_a_mask_sub_sub_size = bits(put_a_mask_sizeOH, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node put_a_mask_sub_sub_bit = bits(s2_req.addr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node put_a_mask_sub_sub_nbit = eq(put_a_mask_sub_sub_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node put_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), put_a_mask_sub_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _put_a_mask_sub_sub_acc_T = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_0_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node put_a_mask_sub_sub_0_1 = or(put_a_mask_sub_sub_sub_0_1, _put_a_mask_sub_sub_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node put_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), put_a_mask_sub_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _put_a_mask_sub_sub_acc_T_1 = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_1_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node put_a_mask_sub_sub_1_1 = or(put_a_mask_sub_sub_sub_0_1, _put_a_mask_sub_sub_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node put_a_mask_sub_size = bits(put_a_mask_sizeOH, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node put_a_mask_sub_bit = bits(s2_req.addr, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node put_a_mask_sub_nbit = eq(put_a_mask_sub_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node put_a_mask_sub_0_2 = and(put_a_mask_sub_sub_0_2, put_a_mask_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _put_a_mask_sub_acc_T = and(put_a_mask_sub_size, put_a_mask_sub_0_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node put_a_mask_sub_0_1 = or(put_a_mask_sub_sub_0_1, _put_a_mask_sub_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node put_a_mask_sub_1_2 = and(put_a_mask_sub_sub_0_2, put_a_mask_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _put_a_mask_sub_acc_T_1 = and(put_a_mask_sub_size, put_a_mask_sub_1_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node put_a_mask_sub_1_1 = or(put_a_mask_sub_sub_0_1, _put_a_mask_sub_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node put_a_mask_sub_2_2 = and(put_a_mask_sub_sub_1_2, put_a_mask_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _put_a_mask_sub_acc_T_2 = and(put_a_mask_sub_size, put_a_mask_sub_2_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node put_a_mask_sub_2_1 = or(put_a_mask_sub_sub_1_1, _put_a_mask_sub_acc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node put_a_mask_sub_3_2 = and(put_a_mask_sub_sub_1_2, put_a_mask_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _put_a_mask_sub_acc_T_3 = and(put_a_mask_sub_size, put_a_mask_sub_3_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node put_a_mask_sub_3_1 = or(put_a_mask_sub_sub_1_1, _put_a_mask_sub_acc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node put_a_mask_size = bits(put_a_mask_sizeOH, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node put_a_mask_bit = bits(s2_req.addr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node put_a_mask_nbit = eq(put_a_mask_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node put_a_mask_eq = and(put_a_mask_sub_0_2, put_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _put_a_mask_acc_T = and(put_a_mask_size, put_a_mask_eq) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node put_a_mask_acc = or(put_a_mask_sub_0_1, _put_a_mask_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node put_a_mask_eq_1 = and(put_a_mask_sub_0_2, put_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _put_a_mask_acc_T_1 = and(put_a_mask_size, put_a_mask_eq_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node put_a_mask_acc_1 = or(put_a_mask_sub_0_1, _put_a_mask_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node put_a_mask_eq_2 = and(put_a_mask_sub_1_2, put_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _put_a_mask_acc_T_2 = and(put_a_mask_size, put_a_mask_eq_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node put_a_mask_acc_2 = or(put_a_mask_sub_1_1, _put_a_mask_acc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node put_a_mask_eq_3 = and(put_a_mask_sub_1_2, put_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _put_a_mask_acc_T_3 = and(put_a_mask_size, put_a_mask_eq_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node put_a_mask_acc_3 = or(put_a_mask_sub_1_1, _put_a_mask_acc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node put_a_mask_eq_4 = and(put_a_mask_sub_2_2, put_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _put_a_mask_acc_T_4 = and(put_a_mask_size, put_a_mask_eq_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node put_a_mask_acc_4 = or(put_a_mask_sub_2_1, _put_a_mask_acc_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node put_a_mask_eq_5 = and(put_a_mask_sub_2_2, put_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _put_a_mask_acc_T_5 = and(put_a_mask_size, put_a_mask_eq_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node put_a_mask_acc_5 = or(put_a_mask_sub_2_1, _put_a_mask_acc_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node put_a_mask_eq_6 = and(put_a_mask_sub_3_2, put_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _put_a_mask_acc_T_6 = and(put_a_mask_size, put_a_mask_eq_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node put_a_mask_acc_6 = or(put_a_mask_sub_3_1, _put_a_mask_acc_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node put_a_mask_eq_7 = and(put_a_mask_sub_3_2, put_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _put_a_mask_acc_T_7 = and(put_a_mask_size, put_a_mask_eq_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node put_a_mask_acc_7 = or(put_a_mask_sub_3_1, _put_a_mask_acc_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node put_a_mask_lo_lo = cat(put_a_mask_acc_1, put_a_mask_acc) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node put_a_mask_lo_hi = cat(put_a_mask_acc_3, put_a_mask_acc_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node put_a_mask_lo = cat(put_a_mask_lo_hi, put_a_mask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node put_a_mask_hi_lo = cat(put_a_mask_acc_5, put_a_mask_acc_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node put_a_mask_hi_hi = cat(put_a_mask_acc_7, put_a_mask_acc_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node put_a_mask_hi = cat(put_a_mask_hi_hi, put_a_mask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node _put_a_mask_T = cat(put_a_mask_hi, put_a_mask_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] connect put.mask, _put_a_mask_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 488:15] connect put.data, pstore1_data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 489:15] connect put.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 490:15] node _putpartial_legal_T = leq(UInt<1>(0h0), s2_req.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _putpartial_legal_T_1 = leq(s2_req.size, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _putpartial_legal_T_2 = and(_putpartial_legal_T, _putpartial_legal_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _putpartial_legal_T_3 = or(UInt<1>(0h0), _putpartial_legal_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _putpartial_legal_T_4 = xor(s2_req.addr, UInt<14>(0h2000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _putpartial_legal_T_5 = cvt(_putpartial_legal_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _putpartial_legal_T_6 = and(_putpartial_legal_T_5, asSInt(UInt<33>(0hfa01e000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_7 = asSInt(_putpartial_legal_T_6) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_8 = eq(_putpartial_legal_T_7, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _putpartial_legal_T_9 = and(_putpartial_legal_T_3, _putpartial_legal_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _putpartial_legal_T_10 = leq(UInt<1>(0h0), s2_req.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _putpartial_legal_T_11 = leq(s2_req.size, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _putpartial_legal_T_12 = and(_putpartial_legal_T_10, _putpartial_legal_T_11) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _putpartial_legal_T_13 = or(UInt<1>(0h0), _putpartial_legal_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _putpartial_legal_T_14 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _putpartial_legal_T_15 = cvt(_putpartial_legal_T_14) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _putpartial_legal_T_16 = and(_putpartial_legal_T_15, asSInt(UInt<33>(0hfa01e000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_17 = asSInt(_putpartial_legal_T_16) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_18 = eq(_putpartial_legal_T_17, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _putpartial_legal_T_19 = xor(s2_req.addr, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _putpartial_legal_T_20 = cvt(_putpartial_legal_T_19) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _putpartial_legal_T_21 = and(_putpartial_legal_T_20, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_22 = asSInt(_putpartial_legal_T_21) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_23 = eq(_putpartial_legal_T_22, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _putpartial_legal_T_24 = xor(s2_req.addr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _putpartial_legal_T_25 = cvt(_putpartial_legal_T_24) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _putpartial_legal_T_26 = and(_putpartial_legal_T_25, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_27 = asSInt(_putpartial_legal_T_26) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_28 = eq(_putpartial_legal_T_27, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _putpartial_legal_T_29 = xor(s2_req.addr, UInt<29>(0h10000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _putpartial_legal_T_30 = cvt(_putpartial_legal_T_29) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _putpartial_legal_T_31 = and(_putpartial_legal_T_30, asSInt(UInt<33>(0hfa018000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_32 = asSInt(_putpartial_legal_T_31) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_33 = eq(_putpartial_legal_T_32, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _putpartial_legal_T_34 = xor(s2_req.addr, UInt<29>(0h10008000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _putpartial_legal_T_35 = cvt(_putpartial_legal_T_34) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _putpartial_legal_T_36 = and(_putpartial_legal_T_35, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_37 = asSInt(_putpartial_legal_T_36) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_38 = eq(_putpartial_legal_T_37, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _putpartial_legal_T_39 = xor(s2_req.addr, UInt<29>(0h10012000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _putpartial_legal_T_40 = cvt(_putpartial_legal_T_39) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _putpartial_legal_T_41 = and(_putpartial_legal_T_40, asSInt(UInt<33>(0hfa01e000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_42 = asSInt(_putpartial_legal_T_41) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_43 = eq(_putpartial_legal_T_42, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _putpartial_legal_T_44 = xor(s2_req.addr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _putpartial_legal_T_45 = cvt(_putpartial_legal_T_44) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _putpartial_legal_T_46 = and(_putpartial_legal_T_45, asSInt(UInt<33>(0hfa01e000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_47 = asSInt(_putpartial_legal_T_46) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_48 = eq(_putpartial_legal_T_47, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _putpartial_legal_T_49 = xor(s2_req.addr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _putpartial_legal_T_50 = cvt(_putpartial_legal_T_49) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _putpartial_legal_T_51 = and(_putpartial_legal_T_50, asSInt(UInt<33>(0hfa000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_52 = asSInt(_putpartial_legal_T_51) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_53 = eq(_putpartial_legal_T_52, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _putpartial_legal_T_54 = or(_putpartial_legal_T_18, _putpartial_legal_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _putpartial_legal_T_55 = or(_putpartial_legal_T_54, _putpartial_legal_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _putpartial_legal_T_56 = or(_putpartial_legal_T_55, _putpartial_legal_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _putpartial_legal_T_57 = or(_putpartial_legal_T_56, _putpartial_legal_T_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _putpartial_legal_T_58 = or(_putpartial_legal_T_57, _putpartial_legal_T_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _putpartial_legal_T_59 = or(_putpartial_legal_T_58, _putpartial_legal_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _putpartial_legal_T_60 = or(_putpartial_legal_T_59, _putpartial_legal_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _putpartial_legal_T_61 = and(_putpartial_legal_T_13, _putpartial_legal_T_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _putpartial_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _putpartial_legal_T_63 = xor(s2_req.addr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _putpartial_legal_T_64 = cvt(_putpartial_legal_T_63) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _putpartial_legal_T_65 = and(_putpartial_legal_T_64, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_66 = asSInt(_putpartial_legal_T_65) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _putpartial_legal_T_67 = eq(_putpartial_legal_T_66, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _putpartial_legal_T_68 = and(_putpartial_legal_T_62, _putpartial_legal_T_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _putpartial_legal_T_69 = or(UInt<1>(0h0), _putpartial_legal_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node _putpartial_legal_T_70 = or(_putpartial_legal_T_69, _putpartial_legal_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node putpartial_legal = or(_putpartial_legal_T_70, _putpartial_legal_T_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire putpartial : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 500:17] connect putpartial.opcode, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 501:15] connect putpartial.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 502:15] connect putpartial.size, s2_req.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 503:15] connect putpartial.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 504:15] connect putpartial.address, s2_req.addr @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 505:15] invalidate putpartial.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 506:15] invalidate putpartial.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 506:15] invalidate putpartial.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 506:15] invalidate putpartial.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 506:15] invalidate putpartial.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 506:15] invalidate putpartial.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 506:15] invalidate putpartial.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 506:15] connect putpartial.mask, a_mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 508:15] connect putpartial.data, pstore1_data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 509:15] connect putpartial.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 510:15] wire _atomics_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:51] connect _atomics_WIRE.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:51] connect _atomics_WIRE.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:51] connect _atomics_WIRE.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:51] connect _atomics_WIRE.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:51] connect _atomics_WIRE.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:51] connect _atomics_WIRE.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:51] connect _atomics_WIRE.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:51] connect _atomics_WIRE.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:51] connect _atomics_WIRE.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:51] connect _atomics_WIRE.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:51] connect _atomics_WIRE.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:51] connect _atomics_WIRE.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:51] connect _atomics_WIRE.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:51] connect _atomics_WIRE.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:51] connect _atomics_WIRE.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:51] wire _atomics_WIRE_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:38] connect _atomics_WIRE_1.corrupt, _atomics_WIRE.corrupt @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:38] connect _atomics_WIRE_1.data, _atomics_WIRE.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:38] connect _atomics_WIRE_1.mask, _atomics_WIRE.mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:38] connect _atomics_WIRE_1.user, _atomics_WIRE.user @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:38] connect _atomics_WIRE_1.address, _atomics_WIRE.address @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:38] connect _atomics_WIRE_1.source, _atomics_WIRE.source @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:38] connect _atomics_WIRE_1.size, _atomics_WIRE.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:38] connect _atomics_WIRE_1.param, _atomics_WIRE.param @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:38] connect _atomics_WIRE_1.opcode, _atomics_WIRE.opcode @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:38] node _atomics_legal_T = leq(UInt<1>(0h0), s2_req.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _atomics_legal_T_1 = leq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _atomics_legal_T_2 = and(_atomics_legal_T, _atomics_legal_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _atomics_legal_T_3 = or(UInt<1>(0h0), _atomics_legal_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _atomics_legal_T_4 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_5 = cvt(_atomics_legal_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_6 = and(_atomics_legal_T_5, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_7 = asSInt(_atomics_legal_T_6) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_8 = eq(_atomics_legal_T_7, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_9 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_10 = cvt(_atomics_legal_T_9) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_11 = and(_atomics_legal_T_10, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_12 = asSInt(_atomics_legal_T_11) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_13 = eq(_atomics_legal_T_12, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_14 = xor(s2_req.addr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_15 = cvt(_atomics_legal_T_14) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_16 = and(_atomics_legal_T_15, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_17 = asSInt(_atomics_legal_T_16) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_18 = eq(_atomics_legal_T_17, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_19 = xor(s2_req.addr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_20 = cvt(_atomics_legal_T_19) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_21 = and(_atomics_legal_T_20, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_22 = asSInt(_atomics_legal_T_21) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_23 = eq(_atomics_legal_T_22, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_24 = xor(s2_req.addr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_25 = cvt(_atomics_legal_T_24) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_26 = and(_atomics_legal_T_25, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_27 = asSInt(_atomics_legal_T_26) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_28 = eq(_atomics_legal_T_27, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_29 = xor(s2_req.addr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_30 = cvt(_atomics_legal_T_29) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_31 = and(_atomics_legal_T_30, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_32 = asSInt(_atomics_legal_T_31) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_33 = eq(_atomics_legal_T_32, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_34 = or(_atomics_legal_T_8, _atomics_legal_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_35 = or(_atomics_legal_T_34, _atomics_legal_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_36 = or(_atomics_legal_T_35, _atomics_legal_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_37 = or(_atomics_legal_T_36, _atomics_legal_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_38 = or(_atomics_legal_T_37, _atomics_legal_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_39 = and(_atomics_legal_T_3, _atomics_legal_T_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _atomics_legal_T_40 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _atomics_legal_T_41 = xor(s2_req.addr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_42 = cvt(_atomics_legal_T_41) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_43 = and(_atomics_legal_T_42, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_44 = asSInt(_atomics_legal_T_43) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_45 = eq(_atomics_legal_T_44, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_46 = and(_atomics_legal_T_40, _atomics_legal_T_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _atomics_legal_T_47 = or(UInt<1>(0h0), _atomics_legal_T_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node atomics_legal = or(_atomics_legal_T_47, _atomics_legal_T_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire atomics_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 534:17] connect atomics_a.opcode, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 535:15] connect atomics_a.param, UInt<3>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 536:15] connect atomics_a.size, s2_req.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 537:15] connect atomics_a.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 538:15] connect atomics_a.address, s2_req.addr @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 539:15] invalidate atomics_a.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] node _atomics_a_mask_sizeOH_T = or(s2_req.size, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node atomics_a_mask_sizeOH_shiftAmount = bits(_atomics_a_mask_sizeOH_T, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _atomics_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _atomics_a_mask_sizeOH_T_2 = bits(_atomics_a_mask_sizeOH_T_1, 2, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node atomics_a_mask_sizeOH = or(_atomics_a_mask_sizeOH_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] node atomics_a_mask_sub_sub_sub_0_1 = geq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 206:21] node atomics_a_mask_sub_sub_size = bits(atomics_a_mask_sizeOH, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_sub_sub_bit = bits(s2_req.addr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_sub_sub_nbit = eq(atomics_a_mask_sub_sub_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_sub_acc_T = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_0_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_sub_0_1 = or(atomics_a_mask_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_sub_acc_T_1 = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_1_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_sub_1_1 = or(atomics_a_mask_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_size = bits(atomics_a_mask_sizeOH, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_sub_bit = bits(s2_req.addr, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_sub_nbit = eq(atomics_a_mask_sub_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_sub_0_2 = and(atomics_a_mask_sub_sub_0_2, atomics_a_mask_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T = and(atomics_a_mask_sub_size, atomics_a_mask_sub_0_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_0_1 = or(atomics_a_mask_sub_sub_0_1, _atomics_a_mask_sub_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_1_2 = and(atomics_a_mask_sub_sub_0_2, atomics_a_mask_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_1 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_1_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_1_1 = or(atomics_a_mask_sub_sub_0_1, _atomics_a_mask_sub_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_2_2 = and(atomics_a_mask_sub_sub_1_2, atomics_a_mask_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_2 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_2_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_2_1 = or(atomics_a_mask_sub_sub_1_1, _atomics_a_mask_sub_acc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_3_2 = and(atomics_a_mask_sub_sub_1_2, atomics_a_mask_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_3 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_3_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_3_1 = or(atomics_a_mask_sub_sub_1_1, _atomics_a_mask_sub_acc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_size = bits(atomics_a_mask_sizeOH, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_bit = bits(s2_req.addr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_nbit = eq(atomics_a_mask_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_eq = and(atomics_a_mask_sub_0_2, atomics_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T = and(atomics_a_mask_size, atomics_a_mask_eq) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc = or(atomics_a_mask_sub_0_1, _atomics_a_mask_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_1 = and(atomics_a_mask_sub_0_2, atomics_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_1 = and(atomics_a_mask_size, atomics_a_mask_eq_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_1 = or(atomics_a_mask_sub_0_1, _atomics_a_mask_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_2 = and(atomics_a_mask_sub_1_2, atomics_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_2 = and(atomics_a_mask_size, atomics_a_mask_eq_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_2 = or(atomics_a_mask_sub_1_1, _atomics_a_mask_acc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_3 = and(atomics_a_mask_sub_1_2, atomics_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_3 = and(atomics_a_mask_size, atomics_a_mask_eq_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_3 = or(atomics_a_mask_sub_1_1, _atomics_a_mask_acc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_4 = and(atomics_a_mask_sub_2_2, atomics_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_4 = and(atomics_a_mask_size, atomics_a_mask_eq_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_4 = or(atomics_a_mask_sub_2_1, _atomics_a_mask_acc_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_5 = and(atomics_a_mask_sub_2_2, atomics_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_5 = and(atomics_a_mask_size, atomics_a_mask_eq_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_5 = or(atomics_a_mask_sub_2_1, _atomics_a_mask_acc_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_6 = and(atomics_a_mask_sub_3_2, atomics_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_6 = and(atomics_a_mask_size, atomics_a_mask_eq_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_6 = or(atomics_a_mask_sub_3_1, _atomics_a_mask_acc_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_7 = and(atomics_a_mask_sub_3_2, atomics_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_7 = and(atomics_a_mask_size, atomics_a_mask_eq_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_7 = or(atomics_a_mask_sub_3_1, _atomics_a_mask_acc_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_lo_lo = cat(atomics_a_mask_acc_1, atomics_a_mask_acc) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_lo_hi = cat(atomics_a_mask_acc_3, atomics_a_mask_acc_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_lo = cat(atomics_a_mask_lo_hi, atomics_a_mask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_lo = cat(atomics_a_mask_acc_5, atomics_a_mask_acc_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_hi = cat(atomics_a_mask_acc_7, atomics_a_mask_acc_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi = cat(atomics_a_mask_hi_hi, atomics_a_mask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node _atomics_a_mask_T = cat(atomics_a_mask_hi, atomics_a_mask_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] connect atomics_a.mask, _atomics_a_mask_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 542:15] connect atomics_a.data, pstore1_data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 543:15] connect atomics_a.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 544:15] node _atomics_legal_T_48 = leq(UInt<1>(0h0), s2_req.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _atomics_legal_T_49 = leq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _atomics_legal_T_50 = and(_atomics_legal_T_48, _atomics_legal_T_49) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _atomics_legal_T_51 = or(UInt<1>(0h0), _atomics_legal_T_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _atomics_legal_T_52 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_53 = cvt(_atomics_legal_T_52) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_54 = and(_atomics_legal_T_53, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_55 = asSInt(_atomics_legal_T_54) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_56 = eq(_atomics_legal_T_55, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_57 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_58 = cvt(_atomics_legal_T_57) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_59 = and(_atomics_legal_T_58, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_60 = asSInt(_atomics_legal_T_59) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_61 = eq(_atomics_legal_T_60, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_62 = xor(s2_req.addr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_63 = cvt(_atomics_legal_T_62) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_64 = and(_atomics_legal_T_63, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_65 = asSInt(_atomics_legal_T_64) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_66 = eq(_atomics_legal_T_65, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_67 = xor(s2_req.addr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_68 = cvt(_atomics_legal_T_67) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_69 = and(_atomics_legal_T_68, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_70 = asSInt(_atomics_legal_T_69) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_71 = eq(_atomics_legal_T_70, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_72 = xor(s2_req.addr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_73 = cvt(_atomics_legal_T_72) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_74 = and(_atomics_legal_T_73, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_75 = asSInt(_atomics_legal_T_74) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_76 = eq(_atomics_legal_T_75, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_77 = xor(s2_req.addr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_78 = cvt(_atomics_legal_T_77) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_79 = and(_atomics_legal_T_78, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_80 = asSInt(_atomics_legal_T_79) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_81 = eq(_atomics_legal_T_80, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_82 = or(_atomics_legal_T_56, _atomics_legal_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_83 = or(_atomics_legal_T_82, _atomics_legal_T_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_84 = or(_atomics_legal_T_83, _atomics_legal_T_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_85 = or(_atomics_legal_T_84, _atomics_legal_T_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_86 = or(_atomics_legal_T_85, _atomics_legal_T_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_87 = and(_atomics_legal_T_51, _atomics_legal_T_86) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _atomics_legal_T_88 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _atomics_legal_T_89 = xor(s2_req.addr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_90 = cvt(_atomics_legal_T_89) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_91 = and(_atomics_legal_T_90, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_92 = asSInt(_atomics_legal_T_91) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_93 = eq(_atomics_legal_T_92, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_94 = and(_atomics_legal_T_88, _atomics_legal_T_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _atomics_legal_T_95 = or(UInt<1>(0h0), _atomics_legal_T_87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node atomics_legal_1 = or(_atomics_legal_T_95, _atomics_legal_T_94) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire atomics_a_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 534:17] connect atomics_a_1.opcode, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 535:15] connect atomics_a_1.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 536:15] connect atomics_a_1.size, s2_req.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 537:15] connect atomics_a_1.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 538:15] connect atomics_a_1.address, s2_req.addr @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 539:15] invalidate atomics_a_1.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a_1.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a_1.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a_1.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a_1.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a_1.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a_1.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] node _atomics_a_mask_sizeOH_T_3 = or(s2_req.size, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node atomics_a_mask_sizeOH_shiftAmount_1 = bits(_atomics_a_mask_sizeOH_T_3, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _atomics_a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_1) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _atomics_a_mask_sizeOH_T_5 = bits(_atomics_a_mask_sizeOH_T_4, 2, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node atomics_a_mask_sizeOH_1 = or(_atomics_a_mask_sizeOH_T_5, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] node atomics_a_mask_sub_sub_sub_0_1_1 = geq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 206:21] node atomics_a_mask_sub_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_sub_sub_bit_1 = bits(s2_req.addr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_sub_sub_nbit_1 = eq(atomics_a_mask_sub_sub_bit_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_sub_sub_0_2_1 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_sub_acc_T_2 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_0_2_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_sub_0_1_1 = or(atomics_a_mask_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_acc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_sub_1_2_1 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_sub_acc_T_3 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_1_2_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_sub_1_1_1 = or(atomics_a_mask_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_acc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_sub_bit_1 = bits(s2_req.addr, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_sub_nbit_1 = eq(atomics_a_mask_sub_bit_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_sub_0_2_1 = and(atomics_a_mask_sub_sub_0_2_1, atomics_a_mask_sub_nbit_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_4 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_0_2_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_0_1_1 = or(atomics_a_mask_sub_sub_0_1_1, _atomics_a_mask_sub_acc_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_1_2_1 = and(atomics_a_mask_sub_sub_0_2_1, atomics_a_mask_sub_bit_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_5 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_1_2_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_1_1_1 = or(atomics_a_mask_sub_sub_0_1_1, _atomics_a_mask_sub_acc_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_2_2_1 = and(atomics_a_mask_sub_sub_1_2_1, atomics_a_mask_sub_nbit_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_6 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_2_2_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_2_1_1 = or(atomics_a_mask_sub_sub_1_1_1, _atomics_a_mask_sub_acc_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_3_2_1 = and(atomics_a_mask_sub_sub_1_2_1, atomics_a_mask_sub_bit_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_7 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_3_2_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_3_1_1 = or(atomics_a_mask_sub_sub_1_1_1, _atomics_a_mask_sub_acc_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_size_1 = bits(atomics_a_mask_sizeOH_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_bit_1 = bits(s2_req.addr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_nbit_1 = eq(atomics_a_mask_bit_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_eq_8 = and(atomics_a_mask_sub_0_2_1, atomics_a_mask_nbit_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_8 = and(atomics_a_mask_size_1, atomics_a_mask_eq_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_8 = or(atomics_a_mask_sub_0_1_1, _atomics_a_mask_acc_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_9 = and(atomics_a_mask_sub_0_2_1, atomics_a_mask_bit_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_9 = and(atomics_a_mask_size_1, atomics_a_mask_eq_9) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_9 = or(atomics_a_mask_sub_0_1_1, _atomics_a_mask_acc_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_10 = and(atomics_a_mask_sub_1_2_1, atomics_a_mask_nbit_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_10 = and(atomics_a_mask_size_1, atomics_a_mask_eq_10) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_10 = or(atomics_a_mask_sub_1_1_1, _atomics_a_mask_acc_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_11 = and(atomics_a_mask_sub_1_2_1, atomics_a_mask_bit_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_11 = and(atomics_a_mask_size_1, atomics_a_mask_eq_11) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_11 = or(atomics_a_mask_sub_1_1_1, _atomics_a_mask_acc_T_11) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_12 = and(atomics_a_mask_sub_2_2_1, atomics_a_mask_nbit_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_12 = and(atomics_a_mask_size_1, atomics_a_mask_eq_12) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_12 = or(atomics_a_mask_sub_2_1_1, _atomics_a_mask_acc_T_12) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_13 = and(atomics_a_mask_sub_2_2_1, atomics_a_mask_bit_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_13 = and(atomics_a_mask_size_1, atomics_a_mask_eq_13) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_13 = or(atomics_a_mask_sub_2_1_1, _atomics_a_mask_acc_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_14 = and(atomics_a_mask_sub_3_2_1, atomics_a_mask_nbit_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_14 = and(atomics_a_mask_size_1, atomics_a_mask_eq_14) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_14 = or(atomics_a_mask_sub_3_1_1, _atomics_a_mask_acc_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_15 = and(atomics_a_mask_sub_3_2_1, atomics_a_mask_bit_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_15 = and(atomics_a_mask_size_1, atomics_a_mask_eq_15) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_15 = or(atomics_a_mask_sub_3_1_1, _atomics_a_mask_acc_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_lo_lo_1 = cat(atomics_a_mask_acc_9, atomics_a_mask_acc_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_lo_hi_1 = cat(atomics_a_mask_acc_11, atomics_a_mask_acc_10) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_lo_1 = cat(atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_lo_1 = cat(atomics_a_mask_acc_13, atomics_a_mask_acc_12) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_hi_1 = cat(atomics_a_mask_acc_15, atomics_a_mask_acc_14) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_1 = cat(atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node _atomics_a_mask_T_1 = cat(atomics_a_mask_hi_1, atomics_a_mask_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] connect atomics_a_1.mask, _atomics_a_mask_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 542:15] connect atomics_a_1.data, pstore1_data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 543:15] connect atomics_a_1.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 544:15] node _atomics_legal_T_96 = leq(UInt<1>(0h0), s2_req.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _atomics_legal_T_97 = leq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _atomics_legal_T_98 = and(_atomics_legal_T_96, _atomics_legal_T_97) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _atomics_legal_T_99 = or(UInt<1>(0h0), _atomics_legal_T_98) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _atomics_legal_T_100 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_101 = cvt(_atomics_legal_T_100) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_102 = and(_atomics_legal_T_101, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_103 = asSInt(_atomics_legal_T_102) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_104 = eq(_atomics_legal_T_103, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_105 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_106 = cvt(_atomics_legal_T_105) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_107 = and(_atomics_legal_T_106, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_108 = asSInt(_atomics_legal_T_107) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_109 = eq(_atomics_legal_T_108, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_110 = xor(s2_req.addr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_111 = cvt(_atomics_legal_T_110) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_112 = and(_atomics_legal_T_111, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_113 = asSInt(_atomics_legal_T_112) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_114 = eq(_atomics_legal_T_113, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_115 = xor(s2_req.addr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_116 = cvt(_atomics_legal_T_115) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_117 = and(_atomics_legal_T_116, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_118 = asSInt(_atomics_legal_T_117) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_119 = eq(_atomics_legal_T_118, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_120 = xor(s2_req.addr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_121 = cvt(_atomics_legal_T_120) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_122 = and(_atomics_legal_T_121, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_123 = asSInt(_atomics_legal_T_122) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_124 = eq(_atomics_legal_T_123, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_125 = xor(s2_req.addr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_126 = cvt(_atomics_legal_T_125) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_127 = and(_atomics_legal_T_126, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_128 = asSInt(_atomics_legal_T_127) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_129 = eq(_atomics_legal_T_128, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_130 = or(_atomics_legal_T_104, _atomics_legal_T_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_131 = or(_atomics_legal_T_130, _atomics_legal_T_114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_132 = or(_atomics_legal_T_131, _atomics_legal_T_119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_133 = or(_atomics_legal_T_132, _atomics_legal_T_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_134 = or(_atomics_legal_T_133, _atomics_legal_T_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_135 = and(_atomics_legal_T_99, _atomics_legal_T_134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _atomics_legal_T_136 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _atomics_legal_T_137 = xor(s2_req.addr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_138 = cvt(_atomics_legal_T_137) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_139 = and(_atomics_legal_T_138, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_140 = asSInt(_atomics_legal_T_139) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_141 = eq(_atomics_legal_T_140, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_142 = and(_atomics_legal_T_136, _atomics_legal_T_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _atomics_legal_T_143 = or(UInt<1>(0h0), _atomics_legal_T_135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node atomics_legal_2 = or(_atomics_legal_T_143, _atomics_legal_T_142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire atomics_a_2 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 534:17] connect atomics_a_2.opcode, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 535:15] connect atomics_a_2.param, UInt<3>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 536:15] connect atomics_a_2.size, s2_req.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 537:15] connect atomics_a_2.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 538:15] connect atomics_a_2.address, s2_req.addr @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 539:15] invalidate atomics_a_2.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a_2.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a_2.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a_2.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a_2.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a_2.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a_2.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] node _atomics_a_mask_sizeOH_T_6 = or(s2_req.size, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node atomics_a_mask_sizeOH_shiftAmount_2 = bits(_atomics_a_mask_sizeOH_T_6, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _atomics_a_mask_sizeOH_T_7 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_2) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _atomics_a_mask_sizeOH_T_8 = bits(_atomics_a_mask_sizeOH_T_7, 2, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node atomics_a_mask_sizeOH_2 = or(_atomics_a_mask_sizeOH_T_8, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] node atomics_a_mask_sub_sub_sub_0_1_2 = geq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 206:21] node atomics_a_mask_sub_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_sub_sub_bit_2 = bits(s2_req.addr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_sub_sub_nbit_2 = eq(atomics_a_mask_sub_sub_bit_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_sub_sub_0_2_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_sub_acc_T_4 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_0_2_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_sub_0_1_2 = or(atomics_a_mask_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_acc_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_sub_1_2_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_sub_acc_T_5 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_1_2_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_sub_1_1_2 = or(atomics_a_mask_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_acc_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_sub_bit_2 = bits(s2_req.addr, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_sub_nbit_2 = eq(atomics_a_mask_sub_bit_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_sub_0_2_2 = and(atomics_a_mask_sub_sub_0_2_2, atomics_a_mask_sub_nbit_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_8 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_0_2_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_0_1_2 = or(atomics_a_mask_sub_sub_0_1_2, _atomics_a_mask_sub_acc_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_1_2_2 = and(atomics_a_mask_sub_sub_0_2_2, atomics_a_mask_sub_bit_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_9 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_1_2_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_1_1_2 = or(atomics_a_mask_sub_sub_0_1_2, _atomics_a_mask_sub_acc_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_2_2_2 = and(atomics_a_mask_sub_sub_1_2_2, atomics_a_mask_sub_nbit_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_10 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_2_2_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_2_1_2 = or(atomics_a_mask_sub_sub_1_1_2, _atomics_a_mask_sub_acc_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_3_2_2 = and(atomics_a_mask_sub_sub_1_2_2, atomics_a_mask_sub_bit_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_11 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_3_2_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_3_1_2 = or(atomics_a_mask_sub_sub_1_1_2, _atomics_a_mask_sub_acc_T_11) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_size_2 = bits(atomics_a_mask_sizeOH_2, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_bit_2 = bits(s2_req.addr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_nbit_2 = eq(atomics_a_mask_bit_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_eq_16 = and(atomics_a_mask_sub_0_2_2, atomics_a_mask_nbit_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_16 = and(atomics_a_mask_size_2, atomics_a_mask_eq_16) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_16 = or(atomics_a_mask_sub_0_1_2, _atomics_a_mask_acc_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_17 = and(atomics_a_mask_sub_0_2_2, atomics_a_mask_bit_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_17 = and(atomics_a_mask_size_2, atomics_a_mask_eq_17) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_17 = or(atomics_a_mask_sub_0_1_2, _atomics_a_mask_acc_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_18 = and(atomics_a_mask_sub_1_2_2, atomics_a_mask_nbit_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_18 = and(atomics_a_mask_size_2, atomics_a_mask_eq_18) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_18 = or(atomics_a_mask_sub_1_1_2, _atomics_a_mask_acc_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_19 = and(atomics_a_mask_sub_1_2_2, atomics_a_mask_bit_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_19 = and(atomics_a_mask_size_2, atomics_a_mask_eq_19) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_19 = or(atomics_a_mask_sub_1_1_2, _atomics_a_mask_acc_T_19) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_20 = and(atomics_a_mask_sub_2_2_2, atomics_a_mask_nbit_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_20 = and(atomics_a_mask_size_2, atomics_a_mask_eq_20) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_20 = or(atomics_a_mask_sub_2_1_2, _atomics_a_mask_acc_T_20) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_21 = and(atomics_a_mask_sub_2_2_2, atomics_a_mask_bit_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_21 = and(atomics_a_mask_size_2, atomics_a_mask_eq_21) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_21 = or(atomics_a_mask_sub_2_1_2, _atomics_a_mask_acc_T_21) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_22 = and(atomics_a_mask_sub_3_2_2, atomics_a_mask_nbit_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_22 = and(atomics_a_mask_size_2, atomics_a_mask_eq_22) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_22 = or(atomics_a_mask_sub_3_1_2, _atomics_a_mask_acc_T_22) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_23 = and(atomics_a_mask_sub_3_2_2, atomics_a_mask_bit_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_23 = and(atomics_a_mask_size_2, atomics_a_mask_eq_23) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_23 = or(atomics_a_mask_sub_3_1_2, _atomics_a_mask_acc_T_23) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_lo_lo_2 = cat(atomics_a_mask_acc_17, atomics_a_mask_acc_16) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_lo_hi_2 = cat(atomics_a_mask_acc_19, atomics_a_mask_acc_18) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_lo_2 = cat(atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_lo_2 = cat(atomics_a_mask_acc_21, atomics_a_mask_acc_20) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_hi_2 = cat(atomics_a_mask_acc_23, atomics_a_mask_acc_22) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_2 = cat(atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node _atomics_a_mask_T_2 = cat(atomics_a_mask_hi_2, atomics_a_mask_lo_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] connect atomics_a_2.mask, _atomics_a_mask_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 542:15] connect atomics_a_2.data, pstore1_data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 543:15] connect atomics_a_2.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 544:15] node _atomics_legal_T_144 = leq(UInt<1>(0h0), s2_req.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _atomics_legal_T_145 = leq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _atomics_legal_T_146 = and(_atomics_legal_T_144, _atomics_legal_T_145) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _atomics_legal_T_147 = or(UInt<1>(0h0), _atomics_legal_T_146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _atomics_legal_T_148 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_149 = cvt(_atomics_legal_T_148) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_150 = and(_atomics_legal_T_149, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_151 = asSInt(_atomics_legal_T_150) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_152 = eq(_atomics_legal_T_151, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_153 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_154 = cvt(_atomics_legal_T_153) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_155 = and(_atomics_legal_T_154, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_156 = asSInt(_atomics_legal_T_155) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_157 = eq(_atomics_legal_T_156, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_158 = xor(s2_req.addr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_159 = cvt(_atomics_legal_T_158) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_160 = and(_atomics_legal_T_159, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_161 = asSInt(_atomics_legal_T_160) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_162 = eq(_atomics_legal_T_161, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_163 = xor(s2_req.addr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_164 = cvt(_atomics_legal_T_163) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_165 = and(_atomics_legal_T_164, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_166 = asSInt(_atomics_legal_T_165) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_167 = eq(_atomics_legal_T_166, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_168 = xor(s2_req.addr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_169 = cvt(_atomics_legal_T_168) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_170 = and(_atomics_legal_T_169, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_171 = asSInt(_atomics_legal_T_170) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_172 = eq(_atomics_legal_T_171, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_173 = xor(s2_req.addr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_174 = cvt(_atomics_legal_T_173) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_175 = and(_atomics_legal_T_174, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_176 = asSInt(_atomics_legal_T_175) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_177 = eq(_atomics_legal_T_176, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_178 = or(_atomics_legal_T_152, _atomics_legal_T_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_179 = or(_atomics_legal_T_178, _atomics_legal_T_162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_180 = or(_atomics_legal_T_179, _atomics_legal_T_167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_181 = or(_atomics_legal_T_180, _atomics_legal_T_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_182 = or(_atomics_legal_T_181, _atomics_legal_T_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_183 = and(_atomics_legal_T_147, _atomics_legal_T_182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _atomics_legal_T_184 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _atomics_legal_T_185 = xor(s2_req.addr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_186 = cvt(_atomics_legal_T_185) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_187 = and(_atomics_legal_T_186, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_188 = asSInt(_atomics_legal_T_187) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_189 = eq(_atomics_legal_T_188, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_190 = and(_atomics_legal_T_184, _atomics_legal_T_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _atomics_legal_T_191 = or(UInt<1>(0h0), _atomics_legal_T_183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node atomics_legal_3 = or(_atomics_legal_T_191, _atomics_legal_T_190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire atomics_a_3 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 534:17] connect atomics_a_3.opcode, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 535:15] connect atomics_a_3.param, UInt<3>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 536:15] connect atomics_a_3.size, s2_req.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 537:15] connect atomics_a_3.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 538:15] connect atomics_a_3.address, s2_req.addr @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 539:15] invalidate atomics_a_3.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a_3.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a_3.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a_3.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a_3.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a_3.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] invalidate atomics_a_3.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 540:15] node _atomics_a_mask_sizeOH_T_9 = or(s2_req.size, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node atomics_a_mask_sizeOH_shiftAmount_3 = bits(_atomics_a_mask_sizeOH_T_9, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _atomics_a_mask_sizeOH_T_10 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_3) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _atomics_a_mask_sizeOH_T_11 = bits(_atomics_a_mask_sizeOH_T_10, 2, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node atomics_a_mask_sizeOH_3 = or(_atomics_a_mask_sizeOH_T_11, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] node atomics_a_mask_sub_sub_sub_0_1_3 = geq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 206:21] node atomics_a_mask_sub_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_sub_sub_bit_3 = bits(s2_req.addr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_sub_sub_nbit_3 = eq(atomics_a_mask_sub_sub_bit_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_sub_sub_0_2_3 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_sub_acc_T_6 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_0_2_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_sub_0_1_3 = or(atomics_a_mask_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_acc_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_sub_1_2_3 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_sub_acc_T_7 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_1_2_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_sub_1_1_3 = or(atomics_a_mask_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_acc_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_sub_bit_3 = bits(s2_req.addr, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_sub_nbit_3 = eq(atomics_a_mask_sub_bit_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_sub_0_2_3 = and(atomics_a_mask_sub_sub_0_2_3, atomics_a_mask_sub_nbit_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_12 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_0_2_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_0_1_3 = or(atomics_a_mask_sub_sub_0_1_3, _atomics_a_mask_sub_acc_T_12) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_1_2_3 = and(atomics_a_mask_sub_sub_0_2_3, atomics_a_mask_sub_bit_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_13 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_1_2_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_1_1_3 = or(atomics_a_mask_sub_sub_0_1_3, _atomics_a_mask_sub_acc_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_2_2_3 = and(atomics_a_mask_sub_sub_1_2_3, atomics_a_mask_sub_nbit_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_14 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_2_2_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_2_1_3 = or(atomics_a_mask_sub_sub_1_1_3, _atomics_a_mask_sub_acc_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_3_2_3 = and(atomics_a_mask_sub_sub_1_2_3, atomics_a_mask_sub_bit_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_15 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_3_2_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_3_1_3 = or(atomics_a_mask_sub_sub_1_1_3, _atomics_a_mask_sub_acc_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_size_3 = bits(atomics_a_mask_sizeOH_3, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_bit_3 = bits(s2_req.addr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_nbit_3 = eq(atomics_a_mask_bit_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_eq_24 = and(atomics_a_mask_sub_0_2_3, atomics_a_mask_nbit_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_24 = and(atomics_a_mask_size_3, atomics_a_mask_eq_24) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_24 = or(atomics_a_mask_sub_0_1_3, _atomics_a_mask_acc_T_24) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_25 = and(atomics_a_mask_sub_0_2_3, atomics_a_mask_bit_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_25 = and(atomics_a_mask_size_3, atomics_a_mask_eq_25) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_25 = or(atomics_a_mask_sub_0_1_3, _atomics_a_mask_acc_T_25) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_26 = and(atomics_a_mask_sub_1_2_3, atomics_a_mask_nbit_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_26 = and(atomics_a_mask_size_3, atomics_a_mask_eq_26) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_26 = or(atomics_a_mask_sub_1_1_3, _atomics_a_mask_acc_T_26) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_27 = and(atomics_a_mask_sub_1_2_3, atomics_a_mask_bit_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_27 = and(atomics_a_mask_size_3, atomics_a_mask_eq_27) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_27 = or(atomics_a_mask_sub_1_1_3, _atomics_a_mask_acc_T_27) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_28 = and(atomics_a_mask_sub_2_2_3, atomics_a_mask_nbit_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_28 = and(atomics_a_mask_size_3, atomics_a_mask_eq_28) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_28 = or(atomics_a_mask_sub_2_1_3, _atomics_a_mask_acc_T_28) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_29 = and(atomics_a_mask_sub_2_2_3, atomics_a_mask_bit_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_29 = and(atomics_a_mask_size_3, atomics_a_mask_eq_29) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_29 = or(atomics_a_mask_sub_2_1_3, _atomics_a_mask_acc_T_29) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_30 = and(atomics_a_mask_sub_3_2_3, atomics_a_mask_nbit_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_30 = and(atomics_a_mask_size_3, atomics_a_mask_eq_30) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_30 = or(atomics_a_mask_sub_3_1_3, _atomics_a_mask_acc_T_30) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_31 = and(atomics_a_mask_sub_3_2_3, atomics_a_mask_bit_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_31 = and(atomics_a_mask_size_3, atomics_a_mask_eq_31) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_31 = or(atomics_a_mask_sub_3_1_3, _atomics_a_mask_acc_T_31) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_lo_lo_3 = cat(atomics_a_mask_acc_25, atomics_a_mask_acc_24) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_lo_hi_3 = cat(atomics_a_mask_acc_27, atomics_a_mask_acc_26) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_lo_3 = cat(atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_lo_3 = cat(atomics_a_mask_acc_29, atomics_a_mask_acc_28) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_hi_3 = cat(atomics_a_mask_acc_31, atomics_a_mask_acc_30) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_3 = cat(atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node _atomics_a_mask_T_3 = cat(atomics_a_mask_hi_3, atomics_a_mask_lo_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] connect atomics_a_3.mask, _atomics_a_mask_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 542:15] connect atomics_a_3.data, pstore1_data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 543:15] connect atomics_a_3.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 544:15] node _atomics_legal_T_192 = leq(UInt<1>(0h0), s2_req.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _atomics_legal_T_193 = leq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _atomics_legal_T_194 = and(_atomics_legal_T_192, _atomics_legal_T_193) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _atomics_legal_T_195 = or(UInt<1>(0h0), _atomics_legal_T_194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _atomics_legal_T_196 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_197 = cvt(_atomics_legal_T_196) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_198 = and(_atomics_legal_T_197, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_199 = asSInt(_atomics_legal_T_198) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_200 = eq(_atomics_legal_T_199, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_201 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_202 = cvt(_atomics_legal_T_201) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_203 = and(_atomics_legal_T_202, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_204 = asSInt(_atomics_legal_T_203) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_205 = eq(_atomics_legal_T_204, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_206 = xor(s2_req.addr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_207 = cvt(_atomics_legal_T_206) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_208 = and(_atomics_legal_T_207, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_209 = asSInt(_atomics_legal_T_208) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_210 = eq(_atomics_legal_T_209, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_211 = xor(s2_req.addr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_212 = cvt(_atomics_legal_T_211) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_213 = and(_atomics_legal_T_212, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_214 = asSInt(_atomics_legal_T_213) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_215 = eq(_atomics_legal_T_214, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_216 = xor(s2_req.addr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_217 = cvt(_atomics_legal_T_216) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_218 = and(_atomics_legal_T_217, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_219 = asSInt(_atomics_legal_T_218) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_220 = eq(_atomics_legal_T_219, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_221 = xor(s2_req.addr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_222 = cvt(_atomics_legal_T_221) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_223 = and(_atomics_legal_T_222, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_224 = asSInt(_atomics_legal_T_223) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_225 = eq(_atomics_legal_T_224, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_226 = or(_atomics_legal_T_200, _atomics_legal_T_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_227 = or(_atomics_legal_T_226, _atomics_legal_T_210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_228 = or(_atomics_legal_T_227, _atomics_legal_T_215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_229 = or(_atomics_legal_T_228, _atomics_legal_T_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_230 = or(_atomics_legal_T_229, _atomics_legal_T_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_231 = and(_atomics_legal_T_195, _atomics_legal_T_230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _atomics_legal_T_232 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _atomics_legal_T_233 = xor(s2_req.addr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_234 = cvt(_atomics_legal_T_233) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_235 = and(_atomics_legal_T_234, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_236 = asSInt(_atomics_legal_T_235) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_237 = eq(_atomics_legal_T_236, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_238 = and(_atomics_legal_T_232, _atomics_legal_T_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _atomics_legal_T_239 = or(UInt<1>(0h0), _atomics_legal_T_231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node atomics_legal_4 = or(_atomics_legal_T_239, _atomics_legal_T_238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire atomics_a_4 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 517:17] connect atomics_a_4.opcode, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 518:15] connect atomics_a_4.param, UInt<3>(0h4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 519:15] connect atomics_a_4.size, s2_req.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 520:15] connect atomics_a_4.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 521:15] connect atomics_a_4.address, s2_req.addr @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 522:15] invalidate atomics_a_4.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_4.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_4.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_4.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_4.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_4.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_4.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] node _atomics_a_mask_sizeOH_T_12 = or(s2_req.size, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node atomics_a_mask_sizeOH_shiftAmount_4 = bits(_atomics_a_mask_sizeOH_T_12, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _atomics_a_mask_sizeOH_T_13 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_4) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _atomics_a_mask_sizeOH_T_14 = bits(_atomics_a_mask_sizeOH_T_13, 2, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node atomics_a_mask_sizeOH_4 = or(_atomics_a_mask_sizeOH_T_14, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] node atomics_a_mask_sub_sub_sub_0_1_4 = geq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 206:21] node atomics_a_mask_sub_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_sub_sub_bit_4 = bits(s2_req.addr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_sub_sub_nbit_4 = eq(atomics_a_mask_sub_sub_bit_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_sub_sub_0_2_4 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_sub_acc_T_8 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_0_2_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_sub_0_1_4 = or(atomics_a_mask_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_acc_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_sub_1_2_4 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_sub_acc_T_9 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_1_2_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_sub_1_1_4 = or(atomics_a_mask_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_acc_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_sub_bit_4 = bits(s2_req.addr, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_sub_nbit_4 = eq(atomics_a_mask_sub_bit_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_sub_0_2_4 = and(atomics_a_mask_sub_sub_0_2_4, atomics_a_mask_sub_nbit_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_16 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_0_2_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_0_1_4 = or(atomics_a_mask_sub_sub_0_1_4, _atomics_a_mask_sub_acc_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_1_2_4 = and(atomics_a_mask_sub_sub_0_2_4, atomics_a_mask_sub_bit_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_17 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_1_2_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_1_1_4 = or(atomics_a_mask_sub_sub_0_1_4, _atomics_a_mask_sub_acc_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_2_2_4 = and(atomics_a_mask_sub_sub_1_2_4, atomics_a_mask_sub_nbit_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_18 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_2_2_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_2_1_4 = or(atomics_a_mask_sub_sub_1_1_4, _atomics_a_mask_sub_acc_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_3_2_4 = and(atomics_a_mask_sub_sub_1_2_4, atomics_a_mask_sub_bit_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_19 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_3_2_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_3_1_4 = or(atomics_a_mask_sub_sub_1_1_4, _atomics_a_mask_sub_acc_T_19) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_size_4 = bits(atomics_a_mask_sizeOH_4, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_bit_4 = bits(s2_req.addr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_nbit_4 = eq(atomics_a_mask_bit_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_eq_32 = and(atomics_a_mask_sub_0_2_4, atomics_a_mask_nbit_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_32 = and(atomics_a_mask_size_4, atomics_a_mask_eq_32) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_32 = or(atomics_a_mask_sub_0_1_4, _atomics_a_mask_acc_T_32) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_33 = and(atomics_a_mask_sub_0_2_4, atomics_a_mask_bit_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_33 = and(atomics_a_mask_size_4, atomics_a_mask_eq_33) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_33 = or(atomics_a_mask_sub_0_1_4, _atomics_a_mask_acc_T_33) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_34 = and(atomics_a_mask_sub_1_2_4, atomics_a_mask_nbit_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_34 = and(atomics_a_mask_size_4, atomics_a_mask_eq_34) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_34 = or(atomics_a_mask_sub_1_1_4, _atomics_a_mask_acc_T_34) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_35 = and(atomics_a_mask_sub_1_2_4, atomics_a_mask_bit_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_35 = and(atomics_a_mask_size_4, atomics_a_mask_eq_35) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_35 = or(atomics_a_mask_sub_1_1_4, _atomics_a_mask_acc_T_35) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_36 = and(atomics_a_mask_sub_2_2_4, atomics_a_mask_nbit_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_36 = and(atomics_a_mask_size_4, atomics_a_mask_eq_36) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_36 = or(atomics_a_mask_sub_2_1_4, _atomics_a_mask_acc_T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_37 = and(atomics_a_mask_sub_2_2_4, atomics_a_mask_bit_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_37 = and(atomics_a_mask_size_4, atomics_a_mask_eq_37) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_37 = or(atomics_a_mask_sub_2_1_4, _atomics_a_mask_acc_T_37) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_38 = and(atomics_a_mask_sub_3_2_4, atomics_a_mask_nbit_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_38 = and(atomics_a_mask_size_4, atomics_a_mask_eq_38) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_38 = or(atomics_a_mask_sub_3_1_4, _atomics_a_mask_acc_T_38) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_39 = and(atomics_a_mask_sub_3_2_4, atomics_a_mask_bit_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_39 = and(atomics_a_mask_size_4, atomics_a_mask_eq_39) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_39 = or(atomics_a_mask_sub_3_1_4, _atomics_a_mask_acc_T_39) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_lo_lo_4 = cat(atomics_a_mask_acc_33, atomics_a_mask_acc_32) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_lo_hi_4 = cat(atomics_a_mask_acc_35, atomics_a_mask_acc_34) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_lo_4 = cat(atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_lo_4 = cat(atomics_a_mask_acc_37, atomics_a_mask_acc_36) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_hi_4 = cat(atomics_a_mask_acc_39, atomics_a_mask_acc_38) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_4 = cat(atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node _atomics_a_mask_T_4 = cat(atomics_a_mask_hi_4, atomics_a_mask_lo_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] connect atomics_a_4.mask, _atomics_a_mask_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 525:15] connect atomics_a_4.data, pstore1_data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 526:15] connect atomics_a_4.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 527:15] node _atomics_legal_T_240 = leq(UInt<1>(0h0), s2_req.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _atomics_legal_T_241 = leq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _atomics_legal_T_242 = and(_atomics_legal_T_240, _atomics_legal_T_241) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _atomics_legal_T_243 = or(UInt<1>(0h0), _atomics_legal_T_242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _atomics_legal_T_244 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_245 = cvt(_atomics_legal_T_244) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_246 = and(_atomics_legal_T_245, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_247 = asSInt(_atomics_legal_T_246) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_248 = eq(_atomics_legal_T_247, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_249 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_250 = cvt(_atomics_legal_T_249) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_251 = and(_atomics_legal_T_250, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_252 = asSInt(_atomics_legal_T_251) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_253 = eq(_atomics_legal_T_252, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_254 = xor(s2_req.addr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_255 = cvt(_atomics_legal_T_254) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_256 = and(_atomics_legal_T_255, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_257 = asSInt(_atomics_legal_T_256) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_258 = eq(_atomics_legal_T_257, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_259 = xor(s2_req.addr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_260 = cvt(_atomics_legal_T_259) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_261 = and(_atomics_legal_T_260, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_262 = asSInt(_atomics_legal_T_261) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_263 = eq(_atomics_legal_T_262, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_264 = xor(s2_req.addr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_265 = cvt(_atomics_legal_T_264) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_266 = and(_atomics_legal_T_265, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_267 = asSInt(_atomics_legal_T_266) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_268 = eq(_atomics_legal_T_267, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_269 = xor(s2_req.addr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_270 = cvt(_atomics_legal_T_269) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_271 = and(_atomics_legal_T_270, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_272 = asSInt(_atomics_legal_T_271) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_273 = eq(_atomics_legal_T_272, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_274 = or(_atomics_legal_T_248, _atomics_legal_T_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_275 = or(_atomics_legal_T_274, _atomics_legal_T_258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_276 = or(_atomics_legal_T_275, _atomics_legal_T_263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_277 = or(_atomics_legal_T_276, _atomics_legal_T_268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_278 = or(_atomics_legal_T_277, _atomics_legal_T_273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_279 = and(_atomics_legal_T_243, _atomics_legal_T_278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _atomics_legal_T_280 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _atomics_legal_T_281 = xor(s2_req.addr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_282 = cvt(_atomics_legal_T_281) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_283 = and(_atomics_legal_T_282, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_284 = asSInt(_atomics_legal_T_283) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_285 = eq(_atomics_legal_T_284, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_286 = and(_atomics_legal_T_280, _atomics_legal_T_285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _atomics_legal_T_287 = or(UInt<1>(0h0), _atomics_legal_T_279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node atomics_legal_5 = or(_atomics_legal_T_287, _atomics_legal_T_286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire atomics_a_5 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 517:17] connect atomics_a_5.opcode, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 518:15] connect atomics_a_5.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 519:15] connect atomics_a_5.size, s2_req.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 520:15] connect atomics_a_5.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 521:15] connect atomics_a_5.address, s2_req.addr @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 522:15] invalidate atomics_a_5.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_5.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_5.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_5.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_5.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_5.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_5.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] node _atomics_a_mask_sizeOH_T_15 = or(s2_req.size, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node atomics_a_mask_sizeOH_shiftAmount_5 = bits(_atomics_a_mask_sizeOH_T_15, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _atomics_a_mask_sizeOH_T_16 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_5) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _atomics_a_mask_sizeOH_T_17 = bits(_atomics_a_mask_sizeOH_T_16, 2, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node atomics_a_mask_sizeOH_5 = or(_atomics_a_mask_sizeOH_T_17, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] node atomics_a_mask_sub_sub_sub_0_1_5 = geq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 206:21] node atomics_a_mask_sub_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_sub_sub_bit_5 = bits(s2_req.addr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_sub_sub_nbit_5 = eq(atomics_a_mask_sub_sub_bit_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_sub_sub_0_2_5 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_sub_acc_T_10 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_0_2_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_sub_0_1_5 = or(atomics_a_mask_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_acc_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_sub_1_2_5 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_sub_acc_T_11 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_1_2_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_sub_1_1_5 = or(atomics_a_mask_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_acc_T_11) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_sub_bit_5 = bits(s2_req.addr, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_sub_nbit_5 = eq(atomics_a_mask_sub_bit_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_sub_0_2_5 = and(atomics_a_mask_sub_sub_0_2_5, atomics_a_mask_sub_nbit_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_20 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_0_2_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_0_1_5 = or(atomics_a_mask_sub_sub_0_1_5, _atomics_a_mask_sub_acc_T_20) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_1_2_5 = and(atomics_a_mask_sub_sub_0_2_5, atomics_a_mask_sub_bit_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_21 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_1_2_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_1_1_5 = or(atomics_a_mask_sub_sub_0_1_5, _atomics_a_mask_sub_acc_T_21) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_2_2_5 = and(atomics_a_mask_sub_sub_1_2_5, atomics_a_mask_sub_nbit_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_22 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_2_2_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_2_1_5 = or(atomics_a_mask_sub_sub_1_1_5, _atomics_a_mask_sub_acc_T_22) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_3_2_5 = and(atomics_a_mask_sub_sub_1_2_5, atomics_a_mask_sub_bit_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_23 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_3_2_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_3_1_5 = or(atomics_a_mask_sub_sub_1_1_5, _atomics_a_mask_sub_acc_T_23) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_size_5 = bits(atomics_a_mask_sizeOH_5, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_bit_5 = bits(s2_req.addr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_nbit_5 = eq(atomics_a_mask_bit_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_eq_40 = and(atomics_a_mask_sub_0_2_5, atomics_a_mask_nbit_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_40 = and(atomics_a_mask_size_5, atomics_a_mask_eq_40) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_40 = or(atomics_a_mask_sub_0_1_5, _atomics_a_mask_acc_T_40) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_41 = and(atomics_a_mask_sub_0_2_5, atomics_a_mask_bit_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_41 = and(atomics_a_mask_size_5, atomics_a_mask_eq_41) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_41 = or(atomics_a_mask_sub_0_1_5, _atomics_a_mask_acc_T_41) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_42 = and(atomics_a_mask_sub_1_2_5, atomics_a_mask_nbit_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_42 = and(atomics_a_mask_size_5, atomics_a_mask_eq_42) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_42 = or(atomics_a_mask_sub_1_1_5, _atomics_a_mask_acc_T_42) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_43 = and(atomics_a_mask_sub_1_2_5, atomics_a_mask_bit_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_43 = and(atomics_a_mask_size_5, atomics_a_mask_eq_43) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_43 = or(atomics_a_mask_sub_1_1_5, _atomics_a_mask_acc_T_43) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_44 = and(atomics_a_mask_sub_2_2_5, atomics_a_mask_nbit_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_44 = and(atomics_a_mask_size_5, atomics_a_mask_eq_44) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_44 = or(atomics_a_mask_sub_2_1_5, _atomics_a_mask_acc_T_44) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_45 = and(atomics_a_mask_sub_2_2_5, atomics_a_mask_bit_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_45 = and(atomics_a_mask_size_5, atomics_a_mask_eq_45) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_45 = or(atomics_a_mask_sub_2_1_5, _atomics_a_mask_acc_T_45) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_46 = and(atomics_a_mask_sub_3_2_5, atomics_a_mask_nbit_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_46 = and(atomics_a_mask_size_5, atomics_a_mask_eq_46) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_46 = or(atomics_a_mask_sub_3_1_5, _atomics_a_mask_acc_T_46) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_47 = and(atomics_a_mask_sub_3_2_5, atomics_a_mask_bit_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_47 = and(atomics_a_mask_size_5, atomics_a_mask_eq_47) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_47 = or(atomics_a_mask_sub_3_1_5, _atomics_a_mask_acc_T_47) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_lo_lo_5 = cat(atomics_a_mask_acc_41, atomics_a_mask_acc_40) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_lo_hi_5 = cat(atomics_a_mask_acc_43, atomics_a_mask_acc_42) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_lo_5 = cat(atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_lo_5 = cat(atomics_a_mask_acc_45, atomics_a_mask_acc_44) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_hi_5 = cat(atomics_a_mask_acc_47, atomics_a_mask_acc_46) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_5 = cat(atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node _atomics_a_mask_T_5 = cat(atomics_a_mask_hi_5, atomics_a_mask_lo_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] connect atomics_a_5.mask, _atomics_a_mask_T_5 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 525:15] connect atomics_a_5.data, pstore1_data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 526:15] connect atomics_a_5.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 527:15] node _atomics_legal_T_288 = leq(UInt<1>(0h0), s2_req.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _atomics_legal_T_289 = leq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _atomics_legal_T_290 = and(_atomics_legal_T_288, _atomics_legal_T_289) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _atomics_legal_T_291 = or(UInt<1>(0h0), _atomics_legal_T_290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _atomics_legal_T_292 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_293 = cvt(_atomics_legal_T_292) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_294 = and(_atomics_legal_T_293, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_295 = asSInt(_atomics_legal_T_294) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_296 = eq(_atomics_legal_T_295, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_297 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_298 = cvt(_atomics_legal_T_297) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_299 = and(_atomics_legal_T_298, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_300 = asSInt(_atomics_legal_T_299) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_301 = eq(_atomics_legal_T_300, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_302 = xor(s2_req.addr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_303 = cvt(_atomics_legal_T_302) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_304 = and(_atomics_legal_T_303, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_305 = asSInt(_atomics_legal_T_304) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_306 = eq(_atomics_legal_T_305, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_307 = xor(s2_req.addr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_308 = cvt(_atomics_legal_T_307) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_309 = and(_atomics_legal_T_308, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_310 = asSInt(_atomics_legal_T_309) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_311 = eq(_atomics_legal_T_310, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_312 = xor(s2_req.addr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_313 = cvt(_atomics_legal_T_312) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_314 = and(_atomics_legal_T_313, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_315 = asSInt(_atomics_legal_T_314) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_316 = eq(_atomics_legal_T_315, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_317 = xor(s2_req.addr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_318 = cvt(_atomics_legal_T_317) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_319 = and(_atomics_legal_T_318, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_320 = asSInt(_atomics_legal_T_319) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_321 = eq(_atomics_legal_T_320, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_322 = or(_atomics_legal_T_296, _atomics_legal_T_301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_323 = or(_atomics_legal_T_322, _atomics_legal_T_306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_324 = or(_atomics_legal_T_323, _atomics_legal_T_311) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_325 = or(_atomics_legal_T_324, _atomics_legal_T_316) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_326 = or(_atomics_legal_T_325, _atomics_legal_T_321) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_327 = and(_atomics_legal_T_291, _atomics_legal_T_326) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _atomics_legal_T_328 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _atomics_legal_T_329 = xor(s2_req.addr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_330 = cvt(_atomics_legal_T_329) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_331 = and(_atomics_legal_T_330, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_332 = asSInt(_atomics_legal_T_331) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_333 = eq(_atomics_legal_T_332, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_334 = and(_atomics_legal_T_328, _atomics_legal_T_333) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _atomics_legal_T_335 = or(UInt<1>(0h0), _atomics_legal_T_327) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node atomics_legal_6 = or(_atomics_legal_T_335, _atomics_legal_T_334) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire atomics_a_6 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 517:17] connect atomics_a_6.opcode, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 518:15] connect atomics_a_6.param, UInt<3>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 519:15] connect atomics_a_6.size, s2_req.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 520:15] connect atomics_a_6.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 521:15] connect atomics_a_6.address, s2_req.addr @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 522:15] invalidate atomics_a_6.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_6.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_6.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_6.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_6.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_6.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_6.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] node _atomics_a_mask_sizeOH_T_18 = or(s2_req.size, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node atomics_a_mask_sizeOH_shiftAmount_6 = bits(_atomics_a_mask_sizeOH_T_18, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _atomics_a_mask_sizeOH_T_19 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_6) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _atomics_a_mask_sizeOH_T_20 = bits(_atomics_a_mask_sizeOH_T_19, 2, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node atomics_a_mask_sizeOH_6 = or(_atomics_a_mask_sizeOH_T_20, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] node atomics_a_mask_sub_sub_sub_0_1_6 = geq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 206:21] node atomics_a_mask_sub_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_sub_sub_bit_6 = bits(s2_req.addr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_sub_sub_nbit_6 = eq(atomics_a_mask_sub_sub_bit_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_sub_sub_0_2_6 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_sub_acc_T_12 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_0_2_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_sub_0_1_6 = or(atomics_a_mask_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_acc_T_12) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_sub_1_2_6 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_sub_acc_T_13 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_1_2_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_sub_1_1_6 = or(atomics_a_mask_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_acc_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_sub_bit_6 = bits(s2_req.addr, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_sub_nbit_6 = eq(atomics_a_mask_sub_bit_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_sub_0_2_6 = and(atomics_a_mask_sub_sub_0_2_6, atomics_a_mask_sub_nbit_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_24 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_0_2_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_0_1_6 = or(atomics_a_mask_sub_sub_0_1_6, _atomics_a_mask_sub_acc_T_24) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_1_2_6 = and(atomics_a_mask_sub_sub_0_2_6, atomics_a_mask_sub_bit_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_25 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_1_2_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_1_1_6 = or(atomics_a_mask_sub_sub_0_1_6, _atomics_a_mask_sub_acc_T_25) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_2_2_6 = and(atomics_a_mask_sub_sub_1_2_6, atomics_a_mask_sub_nbit_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_26 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_2_2_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_2_1_6 = or(atomics_a_mask_sub_sub_1_1_6, _atomics_a_mask_sub_acc_T_26) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_3_2_6 = and(atomics_a_mask_sub_sub_1_2_6, atomics_a_mask_sub_bit_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_27 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_3_2_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_3_1_6 = or(atomics_a_mask_sub_sub_1_1_6, _atomics_a_mask_sub_acc_T_27) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_size_6 = bits(atomics_a_mask_sizeOH_6, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_bit_6 = bits(s2_req.addr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_nbit_6 = eq(atomics_a_mask_bit_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_eq_48 = and(atomics_a_mask_sub_0_2_6, atomics_a_mask_nbit_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_48 = and(atomics_a_mask_size_6, atomics_a_mask_eq_48) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_48 = or(atomics_a_mask_sub_0_1_6, _atomics_a_mask_acc_T_48) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_49 = and(atomics_a_mask_sub_0_2_6, atomics_a_mask_bit_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_49 = and(atomics_a_mask_size_6, atomics_a_mask_eq_49) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_49 = or(atomics_a_mask_sub_0_1_6, _atomics_a_mask_acc_T_49) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_50 = and(atomics_a_mask_sub_1_2_6, atomics_a_mask_nbit_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_50 = and(atomics_a_mask_size_6, atomics_a_mask_eq_50) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_50 = or(atomics_a_mask_sub_1_1_6, _atomics_a_mask_acc_T_50) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_51 = and(atomics_a_mask_sub_1_2_6, atomics_a_mask_bit_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_51 = and(atomics_a_mask_size_6, atomics_a_mask_eq_51) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_51 = or(atomics_a_mask_sub_1_1_6, _atomics_a_mask_acc_T_51) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_52 = and(atomics_a_mask_sub_2_2_6, atomics_a_mask_nbit_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_52 = and(atomics_a_mask_size_6, atomics_a_mask_eq_52) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_52 = or(atomics_a_mask_sub_2_1_6, _atomics_a_mask_acc_T_52) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_53 = and(atomics_a_mask_sub_2_2_6, atomics_a_mask_bit_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_53 = and(atomics_a_mask_size_6, atomics_a_mask_eq_53) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_53 = or(atomics_a_mask_sub_2_1_6, _atomics_a_mask_acc_T_53) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_54 = and(atomics_a_mask_sub_3_2_6, atomics_a_mask_nbit_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_54 = and(atomics_a_mask_size_6, atomics_a_mask_eq_54) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_54 = or(atomics_a_mask_sub_3_1_6, _atomics_a_mask_acc_T_54) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_55 = and(atomics_a_mask_sub_3_2_6, atomics_a_mask_bit_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_55 = and(atomics_a_mask_size_6, atomics_a_mask_eq_55) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_55 = or(atomics_a_mask_sub_3_1_6, _atomics_a_mask_acc_T_55) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_lo_lo_6 = cat(atomics_a_mask_acc_49, atomics_a_mask_acc_48) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_lo_hi_6 = cat(atomics_a_mask_acc_51, atomics_a_mask_acc_50) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_lo_6 = cat(atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_lo_6 = cat(atomics_a_mask_acc_53, atomics_a_mask_acc_52) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_hi_6 = cat(atomics_a_mask_acc_55, atomics_a_mask_acc_54) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_6 = cat(atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node _atomics_a_mask_T_6 = cat(atomics_a_mask_hi_6, atomics_a_mask_lo_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] connect atomics_a_6.mask, _atomics_a_mask_T_6 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 525:15] connect atomics_a_6.data, pstore1_data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 526:15] connect atomics_a_6.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 527:15] node _atomics_legal_T_336 = leq(UInt<1>(0h0), s2_req.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _atomics_legal_T_337 = leq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _atomics_legal_T_338 = and(_atomics_legal_T_336, _atomics_legal_T_337) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _atomics_legal_T_339 = or(UInt<1>(0h0), _atomics_legal_T_338) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _atomics_legal_T_340 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_341 = cvt(_atomics_legal_T_340) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_342 = and(_atomics_legal_T_341, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_343 = asSInt(_atomics_legal_T_342) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_344 = eq(_atomics_legal_T_343, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_345 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_346 = cvt(_atomics_legal_T_345) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_347 = and(_atomics_legal_T_346, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_348 = asSInt(_atomics_legal_T_347) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_349 = eq(_atomics_legal_T_348, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_350 = xor(s2_req.addr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_351 = cvt(_atomics_legal_T_350) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_352 = and(_atomics_legal_T_351, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_353 = asSInt(_atomics_legal_T_352) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_354 = eq(_atomics_legal_T_353, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_355 = xor(s2_req.addr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_356 = cvt(_atomics_legal_T_355) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_357 = and(_atomics_legal_T_356, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_358 = asSInt(_atomics_legal_T_357) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_359 = eq(_atomics_legal_T_358, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_360 = xor(s2_req.addr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_361 = cvt(_atomics_legal_T_360) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_362 = and(_atomics_legal_T_361, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_363 = asSInt(_atomics_legal_T_362) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_364 = eq(_atomics_legal_T_363, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_365 = xor(s2_req.addr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_366 = cvt(_atomics_legal_T_365) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_367 = and(_atomics_legal_T_366, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_368 = asSInt(_atomics_legal_T_367) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_369 = eq(_atomics_legal_T_368, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_370 = or(_atomics_legal_T_344, _atomics_legal_T_349) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_371 = or(_atomics_legal_T_370, _atomics_legal_T_354) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_372 = or(_atomics_legal_T_371, _atomics_legal_T_359) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_373 = or(_atomics_legal_T_372, _atomics_legal_T_364) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_374 = or(_atomics_legal_T_373, _atomics_legal_T_369) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_375 = and(_atomics_legal_T_339, _atomics_legal_T_374) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _atomics_legal_T_376 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _atomics_legal_T_377 = xor(s2_req.addr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_378 = cvt(_atomics_legal_T_377) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_379 = and(_atomics_legal_T_378, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_380 = asSInt(_atomics_legal_T_379) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_381 = eq(_atomics_legal_T_380, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_382 = and(_atomics_legal_T_376, _atomics_legal_T_381) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _atomics_legal_T_383 = or(UInt<1>(0h0), _atomics_legal_T_375) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node atomics_legal_7 = or(_atomics_legal_T_383, _atomics_legal_T_382) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire atomics_a_7 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 517:17] connect atomics_a_7.opcode, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 518:15] connect atomics_a_7.param, UInt<3>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 519:15] connect atomics_a_7.size, s2_req.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 520:15] connect atomics_a_7.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 521:15] connect atomics_a_7.address, s2_req.addr @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 522:15] invalidate atomics_a_7.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_7.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_7.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_7.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_7.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_7.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_7.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] node _atomics_a_mask_sizeOH_T_21 = or(s2_req.size, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node atomics_a_mask_sizeOH_shiftAmount_7 = bits(_atomics_a_mask_sizeOH_T_21, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _atomics_a_mask_sizeOH_T_22 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_7) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _atomics_a_mask_sizeOH_T_23 = bits(_atomics_a_mask_sizeOH_T_22, 2, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node atomics_a_mask_sizeOH_7 = or(_atomics_a_mask_sizeOH_T_23, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] node atomics_a_mask_sub_sub_sub_0_1_7 = geq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 206:21] node atomics_a_mask_sub_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_sub_sub_bit_7 = bits(s2_req.addr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_sub_sub_nbit_7 = eq(atomics_a_mask_sub_sub_bit_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_sub_sub_0_2_7 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_sub_acc_T_14 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_0_2_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_sub_0_1_7 = or(atomics_a_mask_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_acc_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_sub_1_2_7 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_sub_acc_T_15 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_1_2_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_sub_1_1_7 = or(atomics_a_mask_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_acc_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_sub_bit_7 = bits(s2_req.addr, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_sub_nbit_7 = eq(atomics_a_mask_sub_bit_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_sub_0_2_7 = and(atomics_a_mask_sub_sub_0_2_7, atomics_a_mask_sub_nbit_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_28 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_0_2_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_0_1_7 = or(atomics_a_mask_sub_sub_0_1_7, _atomics_a_mask_sub_acc_T_28) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_1_2_7 = and(atomics_a_mask_sub_sub_0_2_7, atomics_a_mask_sub_bit_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_29 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_1_2_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_1_1_7 = or(atomics_a_mask_sub_sub_0_1_7, _atomics_a_mask_sub_acc_T_29) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_2_2_7 = and(atomics_a_mask_sub_sub_1_2_7, atomics_a_mask_sub_nbit_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_30 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_2_2_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_2_1_7 = or(atomics_a_mask_sub_sub_1_1_7, _atomics_a_mask_sub_acc_T_30) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_3_2_7 = and(atomics_a_mask_sub_sub_1_2_7, atomics_a_mask_sub_bit_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_31 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_3_2_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_3_1_7 = or(atomics_a_mask_sub_sub_1_1_7, _atomics_a_mask_sub_acc_T_31) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_size_7 = bits(atomics_a_mask_sizeOH_7, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_bit_7 = bits(s2_req.addr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_nbit_7 = eq(atomics_a_mask_bit_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_eq_56 = and(atomics_a_mask_sub_0_2_7, atomics_a_mask_nbit_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_56 = and(atomics_a_mask_size_7, atomics_a_mask_eq_56) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_56 = or(atomics_a_mask_sub_0_1_7, _atomics_a_mask_acc_T_56) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_57 = and(atomics_a_mask_sub_0_2_7, atomics_a_mask_bit_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_57 = and(atomics_a_mask_size_7, atomics_a_mask_eq_57) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_57 = or(atomics_a_mask_sub_0_1_7, _atomics_a_mask_acc_T_57) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_58 = and(atomics_a_mask_sub_1_2_7, atomics_a_mask_nbit_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_58 = and(atomics_a_mask_size_7, atomics_a_mask_eq_58) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_58 = or(atomics_a_mask_sub_1_1_7, _atomics_a_mask_acc_T_58) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_59 = and(atomics_a_mask_sub_1_2_7, atomics_a_mask_bit_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_59 = and(atomics_a_mask_size_7, atomics_a_mask_eq_59) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_59 = or(atomics_a_mask_sub_1_1_7, _atomics_a_mask_acc_T_59) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_60 = and(atomics_a_mask_sub_2_2_7, atomics_a_mask_nbit_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_60 = and(atomics_a_mask_size_7, atomics_a_mask_eq_60) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_60 = or(atomics_a_mask_sub_2_1_7, _atomics_a_mask_acc_T_60) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_61 = and(atomics_a_mask_sub_2_2_7, atomics_a_mask_bit_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_61 = and(atomics_a_mask_size_7, atomics_a_mask_eq_61) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_61 = or(atomics_a_mask_sub_2_1_7, _atomics_a_mask_acc_T_61) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_62 = and(atomics_a_mask_sub_3_2_7, atomics_a_mask_nbit_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_62 = and(atomics_a_mask_size_7, atomics_a_mask_eq_62) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_62 = or(atomics_a_mask_sub_3_1_7, _atomics_a_mask_acc_T_62) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_63 = and(atomics_a_mask_sub_3_2_7, atomics_a_mask_bit_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_63 = and(atomics_a_mask_size_7, atomics_a_mask_eq_63) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_63 = or(atomics_a_mask_sub_3_1_7, _atomics_a_mask_acc_T_63) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_lo_lo_7 = cat(atomics_a_mask_acc_57, atomics_a_mask_acc_56) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_lo_hi_7 = cat(atomics_a_mask_acc_59, atomics_a_mask_acc_58) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_lo_7 = cat(atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_lo_7 = cat(atomics_a_mask_acc_61, atomics_a_mask_acc_60) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_hi_7 = cat(atomics_a_mask_acc_63, atomics_a_mask_acc_62) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_7 = cat(atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node _atomics_a_mask_T_7 = cat(atomics_a_mask_hi_7, atomics_a_mask_lo_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] connect atomics_a_7.mask, _atomics_a_mask_T_7 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 525:15] connect atomics_a_7.data, pstore1_data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 526:15] connect atomics_a_7.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 527:15] node _atomics_legal_T_384 = leq(UInt<1>(0h0), s2_req.size) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _atomics_legal_T_385 = leq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _atomics_legal_T_386 = and(_atomics_legal_T_384, _atomics_legal_T_385) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _atomics_legal_T_387 = or(UInt<1>(0h0), _atomics_legal_T_386) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _atomics_legal_T_388 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_389 = cvt(_atomics_legal_T_388) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_390 = and(_atomics_legal_T_389, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_391 = asSInt(_atomics_legal_T_390) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_392 = eq(_atomics_legal_T_391, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_393 = xor(s2_req.addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_394 = cvt(_atomics_legal_T_393) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_395 = and(_atomics_legal_T_394, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_396 = asSInt(_atomics_legal_T_395) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_397 = eq(_atomics_legal_T_396, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_398 = xor(s2_req.addr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_399 = cvt(_atomics_legal_T_398) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_400 = and(_atomics_legal_T_399, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_401 = asSInt(_atomics_legal_T_400) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_402 = eq(_atomics_legal_T_401, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_403 = xor(s2_req.addr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_404 = cvt(_atomics_legal_T_403) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_405 = and(_atomics_legal_T_404, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_406 = asSInt(_atomics_legal_T_405) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_407 = eq(_atomics_legal_T_406, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_408 = xor(s2_req.addr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_409 = cvt(_atomics_legal_T_408) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_410 = and(_atomics_legal_T_409, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_411 = asSInt(_atomics_legal_T_410) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_412 = eq(_atomics_legal_T_411, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_413 = xor(s2_req.addr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_414 = cvt(_atomics_legal_T_413) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_415 = and(_atomics_legal_T_414, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_416 = asSInt(_atomics_legal_T_415) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_417 = eq(_atomics_legal_T_416, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_418 = or(_atomics_legal_T_392, _atomics_legal_T_397) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_419 = or(_atomics_legal_T_418, _atomics_legal_T_402) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_420 = or(_atomics_legal_T_419, _atomics_legal_T_407) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_421 = or(_atomics_legal_T_420, _atomics_legal_T_412) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_422 = or(_atomics_legal_T_421, _atomics_legal_T_417) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _atomics_legal_T_423 = and(_atomics_legal_T_387, _atomics_legal_T_422) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _atomics_legal_T_424 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _atomics_legal_T_425 = xor(s2_req.addr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _atomics_legal_T_426 = cvt(_atomics_legal_T_425) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _atomics_legal_T_427 = and(_atomics_legal_T_426, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_428 = asSInt(_atomics_legal_T_427) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _atomics_legal_T_429 = eq(_atomics_legal_T_428, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _atomics_legal_T_430 = and(_atomics_legal_T_424, _atomics_legal_T_429) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _atomics_legal_T_431 = or(UInt<1>(0h0), _atomics_legal_T_423) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node atomics_legal_8 = or(_atomics_legal_T_431, _atomics_legal_T_430) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire atomics_a_8 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 517:17] connect atomics_a_8.opcode, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 518:15] connect atomics_a_8.param, UInt<3>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 519:15] connect atomics_a_8.size, s2_req.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 520:15] connect atomics_a_8.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 521:15] connect atomics_a_8.address, s2_req.addr @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 522:15] invalidate atomics_a_8.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_8.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_8.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_8.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_8.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_8.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] invalidate atomics_a_8.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 523:15] node _atomics_a_mask_sizeOH_T_24 = or(s2_req.size, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node atomics_a_mask_sizeOH_shiftAmount_8 = bits(_atomics_a_mask_sizeOH_T_24, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _atomics_a_mask_sizeOH_T_25 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_8) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _atomics_a_mask_sizeOH_T_26 = bits(_atomics_a_mask_sizeOH_T_25, 2, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node atomics_a_mask_sizeOH_8 = or(_atomics_a_mask_sizeOH_T_26, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] node atomics_a_mask_sub_sub_sub_0_1_8 = geq(s2_req.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 206:21] node atomics_a_mask_sub_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_sub_sub_bit_8 = bits(s2_req.addr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_sub_sub_nbit_8 = eq(atomics_a_mask_sub_sub_bit_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_sub_sub_0_2_8 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_sub_acc_T_16 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_0_2_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_sub_0_1_8 = or(atomics_a_mask_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_acc_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_sub_1_2_8 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_sub_acc_T_17 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_1_2_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_sub_1_1_8 = or(atomics_a_mask_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_acc_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_sub_bit_8 = bits(s2_req.addr, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_sub_nbit_8 = eq(atomics_a_mask_sub_bit_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_sub_0_2_8 = and(atomics_a_mask_sub_sub_0_2_8, atomics_a_mask_sub_nbit_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_32 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_0_2_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_0_1_8 = or(atomics_a_mask_sub_sub_0_1_8, _atomics_a_mask_sub_acc_T_32) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_1_2_8 = and(atomics_a_mask_sub_sub_0_2_8, atomics_a_mask_sub_bit_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_33 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_1_2_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_1_1_8 = or(atomics_a_mask_sub_sub_0_1_8, _atomics_a_mask_sub_acc_T_33) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_2_2_8 = and(atomics_a_mask_sub_sub_1_2_8, atomics_a_mask_sub_nbit_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_34 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_2_2_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_2_1_8 = or(atomics_a_mask_sub_sub_1_1_8, _atomics_a_mask_sub_acc_T_34) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_sub_3_2_8 = and(atomics_a_mask_sub_sub_1_2_8, atomics_a_mask_sub_bit_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_sub_acc_T_35 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_3_2_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_sub_3_1_8 = or(atomics_a_mask_sub_sub_1_1_8, _atomics_a_mask_sub_acc_T_35) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_size_8 = bits(atomics_a_mask_sizeOH_8, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node atomics_a_mask_bit_8 = bits(s2_req.addr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node atomics_a_mask_nbit_8 = eq(atomics_a_mask_bit_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node atomics_a_mask_eq_64 = and(atomics_a_mask_sub_0_2_8, atomics_a_mask_nbit_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_64 = and(atomics_a_mask_size_8, atomics_a_mask_eq_64) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_64 = or(atomics_a_mask_sub_0_1_8, _atomics_a_mask_acc_T_64) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_65 = and(atomics_a_mask_sub_0_2_8, atomics_a_mask_bit_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_65 = and(atomics_a_mask_size_8, atomics_a_mask_eq_65) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_65 = or(atomics_a_mask_sub_0_1_8, _atomics_a_mask_acc_T_65) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_66 = and(atomics_a_mask_sub_1_2_8, atomics_a_mask_nbit_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_66 = and(atomics_a_mask_size_8, atomics_a_mask_eq_66) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_66 = or(atomics_a_mask_sub_1_1_8, _atomics_a_mask_acc_T_66) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_67 = and(atomics_a_mask_sub_1_2_8, atomics_a_mask_bit_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_67 = and(atomics_a_mask_size_8, atomics_a_mask_eq_67) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_67 = or(atomics_a_mask_sub_1_1_8, _atomics_a_mask_acc_T_67) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_68 = and(atomics_a_mask_sub_2_2_8, atomics_a_mask_nbit_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_68 = and(atomics_a_mask_size_8, atomics_a_mask_eq_68) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_68 = or(atomics_a_mask_sub_2_1_8, _atomics_a_mask_acc_T_68) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_69 = and(atomics_a_mask_sub_2_2_8, atomics_a_mask_bit_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_69 = and(atomics_a_mask_size_8, atomics_a_mask_eq_69) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_69 = or(atomics_a_mask_sub_2_1_8, _atomics_a_mask_acc_T_69) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_70 = and(atomics_a_mask_sub_3_2_8, atomics_a_mask_nbit_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_70 = and(atomics_a_mask_size_8, atomics_a_mask_eq_70) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_70 = or(atomics_a_mask_sub_3_1_8, _atomics_a_mask_acc_T_70) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_eq_71 = and(atomics_a_mask_sub_3_2_8, atomics_a_mask_bit_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _atomics_a_mask_acc_T_71 = and(atomics_a_mask_size_8, atomics_a_mask_eq_71) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node atomics_a_mask_acc_71 = or(atomics_a_mask_sub_3_1_8, _atomics_a_mask_acc_T_71) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node atomics_a_mask_lo_lo_8 = cat(atomics_a_mask_acc_65, atomics_a_mask_acc_64) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_lo_hi_8 = cat(atomics_a_mask_acc_67, atomics_a_mask_acc_66) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_lo_8 = cat(atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_lo_8 = cat(atomics_a_mask_acc_69, atomics_a_mask_acc_68) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_hi_8 = cat(atomics_a_mask_acc_71, atomics_a_mask_acc_70) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node atomics_a_mask_hi_8 = cat(atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node _atomics_a_mask_T_8 = cat(atomics_a_mask_hi_8, atomics_a_mask_lo_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] connect atomics_a_8.mask, _atomics_a_mask_T_8 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 525:15] connect atomics_a_8.data, pstore1_data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 526:15] connect atomics_a_8.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 527:15] node _atomics_T = eq(UInt<3>(0h4), s2_req.cmd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:81] node _atomics_T_1 = mux(_atomics_T, atomics_a, _atomics_WIRE_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:81] node _atomics_T_2 = eq(UInt<4>(0h9), s2_req.cmd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:81] node _atomics_T_3 = mux(_atomics_T_2, atomics_a_1, _atomics_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:81] node _atomics_T_4 = eq(UInt<4>(0ha), s2_req.cmd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:81] node _atomics_T_5 = mux(_atomics_T_4, atomics_a_2, _atomics_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:81] node _atomics_T_6 = eq(UInt<4>(0hb), s2_req.cmd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:81] node _atomics_T_7 = mux(_atomics_T_6, atomics_a_3, _atomics_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:81] node _atomics_T_8 = eq(UInt<4>(0h8), s2_req.cmd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:81] node _atomics_T_9 = mux(_atomics_T_8, atomics_a_4, _atomics_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:81] node _atomics_T_10 = eq(UInt<4>(0hc), s2_req.cmd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:81] node _atomics_T_11 = mux(_atomics_T_10, atomics_a_5, _atomics_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:81] node _atomics_T_12 = eq(UInt<4>(0hd), s2_req.cmd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:81] node _atomics_T_13 = mux(_atomics_T_12, atomics_a_6, _atomics_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:81] node _atomics_T_14 = eq(UInt<4>(0he), s2_req.cmd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:81] node _atomics_T_15 = mux(_atomics_T_14, atomics_a_7, _atomics_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:81] node _atomics_T_16 = eq(UInt<4>(0hf), s2_req.cmd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:81] node atomics = mux(_atomics_T_16, atomics_a_8, _atomics_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 585:81] node _tl_out_a_valid_T = eq(io.cpu.s2_kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 601:21] node _tl_out_a_valid_T_1 = xor(s2_req.addr, release_ack_addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 604:43] node _tl_out_a_valid_T_2 = bits(_tl_out_a_valid_T_1, 20, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 604:62] node _tl_out_a_valid_T_3 = eq(_tl_out_a_valid_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 604:118] node _tl_out_a_valid_T_4 = and(release_ack_wait, _tl_out_a_valid_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 604:27] node _tl_out_a_valid_T_5 = eq(_tl_out_a_valid_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 604:8] node _tl_out_a_valid_T_6 = and(s2_valid_cached_miss, _tl_out_a_valid_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 603:29] node _tl_out_a_valid_T_7 = eq(release_ack_wait, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 605:47] node _tl_out_a_valid_T_8 = and(UInt<1>(0h0), _tl_out_a_valid_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 605:44] node _tl_out_a_valid_T_9 = and(_tl_out_a_valid_T_8, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 605:65] node _tl_out_a_valid_T_10 = eq(s2_victim_dirty, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 605:91] node _tl_out_a_valid_T_11 = or(_tl_out_a_valid_T_9, _tl_out_a_valid_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 605:88] node _tl_out_a_valid_T_12 = and(_tl_out_a_valid_T_6, _tl_out_a_valid_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 604:127] node _tl_out_a_valid_T_13 = or(s2_valid_uncached_pending, _tl_out_a_valid_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 602:32] node _tl_out_a_valid_T_14 = and(_tl_out_a_valid_T, _tl_out_a_valid_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 601:37] connect tl_out_a.valid, _tl_out_a_valid_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 601:18] node _tl_out_a_bits_T = eq(s2_uncached, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 606:24] wire _tl_out_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:67] connect _tl_out_a_bits_WIRE.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:67] connect _tl_out_a_bits_WIRE.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:67] connect _tl_out_a_bits_WIRE.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:67] connect _tl_out_a_bits_WIRE.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:67] connect _tl_out_a_bits_WIRE.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:67] connect _tl_out_a_bits_WIRE.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:67] connect _tl_out_a_bits_WIRE.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:67] connect _tl_out_a_bits_WIRE.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:67] connect _tl_out_a_bits_WIRE.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:67] connect _tl_out_a_bits_WIRE.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:67] connect _tl_out_a_bits_WIRE.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:67] connect _tl_out_a_bits_WIRE.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:67] connect _tl_out_a_bits_WIRE.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:67] connect _tl_out_a_bits_WIRE.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:67] connect _tl_out_a_bits_WIRE.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:67] wire _tl_out_a_bits_WIRE_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:54] connect _tl_out_a_bits_WIRE_1.corrupt, _tl_out_a_bits_WIRE.corrupt @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:54] connect _tl_out_a_bits_WIRE_1.data, _tl_out_a_bits_WIRE.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:54] connect _tl_out_a_bits_WIRE_1.mask, _tl_out_a_bits_WIRE.mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:54] connect _tl_out_a_bits_WIRE_1.user, _tl_out_a_bits_WIRE.user @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:54] connect _tl_out_a_bits_WIRE_1.address, _tl_out_a_bits_WIRE.address @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:54] connect _tl_out_a_bits_WIRE_1.source, _tl_out_a_bits_WIRE.source @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:54] connect _tl_out_a_bits_WIRE_1.size, _tl_out_a_bits_WIRE.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:54] connect _tl_out_a_bits_WIRE_1.param, _tl_out_a_bits_WIRE.param @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:54] connect _tl_out_a_bits_WIRE_1.opcode, _tl_out_a_bits_WIRE.opcode @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1207:54] node _tl_out_a_bits_T_1 = eq(s2_write, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 607:9] node _tl_out_a_bits_T_2 = eq(s2_req.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 608:20] node _tl_out_a_bits_T_3 = eq(s2_read, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 609:9] node _tl_out_a_bits_T_4 = mux(_tl_out_a_bits_T_3, put, atomics) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 609:8] node _tl_out_a_bits_T_5 = mux(_tl_out_a_bits_T_2, putpartial, _tl_out_a_bits_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 608:8] node _tl_out_a_bits_T_6 = mux(_tl_out_a_bits_T_1, get, _tl_out_a_bits_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 607:8] node _tl_out_a_bits_T_7 = mux(_tl_out_a_bits_T, _tl_out_a_bits_WIRE_1, _tl_out_a_bits_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 606:23] connect tl_out_a.bits, _tl_out_a_bits_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 606:17] node _tl_out_a_bits_user_amba_prot_privileged_T = eq(s2_req.dprv, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 615:34] node _tl_out_a_bits_user_amba_prot_privileged_T_1 = or(_tl_out_a_bits_user_amba_prot_privileged_T, s2_pma.cacheable) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 615:46] connect tl_out_a.bits.user.amba_prot.privileged, _tl_out_a_bits_user_amba_prot_privileged_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 615:19] connect tl_out_a.bits.user.amba_prot.bufferable, s2_pma.cacheable @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 617:19] connect tl_out_a.bits.user.amba_prot.modifiable, s2_pma.cacheable @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 618:19] connect tl_out_a.bits.user.amba_prot.readalloc, s2_pma.cacheable @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 619:19] connect tl_out_a.bits.user.amba_prot.writealloc, s2_pma.cacheable @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 620:19] connect tl_out_a.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 623:19] connect tl_out_a.bits.user.amba_prot.secure, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 624:19] node a_sel = shr(UInt<1>(0h1), 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 628:66] node _T_60 = and(tl_out_a.ready, tl_out_a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_60 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 629:24] when s2_uncached : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 630:24] node _T_61 = bits(a_sel, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 631:14] when _T_61 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 632:18] connect uncachedInFlight[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 633:13] connect uncachedReqs[0], s2_req @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 634:13] node _uncachedReqs_0_cmd_T = eq(s2_req.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 635:49] node _uncachedReqs_0_cmd_T_1 = mux(_uncachedReqs_0_cmd_T, UInt<5>(0h11), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 635:37] node _uncachedReqs_0_cmd_T_2 = mux(s2_write, _uncachedReqs_0_cmd_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 635:23] connect uncachedReqs[0].cmd, _uncachedReqs_0_cmd_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 635:17] else : connect cached_grant_wait, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 639:25] connect refill_way, s2_victim_or_hit_way @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 640:18] node _T_62 = and(nodeOut.d.ready, nodeOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _r_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node r_beats1_decode = shr(_r_beats1_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node r_beats1_opdata = bits(nodeOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node r_counter1 = tail(_r_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node d_first = eq(r_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _r_last_T = eq(r_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node d_last = or(_r_last_T, _r_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node d_done = and(d_last, _T_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _r_count_T = not(r_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node r_4 = and(r_beats1, _r_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _T_62 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _r_counter_T = mux(d_first, r_beats1, r_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect r_counter, _r_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node d_address_inc = shl(r_4, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 269:29] node _T_63 = eq(nodeOut.d.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 652:14] node _T_64 = eq(nodeOut.d.bits.opcode, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_65 = eq(nodeOut.d.bits.opcode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_66 = eq(nodeOut.d.bits.opcode, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_67 = or(_T_64, _T_65) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_68 = or(_T_67, _T_66) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_69 = or(_T_63, _T_68) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 652:30] node _T_70 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 652:13] node _T_71 = eq(_T_70, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 652:13] when _T_71 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 652:13] node _T_72 = eq(_T_69, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 652:13] when _T_72 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 652:13] printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:652 assert(!tl_out.d.valid || whole_opc.isOneOf(uncachedGrantOpcodes))\n") : printf_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 652:13] assert(clock, _T_69, UInt<1>(0h1), "") : assert_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 652:13] node d_opc = bits(nodeOut.d.bits.opcode, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 654:26] wire data_plaInput : UInt<2> @[src/main/scala/chisel3/util/pla.scala 77:22] node data_invInputs = not(data_plaInput) @[src/main/scala/chisel3/util/pla.scala 78:21] wire data_plaOutput : UInt<1> @[src/main/scala/chisel3/util/pla.scala 81:23] node data_andMatrixOutputs_andMatrixInput_0 = bits(data_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node data_andMatrixOutputs_andMatrixInput_1 = bits(data_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node _data_andMatrixOutputs_T = cat(data_andMatrixOutputs_andMatrixInput_0, data_andMatrixOutputs_andMatrixInput_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node data_andMatrixOutputs_0_2 = andr(_data_andMatrixOutputs_T) @[src/main/scala/chisel3/util/pla.scala 98:70] node data_orMatrixOutputs = orr(data_andMatrixOutputs_0_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node data_invMatrixOutputs = bits(data_orMatrixOutputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 124:31] connect data_plaOutput, data_invMatrixOutputs @[src/main/scala/chisel3/util/pla.scala 129:13] connect data_plaInput, d_opc @[src/main/scala/chisel3/util/experimental/decode/decoder.scala 35:16] node grantIsUncachedData = bits(data_plaOutput, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 55:116] node _tl_d_data_encoded_T_9 = bits(io.ptw.customCSRs.csrs[0].value, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tile/CustomCSRs.scala 47:65] node _tl_d_data_encoded_T_10 = eq(_tl_d_data_encoded_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 661:80] node _tl_d_data_encoded_T_11 = and(nodeOut.d.bits.corrupt, _tl_d_data_encoded_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 661:77] node _tl_d_data_encoded_T_12 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 661:129] node _tl_d_data_encoded_T_13 = and(_tl_d_data_encoded_T_11, _tl_d_data_encoded_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 661:126] node _tl_d_data_encoded_T_14 = bits(nodeOut.d.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _tl_d_data_encoded_T_15 = bits(nodeOut.d.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _tl_d_data_encoded_T_16 = bits(nodeOut.d.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _tl_d_data_encoded_T_17 = bits(nodeOut.d.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _tl_d_data_encoded_T_18 = bits(nodeOut.d.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _tl_d_data_encoded_T_19 = bits(nodeOut.d.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _tl_d_data_encoded_T_20 = bits(nodeOut.d.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node _tl_d_data_encoded_T_21 = bits(nodeOut.d.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] node tl_d_data_encoded_lo_lo_1 = cat(_tl_d_data_encoded_T_15, _tl_d_data_encoded_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node tl_d_data_encoded_lo_hi_1 = cat(_tl_d_data_encoded_T_17, _tl_d_data_encoded_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node tl_d_data_encoded_lo_1 = cat(tl_d_data_encoded_lo_hi_1, tl_d_data_encoded_lo_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node tl_d_data_encoded_hi_lo_1 = cat(_tl_d_data_encoded_T_19, _tl_d_data_encoded_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node tl_d_data_encoded_hi_hi_1 = cat(_tl_d_data_encoded_T_21, _tl_d_data_encoded_T_20) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node tl_d_data_encoded_hi_1 = cat(tl_d_data_encoded_hi_hi_1, tl_d_data_encoded_hi_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _tl_d_data_encoded_T_22 = cat(tl_d_data_encoded_hi_1, tl_d_data_encoded_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] connect tl_d_data_encoded, _tl_d_data_encoded_T_22 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 661:21] node _grantIsCached_T = eq(d_opc, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _grantIsCached_T_1 = eq(d_opc, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node grantIsCached = or(_grantIsCached_T, _grantIsCached_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node grantIsVoluntary = eq(d_opc, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 663:32] node grantIsRefill = eq(d_opc, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 664:29] regreset grantInProgress : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 665:32] regreset blockProbeAfterGrantCount : UInt, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 666:42] node _T_73 = gt(blockProbeAfterGrantCount, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 667:35] when _T_73 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 667:42] node _blockProbeAfterGrantCount_T = sub(blockProbeAfterGrantCount, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 667:99] node _blockProbeAfterGrantCount_T_1 = tail(_blockProbeAfterGrantCount_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 667:99] connect blockProbeAfterGrantCount, _blockProbeAfterGrantCount_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 667:70] node _canAcceptCachedGrant_T = eq(release_state, UInt<4>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _canAcceptCachedGrant_T_1 = eq(release_state, UInt<4>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _canAcceptCachedGrant_T_2 = eq(release_state, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _canAcceptCachedGrant_T_3 = or(_canAcceptCachedGrant_T, _canAcceptCachedGrant_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _canAcceptCachedGrant_T_4 = or(_canAcceptCachedGrant_T_3, _canAcceptCachedGrant_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node canAcceptCachedGrant = eq(_canAcceptCachedGrant_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 668:30] node _nodeOut_d_ready_T = eq(d_first, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 669:41] wire _nodeOut_d_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _nodeOut_d_ready_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _nodeOut_d_ready_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _nodeOut_d_ready_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _nodeOut_d_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _nodeOut_d_ready_WIRE_1.bits, _nodeOut_d_ready_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _nodeOut_d_ready_WIRE_1.valid, _nodeOut_d_ready_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _nodeOut_d_ready_WIRE_1.ready, _nodeOut_d_ready_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] node _nodeOut_d_ready_T_1 = or(_nodeOut_d_ready_T, _nodeOut_d_ready_WIRE_1.ready) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 669:50] node _nodeOut_d_ready_T_2 = and(_nodeOut_d_ready_T_1, canAcceptCachedGrant) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 669:69] node _nodeOut_d_ready_T_3 = mux(grantIsCached, _nodeOut_d_ready_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 669:24] connect nodeOut.d.ready, _nodeOut_d_ready_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 669:18] node uncachedRespIdxOH = shr(UInt<1>(0h1), 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 670:90] node _uncachedResp_T = bits(uncachedRespIdxOH, 0, 0) @[src/main/scala/chisel3/util/Mux.scala 32:36] connect uncachedResp, uncachedReqs[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 671:16] node _T_74 = and(nodeOut.d.ready, nodeOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_74 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 672:24] when grantIsCached : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 673:26] connect grantInProgress, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 674:23] node _T_75 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 675:13] node _T_76 = eq(_T_75, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 675:13] when _T_76 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 675:13] node _T_77 = eq(cached_grant_wait, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 675:13] when _T_77 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 675:13] printf(clock, UInt<1>(0h1), "Assertion failed: A GrantData was unexpected by the dcache.\n at DCache.scala:675 assert(cached_grant_wait, \"A GrantData was unexpected by the dcache.\")\n") : printf_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 675:13] assert(clock, cached_grant_wait, UInt<1>(0h1), "") : assert_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 675:13] when d_last : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 676:20] connect cached_grant_wait, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 677:27] connect grantInProgress, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 678:25] connect blockProbeAfterGrantCount, UInt<3>(0h7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 679:35] connect replace, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 45:22] else : when UInt<1>(0h1) : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 682:35] node _T_78 = bits(uncachedRespIdxOH, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 683:26] node _T_79 = and(_T_78, d_last) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 684:17] when _T_79 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 684:28] node _T_80 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 685:17] node _T_81 = eq(_T_80, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 685:17] when _T_81 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 685:17] node _T_82 = eq(uncachedInFlight[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 685:17] when _T_82 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 685:17] printf(clock, UInt<1>(0h1), "Assertion failed: An AccessAck was unexpected by the dcache.\n at DCache.scala:685 assert(f, \"An AccessAck was unexpected by the dcache.\") // TODO must handle Ack coming back on same cycle!\n") : printf_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 685:17] assert(clock, uncachedInFlight[0], UInt<1>(0h1), "") : assert_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 685:17] connect uncachedInFlight[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 686:13] when grantIsUncachedData : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 689:34] node _s1_data_way_T = shl(UInt<1>(0h1), 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 692:32] connect s1_data_way, _s1_data_way_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 692:25] connect s2_req.cmd, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 693:22] connect s2_req.size, uncachedResp.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 694:23] connect s2_req.signed, uncachedResp.signed @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 695:25] connect s2_req.tag, uncachedResp.tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 696:22] node _s2_req_addr_dontCareBits_T = shr(s1_paddr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 699:41] node s2_req_addr_dontCareBits = shl(_s2_req_addr_dontCareBits_T, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 699:55] node _s2_req_addr_T = bits(uncachedResp.addr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 700:45] node _s2_req_addr_T_1 = or(s2_req_addr_dontCareBits, _s2_req_addr_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 700:26] connect s2_req.addr, _s2_req_addr_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 697:23] connect s2_uncached_resp_addr, uncachedResp.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 702:33] else : when grantIsVoluntary : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 705:36] node _T_83 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 706:13] node _T_84 = eq(_T_83, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 706:13] when _T_84 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 706:13] node _T_85 = eq(release_ack_wait, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 706:13] when _T_85 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 706:13] printf(clock, UInt<1>(0h1), "Assertion failed: A ReleaseAck was unexpected by the dcache.\n at DCache.scala:706 assert(release_ack_wait, \"A ReleaseAck was unexpected by the dcache.\") // TODO should handle Ack coming back on same cycle!\n") : printf_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 706:13] assert(clock, release_ack_wait, UInt<1>(0h1), "") : assert_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 706:13] connect release_ack_wait, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 707:24] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_1.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_1.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_2.bits, _WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_2.valid, _WIRE_1.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_2.ready, _WIRE_1.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] node _T_86 = and(nodeOut.d.valid, d_first) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 712:36] node _T_87 = and(_T_86, grantIsCached) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 712:47] node _T_88 = and(_T_87, canAcceptCachedGrant) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 712:64] connect _WIRE_2.valid, _T_88 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 712:18] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_3.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_3.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_3.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_4.bits, _WIRE_3.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_4.valid, _WIRE_3.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_4.ready, _WIRE_3.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire e : { sink : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 451:17] connect e.sink, nodeOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 452:12] connect _WIRE_4.bits, e @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 713:17] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_5.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_5.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_5.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_6.bits, _WIRE_5.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_6.valid, _WIRE_5.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_6.ready, _WIRE_5.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] node _T_89 = and(_WIRE_6.ready, _WIRE_6.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_90 = and(nodeOut.d.ready, nodeOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_91 = and(_T_90, d_first) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 714:43] node _T_92 = and(_T_91, grantIsCached) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 714:54] node _T_93 = eq(_T_89, _T_92) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 714:24] node _T_94 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 714:9] node _T_95 = eq(_T_94, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 714:9] when _T_95 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 714:9] node _T_96 = eq(_T_93, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 714:9] when _T_96 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 714:9] printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:714 assert(tl_out.e.fire === (tl_out.d.fire && d_first && grantIsCached))\n") : printf_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 714:9] assert(clock, _T_93, UInt<1>(0h1), "") : assert_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 714:9] node _dataArb_io_in_1_valid_T = and(nodeOut.d.valid, grantIsRefill) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 719:44] node _dataArb_io_in_1_valid_T_1 = and(_dataArb_io_in_1_valid_T, canAcceptCachedGrant) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 719:61] connect dataArb.io.in[1].valid, _dataArb_io_in_1_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 719:26] node _T_97 = eq(dataArb.io.in[1].ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 720:26] node _T_98 = and(grantIsRefill, _T_97) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 720:23] when _T_98 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 720:51] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_7.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_7.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_7.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_8.bits, _WIRE_7.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_8.valid, _WIRE_7.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_8.ready, _WIRE_7.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 721:20] connect nodeOut.d.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 722:20] connect dataArb.io.in[1].bits.way_en, dataArb.io.in[0].bits.way_en @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 732:27] connect dataArb.io.in[1].bits.eccMask, dataArb.io.in[0].bits.eccMask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 732:27] connect dataArb.io.in[1].bits.wordMask, dataArb.io.in[0].bits.wordMask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 732:27] connect dataArb.io.in[1].bits.wdata, dataArb.io.in[0].bits.wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 732:27] connect dataArb.io.in[1].bits.write, dataArb.io.in[0].bits.write @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 732:27] connect dataArb.io.in[1].bits.addr, dataArb.io.in[0].bits.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 732:27] node _metaArb_io_in_3_valid_T = and(grantIsCached, d_done) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 739:43] node _metaArb_io_in_3_valid_T_1 = eq(nodeOut.d.bits.denied, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 739:56] node _metaArb_io_in_3_valid_T_2 = and(_metaArb_io_in_3_valid_T, _metaArb_io_in_3_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 739:53] connect metaArb.io.in[3].valid, _metaArb_io_in_3_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 739:26] connect metaArb.io.in[3].bits.write, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 740:31] connect metaArb.io.in[3].bits.way_en, refill_way @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 741:32] node _metaArb_io_in_3_bits_idx_T = bits(s2_vaddr, 19, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 742:40] connect metaArb.io.in[3].bits.idx, _metaArb_io_in_3_bits_idx_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 742:29] node _metaArb_io_in_3_bits_addr_T = shr(io.cpu.req.bits.addr, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 743:58] node _metaArb_io_in_3_bits_addr_T_1 = bits(s2_vaddr, 19, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 743:80] node _metaArb_io_in_3_bits_addr_T_2 = cat(_metaArb_io_in_3_bits_addr_T, _metaArb_io_in_3_bits_addr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 743:36] connect metaArb.io.in[3].bits.addr, _metaArb_io_in_3_bits_addr_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 743:30] node _metaArb_io_in_3_bits_data_T = shr(s2_req.addr, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 744:68] node _metaArb_io_in_3_bits_data_c_cat_T = eq(s2_req.cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:32] node _metaArb_io_in_3_bits_data_c_cat_T_1 = eq(s2_req.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:49] node _metaArb_io_in_3_bits_data_c_cat_T_2 = or(_metaArb_io_in_3_bits_data_c_cat_T, _metaArb_io_in_3_bits_data_c_cat_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:42] node _metaArb_io_in_3_bits_data_c_cat_T_3 = eq(s2_req.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:66] node _metaArb_io_in_3_bits_data_c_cat_T_4 = or(_metaArb_io_in_3_bits_data_c_cat_T_2, _metaArb_io_in_3_bits_data_c_cat_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:59] node _metaArb_io_in_3_bits_data_c_cat_T_5 = eq(s2_req.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_3_bits_data_c_cat_T_6 = eq(s2_req.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_3_bits_data_c_cat_T_7 = eq(s2_req.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_3_bits_data_c_cat_T_8 = eq(s2_req.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_3_bits_data_c_cat_T_9 = or(_metaArb_io_in_3_bits_data_c_cat_T_5, _metaArb_io_in_3_bits_data_c_cat_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _metaArb_io_in_3_bits_data_c_cat_T_10 = or(_metaArb_io_in_3_bits_data_c_cat_T_9, _metaArb_io_in_3_bits_data_c_cat_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _metaArb_io_in_3_bits_data_c_cat_T_11 = or(_metaArb_io_in_3_bits_data_c_cat_T_10, _metaArb_io_in_3_bits_data_c_cat_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _metaArb_io_in_3_bits_data_c_cat_T_12 = eq(s2_req.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_3_bits_data_c_cat_T_13 = eq(s2_req.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_3_bits_data_c_cat_T_14 = eq(s2_req.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_3_bits_data_c_cat_T_15 = eq(s2_req.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_3_bits_data_c_cat_T_16 = eq(s2_req.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_3_bits_data_c_cat_T_17 = or(_metaArb_io_in_3_bits_data_c_cat_T_12, _metaArb_io_in_3_bits_data_c_cat_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _metaArb_io_in_3_bits_data_c_cat_T_18 = or(_metaArb_io_in_3_bits_data_c_cat_T_17, _metaArb_io_in_3_bits_data_c_cat_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _metaArb_io_in_3_bits_data_c_cat_T_19 = or(_metaArb_io_in_3_bits_data_c_cat_T_18, _metaArb_io_in_3_bits_data_c_cat_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _metaArb_io_in_3_bits_data_c_cat_T_20 = or(_metaArb_io_in_3_bits_data_c_cat_T_19, _metaArb_io_in_3_bits_data_c_cat_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _metaArb_io_in_3_bits_data_c_cat_T_21 = or(_metaArb_io_in_3_bits_data_c_cat_T_11, _metaArb_io_in_3_bits_data_c_cat_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node _metaArb_io_in_3_bits_data_c_cat_T_22 = or(_metaArb_io_in_3_bits_data_c_cat_T_4, _metaArb_io_in_3_bits_data_c_cat_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:76] node _metaArb_io_in_3_bits_data_c_cat_T_23 = eq(s2_req.cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:32] node _metaArb_io_in_3_bits_data_c_cat_T_24 = eq(s2_req.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:49] node _metaArb_io_in_3_bits_data_c_cat_T_25 = or(_metaArb_io_in_3_bits_data_c_cat_T_23, _metaArb_io_in_3_bits_data_c_cat_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:42] node _metaArb_io_in_3_bits_data_c_cat_T_26 = eq(s2_req.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:66] node _metaArb_io_in_3_bits_data_c_cat_T_27 = or(_metaArb_io_in_3_bits_data_c_cat_T_25, _metaArb_io_in_3_bits_data_c_cat_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:59] node _metaArb_io_in_3_bits_data_c_cat_T_28 = eq(s2_req.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_3_bits_data_c_cat_T_29 = eq(s2_req.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_3_bits_data_c_cat_T_30 = eq(s2_req.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_3_bits_data_c_cat_T_31 = eq(s2_req.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_3_bits_data_c_cat_T_32 = or(_metaArb_io_in_3_bits_data_c_cat_T_28, _metaArb_io_in_3_bits_data_c_cat_T_29) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _metaArb_io_in_3_bits_data_c_cat_T_33 = or(_metaArb_io_in_3_bits_data_c_cat_T_32, _metaArb_io_in_3_bits_data_c_cat_T_30) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _metaArb_io_in_3_bits_data_c_cat_T_34 = or(_metaArb_io_in_3_bits_data_c_cat_T_33, _metaArb_io_in_3_bits_data_c_cat_T_31) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _metaArb_io_in_3_bits_data_c_cat_T_35 = eq(s2_req.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_3_bits_data_c_cat_T_36 = eq(s2_req.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_3_bits_data_c_cat_T_37 = eq(s2_req.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_3_bits_data_c_cat_T_38 = eq(s2_req.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_3_bits_data_c_cat_T_39 = eq(s2_req.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_3_bits_data_c_cat_T_40 = or(_metaArb_io_in_3_bits_data_c_cat_T_35, _metaArb_io_in_3_bits_data_c_cat_T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _metaArb_io_in_3_bits_data_c_cat_T_41 = or(_metaArb_io_in_3_bits_data_c_cat_T_40, _metaArb_io_in_3_bits_data_c_cat_T_37) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _metaArb_io_in_3_bits_data_c_cat_T_42 = or(_metaArb_io_in_3_bits_data_c_cat_T_41, _metaArb_io_in_3_bits_data_c_cat_T_38) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _metaArb_io_in_3_bits_data_c_cat_T_43 = or(_metaArb_io_in_3_bits_data_c_cat_T_42, _metaArb_io_in_3_bits_data_c_cat_T_39) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _metaArb_io_in_3_bits_data_c_cat_T_44 = or(_metaArb_io_in_3_bits_data_c_cat_T_34, _metaArb_io_in_3_bits_data_c_cat_T_43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node _metaArb_io_in_3_bits_data_c_cat_T_45 = or(_metaArb_io_in_3_bits_data_c_cat_T_27, _metaArb_io_in_3_bits_data_c_cat_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:76] node _metaArb_io_in_3_bits_data_c_cat_T_46 = eq(s2_req.cmd, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 91:54] node _metaArb_io_in_3_bits_data_c_cat_T_47 = or(_metaArb_io_in_3_bits_data_c_cat_T_45, _metaArb_io_in_3_bits_data_c_cat_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 91:47] node _metaArb_io_in_3_bits_data_c_cat_T_48 = eq(s2_req.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 91:71] node _metaArb_io_in_3_bits_data_c_cat_T_49 = or(_metaArb_io_in_3_bits_data_c_cat_T_47, _metaArb_io_in_3_bits_data_c_cat_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 91:64] node metaArb_io_in_3_bits_data_c = cat(_metaArb_io_in_3_bits_data_c_cat_T_22, _metaArb_io_in_3_bits_data_c_cat_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 29:18] node _metaArb_io_in_3_bits_data_T_1 = cat(metaArb_io_in_3_bits_data_c, nodeOut.d.bits.param) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 84:18] node _metaArb_io_in_3_bits_data_T_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 26:15] node _metaArb_io_in_3_bits_data_T_3 = cat(_metaArb_io_in_3_bits_data_T_2, UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 86:10] node _metaArb_io_in_3_bits_data_T_4 = cat(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 26:15] node _metaArb_io_in_3_bits_data_T_5 = cat(_metaArb_io_in_3_bits_data_T_4, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 87:10] node _metaArb_io_in_3_bits_data_T_6 = cat(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 25:15] node _metaArb_io_in_3_bits_data_T_7 = cat(_metaArb_io_in_3_bits_data_T_6, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 88:10] node _metaArb_io_in_3_bits_data_T_8 = cat(UInt<1>(0h1), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 24:15] node _metaArb_io_in_3_bits_data_T_9 = cat(_metaArb_io_in_3_bits_data_T_8, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 89:10] node _metaArb_io_in_3_bits_data_T_10 = eq(_metaArb_io_in_3_bits_data_T_3, _metaArb_io_in_3_bits_data_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 84:38] node _metaArb_io_in_3_bits_data_T_11 = mux(_metaArb_io_in_3_bits_data_T_10, UInt<2>(0h1), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 84:38] node _metaArb_io_in_3_bits_data_T_12 = eq(_metaArb_io_in_3_bits_data_T_5, _metaArb_io_in_3_bits_data_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 84:38] node _metaArb_io_in_3_bits_data_T_13 = mux(_metaArb_io_in_3_bits_data_T_12, UInt<2>(0h2), _metaArb_io_in_3_bits_data_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 84:38] node _metaArb_io_in_3_bits_data_T_14 = eq(_metaArb_io_in_3_bits_data_T_7, _metaArb_io_in_3_bits_data_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 84:38] node _metaArb_io_in_3_bits_data_T_15 = mux(_metaArb_io_in_3_bits_data_T_14, UInt<2>(0h2), _metaArb_io_in_3_bits_data_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 84:38] node _metaArb_io_in_3_bits_data_T_16 = eq(_metaArb_io_in_3_bits_data_T_9, _metaArb_io_in_3_bits_data_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 84:38] node _metaArb_io_in_3_bits_data_T_17 = mux(_metaArb_io_in_3_bits_data_T_16, UInt<2>(0h3), _metaArb_io_in_3_bits_data_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 84:38] wire metaArb_io_in_3_bits_data_meta : { state : UInt<2>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 160:20] connect metaArb_io_in_3_bits_data_meta.state, _metaArb_io_in_3_bits_data_T_17 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 161:16] wire metaArb_io_in_3_bits_data_meta_1 : { coh : { state : UInt<2>}, tag : UInt<12>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 305:20] connect metaArb_io_in_3_bits_data_meta_1.tag, _metaArb_io_in_3_bits_data_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 306:14] connect metaArb_io_in_3_bits_data_meta_1.coh, metaArb_io_in_3_bits_data_meta @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 307:14] node _metaArb_io_in_3_bits_data_T_18 = cat(metaArb_io_in_3_bits_data_meta_1.coh.state, metaArb_io_in_3_bits_data_meta_1.tag) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 744:134] connect metaArb.io.in[3].bits.data, _metaArb_io_in_3_bits_data_T_18 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 744:30] reg blockUncachedGrant : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 748:33] connect blockUncachedGrant, dataArb.io.out.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 749:24] node _T_99 = or(blockUncachedGrant, s1_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 750:54] node _T_100 = and(grantIsUncachedData, _T_99) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 750:31] when _T_100 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 750:68] connect nodeOut.d.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 751:22] when nodeOut.d.valid : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 753:29] connect io.cpu.req.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 754:26] connect dataArb.io.in[1].valid, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 755:32] connect dataArb.io.in[1].bits.write, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 756:37] node _blockUncachedGrant_T = eq(dataArb.io.in[1].ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 757:31] connect blockUncachedGrant, _blockUncachedGrant_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 757:28] node _T_101 = eq(nodeOut.d.ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 761:28] node _T_102 = and(nodeOut.d.valid, _T_101) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 761:25] node _block_probe_for_core_progress_T = gt(blockProbeAfterGrantCount, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 764:65] node block_probe_for_core_progress = or(_block_probe_for_core_progress_T, lrscValid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 764:71] wire _block_probe_for_pending_release_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _block_probe_for_pending_release_ack_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _block_probe_for_pending_release_ack_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _block_probe_for_pending_release_ack_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _block_probe_for_pending_release_ack_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _block_probe_for_pending_release_ack_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _block_probe_for_pending_release_ack_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _block_probe_for_pending_release_ack_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _block_probe_for_pending_release_ack_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _block_probe_for_pending_release_ack_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _block_probe_for_pending_release_ack_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _block_probe_for_pending_release_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _block_probe_for_pending_release_ack_WIRE_1.bits, _block_probe_for_pending_release_ack_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _block_probe_for_pending_release_ack_WIRE_1.valid, _block_probe_for_pending_release_ack_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _block_probe_for_pending_release_ack_WIRE_1.ready, _block_probe_for_pending_release_ack_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _block_probe_for_pending_release_ack_T = xor(_block_probe_for_pending_release_ack_WIRE_1.bits.address, release_ack_addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 765:88] node _block_probe_for_pending_release_ack_T_1 = bits(_block_probe_for_pending_release_ack_T, 20, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 765:107] node _block_probe_for_pending_release_ack_T_2 = eq(_block_probe_for_pending_release_ack_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 765:163] node block_probe_for_pending_release_ack = and(release_ack_wait, _block_probe_for_pending_release_ack_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 765:62] node _block_probe_for_ordering_T = or(releaseInFlight, block_probe_for_pending_release_ack) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 766:50] node block_probe_for_ordering = or(_block_probe_for_ordering_T, grantInProgress) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 766:89] wire _metaArb_io_in_6_valid_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_valid_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_valid_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_valid_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_valid_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_valid_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_valid_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_valid_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_valid_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_valid_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_valid_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _metaArb_io_in_6_valid_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _metaArb_io_in_6_valid_WIRE_1.bits, _metaArb_io_in_6_valid_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _metaArb_io_in_6_valid_WIRE_1.valid, _metaArb_io_in_6_valid_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _metaArb_io_in_6_valid_WIRE_1.ready, _metaArb_io_in_6_valid_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _metaArb_io_in_6_valid_T = eq(block_probe_for_core_progress, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 767:48] node _metaArb_io_in_6_valid_T_1 = or(_metaArb_io_in_6_valid_T, lrscBackingOff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 767:79] node _metaArb_io_in_6_valid_T_2 = and(_metaArb_io_in_6_valid_WIRE_1.valid, _metaArb_io_in_6_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 767:44] connect metaArb.io.in[6].valid, _metaArb_io_in_6_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 767:26] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_9.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_9.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_9.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_9.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_9.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_9.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_9.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_9.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_9.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_10.bits, _WIRE_9.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_10.valid, _WIRE_9.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_10.ready, _WIRE_9.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _T_103 = or(block_probe_for_core_progress, block_probe_for_ordering) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 768:79] node _T_104 = or(_T_103, s1_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 768:107] node _T_105 = or(_T_104, s2_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 768:119] node _T_106 = eq(_T_105, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 768:47] node _T_107 = and(metaArb.io.in[6].ready, _T_106) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 768:44] connect _WIRE_10.ready, _T_107 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 768:18] connect metaArb.io.in[6].bits.write, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 769:31] wire _metaArb_io_in_6_bits_idx_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_idx_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_idx_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_idx_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_idx_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_idx_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_idx_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_idx_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_idx_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_idx_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_idx_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _metaArb_io_in_6_bits_idx_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _metaArb_io_in_6_bits_idx_WIRE_1.bits, _metaArb_io_in_6_bits_idx_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _metaArb_io_in_6_bits_idx_WIRE_1.valid, _metaArb_io_in_6_bits_idx_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _metaArb_io_in_6_bits_idx_WIRE_1.ready, _metaArb_io_in_6_bits_idx_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _metaArb_io_in_6_bits_idx_T = bits(_metaArb_io_in_6_bits_idx_WIRE_1.bits.address, 19, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1198:47] connect metaArb.io.in[6].bits.idx, _metaArb_io_in_6_bits_idx_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 770:29] node _metaArb_io_in_6_bits_addr_T = shr(io.cpu.req.bits.addr, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 771:58] wire _metaArb_io_in_6_bits_addr_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_addr_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_addr_WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_addr_WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_addr_WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_addr_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_addr_WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_addr_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_addr_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_addr_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _metaArb_io_in_6_bits_addr_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _metaArb_io_in_6_bits_addr_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _metaArb_io_in_6_bits_addr_WIRE_1.bits, _metaArb_io_in_6_bits_addr_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _metaArb_io_in_6_bits_addr_WIRE_1.valid, _metaArb_io_in_6_bits_addr_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _metaArb_io_in_6_bits_addr_WIRE_1.ready, _metaArb_io_in_6_bits_addr_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _metaArb_io_in_6_bits_addr_T_1 = cat(_metaArb_io_in_6_bits_addr_T, _metaArb_io_in_6_bits_addr_WIRE_1.bits.address) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 771:36] connect metaArb.io.in[6].bits.addr, _metaArb_io_in_6_bits_addr_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 771:30] connect metaArb.io.in[6].bits.way_en, metaArb.io.in[4].bits.way_en @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 772:32] connect metaArb.io.in[6].bits.data, metaArb.io.in[4].bits.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 773:30] connect s1_victim_way, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 776:17] node _T_108 = and(tl_out_c.ready, tl_out_c.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _r_beats1_decode_T_3 = dshl(UInt<12>(0hfff), tl_out_c.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node r_beats1_opdata_1 = bits(tl_out_c.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 102:36] node r_beats1_1 = mux(UInt<1>(0h0), r_beats1_decode_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset r_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node r_counter1_1 = tail(_r_counter1_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node c_first = eq(r_counter_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node c_last = or(_r_last_T_2, _r_last_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node releaseDone = and(c_last, _T_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _r_count_T_1 = not(r_counter1_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node c_count = and(r_beats1_1, _r_count_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _T_108 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _r_counter_T_1 = mux(c_first, r_beats1_1, r_counter1_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect r_counter_1, _r_counter_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] wire releaseRejected : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 798:29] node _s1_release_data_valid_T = and(dataArb.io.in[2].ready, dataArb.io.in[2].valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] reg s1_release_data_valid : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 799:38] connect s1_release_data_valid, _s1_release_data_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 799:38] node _s2_release_data_valid_T = eq(releaseRejected, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 800:64] node _s2_release_data_valid_T_1 = and(s1_release_data_valid, _s2_release_data_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 800:61] reg s2_release_data_valid : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 800:38] connect s2_release_data_valid, _s2_release_data_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 800:38] node _releaseRejected_T = and(tl_out_c.ready, tl_out_c.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _releaseRejected_T_1 = eq(_releaseRejected_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 801:47] node _releaseRejected_T_2 = and(s2_release_data_valid, _releaseRejected_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 801:44] connect releaseRejected, _releaseRejected_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 801:19] node _releaseDataBeat_T = cat(UInt<1>(0h0), c_count) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 802:28] node _releaseDataBeat_T_1 = cat(UInt<1>(0h0), s2_release_data_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 802:98] node _releaseDataBeat_T_2 = add(s1_release_data_valid, _releaseDataBeat_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 802:93] node _releaseDataBeat_T_3 = tail(_releaseDataBeat_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 802:93] node _releaseDataBeat_T_4 = mux(releaseRejected, UInt<1>(0h0), _releaseDataBeat_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 802:48] node _releaseDataBeat_T_5 = add(_releaseDataBeat_T, _releaseDataBeat_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 802:43] node releaseDataBeat = tail(_releaseDataBeat_T_5, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 802:43] wire nackResponseMessage : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 416:17] connect nackResponseMessage.opcode, UInt<3>(0h4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 417:15] connect nackResponseMessage.param, UInt<3>(0h5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 418:15] connect nackResponseMessage.size, probe_bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 419:15] connect nackResponseMessage.source, probe_bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 420:15] connect nackResponseMessage.address, probe_bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 421:15] invalidate nackResponseMessage.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 422:15] invalidate nackResponseMessage.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 422:15] invalidate nackResponseMessage.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 422:15] invalidate nackResponseMessage.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 422:15] invalidate nackResponseMessage.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 422:15] invalidate nackResponseMessage.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 422:15] invalidate nackResponseMessage.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 422:15] invalidate nackResponseMessage.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 424:15] connect nackResponseMessage.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 425:15] wire cleanReleaseMessage : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 416:17] connect cleanReleaseMessage.opcode, UInt<3>(0h4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 417:15] connect cleanReleaseMessage.param, s2_report_param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 418:15] connect cleanReleaseMessage.size, probe_bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 419:15] connect cleanReleaseMessage.source, probe_bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 420:15] connect cleanReleaseMessage.address, probe_bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 421:15] invalidate cleanReleaseMessage.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 422:15] invalidate cleanReleaseMessage.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 422:15] invalidate cleanReleaseMessage.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 422:15] invalidate cleanReleaseMessage.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 422:15] invalidate cleanReleaseMessage.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 422:15] invalidate cleanReleaseMessage.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 422:15] invalidate cleanReleaseMessage.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 422:15] invalidate cleanReleaseMessage.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 424:15] connect cleanReleaseMessage.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 425:15] wire dirtyReleaseMessage : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 433:17] connect dirtyReleaseMessage.opcode, UInt<3>(0h5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 434:15] connect dirtyReleaseMessage.param, s2_report_param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 435:15] connect dirtyReleaseMessage.size, probe_bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 436:15] connect dirtyReleaseMessage.source, probe_bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 437:15] connect dirtyReleaseMessage.address, probe_bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 438:15] invalidate dirtyReleaseMessage.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 439:15] invalidate dirtyReleaseMessage.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 439:15] invalidate dirtyReleaseMessage.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 439:15] invalidate dirtyReleaseMessage.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 439:15] invalidate dirtyReleaseMessage.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 439:15] invalidate dirtyReleaseMessage.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 439:15] invalidate dirtyReleaseMessage.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 439:15] connect dirtyReleaseMessage.data, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 441:15] connect dirtyReleaseMessage.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 442:15] node _tl_out_c_valid_T = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 808:48] node _tl_out_c_valid_T_1 = eq(release_state, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 808:91] node _tl_out_c_valid_T_2 = and(_tl_out_c_valid_T, _tl_out_c_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 808:74] node _tl_out_c_valid_T_3 = or(s2_release_data_valid, _tl_out_c_valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 808:44] node _tl_out_c_valid_T_4 = and(c_first, release_ack_wait) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 808:130] node _tl_out_c_valid_T_5 = eq(_tl_out_c_valid_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 808:120] node _tl_out_c_valid_T_6 = and(_tl_out_c_valid_T_3, _tl_out_c_valid_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 808:117] connect tl_out_c.valid, _tl_out_c_valid_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 808:18] connect tl_out_c.bits, nackResponseMessage @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 809:17] wire newCoh : { state : UInt<2>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 810:27] connect newCoh, probeNewCoh @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 810:27] connect releaseWay, s2_probe_way @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 811:14] connect tl_out_c.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 889:19] connect tl_out_c.bits.user.amba_prot.secure, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 890:19] connect tl_out_c.bits.user.amba_prot.privileged, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 891:19] connect tl_out_c.bits.user.amba_prot.bufferable, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 892:19] connect tl_out_c.bits.user.amba_prot.modifiable, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 893:19] connect tl_out_c.bits.user.amba_prot.readalloc, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 894:19] connect tl_out_c.bits.user.amba_prot.writealloc, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 895:19] node _dataArb_io_in_2_valid_T = lt(releaseDataBeat, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 898:60] node _dataArb_io_in_2_valid_T_1 = and(inWriteback, _dataArb_io_in_2_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 898:41] connect dataArb.io.in[2].valid, _dataArb_io_in_2_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 898:26] connect dataArb.io.in[2].bits.way_en, dataArb.io.in[1].bits.way_en @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 899:25] connect dataArb.io.in[2].bits.eccMask, dataArb.io.in[1].bits.eccMask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 899:25] connect dataArb.io.in[2].bits.wordMask, dataArb.io.in[1].bits.wordMask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 899:25] connect dataArb.io.in[2].bits.wdata, dataArb.io.in[1].bits.wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 899:25] connect dataArb.io.in[2].bits.write, dataArb.io.in[1].bits.write @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 899:25] connect dataArb.io.in[2].bits.addr, dataArb.io.in[1].bits.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 899:25] connect dataArb.io.in[2].bits.write, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 900:31] node _dataArb_io_in_2_bits_addr_T = bits(probe_bits.address, 19, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1198:47] node _dataArb_io_in_2_bits_addr_T_1 = shl(_dataArb_io_in_2_bits_addr_T, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 901:55] node _dataArb_io_in_2_bits_addr_T_2 = bits(releaseDataBeat, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 901:90] node _dataArb_io_in_2_bits_addr_T_3 = shl(_dataArb_io_in_2_bits_addr_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 901:117] node _dataArb_io_in_2_bits_addr_T_4 = or(_dataArb_io_in_2_bits_addr_T_1, _dataArb_io_in_2_bits_addr_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 901:72] connect dataArb.io.in[2].bits.addr, _dataArb_io_in_2_bits_addr_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 901:30] node _dataArb_io_in_2_bits_wordMask_T = not(UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 902:37] connect dataArb.io.in[2].bits.wordMask, _dataArb_io_in_2_bits_wordMask_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 902:34] node _dataArb_io_in_2_bits_eccMask_T = not(UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 903:36] connect dataArb.io.in[2].bits.eccMask, _dataArb_io_in_2_bits_eccMask_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 903:33] node _dataArb_io_in_2_bits_way_en_T = not(UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 904:35] connect dataArb.io.in[2].bits.way_en, _dataArb_io_in_2_bits_way_en_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 904:32] node _metaArb_io_in_4_valid_T = eq(release_state, UInt<4>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_4_valid_T_1 = eq(release_state, UInt<4>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _metaArb_io_in_4_valid_T_2 = or(_metaArb_io_in_4_valid_T, _metaArb_io_in_4_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] connect metaArb.io.in[4].valid, _metaArb_io_in_4_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 906:26] connect metaArb.io.in[4].bits.write, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 907:31] connect metaArb.io.in[4].bits.way_en, releaseWay @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 908:32] node _metaArb_io_in_4_bits_idx_T = bits(probe_bits.address, 19, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1198:47] connect metaArb.io.in[4].bits.idx, _metaArb_io_in_4_bits_idx_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 909:29] node _metaArb_io_in_4_bits_addr_T = shr(io.cpu.req.bits.addr, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 910:58] node _metaArb_io_in_4_bits_addr_T_1 = bits(probe_bits.address, 19, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 910:90] node _metaArb_io_in_4_bits_addr_T_2 = cat(_metaArb_io_in_4_bits_addr_T, _metaArb_io_in_4_bits_addr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 910:36] connect metaArb.io.in[4].bits.addr, _metaArb_io_in_4_bits_addr_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 910:30] node _metaArb_io_in_4_bits_data_T = shr(tl_out_c.bits.address, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 911:78] wire metaArb_io_in_4_bits_data_meta : { coh : { state : UInt<2>}, tag : UInt<12>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 305:20] connect metaArb_io_in_4_bits_data_meta.tag, _metaArb_io_in_4_bits_data_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 306:14] connect metaArb_io_in_4_bits_data_meta.coh, newCoh @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 307:14] node _metaArb_io_in_4_bits_data_T_1 = cat(metaArb_io_in_4_bits_data_meta.coh.state, metaArb_io_in_4_bits_data_meta.tag) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 911:97] connect metaArb.io.in[4].bits.data, _metaArb_io_in_4_bits_data_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 911:30] node _T_109 = and(metaArb.io.in[4].ready, metaArb.io.in[4].valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_109 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 912:32] connect release_state, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 912:48] connect io.cpu.resp.bits.mask, s2_req.mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 915:37] connect io.cpu.resp.bits.data, s2_req.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 915:37] connect io.cpu.resp.bits.dv, s2_req.dv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 915:37] connect io.cpu.resp.bits.dprv, s2_req.dprv @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 915:37] connect io.cpu.resp.bits.signed, s2_req.signed @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 915:37] connect io.cpu.resp.bits.size, s2_req.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 915:37] connect io.cpu.resp.bits.cmd, s2_req.cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 915:37] connect io.cpu.resp.bits.tag, s2_req.tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 915:37] connect io.cpu.resp.bits.addr, s2_req.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 915:37] connect io.cpu.resp.bits.has_data, s2_read @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 916:29] connect io.cpu.resp.bits.replay, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 917:27] node _io_cpu_s2_uncached_T = eq(s2_hit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 918:40] node _io_cpu_s2_uncached_T_1 = and(s2_uncached, _io_cpu_s2_uncached_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 918:37] connect io.cpu.s2_uncached, _io_cpu_s2_uncached_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 918:22] connect io.cpu.s2_paddr, s2_req.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 919:19] connect io.cpu.s2_gpa, s2_tlb_xcpt.gpa @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 920:17] connect io.cpu.s2_gpa_is_pte, s2_tlb_xcpt.gpa_is_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 921:24] node _io_cpu_ordered_T = eq(s1_req.no_xcpt, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 927:35] node _io_cpu_ordered_T_1 = and(s1_valid, _io_cpu_ordered_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 927:32] node _io_cpu_ordered_T_2 = eq(s2_req.no_xcpt, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 927:72] node _io_cpu_ordered_T_3 = and(s2_valid, _io_cpu_ordered_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 927:69] node _io_cpu_ordered_T_4 = or(_io_cpu_ordered_T_1, _io_cpu_ordered_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 927:57] node _io_cpu_ordered_T_5 = or(_io_cpu_ordered_T_4, cached_grant_wait) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 927:94] node _io_cpu_ordered_T_6 = orr(uncachedInFlight[0]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 927:142] node _io_cpu_ordered_T_7 = or(_io_cpu_ordered_T_5, _io_cpu_ordered_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 927:115] node _io_cpu_ordered_T_8 = eq(_io_cpu_ordered_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 927:21] connect io.cpu.ordered, _io_cpu_ordered_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 927:18] node _io_cpu_store_pending_T = eq(s2_req.cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:32] node _io_cpu_store_pending_T_1 = eq(s2_req.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:49] node _io_cpu_store_pending_T_2 = or(_io_cpu_store_pending_T, _io_cpu_store_pending_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:42] node _io_cpu_store_pending_T_3 = eq(s2_req.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:66] node _io_cpu_store_pending_T_4 = or(_io_cpu_store_pending_T_2, _io_cpu_store_pending_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:59] node _io_cpu_store_pending_T_5 = eq(s2_req.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_store_pending_T_6 = eq(s2_req.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_store_pending_T_7 = eq(s2_req.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_store_pending_T_8 = eq(s2_req.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_store_pending_T_9 = or(_io_cpu_store_pending_T_5, _io_cpu_store_pending_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_store_pending_T_10 = or(_io_cpu_store_pending_T_9, _io_cpu_store_pending_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_store_pending_T_11 = or(_io_cpu_store_pending_T_10, _io_cpu_store_pending_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_store_pending_T_12 = eq(s2_req.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_store_pending_T_13 = eq(s2_req.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_store_pending_T_14 = eq(s2_req.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_store_pending_T_15 = eq(s2_req.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_store_pending_T_16 = eq(s2_req.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_store_pending_T_17 = or(_io_cpu_store_pending_T_12, _io_cpu_store_pending_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_store_pending_T_18 = or(_io_cpu_store_pending_T_17, _io_cpu_store_pending_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_store_pending_T_19 = or(_io_cpu_store_pending_T_18, _io_cpu_store_pending_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_store_pending_T_20 = or(_io_cpu_store_pending_T_19, _io_cpu_store_pending_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_store_pending_T_21 = or(_io_cpu_store_pending_T_11, _io_cpu_store_pending_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node _io_cpu_store_pending_T_22 = or(_io_cpu_store_pending_T_4, _io_cpu_store_pending_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:76] node _io_cpu_store_pending_T_23 = and(cached_grant_wait, _io_cpu_store_pending_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 928:46] node _io_cpu_store_pending_T_24 = orr(uncachedInFlight[0]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 928:97] node _io_cpu_store_pending_T_25 = or(_io_cpu_store_pending_T_23, _io_cpu_store_pending_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 928:70] connect io.cpu.store_pending, _io_cpu_store_pending_T_25 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 928:24] node _s1_xcpt_valid_T = eq(s1_req.no_xcpt, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 930:43] node _s1_xcpt_valid_T_1 = and(tlb.io.req.valid, _s1_xcpt_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 930:40] node _s1_xcpt_valid_T_2 = eq(s1_nack, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 930:68] node s1_xcpt_valid = and(_s1_xcpt_valid_T_1, _s1_xcpt_valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 930:65] reg io_cpu_s2_xcpt_REG : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:32] connect io_cpu_s2_xcpt_REG, s1_xcpt_valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:32] wire _io_cpu_s2_xcpt_WIRE : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<34>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.cmd, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.prefetchable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.must_alloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.cacheable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.ma.inst, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.ma.st, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.ma.ld, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.ae.inst, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.ae.st, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.ae.ld, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.gf.inst, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.gf.st, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.gf.ld, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.pf.inst, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.pf.st, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.pf.ld, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.gpa_is_pte, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.gpa, UInt<34>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.paddr, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] connect _io_cpu_s2_xcpt_WIRE.miss, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:74] node _io_cpu_s2_xcpt_T = mux(io_cpu_s2_xcpt_REG, s2_tlb_xcpt, _io_cpu_s2_xcpt_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:24] connect io.cpu.s2_xcpt.ae.st, _io_cpu_s2_xcpt_T.ae.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:18] connect io.cpu.s2_xcpt.ae.ld, _io_cpu_s2_xcpt_T.ae.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:18] connect io.cpu.s2_xcpt.gf.st, _io_cpu_s2_xcpt_T.gf.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:18] connect io.cpu.s2_xcpt.gf.ld, _io_cpu_s2_xcpt_T.gf.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:18] connect io.cpu.s2_xcpt.pf.st, _io_cpu_s2_xcpt_T.pf.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:18] connect io.cpu.s2_xcpt.pf.ld, _io_cpu_s2_xcpt_T.pf.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:18] connect io.cpu.s2_xcpt.ma.st, _io_cpu_s2_xcpt_T.ma.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:18] connect io.cpu.s2_xcpt.ma.ld, _io_cpu_s2_xcpt_T.ma.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 931:18] node _T_110 = eq(s2_req.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_111 = eq(s2_req.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_112 = or(_T_110, _T_111) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_113 = and(s2_valid_masked, _T_112) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 934:30] node _T_114 = eq(_T_113, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 934:12] node _T_115 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 934:11] node _T_116 = eq(_T_115, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 934:11] when _T_116 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 934:11] node _T_117 = eq(_T_114, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 934:11] when _T_117 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 934:11] printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:934 assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC)))\n") : printf_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 934:11] assert(clock, _T_114, UInt<1>(0h1), "") : assert_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 934:11] node s1_uncached_data_word = bits(nodeOut.d.bits.data, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 212:50] reg s2_uncached_data_word : UInt<64>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 945:40] when io.cpu.replay_next : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 945:40] connect s2_uncached_data_word, s1_uncached_data_word @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 945:40] reg doUncachedResp : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 946:31] connect doUncachedResp, io.cpu.replay_next @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 946:31] node _io_cpu_resp_valid_T = or(s2_valid_hit_pre_data_ecc, doUncachedResp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 947:51] node _io_cpu_resp_valid_T_1 = eq(s2_data_error, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 947:73] node _io_cpu_resp_valid_T_2 = and(_io_cpu_resp_valid_T, _io_cpu_resp_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 947:70] connect io.cpu.resp.valid, _io_cpu_resp_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 947:21] node _io_cpu_replay_next_T = and(nodeOut.d.ready, nodeOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _io_cpu_replay_next_T_1 = and(_io_cpu_replay_next_T, grantIsUncachedData) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 948:39] node _io_cpu_replay_next_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 948:65] node _io_cpu_replay_next_T_3 = and(_io_cpu_replay_next_T_1, _io_cpu_replay_next_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 948:62] connect io.cpu.replay_next, _io_cpu_replay_next_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 948:22] when doUncachedResp : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 949:25] node _T_118 = eq(s2_valid_hit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 950:12] node _T_119 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 950:11] node _T_120 = eq(_T_119, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 950:11] when _T_120 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 950:11] node _T_121 = eq(_T_118, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 950:11] when _T_121 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 950:11] printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:950 assert(!s2_valid_hit)\n") : printf_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 950:11] assert(clock, _T_118, UInt<1>(0h1), "") : assert_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 950:11] connect io.cpu.resp.bits.replay, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 951:29] connect io.cpu.resp.bits.addr, s2_uncached_resp_addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 952:27] node s2_data_word = bits(s2_data_uncorrected, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 968:80] node s2_data_word_corrected = bits(s2_data_corrected, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 969:88] node _s2_data_word_possibly_uncached_T = and(UInt<1>(0h0), doUncachedResp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 970:73] node _s2_data_word_possibly_uncached_T_1 = mux(_s2_data_word_possibly_uncached_T, s2_uncached_data_word, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 970:43] node s2_data_word_possibly_uncached = or(_s2_data_word_possibly_uncached_T_1, s2_data_word) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 970:120] wire size : UInt<2> @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 11:18] connect size, s2_req.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 12:8] node _io_cpu_resp_bits_data_shifted_T = bits(s2_req.addr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 42:29] node _io_cpu_resp_bits_data_shifted_T_1 = bits(s2_data_word_possibly_uncached, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 42:37] node _io_cpu_resp_bits_data_shifted_T_2 = bits(s2_data_word_possibly_uncached, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 42:55] node io_cpu_resp_bits_data_shifted = mux(_io_cpu_resp_bits_data_shifted_T, _io_cpu_resp_bits_data_shifted_T_1, _io_cpu_resp_bits_data_shifted_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 42:24] node io_cpu_resp_bits_data_doZero = and(UInt<1>(0h0), s2_sc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 43:31] node io_cpu_resp_bits_data_zeroed = mux(io_cpu_resp_bits_data_doZero, UInt<1>(0h0), io_cpu_resp_bits_data_shifted) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 44:23] node _io_cpu_resp_bits_data_T = eq(size, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:26] node _io_cpu_resp_bits_data_T_1 = or(_io_cpu_resp_bits_data_T, io_cpu_resp_bits_data_doZero) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:34] node _io_cpu_resp_bits_data_T_2 = bits(io_cpu_resp_bits_data_zeroed, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:81] node _io_cpu_resp_bits_data_T_3 = and(s2_req.signed, _io_cpu_resp_bits_data_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:72] node _io_cpu_resp_bits_data_T_4 = mux(_io_cpu_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:49] node _io_cpu_resp_bits_data_T_5 = bits(s2_data_word_possibly_uncached, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:94] node _io_cpu_resp_bits_data_T_6 = mux(_io_cpu_resp_bits_data_T_1, _io_cpu_resp_bits_data_T_4, _io_cpu_resp_bits_data_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:20] node _io_cpu_resp_bits_data_T_7 = cat(_io_cpu_resp_bits_data_T_6, io_cpu_resp_bits_data_zeroed) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:16] node _io_cpu_resp_bits_data_shifted_T_3 = bits(s2_req.addr, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 42:29] node _io_cpu_resp_bits_data_shifted_T_4 = bits(_io_cpu_resp_bits_data_T_7, 31, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 42:37] node _io_cpu_resp_bits_data_shifted_T_5 = bits(_io_cpu_resp_bits_data_T_7, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 42:55] node io_cpu_resp_bits_data_shifted_1 = mux(_io_cpu_resp_bits_data_shifted_T_3, _io_cpu_resp_bits_data_shifted_T_4, _io_cpu_resp_bits_data_shifted_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 42:24] node io_cpu_resp_bits_data_doZero_1 = and(UInt<1>(0h0), s2_sc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 43:31] node io_cpu_resp_bits_data_zeroed_1 = mux(io_cpu_resp_bits_data_doZero_1, UInt<1>(0h0), io_cpu_resp_bits_data_shifted_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 44:23] node _io_cpu_resp_bits_data_T_8 = eq(size, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:26] node _io_cpu_resp_bits_data_T_9 = or(_io_cpu_resp_bits_data_T_8, io_cpu_resp_bits_data_doZero_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:34] node _io_cpu_resp_bits_data_T_10 = bits(io_cpu_resp_bits_data_zeroed_1, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:81] node _io_cpu_resp_bits_data_T_11 = and(s2_req.signed, _io_cpu_resp_bits_data_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:72] node _io_cpu_resp_bits_data_T_12 = mux(_io_cpu_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:49] node _io_cpu_resp_bits_data_T_13 = bits(_io_cpu_resp_bits_data_T_7, 63, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:94] node _io_cpu_resp_bits_data_T_14 = mux(_io_cpu_resp_bits_data_T_9, _io_cpu_resp_bits_data_T_12, _io_cpu_resp_bits_data_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:20] node _io_cpu_resp_bits_data_T_15 = cat(_io_cpu_resp_bits_data_T_14, io_cpu_resp_bits_data_zeroed_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:16] node _io_cpu_resp_bits_data_shifted_T_6 = bits(s2_req.addr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 42:29] node _io_cpu_resp_bits_data_shifted_T_7 = bits(_io_cpu_resp_bits_data_T_15, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 42:37] node _io_cpu_resp_bits_data_shifted_T_8 = bits(_io_cpu_resp_bits_data_T_15, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 42:55] node io_cpu_resp_bits_data_shifted_2 = mux(_io_cpu_resp_bits_data_shifted_T_6, _io_cpu_resp_bits_data_shifted_T_7, _io_cpu_resp_bits_data_shifted_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 42:24] node io_cpu_resp_bits_data_doZero_2 = and(UInt<1>(0h1), s2_sc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 43:31] node io_cpu_resp_bits_data_zeroed_2 = mux(io_cpu_resp_bits_data_doZero_2, UInt<1>(0h0), io_cpu_resp_bits_data_shifted_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 44:23] node _io_cpu_resp_bits_data_T_16 = eq(size, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:26] node _io_cpu_resp_bits_data_T_17 = or(_io_cpu_resp_bits_data_T_16, io_cpu_resp_bits_data_doZero_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:34] node _io_cpu_resp_bits_data_T_18 = bits(io_cpu_resp_bits_data_zeroed_2, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:81] node _io_cpu_resp_bits_data_T_19 = and(s2_req.signed, _io_cpu_resp_bits_data_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:72] node _io_cpu_resp_bits_data_T_20 = mux(_io_cpu_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:49] node _io_cpu_resp_bits_data_T_21 = bits(_io_cpu_resp_bits_data_T_15, 63, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:94] node _io_cpu_resp_bits_data_T_22 = mux(_io_cpu_resp_bits_data_T_17, _io_cpu_resp_bits_data_T_20, _io_cpu_resp_bits_data_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:20] node _io_cpu_resp_bits_data_T_23 = cat(_io_cpu_resp_bits_data_T_22, io_cpu_resp_bits_data_zeroed_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:16] node _io_cpu_resp_bits_data_T_24 = or(_io_cpu_resp_bits_data_T_23, s2_sc_fail) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 972:41] connect io.cpu.resp.bits.data, _io_cpu_resp_bits_data_T_24 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 972:25] node _io_cpu_resp_bits_data_word_bypass_shifted_T = bits(s2_req.addr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 42:29] node _io_cpu_resp_bits_data_word_bypass_shifted_T_1 = bits(s2_data_word_possibly_uncached, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 42:37] node _io_cpu_resp_bits_data_word_bypass_shifted_T_2 = bits(s2_data_word_possibly_uncached, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 42:55] node io_cpu_resp_bits_data_word_bypass_shifted = mux(_io_cpu_resp_bits_data_word_bypass_shifted_T, _io_cpu_resp_bits_data_word_bypass_shifted_T_1, _io_cpu_resp_bits_data_word_bypass_shifted_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 42:24] node io_cpu_resp_bits_data_word_bypass_doZero = and(UInt<1>(0h0), s2_sc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 43:31] node io_cpu_resp_bits_data_word_bypass_zeroed = mux(io_cpu_resp_bits_data_word_bypass_doZero, UInt<1>(0h0), io_cpu_resp_bits_data_word_bypass_shifted) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 44:23] node _io_cpu_resp_bits_data_word_bypass_T = eq(size, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:26] node _io_cpu_resp_bits_data_word_bypass_T_1 = or(_io_cpu_resp_bits_data_word_bypass_T, io_cpu_resp_bits_data_word_bypass_doZero) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:34] node _io_cpu_resp_bits_data_word_bypass_T_2 = bits(io_cpu_resp_bits_data_word_bypass_zeroed, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:81] node _io_cpu_resp_bits_data_word_bypass_T_3 = and(s2_req.signed, _io_cpu_resp_bits_data_word_bypass_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:72] node _io_cpu_resp_bits_data_word_bypass_T_4 = mux(_io_cpu_resp_bits_data_word_bypass_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:49] node _io_cpu_resp_bits_data_word_bypass_T_5 = bits(s2_data_word_possibly_uncached, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:94] node _io_cpu_resp_bits_data_word_bypass_T_6 = mux(_io_cpu_resp_bits_data_word_bypass_T_1, _io_cpu_resp_bits_data_word_bypass_T_4, _io_cpu_resp_bits_data_word_bypass_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:20] node _io_cpu_resp_bits_data_word_bypass_T_7 = cat(_io_cpu_resp_bits_data_word_bypass_T_6, io_cpu_resp_bits_data_word_bypass_zeroed) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 45:16] connect io.cpu.resp.bits.data_word_bypass, _io_cpu_resp_bits_data_word_bypass_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 973:37] connect io.cpu.resp.bits.data_raw, s2_data_word @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 974:29] connect io.cpu.resp.bits.store_data, pstore1_data @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 975:31] inst amoalus_0 of AMOALU @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 980:26] connect amoalus_0.clock, clock connect amoalus_0.reset, reset node _amoalu_io_mask_T = shr(pstore1_mask, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 981:38] connect amoalus_0.io.mask, _amoalu_io_mask_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 981:22] connect amoalus_0.io.cmd, pstore1_cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 982:21] node _amoalu_io_lhs_T = shr(s2_data_word, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 983:37] connect amoalus_0.io.lhs, _amoalu_io_lhs_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 983:21] node _amoalu_io_rhs_T = shr(pstore1_data, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 984:37] connect amoalus_0.io.rhs, _amoalu_io_rhs_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 984:21] node _pstore1_storegen_data_mask_T = mux(s2_correct, UInt<1>(0h0), pstore1_mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:40] node _pstore1_storegen_data_mask_T_1 = bits(_pstore1_storegen_data_mask_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node _pstore1_storegen_data_mask_T_2 = bits(_pstore1_storegen_data_mask_T, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node _pstore1_storegen_data_mask_T_3 = bits(_pstore1_storegen_data_mask_T, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node _pstore1_storegen_data_mask_T_4 = bits(_pstore1_storegen_data_mask_T, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node _pstore1_storegen_data_mask_T_5 = bits(_pstore1_storegen_data_mask_T, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node _pstore1_storegen_data_mask_T_6 = bits(_pstore1_storegen_data_mask_T, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node _pstore1_storegen_data_mask_T_7 = bits(_pstore1_storegen_data_mask_T, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node _pstore1_storegen_data_mask_T_8 = bits(_pstore1_storegen_data_mask_T, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node _pstore1_storegen_data_mask_T_9 = mux(_pstore1_storegen_data_mask_T_1, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node _pstore1_storegen_data_mask_T_10 = mux(_pstore1_storegen_data_mask_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node _pstore1_storegen_data_mask_T_11 = mux(_pstore1_storegen_data_mask_T_3, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node _pstore1_storegen_data_mask_T_12 = mux(_pstore1_storegen_data_mask_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node _pstore1_storegen_data_mask_T_13 = mux(_pstore1_storegen_data_mask_T_5, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node _pstore1_storegen_data_mask_T_14 = mux(_pstore1_storegen_data_mask_T_6, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node _pstore1_storegen_data_mask_T_15 = mux(_pstore1_storegen_data_mask_T_7, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node _pstore1_storegen_data_mask_T_16 = mux(_pstore1_storegen_data_mask_T_8, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node pstore1_storegen_data_mask_lo_lo = cat(_pstore1_storegen_data_mask_T_10, _pstore1_storegen_data_mask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node pstore1_storegen_data_mask_lo_hi = cat(_pstore1_storegen_data_mask_T_12, _pstore1_storegen_data_mask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node pstore1_storegen_data_mask_lo = cat(pstore1_storegen_data_mask_lo_hi, pstore1_storegen_data_mask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node pstore1_storegen_data_mask_hi_lo = cat(_pstore1_storegen_data_mask_T_14, _pstore1_storegen_data_mask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node pstore1_storegen_data_mask_hi_hi = cat(_pstore1_storegen_data_mask_T_16, _pstore1_storegen_data_mask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node pstore1_storegen_data_mask_hi = cat(pstore1_storegen_data_mask_hi_hi, pstore1_storegen_data_mask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node pstore1_storegen_data_mask = cat(pstore1_storegen_data_mask_hi, pstore1_storegen_data_mask_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 988:33] node _pstore1_storegen_data_T = and(amoalus_0.io.out_unmasked, pstore1_storegen_data_mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 989:45] node _pstore1_storegen_data_T_1 = not(pstore1_storegen_data_mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 989:79] node _pstore1_storegen_data_T_2 = and(s2_data_word_corrected, _pstore1_storegen_data_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 989:77] node _pstore1_storegen_data_T_3 = or(_pstore1_storegen_data_T, _pstore1_storegen_data_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 989:52] connect pstore1_storegen_data, _pstore1_storegen_data_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 987:27] node flushCounterNext = add(flushCounter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1007:39] node _flushDone_T = shr(flushCounterNext, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1008:37] node flushDone = eq(_flushDone_T, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1008:57] node flushCounterWrap = bits(flushCounterNext, 13, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1009:42] node _T_122 = and(s2_valid_masked, s2_cmd_flush_all) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1010:26] node _T_123 = and(_T_122, s2_meta_error) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1010:46] node _T_124 = and(s2_valid_masked, s2_cmd_flush_all) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1011:26] node _T_125 = and(_T_124, s2_data_error) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1011:46] node _s1_flush_valid_T = and(metaArb.io.in[5].ready, metaArb.io.in[5].valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _s1_flush_valid_T_1 = eq(s1_flush_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1012:46] node _s1_flush_valid_T_2 = and(_s1_flush_valid_T, _s1_flush_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1012:43] node _s1_flush_valid_T_3 = eq(s2_flush_valid_pre_tag_ecc, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1012:65] node _s1_flush_valid_T_4 = and(_s1_flush_valid_T_2, _s1_flush_valid_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1012:62] node _s1_flush_valid_T_5 = eq(release_state, UInt<4>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1012:110] node _s1_flush_valid_T_6 = and(_s1_flush_valid_T_4, _s1_flush_valid_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1012:93] node _s1_flush_valid_T_7 = eq(release_ack_wait, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1012:125] node _s1_flush_valid_T_8 = and(_s1_flush_valid_T_6, _s1_flush_valid_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1012:122] connect s1_flush_valid, _s1_flush_valid_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1012:18] node _metaArb_io_in_5_valid_T = eq(flushed, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1013:41] node _metaArb_io_in_5_valid_T_1 = and(flushing, _metaArb_io_in_5_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1013:38] connect metaArb.io.in[5].valid, _metaArb_io_in_5_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1013:26] connect metaArb.io.in[5].bits.write, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1014:31] node _metaArb_io_in_5_bits_idx_T = bits(flushCounter, 13, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1015:44] connect metaArb.io.in[5].bits.idx, _metaArb_io_in_5_bits_idx_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1015:29] node _metaArb_io_in_5_bits_addr_T = shr(io.cpu.req.bits.addr, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1016:58] node _metaArb_io_in_5_bits_addr_T_1 = shl(metaArb.io.in[5].bits.idx, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1016:98] node _metaArb_io_in_5_bits_addr_T_2 = cat(_metaArb_io_in_5_bits_addr_T, _metaArb_io_in_5_bits_addr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1016:36] connect metaArb.io.in[5].bits.addr, _metaArb_io_in_5_bits_addr_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1016:30] connect metaArb.io.in[5].bits.way_en, metaArb.io.in[4].bits.way_en @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1017:32] connect metaArb.io.in[5].bits.data, metaArb.io.in[4].bits.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1018:30] connect metaArb.io.in[0].valid, resetting @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1044:26] connect metaArb.io.in[0].bits.data, metaArb.io.in[5].bits.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1045:25] connect metaArb.io.in[0].bits.way_en, metaArb.io.in[5].bits.way_en @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1045:25] connect metaArb.io.in[0].bits.idx, metaArb.io.in[5].bits.idx @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1045:25] connect metaArb.io.in[0].bits.addr, metaArb.io.in[5].bits.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1045:25] connect metaArb.io.in[0].bits.write, metaArb.io.in[5].bits.write @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1045:25] connect metaArb.io.in[0].bits.write, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1046:31] node _metaArb_io_in_0_bits_way_en_T = not(UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1047:35] connect metaArb.io.in[0].bits.way_en, _metaArb_io_in_0_bits_way_en_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1047:32] wire metaArb_io_in_0_bits_data_meta : { state : UInt<2>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 160:20] connect metaArb_io_in_0_bits_data_meta.state, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Metadata.scala 161:16] wire metaArb_io_in_0_bits_data_meta_1 : { coh : { state : UInt<2>}, tag : UInt<12>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 305:20] connect metaArb_io_in_0_bits_data_meta_1.tag, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 306:14] connect metaArb_io_in_0_bits_data_meta_1.coh, metaArb_io_in_0_bits_data_meta @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 307:14] node _metaArb_io_in_0_bits_data_T = cat(metaArb_io_in_0_bits_data_meta_1.coh.state, metaArb_io_in_0_bits_data_meta_1.tag) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1048:85] connect metaArb.io.in[0].bits.data, _metaArb_io_in_0_bits_data_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1048:30] when resetting : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1049:20] connect flushCounter, flushCounterNext @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1050:18] when flushDone : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1051:22] connect resetting, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1052:17] node _clock_en_reg_T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1058:19] node _clock_en_reg_T_1 = bits(io.ptw.customCSRs.csrs[0].value, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/CustomCSRs.scala 43:61] node _clock_en_reg_T_2 = or(_clock_en_reg_T, _clock_en_reg_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1058:44] node _clock_en_reg_T_3 = or(_clock_en_reg_T_2, io.cpu.keep_clock_enabled) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1059:46] node _clock_en_reg_T_4 = or(_clock_en_reg_T_3, metaArb.io.out.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1060:31] node _clock_en_reg_T_5 = or(_clock_en_reg_T_4, s1_probe) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1061:26] node _clock_en_reg_T_6 = or(_clock_en_reg_T_5, s2_probe) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1062:14] node _clock_en_reg_T_7 = or(_clock_en_reg_T_6, s1_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1062:26] node _clock_en_reg_T_8 = or(_clock_en_reg_T_7, s2_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1063:14] node _clock_en_reg_T_9 = or(_clock_en_reg_T_8, io.tlb_port.req.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1063:26] node _clock_en_reg_T_10 = or(_clock_en_reg_T_9, s1_tlb_req_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1064:27] node _clock_en_reg_T_11 = or(_clock_en_reg_T_10, s2_tlb_req_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1065:22] node _clock_en_reg_T_12 = or(_clock_en_reg_T_11, pstore1_held) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1065:42] node _clock_en_reg_T_13 = or(_clock_en_reg_T_12, pstore2_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1066:18] node _clock_en_reg_T_14 = neq(release_state, UInt<4>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1067:19] node _clock_en_reg_T_15 = or(_clock_en_reg_T_13, _clock_en_reg_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1066:35] node _clock_en_reg_T_16 = or(_clock_en_reg_T_15, release_ack_wait) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1067:31] node _clock_en_reg_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1068:25] node _clock_en_reg_T_18 = or(_clock_en_reg_T_16, _clock_en_reg_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1068:22] node _clock_en_reg_T_19 = eq(tlb.io.req.ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1069:5] node _clock_en_reg_T_20 = or(_clock_en_reg_T_18, _clock_en_reg_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1068:46] node _clock_en_reg_T_21 = or(_clock_en_reg_T_20, cached_grant_wait) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1069:23] node _clock_en_reg_T_22 = orr(uncachedInFlight[0]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1070:50] node _clock_en_reg_T_23 = or(_clock_en_reg_T_21, _clock_en_reg_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1070:23] node _clock_en_reg_T_24 = gt(lrscCount, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1071:15] node _clock_en_reg_T_25 = or(_clock_en_reg_T_23, _clock_en_reg_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1070:54] node _clock_en_reg_T_26 = gt(blockProbeAfterGrantCount, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1071:50] node _clock_en_reg_T_27 = or(_clock_en_reg_T_25, _clock_en_reg_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1071:21] connect clock_en_reg, _clock_en_reg_T_27 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1058:16] node _io_cpu_perf_acquire_T = and(tl_out_a.ready, tl_out_a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _io_cpu_perf_acquire_beats1_decode_T = dshl(UInt<12>(0hfff), tl_out_a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _io_cpu_perf_acquire_beats1_decode_T_1 = bits(_io_cpu_perf_acquire_beats1_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _io_cpu_perf_acquire_beats1_decode_T_2 = not(_io_cpu_perf_acquire_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node io_cpu_perf_acquire_beats1_decode = shr(_io_cpu_perf_acquire_beats1_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _io_cpu_perf_acquire_beats1_opdata_T = bits(tl_out_a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node io_cpu_perf_acquire_beats1_opdata = eq(_io_cpu_perf_acquire_beats1_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node io_cpu_perf_acquire_beats1 = mux(io_cpu_perf_acquire_beats1_opdata, io_cpu_perf_acquire_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset io_cpu_perf_acquire_counter : UInt<9>, clock, reset, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _io_cpu_perf_acquire_counter1_T = sub(io_cpu_perf_acquire_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node io_cpu_perf_acquire_counter1 = tail(_io_cpu_perf_acquire_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node io_cpu_perf_acquire_first = eq(io_cpu_perf_acquire_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _io_cpu_perf_acquire_last_T = eq(io_cpu_perf_acquire_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _io_cpu_perf_acquire_last_T_1 = eq(io_cpu_perf_acquire_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node io_cpu_perf_acquire_last = or(_io_cpu_perf_acquire_last_T, _io_cpu_perf_acquire_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node io_cpu_perf_acquire_done = and(io_cpu_perf_acquire_last, _io_cpu_perf_acquire_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _io_cpu_perf_acquire_count_T = not(io_cpu_perf_acquire_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node io_cpu_perf_acquire_count = and(io_cpu_perf_acquire_beats1, _io_cpu_perf_acquire_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _io_cpu_perf_acquire_T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _io_cpu_perf_acquire_counter_T = mux(io_cpu_perf_acquire_first, io_cpu_perf_acquire_beats1, io_cpu_perf_acquire_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect io_cpu_perf_acquire_counter, _io_cpu_perf_acquire_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] connect io.cpu.perf.acquire, io_cpu_perf_acquire_done @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1074:23] node _io_cpu_perf_release_T = and(tl_out_c.ready, tl_out_c.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _io_cpu_perf_release_beats1_decode_T = dshl(UInt<12>(0hfff), tl_out_c.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _io_cpu_perf_release_beats1_decode_T_1 = bits(_io_cpu_perf_release_beats1_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _io_cpu_perf_release_beats1_decode_T_2 = not(_io_cpu_perf_release_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node io_cpu_perf_release_beats1_decode = shr(_io_cpu_perf_release_beats1_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node io_cpu_perf_release_beats1_opdata = bits(tl_out_c.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 102:36] node io_cpu_perf_release_beats1 = mux(UInt<1>(0h0), io_cpu_perf_release_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset io_cpu_perf_release_counter : UInt<9>, clock, reset, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _io_cpu_perf_release_counter1_T = sub(io_cpu_perf_release_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node io_cpu_perf_release_counter1 = tail(_io_cpu_perf_release_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node io_cpu_perf_release_first = eq(io_cpu_perf_release_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _io_cpu_perf_release_last_T = eq(io_cpu_perf_release_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _io_cpu_perf_release_last_T_1 = eq(io_cpu_perf_release_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node io_cpu_perf_release_last = or(_io_cpu_perf_release_last_T, _io_cpu_perf_release_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node io_cpu_perf_release_done = and(io_cpu_perf_release_last, _io_cpu_perf_release_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _io_cpu_perf_release_count_T = not(io_cpu_perf_release_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node io_cpu_perf_release_count = and(io_cpu_perf_release_beats1, _io_cpu_perf_release_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _io_cpu_perf_release_T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _io_cpu_perf_release_counter_T = mux(io_cpu_perf_release_first, io_cpu_perf_release_beats1, io_cpu_perf_release_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect io_cpu_perf_release_counter, _io_cpu_perf_release_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] connect io.cpu.perf.release, io_cpu_perf_release_done @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1075:23] node _io_cpu_perf_grant_T = and(nodeOut.d.valid, d_last) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1076:39] connect io.cpu.perf.grant, _io_cpu_perf_grant_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1076:21] node _io_cpu_perf_tlbMiss_T = and(io.ptw.req.ready, io.ptw.req.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] connect io.cpu.perf.tlbMiss, _io_cpu_perf_tlbMiss_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1077:23] node _io_cpu_perf_storeBufferEmptyAfterLoad_T = and(s1_valid, s1_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1079:15] node _io_cpu_perf_storeBufferEmptyAfterLoad_T_1 = and(s2_valid, s2_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1080:16] node _io_cpu_perf_storeBufferEmptyAfterLoad_T_2 = eq(s2_waw_hazard, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1080:31] node _io_cpu_perf_storeBufferEmptyAfterLoad_T_3 = and(_io_cpu_perf_storeBufferEmptyAfterLoad_T_1, _io_cpu_perf_storeBufferEmptyAfterLoad_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1080:28] node _io_cpu_perf_storeBufferEmptyAfterLoad_T_4 = or(_io_cpu_perf_storeBufferEmptyAfterLoad_T_3, pstore1_held) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1080:47] node _io_cpu_perf_storeBufferEmptyAfterLoad_T_5 = or(_io_cpu_perf_storeBufferEmptyAfterLoad_T, _io_cpu_perf_storeBufferEmptyAfterLoad_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1079:28] node _io_cpu_perf_storeBufferEmptyAfterLoad_T_6 = or(_io_cpu_perf_storeBufferEmptyAfterLoad_T_5, pstore2_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1080:64] node _io_cpu_perf_storeBufferEmptyAfterLoad_T_7 = eq(_io_cpu_perf_storeBufferEmptyAfterLoad_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1078:44] connect io.cpu.perf.storeBufferEmptyAfterLoad, _io_cpu_perf_storeBufferEmptyAfterLoad_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1078:41] node _io_cpu_perf_storeBufferEmptyAfterStore_T = and(s1_valid, s1_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1083:15] node _io_cpu_perf_storeBufferEmptyAfterStore_T_1 = and(s2_valid, s2_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1084:15] node _io_cpu_perf_storeBufferEmptyAfterStore_T_2 = and(_io_cpu_perf_storeBufferEmptyAfterStore_T_1, pstore1_rmw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1084:27] node _io_cpu_perf_storeBufferEmptyAfterStore_T_3 = or(_io_cpu_perf_storeBufferEmptyAfterStore_T, _io_cpu_perf_storeBufferEmptyAfterStore_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1083:28] node _io_cpu_perf_storeBufferEmptyAfterStore_T_4 = and(s2_valid, s2_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1085:16] node _io_cpu_perf_storeBufferEmptyAfterStore_T_5 = eq(s2_waw_hazard, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1085:31] node _io_cpu_perf_storeBufferEmptyAfterStore_T_6 = and(_io_cpu_perf_storeBufferEmptyAfterStore_T_4, _io_cpu_perf_storeBufferEmptyAfterStore_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1085:28] node _io_cpu_perf_storeBufferEmptyAfterStore_T_7 = or(_io_cpu_perf_storeBufferEmptyAfterStore_T_6, pstore1_held) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1085:46] node _io_cpu_perf_storeBufferEmptyAfterStore_T_8 = and(_io_cpu_perf_storeBufferEmptyAfterStore_T_7, pstore2_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1085:63] node _io_cpu_perf_storeBufferEmptyAfterStore_T_9 = or(_io_cpu_perf_storeBufferEmptyAfterStore_T_3, _io_cpu_perf_storeBufferEmptyAfterStore_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1084:43] node _io_cpu_perf_storeBufferEmptyAfterStore_T_10 = eq(_io_cpu_perf_storeBufferEmptyAfterStore_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1082:45] connect io.cpu.perf.storeBufferEmptyAfterStore, _io_cpu_perf_storeBufferEmptyAfterStore_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1082:42] node _io_cpu_perf_canAcceptStoreThenLoad_T = and(s2_valid, s2_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1087:16] node _io_cpu_perf_canAcceptStoreThenLoad_T_1 = and(_io_cpu_perf_canAcceptStoreThenLoad_T, pstore1_rmw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1087:28] node _io_cpu_perf_canAcceptStoreThenLoad_T_2 = and(s1_valid, s1_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1087:57] node _io_cpu_perf_canAcceptStoreThenLoad_T_3 = eq(s1_waw_hazard, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1087:72] node _io_cpu_perf_canAcceptStoreThenLoad_T_4 = and(_io_cpu_perf_canAcceptStoreThenLoad_T_2, _io_cpu_perf_canAcceptStoreThenLoad_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1087:69] node _io_cpu_perf_canAcceptStoreThenLoad_T_5 = and(_io_cpu_perf_canAcceptStoreThenLoad_T_1, _io_cpu_perf_canAcceptStoreThenLoad_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1087:44] node _io_cpu_perf_canAcceptStoreThenLoad_T_6 = and(pstore2_valid, pstore1_valid_likely) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1088:20] node _io_cpu_perf_canAcceptStoreThenLoad_T_7 = and(s1_valid, s1_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1088:57] node _io_cpu_perf_canAcceptStoreThenLoad_T_8 = and(_io_cpu_perf_canAcceptStoreThenLoad_T_6, _io_cpu_perf_canAcceptStoreThenLoad_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1088:44] node _io_cpu_perf_canAcceptStoreThenLoad_T_9 = or(_io_cpu_perf_canAcceptStoreThenLoad_T_5, _io_cpu_perf_canAcceptStoreThenLoad_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1087:89] node _io_cpu_perf_canAcceptStoreThenLoad_T_10 = eq(_io_cpu_perf_canAcceptStoreThenLoad_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1086:41] connect io.cpu.perf.canAcceptStoreThenLoad, _io_cpu_perf_canAcceptStoreThenLoad_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1086:38] node _io_cpu_perf_canAcceptStoreThenRMW_T = eq(pstore2_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1089:78] node _io_cpu_perf_canAcceptStoreThenRMW_T_1 = and(io.cpu.perf.canAcceptStoreThenLoad, _io_cpu_perf_canAcceptStoreThenRMW_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1089:75] connect io.cpu.perf.canAcceptStoreThenRMW, _io_cpu_perf_canAcceptStoreThenRMW_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1089:37] node _io_cpu_perf_canAcceptLoadThenLoad_T = and(s1_valid, s1_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1090:52] node _io_cpu_perf_canAcceptLoadThenLoad_T_1 = eq(s1_req.cmd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_2 = eq(s1_req.cmd, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_3 = eq(s1_req.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_4 = eq(s1_req.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_5 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_1, _io_cpu_perf_canAcceptLoadThenLoad_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_perf_canAcceptLoadThenLoad_T_6 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_5, _io_cpu_perf_canAcceptLoadThenLoad_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_perf_canAcceptLoadThenLoad_T_7 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_6, _io_cpu_perf_canAcceptLoadThenLoad_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_perf_canAcceptLoadThenLoad_T_8 = eq(s1_req.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_9 = eq(s1_req.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_10 = eq(s1_req.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_11 = eq(s1_req.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_12 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_8, _io_cpu_perf_canAcceptLoadThenLoad_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_perf_canAcceptLoadThenLoad_T_13 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_12, _io_cpu_perf_canAcceptLoadThenLoad_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_perf_canAcceptLoadThenLoad_T_14 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_13, _io_cpu_perf_canAcceptLoadThenLoad_T_11) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_perf_canAcceptLoadThenLoad_T_15 = eq(s1_req.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_16 = eq(s1_req.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_17 = eq(s1_req.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_18 = eq(s1_req.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_19 = eq(s1_req.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_20 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_15, _io_cpu_perf_canAcceptLoadThenLoad_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_perf_canAcceptLoadThenLoad_T_21 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_20, _io_cpu_perf_canAcceptLoadThenLoad_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_perf_canAcceptLoadThenLoad_T_22 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_21, _io_cpu_perf_canAcceptLoadThenLoad_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_perf_canAcceptLoadThenLoad_T_23 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_22, _io_cpu_perf_canAcceptLoadThenLoad_T_19) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_perf_canAcceptLoadThenLoad_T_24 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_14, _io_cpu_perf_canAcceptLoadThenLoad_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node _io_cpu_perf_canAcceptLoadThenLoad_T_25 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_7, _io_cpu_perf_canAcceptLoadThenLoad_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 89:68] node _io_cpu_perf_canAcceptLoadThenLoad_T_26 = eq(s1_req.cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:32] node _io_cpu_perf_canAcceptLoadThenLoad_T_27 = eq(s1_req.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:49] node _io_cpu_perf_canAcceptLoadThenLoad_T_28 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_26, _io_cpu_perf_canAcceptLoadThenLoad_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:42] node _io_cpu_perf_canAcceptLoadThenLoad_T_29 = eq(s1_req.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:66] node _io_cpu_perf_canAcceptLoadThenLoad_T_30 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_28, _io_cpu_perf_canAcceptLoadThenLoad_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:59] node _io_cpu_perf_canAcceptLoadThenLoad_T_31 = eq(s1_req.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_32 = eq(s1_req.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_33 = eq(s1_req.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_34 = eq(s1_req.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_35 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_31, _io_cpu_perf_canAcceptLoadThenLoad_T_32) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_perf_canAcceptLoadThenLoad_T_36 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_35, _io_cpu_perf_canAcceptLoadThenLoad_T_33) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_perf_canAcceptLoadThenLoad_T_37 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_36, _io_cpu_perf_canAcceptLoadThenLoad_T_34) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_perf_canAcceptLoadThenLoad_T_38 = eq(s1_req.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_39 = eq(s1_req.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_40 = eq(s1_req.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_41 = eq(s1_req.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_42 = eq(s1_req.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_cpu_perf_canAcceptLoadThenLoad_T_43 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_38, _io_cpu_perf_canAcceptLoadThenLoad_T_39) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_perf_canAcceptLoadThenLoad_T_44 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_43, _io_cpu_perf_canAcceptLoadThenLoad_T_40) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_perf_canAcceptLoadThenLoad_T_45 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_44, _io_cpu_perf_canAcceptLoadThenLoad_T_41) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_perf_canAcceptLoadThenLoad_T_46 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_45, _io_cpu_perf_canAcceptLoadThenLoad_T_42) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_cpu_perf_canAcceptLoadThenLoad_T_47 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_37, _io_cpu_perf_canAcceptLoadThenLoad_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node _io_cpu_perf_canAcceptLoadThenLoad_T_48 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_30, _io_cpu_perf_canAcceptLoadThenLoad_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:76] node _io_cpu_perf_canAcceptLoadThenLoad_T_49 = eq(s1_req.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:35] node _io_cpu_perf_canAcceptLoadThenLoad_T_50 = lt(s1_req.size, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:57] node _io_cpu_perf_canAcceptLoadThenLoad_T_51 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_49, _io_cpu_perf_canAcceptLoadThenLoad_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:45] node _io_cpu_perf_canAcceptLoadThenLoad_T_52 = and(_io_cpu_perf_canAcceptLoadThenLoad_T_48, _io_cpu_perf_canAcceptLoadThenLoad_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1189:23] node _io_cpu_perf_canAcceptLoadThenLoad_T_53 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_25, _io_cpu_perf_canAcceptLoadThenLoad_T_52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1188:21] node _io_cpu_perf_canAcceptLoadThenLoad_T_54 = and(_io_cpu_perf_canAcceptLoadThenLoad_T, _io_cpu_perf_canAcceptLoadThenLoad_T_53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1090:64] node _io_cpu_perf_canAcceptLoadThenLoad_T_55 = and(s2_valid, s2_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1090:100] node _io_cpu_perf_canAcceptLoadThenLoad_T_56 = eq(s2_waw_hazard, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1090:115] node _io_cpu_perf_canAcceptLoadThenLoad_T_57 = and(_io_cpu_perf_canAcceptLoadThenLoad_T_55, _io_cpu_perf_canAcceptLoadThenLoad_T_56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1090:112] node _io_cpu_perf_canAcceptLoadThenLoad_T_58 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_57, pstore1_held) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1090:130] node _io_cpu_perf_canAcceptLoadThenLoad_T_59 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_58, pstore2_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1090:147] node _io_cpu_perf_canAcceptLoadThenLoad_T_60 = and(_io_cpu_perf_canAcceptLoadThenLoad_T_54, _io_cpu_perf_canAcceptLoadThenLoad_T_59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1090:86] node _io_cpu_perf_canAcceptLoadThenLoad_T_61 = eq(_io_cpu_perf_canAcceptLoadThenLoad_T_60, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1090:40] connect io.cpu.perf.canAcceptLoadThenLoad, _io_cpu_perf_canAcceptLoadThenLoad_T_61 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1090:37] regreset io_cpu_perf_blocked_near_end_of_refill_refill_count : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1100:33] node _io_cpu_perf_blocked_near_end_of_refill_T = and(nodeOut.d.ready, nodeOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _io_cpu_perf_blocked_near_end_of_refill_T_1 = and(_io_cpu_perf_blocked_near_end_of_refill_T, grantIsRefill) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1101:27] when _io_cpu_perf_blocked_near_end_of_refill_T_1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1101:45] node _io_cpu_perf_blocked_near_end_of_refill_refill_count_T = add(io_cpu_perf_blocked_near_end_of_refill_refill_count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1101:76] node _io_cpu_perf_blocked_near_end_of_refill_refill_count_T_1 = tail(_io_cpu_perf_blocked_near_end_of_refill_refill_count_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1101:76] connect io_cpu_perf_blocked_near_end_of_refill_refill_count, _io_cpu_perf_blocked_near_end_of_refill_refill_count_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1101:60] node io_cpu_perf_blocked_near_end_of_refill = geq(io_cpu_perf_blocked_near_end_of_refill_refill_count, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1102:20] node _io_cpu_perf_blocked_T = eq(io_cpu_perf_blocked_near_end_of_refill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1104:26] node _io_cpu_perf_blocked_T_1 = and(cached_grant_wait, _io_cpu_perf_blocked_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1104:23] connect io.cpu.perf.blocked, _io_cpu_perf_blocked_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1091:23] node _error_addr_T = bits(metaArb.io.in[1].bits.addr, 19, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1116:94] node _error_addr_T_1 = cat(s2_meta_corrected_0.tag, _error_addr_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1116:38] node _error_addr_T_2 = shr(s2_req.addr, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1117:27] node _error_addr_T_3 = mux(metaArb.io.in[1].valid, _error_addr_T_1, _error_addr_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1116:10] node error_addr = shl(_error_addr_T_3, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1117:38] node _io_errors_bus_valid_T = and(nodeOut.d.ready, nodeOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _io_errors_bus_valid_T_1 = or(nodeOut.d.bits.denied, nodeOut.d.bits.corrupt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1127:67] node _io_errors_bus_valid_T_2 = and(_io_errors_bus_valid_T, _io_errors_bus_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1127:42] connect io.errors.bus.valid, _io_errors_bus_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1127:25] node _io_errors_bus_bits_T = shr(s2_req.addr, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1128:58] node _io_errors_bus_bits_T_1 = shl(_io_errors_bus_bits_T, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1128:68] node _io_errors_bus_bits_T_2 = mux(grantIsCached, _io_errors_bus_bits_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1128:30] connect io.errors.bus.bits, _io_errors_bus_bits_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1128:24] node _T_126 = and(io.errors.bus.valid, grantIsCached) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1130:45] node _T_127 = eq(grantIsCached, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1131:35] node _T_128 = and(io.errors.bus.valid, _T_127) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1131:32] node _T_129 = eq(s2_valid_data_error, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1136:29] node _T_130 = eq(s2_data_error_uncorrectable, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1137:43] node _T_131 = and(s2_valid_data_error, _T_130) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1137:40] node _T_132 = and(s2_valid_data_error, s2_data_error_uncorrectable) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1138:40] node _T_133 = eq(s2_req.no_xcpt, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/DCache.scala 1141:29] node _T_134 = and(_T_129, s2_req.no_xcpt) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_135 = and(_T_129, _T_133) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_136 = and(_T_131, s2_req.no_xcpt) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_137 = and(_T_131, _T_133) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_138 = and(_T_132, s2_req.no_xcpt) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_139 = and(_T_132, _T_133) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] module ICache : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 251:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 251:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 251:7] output auto : { master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<33>}}, flip s1_paddr : UInt<32>, flip s2_vaddr : UInt<33>, flip s1_kill : UInt<1>, flip s2_kill : UInt<1>, flip s2_cacheable : UInt<1>, flip s2_prefetch : UInt<1>, resp : { valid : UInt<1>, bits : { data : UInt<32>, replay : UInt<1>, ae : UInt<1>}}, flip invalidate : UInt<1>, errors : { bus : { valid : UInt<1>, bits : UInt<32>}}, perf : { acquire : UInt<1>}, flip clock_enabled : UInt<1>, keep_clock_enabled : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 256:14] wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate masterNodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate masterNodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.master_out, masterNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] regreset scratchpadOn : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 280:29] regreset s1_slaveValid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 331:30] connect s1_slaveValid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 331:30] regreset s2_slaveValid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 332:30] connect s2_slaveValid, s1_slaveValid @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 332:30] reg s3_slaveValid : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 333:30] connect s3_slaveValid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 333:30] node s0_valid = and(io.req.ready, io.req.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] regreset s1_valid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 341:25] reg s1_vaddr : UInt<33>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 343:27] when s0_valid : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 343:27] connect s1_vaddr, io.req.bits.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 343:27] wire s1_tag_hit : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 345:24] node _s1_hit_T = mux(s1_slaveValid, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 361:46] node s1_hit = or(s1_tag_hit[0], _s1_hit_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 361:40] node _s2_valid_T = eq(io.s1_kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 363:38] node _s2_valid_T_1 = and(s1_valid, _s2_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 363:35] regreset s2_valid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 363:25] connect s2_valid, _s2_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 363:25] reg s2_hit : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 364:23] connect s2_hit, s1_hit @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 364:23] reg invalidated : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 367:24] regreset refill_valid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 368:29] regreset send_hint : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 372:26] node _refill_fire_T = and(masterNodeOut.a.ready, masterNodeOut.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _refill_fire_T_1 = eq(send_hint, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 374:38] node refill_fire = and(_refill_fire_T, _refill_fire_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 374:35] regreset hint_outstanding : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 376:33] node _s2_miss_T = eq(s2_hit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 378:29] node _s2_miss_T_1 = and(s2_valid, _s2_miss_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 378:26] node _s2_miss_T_2 = eq(io.s2_kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 378:40] node s2_miss = and(_s2_miss_T_1, _s2_miss_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 378:37] node _s1_can_request_refill_T = or(s2_miss, refill_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 380:41] node s1_can_request_refill = eq(_s1_can_request_refill_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 380:31] reg s2_request_refill_REG : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 385:45] connect s2_request_refill_REG, s1_can_request_refill @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 385:45] node s2_request_refill = and(s2_miss, s2_request_refill_REG) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 385:35] node _refill_paddr_T = and(s1_valid, s1_can_request_refill) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 386:54] reg refill_paddr : UInt<32>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 386:31] when _refill_paddr_T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 386:31] connect refill_paddr, io.s1_paddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 386:31] node _refill_vaddr_T = and(s1_valid, s1_can_request_refill) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 387:51] reg refill_vaddr : UInt<33>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 387:31] when _refill_vaddr_T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 387:31] connect refill_vaddr, s1_vaddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 387:31] node refill_tag = shr(refill_paddr, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 388:33] node refill_idx = bits(refill_paddr, 11, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 859:21] node _refill_one_beat_T = and(masterNodeOut.d.ready, masterNodeOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node refill_one_beat_opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node refill_one_beat = and(_refill_one_beat_T, refill_one_beat_opdata) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 391:39] node _io_req_ready_T = or(refill_one_beat, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 394:37] node _io_req_ready_T_1 = or(_io_req_ready_T, s3_slaveValid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 394:54] node _io_req_ready_T_2 = eq(_io_req_ready_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 394:19] connect io.req.ready, _io_req_ready_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 394:16] connect s1_valid, s0_valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 395:12] node _T = and(masterNodeOut.d.ready, masterNodeOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _r_beats1_decode_T = dshl(UInt<12>(0hfff), masterNodeOut.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node r_beats1_decode = shr(_r_beats1_decode_T_2, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node r_beats1_opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node r_counter1 = tail(_r_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node r_1 = eq(r_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _r_last_T = eq(r_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node r_2 = or(_r_last_T, _r_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node d_done = and(r_2, _T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _r_count_T = not(r_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node refill_cnt = and(r_beats1, _r_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _r_counter_T = mux(r_1, r_beats1, r_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect r_counter, _r_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node refill_done = and(refill_one_beat, d_done) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 399:37] node _masterNodeOut_d_ready_T = eq(s3_slaveValid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 401:21] connect masterNodeOut.d.ready, _masterNodeOut_d_ready_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 401:18] smem rockettile_icache_tag_array : UInt<21>[1] [64] @[hardware/upstream/rocket-chip/src/main/scala/util/DescribedSRAM.scala 17:26] node _tag_rdata_T = bits(io.req.bits.addr, 11, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 426:42] node _tag_rdata_T_1 = eq(refill_done, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 426:70] node _tag_rdata_T_2 = and(_tag_rdata_T_1, s0_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 426:83] wire _tag_rdata_WIRE : UInt<6> @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 426:33] invalidate _tag_rdata_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 426:33] when _tag_rdata_T_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 426:33] connect _tag_rdata_WIRE, _tag_rdata_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 426:33] read mport tag_rdata = rockettile_icache_tag_array[_tag_rdata_WIRE], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 426:33] reg accruedRefillError : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 428:31] node _refillError_T = gt(refill_cnt, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 430:58] node _refillError_T_1 = and(_refillError_T, accruedRefillError) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 430:64] node refillError = or(masterNodeOut.d.bits.corrupt, _refillError_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 430:43] when refill_done : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 431:22] node enc_tag = cat(refillError, refill_tag) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 435:34] wire _WIRE : UInt<21>[1] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 436:40] connect _WIRE[0], enc_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 436:40] node _T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 436:97] write mport MPORT = rockettile_icache_tag_array[refill_idx], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 436:20] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 436:20] connect MPORT[0], _WIRE[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 436:20] node _io_errors_bus_valid_T = and(masterNodeOut.d.ready, masterNodeOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _io_errors_bus_valid_T_1 = or(masterNodeOut.d.bits.denied, masterNodeOut.d.bits.corrupt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 441:65] node _io_errors_bus_valid_T_2 = and(_io_errors_bus_valid_T, _io_errors_bus_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 441:40] connect io.errors.bus.valid, _io_errors_bus_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 441:23] node _io_errors_bus_bits_T = shr(refill_paddr, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 442:40] node _io_errors_bus_bits_T_1 = shl(_io_errors_bus_bits_T, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 442:57] connect io.errors.bus.bits, _io_errors_bus_bits_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 442:23] regreset vb_array : UInt<64>, clock, reset, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 448:25] when refill_one_beat : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 449:26] connect accruedRefillError, refillError @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 450:24] node _vb_array_T = cat(UInt<1>(0h0), refill_idx) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 452:36] node _vb_array_T_1 = eq(invalidated, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 452:75] node _vb_array_T_2 = and(refill_done, _vb_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 452:72] node _vb_array_T_3 = dshl(UInt<1>(0h1), _vb_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 452:32] node _vb_array_T_4 = or(vb_array, _vb_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 452:32] node _vb_array_T_5 = not(vb_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 452:32] node _vb_array_T_6 = or(_vb_array_T_5, _vb_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 452:32] node _vb_array_T_7 = not(_vb_array_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 452:32] node _vb_array_T_8 = mux(_vb_array_T_2, _vb_array_T_4, _vb_array_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 452:32] connect vb_array, _vb_array_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 452:14] wire invalidate : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 456:31] connect invalidate, io.invalidate @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 456:31] when invalidate : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 457:21] connect vb_array, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 458:14] connect invalidated, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 459:17] wire s1_tag_disparity : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 465:30] wire s1_tl_error : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 469:25] wire s1_dout : UInt<32>[1] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 473:21] invalidate s1_dout[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 474:11] reg s1s3_slaveAddr : UInt<12>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 483:27] reg s1s3_slaveData : UInt<32>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 489:27] node s1_idx = bits(io.s1_paddr, 11, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 859:21] node s1_tag = shr(io.s1_paddr, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 493:30] node _scratchpadHit_T = lt(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 316:43] node _scratchpadHit_T_1 = bits(s1s3_slaveAddr, 11, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 327:40] node _scratchpadHit_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 503:91] node _scratchpadHit_T_3 = and(UInt<1>(0h0), _scratchpadHit_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 503:58] node _scratchpadHit_T_4 = bits(io.s1_paddr, 11, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 302:90] node _scratchpadHit_T_5 = and(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 302:66] node _scratchpadHit_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 507:69] node _scratchpadHit_T_7 = and(_scratchpadHit_T_5, _scratchpadHit_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 507:39] node _scratchpadHit_T_8 = mux(s1_slaveValid, _scratchpadHit_T_3, _scratchpadHit_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 498:10] node scratchpadHit = and(_scratchpadHit_T, _scratchpadHit_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 497:49] node _s1_vb_T = cat(UInt<1>(0h0), s1_idx) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 508:29] node _s1_vb_T_1 = dshr(vb_array, _s1_vb_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 508:25] node _s1_vb_T_2 = bits(_s1_vb_T_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 508:25] node _s1_vb_T_3 = eq(s1_slaveValid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 508:74] node s1_vb = and(_s1_vb_T_2, _s1_vb_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 508:71] node tl_error = bits(tag_rdata[0], 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node tag = bits(tag_rdata[0], 19, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _tagMatch_T = eq(tag, s1_tag) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 514:33] node tagMatch = and(s1_vb, _tagMatch_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 514:26] node _s1_tag_disparity_0_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/ECC.scala 15:27] node _s1_tag_disparity_0_T_1 = and(s1_vb, _s1_tag_disparity_0_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 516:34] connect s1_tag_disparity[0], _s1_tag_disparity_0_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 516:25] node _s1_tl_error_0_T = bits(tl_error, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 518:44] node _s1_tl_error_0_T_1 = and(tagMatch, _s1_tl_error_0_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 518:32] connect s1_tl_error[0], _s1_tl_error_0_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 518:20] node _s1_tag_hit_0_T = or(tagMatch, scratchpadHit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 519:31] connect s1_tag_hit[0], _s1_tag_hit_0_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 519:19] node _T_2 = or(s1_valid, s1_slaveValid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 521:21] node _T_3 = eq(_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 521:10] node _T_4 = eq(s1_tag_disparity[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 521:109] node _T_5 = and(s1_tag_hit[0], _T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 521:106] node _T_6 = leq(_T_5, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 521:115] node _T_7 = or(_T_3, _T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 521:39] node _T_8 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 521:9] node _T_9 = eq(_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 521:9] when _T_9 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 521:9] node _T_10 = eq(_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 521:9] when _T_10 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 521:9] printf(clock, UInt<1>(0h1), "Assertion failed\n at ICache.scala:521 assert(!(s1_valid || s1_slaveValid) || PopCount(s1_tag_hit zip s1_tag_disparity map { case (h, d) => h && !d }) <= 1.U)\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 521:9] assert(clock, _T_7, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 521:9] smem rockettile_icache_data_arrays_0 : UInt<32>[1] [512] @[hardware/upstream/rocket-chip/src/main/scala/util/DescribedSRAM.scala 17:26] smem rockettile_icache_data_arrays_1 : UInt<32>[1] [512] @[hardware/upstream/rocket-chip/src/main/scala/util/DescribedSRAM.scala 17:26] node _s0_ren_T = bits(io.req.bits.addr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _s0_ren_T_1 = eq(_s0_ren_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 564:111] node _s0_ren_T_2 = and(s0_valid, _s0_ren_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 567:28] node _s0_ren_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 564:111] node _s0_ren_T_4 = and(UInt<1>(0h0), _s0_ren_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 567:70] node s0_ren = or(_s0_ren_T_2, _s0_ren_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 567:52] node _wen_T = eq(invalidated, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 570:35] node _wen_T_1 = and(refill_one_beat, _wen_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 570:32] node _wen_T_2 = bits(s1s3_slaveAddr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _wen_T_3 = eq(_wen_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 564:111] node _wen_T_4 = and(s3_slaveValid, _wen_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 570:67] node wen = or(_wen_T_1, _wen_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 570:49] node _mem_idx_T = shl(refill_idx, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 574:40] node _mem_idx_T_1 = or(_mem_idx_T, refill_cnt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 574:67] node _mem_idx_T_2 = bits(s1s3_slaveAddr, 11, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 565:31] node _mem_idx_T_3 = bits(io.req.bits.addr, 11, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 565:31] node _mem_idx_T_4 = mux(UInt<1>(0h0), UInt<9>(0h0), _mem_idx_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 578:22] node _mem_idx_T_5 = mux(s3_slaveValid, _mem_idx_T_2, _mem_idx_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 576:22] node mem_idx = mux(refill_one_beat, _mem_idx_T_1, _mem_idx_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 574:10] when wen : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 581:16] node _data_T = bits(masterNodeOut.d.bits.data, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 583:71] node data = mux(s3_slaveValid, s1s3_slaveData, _data_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 583:21] node way = mux(s3_slaveValid, UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 585:20] wire _WIRE_1 : UInt<32>[1] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 586:40] connect _WIRE_1[0], data @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 586:40] node _T_11 = eq(way, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 586:102] write mport MPORT_1 = rockettile_icache_data_arrays_0[mem_idx], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 586:23] when _T_11 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 586:23] connect MPORT_1[0], _WIRE_1[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 586:23] node _dout_T = eq(wen, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 590:41] node _dout_T_1 = and(_dout_T, s0_ren) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 590:46] wire _dout_WIRE : UInt<9> @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 590:31] invalidate _dout_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 590:31] when _dout_T_1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 590:31] connect _dout_WIRE, mem_idx @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 590:31] read mport dout = rockettile_icache_data_arrays_0[_dout_WIRE], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 590:31] node _T_12 = mux(s1_slaveValid, s1s3_slaveAddr, io.s1_paddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 592:24] node _T_13 = bits(_T_12, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _T_14 = eq(_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 564:111] when _T_14 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 592:71] connect s1_dout, dout @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 593:15] node _s0_ren_T_5 = bits(io.req.bits.addr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _s0_ren_T_6 = eq(_s0_ren_T_5, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 564:111] node _s0_ren_T_7 = and(s0_valid, _s0_ren_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 567:28] node _s0_ren_T_8 = eq(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 564:111] node _s0_ren_T_9 = and(UInt<1>(0h0), _s0_ren_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 567:70] node s0_ren_1 = or(_s0_ren_T_7, _s0_ren_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 567:52] node _wen_T_5 = eq(invalidated, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 570:35] node _wen_T_6 = and(refill_one_beat, _wen_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 570:32] node _wen_T_7 = bits(s1s3_slaveAddr, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _wen_T_8 = eq(_wen_T_7, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 564:111] node _wen_T_9 = and(s3_slaveValid, _wen_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 570:67] node wen_1 = or(_wen_T_6, _wen_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 570:49] node _mem_idx_T_6 = shl(refill_idx, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 574:40] node _mem_idx_T_7 = or(_mem_idx_T_6, refill_cnt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 574:67] node _mem_idx_T_8 = bits(s1s3_slaveAddr, 11, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 565:31] node _mem_idx_T_9 = bits(io.req.bits.addr, 11, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 565:31] node _mem_idx_T_10 = mux(UInt<1>(0h0), UInt<9>(0h0), _mem_idx_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 578:22] node _mem_idx_T_11 = mux(s3_slaveValid, _mem_idx_T_8, _mem_idx_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 576:22] node mem_idx_1 = mux(refill_one_beat, _mem_idx_T_7, _mem_idx_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 574:10] when wen_1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 581:16] node _data_T_1 = bits(masterNodeOut.d.bits.data, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 583:71] node data_1 = mux(s3_slaveValid, s1s3_slaveData, _data_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 583:21] node way_1 = mux(s3_slaveValid, UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 585:20] wire _WIRE_2 : UInt<32>[1] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 586:40] connect _WIRE_2[0], data_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 586:40] node _T_15 = eq(way_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 586:102] write mport MPORT_2 = rockettile_icache_data_arrays_1[mem_idx_1], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 586:23] when _T_15 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 586:23] connect MPORT_2[0], _WIRE_2[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 586:23] node _dout_T_2 = eq(wen_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 590:41] node _dout_T_3 = and(_dout_T_2, s0_ren_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 590:46] wire _dout_WIRE_1 : UInt<9> @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 590:31] invalidate _dout_WIRE_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 590:31] when _dout_T_3 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 590:31] connect _dout_WIRE_1, mem_idx_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 590:31] read mport dout_1 = rockettile_icache_data_arrays_1[_dout_WIRE_1], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 590:31] node _T_16 = mux(s1_slaveValid, s1s3_slaveAddr, io.s1_paddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 592:24] node _T_17 = bits(_T_16, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _T_18 = eq(_T_17, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 564:111] when _T_18 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 592:71] connect s1_dout, dout_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 593:15] wire s1s2_full_word_write : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 600:41] connect s1s2_full_word_write, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 600:41] node s1_dont_read = and(s1_slaveValid, s1s2_full_word_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 601:36] node s1_clk_en = or(s1_valid, s1_slaveValid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 604:28] wire _s2_tag_hit_WIRE : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 605:60] connect _s2_tag_hit_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 605:60] node _s2_tag_hit_T = mux(s1_dont_read, _s2_tag_hit_WIRE, s1_tag_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 605:33] reg s2_tag_hit : UInt<1>[1], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 605:29] when s1_clk_en : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 605:29] connect s2_tag_hit, _s2_tag_hit_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 605:29] node _s2_scratchpad_word_addr_T = mux(s2_slaveValid, s1s3_slaveAddr, io.s2_vaddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 611:52] node _s2_scratchpad_word_addr_T_1 = bits(_s2_scratchpad_word_addr_T, 11, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 611:96] node s2_scratchpad_word_addr_hi = cat(UInt<1>(0h0), _s2_scratchpad_word_addr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 611:36] node s2_scratchpad_word_addr = cat(s2_scratchpad_word_addr_hi, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 611:36] reg s2_dout : UInt<32>[1], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 612:26] when s1_clk_en : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 612:26] connect s2_dout, s1_dout @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 612:26] reg s2_tag_disparity_r : UInt<1>[1], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 614:35] when s1_clk_en : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 614:35] connect s2_tag_disparity_r, s1_tag_disparity @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 614:35] node s2_tag_disparity = orr(s2_tag_disparity_r[0]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 614:72] node _s2_tl_error_T = orr(s1_tl_error[0]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 615:50] reg s2_tl_error : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 615:30] when s1_clk_en : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 615:30] connect s2_tl_error, _s2_tl_error_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 615:30] node _s2_disparity_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/ECC.scala 15:27] node s2_disparity = or(s2_tag_disparity, _s2_disparity_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 619:39] node _s1_scratchpad_hit_T = bits(s1s3_slaveAddr, 11, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 327:40] node _s1_scratchpad_hit_T_1 = bits(io.s1_paddr, 11, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 302:90] node _s1_scratchpad_hit_T_2 = and(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 302:66] node s1_scratchpad_hit = mux(s1_slaveValid, UInt<1>(0h0), _s1_scratchpad_hit_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 621:30] reg s2_scratchpad_hit : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 623:36] when s1_clk_en : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 623:36] connect s2_scratchpad_hit, s1_scratchpad_hit @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 623:36] node _s2_report_uncorrectable_error_T = and(s2_scratchpad_hit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 632:57] node _s2_report_uncorrectable_error_T_1 = eq(s1s2_full_word_write, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 632:124] node _s2_report_uncorrectable_error_T_2 = and(s2_slaveValid, _s2_report_uncorrectable_error_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 632:121] node _s2_report_uncorrectable_error_T_3 = or(s2_valid, _s2_report_uncorrectable_error_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 632:103] node s2_report_uncorrectable_error = and(_s2_report_uncorrectable_error_T, _s2_report_uncorrectable_error_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 632:90] node _T_19 = and(s2_valid, s2_disparity) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 653:22] when _T_19 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 653:39] connect invalidate, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 653:52] connect io.resp.bits.data, s2_dout[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 656:25] connect io.resp.bits.ae, s2_tl_error @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 657:23] connect io.resp.bits.replay, s2_disparity @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 658:27] node _io_resp_valid_T = and(s2_valid, s2_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 659:33] connect io.resp.valid, _io_resp_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 659:21] connect masterNodeOut.a.valid, s2_request_refill @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 766:18] node _masterNodeOut_a_bits_T = shr(refill_paddr, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 769:47] node _masterNodeOut_a_bits_T_1 = shl(_masterNodeOut_a_bits_T, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 769:64] node _masterNodeOut_a_bits_legal_T = leq(UInt<1>(0h0), UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _masterNodeOut_a_bits_legal_T_1 = leq(UInt<3>(0h6), UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _masterNodeOut_a_bits_legal_T_2 = and(_masterNodeOut_a_bits_legal_T, _masterNodeOut_a_bits_legal_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _masterNodeOut_a_bits_legal_T_3 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _masterNodeOut_a_bits_legal_T_4 = xor(_masterNodeOut_a_bits_T_1, UInt<13>(0h1000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _masterNodeOut_a_bits_legal_T_5 = cvt(_masterNodeOut_a_bits_legal_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _masterNodeOut_a_bits_legal_T_6 = and(_masterNodeOut_a_bits_legal_T_5, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_7 = asSInt(_masterNodeOut_a_bits_legal_T_6) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_8 = eq(_masterNodeOut_a_bits_legal_T_7, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _masterNodeOut_a_bits_legal_T_9 = and(_masterNodeOut_a_bits_legal_T_3, _masterNodeOut_a_bits_legal_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _masterNodeOut_a_bits_legal_T_10 = leq(UInt<1>(0h0), UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _masterNodeOut_a_bits_legal_T_11 = leq(UInt<3>(0h6), UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _masterNodeOut_a_bits_legal_T_12 = and(_masterNodeOut_a_bits_legal_T_10, _masterNodeOut_a_bits_legal_T_11) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _masterNodeOut_a_bits_legal_T_13 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _masterNodeOut_a_bits_legal_T_14 = xor(_masterNodeOut_a_bits_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _masterNodeOut_a_bits_legal_T_15 = cvt(_masterNodeOut_a_bits_legal_T_14) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _masterNodeOut_a_bits_legal_T_16 = and(_masterNodeOut_a_bits_legal_T_15, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_17 = asSInt(_masterNodeOut_a_bits_legal_T_16) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_18 = eq(_masterNodeOut_a_bits_legal_T_17, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _masterNodeOut_a_bits_legal_T_19 = xor(_masterNodeOut_a_bits_T_1, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _masterNodeOut_a_bits_legal_T_20 = cvt(_masterNodeOut_a_bits_legal_T_19) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _masterNodeOut_a_bits_legal_T_21 = and(_masterNodeOut_a_bits_legal_T_20, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_22 = asSInt(_masterNodeOut_a_bits_legal_T_21) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_23 = eq(_masterNodeOut_a_bits_legal_T_22, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _masterNodeOut_a_bits_legal_T_24 = xor(_masterNodeOut_a_bits_T_1, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _masterNodeOut_a_bits_legal_T_25 = cvt(_masterNodeOut_a_bits_legal_T_24) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _masterNodeOut_a_bits_legal_T_26 = and(_masterNodeOut_a_bits_legal_T_25, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_27 = asSInt(_masterNodeOut_a_bits_legal_T_26) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_28 = eq(_masterNodeOut_a_bits_legal_T_27, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _masterNodeOut_a_bits_legal_T_29 = xor(_masterNodeOut_a_bits_T_1, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _masterNodeOut_a_bits_legal_T_30 = cvt(_masterNodeOut_a_bits_legal_T_29) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _masterNodeOut_a_bits_legal_T_31 = and(_masterNodeOut_a_bits_legal_T_30, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_32 = asSInt(_masterNodeOut_a_bits_legal_T_31) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_33 = eq(_masterNodeOut_a_bits_legal_T_32, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _masterNodeOut_a_bits_legal_T_34 = xor(_masterNodeOut_a_bits_T_1, UInt<29>(0h10000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _masterNodeOut_a_bits_legal_T_35 = cvt(_masterNodeOut_a_bits_legal_T_34) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _masterNodeOut_a_bits_legal_T_36 = and(_masterNodeOut_a_bits_legal_T_35, asSInt(UInt<33>(0hfa018000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_37 = asSInt(_masterNodeOut_a_bits_legal_T_36) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_38 = eq(_masterNodeOut_a_bits_legal_T_37, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _masterNodeOut_a_bits_legal_T_39 = xor(_masterNodeOut_a_bits_T_1, UInt<29>(0h10008000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _masterNodeOut_a_bits_legal_T_40 = cvt(_masterNodeOut_a_bits_legal_T_39) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _masterNodeOut_a_bits_legal_T_41 = and(_masterNodeOut_a_bits_legal_T_40, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_42 = asSInt(_masterNodeOut_a_bits_legal_T_41) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_43 = eq(_masterNodeOut_a_bits_legal_T_42, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _masterNodeOut_a_bits_legal_T_44 = xor(_masterNodeOut_a_bits_T_1, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _masterNodeOut_a_bits_legal_T_45 = cvt(_masterNodeOut_a_bits_legal_T_44) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _masterNodeOut_a_bits_legal_T_46 = and(_masterNodeOut_a_bits_legal_T_45, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_47 = asSInt(_masterNodeOut_a_bits_legal_T_46) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_48 = eq(_masterNodeOut_a_bits_legal_T_47, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _masterNodeOut_a_bits_legal_T_49 = xor(_masterNodeOut_a_bits_T_1, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _masterNodeOut_a_bits_legal_T_50 = cvt(_masterNodeOut_a_bits_legal_T_49) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _masterNodeOut_a_bits_legal_T_51 = and(_masterNodeOut_a_bits_legal_T_50, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_52 = asSInt(_masterNodeOut_a_bits_legal_T_51) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_53 = eq(_masterNodeOut_a_bits_legal_T_52, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _masterNodeOut_a_bits_legal_T_54 = xor(_masterNodeOut_a_bits_T_1, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _masterNodeOut_a_bits_legal_T_55 = cvt(_masterNodeOut_a_bits_legal_T_54) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _masterNodeOut_a_bits_legal_T_56 = and(_masterNodeOut_a_bits_legal_T_55, asSInt(UInt<33>(0hfa000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_57 = asSInt(_masterNodeOut_a_bits_legal_T_56) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _masterNodeOut_a_bits_legal_T_58 = eq(_masterNodeOut_a_bits_legal_T_57, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _masterNodeOut_a_bits_legal_T_59 = or(_masterNodeOut_a_bits_legal_T_18, _masterNodeOut_a_bits_legal_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _masterNodeOut_a_bits_legal_T_60 = or(_masterNodeOut_a_bits_legal_T_59, _masterNodeOut_a_bits_legal_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _masterNodeOut_a_bits_legal_T_61 = or(_masterNodeOut_a_bits_legal_T_60, _masterNodeOut_a_bits_legal_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _masterNodeOut_a_bits_legal_T_62 = or(_masterNodeOut_a_bits_legal_T_61, _masterNodeOut_a_bits_legal_T_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _masterNodeOut_a_bits_legal_T_63 = or(_masterNodeOut_a_bits_legal_T_62, _masterNodeOut_a_bits_legal_T_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _masterNodeOut_a_bits_legal_T_64 = or(_masterNodeOut_a_bits_legal_T_63, _masterNodeOut_a_bits_legal_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _masterNodeOut_a_bits_legal_T_65 = or(_masterNodeOut_a_bits_legal_T_64, _masterNodeOut_a_bits_legal_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _masterNodeOut_a_bits_legal_T_66 = or(_masterNodeOut_a_bits_legal_T_65, _masterNodeOut_a_bits_legal_T_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _masterNodeOut_a_bits_legal_T_67 = and(_masterNodeOut_a_bits_legal_T_13, _masterNodeOut_a_bits_legal_T_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _masterNodeOut_a_bits_legal_T_68 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node masterNodeOut_a_bits_legal = or(_masterNodeOut_a_bits_legal_T_68, _masterNodeOut_a_bits_legal_T_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire masterNodeOut_a_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 460:17] connect masterNodeOut_a_bits_a.opcode, UInt<3>(0h4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 461:15] connect masterNodeOut_a_bits_a.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 462:15] connect masterNodeOut_a_bits_a.size, UInt<3>(0h6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 463:15] connect masterNodeOut_a_bits_a.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 464:15] connect masterNodeOut_a_bits_a.address, _masterNodeOut_a_bits_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 465:15] invalidate masterNodeOut_a_bits_a.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] invalidate masterNodeOut_a_bits_a.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] invalidate masterNodeOut_a_bits_a.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] invalidate masterNodeOut_a_bits_a.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] invalidate masterNodeOut_a_bits_a.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] invalidate masterNodeOut_a_bits_a.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] invalidate masterNodeOut_a_bits_a.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] node _masterNodeOut_a_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount = bits(_masterNodeOut_a_bits_a_mask_sizeOH_T, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _masterNodeOut_a_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _masterNodeOut_a_bits_a_mask_sizeOH_T_2 = bits(_masterNodeOut_a_bits_a_mask_sizeOH_T_1, 2, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node masterNodeOut_a_bits_a_mask_sizeOH = or(_masterNodeOut_a_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] node masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 206:21] node masterNodeOut_a_bits_a_mask_sub_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node masterNodeOut_a_bits_a_mask_sub_sub_bit = bits(_masterNodeOut_a_bits_T_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node masterNodeOut_a_bits_a_mask_sub_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node masterNodeOut_a_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sub_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_0_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node masterNodeOut_a_bits_a_mask_sub_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node masterNodeOut_a_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sub_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_1_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node masterNodeOut_a_bits_a_mask_sub_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node masterNodeOut_a_bits_a_mask_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node masterNodeOut_a_bits_a_mask_sub_bit = bits(_masterNodeOut_a_bits_T_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node masterNodeOut_a_bits_a_mask_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node masterNodeOut_a_bits_a_mask_sub_0_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _masterNodeOut_a_bits_a_mask_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_0_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node masterNodeOut_a_bits_a_mask_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node masterNodeOut_a_bits_a_mask_sub_1_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _masterNodeOut_a_bits_a_mask_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_1_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node masterNodeOut_a_bits_a_mask_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node masterNodeOut_a_bits_a_mask_sub_2_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _masterNodeOut_a_bits_a_mask_sub_acc_T_2 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_2_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node masterNodeOut_a_bits_a_mask_sub_2_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node masterNodeOut_a_bits_a_mask_sub_3_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _masterNodeOut_a_bits_a_mask_sub_acc_T_3 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_3_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node masterNodeOut_a_bits_a_mask_sub_3_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node masterNodeOut_a_bits_a_mask_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node masterNodeOut_a_bits_a_mask_bit = bits(_masterNodeOut_a_bits_T_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node masterNodeOut_a_bits_a_mask_nbit = eq(masterNodeOut_a_bits_a_mask_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node masterNodeOut_a_bits_a_mask_eq = and(masterNodeOut_a_bits_a_mask_sub_0_2, masterNodeOut_a_bits_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _masterNodeOut_a_bits_a_mask_acc_T = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node masterNodeOut_a_bits_a_mask_acc = or(masterNodeOut_a_bits_a_mask_sub_0_1, _masterNodeOut_a_bits_a_mask_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node masterNodeOut_a_bits_a_mask_eq_1 = and(masterNodeOut_a_bits_a_mask_sub_0_2, masterNodeOut_a_bits_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _masterNodeOut_a_bits_a_mask_acc_T_1 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node masterNodeOut_a_bits_a_mask_acc_1 = or(masterNodeOut_a_bits_a_mask_sub_0_1, _masterNodeOut_a_bits_a_mask_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node masterNodeOut_a_bits_a_mask_eq_2 = and(masterNodeOut_a_bits_a_mask_sub_1_2, masterNodeOut_a_bits_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _masterNodeOut_a_bits_a_mask_acc_T_2 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node masterNodeOut_a_bits_a_mask_acc_2 = or(masterNodeOut_a_bits_a_mask_sub_1_1, _masterNodeOut_a_bits_a_mask_acc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node masterNodeOut_a_bits_a_mask_eq_3 = and(masterNodeOut_a_bits_a_mask_sub_1_2, masterNodeOut_a_bits_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _masterNodeOut_a_bits_a_mask_acc_T_3 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node masterNodeOut_a_bits_a_mask_acc_3 = or(masterNodeOut_a_bits_a_mask_sub_1_1, _masterNodeOut_a_bits_a_mask_acc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node masterNodeOut_a_bits_a_mask_eq_4 = and(masterNodeOut_a_bits_a_mask_sub_2_2, masterNodeOut_a_bits_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _masterNodeOut_a_bits_a_mask_acc_T_4 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node masterNodeOut_a_bits_a_mask_acc_4 = or(masterNodeOut_a_bits_a_mask_sub_2_1, _masterNodeOut_a_bits_a_mask_acc_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node masterNodeOut_a_bits_a_mask_eq_5 = and(masterNodeOut_a_bits_a_mask_sub_2_2, masterNodeOut_a_bits_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _masterNodeOut_a_bits_a_mask_acc_T_5 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node masterNodeOut_a_bits_a_mask_acc_5 = or(masterNodeOut_a_bits_a_mask_sub_2_1, _masterNodeOut_a_bits_a_mask_acc_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node masterNodeOut_a_bits_a_mask_eq_6 = and(masterNodeOut_a_bits_a_mask_sub_3_2, masterNodeOut_a_bits_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _masterNodeOut_a_bits_a_mask_acc_T_6 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node masterNodeOut_a_bits_a_mask_acc_6 = or(masterNodeOut_a_bits_a_mask_sub_3_1, _masterNodeOut_a_bits_a_mask_acc_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node masterNodeOut_a_bits_a_mask_eq_7 = and(masterNodeOut_a_bits_a_mask_sub_3_2, masterNodeOut_a_bits_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _masterNodeOut_a_bits_a_mask_acc_T_7 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node masterNodeOut_a_bits_a_mask_acc_7 = or(masterNodeOut_a_bits_a_mask_sub_3_1, _masterNodeOut_a_bits_a_mask_acc_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node masterNodeOut_a_bits_a_mask_lo_lo = cat(masterNodeOut_a_bits_a_mask_acc_1, masterNodeOut_a_bits_a_mask_acc) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node masterNodeOut_a_bits_a_mask_lo_hi = cat(masterNodeOut_a_bits_a_mask_acc_3, masterNodeOut_a_bits_a_mask_acc_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node masterNodeOut_a_bits_a_mask_lo = cat(masterNodeOut_a_bits_a_mask_lo_hi, masterNodeOut_a_bits_a_mask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node masterNodeOut_a_bits_a_mask_hi_lo = cat(masterNodeOut_a_bits_a_mask_acc_5, masterNodeOut_a_bits_a_mask_acc_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node masterNodeOut_a_bits_a_mask_hi_hi = cat(masterNodeOut_a_bits_a_mask_acc_7, masterNodeOut_a_bits_a_mask_acc_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node masterNodeOut_a_bits_a_mask_hi = cat(masterNodeOut_a_bits_a_mask_hi_hi, masterNodeOut_a_bits_a_mask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node _masterNodeOut_a_bits_a_mask_T = cat(masterNodeOut_a_bits_a_mask_hi, masterNodeOut_a_bits_a_mask_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] connect masterNodeOut_a_bits_a.mask, _masterNodeOut_a_bits_a_mask_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 468:15] invalidate masterNodeOut_a_bits_a.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 469:15] connect masterNodeOut_a_bits_a.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 470:15] connect masterNodeOut.a.bits, masterNodeOut_a_bits_a @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 767:17] connect masterNodeOut.a.bits.user.amba_prot.fetch, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 815:19] connect masterNodeOut.a.bits.user.amba_prot.secure, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 816:19] connect masterNodeOut.a.bits.user.amba_prot.privileged, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 817:19] connect masterNodeOut.a.bits.user.amba_prot.bufferable, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 818:19] connect masterNodeOut.a.bits.user.amba_prot.modifiable, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 819:19] connect masterNodeOut.a.bits.user.amba_prot.readalloc, io.s2_cacheable @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 820:19] connect masterNodeOut.a.bits.user.amba_prot.writealloc, io.s2_cacheable @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 821:19] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_3.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_3.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_3.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_3.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_3.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_3.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_3.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_3.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_3.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_3.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_4.bits, _WIRE_3.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_4.valid, _WIRE_3.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_4.ready, _WIRE_3.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_4.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 823:18] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_5.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_5.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_5.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_5.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_5.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_5.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_5.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_5.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_5.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_5.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_5.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_5.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_5.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_5.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_5.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_5.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_6.bits, _WIRE_5.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_6.valid, _WIRE_5.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_6.ready, _WIRE_5.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 824:18] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_7.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_7.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_7.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_8.bits, _WIRE_7.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_8.valid, _WIRE_7.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_8.ready, _WIRE_7.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 825:18] node _T_20 = and(masterNodeOut.a.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 826:27] node _T_21 = eq(_T_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 826:10] node _T_22 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 826:9] node _T_23 = eq(_T_22, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 826:9] when _T_23 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 826:9] node _T_24 = eq(_T_21, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 826:9] when _T_24 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 826:9] printf(clock, UInt<1>(0h1), "Assertion failed\n at ICache.scala:826 assert(!(tl_out.a.valid && addrMaybeInScratchpad(tl_out.a.bits.address)))\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 826:9] assert(clock, _T_21, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 826:9] node _T_25 = eq(refill_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 829:9] when _T_25 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 829:24] connect invalidated, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 829:38] when refill_fire : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 830:22] connect refill_valid, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 830:37] when refill_done : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 831:22] connect refill_valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 831:37] connect io.perf.acquire, refill_fire @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 833:19] node _io_keep_clock_enabled_T = or(UInt<1>(0h0), s1_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 836:117] node _io_keep_clock_enabled_T_1 = or(_io_keep_clock_enabled_T, s2_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 837:14] node _io_keep_clock_enabled_T_2 = or(_io_keep_clock_enabled_T_1, refill_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 837:26] node _io_keep_clock_enabled_T_3 = or(_io_keep_clock_enabled_T_2, send_hint) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 837:42] node _io_keep_clock_enabled_T_4 = or(_io_keep_clock_enabled_T_3, hint_outstanding) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 837:55] connect io.keep_clock_enabled, _io_keep_clock_enabled_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 835:25] node _T_26 = eq(send_hint, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 865:10] node _T_27 = eq(masterNodeOut.a.ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 865:43] node _T_28 = and(masterNodeOut.a.valid, _T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 865:40] node _T_29 = and(_T_26, _T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 865:21] node _T_30 = and(invalidate, refill_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 866:21] node _T_31 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 873:27] node _T_32 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 873:59] node _T_33 = and(_T_31, _T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 873:56] node _T_34 = eq(s2_slaveValid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 877:27] node _T_35 = eq(s2_tag_disparity, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 881:27] node _T_36 = eq(s2_scratchpad_hit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 886:27] node _T_37 = and(_T_34, s2_scratchpad_hit) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_38 = and(_T_34, _T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_39 = and(s2_slaveValid, s2_scratchpad_hit) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_40 = and(s2_slaveValid, _T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_41 = and(_T_35, _T_37) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_42 = and(_T_35, _T_38) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_43 = and(_T_35, _T_39) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_44 = and(_T_35, _T_40) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_45 = and(_T_34, s2_scratchpad_hit) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_46 = and(_T_34, _T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_47 = and(s2_slaveValid, s2_scratchpad_hit) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_48 = and(s2_slaveValid, _T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_49 = and(s2_tag_disparity, _T_45) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_50 = and(s2_tag_disparity, _T_46) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_51 = and(s2_tag_disparity, _T_47) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_52 = and(s2_tag_disparity, _T_48) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_53 = and(_T_33, _T_41) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_54 = and(_T_33, _T_42) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_55 = and(_T_33, _T_43) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_56 = and(_T_33, _T_44) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_57 = and(_T_33, _T_49) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_58 = and(_T_33, _T_50) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_59 = and(_T_33, _T_51) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_60 = and(_T_33, _T_52) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_61 = and(_T_34, s2_scratchpad_hit) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_62 = and(_T_34, _T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_63 = and(s2_slaveValid, s2_scratchpad_hit) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_64 = and(s2_slaveValid, _T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_65 = and(_T_35, _T_61) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_66 = and(_T_35, _T_62) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_67 = and(_T_35, _T_63) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_68 = and(_T_35, _T_64) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_69 = and(_T_34, s2_scratchpad_hit) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_70 = and(_T_34, _T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_71 = and(s2_slaveValid, s2_scratchpad_hit) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_72 = and(s2_slaveValid, _T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_73 = and(s2_tag_disparity, _T_69) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_74 = and(s2_tag_disparity, _T_70) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_75 = and(s2_tag_disparity, _T_71) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_76 = and(s2_tag_disparity, _T_72) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_77 = and(UInt<1>(0h0), _T_65) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_78 = and(UInt<1>(0h0), _T_66) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_79 = and(UInt<1>(0h0), _T_67) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_80 = and(UInt<1>(0h0), _T_68) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_81 = and(UInt<1>(0h0), _T_73) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_82 = and(UInt<1>(0h0), _T_74) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_83 = and(UInt<1>(0h0), _T_75) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_84 = and(UInt<1>(0h0), _T_76) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_85 = and(_T_34, s2_scratchpad_hit) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_86 = and(_T_34, _T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_87 = and(s2_slaveValid, s2_scratchpad_hit) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_88 = and(s2_slaveValid, _T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_89 = and(_T_35, _T_85) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_90 = and(_T_35, _T_86) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_91 = and(_T_35, _T_87) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_92 = and(_T_35, _T_88) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_93 = and(_T_34, s2_scratchpad_hit) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_94 = and(_T_34, _T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_95 = and(s2_slaveValid, s2_scratchpad_hit) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_96 = and(s2_slaveValid, _T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_97 = and(s2_tag_disparity, _T_93) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_98 = and(s2_tag_disparity, _T_94) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_99 = and(s2_tag_disparity, _T_95) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_100 = and(s2_tag_disparity, _T_96) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_101 = and(UInt<1>(0h0), _T_89) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_102 = and(UInt<1>(0h0), _T_90) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_103 = and(UInt<1>(0h0), _T_91) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_104 = and(UInt<1>(0h0), _T_92) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_105 = and(UInt<1>(0h0), _T_97) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_106 = and(UInt<1>(0h0), _T_98) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_107 = and(UInt<1>(0h0), _T_99) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_108 = and(UInt<1>(0h0), _T_100) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_109 = and(s2_valid, _T_53) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_110 = and(s2_valid, _T_54) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_111 = and(s2_valid, _T_55) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_112 = and(s2_valid, _T_56) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_113 = and(s2_valid, _T_57) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_114 = and(s2_valid, _T_58) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_115 = and(s2_valid, _T_59) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_116 = and(s2_valid, _T_60) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_117 = and(s2_valid, _T_77) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_118 = and(s2_valid, _T_78) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_119 = and(s2_valid, _T_79) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_120 = and(s2_valid, _T_80) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_121 = and(s2_valid, _T_81) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_122 = and(s2_valid, _T_82) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_123 = and(s2_valid, _T_83) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_124 = and(s2_valid, _T_84) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_125 = and(s2_valid, _T_101) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_126 = and(s2_valid, _T_102) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_127 = and(s2_valid, _T_103) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_128 = and(s2_valid, _T_104) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_129 = and(s2_valid, _T_105) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_130 = and(s2_valid, _T_106) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_131 = and(s2_valid, _T_107) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] node _T_132 = and(s2_valid, _T_108) @[hardware/upstream/rocket-chip/src/main/scala/util/Property.scala 81:34] module ShiftQueue : @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 12:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 12:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 12:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<1>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<34>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<1>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<34>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, count : UInt<3>, mask : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 17:14] wire _valid_WIRE : UInt<1>[5] @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 21:38] connect _valid_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 21:38] connect _valid_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 21:38] connect _valid_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 21:38] connect _valid_WIRE[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 21:38] connect _valid_WIRE[4], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 21:38] regreset valid : UInt<1>[5], clock, reset, _valid_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 21:30] reg elts : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<1>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<34>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}[5], clock @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 22:25] node wdata = mux(valid[1], elts[1], io.enq.bits) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 27:57] node _wen_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _wen_T_1 = or(UInt<1>(0h0), valid[0]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 30:67] node _wen_T_2 = and(_wen_T, _wen_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 30:43] node _wen_T_3 = or(valid[1], _wen_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 30:28] node _wen_T_4 = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _wen_T_5 = and(_wen_T_4, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 31:23] node _wen_T_6 = eq(valid[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 31:46] node _wen_T_7 = and(_wen_T_5, _wen_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 31:43] node wen = mux(io.deq.ready, _wen_T_3, _wen_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 29:10] when wen : @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 32:16] connect elts[0], wdata @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 32:26] node _valid_0_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _valid_0_T_1 = or(UInt<1>(0h0), valid[0]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 36:67] node _valid_0_T_2 = and(_valid_0_T, _valid_0_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 36:43] node _valid_0_T_3 = or(valid[1], _valid_0_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 36:28] node _valid_0_T_4 = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _valid_0_T_5 = and(_valid_0_T_4, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 37:23] node _valid_0_T_6 = or(_valid_0_T_5, valid[0]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 37:43] node _valid_0_T_7 = mux(io.deq.ready, _valid_0_T_3, _valid_0_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 35:10] connect valid[0], _valid_0_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 34:14] node wdata_1 = mux(valid[2], elts[2], io.enq.bits) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 27:57] node _wen_T_8 = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _wen_T_9 = or(UInt<1>(0h0), valid[1]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 30:67] node _wen_T_10 = and(_wen_T_8, _wen_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 30:43] node _wen_T_11 = or(valid[2], _wen_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 30:28] node _wen_T_12 = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _wen_T_13 = and(_wen_T_12, valid[0]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 31:23] node _wen_T_14 = eq(valid[1], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 31:46] node _wen_T_15 = and(_wen_T_13, _wen_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 31:43] node wen_1 = mux(io.deq.ready, _wen_T_11, _wen_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 29:10] when wen_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 32:16] connect elts[1], wdata_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 32:26] node _valid_1_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _valid_1_T_1 = or(UInt<1>(0h0), valid[1]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 36:67] node _valid_1_T_2 = and(_valid_1_T, _valid_1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 36:43] node _valid_1_T_3 = or(valid[2], _valid_1_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 36:28] node _valid_1_T_4 = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _valid_1_T_5 = and(_valid_1_T_4, valid[0]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 37:23] node _valid_1_T_6 = or(_valid_1_T_5, valid[1]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 37:43] node _valid_1_T_7 = mux(io.deq.ready, _valid_1_T_3, _valid_1_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 35:10] connect valid[1], _valid_1_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 34:14] node wdata_2 = mux(valid[3], elts[3], io.enq.bits) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 27:57] node _wen_T_16 = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _wen_T_17 = or(UInt<1>(0h0), valid[2]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 30:67] node _wen_T_18 = and(_wen_T_16, _wen_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 30:43] node _wen_T_19 = or(valid[3], _wen_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 30:28] node _wen_T_20 = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _wen_T_21 = and(_wen_T_20, valid[1]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 31:23] node _wen_T_22 = eq(valid[2], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 31:46] node _wen_T_23 = and(_wen_T_21, _wen_T_22) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 31:43] node wen_2 = mux(io.deq.ready, _wen_T_19, _wen_T_23) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 29:10] when wen_2 : @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 32:16] connect elts[2], wdata_2 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 32:26] node _valid_2_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _valid_2_T_1 = or(UInt<1>(0h0), valid[2]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 36:67] node _valid_2_T_2 = and(_valid_2_T, _valid_2_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 36:43] node _valid_2_T_3 = or(valid[3], _valid_2_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 36:28] node _valid_2_T_4 = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _valid_2_T_5 = and(_valid_2_T_4, valid[1]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 37:23] node _valid_2_T_6 = or(_valid_2_T_5, valid[2]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 37:43] node _valid_2_T_7 = mux(io.deq.ready, _valid_2_T_3, _valid_2_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 35:10] connect valid[2], _valid_2_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 34:14] node wdata_3 = mux(valid[4], elts[4], io.enq.bits) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 27:57] node _wen_T_24 = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _wen_T_25 = or(UInt<1>(0h0), valid[3]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 30:67] node _wen_T_26 = and(_wen_T_24, _wen_T_25) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 30:43] node _wen_T_27 = or(valid[4], _wen_T_26) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 30:28] node _wen_T_28 = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _wen_T_29 = and(_wen_T_28, valid[2]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 31:23] node _wen_T_30 = eq(valid[3], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 31:46] node _wen_T_31 = and(_wen_T_29, _wen_T_30) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 31:43] node wen_3 = mux(io.deq.ready, _wen_T_27, _wen_T_31) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 29:10] when wen_3 : @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 32:16] connect elts[3], wdata_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 32:26] node _valid_3_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _valid_3_T_1 = or(UInt<1>(0h0), valid[3]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 36:67] node _valid_3_T_2 = and(_valid_3_T, _valid_3_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 36:43] node _valid_3_T_3 = or(valid[4], _valid_3_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 36:28] node _valid_3_T_4 = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _valid_3_T_5 = and(_valid_3_T_4, valid[2]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 37:23] node _valid_3_T_6 = or(_valid_3_T_5, valid[3]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 37:43] node _valid_3_T_7 = mux(io.deq.ready, _valid_3_T_3, _valid_3_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 35:10] connect valid[3], _valid_3_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 34:14] node _wen_T_32 = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _wen_T_33 = or(UInt<1>(0h0), valid[4]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 30:67] node _wen_T_34 = and(_wen_T_32, _wen_T_33) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 30:43] node _wen_T_35 = or(UInt<1>(0h0), _wen_T_34) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 30:28] node _wen_T_36 = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _wen_T_37 = and(_wen_T_36, valid[3]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 31:23] node _wen_T_38 = eq(valid[4], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 31:46] node _wen_T_39 = and(_wen_T_37, _wen_T_38) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 31:43] node wen_4 = mux(io.deq.ready, _wen_T_35, _wen_T_39) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 29:10] when wen_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 32:16] connect elts[4], io.enq.bits @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 32:26] node _valid_4_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _valid_4_T_1 = or(UInt<1>(0h0), valid[4]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 36:67] node _valid_4_T_2 = and(_valid_4_T, _valid_4_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 36:43] node _valid_4_T_3 = or(UInt<1>(0h0), _valid_4_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 36:28] node _valid_4_T_4 = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _valid_4_T_5 = and(_valid_4_T_4, valid[3]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 37:23] node _valid_4_T_6 = or(_valid_4_T_5, valid[4]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 37:43] node _valid_4_T_7 = mux(io.deq.ready, _valid_4_T_3, _valid_4_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 35:10] connect valid[4], _valid_4_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 34:14] node _io_enq_ready_T = eq(valid[4], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 40:19] connect io.enq.ready, _io_enq_ready_T @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 40:16] connect io.deq.valid, valid[0] @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 41:16] connect io.deq.bits, elts[0] @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 42:15] when io.enq.valid : @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 45:25] connect io.deq.valid, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 45:40] node _T = eq(valid[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 46:11] when _T : @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 46:22] connect io.deq.bits, io.enq.bits @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 46:36] node io_mask_lo = cat(valid[1], valid[0]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 53:20] node io_mask_hi_hi = cat(valid[4], valid[3]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 53:20] node io_mask_hi = cat(io_mask_hi_hi, valid[2]) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 53:20] node _io_mask_T = cat(io_mask_hi, io_mask_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 53:20] connect io.mask, _io_mask_T @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 53:11] node _io_count_T = bits(io.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 54:23] node _io_count_T_1 = bits(io.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 54:23] node _io_count_T_2 = bits(io.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 54:23] node _io_count_T_3 = bits(io.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 54:23] node _io_count_T_4 = bits(io.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 54:23] node _io_count_T_5 = add(_io_count_T, _io_count_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 54:23] node _io_count_T_6 = bits(_io_count_T_5, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 54:23] node _io_count_T_7 = add(_io_count_T_3, _io_count_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 54:23] node _io_count_T_8 = bits(_io_count_T_7, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 54:23] node _io_count_T_9 = add(_io_count_T_2, _io_count_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 54:23] node _io_count_T_10 = bits(_io_count_T_9, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 54:23] node _io_count_T_11 = add(_io_count_T_6, _io_count_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 54:23] node _io_count_T_12 = bits(_io_count_T_11, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 54:23] connect io.count, _io_count_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftQueue.scala 54:12] module OptimizationBarrier_TLBEntryData_14 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module PMPChecker_s2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 143:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 143:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 143:7] output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 146:14] node default = gt(io.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 156:56] wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.mask, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.addr, UInt<30>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.cfg.r, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.cfg.w, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.cfg.x, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.cfg.a, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.cfg.res, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] connect _pmp0_WIRE.cfg.l, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:35] wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:22] connect pmp0, _pmp0_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 157:22] connect pmp0.cfg.r, default @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 158:14] connect pmp0.cfg.w, default @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 159:14] connect pmp0.cfg.x, default @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 160:14] node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_T_1 = shl(io.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_2 = not(_res_hit_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_3 = or(_res_hit_T_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_4 = not(_res_hit_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_5 = xor(io.addr, _res_hit_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_T_6 = not(io.pmp[7].mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_T_7 = and(_res_hit_T_5, _res_hit_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_9 = bits(io.pmp[7].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_10 = dshl(UInt<2>(0h3), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_11 = bits(_res_hit_T_10, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_12 = not(_res_hit_T_11) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_T_13 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_14 = not(_res_hit_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_15 = or(_res_hit_T_14, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_16 = not(_res_hit_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_17 = lt(io.addr, _res_hit_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 77:9] node _res_hit_T_18 = eq(_res_hit_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_T_19 = shl(io.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_20 = not(_res_hit_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_21 = or(_res_hit_T_20, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_22 = not(_res_hit_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_23 = lt(io.addr, _res_hit_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 77:9] node _res_hit_T_24 = and(_res_hit_T_18, _res_hit_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_25 = and(_res_hit_T_9, _res_hit_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit = mux(_res_hit_T, _res_hit_T_8, _res_hit_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore = and(default, _res_ignore_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_6 = eq(_res_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_8 = eq(_res_T_7, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_10 = eq(_res_T_9, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_12 = eq(_res_T_11, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_14 = eq(_res_T_13, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_16 = eq(_res_T_15, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_17 = eq(res_ignore, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_18 = and(_res_T_17, res_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_19 = and(_res_T_18, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_21 = and(_res_T_19, _res_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_22 = and(io.pmp[7].cfg.l, res_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_23 = and(_res_T_22, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_25 = and(_res_T_23, _res_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_26 = eq(res_ignore, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_27 = and(_res_T_26, res_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_28 = and(_res_T_27, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_30 = and(_res_T_28, _res_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_31 = and(io.pmp[7].cfg.l, res_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_32 = and(_res_T_31, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_34 = and(_res_T_32, _res_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_35 = eq(res_ignore, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_36 = and(_res_T_35, res_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_37 = and(_res_T_36, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_39 = and(_res_T_37, _res_T_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_40 = and(io.pmp[7].cfg.l, res_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_41 = and(_res_T_40, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_43 = and(_res_T_41, _res_T_42) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur, io.pmp[7] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_1 = and(UInt<1>(0h1), _res_cur_cfg_r_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur.cfg.r, _res_cur_cfg_r_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_1 = and(UInt<1>(0h1), _res_cur_cfg_w_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur.cfg.w, _res_cur_cfg_w_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_1 = and(UInt<1>(0h1), _res_cur_cfg_x_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur.cfg.x, _res_cur_cfg_x_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_44 = mux(res_hit, res_cur, pmp0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_26 = bits(io.pmp[6].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_T_27 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_28 = not(_res_hit_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_29 = or(_res_hit_T_28, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_30 = not(_res_hit_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_31 = xor(io.addr, _res_hit_T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_T_32 = not(io.pmp[6].mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_T_33 = and(_res_hit_T_31, _res_hit_T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_35 = bits(io.pmp[6].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_36 = dshl(UInt<2>(0h3), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_37 = bits(_res_hit_T_36, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_38 = not(_res_hit_T_37) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_T_39 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_40 = not(_res_hit_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_41 = or(_res_hit_T_40, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_42 = not(_res_hit_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_43 = lt(io.addr, _res_hit_T_42) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 77:9] node _res_hit_T_44 = eq(_res_hit_T_43, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_T_45 = shl(io.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_46 = not(_res_hit_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_47 = or(_res_hit_T_46, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_48 = not(_res_hit_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_49 = lt(io.addr, _res_hit_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 77:9] node _res_hit_T_50 = and(_res_hit_T_44, _res_hit_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_51 = and(_res_hit_T_35, _res_hit_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_1 = mux(_res_hit_T_26, _res_hit_T_34, _res_hit_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_1 = and(default, _res_ignore_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_51 = eq(_res_T_50, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_53 = eq(_res_T_52, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_55 = eq(_res_T_54, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_57 = eq(_res_T_56, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_59 = eq(_res_T_58, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_61 = eq(_res_T_60, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_63 = and(_res_T_62, res_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_64 = and(_res_T_63, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_66 = and(_res_T_64, _res_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_68 = and(_res_T_67, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_70 = and(_res_T_68, _res_T_69) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_72 = and(_res_T_71, res_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_73 = and(_res_T_72, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_75 = and(_res_T_73, _res_T_74) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_77 = and(_res_T_76, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_79 = and(_res_T_77, _res_T_78) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_81 = and(_res_T_80, res_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_82 = and(_res_T_81, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_84 = and(_res_T_82, _res_T_83) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_86 = and(_res_T_85, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_88 = and(_res_T_86, _res_T_87) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_1, io.pmp[6] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_3 = and(UInt<1>(0h1), _res_cur_cfg_r_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_3 = and(UInt<1>(0h1), _res_cur_cfg_w_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_3 = and(UInt<1>(0h1), _res_cur_cfg_x_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_52 = bits(io.pmp[5].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_T_53 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_54 = not(_res_hit_T_53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_55 = or(_res_hit_T_54, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_56 = not(_res_hit_T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_57 = xor(io.addr, _res_hit_T_56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_T_58 = not(io.pmp[5].mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_T_59 = and(_res_hit_T_57, _res_hit_T_58) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_61 = bits(io.pmp[5].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_62 = dshl(UInt<2>(0h3), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_63 = bits(_res_hit_T_62, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_64 = not(_res_hit_T_63) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_T_65 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_66 = not(_res_hit_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_67 = or(_res_hit_T_66, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_68 = not(_res_hit_T_67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_69 = lt(io.addr, _res_hit_T_68) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 77:9] node _res_hit_T_70 = eq(_res_hit_T_69, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_T_71 = shl(io.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_72 = not(_res_hit_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_73 = or(_res_hit_T_72, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_74 = not(_res_hit_T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_75 = lt(io.addr, _res_hit_T_74) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 77:9] node _res_hit_T_76 = and(_res_hit_T_70, _res_hit_T_75) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_77 = and(_res_hit_T_61, _res_hit_T_76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_2 = mux(_res_hit_T_52, _res_hit_T_60, _res_hit_T_77) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_2 = and(default, _res_ignore_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_96 = eq(_res_T_95, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_98 = eq(_res_T_97, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_100 = eq(_res_T_99, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_102 = eq(_res_T_101, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_104 = eq(_res_T_103, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_106 = eq(_res_T_105, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_108 = and(_res_T_107, res_hit_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_109 = and(_res_T_108, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_111 = and(_res_T_109, _res_T_110) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_113 = and(_res_T_112, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_115 = and(_res_T_113, _res_T_114) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_117 = and(_res_T_116, res_hit_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_118 = and(_res_T_117, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_120 = and(_res_T_118, _res_T_119) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_122 = and(_res_T_121, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_124 = and(_res_T_122, _res_T_123) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_126 = and(_res_T_125, res_hit_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_127 = and(_res_T_126, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_129 = and(_res_T_127, _res_T_128) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_131 = and(_res_T_130, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_133 = and(_res_T_131, _res_T_132) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_2, io.pmp[5] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_5 = and(UInt<1>(0h1), _res_cur_cfg_r_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_5 = and(UInt<1>(0h1), _res_cur_cfg_w_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_5 = and(UInt<1>(0h1), _res_cur_cfg_x_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_78 = bits(io.pmp[4].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_T_79 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_80 = not(_res_hit_T_79) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_81 = or(_res_hit_T_80, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_82 = not(_res_hit_T_81) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_83 = xor(io.addr, _res_hit_T_82) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_T_84 = not(io.pmp[4].mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_T_85 = and(_res_hit_T_83, _res_hit_T_84) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_87 = bits(io.pmp[4].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_88 = dshl(UInt<2>(0h3), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_89 = bits(_res_hit_T_88, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_90 = not(_res_hit_T_89) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_T_91 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_92 = not(_res_hit_T_91) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_93 = or(_res_hit_T_92, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_94 = not(_res_hit_T_93) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_95 = lt(io.addr, _res_hit_T_94) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 77:9] node _res_hit_T_96 = eq(_res_hit_T_95, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_T_97 = shl(io.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_98 = not(_res_hit_T_97) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_99 = or(_res_hit_T_98, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_100 = not(_res_hit_T_99) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_101 = lt(io.addr, _res_hit_T_100) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 77:9] node _res_hit_T_102 = and(_res_hit_T_96, _res_hit_T_101) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_103 = and(_res_hit_T_87, _res_hit_T_102) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_3 = mux(_res_hit_T_78, _res_hit_T_86, _res_hit_T_103) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_3 = and(default, _res_ignore_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_141 = eq(_res_T_140, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_143 = eq(_res_T_142, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_145 = eq(_res_T_144, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_147 = eq(_res_T_146, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_149 = eq(_res_T_148, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_151 = eq(_res_T_150, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_153 = and(_res_T_152, res_hit_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_154 = and(_res_T_153, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_156 = and(_res_T_154, _res_T_155) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_158 = and(_res_T_157, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_160 = and(_res_T_158, _res_T_159) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_162 = and(_res_T_161, res_hit_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_163 = and(_res_T_162, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_165 = and(_res_T_163, _res_T_164) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_167 = and(_res_T_166, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_169 = and(_res_T_167, _res_T_168) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_171 = and(_res_T_170, res_hit_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_172 = and(_res_T_171, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_174 = and(_res_T_172, _res_T_173) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_176 = and(_res_T_175, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_178 = and(_res_T_176, _res_T_177) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_3, io.pmp[4] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_7 = and(UInt<1>(0h1), _res_cur_cfg_r_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_7 = and(UInt<1>(0h1), _res_cur_cfg_w_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_7 = and(UInt<1>(0h1), _res_cur_cfg_x_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_104 = bits(io.pmp[3].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_T_105 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_106 = not(_res_hit_T_105) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_107 = or(_res_hit_T_106, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_108 = not(_res_hit_T_107) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_109 = xor(io.addr, _res_hit_T_108) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_T_110 = not(io.pmp[3].mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_T_111 = and(_res_hit_T_109, _res_hit_T_110) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node _res_hit_T_112 = eq(_res_hit_T_111, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_113 = bits(io.pmp[3].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_114 = dshl(UInt<2>(0h3), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_115 = bits(_res_hit_T_114, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_116 = not(_res_hit_T_115) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_T_117 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_118 = not(_res_hit_T_117) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_119 = or(_res_hit_T_118, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_120 = not(_res_hit_T_119) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_121 = lt(io.addr, _res_hit_T_120) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 77:9] node _res_hit_T_122 = eq(_res_hit_T_121, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_T_123 = shl(io.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_124 = not(_res_hit_T_123) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_125 = or(_res_hit_T_124, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_126 = not(_res_hit_T_125) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_127 = lt(io.addr, _res_hit_T_126) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 77:9] node _res_hit_T_128 = and(_res_hit_T_122, _res_hit_T_127) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_129 = and(_res_hit_T_113, _res_hit_T_128) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_4 = mux(_res_hit_T_104, _res_hit_T_112, _res_hit_T_129) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_4 = and(default, _res_ignore_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_186 = eq(_res_T_185, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_188 = eq(_res_T_187, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_190 = eq(_res_T_189, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_192 = eq(_res_T_191, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_194 = eq(_res_T_193, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_196 = eq(_res_T_195, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_198 = and(_res_T_197, res_hit_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_199 = and(_res_T_198, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_201 = and(_res_T_199, _res_T_200) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_203 = and(_res_T_202, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_205 = and(_res_T_203, _res_T_204) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_207 = and(_res_T_206, res_hit_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_208 = and(_res_T_207, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_210 = and(_res_T_208, _res_T_209) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_212 = and(_res_T_211, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_214 = and(_res_T_212, _res_T_213) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_216 = and(_res_T_215, res_hit_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_217 = and(_res_T_216, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_219 = and(_res_T_217, _res_T_218) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_221 = and(_res_T_220, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_223 = and(_res_T_221, _res_T_222) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_4, io.pmp[3] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_9 = and(UInt<1>(0h1), _res_cur_cfg_r_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_9 = and(UInt<1>(0h1), _res_cur_cfg_w_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_9 = and(UInt<1>(0h1), _res_cur_cfg_x_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_130 = bits(io.pmp[2].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_T_131 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_132 = not(_res_hit_T_131) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_133 = or(_res_hit_T_132, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_134 = not(_res_hit_T_133) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_135 = xor(io.addr, _res_hit_T_134) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_T_136 = not(io.pmp[2].mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_T_137 = and(_res_hit_T_135, _res_hit_T_136) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node _res_hit_T_138 = eq(_res_hit_T_137, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_139 = bits(io.pmp[2].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_140 = dshl(UInt<2>(0h3), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_141 = bits(_res_hit_T_140, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_142 = not(_res_hit_T_141) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_T_143 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_144 = not(_res_hit_T_143) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_145 = or(_res_hit_T_144, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_146 = not(_res_hit_T_145) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_147 = lt(io.addr, _res_hit_T_146) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 77:9] node _res_hit_T_148 = eq(_res_hit_T_147, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_T_149 = shl(io.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_150 = not(_res_hit_T_149) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_151 = or(_res_hit_T_150, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_152 = not(_res_hit_T_151) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_153 = lt(io.addr, _res_hit_T_152) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 77:9] node _res_hit_T_154 = and(_res_hit_T_148, _res_hit_T_153) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_155 = and(_res_hit_T_139, _res_hit_T_154) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_5 = mux(_res_hit_T_130, _res_hit_T_138, _res_hit_T_155) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_5 = and(default, _res_ignore_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_231 = eq(_res_T_230, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_233 = eq(_res_T_232, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_235 = eq(_res_T_234, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_237 = eq(_res_T_236, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_239 = eq(_res_T_238, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_241 = eq(_res_T_240, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_243 = and(_res_T_242, res_hit_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_244 = and(_res_T_243, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_246 = and(_res_T_244, _res_T_245) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_248 = and(_res_T_247, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_250 = and(_res_T_248, _res_T_249) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_252 = and(_res_T_251, res_hit_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_253 = and(_res_T_252, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_255 = and(_res_T_253, _res_T_254) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_257 = and(_res_T_256, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_259 = and(_res_T_257, _res_T_258) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_261 = and(_res_T_260, res_hit_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_262 = and(_res_T_261, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_264 = and(_res_T_262, _res_T_263) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_266 = and(_res_T_265, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_268 = and(_res_T_266, _res_T_267) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_5, io.pmp[2] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_11 = and(UInt<1>(0h1), _res_cur_cfg_r_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_11 = and(UInt<1>(0h1), _res_cur_cfg_w_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_11 = and(UInt<1>(0h1), _res_cur_cfg_x_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_156 = bits(io.pmp[1].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_T_157 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_158 = not(_res_hit_T_157) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_159 = or(_res_hit_T_158, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_160 = not(_res_hit_T_159) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_161 = xor(io.addr, _res_hit_T_160) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_T_162 = not(io.pmp[1].mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_T_163 = and(_res_hit_T_161, _res_hit_T_162) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node _res_hit_T_164 = eq(_res_hit_T_163, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_165 = bits(io.pmp[1].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_166 = dshl(UInt<2>(0h3), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_167 = bits(_res_hit_T_166, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_168 = not(_res_hit_T_167) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_T_169 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_170 = not(_res_hit_T_169) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_171 = or(_res_hit_T_170, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_172 = not(_res_hit_T_171) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_173 = lt(io.addr, _res_hit_T_172) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 77:9] node _res_hit_T_174 = eq(_res_hit_T_173, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_T_175 = shl(io.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_176 = not(_res_hit_T_175) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_177 = or(_res_hit_T_176, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_178 = not(_res_hit_T_177) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_179 = lt(io.addr, _res_hit_T_178) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 77:9] node _res_hit_T_180 = and(_res_hit_T_174, _res_hit_T_179) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_181 = and(_res_hit_T_165, _res_hit_T_180) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_6 = mux(_res_hit_T_156, _res_hit_T_164, _res_hit_T_181) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_6 = and(default, _res_ignore_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_276 = eq(_res_T_275, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_278 = eq(_res_T_277, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_280 = eq(_res_T_279, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_282 = eq(_res_T_281, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_284 = eq(_res_T_283, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_286 = eq(_res_T_285, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_288 = and(_res_T_287, res_hit_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_289 = and(_res_T_288, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_291 = and(_res_T_289, _res_T_290) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_293 = and(_res_T_292, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_295 = and(_res_T_293, _res_T_294) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_297 = and(_res_T_296, res_hit_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_298 = and(_res_T_297, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_300 = and(_res_T_298, _res_T_299) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_302 = and(_res_T_301, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_304 = and(_res_T_302, _res_T_303) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_306 = and(_res_T_305, res_hit_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_307 = and(_res_T_306, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_309 = and(_res_T_307, _res_T_308) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_311 = and(_res_T_310, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_313 = and(_res_T_311, _res_T_312) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_6, io.pmp[1] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_13 = and(UInt<1>(0h1), _res_cur_cfg_r_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_13 = and(UInt<1>(0h1), _res_cur_cfg_w_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_13 = and(UInt<1>(0h1), _res_cur_cfg_x_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] node _res_hit_T_182 = bits(io.pmp[0].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _res_hit_T_183 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_184 = not(_res_hit_T_183) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_185 = or(_res_hit_T_184, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_186 = not(_res_hit_T_185) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_187 = xor(io.addr, _res_hit_T_186) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:47] node _res_hit_T_188 = not(io.pmp[0].mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:54] node _res_hit_T_189 = and(_res_hit_T_187, _res_hit_T_188) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:52] node _res_hit_T_190 = eq(_res_hit_T_189, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 63:58] node _res_hit_T_191 = bits(io.pmp[0].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _res_hit_T_192 = dshl(UInt<2>(0h3), io.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _res_hit_T_193 = bits(_res_hit_T_192, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _res_hit_T_194 = not(_res_hit_T_193) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _res_hit_T_195 = shl(pmp0.addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_196 = not(_res_hit_T_195) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_197 = or(_res_hit_T_196, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_198 = not(_res_hit_T_197) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_199 = lt(io.addr, _res_hit_T_198) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 77:9] node _res_hit_T_200 = eq(_res_hit_T_199, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 88:5] node _res_hit_T_201 = shl(io.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _res_hit_T_202 = not(_res_hit_T_201) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _res_hit_T_203 = or(_res_hit_T_202, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _res_hit_T_204 = not(_res_hit_T_203) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _res_hit_T_205 = lt(io.addr, _res_hit_T_204) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 77:9] node _res_hit_T_206 = and(_res_hit_T_200, _res_hit_T_205) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 94:48] node _res_hit_T_207 = and(_res_hit_T_191, _res_hit_T_206) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:61] node res_hit_7 = mux(_res_hit_T_182, _res_hit_T_190, _res_hit_T_207) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 132:8] node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:29] node res_ignore_7 = and(default, _res_ignore_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 164:26] node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 168:32] node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 170:30] node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_321 = eq(_res_T_320, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_323 = eq(_res_T_322, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_325 = eq(_res_T_324, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_327 = eq(_res_T_326, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_329 = eq(_res_T_328, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:26] node _res_T_331 = eq(_res_T_330, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 174:60] node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_333 = and(_res_T_332, res_hit_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_334 = and(_res_T_333, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_336 = and(_res_T_334, _res_T_335) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_338 = and(_res_T_337, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_340 = and(_res_T_338, _res_T_339) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_342 = and(_res_T_341, res_hit_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_343 = and(_res_T_342, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_345 = and(_res_T_343, _res_T_344) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_347 = and(_res_T_346, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_349 = and(_res_T_347, _res_T_348) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:22] node _res_T_351 = and(_res_T_350, res_hit_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:30] node _res_T_352 = and(_res_T_351, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:37] node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:61] node _res_T_354 = and(_res_T_352, _res_T_353) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 177:48] node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:32] node _res_T_356 = and(_res_T_355, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:39] node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:63] node _res_T_358 = and(_res_T_356, _res_T_357) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 178:50] wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] connect res_cur_7, io.pmp[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 181:23] node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:40] node _res_cur_cfg_r_T_15 = and(UInt<1>(0h1), _res_cur_cfg_r_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:26] connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 182:15] node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:40] node _res_cur_cfg_w_T_15 = and(UInt<1>(0h1), _res_cur_cfg_w_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:26] connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 183:15] node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:40] node _res_cur_cfg_x_T_15 = and(UInt<1>(0h1), _res_cur_cfg_x_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:26] connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 184:15] node res = mux(res_hit_7, res_cur_7, _res_T_314) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 185:8] connect io.r, res.cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 188:8] connect io.w, res.cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 189:8] connect io.x, res.cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 190:8] module PMAChecker_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 18:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 18:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 18:7] output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 19:14] node _legal_address_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_1 = cvt(_legal_address_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_3 = asSInt(_legal_address_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_5 = xor(io.paddr, UInt<14>(0h3000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_6 = cvt(_legal_address_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_8 = asSInt(_legal_address_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_10 = xor(io.paddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_11 = cvt(_legal_address_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<17>(0h10000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_13 = asSInt(_legal_address_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_15 = xor(io.paddr, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_16 = cvt(_legal_address_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_18 = asSInt(_legal_address_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_20 = xor(io.paddr, UInt<28>(0hc000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_21 = cvt(_legal_address_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<27>(0h4000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_23 = asSInt(_legal_address_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_25 = xor(io.paddr, UInt<29>(0h10013000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_26 = cvt(_legal_address_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_28 = asSInt(_legal_address_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_30 = xor(io.paddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_31 = cvt(_legal_address_T_30) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_33 = asSInt(_legal_address_T_32) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_35 = xor(io.paddr, UInt<29>(0h10015000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_36 = cvt(_legal_address_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_38 = asSInt(_legal_address_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_40 = xor(io.paddr, UInt<29>(0h10020000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_41 = cvt(_legal_address_T_40) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_43 = asSInt(_legal_address_T_42) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_45 = xor(io.paddr, UInt<29>(0h10021000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_46 = cvt(_legal_address_T_45) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_48 = asSInt(_legal_address_T_47) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_50 = xor(io.paddr, UInt<29>(0h10022000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_51 = cvt(_legal_address_T_50) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_53 = asSInt(_legal_address_T_52) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_55 = xor(io.paddr, UInt<29>(0h10023000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_56 = cvt(_legal_address_T_55) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_58 = asSInt(_legal_address_T_57) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_60 = xor(io.paddr, UInt<29>(0h10024000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_61 = cvt(_legal_address_T_60) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_62 = and(_legal_address_T_61, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_63 = asSInt(_legal_address_T_62) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_64 = eq(_legal_address_T_63, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_65 = xor(io.paddr, UInt<29>(0h10025000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_66 = cvt(_legal_address_T_65) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_67 = and(_legal_address_T_66, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_68 = asSInt(_legal_address_T_67) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_69 = eq(_legal_address_T_68, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_70 = xor(io.paddr, UInt<29>(0h10026000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_71 = cvt(_legal_address_T_70) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_72 = and(_legal_address_T_71, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_73 = asSInt(_legal_address_T_72) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_74 = eq(_legal_address_T_73, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_75 = xor(io.paddr, UInt<29>(0h10027000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_76 = cvt(_legal_address_T_75) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_77 = and(_legal_address_T_76, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_78 = asSInt(_legal_address_T_77) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_79 = eq(_legal_address_T_78, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_80 = xor(io.paddr, UInt<29>(0h10028000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_81 = cvt(_legal_address_T_80) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_82 = and(_legal_address_T_81, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_83 = asSInt(_legal_address_T_82) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_84 = eq(_legal_address_T_83, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_85 = xor(io.paddr, UInt<29>(0h10029000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_86 = cvt(_legal_address_T_85) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_87 = and(_legal_address_T_86, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_88 = asSInt(_legal_address_T_87) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_89 = eq(_legal_address_T_88, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_90 = xor(io.paddr, UInt<29>(0h1002a000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_91 = cvt(_legal_address_T_90) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_92 = and(_legal_address_T_91, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_93 = asSInt(_legal_address_T_92) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_94 = eq(_legal_address_T_93, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _legal_address_T_95 = xor(io.paddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _legal_address_T_96 = cvt(_legal_address_T_95) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _legal_address_T_97 = and(_legal_address_T_96, asSInt(UInt<21>(0h100000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_98 = asSInt(_legal_address_T_97) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _legal_address_T_99 = eq(_legal_address_T_98, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] wire _legal_address_WIRE : UInt<1>[20] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[0], _legal_address_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[1], _legal_address_T_9 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[2], _legal_address_T_14 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[3], _legal_address_T_19 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[4], _legal_address_T_24 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[5], _legal_address_T_29 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[6], _legal_address_T_34 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[7], _legal_address_T_39 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[8], _legal_address_T_44 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[9], _legal_address_T_49 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[10], _legal_address_T_54 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[11], _legal_address_T_59 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[12], _legal_address_T_64 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[13], _legal_address_T_69 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[14], _legal_address_T_74 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[15], _legal_address_T_79 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[16], _legal_address_T_84 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[17], _legal_address_T_89 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[18], _legal_address_T_94 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] connect _legal_address_WIRE[19], _legal_address_T_99 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 612:40] node _legal_address_T_100 = or(_legal_address_WIRE[0], _legal_address_WIRE[1]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_101 = or(_legal_address_T_100, _legal_address_WIRE[2]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_102 = or(_legal_address_T_101, _legal_address_WIRE[3]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_103 = or(_legal_address_T_102, _legal_address_WIRE[4]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_104 = or(_legal_address_T_103, _legal_address_WIRE[5]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_105 = or(_legal_address_T_104, _legal_address_WIRE[6]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_106 = or(_legal_address_T_105, _legal_address_WIRE[7]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_107 = or(_legal_address_T_106, _legal_address_WIRE[8]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_108 = or(_legal_address_T_107, _legal_address_WIRE[9]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_109 = or(_legal_address_T_108, _legal_address_WIRE[10]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_110 = or(_legal_address_T_109, _legal_address_WIRE[11]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_111 = or(_legal_address_T_110, _legal_address_WIRE[12]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_112 = or(_legal_address_T_111, _legal_address_WIRE[13]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_113 = or(_legal_address_T_112, _legal_address_WIRE[14]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_114 = or(_legal_address_T_113, _legal_address_WIRE[15]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_115 = or(_legal_address_T_114, _legal_address_WIRE[16]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_116 = or(_legal_address_T_115, _legal_address_WIRE[17]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _legal_address_T_117 = or(_legal_address_T_116, _legal_address_WIRE[18]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node legal_address = or(_legal_address_T_117, _legal_address_WIRE[19]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 36:58] node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_cacheable_T_5 = and(legal_address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.cacheable, _io_resp_cacheable_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 41:21] node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_r_T_1 = cvt(_io_resp_r_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.r, _io_resp_r_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 42:13] node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_1 = cvt(_io_resp_w_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_5 = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_6 = cvt(_io_resp_w_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_10 = xor(io.paddr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_11 = cvt(_io_resp_w_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_15 = xor(io.paddr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_16 = cvt(_io_resp_w_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_20 = xor(io.paddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_21 = cvt(_io_resp_w_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_25 = xor(io.paddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_26 = cvt(_io_resp_w_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_30 = or(_io_resp_w_T_4, _io_resp_w_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_w_T_31 = or(_io_resp_w_T_30, _io_resp_w_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_w_T_32 = or(_io_resp_w_T_31, _io_resp_w_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_w_T_33 = or(_io_resp_w_T_32, _io_resp_w_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_w_T_34 = or(_io_resp_w_T_33, _io_resp_w_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_w_T_35 = xor(io.paddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_w_T_36 = cvt(_io_resp_w_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_w_T_37 = and(_io_resp_w_T_36, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_38 = asSInt(_io_resp_w_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_w_T_39 = eq(_io_resp_w_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_w_T_40 = mux(_io_resp_w_T_34, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_w_T_41 = mux(_io_resp_w_T_39, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_w_T_42 = or(_io_resp_w_T_40, _io_resp_w_T_41) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_resp_w_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_resp_w_WIRE, _io_resp_w_T_42 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_w_T_43 = and(legal_address, _io_resp_w_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.w, _io_resp_w_T_43 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 43:13] node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_1 = cvt(_io_resp_pp_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_5 = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_10 = xor(io.paddr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_15 = xor(io.paddr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_20 = xor(io.paddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_25 = xor(io.paddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_30 = or(_io_resp_pp_T_4, _io_resp_pp_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_pp_T_31 = or(_io_resp_pp_T_30, _io_resp_pp_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_pp_T_32 = or(_io_resp_pp_T_31, _io_resp_pp_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_pp_T_33 = or(_io_resp_pp_T_32, _io_resp_pp_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_pp_T_34 = or(_io_resp_pp_T_33, _io_resp_pp_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_pp_T_35 = xor(io.paddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_pp_T_36 = cvt(_io_resp_pp_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_pp_T_37 = and(_io_resp_pp_T_36, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_38 = asSInt(_io_resp_pp_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_pp_T_39 = eq(_io_resp_pp_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_pp_T_40 = mux(_io_resp_pp_T_34, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_pp_T_41 = mux(_io_resp_pp_T_39, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_pp_T_42 = or(_io_resp_pp_T_40, _io_resp_pp_T_41) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_resp_pp_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_resp_pp_WIRE, _io_resp_pp_T_42 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_pp_T_43 = and(legal_address, _io_resp_pp_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.pp, _io_resp_pp_T_43 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 44:14] node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_1 = cvt(_io_resp_al_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_5 = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_6 = cvt(_io_resp_al_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_10 = xor(io.paddr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_11 = cvt(_io_resp_al_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_15 = xor(io.paddr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_16 = cvt(_io_resp_al_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_20 = xor(io.paddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_21 = cvt(_io_resp_al_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_25 = xor(io.paddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_26 = cvt(_io_resp_al_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_30 = or(_io_resp_al_T_4, _io_resp_al_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_al_T_31 = or(_io_resp_al_T_30, _io_resp_al_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_al_T_32 = or(_io_resp_al_T_31, _io_resp_al_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_al_T_33 = or(_io_resp_al_T_32, _io_resp_al_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_al_T_34 = or(_io_resp_al_T_33, _io_resp_al_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_al_T_35 = xor(io.paddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_al_T_36 = cvt(_io_resp_al_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_al_T_37 = and(_io_resp_al_T_36, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_38 = asSInt(_io_resp_al_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_al_T_39 = eq(_io_resp_al_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_al_T_40 = mux(_io_resp_al_T_34, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_al_T_41 = mux(_io_resp_al_T_39, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_al_T_42 = or(_io_resp_al_T_40, _io_resp_al_T_41) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_resp_al_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_resp_al_WIRE, _io_resp_al_T_42 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_al_T_43 = and(legal_address, _io_resp_al_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.al, _io_resp_al_T_43 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 45:14] node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_1 = cvt(_io_resp_aa_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0he8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_5 = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_10 = xor(io.paddr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_15 = xor(io.paddr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0hf8015000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_20 = xor(io.paddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0hf8014000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_25 = xor(io.paddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_30 = or(_io_resp_aa_T_4, _io_resp_aa_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_aa_T_31 = or(_io_resp_aa_T_30, _io_resp_aa_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_aa_T_32 = or(_io_resp_aa_T_31, _io_resp_aa_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_aa_T_33 = or(_io_resp_aa_T_32, _io_resp_aa_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_aa_T_34 = or(_io_resp_aa_T_33, _io_resp_aa_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_aa_T_35 = xor(io.paddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_aa_T_36 = cvt(_io_resp_aa_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_aa_T_37 = and(_io_resp_aa_T_36, asSInt(UInt<33>(0hf8010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_38 = asSInt(_io_resp_aa_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_aa_T_39 = eq(_io_resp_aa_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_aa_T_40 = mux(_io_resp_aa_T_34, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_aa_T_41 = mux(_io_resp_aa_T_39, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_aa_T_42 = or(_io_resp_aa_T_40, _io_resp_aa_T_41) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_resp_aa_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_resp_aa_WIRE, _io_resp_aa_T_42 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_aa_T_43 = and(legal_address, _io_resp_aa_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.aa, _io_resp_aa_T_43 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 46:14] node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_x_T_1 = cvt(_io_resp_x_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<32>(0h7a000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_x_T_5 = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_x_T_6 = cvt(_io_resp_x_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0hfa004000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_x_T_10 = or(_io_resp_x_T_4, _io_resp_x_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_x_T_11 = xor(io.paddr, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_x_T_12 = cvt(_io_resp_x_T_11) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_x_T_13 = and(_io_resp_x_T_12, asSInt(UInt<33>(0hfa000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_14 = asSInt(_io_resp_x_T_13) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_15 = eq(_io_resp_x_T_14, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_x_T_16 = xor(io.paddr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_x_T_17 = cvt(_io_resp_x_T_16) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_x_T_18 = and(_io_resp_x_T_17, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_19 = asSInt(_io_resp_x_T_18) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_20 = eq(_io_resp_x_T_19, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_x_T_21 = xor(io.paddr, UInt<29>(0h10000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_x_T_22 = cvt(_io_resp_x_T_21) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_x_T_23 = and(_io_resp_x_T_22, asSInt(UInt<33>(0hfa000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_24 = asSInt(_io_resp_x_T_23) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_x_T_25 = eq(_io_resp_x_T_24, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_x_T_26 = or(_io_resp_x_T_15, _io_resp_x_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_x_T_28 = mux(_io_resp_x_T_10, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_x_T_29 = mux(_io_resp_x_T_27, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_x_T_30 = or(_io_resp_x_T_28, _io_resp_x_T_29) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_resp_x_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_resp_x_WIRE, _io_resp_x_T_30 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_x_T_31 = and(legal_address, _io_resp_x_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.x, _io_resp_x_T_31 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 47:13] node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_1 = cvt(_io_resp_eff_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_5 = xor(io.paddr, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_10 = xor(io.paddr, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_15 = xor(io.paddr, UInt<29>(0h10000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0hfa018000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_20 = xor(io.paddr, UInt<29>(0h10008000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_25 = xor(io.paddr, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_30 = xor(io.paddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_31 = cvt(_io_resp_eff_T_30) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_32 = and(_io_resp_eff_T_31, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_33 = asSInt(_io_resp_eff_T_32) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_34 = eq(_io_resp_eff_T_33, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_35 = or(_io_resp_eff_T_4, _io_resp_eff_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_36 = or(_io_resp_eff_T_35, _io_resp_eff_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_37 = or(_io_resp_eff_T_36, _io_resp_eff_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_38 = or(_io_resp_eff_T_37, _io_resp_eff_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_39 = or(_io_resp_eff_T_38, _io_resp_eff_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_40 = or(_io_resp_eff_T_39, _io_resp_eff_T_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_41 = xor(io.paddr, UInt<13>(0h1000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_42 = cvt(_io_resp_eff_T_41) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_43 = and(_io_resp_eff_T_42, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_44 = asSInt(_io_resp_eff_T_43) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_45 = eq(_io_resp_eff_T_44, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_46 = xor(io.paddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_47 = cvt(_io_resp_eff_T_46) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_48 = and(_io_resp_eff_T_47, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_49 = asSInt(_io_resp_eff_T_48) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_50 = eq(_io_resp_eff_T_49, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_51 = xor(io.paddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _io_resp_eff_T_52 = cvt(_io_resp_eff_T_51) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _io_resp_eff_T_53 = and(_io_resp_eff_T_52, asSInt(UInt<33>(0hfa000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_54 = asSInt(_io_resp_eff_T_53) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _io_resp_eff_T_55 = eq(_io_resp_eff_T_54, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _io_resp_eff_T_56 = or(_io_resp_eff_T_45, _io_resp_eff_T_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_57 = or(_io_resp_eff_T_56, _io_resp_eff_T_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 629:89] node _io_resp_eff_T_58 = mux(_io_resp_eff_T_40, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_eff_T_59 = mux(_io_resp_eff_T_57, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_eff_T_60 = or(_io_resp_eff_T_58, _io_resp_eff_T_59) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_resp_eff_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_resp_eff_WIRE, _io_resp_eff_T_60 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_resp_eff_T_61 = and(legal_address, _io_resp_eff_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 39:19] connect io.resp.eff, _io_resp_eff_T_61 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMA.scala 48:15] module OptimizationBarrier_TLBEntryData_15 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module OptimizationBarrier_TLBEntryData_16 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module OptimizationBarrier_TLBEntryData_17 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module OptimizationBarrier_TLBEntryData_18 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module OptimizationBarrier_TLBEntryData_19 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module OptimizationBarrier_TLBEntryData_20 : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module ITLB : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 318:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 318:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 318:7] output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<34>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<34>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<33>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<21>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<33>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 320:14] invalidate io.ptw.customCSRs.csrs[0].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[0].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[0].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[0].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[0].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[0].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[0].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[1].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[2].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] invalidate io.ptw.customCSRs.csrs[3].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 332:21] node vpn = bits(io.req.bits.vaddr, 32, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 335:30] reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<21>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[1][1], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 339:29] reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<21>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 341:30] reg special_entry : { level : UInt<2>, tag_vpn : UInt<21>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 346:56] regreset state : UInt<2>, clock, reset, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 352:22] reg r_refill_tag : UInt<21>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 354:25] reg r_superpage_repl_addr : UInt<2>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 355:34] reg r_sectored_repl_addr : UInt<0>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 356:33] reg r_sectored_hit : { valid : UInt<1>, bits : UInt<0>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 357:27] reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 358:28] reg r_vstage1_en : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 359:25] reg r_stage2_en : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 360:24] reg r_need_gpa : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 361:23] reg r_gpa_valid : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 362:24] reg r_gpa : UInt<33>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 363:18] reg r_gpa_vpn : UInt<21>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 364:22] reg r_gpa_is_pte : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 365:25] node priv_v = and(UInt<1>(0h0), io.req.bits.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 369:34] node priv_s = bits(io.req.bits.prv, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 370:20] node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 372:27] node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 373:17] node _stage1_en_T = bits(satp.mode, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 374:41] node stage1_en = and(UInt<1>(0h0), _stage1_en_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 374:29] node _vstage1_en_T = and(UInt<1>(0h0), priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 376:38] node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 376:68] node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 376:48] node _stage2_en_T = and(UInt<1>(0h0), priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 378:38] node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 378:68] node stage2_en = and(_stage2_en_T, _stage2_en_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 378:48] node _vm_enabled_T = or(stage1_en, stage2_en) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 399:31] node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 399:45] node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 399:64] node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 399:61] regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 402:37] node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 403:52] node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 403:37] node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 403:81] node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 403:78] node do_refill = and(UInt<1>(0h0), io.ptw.resp.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 408:29] node _invalidate_refill_T = eq(state, UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 410:88] node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 413:32] wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _mpu_ppn_WIRE_1 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE_1, special_entry.data[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_14 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect mpu_ppn_barrier.clock, clock connect mpu_ppn_barrier.reset, reset connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] node _mpu_ppn_T_24 = shr(io.req.bits.vaddr, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 413:146] node _mpu_ppn_T_25 = mux(_mpu_ppn_T, mpu_ppn_barrier.io.y.ppn, _mpu_ppn_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 413:20] node mpu_ppn = mux(do_refill, UInt<1>(0h0), _mpu_ppn_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 412:20] node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 414:52] node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 414:25] node _mpu_priv_T = or(do_refill, io.req.bits.passthrough) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 415:52] node _mpu_priv_T_1 = and(UInt<1>(0h0), _mpu_priv_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 415:38] node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 415:103] node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 415:27] inst pmp of PMPChecker_s2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 416:19] connect pmp.clock, clock connect pmp.reset, reset connect pmp.io.addr, mpu_physaddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 417:15] connect pmp.io.size, io.req.bits.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 418:15] connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 419:14] connect pmp.io.prv, mpu_priv @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 420:14] inst pma of PMAChecker_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 422:19] connect pma.clock, clock connect pma.reset, reset connect pma.io.paddr, mpu_physaddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 423:16] node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 425:41] node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_1 = cvt(_homogeneous_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_3 = asSInt(_homogeneous_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_6 = cvt(_homogeneous_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_8 = asSInt(_homogeneous_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_11 = cvt(_homogeneous_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_13 = asSInt(_homogeneous_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_15 = xor(mpu_physaddr, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_16 = cvt(_homogeneous_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<17>(0h10000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_18 = asSInt(_homogeneous_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_20 = xor(mpu_physaddr, UInt<28>(0hc000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_21 = cvt(_homogeneous_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<27>(0h4000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_23 = asSInt(_homogeneous_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_25 = xor(mpu_physaddr, UInt<29>(0h10013000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_26 = cvt(_homogeneous_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_28 = asSInt(_homogeneous_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_30 = xor(mpu_physaddr, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_31 = cvt(_homogeneous_T_30) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<14>(0h2000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_33 = asSInt(_homogeneous_T_32) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_35 = xor(mpu_physaddr, UInt<29>(0h10020000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_36 = cvt(_homogeneous_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<16>(0h8000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_38 = asSInt(_homogeneous_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10028000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_41 = cvt(_homogeneous_T_40) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<14>(0h2000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_43 = asSInt(_homogeneous_T_42) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_45 = xor(mpu_physaddr, UInt<29>(0h1002a000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_46 = cvt(_homogeneous_T_45) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_48 = asSInt(_homogeneous_T_47) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_50 = xor(mpu_physaddr, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_51 = cvt(_homogeneous_T_50) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_52 = and(_homogeneous_T_51, asSInt(UInt<21>(0h100000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_53 = asSInt(_homogeneous_T_52) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_54 = eq(_homogeneous_T_53, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_55 = or(UInt<1>(0h0), _homogeneous_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_59 = or(_homogeneous_T_58, _homogeneous_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_60 = or(_homogeneous_T_59, _homogeneous_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_61 = or(_homogeneous_T_60, _homogeneous_T_34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_62 = or(_homogeneous_T_61, _homogeneous_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_63 = or(_homogeneous_T_62, _homogeneous_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_64 = or(_homogeneous_T_63, _homogeneous_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node homogeneous = or(_homogeneous_T_64, _homogeneous_T_54) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _homogeneous_T_65 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _homogeneous_T_66 = xor(mpu_physaddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_67 = cvt(_homogeneous_T_66) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_68 = and(_homogeneous_T_67, asSInt(UInt<33>(0h98010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_69 = asSInt(_homogeneous_T_68) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_70 = eq(_homogeneous_T_69, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_71 = or(UInt<1>(0h0), _homogeneous_T_70) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:66] node _homogeneous_T_72 = eq(_homogeneous_T_71, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _homogeneous_T_73 = xor(mpu_physaddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_74 = cvt(_homogeneous_T_73) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_75 = and(_homogeneous_T_74, asSInt(UInt<30>(0h1a000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_76 = asSInt(_homogeneous_T_75) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_77 = eq(_homogeneous_T_76, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_78 = or(UInt<1>(0h0), _homogeneous_T_77) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 85:66] node _homogeneous_T_79 = xor(mpu_physaddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_80 = cvt(_homogeneous_T_79) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_81 = and(_homogeneous_T_80, asSInt(UInt<33>(0h98010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_82 = asSInt(_homogeneous_T_81) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_83 = eq(_homogeneous_T_82, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_84 = or(UInt<1>(0h0), _homogeneous_T_83) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:66] node _homogeneous_T_85 = eq(_homogeneous_T_84, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _homogeneous_T_86 = xor(mpu_physaddr, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _homogeneous_T_87 = cvt(_homogeneous_T_86) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _homogeneous_T_88 = and(_homogeneous_T_87, asSInt(UInt<33>(0h98010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_89 = asSInt(_homogeneous_T_88) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _homogeneous_T_90 = eq(_homogeneous_T_89, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _homogeneous_T_91 = or(UInt<1>(0h0), _homogeneous_T_90) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:66] node _homogeneous_T_92 = eq(_homogeneous_T_91, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 428:39] node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 428:50] node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 429:33] node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 429:30] node prot_r = and(_prot_r_T_1, pmp.io.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 429:55] node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 430:33] node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 430:30] node prot_w = and(_prot_w_T_1, pmp.io.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 430:55] node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 434:33] node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 434:30] node prot_x = and(_prot_x_T_1, pmp.io.x) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 434:55] node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _sector_hits_T_4 = shr(_sector_hits_T_3, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 172:55] node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _superpage_hits_T_1 = shr(_superpage_hits_T, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _superpage_hits_T_3 = eq(superpage_entries[0].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _superpage_hits_T_4 = and(_superpage_hits_T_2, _superpage_hits_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node superpage_hits_0 = and(superpage_entries[0].valid[0], _superpage_hits_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node _superpage_hits_T_5 = xor(superpage_entries[1].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _superpage_hits_T_6 = shr(_superpage_hits_T_5, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _superpage_hits_T_8 = eq(superpage_entries[1].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _superpage_hits_T_9 = and(_superpage_hits_T_7, _superpage_hits_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node superpage_hits_1 = and(superpage_entries[1].valid[0], _superpage_hits_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node _superpage_hits_T_10 = xor(superpage_entries[2].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _superpage_hits_T_11 = shr(_superpage_hits_T_10, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _superpage_hits_T_13 = eq(superpage_entries[2].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _superpage_hits_T_14 = and(_superpage_hits_T_12, _superpage_hits_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node superpage_hits_2 = and(superpage_entries[2].valid[0], _superpage_hits_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node _superpage_hits_T_15 = xor(superpage_entries[3].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _superpage_hits_T_16 = shr(_superpage_hits_T_15, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _superpage_hits_T_17 = eq(_superpage_hits_T_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _superpage_hits_T_18 = eq(superpage_entries[3].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _superpage_hits_T_19 = and(_superpage_hits_T_17, _superpage_hits_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node superpage_hits_3 = and(superpage_entries[3].valid[0], _superpage_hits_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_idx = bits(vpn, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _hitsVec_T_1 = shr(_hitsVec_T, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_0 = and(vm_enabled, _hitsVec_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 440:44] node _hitsVec_T_6 = xor(superpage_entries[0].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _hitsVec_T_7 = shr(_hitsVec_T_6, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _hitsVec_T_9 = eq(superpage_entries[0].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node _hitsVec_T_11 = and(superpage_entries[0].valid[0], _hitsVec_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_1 = and(vm_enabled, _hitsVec_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 440:44] node _hitsVec_T_12 = xor(superpage_entries[1].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _hitsVec_T_13 = shr(_hitsVec_T_12, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _hitsVec_T_15 = eq(superpage_entries[1].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node _hitsVec_T_17 = and(superpage_entries[1].valid[0], _hitsVec_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_2 = and(vm_enabled, _hitsVec_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 440:44] node _hitsVec_T_18 = xor(superpage_entries[2].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _hitsVec_T_19 = shr(_hitsVec_T_18, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _hitsVec_T_21 = eq(superpage_entries[2].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node _hitsVec_T_23 = and(superpage_entries[2].valid[0], _hitsVec_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_3 = and(vm_enabled, _hitsVec_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 440:44] node _hitsVec_T_24 = xor(superpage_entries[3].tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _hitsVec_T_25 = shr(_hitsVec_T_24, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _hitsVec_T_27 = eq(superpage_entries[3].tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _hitsVec_T_28 = and(_hitsVec_T_26, _hitsVec_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node _hitsVec_T_29 = and(superpage_entries[3].valid[0], _hitsVec_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_4 = and(vm_enabled, _hitsVec_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 440:44] node _hitsVec_T_30 = xor(special_entry.tag_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:61] node _hitsVec_T_31 = shr(_hitsVec_T_30, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:68] node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:86] node _hitsVec_T_33 = eq(special_entry.tag_v, priv_v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:105] node _hitsVec_T_34 = and(_hitsVec_T_32, _hitsVec_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 174:95] node _hitsVec_T_35 = and(special_entry.valid[0], _hitsVec_T_34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 188:18] node hitsVec_5 = and(vm_enabled, _hitsVec_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 440:44] node real_hits_lo_hi = cat(hitsVec_2, hitsVec_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node real_hits_lo = cat(real_hits_lo_hi, hitsVec_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node real_hits_hi_hi = cat(hitsVec_5, hitsVec_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node real_hits_hi = cat(real_hits_hi_hi, hitsVec_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node real_hits = cat(real_hits_hi, real_hits_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hits_T = eq(vm_enabled, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 442:18] node hits = cat(_hits_T, real_hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 442:17] when do_refill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 446:20] node refill_v = or(r_vstage1_en, r_stage2_en) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 448:33] wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 449:24] connect newEntry.ppn, io.ptw.resp.bits.pte.ppn @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 450:18] connect newEntry.c, cacheable @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 451:16] connect newEntry.u, io.ptw.resp.bits.pte.u @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 452:16] node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 453:25] connect newEntry.g, _newEntry_g_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 453:16] connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 454:21] connect newEntry.ae_final, io.ptw.resp.bits.ae_final @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 455:23] node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 456:53] node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 456:84] connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 456:24] connect newEntry.pf, io.ptw.resp.bits.pf @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 457:17] connect newEntry.gf, io.ptw.resp.bits.gf @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 458:17] connect newEntry.hr, io.ptw.resp.bits.hr @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 459:17] connect newEntry.hw, io.ptw.resp.bits.hw @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 460:17] connect newEntry.hx, io.ptw.resp.bits.hx @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 461:17] node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:47] node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:44] node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:38] node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:32] node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:52] node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 149:35] connect newEntry.sr, _newEntry_sr_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 462:17] node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:47] node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:44] node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:38] node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:32] node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:52] node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 151:35] node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 151:40] connect newEntry.sw, _newEntry_sw_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 463:17] node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:47] node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:44] node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:38] node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:32] node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:52] node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 153:35] connect newEntry.sx, _newEntry_sx_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 464:17] connect newEntry.pr, prot_r @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 465:17] connect newEntry.pw, prot_w @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 466:17] connect newEntry.px, prot_x @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 467:17] connect newEntry.ppp, pma.io.resp.pp @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 468:18] connect newEntry.pal, pma.io.resp.al @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 469:18] connect newEntry.paa, pma.io.resp.aa @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 470:18] connect newEntry.eff, pma.io.resp.eff @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 471:18] connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 472:35] node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 474:39] node _T_1 = and(UInt<1>(0h1), _T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 474:36] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 474:70] connect special_entry.tag_vpn, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 211:18] connect special_entry.tag_v, refill_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 212:16] node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect special_entry.level, _special_entry_level_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 213:16] connect special_entry.valid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 216:16] node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] connect special_entry.data[0], _special_entry_data_0_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:15] else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 476:40] when _T_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 476:58] node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 477:45] node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 477:22] node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:82] when _T_3 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:91] connect superpage_entries[0].tag_vpn, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 211:18] connect superpage_entries[0].tag_v, refill_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 212:16] node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect superpage_entries[0].level, _superpage_entries_0_level_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 213:16] connect superpage_entries[0].valid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 216:16] node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:15] when invalidate_refill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 480:34] connect superpage_entries[0].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:82] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:91] connect superpage_entries[1].tag_vpn, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 211:18] connect superpage_entries[1].tag_v, refill_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 212:16] node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect superpage_entries[1].level, _superpage_entries_1_level_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 213:16] connect superpage_entries[1].valid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 216:16] node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:15] when invalidate_refill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 480:34] connect superpage_entries[1].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:82] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:91] connect superpage_entries[2].tag_vpn, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 211:18] connect superpage_entries[2].tag_v, refill_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 212:16] node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect superpage_entries[2].level, _superpage_entries_2_level_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 213:16] connect superpage_entries[2].valid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 216:16] node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:15] when invalidate_refill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 480:34] connect superpage_entries[2].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:82] when _T_6 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 478:91] connect superpage_entries[3].tag_vpn, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 211:18] connect superpage_entries[3].tag_v, refill_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 212:16] node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect superpage_entries[3].level, _superpage_entries_3_level_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 213:16] connect superpage_entries[3].valid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 216:16] node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:15] when invalidate_refill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 480:34] connect superpage_entries[3].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] else : node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 485:22] node _T_7 = eq(waddr_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 486:75] when _T_7 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 486:84] node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 487:15] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 487:38] connect sectored_entries[0][0].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].valid[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].valid[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].valid[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].tag_vpn, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 211:18] connect sectored_entries[0][0].tag_v, refill_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 212:16] connect sectored_entries[0][0].level, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 213:16] node idx = bits(r_refill_tag, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect sectored_entries[0][0].valid[idx], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 216:16] node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:24] connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 217:15] when invalidate_refill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 489:34] connect sectored_entries[0][0].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].valid[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].valid[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect sectored_entries[0][0].valid[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 220:46] connect r_gpa_valid, io.ptw.resp.bits.gpa.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 493:17] connect r_gpa, io.ptw.resp.bits.gpa.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 494:11] connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 495:18] node _entries_T = bits(vpn, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _entries_WIRE_1 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_1 = bits(_entries_WIRE_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.fragmented_superpage, _entries_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_2 = bits(_entries_WIRE_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.c, _entries_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_3 = bits(_entries_WIRE_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.eff, _entries_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_4 = bits(_entries_WIRE_1, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.paa, _entries_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_5 = bits(_entries_WIRE_1, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.pal, _entries_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_6 = bits(_entries_WIRE_1, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.ppp, _entries_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_7 = bits(_entries_WIRE_1, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.pr, _entries_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_8 = bits(_entries_WIRE_1, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.px, _entries_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_9 = bits(_entries_WIRE_1, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.pw, _entries_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_10 = bits(_entries_WIRE_1, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.hr, _entries_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_11 = bits(_entries_WIRE_1, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.hx, _entries_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_12 = bits(_entries_WIRE_1, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.hw, _entries_T_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_13 = bits(_entries_WIRE_1, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.sr, _entries_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_14 = bits(_entries_WIRE_1, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.sx, _entries_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_15 = bits(_entries_WIRE_1, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.sw, _entries_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_16 = bits(_entries_WIRE_1, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.gf, _entries_T_16 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_17 = bits(_entries_WIRE_1, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.pf, _entries_T_17 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_18 = bits(_entries_WIRE_1, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.ae_stage2, _entries_T_18 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_19 = bits(_entries_WIRE_1, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.ae_final, _entries_T_19 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_20 = bits(_entries_WIRE_1, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.ae_ptw, _entries_T_20 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_21 = bits(_entries_WIRE_1, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.g, _entries_T_21 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_22 = bits(_entries_WIRE_1, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.u, _entries_T_22 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_23 = bits(_entries_WIRE_1, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE.ppn, _entries_T_23 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst entries_barrier of OptimizationBarrier_TLBEntryData_15 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.c, _entries_WIRE.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.eff, _entries_WIRE.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.paa, _entries_WIRE.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.pal, _entries_WIRE.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.ppp, _entries_WIRE.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.pr, _entries_WIRE.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.px, _entries_WIRE.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.pw, _entries_WIRE.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.hr, _entries_WIRE.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.hx, _entries_WIRE.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.hw, _entries_WIRE.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.sr, _entries_WIRE.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.sx, _entries_WIRE.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.sw, _entries_WIRE.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.gf, _entries_WIRE.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.pf, _entries_WIRE.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.g, _entries_WIRE.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.u, _entries_WIRE.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier.io.x.ppn, _entries_WIRE.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _entries_WIRE_3 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_3, superpage_entries[0].data[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_24 = bits(_entries_WIRE_3, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.fragmented_superpage, _entries_T_24 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_25 = bits(_entries_WIRE_3, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.c, _entries_T_25 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_26 = bits(_entries_WIRE_3, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.eff, _entries_T_26 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_27 = bits(_entries_WIRE_3, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.paa, _entries_T_27 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_28 = bits(_entries_WIRE_3, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.pal, _entries_T_28 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_29 = bits(_entries_WIRE_3, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.ppp, _entries_T_29 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_30 = bits(_entries_WIRE_3, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.pr, _entries_T_30 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_31 = bits(_entries_WIRE_3, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.px, _entries_T_31 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_32 = bits(_entries_WIRE_3, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.pw, _entries_T_32 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_33 = bits(_entries_WIRE_3, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.hr, _entries_T_33 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_34 = bits(_entries_WIRE_3, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.hx, _entries_T_34 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_35 = bits(_entries_WIRE_3, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.hw, _entries_T_35 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_36 = bits(_entries_WIRE_3, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.sr, _entries_T_36 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_37 = bits(_entries_WIRE_3, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.sx, _entries_T_37 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_38 = bits(_entries_WIRE_3, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.sw, _entries_T_38 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_39 = bits(_entries_WIRE_3, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.gf, _entries_T_39 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_40 = bits(_entries_WIRE_3, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.pf, _entries_T_40 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_41 = bits(_entries_WIRE_3, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.ae_stage2, _entries_T_41 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_42 = bits(_entries_WIRE_3, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.ae_final, _entries_T_42 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_43 = bits(_entries_WIRE_3, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.ae_ptw, _entries_T_43 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_44 = bits(_entries_WIRE_3, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.g, _entries_T_44 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_45 = bits(_entries_WIRE_3, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.u, _entries_T_45 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_46 = bits(_entries_WIRE_3, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_2.ppn, _entries_T_46 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_16 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.c, _entries_WIRE_2.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.px, _entries_WIRE_2.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.g, _entries_WIRE_2.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.u, _entries_WIRE_2.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _entries_WIRE_5 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_5, superpage_entries[1].data[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_47 = bits(_entries_WIRE_5, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.fragmented_superpage, _entries_T_47 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_48 = bits(_entries_WIRE_5, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.c, _entries_T_48 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_49 = bits(_entries_WIRE_5, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.eff, _entries_T_49 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_50 = bits(_entries_WIRE_5, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.paa, _entries_T_50 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_51 = bits(_entries_WIRE_5, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.pal, _entries_T_51 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_52 = bits(_entries_WIRE_5, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.ppp, _entries_T_52 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_53 = bits(_entries_WIRE_5, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.pr, _entries_T_53 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_54 = bits(_entries_WIRE_5, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.px, _entries_T_54 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_55 = bits(_entries_WIRE_5, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.pw, _entries_T_55 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_56 = bits(_entries_WIRE_5, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.hr, _entries_T_56 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_57 = bits(_entries_WIRE_5, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.hx, _entries_T_57 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_58 = bits(_entries_WIRE_5, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.hw, _entries_T_58 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_59 = bits(_entries_WIRE_5, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.sr, _entries_T_59 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_60 = bits(_entries_WIRE_5, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.sx, _entries_T_60 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_61 = bits(_entries_WIRE_5, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.sw, _entries_T_61 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_62 = bits(_entries_WIRE_5, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.gf, _entries_T_62 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_63 = bits(_entries_WIRE_5, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.pf, _entries_T_63 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_64 = bits(_entries_WIRE_5, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.ae_stage2, _entries_T_64 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_65 = bits(_entries_WIRE_5, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.ae_final, _entries_T_65 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_66 = bits(_entries_WIRE_5, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.ae_ptw, _entries_T_66 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_67 = bits(_entries_WIRE_5, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.g, _entries_T_67 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_68 = bits(_entries_WIRE_5, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.u, _entries_T_68 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_69 = bits(_entries_WIRE_5, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_4.ppn, _entries_T_69 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_17 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.c, _entries_WIRE_4.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.px, _entries_WIRE_4.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.g, _entries_WIRE_4.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.u, _entries_WIRE_4.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _entries_WIRE_7 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_7, superpage_entries[2].data[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_70 = bits(_entries_WIRE_7, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.fragmented_superpage, _entries_T_70 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_71 = bits(_entries_WIRE_7, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.c, _entries_T_71 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_72 = bits(_entries_WIRE_7, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.eff, _entries_T_72 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_73 = bits(_entries_WIRE_7, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.paa, _entries_T_73 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_74 = bits(_entries_WIRE_7, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.pal, _entries_T_74 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_75 = bits(_entries_WIRE_7, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.ppp, _entries_T_75 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_76 = bits(_entries_WIRE_7, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.pr, _entries_T_76 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_77 = bits(_entries_WIRE_7, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.px, _entries_T_77 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_78 = bits(_entries_WIRE_7, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.pw, _entries_T_78 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_79 = bits(_entries_WIRE_7, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.hr, _entries_T_79 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_80 = bits(_entries_WIRE_7, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.hx, _entries_T_80 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_81 = bits(_entries_WIRE_7, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.hw, _entries_T_81 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_82 = bits(_entries_WIRE_7, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.sr, _entries_T_82 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_83 = bits(_entries_WIRE_7, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.sx, _entries_T_83 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_84 = bits(_entries_WIRE_7, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.sw, _entries_T_84 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_85 = bits(_entries_WIRE_7, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.gf, _entries_T_85 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_86 = bits(_entries_WIRE_7, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.pf, _entries_T_86 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_87 = bits(_entries_WIRE_7, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.ae_stage2, _entries_T_87 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_88 = bits(_entries_WIRE_7, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.ae_final, _entries_T_88 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_89 = bits(_entries_WIRE_7, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.ae_ptw, _entries_T_89 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_90 = bits(_entries_WIRE_7, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.g, _entries_T_90 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_91 = bits(_entries_WIRE_7, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.u, _entries_T_91 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_92 = bits(_entries_WIRE_7, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_6.ppn, _entries_T_92 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_18 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.c, _entries_WIRE_6.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.px, _entries_WIRE_6.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.g, _entries_WIRE_6.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.u, _entries_WIRE_6.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _entries_WIRE_9 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_9, superpage_entries[3].data[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_93 = bits(_entries_WIRE_9, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.fragmented_superpage, _entries_T_93 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_94 = bits(_entries_WIRE_9, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.c, _entries_T_94 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_95 = bits(_entries_WIRE_9, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.eff, _entries_T_95 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_96 = bits(_entries_WIRE_9, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.paa, _entries_T_96 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_97 = bits(_entries_WIRE_9, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.pal, _entries_T_97 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_98 = bits(_entries_WIRE_9, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.ppp, _entries_T_98 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_99 = bits(_entries_WIRE_9, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.pr, _entries_T_99 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_100 = bits(_entries_WIRE_9, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.px, _entries_T_100 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_101 = bits(_entries_WIRE_9, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.pw, _entries_T_101 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_102 = bits(_entries_WIRE_9, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.hr, _entries_T_102 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_103 = bits(_entries_WIRE_9, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.hx, _entries_T_103 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_104 = bits(_entries_WIRE_9, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.hw, _entries_T_104 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_105 = bits(_entries_WIRE_9, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.sr, _entries_T_105 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_106 = bits(_entries_WIRE_9, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.sx, _entries_T_106 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_107 = bits(_entries_WIRE_9, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.sw, _entries_T_107 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_108 = bits(_entries_WIRE_9, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.gf, _entries_T_108 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_109 = bits(_entries_WIRE_9, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.pf, _entries_T_109 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_110 = bits(_entries_WIRE_9, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.ae_stage2, _entries_T_110 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_111 = bits(_entries_WIRE_9, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.ae_final, _entries_T_111 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_112 = bits(_entries_WIRE_9, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.ae_ptw, _entries_T_112 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_113 = bits(_entries_WIRE_9, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.g, _entries_T_113 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_114 = bits(_entries_WIRE_9, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.u, _entries_T_114 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_115 = bits(_entries_WIRE_9, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_8.ppn, _entries_T_115 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_19 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.c, _entries_WIRE_8.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.px, _entries_WIRE_8.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.g, _entries_WIRE_8.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.u, _entries_WIRE_8.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] wire _entries_WIRE_11 : UInt<42> @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_11, special_entry.data[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_116 = bits(_entries_WIRE_11, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.fragmented_superpage, _entries_T_116 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_117 = bits(_entries_WIRE_11, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.c, _entries_T_117 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_118 = bits(_entries_WIRE_11, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.eff, _entries_T_118 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_119 = bits(_entries_WIRE_11, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.paa, _entries_T_119 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_120 = bits(_entries_WIRE_11, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.pal, _entries_T_120 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_121 = bits(_entries_WIRE_11, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.ppp, _entries_T_121 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_122 = bits(_entries_WIRE_11, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.pr, _entries_T_122 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_123 = bits(_entries_WIRE_11, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.px, _entries_T_123 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_124 = bits(_entries_WIRE_11, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.pw, _entries_T_124 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_125 = bits(_entries_WIRE_11, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.hr, _entries_T_125 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_126 = bits(_entries_WIRE_11, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.hx, _entries_T_126 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_127 = bits(_entries_WIRE_11, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.hw, _entries_T_127 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_128 = bits(_entries_WIRE_11, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.sr, _entries_T_128 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_129 = bits(_entries_WIRE_11, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.sx, _entries_T_129 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_130 = bits(_entries_WIRE_11, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.sw, _entries_T_130 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_131 = bits(_entries_WIRE_11, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.gf, _entries_T_131 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_132 = bits(_entries_WIRE_11, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.pf, _entries_T_132 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_133 = bits(_entries_WIRE_11, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.ae_stage2, _entries_T_133 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_134 = bits(_entries_WIRE_11, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.ae_final, _entries_T_134 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_135 = bits(_entries_WIRE_11, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.ae_ptw, _entries_T_135 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_136 = bits(_entries_WIRE_11, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.g, _entries_T_136 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_137 = bits(_entries_WIRE_11, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.u, _entries_T_137 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] node _entries_T_138 = bits(_entries_WIRE_11, 41, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] connect _entries_WIRE_10.ppn, _entries_T_138 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 170:77] inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_20 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.c, _entries_WIRE_10.c @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.px, _entries_WIRE_10.px @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.g, _entries_WIRE_10.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.u, _entries_WIRE_10.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] node _ppn_T = eq(vm_enabled, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 502:30] node _ppn_T_1 = bits(vpn, 19, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 502:125] node _ppn_T_2 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_3 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_4 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_5 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_6 = mux(hitsVec_4, entries_barrier_4.io.y.ppn, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_7 = mux(hitsVec_5, entries_barrier_5.io.y.ppn, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_8 = mux(_ppn_T, _ppn_T_1, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_9 = or(_ppn_T_2, _ppn_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_10 = or(_ppn_T_9, _ppn_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_11 = or(_ppn_T_10, _ppn_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_12 = or(_ppn_T_11, _ppn_T_6) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_13 = or(_ppn_T_12, _ppn_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _ppn_T_14 = or(_ppn_T_13, _ppn_T_8) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire ppn : UInt<20> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect ppn, _ppn_T_14 @[src/main/scala/chisel3/util/Mux.scala 30:73] node ptw_ae_array_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, entries_barrier.io.y.ae_ptw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_ae_array_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, entries_barrier_3.io.y.ae_ptw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 506:25] node final_ae_array_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node final_ae_array_lo = cat(final_ae_array_lo_hi, entries_barrier.io.y.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node final_ae_array_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node final_ae_array_hi = cat(final_ae_array_hi_hi, entries_barrier_3.io.y.ae_final) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 507:27] node ptw_pf_array_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, entries_barrier.io.y.pf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_pf_array_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, entries_barrier_3.io.y.pf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 508:25] node ptw_gf_array_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, entries_barrier.io.y.gf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_gf_array_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, entries_barrier_3.io.y.gf) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 509:25] node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 510:16] node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 513:24] node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 513:32] node priv_rw_ok_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, entries_barrier.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_rw_ok_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, entries_barrier_3.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 513:23] node priv_rw_ok_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, entries_barrier.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_rw_ok_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, entries_barrier_3.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 513:84] node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 513:75] node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 513:70] node priv_x_ok_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok_lo = cat(priv_x_ok_lo_hi, entries_barrier.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok_hi = cat(priv_x_ok_hi_hi, entries_barrier_3.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_x_ok_T_1 = not(_priv_x_ok_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 516:31] node priv_x_ok_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, entries_barrier.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, entries_barrier_3.io.y.u) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 516:22] node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<6>(0h3f), UInt<6>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 517:27] node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 517:83] node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<6>(0h3f), UInt<6>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 517:68] node stage1_bypass_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node stage1_bypass_lo = cat(stage1_bypass_lo_hi, entries_barrier.io.y.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node stage1_bypass_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node stage1_bypass_hi = cat(stage1_bypass_hi_hi, entries_barrier_3.io.y.ae_stage2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 517:95] node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 517:61] node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 518:36] node mxr = or(io.ptw.status.mxr, _mxr_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 518:31] node r_array_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_lo = cat(r_array_lo_hi, entries_barrier.io.y.sr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_hi = cat(r_array_hi_hi, entries_barrier_3.io.y.sr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _r_array_T = cat(r_array_hi, r_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_lo_1 = cat(r_array_lo_hi_1, entries_barrier.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_array_hi_1 = cat(r_array_hi_hi_1, entries_barrier_3.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 520:74] node _r_array_T_3 = or(_r_array_T, _r_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 520:69] node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 520:41] node _r_array_T_5 = or(_r_array_T_4, stage1_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 520:113] node r_array = cat(UInt<1>(0h1), _r_array_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 520:20] node w_array_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node w_array_lo = cat(w_array_lo_hi, entries_barrier.io.y.sw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node w_array_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node w_array_hi = cat(w_array_hi_hi, entries_barrier_3.io.y.sw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _w_array_T = cat(w_array_hi, w_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _w_array_T_1 = and(priv_rw_ok, _w_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 521:41] node _w_array_T_2 = or(_w_array_T_1, stage1_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 521:69] node w_array = cat(UInt<1>(0h1), _w_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 521:20] node x_array_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node x_array_lo = cat(x_array_lo_hi, entries_barrier.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node x_array_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node x_array_hi = cat(x_array_hi_hi, entries_barrier_3.io.y.sx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _x_array_T = cat(x_array_hi, x_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _x_array_T_1 = and(priv_x_ok, _x_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 522:40] node _x_array_T_2 = or(_x_array_T_1, stage1_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 522:68] node x_array = cat(UInt<1>(0h1), _x_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 522:20] node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 523:42] node stage2_bypass = mux(_stage2_bypass_T, UInt<6>(0h3f), UInt<6>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 523:27] node hr_array_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_lo = cat(hr_array_lo_hi, entries_barrier.io.y.hr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_hi = cat(hr_array_hi_hi, entries_barrier_3.io.y.hr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hr_array_T = cat(hr_array_hi, hr_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_lo_1 = cat(hr_array_lo_hi_1, entries_barrier.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hr_array_hi_1 = cat(hr_array_hi_hi_1, entries_barrier_3.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 524:60] node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 524:55] node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 524:111] node hr_array = cat(UInt<1>(0h1), _hr_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 524:21] node hw_array_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hw_array_lo = cat(hw_array_lo_hi, entries_barrier.io.y.hw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hw_array_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hw_array_hi = cat(hw_array_hi_hi, entries_barrier_3.io.y.hw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hw_array_T = cat(hw_array_hi, hw_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hw_array_T_1 = or(_hw_array_T, stage2_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 525:55] node hw_array = cat(UInt<1>(0h1), _hw_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 525:21] node hx_array_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hx_array_lo = cat(hx_array_lo_hi, entries_barrier.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hx_array_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hx_array_hi = cat(hx_array_hi_hi, entries_barrier_3.io.y.hx) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hx_array_T = cat(hx_array_hi, hx_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hx_array_T_1 = or(_hx_array_T, stage2_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 526:55] node hx_array = cat(UInt<1>(0h1), _hx_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 526:21] node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 529:26] node pr_array_lo = cat(entries_barrier_1.io.y.pr, entries_barrier.io.y.pr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pr_array_hi_hi = cat(entries_barrier_4.io.y.pr, entries_barrier_3.io.y.pr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pr_array_hi = cat(pr_array_hi_hi, entries_barrier_2.io.y.pr) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 529:21] node _pr_array_T_3 = or(ptw_ae_array, final_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 529:104] node _pr_array_T_4 = not(_pr_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 529:89] node pr_array = and(_pr_array_T_2, _pr_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 529:87] node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 531:26] node pw_array_lo = cat(entries_barrier_1.io.y.pw, entries_barrier.io.y.pw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pw_array_hi_hi = cat(entries_barrier_4.io.y.pw, entries_barrier_3.io.y.pw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pw_array_hi = cat(pw_array_hi_hi, entries_barrier_2.io.y.pw) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 531:21] node _pw_array_T_3 = or(ptw_ae_array, final_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 531:104] node _pw_array_T_4 = not(_pw_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 531:89] node pw_array = and(_pw_array_T_2, _pw_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 531:87] node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 533:26] node px_array_lo = cat(entries_barrier_1.io.y.px, entries_barrier.io.y.px) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node px_array_hi_hi = cat(entries_barrier_4.io.y.px, entries_barrier_3.io.y.px) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node px_array_hi = cat(px_array_hi_hi, entries_barrier_2.io.y.px) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _px_array_T_1 = cat(px_array_hi, px_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 533:21] node _px_array_T_3 = or(ptw_ae_array, final_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 533:104] node _px_array_T_4 = not(_px_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 533:89] node px_array = and(_px_array_T_2, _px_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 533:87] node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 535:27] node eff_array_lo = cat(entries_barrier_1.io.y.eff, entries_barrier.io.y.eff) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node eff_array_hi_hi = cat(entries_barrier_4.io.y.eff, entries_barrier_3.io.y.eff) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node eff_array_hi = cat(eff_array_hi_hi, entries_barrier_2.io.y.eff) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node eff_array = cat(_eff_array_T, _eff_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 535:22] node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 537:25] node c_array_lo = cat(entries_barrier_1.io.y.c, entries_barrier.io.y.c) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node c_array_hi_hi = cat(entries_barrier_4.io.y.c, entries_barrier_3.io.y.c) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node c_array_hi = cat(c_array_hi_hi, entries_barrier_2.io.y.c) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _c_array_T_1 = cat(c_array_hi, c_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node c_array = cat(_c_array_T, _c_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 537:20] node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 539:27] node ppp_array_lo = cat(entries_barrier_1.io.y.ppp, entries_barrier.io.y.ppp) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ppp_array_hi_hi = cat(entries_barrier_4.io.y.ppp, entries_barrier_3.io.y.ppp) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ppp_array_hi = cat(ppp_array_hi_hi, entries_barrier_2.io.y.ppp) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ppp_array = cat(_ppp_array_T, _ppp_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 539:22] node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 541:27] node paa_array_lo = cat(entries_barrier_1.io.y.paa, entries_barrier.io.y.paa) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node paa_array_hi_hi = cat(entries_barrier_4.io.y.paa, entries_barrier_3.io.y.paa) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node paa_array_hi = cat(paa_array_hi_hi, entries_barrier_2.io.y.paa) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node paa_array = cat(_paa_array_T, _paa_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 541:22] node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 543:27] node pal_array_lo = cat(entries_barrier_1.io.y.pal, entries_barrier.io.y.pal) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pal_array_hi_hi = cat(entries_barrier_4.io.y.pal, entries_barrier_3.io.y.pal) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pal_array_hi = cat(pal_array_hi_hi, entries_barrier_2.io.y.pal) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node pal_array = cat(_pal_array_T, _pal_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 543:22] node ppp_array_if_cached = or(ppp_array, c_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 544:39] node paa_array_if_cached = or(paa_array, c_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 545:39] node pal_array_if_cached = or(pal_array, c_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 546:39] node _prefetchable_array_T = and(cacheable, homogeneous) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 547:43] node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 547:59] node prefetchable_array_lo = cat(entries_barrier_1.io.y.c, entries_barrier.io.y.c) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node prefetchable_array_hi_hi = cat(entries_barrier_4.io.y.c, entries_barrier_3.io.y.c) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node prefetchable_array_hi = cat(prefetchable_array_hi_hi, entries_barrier_2.io.y.c) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 547:31] node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 550:69] node _misaligned_T_2 = tail(_misaligned_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 550:69] node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 550:39] node misaligned = orr(_misaligned_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 550:77] node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 570:33] node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 571:40] node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 572:43] node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 573:41] node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 89:68] node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 575:56] node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 575:37] node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:32] node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:49] node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:42] node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:66] node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:59] node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:76] node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 577:35] node lrscAllowed = mux(UInt<1>(0h1), UInt<1>(0h0), c_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 580:24] node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 582:8] node _ae_array_T_1 = not(lrscAllowed) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 583:19] node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 583:8] node ae_array = or(_ae_array_T, _ae_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 582:37] node _ae_ld_array_T = and(pr_array, px_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 586:71] node _ae_ld_array_T_1 = mux(cmd_readx, _ae_ld_array_T, pr_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 586:50] node _ae_ld_array_T_2 = not(_ae_ld_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 586:46] node _ae_ld_array_T_3 = or(ae_array, _ae_ld_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 586:44] node ae_ld_array = mux(cmd_read, _ae_ld_array_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 586:24] node _ae_st_array_T = not(pw_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 588:37] node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 588:35] node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 588:8] node _ae_st_array_T_3 = not(ppp_array_if_cached) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 589:26] node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 589:8] node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 588:53] node _ae_st_array_T_6 = not(pal_array_if_cached) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 590:26] node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 590:8] node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 589:53] node _ae_st_array_T_9 = not(paa_array_if_cached) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 591:29] node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 591:8] node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 590:53] node _must_alloc_array_T = not(ppp_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 593:26] node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 593:8] node _must_alloc_array_T_2 = not(pal_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 594:26] node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 594:8] node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 593:43] node _must_alloc_array_T_5 = not(paa_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 595:29] node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 595:8] node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 594:43] node _must_alloc_array_T_8 = not(UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 596:19] node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 596:8] node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 595:46] node _pf_ld_array_T = mux(cmd_readx, x_array, r_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:41] node _pf_ld_array_T_1 = not(_pf_ld_array_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:37] node _pf_ld_array_T_2 = not(ptw_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:73] node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:71] node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:88] node _pf_ld_array_T_5 = not(ptw_gf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:106] node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:104] node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 597:24] node _pf_st_array_T = not(w_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:44] node _pf_st_array_T_1 = not(ptw_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:55] node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:53] node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:70] node _pf_st_array_T_4 = not(ptw_gf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:88] node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:86] node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 598:24] node _pf_inst_array_T = not(x_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 599:25] node _pf_inst_array_T_1 = not(ptw_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 599:36] node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 599:34] node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 599:51] node _pf_inst_array_T_4 = not(ptw_gf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 599:69] node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 599:67] node _gf_ld_array_T = and(priv_v, cmd_read) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:32] node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:50] node _gf_ld_array_T_2 = not(_gf_ld_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:46] node _gf_ld_array_T_3 = not(ptw_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:84] node _gf_ld_array_T_4 = and(_gf_ld_array_T_2, _gf_ld_array_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:82] node _gf_ld_array_T_5 = or(_gf_ld_array_T_4, ptw_gf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:99] node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 600:24] node _gf_st_array_T = and(priv_v, cmd_write_perms) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 601:32] node _gf_st_array_T_1 = not(hw_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 601:53] node _gf_st_array_T_2 = not(ptw_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 601:65] node _gf_st_array_T_3 = and(_gf_st_array_T_1, _gf_st_array_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 601:63] node _gf_st_array_T_4 = or(_gf_st_array_T_3, ptw_gf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 601:80] node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 601:24] node _gf_inst_array_T = not(hx_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 602:36] node _gf_inst_array_T_1 = not(ptw_ae_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 602:48] node _gf_inst_array_T_2 = and(_gf_inst_array_T, _gf_inst_array_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 602:46] node _gf_inst_array_T_3 = or(_gf_inst_array_T_2, ptw_gf_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 602:63] node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 602:26] node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 606:73] node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 606:60] node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<5>(0h1f), UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 606:24] node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 606:107] node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<6>(0h3f), UInt<6>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 606:88] node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 606:82] node _gpa_hits_T = bits(gf_inst_array, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 607:30] node _gpa_hits_T_1 = not(_gpa_hits_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 607:16] node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 607:14] node tlb_hit_if_not_gpa_miss = orr(real_hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 610:43] node _tlb_hit_T = and(real_hits, gpa_hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 611:28] node tlb_hit = orr(_tlb_hit_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 611:40] node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 613:32] node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 613:29] node _tlb_miss_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 613:56] node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 613:53] node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 613:67] node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 613:64] reg state_reg : UInt<0>, clock @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 168:46] reg state_vec : UInt<0>[1], clock @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 304:30] regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 168:70] node _T_9 = and(io.req.valid, vm_enabled) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 617:22] when _T_9 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 617:37] when sector_hits_0 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 619:28] connect state_vec[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 308:20] node _T_10 = or(superpage_hits_0, superpage_hits_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_11 = or(_T_10, superpage_hits_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_12 = or(_T_11, superpage_hits_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] when _T_12 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 620:31] node lo = cat(superpage_hits_1, superpage_hits_0) @[src/main/scala/chisel3/util/OneHot.scala 21:45] node hi = cat(superpage_hits_3, superpage_hits_2) @[src/main/scala/chisel3/util/OneHot.scala 21:45] node _T_13 = cat(hi, lo) @[src/main/scala/chisel3/util/OneHot.scala 21:45] node hi_1 = bits(_T_13, 3, 2) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node lo_1 = bits(_T_13, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _T_14 = orr(hi_1) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _T_15 = or(hi_1, lo_1) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node _T_16 = bits(_T_15, 1, 1) @[src/main/scala/chisel3/util/CircuitMath.scala 28:8] node _T_17 = cat(_T_14, _T_16) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node state_reg_touch_way_sized = bits(_T_17, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:43] node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:33] node state_reg_left_subtree_state = bits(state_reg_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node state_reg_right_subtree_state = bits(state_reg_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 198:38] node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_T_1 = bits(_state_reg_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 203:16] node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 207:62] node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 206:16] node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] connect state_reg_1, _state_reg_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 172:15] node _multipleHits_T = bits(real_hits, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 181:37] node _multipleHits_T_1 = bits(_multipleHits_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 181:37] node multipleHits_leftOne = bits(_multipleHits_T_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 178:18] node _multipleHits_T_2 = bits(_multipleHits_T, 2, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 182:39] node _multipleHits_T_3 = bits(_multipleHits_T_2, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 181:37] node multipleHits_leftOne_1 = bits(_multipleHits_T_3, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 178:18] node _multipleHits_T_4 = bits(_multipleHits_T_2, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 182:39] node multipleHits_rightOne = bits(_multipleHits_T_4, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 178:18] node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:16] node _multipleHits_T_5 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:37] node _multipleHits_T_6 = and(multipleHits_leftOne_1, multipleHits_rightOne) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:61] node multipleHits_rightTwo = or(_multipleHits_T_5, _multipleHits_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:49] node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:16] node _multipleHits_T_7 = or(UInt<1>(0h0), multipleHits_rightTwo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:37] node _multipleHits_T_8 = and(multipleHits_leftOne, multipleHits_rightOne_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:61] node multipleHits_leftTwo = or(_multipleHits_T_7, _multipleHits_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:49] node _multipleHits_T_9 = bits(real_hits, 5, 3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 182:39] node _multipleHits_T_10 = bits(_multipleHits_T_9, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 181:37] node multipleHits_leftOne_3 = bits(_multipleHits_T_10, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 178:18] node _multipleHits_T_11 = bits(_multipleHits_T_9, 2, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 182:39] node _multipleHits_T_12 = bits(_multipleHits_T_11, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 181:37] node multipleHits_leftOne_4 = bits(_multipleHits_T_12, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 178:18] node _multipleHits_T_13 = bits(_multipleHits_T_11, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 182:39] node multipleHits_rightOne_2 = bits(_multipleHits_T_13, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 178:18] node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:16] node _multipleHits_T_14 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:37] node _multipleHits_T_15 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:61] node multipleHits_rightTwo_1 = or(_multipleHits_T_14, _multipleHits_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:49] node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:16] node _multipleHits_T_16 = or(UInt<1>(0h0), multipleHits_rightTwo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:37] node _multipleHits_T_17 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:61] node multipleHits_rightTwo_2 = or(_multipleHits_T_16, _multipleHits_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:49] node _multipleHits_T_18 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:16] node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:37] node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:61] node multipleHits = or(_multipleHits_T_19, _multipleHits_T_20) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 183:49] node _io_req_ready_T = eq(state, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 631:25] connect io.req.ready, _io_req_ready_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 631:16] node _io_resp_pf_ld_T = and(UInt<1>(0h0), cmd_read) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 633:28] node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 633:57] node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 633:65] node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 633:41] connect io.resp.pf.ld, _io_resp_pf_ld_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 633:17] node _io_resp_pf_st_T = and(UInt<1>(0h0), cmd_write_perms) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 634:28] node _io_resp_pf_st_T_1 = and(pf_st_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 634:64] node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 634:72] node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 634:48] connect io.resp.pf.st, _io_resp_pf_st_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 634:17] node _io_resp_pf_inst_T = and(pf_inst_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 635:47] node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 635:55] node _io_resp_pf_inst_T_2 = or(UInt<1>(0h0), _io_resp_pf_inst_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 635:29] connect io.resp.pf.inst, _io_resp_pf_inst_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 635:19] node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 637:29] node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 637:58] node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 637:66] node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 637:42] connect io.resp.gf.ld, _io_resp_gf_ld_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 637:17] node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 638:29] node _io_resp_gf_st_T_1 = and(gf_st_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 638:65] node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 638:73] node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 638:49] connect io.resp.gf.st, _io_resp_gf_st_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 638:17] node _io_resp_gf_inst_T = and(gf_inst_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 639:48] node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 639:56] node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 639:30] connect io.resp.gf.inst, _io_resp_gf_inst_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 639:19] node _io_resp_ae_ld_T = and(ae_ld_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 641:33] node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 641:41] connect io.resp.ae.ld, _io_resp_ae_ld_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 641:17] node _io_resp_ae_st_T = and(ae_st_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 642:33] node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 642:41] connect io.resp.ae.st, _io_resp_ae_st_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 642:17] node _io_resp_ae_inst_T = not(px_array) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 643:23] node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 643:33] node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 643:41] connect io.resp.ae.inst, _io_resp_ae_inst_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 643:19] node _io_resp_ma_ld_T = and(misaligned, cmd_read) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 645:31] connect io.resp.ma.ld, _io_resp_ma_ld_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 645:17] node _io_resp_ma_st_T = and(misaligned, cmd_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 646:31] connect io.resp.ma.st, _io_resp_ma_st_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 646:17] connect io.resp.ma.inst, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 647:19] node _io_resp_cacheable_T = and(c_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 648:33] node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 648:41] connect io.resp.cacheable, _io_resp_cacheable_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 648:21] node _io_resp_must_alloc_T = and(must_alloc_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 649:43] node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 649:51] connect io.resp.must_alloc, _io_resp_must_alloc_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 649:22] node _io_resp_prefetchable_T = and(prefetchable_array, hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 650:47] node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 650:55] node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 650:59] connect io.resp.prefetchable, _io_resp_prefetchable_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 650:24] node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 651:29] node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 651:52] node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 651:64] connect io.resp.miss, _io_resp_miss_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 651:16] node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 652:46] node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 652:23] connect io.resp.paddr, _io_resp_paddr_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 652:17] connect io.resp.size, io.req.bits.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 653:16] connect io.resp.cmd, io.req.bits.cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 654:15] node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 655:36] connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 655:22] node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 657:20] node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 657:36] node _io_resp_gpa_page_T_2 = shr(r_gpa, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 657:58] node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 657:19] node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 658:47] node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 658:82] node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 658:21] node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 659:8] connect io.resp.gpa, _io_resp_gpa_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 656:15] node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 662:29] connect io.ptw.req.valid, _io_ptw_req_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 662:20] node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 663:28] connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 663:25] connect io.ptw.req.bits.bits.addr, r_refill_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 664:29] connect io.ptw.req.bits.bits.vstage1, r_vstage1_en @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 665:32] connect io.ptw.req.bits.bits.stage2, r_stage2_en @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 666:31] connect io.ptw.req.bits.bits.need_gpa, r_need_gpa @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLB.scala 667:33] module Frontend : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 82:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 82:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 82:7] output auto : { icache_master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip reset_vector_sink_in : UInt<32>} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output io : { flip cpu : { might_request : UInt<1>, flip clock_enabled : UInt<1>, req : { valid : UInt<1>, bits : { pc : UInt<34>, speculative : UInt<1>}}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<33>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<1>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<34>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, flip gpa : { valid : UInt<1>, bits : UInt<34>}, flip gpa_is_pte : UInt<1>, btb_update : { valid : UInt<1>, bits : { prediction : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<1>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<33>, target : UInt<33>, taken : UInt<1>, isValid : UInt<1>, br_pc : UInt<33>, cfiType : UInt<2>}}, bht_update : { valid : UInt<1>, bits : { prediction : { history : UInt<8>, value : UInt<1>}, pc : UInt<33>, branch : UInt<1>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : { valid : UInt<1>, bits : { cfiType : UInt<2>, returnAddr : UInt<33>}}, flush_icache : UInt<1>, flip npc : UInt<34>, flip perf : { acquire : UInt<1>, tlbMiss : UInt<1>}, progress : UInt<1>}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<21>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<33>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, errors : { bus : { valid : UInt<1>, bits : UInt<32>}}} @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 85:14] inst icache of ICache @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 70:26] connect icache.clock, clock connect icache.reset, reset wire resetVectorSinkNodeIn : UInt<32> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate resetVectorSinkNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect resetVectorSinkNodeIn, auto.reset_vector_sink_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect icache.auto.master_out.d, auto.icache_master_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.icache_master_out.a.bits, icache.auto.master_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.icache_master_out.a.valid, icache.auto.master_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect icache.auto.master_out.a.ready, auto.icache_master_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] node _T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 91:28] node _T_1 = or(_T, io.cpu.req.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 91:35] inst fq of ShiftQueue @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 91:64] connect fq.clock, clock connect fq.reset, _T_1 reg clock_en_reg : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 93:25] node clock_en = or(clock_en_reg, io.cpu.might_request) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 94:31] connect io.cpu.clock_enabled, clock_en @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 95:24] node _T_2 = or(io.cpu.req.valid, io.cpu.sfence.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 96:29] node _T_3 = or(_T_2, io.cpu.flush_icache) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 96:52] node _T_4 = or(_T_3, io.cpu.bht_update.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 96:75] node _T_5 = or(_T_4, io.cpu.btb_update.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 96:102] node _T_6 = eq(_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 96:10] node _T_7 = or(_T_6, io.cpu.might_request) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 96:130] node _T_8 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 96:9] node _T_9 = eq(_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 96:9] when _T_9 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 96:9] node _T_10 = eq(_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 96:9] when _T_10 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 96:9] printf(clock, UInt<1>(0h1), "Assertion failed\n at Frontend.scala:96 assert(!(io.cpu.req.valid || io.cpu.sfence.valid || io.cpu.flush_icache || io.cpu.bht_update.valid || io.cpu.btb_update.valid) || io.cpu.might_request)\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 96:9] assert(clock, _T_7, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 96:9] connect icache.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 101:16] connect icache.io.clock_enabled, clock_en @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 102:27] inst tlb of ITLB @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 105:19] connect tlb.clock, clock connect tlb.reset, reset reg s1_valid : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 107:21] regreset s2_valid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 108:25] node _s0_fq_has_space_T = bits(fq.io.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 110:16] node _s0_fq_has_space_T_1 = eq(_s0_fq_has_space_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 110:5] node _s0_fq_has_space_T_2 = bits(fq.io.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 111:17] node _s0_fq_has_space_T_3 = eq(_s0_fq_has_space_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 111:6] node _s0_fq_has_space_T_4 = eq(s1_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 111:45] node _s0_fq_has_space_T_5 = eq(s2_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 111:58] node _s0_fq_has_space_T_6 = or(_s0_fq_has_space_T_4, _s0_fq_has_space_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 111:55] node _s0_fq_has_space_T_7 = and(_s0_fq_has_space_T_3, _s0_fq_has_space_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 111:41] node _s0_fq_has_space_T_8 = or(_s0_fq_has_space_T_1, _s0_fq_has_space_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 110:40] node _s0_fq_has_space_T_9 = bits(fq.io.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 112:17] node _s0_fq_has_space_T_10 = eq(_s0_fq_has_space_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 112:6] node _s0_fq_has_space_T_11 = eq(s1_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 112:45] node _s0_fq_has_space_T_12 = eq(s2_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 112:58] node _s0_fq_has_space_T_13 = and(_s0_fq_has_space_T_11, _s0_fq_has_space_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 112:55] node _s0_fq_has_space_T_14 = and(_s0_fq_has_space_T_10, _s0_fq_has_space_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 112:41] node s0_fq_has_space = or(_s0_fq_has_space_T_8, _s0_fq_has_space_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 111:70] node s0_valid = or(io.cpu.req.valid, s0_fq_has_space) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 113:35] connect s1_valid, s0_valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 114:12] reg s1_pc : UInt<34>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 115:18] reg s1_speculative : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 116:27] node _s2_pc_T = not(resetVectorSinkNodeIn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 384:29] node _s2_pc_T_1 = or(_s2_pc_T, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 384:33] node _s2_pc_T_2 = not(_s2_pc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 384:27] regreset s2_pc : UInt<34>, clock, reset, _s2_pc_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 117:22] reg s2_btb_resp_bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<1>, bht : { history : UInt<8>, value : UInt<1>}}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 119:29] node s2_btb_taken = and(UInt<1>(0h0), s2_btb_resp_bits.taken) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 120:40] reg s2_tlb_resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<34>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 121:24] node _s2_xcpt_T = or(s2_tlb_resp.ae.inst, s2_tlb_resp.pf.inst) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 122:37] node s2_xcpt = or(_s2_xcpt_T, s2_tlb_resp.gf.inst) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 122:60] regreset s2_speculative : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 123:31] regreset s2_partial_insn_valid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 124:38] reg s2_partial_insn : UInt<16>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 125:28] regreset wrong_path : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 126:27] node _s1_base_pc_T = not(s1_pc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 128:22] node _s1_base_pc_T_1 = or(_s1_base_pc_T, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 128:29] node s1_base_pc = not(_s1_base_pc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 128:20] node _ntpc_T = add(s1_base_pc, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 129:25] node ntpc = tail(_ntpc_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 129:25] wire predicted_npc : UInt @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 130:34] connect predicted_npc, ntpc @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 130:34] wire predicted_taken : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 131:36] connect predicted_taken, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 131:36] wire s2_replay : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 133:23] node _s2_replay_T = and(fq.io.enq.ready, fq.io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _s2_replay_T_1 = eq(_s2_replay_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 134:29] node _s2_replay_T_2 = and(s2_valid, _s2_replay_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 134:26] node _s2_replay_T_3 = eq(s0_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 134:70] node _s2_replay_T_4 = and(s2_replay, _s2_replay_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 134:67] regreset s2_replay_REG : UInt<1>, clock, reset, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 134:56] connect s2_replay_REG, _s2_replay_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 134:56] node _s2_replay_T_5 = or(_s2_replay_T_2, s2_replay_REG) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 134:46] connect s2_replay, _s2_replay_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 134:13] node npc = mux(s2_replay, s2_pc, predicted_npc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 135:16] connect s1_pc, io.cpu.npc @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 137:9] node _s0_speculative_T = eq(s2_speculative, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 141:56] node _s0_speculative_T_1 = and(s2_valid, _s0_speculative_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 141:53] node _s0_speculative_T_2 = or(s1_speculative, _s0_speculative_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 141:41] node s0_speculative = or(_s0_speculative_T_2, predicted_taken) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 141:72] node _s1_speculative_T = mux(s2_replay, s2_speculative, s0_speculative) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 143:75] node _s1_speculative_T_1 = mux(io.cpu.req.valid, io.cpu.req.bits.speculative, _s1_speculative_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 143:24] connect s1_speculative, _s1_speculative_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 143:18] wire s2_redirect : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 145:32] connect s2_redirect, io.cpu.req.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 145:32] connect s2_valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 146:12] node _T_11 = eq(s2_replay, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 147:9] when _T_11 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 147:21] node _s2_valid_T = eq(s2_redirect, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 148:17] connect s2_valid, _s2_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 148:14] connect s2_pc, s1_pc @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 149:11] connect s2_speculative, s1_speculative @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 150:20] connect s2_tlb_resp, tlb.io.resp @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 151:17] regreset recent_progress_counter : UInt, clock, reset, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 155:40] node recent_progress = gt(recent_progress_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 156:49] node _T_12 = and(io.ptw.req.ready, io.ptw.req.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_13 = and(_T_12, recent_progress) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 157:24] when _T_13 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 157:44] node _recent_progress_counter_T = sub(recent_progress_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 157:97] node _recent_progress_counter_T_1 = tail(_recent_progress_counter_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 157:97] connect recent_progress_counter, _recent_progress_counter_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 157:70] when io.cpu.progress : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 158:25] connect recent_progress_counter, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 158:51] node _s2_kill_speculative_tlb_refill_T = eq(recent_progress, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 160:58] node s2_kill_speculative_tlb_refill = and(s2_speculative, _s2_kill_speculative_tlb_refill_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 160:55] connect tlb.io.ptw.customCSRs, io.ptw.customCSRs @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] connect tlb.io.ptw.pmp[0], io.ptw.pmp[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] connect tlb.io.ptw.pmp[1], io.ptw.pmp[1] @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] connect tlb.io.ptw.pmp[2], io.ptw.pmp[2] @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] connect tlb.io.ptw.pmp[3], io.ptw.pmp[3] @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] connect tlb.io.ptw.pmp[4], io.ptw.pmp[4] @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] connect tlb.io.ptw.pmp[5], io.ptw.pmp[5] @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] connect tlb.io.ptw.pmp[6], io.ptw.pmp[6] @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] connect tlb.io.ptw.pmp[7], io.ptw.pmp[7] @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] connect tlb.io.ptw.gstatus, io.ptw.gstatus @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] connect tlb.io.ptw.hstatus, io.ptw.hstatus @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] connect tlb.io.ptw.status, io.ptw.status @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] connect tlb.io.ptw.vsatp, io.ptw.vsatp @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] connect tlb.io.ptw.hgatp, io.ptw.hgatp @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] connect tlb.io.ptw.ptbr, io.ptw.ptbr @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] connect tlb.io.ptw.resp, io.ptw.resp @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] connect io.ptw.req.bits, tlb.io.ptw.req.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] connect io.ptw.req.valid, tlb.io.ptw.req.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] connect tlb.io.ptw.req.ready, io.ptw.req.ready @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 162:10] node _tlb_io_req_valid_T = eq(s2_replay, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 163:35] node _tlb_io_req_valid_T_1 = and(s1_valid, _tlb_io_req_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 163:32] connect tlb.io.req.valid, _tlb_io_req_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 163:20] connect tlb.io.req.bits.cmd, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 164:23] connect tlb.io.req.bits.vaddr, s1_pc @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 165:25] connect tlb.io.req.bits.passthrough, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 166:31] connect tlb.io.req.bits.size, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 167:24] connect tlb.io.req.bits.prv, io.ptw.status.prv @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 168:23] connect tlb.io.req.bits.v, io.ptw.status.v @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 169:21] connect tlb.io.sfence.bits.hg, io.cpu.sfence.bits.hg @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 170:17] connect tlb.io.sfence.bits.hv, io.cpu.sfence.bits.hv @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 170:17] connect tlb.io.sfence.bits.asid, io.cpu.sfence.bits.asid @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 170:17] connect tlb.io.sfence.bits.addr, io.cpu.sfence.bits.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 170:17] connect tlb.io.sfence.bits.rs2, io.cpu.sfence.bits.rs2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 170:17] connect tlb.io.sfence.bits.rs1, io.cpu.sfence.bits.rs1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 170:17] connect tlb.io.sfence.valid, io.cpu.sfence.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 170:17] node _tlb_io_kill_T = eq(s2_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 171:18] node _tlb_io_kill_T_1 = or(_tlb_io_kill_T, s2_kill_speculative_tlb_refill) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 171:28] connect tlb.io.kill, _tlb_io_kill_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 171:15] connect icache.io.req.valid, s0_valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 173:23] connect icache.io.req.bits.addr, io.cpu.npc @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 174:27] connect icache.io.invalidate, io.cpu.flush_icache @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 175:24] connect icache.io.s1_paddr, tlb.io.resp.paddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 176:22] connect icache.io.s2_vaddr, s2_pc @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 177:22] node _icache_io_s1_kill_T = or(s2_redirect, tlb.io.resp.miss) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 178:36] node _icache_io_s1_kill_T_1 = or(_icache_io_s1_kill_T, s2_replay) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 178:56] connect icache.io.s1_kill, _icache_io_s1_kill_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 178:21] node _s2_can_speculatively_refill_T = bits(io.ptw.customCSRs.csrs[0].value, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tile/CustomCSRs.scala 46:69] node _s2_can_speculatively_refill_T_1 = eq(_s2_can_speculatively_refill_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 179:62] node s2_can_speculatively_refill = and(s2_tlb_resp.cacheable, _s2_can_speculatively_refill_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 179:59] node _icache_io_s2_kill_T = eq(s2_can_speculatively_refill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 180:42] node _icache_io_s2_kill_T_1 = and(s2_speculative, _icache_io_s2_kill_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 180:39] node _icache_io_s2_kill_T_2 = or(_icache_io_s2_kill_T_1, s2_xcpt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 180:71] connect icache.io.s2_kill, _icache_io_s2_kill_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 180:21] connect icache.io.s2_cacheable, s2_tlb_resp.cacheable @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 181:26] node _icache_io_s2_prefetch_T = bits(io.ptw.customCSRs.csrs[0].value, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 117:60] node _icache_io_s2_prefetch_T_1 = eq(_icache_io_s2_prefetch_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 182:56] node _icache_io_s2_prefetch_T_2 = and(s2_tlb_resp.prefetchable, _icache_io_s2_prefetch_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 182:53] connect icache.io.s2_prefetch, _icache_io_s2_prefetch_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 182:25] reg fq_io_enq_valid_REG : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 184:29] connect fq_io_enq_valid_REG, s1_valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 184:29] node _fq_io_enq_valid_T = and(fq_io_enq_valid_REG, s2_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 184:40] node _fq_io_enq_valid_T_1 = and(s2_kill_speculative_tlb_refill, s2_tlb_resp.miss) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 184:112] node _fq_io_enq_valid_T_2 = or(icache.io.resp.valid, _fq_io_enq_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 184:77] node _fq_io_enq_valid_T_3 = eq(s2_tlb_resp.miss, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 184:137] node _fq_io_enq_valid_T_4 = and(_fq_io_enq_valid_T_3, icache.io.s2_kill) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 184:155] node _fq_io_enq_valid_T_5 = or(_fq_io_enq_valid_T_2, _fq_io_enq_valid_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 184:133] node _fq_io_enq_valid_T_6 = and(_fq_io_enq_valid_T, _fq_io_enq_valid_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 184:52] connect fq.io.enq.valid, _fq_io_enq_valid_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 184:19] connect fq.io.enq.bits.pc, s2_pc @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 185:21] node _io_cpu_npc_T = mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 186:28] node _io_cpu_npc_T_1 = not(_io_cpu_npc_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 384:29] node _io_cpu_npc_T_2 = or(_io_cpu_npc_T_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 384:33] node _io_cpu_npc_T_3 = not(_io_cpu_npc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 384:27] connect io.cpu.npc, _io_cpu_npc_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 186:14] connect fq.io.enq.bits.data, icache.io.resp.bits.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 188:23] node _fq_io_enq_bits_mask_T = bits(s2_pc, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _fq_io_enq_bits_mask_T_1 = dshl(UInt<2>(0h3), _fq_io_enq_bits_mask_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 189:50] connect fq.io.enq.bits.mask, _fq_io_enq_bits_mask_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 189:23] node _fq_io_enq_bits_replay_T = eq(icache.io.resp.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 190:80] node _fq_io_enq_bits_replay_T_1 = and(icache.io.s2_kill, _fq_io_enq_bits_replay_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 190:77] node _fq_io_enq_bits_replay_T_2 = eq(s2_xcpt, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 190:105] node _fq_io_enq_bits_replay_T_3 = and(_fq_io_enq_bits_replay_T_1, _fq_io_enq_bits_replay_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 190:102] node _fq_io_enq_bits_replay_T_4 = or(icache.io.resp.bits.replay, _fq_io_enq_bits_replay_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 190:56] node _fq_io_enq_bits_replay_T_5 = and(s2_kill_speculative_tlb_refill, s2_tlb_resp.miss) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 190:150] node _fq_io_enq_bits_replay_T_6 = or(_fq_io_enq_bits_replay_T_4, _fq_io_enq_bits_replay_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 190:115] connect fq.io.enq.bits.replay, _fq_io_enq_bits_replay_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 190:25] connect fq.io.enq.bits.btb.bht.value, s2_btb_resp_bits.bht.value @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 191:22] connect fq.io.enq.bits.btb.bht.history, s2_btb_resp_bits.bht.history @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 191:22] connect fq.io.enq.bits.btb.entry, s2_btb_resp_bits.entry @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 191:22] connect fq.io.enq.bits.btb.target, s2_btb_resp_bits.target @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 191:22] connect fq.io.enq.bits.btb.bridx, s2_btb_resp_bits.bridx @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 191:22] connect fq.io.enq.bits.btb.mask, s2_btb_resp_bits.mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 191:22] connect fq.io.enq.bits.btb.taken, s2_btb_resp_bits.taken @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 191:22] connect fq.io.enq.bits.btb.cfiType, s2_btb_resp_bits.cfiType @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 191:22] connect fq.io.enq.bits.btb.taken, s2_btb_taken @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 192:28] connect fq.io.enq.bits.xcpt.ae.inst, s2_tlb_resp.ae.inst @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 193:23] connect fq.io.enq.bits.xcpt.gf.inst, s2_tlb_resp.gf.inst @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 193:23] connect fq.io.enq.bits.xcpt.pf.inst, s2_tlb_resp.pf.inst @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 193:23] node _T_14 = bits(io.ptw.customCSRs.csrs[0].value, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tile/CustomCSRs.scala 46:69] node _T_15 = and(s2_speculative, _T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 194:27] node _T_16 = eq(icache.io.s2_kill, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 194:113] node _T_17 = and(_T_15, _T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 194:110] node _T_18 = eq(_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 194:10] node _T_19 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 194:9] node _T_20 = eq(_T_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 194:9] when _T_20 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 194:9] node _T_21 = eq(_T_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 194:9] when _T_21 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 194:9] printf(clock, UInt<1>(0h1), "Assertion failed\n at Frontend.scala:194 assert(!(s2_speculative && io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill && !icache.io.s2_kill))\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 194:9] assert(clock, _T_18, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 194:9] node _T_22 = and(icache.io.resp.valid, icache.io.resp.bits.ae) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 195:30] when _T_22 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 195:57] connect fq.io.enq.bits.xcpt.ae.inst, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 195:87] connect io.cpu.resp.bits, fq.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 350:15] connect io.cpu.resp.valid, fq.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 350:15] connect fq.io.deq.ready, io.cpu.resp.ready @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 350:15] reg gpa_valid : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 353:22] reg gpa : UInt<34>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 354:16] reg gpa_is_pte : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 355:23] node _T_23 = and(fq.io.enq.ready, fq.io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_24 = and(_T_23, s2_tlb_resp.gf.inst) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 356:24] when _T_24 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 356:48] node _T_25 = eq(gpa_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 357:11] when _T_25 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 357:23] connect gpa, s2_tlb_resp.gpa @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 358:11] connect gpa_is_pte, s2_tlb_resp.gpa_is_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 359:18] connect gpa_valid, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 361:15] when io.cpu.req.valid : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 363:27] connect gpa_valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 364:15] connect io.cpu.gpa.valid, gpa_valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 366:20] connect io.cpu.gpa.bits, gpa @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 367:19] connect io.cpu.gpa_is_pte, gpa_is_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 368:21] connect io.cpu.perf.acquire, icache.io.perf.acquire @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 371:23] node _io_cpu_perf_tlbMiss_T = and(io.ptw.req.ready, io.ptw.req.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] connect io.cpu.perf.tlbMiss, _io_cpu_perf_tlbMiss_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 372:23] connect io.errors, icache.io.errors @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 373:13] node _clock_en_reg_T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 376:19] node _clock_en_reg_T_1 = or(_clock_en_reg_T, io.cpu.might_request) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 376:45] node _clock_en_reg_T_2 = or(_clock_en_reg_T_1, icache.io.keep_clock_enabled) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 377:26] node _clock_en_reg_T_3 = or(_clock_en_reg_T_2, s1_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 378:34] node _clock_en_reg_T_4 = or(_clock_en_reg_T_3, s2_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 379:14] node _clock_en_reg_T_5 = eq(tlb.io.req.ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 380:5] node _clock_en_reg_T_6 = or(_clock_en_reg_T_4, _clock_en_reg_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 379:26] node _clock_en_reg_T_7 = bits(fq.io.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 381:16] node _clock_en_reg_T_8 = eq(_clock_en_reg_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 381:5] node _clock_en_reg_T_9 = or(_clock_en_reg_T_6, _clock_en_reg_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 380:23] connect clock_en_reg, _clock_en_reg_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 376:16] module TLWidthWidget8_6 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonOut.a.bits, anonIn.a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonOut.a.valid, anonIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 155:19] connect anonIn.a.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 156:18] connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 154:18] connect anonIn.d.valid, anonOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 155:19] connect anonOut.d.ready, anonIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 156:18] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 215:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 216:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 217:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 218:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 219:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 220:21] module TLFragmenter : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] output auto : { } @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] skip module TLWidthWidget8_7 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 27:9] output auto : { } @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] skip module ScratchpadSlavePort : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 43:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 43:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 43:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output io : { dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<34>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 44:16] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] regreset state : UInt<3>, clock, reset, UInt<3>(0h4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 53:24] wire dmem_req_valid : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 54:30] node _T = eq(state, UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 55:17] when _T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 55:30] connect state, UInt<3>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 55:38] node _T_1 = eq(state, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 56:17] node _T_2 = and(_T_1, nodeIn.a.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 56:28] when _T_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 56:46] connect state, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 56:54] when io.dmem.resp.valid : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 57:31] connect state, UInt<3>(0h5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 57:39] node _T_3 = and(nodeIn.d.ready, nodeIn.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_3 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 58:25] connect state, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 58:33] when io.dmem.s2_nack : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 59:28] connect state, UInt<3>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 59:36] node _T_4 = and(dmem_req_valid, io.dmem.req.ready) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 60:26] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 60:48] connect state, UInt<3>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 60:56] reg acq : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 62:18] node _T_5 = and(nodeIn.a.ready, nodeIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 63:25] connect acq, nodeIn.a.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 63:31] node _ready_likely_T = eq(state, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _ready_likely_T_1 = eq(state, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node ready_likely = or(_ready_likely_T, _ready_likely_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _ready_T = eq(state, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 112:23] node _ready_T_1 = eq(state, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 112:44] node _ready_T_2 = and(_ready_T_1, io.dmem.resp.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 112:56] node _ready_T_3 = and(_ready_T_2, nodeIn.d.ready) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 112:78] node ready = or(_ready_T, _ready_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 112:35] node _dmem_req_valid_T = and(nodeIn.a.valid, ready) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 113:38] node _dmem_req_valid_T_1 = eq(state, UInt<3>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 113:57] node _dmem_req_valid_T_2 = or(_dmem_req_valid_T, _dmem_req_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 113:48] connect dmem_req_valid, _dmem_req_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 113:20] node _dmem_req_valid_likely_T = and(nodeIn.a.valid, ready_likely) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 114:48] node _dmem_req_valid_likely_T_1 = eq(state, UInt<3>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 114:74] node dmem_req_valid_likely = or(_dmem_req_valid_likely_T, _dmem_req_valid_likely_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 114:65] invalidate io.dmem.keep_clock_enabled @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 116:32] connect io.dmem.req.valid, dmem_req_valid_likely @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 117:23] node _nodeIn_a_ready_T = and(io.dmem.req.ready, ready) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 118:40] connect nodeIn.a.ready, _nodeIn_a_ready_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 118:19] node _io_dmem_req_bits_T = eq(state, UInt<3>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 119:48] node _io_dmem_req_bits_T_1 = mux(_io_dmem_req_bits_T, acq, nodeIn.a.bits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 119:41] wire io_dmem_req_bits_req : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 66:21] node _io_dmem_req_bits_req_cmd_T = eq(UInt<3>(0h0), _io_dmem_req_bits_T_1.param) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 70:63] node _io_dmem_req_bits_req_cmd_T_1 = mux(_io_dmem_req_bits_req_cmd_T, UInt<4>(0hc), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 70:63] node _io_dmem_req_bits_req_cmd_T_2 = eq(UInt<3>(0h1), _io_dmem_req_bits_T_1.param) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 70:63] node _io_dmem_req_bits_req_cmd_T_3 = mux(_io_dmem_req_bits_req_cmd_T_2, UInt<4>(0hd), _io_dmem_req_bits_req_cmd_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 70:63] node _io_dmem_req_bits_req_cmd_T_4 = eq(UInt<3>(0h2), _io_dmem_req_bits_T_1.param) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 70:63] node _io_dmem_req_bits_req_cmd_T_5 = mux(_io_dmem_req_bits_req_cmd_T_4, UInt<4>(0he), _io_dmem_req_bits_req_cmd_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 70:63] node _io_dmem_req_bits_req_cmd_T_6 = eq(UInt<3>(0h3), _io_dmem_req_bits_T_1.param) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 70:63] node _io_dmem_req_bits_req_cmd_T_7 = mux(_io_dmem_req_bits_req_cmd_T_6, UInt<4>(0hf), _io_dmem_req_bits_req_cmd_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 70:63] node _io_dmem_req_bits_req_cmd_T_8 = eq(UInt<3>(0h4), _io_dmem_req_bits_T_1.param) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 70:63] node _io_dmem_req_bits_req_cmd_T_9 = mux(_io_dmem_req_bits_req_cmd_T_8, UInt<4>(0h8), _io_dmem_req_bits_req_cmd_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 70:63] node _io_dmem_req_bits_req_cmd_T_10 = eq(UInt<3>(0h0), _io_dmem_req_bits_T_1.param) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 76:63] node _io_dmem_req_bits_req_cmd_T_11 = mux(_io_dmem_req_bits_req_cmd_T_10, UInt<4>(0h9), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 76:63] node _io_dmem_req_bits_req_cmd_T_12 = eq(UInt<3>(0h1), _io_dmem_req_bits_T_1.param) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 76:63] node _io_dmem_req_bits_req_cmd_T_13 = mux(_io_dmem_req_bits_req_cmd_T_12, UInt<4>(0ha), _io_dmem_req_bits_req_cmd_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 76:63] node _io_dmem_req_bits_req_cmd_T_14 = eq(UInt<3>(0h2), _io_dmem_req_bits_T_1.param) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 76:63] node _io_dmem_req_bits_req_cmd_T_15 = mux(_io_dmem_req_bits_req_cmd_T_14, UInt<4>(0hb), _io_dmem_req_bits_req_cmd_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 76:63] node _io_dmem_req_bits_req_cmd_T_16 = eq(UInt<3>(0h3), _io_dmem_req_bits_T_1.param) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 76:63] node _io_dmem_req_bits_req_cmd_T_17 = mux(_io_dmem_req_bits_req_cmd_T_16, UInt<3>(0h4), _io_dmem_req_bits_req_cmd_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 76:63] node _io_dmem_req_bits_req_cmd_T_18 = eq(UInt<1>(0h0), _io_dmem_req_bits_T_1.opcode) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 67:44] node _io_dmem_req_bits_req_cmd_T_19 = mux(_io_dmem_req_bits_req_cmd_T_18, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 67:44] node _io_dmem_req_bits_req_cmd_T_20 = eq(UInt<1>(0h1), _io_dmem_req_bits_T_1.opcode) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 67:44] node _io_dmem_req_bits_req_cmd_T_21 = mux(_io_dmem_req_bits_req_cmd_T_20, UInt<5>(0h11), _io_dmem_req_bits_req_cmd_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 67:44] node _io_dmem_req_bits_req_cmd_T_22 = eq(UInt<2>(0h2), _io_dmem_req_bits_T_1.opcode) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 67:44] node _io_dmem_req_bits_req_cmd_T_23 = mux(_io_dmem_req_bits_req_cmd_T_22, _io_dmem_req_bits_req_cmd_T_9, _io_dmem_req_bits_req_cmd_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 67:44] node _io_dmem_req_bits_req_cmd_T_24 = eq(UInt<2>(0h3), _io_dmem_req_bits_T_1.opcode) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 67:44] node _io_dmem_req_bits_req_cmd_T_25 = mux(_io_dmem_req_bits_req_cmd_T_24, _io_dmem_req_bits_req_cmd_T_17, _io_dmem_req_bits_req_cmd_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 67:44] node _io_dmem_req_bits_req_cmd_T_26 = eq(UInt<3>(0h4), _io_dmem_req_bits_T_1.opcode) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 67:44] node _io_dmem_req_bits_req_cmd_T_27 = mux(_io_dmem_req_bits_req_cmd_T_26, UInt<1>(0h0), _io_dmem_req_bits_req_cmd_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 67:44] connect io_dmem_req_bits_req.cmd, _io_dmem_req_bits_req_cmd_T_27 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 67:15] wire io_dmem_req_bits_mask_full_desired_mask_size : UInt<2> @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 11:18] connect io_dmem_req_bits_mask_full_desired_mask_size, _io_dmem_req_bits_T_1.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 12:8] node _io_dmem_req_bits_mask_full_desired_mask_upper_T = bits(_io_dmem_req_bits_T_1.address, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:27] node _io_dmem_req_bits_mask_full_desired_mask_upper_T_1 = mux(_io_dmem_req_bits_mask_full_desired_mask_upper_T, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:22] node _io_dmem_req_bits_mask_full_desired_mask_upper_T_2 = geq(io_dmem_req_bits_mask_full_desired_mask_size, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:53] node _io_dmem_req_bits_mask_full_desired_mask_upper_T_3 = mux(_io_dmem_req_bits_mask_full_desired_mask_upper_T_2, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:47] node io_dmem_req_bits_mask_full_desired_mask_upper = or(_io_dmem_req_bits_mask_full_desired_mask_upper_T_1, _io_dmem_req_bits_mask_full_desired_mask_upper_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:42] node _io_dmem_req_bits_mask_full_desired_mask_lower_T = bits(_io_dmem_req_bits_T_1.address, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 21:27] node io_dmem_req_bits_mask_full_desired_mask_lower = mux(_io_dmem_req_bits_mask_full_desired_mask_lower_T, UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 21:22] node _io_dmem_req_bits_mask_full_desired_mask_T = cat(io_dmem_req_bits_mask_full_desired_mask_upper, io_dmem_req_bits_mask_full_desired_mask_lower) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 22:16] node _io_dmem_req_bits_mask_full_desired_mask_upper_T_4 = bits(_io_dmem_req_bits_T_1.address, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:27] node _io_dmem_req_bits_mask_full_desired_mask_upper_T_5 = mux(_io_dmem_req_bits_mask_full_desired_mask_upper_T_4, _io_dmem_req_bits_mask_full_desired_mask_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:22] node _io_dmem_req_bits_mask_full_desired_mask_upper_T_6 = geq(io_dmem_req_bits_mask_full_desired_mask_size, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:53] node _io_dmem_req_bits_mask_full_desired_mask_upper_T_7 = mux(_io_dmem_req_bits_mask_full_desired_mask_upper_T_6, UInt<2>(0h3), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:47] node io_dmem_req_bits_mask_full_desired_mask_upper_1 = or(_io_dmem_req_bits_mask_full_desired_mask_upper_T_5, _io_dmem_req_bits_mask_full_desired_mask_upper_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:42] node _io_dmem_req_bits_mask_full_desired_mask_lower_T_1 = bits(_io_dmem_req_bits_T_1.address, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 21:27] node io_dmem_req_bits_mask_full_desired_mask_lower_1 = mux(_io_dmem_req_bits_mask_full_desired_mask_lower_T_1, UInt<1>(0h0), _io_dmem_req_bits_mask_full_desired_mask_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 21:22] node _io_dmem_req_bits_mask_full_desired_mask_T_1 = cat(io_dmem_req_bits_mask_full_desired_mask_upper_1, io_dmem_req_bits_mask_full_desired_mask_lower_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 22:16] node _io_dmem_req_bits_mask_full_desired_mask_upper_T_8 = bits(_io_dmem_req_bits_T_1.address, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:27] node _io_dmem_req_bits_mask_full_desired_mask_upper_T_9 = mux(_io_dmem_req_bits_mask_full_desired_mask_upper_T_8, _io_dmem_req_bits_mask_full_desired_mask_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:22] node _io_dmem_req_bits_mask_full_desired_mask_upper_T_10 = geq(io_dmem_req_bits_mask_full_desired_mask_size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:53] node _io_dmem_req_bits_mask_full_desired_mask_upper_T_11 = mux(_io_dmem_req_bits_mask_full_desired_mask_upper_T_10, UInt<4>(0hf), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:47] node io_dmem_req_bits_mask_full_desired_mask_upper_2 = or(_io_dmem_req_bits_mask_full_desired_mask_upper_T_9, _io_dmem_req_bits_mask_full_desired_mask_upper_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 20:42] node _io_dmem_req_bits_mask_full_desired_mask_lower_T_2 = bits(_io_dmem_req_bits_T_1.address, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 21:27] node io_dmem_req_bits_mask_full_desired_mask_lower_2 = mux(_io_dmem_req_bits_mask_full_desired_mask_lower_T_2, UInt<1>(0h0), _io_dmem_req_bits_mask_full_desired_mask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 21:22] node io_dmem_req_bits_mask_full_desired_mask = cat(io_dmem_req_bits_mask_full_desired_mask_upper_2, io_dmem_req_bits_mask_full_desired_mask_lower_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 22:16] node _io_dmem_req_bits_mask_full_T = not(io_dmem_req_bits_mask_full_desired_mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 87:19] node _io_dmem_req_bits_mask_full_T_1 = or(_io_dmem_req_bits_T_1.mask, _io_dmem_req_bits_mask_full_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 87:17] node io_dmem_req_bits_mask_full = andr(_io_dmem_req_bits_mask_full_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 87:34] node _io_dmem_req_bits_T_2 = eq(state, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 89:19] node _io_dmem_req_bits_T_3 = eq(_io_dmem_req_bits_T_1.opcode, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 89:43] node _io_dmem_req_bits_T_4 = and(_io_dmem_req_bits_T_3, io_dmem_req_bits_mask_full) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 89:73] node _io_dmem_req_bits_T_5 = or(_io_dmem_req_bits_T_2, _io_dmem_req_bits_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 89:30] when _io_dmem_req_bits_T_5 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 89:88] connect io_dmem_req_bits_req.cmd, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 90:17] connect io_dmem_req_bits_req.size, _io_dmem_req_bits_T_1.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 93:16] connect io_dmem_req_bits_req.signed, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 94:18] connect io_dmem_req_bits_req.addr, _io_dmem_req_bits_T_1.address @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 95:16] connect io_dmem_req_bits_req.tag, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 96:15] connect io_dmem_req_bits_req.phys, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 97:16] connect io_dmem_req_bits_req.no_xcpt, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 98:19] connect io_dmem_req_bits_req.no_resp, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 99:19] connect io_dmem_req_bits_req.data, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 100:16] connect io_dmem_req_bits_req.no_alloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 101:20] connect io_dmem_req_bits_req.mask, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 102:16] connect io_dmem_req_bits_req.dprv, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 103:16] connect io_dmem_req_bits_req.dv, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 104:14] connect io.dmem.req.bits, io_dmem_req_bits_req @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 119:22] connect io.dmem.s1_data.data, acq.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 120:26] connect io.dmem.s1_data.mask, acq.mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 121:26] node _io_dmem_s1_kill_T = neq(state, UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 122:30] connect io.dmem.s1_kill, _io_dmem_s1_kill_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 122:21] connect io.dmem.s2_kill, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 123:21] node _nodeIn_d_valid_T = eq(state, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 125:50] node _nodeIn_d_valid_T_1 = or(io.dmem.resp.valid, _nodeIn_d_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 125:41] connect nodeIn.d.valid, _nodeIn_d_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 125:19] node _nodeIn_d_bits_T = eq(acq.opcode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _nodeIn_d_bits_T_1 = eq(acq.opcode, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _nodeIn_d_bits_T_2 = or(_nodeIn_d_bits_T, _nodeIn_d_bits_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 792:17] connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 793:15] connect nodeIn_d_bits_d.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 794:15] connect nodeIn_d_bits_d.size, acq.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 795:15] connect nodeIn_d_bits_d.source, acq.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 796:15] connect nodeIn_d_bits_d.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 797:15] connect nodeIn_d_bits_d.denied, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 798:15] invalidate nodeIn_d_bits_d.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 801:15] connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 802:15] wire nodeIn_d_bits_d_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 810:17] connect nodeIn_d_bits_d_1.opcode, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 811:15] connect nodeIn_d_bits_d_1.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 812:15] connect nodeIn_d_bits_d_1.size, acq.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 813:15] connect nodeIn_d_bits_d_1.source, acq.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 814:15] connect nodeIn_d_bits_d_1.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 815:15] connect nodeIn_d_bits_d_1.denied, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 816:15] connect nodeIn_d_bits_d_1.data, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 819:15] connect nodeIn_d_bits_d_1.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 820:15] node _nodeIn_d_bits_T_3 = mux(_nodeIn_d_bits_T_2, nodeIn_d_bits_d, nodeIn_d_bits_d_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 126:24] connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_T_3.corrupt @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 126:18] connect nodeIn.d.bits.data, _nodeIn_d_bits_T_3.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 126:18] connect nodeIn.d.bits.denied, _nodeIn_d_bits_T_3.denied @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 126:18] connect nodeIn.d.bits.sink, _nodeIn_d_bits_T_3.sink @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 126:18] connect nodeIn.d.bits.source, _nodeIn_d_bits_T_3.source @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 126:18] connect nodeIn.d.bits.size, _nodeIn_d_bits_T_3.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 126:18] connect nodeIn.d.bits.param, _nodeIn_d_bits_T_3.param @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 126:18] connect nodeIn.d.bits.opcode, _nodeIn_d_bits_T_3.opcode @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 126:18] node _nodeIn_d_bits_data_T = eq(state, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 129:70] reg nodeIn_d_bits_data_r : UInt<64>, clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 89:63] when _nodeIn_d_bits_data_T : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 89:63] connect nodeIn_d_bits_data_r, io.dmem.resp.bits.data_raw @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 89:63] node _nodeIn_d_bits_data_T_1 = mux(_nodeIn_d_bits_data_T, io.dmem.resp.bits.data_raw, nodeIn_d_bits_data_r) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 89:42] connect nodeIn.d.bits.data, _nodeIn_d_bits_data_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 129:23] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 132:19] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 133:19] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala 134:19] module Repeater_TLBundleA_a32d64s2k1z3u : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 10:7] output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 13:14] regreset full : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 20:21] reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 21:18] node _io_deq_valid_T = or(io.enq.valid, full) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:32] connect io.deq.valid, _io_deq_valid_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 24:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:35] node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:32] connect io.enq.ready, _io_enq_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 25:16] node _io_deq_bits_T = mux(full, saved, io.enq.bits) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:21] connect io.deq.bits, _io_deq_bits_T @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 26:15] connect io.full, full @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 27:11] node _T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_1 = and(_T, io.repeat) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:21] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:36] connect full, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:43] connect saved, io.enq.bits @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 29:60] node _T_2 = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_3 = eq(io.repeat, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:24] node _T_4 = and(_T_2, _T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:21] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:36] connect full, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Repeater.scala 30:43] module TLFragmenter_1 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 92:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 201:29] reg dOrig : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 202:24] regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 203:30] node dFragnum = bits(anonOut.d.bits.source, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 204:41] node dFirst = eq(acknum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 205:29] node dLast = eq(dFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 206:30] node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node dsizeOH = bits(_dsizeOH_T, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node dsizeOH1 = not(_dsizeOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node dHasData = bits(anonOut.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node acknum_fragment = shl(dFragnum, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 212:40] node acknum_size = shr(dsizeOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 213:36] node _T = eq(anonOut.d.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:17] node _T_1 = and(acknum_fragment, acknum_size) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:50] node _T_2 = eq(_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:65] node _T_3 = or(_T, _T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:30] node _T_4 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _T_5 = eq(_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _T_6 = eq(_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] when _T_6 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] assert(clock, _T_3, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 214:16] node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 215:50] node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 215:45] node _ack_decrement_T = shr(dsizeOH, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 216:56] node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 216:32] node _dFirst_size_T = shl(dFragnum, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 218:47] node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 218:69] node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:35] node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:40] node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:53] node _dFirst_size_T_5 = not(_dFirst_size_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:49] node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 242:47] node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _dFirst_size_T_7 = orr(dFirst_size_hi) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _dFirst_size_T_9 = orr(dFirst_size_hi_1) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) @[src/main/scala/chisel3/util/CircuitMath.scala 28:8] node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node _T_7 = and(anonOut.d.ready, anonOut.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_7 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 220:27] node _acknum_T = sub(acknum, ack_decrement) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:55] node _acknum_T_1 = tail(_acknum_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:55] node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:24] connect acknum, _acknum_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 221:18] when dFirst : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 222:25] connect dOrig, dFirst_size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 223:19] node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 224:41] connect dToggle, _dToggle_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 224:21] node doEarlyAck = bits(anonOut.d.bits.source, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 231:54] node _drop_T = eq(dHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:20] node _drop_T_1 = mux(doEarlyAck, dFirst, dLast) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:37] node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:33] node drop = and(_drop_T, _drop_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 234:30] node _anonOut_d_ready_T = or(anonIn.d.ready, drop) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 235:35] connect anonOut.d.ready, _anonOut_d_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 235:21] node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:39] node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:36] connect anonIn.d.valid, _anonIn_d_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 236:21] connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] connect anonIn.d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 237:21] node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 238:47] connect anonIn.d.bits.source, _anonIn_d_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 238:26] node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 239:32] connect anonIn.d.bits.size, _anonIn_d_bits_size_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 239:26] inst repeater of Repeater_TLBundleA_a32d64s2k1z3u @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 274:30] connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 275:25] node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _find_T_1 = cvt(_find_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_3 = asSInt(_find_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] wire find : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] connect find[0], _find_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 616:12] node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 288:49] node _aFrag_T = gt(repeater.io.deq.bits.size, limit) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 297:31] node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 297:24] node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node aOrigOH1 = not(_aOrigOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node aFragOH1 = not(_aFragOH1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 301:24] regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 303:29] node aFirst = eq(gennum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 304:29] node _old_gennum1_T = shr(aOrigOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:48] node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:79] node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:79] node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 305:30] node _new_gennum_T = not(old_gennum1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:28] node _new_gennum_T_1 = shr(aMask, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:50] node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:41] node new_gennum = not(_new_gennum_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 306:26] node _aFragnum_T = shr(old_gennum1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:40] node _aFragnum_T_1 = not(_aFragnum_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:26] node _aFragnum_T_2 = shr(aFragOH1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:84] node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:72] node aFragnum = not(_aFragnum_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 307:24] node aLast = eq(aFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 308:30] reg aToggle_r : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] when aFirst : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] connect aToggle_r, dToggle @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:54] node _aToggle_T = mux(aFirst, dToggle, aToggle_r) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:27] node aToggle = eq(_aToggle_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 309:23] node aFull = eq(repeater.io.deq.bits.opcode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 310:78] node _T_8 = and(anonOut.a.ready, anonOut.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 312:27] connect gennum, new_gennum @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 312:36] node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:31] node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:53] node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:41] connect repeater.io.repeat, _repeater_io_repeat_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 314:28] connect anonOut.a.bits, repeater.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] connect anonOut.a.valid, repeater.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] connect repeater.io.deq.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 315:15] node _anonOut_a_bits_address_T = shl(old_gennum1, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:65] node _anonOut_a_bits_address_T_1 = not(aOrigOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:90] node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:88] node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:100] node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:111] node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:51] node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:49] connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 316:28] node anonOut_a_bits_source_lo = cat(aToggle, aFragnum) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aFull) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, anonOut_a_bits_source_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:33] connect anonOut.a.bits.source, _anonOut_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 317:27] connect anonOut.a.bits.size, aFrag @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 318:25] node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:17] node _T_10 = eq(aHasData, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:38] node _T_11 = or(_T_9, _T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:35] node _T_12 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] node _T_13 = eq(_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] when _T_13 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] node _T_14 = eq(_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] when _T_14 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 321:16] connect anonOut.a.bits.data, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 322:25] node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:17] node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:53] node _T_17 = or(_T_15, _T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:35] node _T_18 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _T_19 = eq(_T_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] when _T_19 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _T_20 = eq(_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] when _T_20 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 324:16] node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 325:31] connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 325:25] wire anonOut_a_bits_user_out : { } @[hardware/upstream/rocket-chip/src/main/scala/util/BundleMap.scala 114:19] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 329:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 330:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 331:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 332:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 333:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 334:21] module TLBuffer_a32d64s1k1z4u_1 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut.a, nodeIn.a @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] connect nodeIn.d, nodeOut.d @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 52:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 53:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 54:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 55:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 56:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 57:21] module TLBuffer_a32d64s2k1z3u : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut.a, nodeIn.a @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] connect nodeIn.d, nodeOut.d @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 52:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 53:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 54:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 55:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 56:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 57:21] module FPUDecoder : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 55:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 55:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 55:7] output io : { flip inst : UInt<32>, sigs : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 56:14] wire decoder_decoded_plaInput : UInt<32> @[src/main/scala/chisel3/util/pla.scala 77:22] node decoder_decoded_invInputs = not(decoder_decoded_plaInput) @[src/main/scala/chisel3/util/pla.scala 78:21] wire decoder_decoded : UInt<19> @[src/main/scala/chisel3/util/pla.scala 81:23] node decoder_decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3, decoder_decoded_andMatrixOutputs_andMatrixInput_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0, decoder_decoded_andMatrixOutputs_andMatrixInput_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi = cat(decoder_decoded_andMatrixOutputs_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T = cat(decoder_decoded_andMatrixOutputs_hi, decoder_decoded_andMatrixOutputs_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_35_2 = andr(_decoder_decoded_andMatrixOutputs_T) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9, decoder_decoded_andMatrixOutputs_andMatrixInput_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6, decoder_decoded_andMatrixOutputs_andMatrixInput_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_1 = cat(decoder_decoded_andMatrixOutputs_lo_hi, decoder_decoded_andMatrixOutputs_lo_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_1, decoder_decoded_andMatrixOutputs_andMatrixInput_4_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, decoder_decoded_andMatrixOutputs_andMatrixInput_1_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_1 = cat(decoder_decoded_andMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_hi_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_1 = cat(decoder_decoded_andMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_0_2 = andr(_decoder_decoded_andMatrixOutputs_T_1) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_1, decoder_decoded_andMatrixOutputs_andMatrixInput_10_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, decoder_decoded_andMatrixOutputs_andMatrixInput_7_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_8_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_2 = cat(decoder_decoded_andMatrixOutputs_lo_hi_1, decoder_decoded_andMatrixOutputs_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_2, decoder_decoded_andMatrixOutputs_andMatrixInput_4_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, decoder_decoded_andMatrixOutputs_andMatrixInput_1_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_2 = cat(decoder_decoded_andMatrixOutputs_hi_hi_2, decoder_decoded_andMatrixOutputs_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_2 = cat(decoder_decoded_andMatrixOutputs_hi_2, decoder_decoded_andMatrixOutputs_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_33_2 = andr(_decoder_decoded_andMatrixOutputs_T_2) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_2, decoder_decoded_andMatrixOutputs_andMatrixInput_10_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_11_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, decoder_decoded_andMatrixOutputs_andMatrixInput_7_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_8_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_3 = cat(decoder_decoded_andMatrixOutputs_lo_hi_2, decoder_decoded_andMatrixOutputs_lo_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_3, decoder_decoded_andMatrixOutputs_andMatrixInput_4_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, decoder_decoded_andMatrixOutputs_andMatrixInput_1_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_3 = cat(decoder_decoded_andMatrixOutputs_hi_hi_3, decoder_decoded_andMatrixOutputs_hi_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_3 = cat(decoder_decoded_andMatrixOutputs_hi_3, decoder_decoded_andMatrixOutputs_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_36_2 = andr(_decoder_decoded_andMatrixOutputs_T_3) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_3, decoder_decoded_andMatrixOutputs_andMatrixInput_7_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_4 = cat(decoder_decoded_andMatrixOutputs_lo_hi_3, decoder_decoded_andMatrixOutputs_lo_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, decoder_decoded_andMatrixOutputs_andMatrixInput_3_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, decoder_decoded_andMatrixOutputs_andMatrixInput_1_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_4 = cat(decoder_decoded_andMatrixOutputs_hi_hi_4, decoder_decoded_andMatrixOutputs_hi_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_4 = cat(decoder_decoded_andMatrixOutputs_hi_4, decoder_decoded_andMatrixOutputs_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_8_2 = andr(_decoder_decoded_andMatrixOutputs_T_4) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_4, decoder_decoded_andMatrixOutputs_andMatrixInput_8_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_4, decoder_decoded_andMatrixOutputs_andMatrixInput_6_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_5 = cat(decoder_decoded_andMatrixOutputs_lo_hi_4, decoder_decoded_andMatrixOutputs_lo_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, decoder_decoded_andMatrixOutputs_andMatrixInput_4_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, decoder_decoded_andMatrixOutputs_andMatrixInput_1_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_2_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_5 = cat(decoder_decoded_andMatrixOutputs_hi_hi_5, decoder_decoded_andMatrixOutputs_hi_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_5 = cat(decoder_decoded_andMatrixOutputs_hi_5, decoder_decoded_andMatrixOutputs_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_18_2 = andr(_decoder_decoded_andMatrixOutputs_T_5) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_5, decoder_decoded_andMatrixOutputs_andMatrixInput_8_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, decoder_decoded_andMatrixOutputs_andMatrixInput_6_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_6 = cat(decoder_decoded_andMatrixOutputs_lo_hi_5, decoder_decoded_andMatrixOutputs_lo_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, decoder_decoded_andMatrixOutputs_andMatrixInput_4_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, decoder_decoded_andMatrixOutputs_andMatrixInput_1_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_6 = cat(decoder_decoded_andMatrixOutputs_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_6 = cat(decoder_decoded_andMatrixOutputs_hi_6, decoder_decoded_andMatrixOutputs_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_24_2 = andr(_decoder_decoded_andMatrixOutputs_T_6) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, decoder_decoded_andMatrixOutputs_andMatrixInput_9_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, decoder_decoded_andMatrixOutputs_andMatrixInput_6_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_7_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_7 = cat(decoder_decoded_andMatrixOutputs_lo_hi_6, decoder_decoded_andMatrixOutputs_lo_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, decoder_decoded_andMatrixOutputs_andMatrixInput_4_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, decoder_decoded_andMatrixOutputs_andMatrixInput_1_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_7 = cat(decoder_decoded_andMatrixOutputs_hi_hi_7, decoder_decoded_andMatrixOutputs_hi_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_7 = cat(decoder_decoded_andMatrixOutputs_hi_7, decoder_decoded_andMatrixOutputs_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_11_2 = andr(_decoder_decoded_andMatrixOutputs_T_7) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_8, decoder_decoded_andMatrixOutputs_andMatrixInput_5_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_8 = cat(decoder_decoded_andMatrixOutputs_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_6_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, decoder_decoded_andMatrixOutputs_andMatrixInput_3_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, decoder_decoded_andMatrixOutputs_andMatrixInput_1_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_8 = cat(decoder_decoded_andMatrixOutputs_hi_hi_8, decoder_decoded_andMatrixOutputs_hi_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_8 = cat(decoder_decoded_andMatrixOutputs_hi_8, decoder_decoded_andMatrixOutputs_lo_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_16_2 = andr(_decoder_decoded_andMatrixOutputs_T_8) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_4, decoder_decoded_andMatrixOutputs_andMatrixInput_10_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_7 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_11_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_8 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_8_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_9 = cat(decoder_decoded_andMatrixOutputs_lo_hi_8, decoder_decoded_andMatrixOutputs_lo_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, decoder_decoded_andMatrixOutputs_andMatrixInput_4_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_8 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, decoder_decoded_andMatrixOutputs_andMatrixInput_1_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_2_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_9 = cat(decoder_decoded_andMatrixOutputs_hi_hi_9, decoder_decoded_andMatrixOutputs_hi_lo_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_9 = cat(decoder_decoded_andMatrixOutputs_hi_9, decoder_decoded_andMatrixOutputs_lo_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_20_2 = andr(_decoder_decoded_andMatrixOutputs_T_9) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoder_decoded_plaInput, 27, 27) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, decoder_decoded_andMatrixOutputs_andMatrixInput_11_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_8 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_8, decoder_decoded_andMatrixOutputs_andMatrixInput_8_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_9 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_9_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_10 = cat(decoder_decoded_andMatrixOutputs_lo_hi_9, decoder_decoded_andMatrixOutputs_lo_lo_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, decoder_decoded_andMatrixOutputs_andMatrixInput_5_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_9 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_6_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, decoder_decoded_andMatrixOutputs_andMatrixInput_3_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, decoder_decoded_andMatrixOutputs_andMatrixInput_1_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_10 = cat(decoder_decoded_andMatrixOutputs_hi_hi_10, decoder_decoded_andMatrixOutputs_hi_lo_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_10 = cat(decoder_decoded_andMatrixOutputs_hi_10, decoder_decoded_andMatrixOutputs_lo_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_3_2 = andr(_decoder_decoded_andMatrixOutputs_T_10) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_4, decoder_decoded_andMatrixOutputs_andMatrixInput_12_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_9 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, decoder_decoded_andMatrixOutputs_andMatrixInput_10_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, decoder_decoded_andMatrixOutputs_andMatrixInput_8_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_10 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_11 = cat(decoder_decoded_andMatrixOutputs_lo_hi_10, decoder_decoded_andMatrixOutputs_lo_lo_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, decoder_decoded_andMatrixOutputs_andMatrixInput_5_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_10 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_6_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, decoder_decoded_andMatrixOutputs_andMatrixInput_3_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, decoder_decoded_andMatrixOutputs_andMatrixInput_1_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_hi_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_11 = cat(decoder_decoded_andMatrixOutputs_hi_hi_11, decoder_decoded_andMatrixOutputs_hi_lo_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_11 = cat(decoder_decoded_andMatrixOutputs_hi_11, decoder_decoded_andMatrixOutputs_lo_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_9_2 = andr(_decoder_decoded_andMatrixOutputs_T_11) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_5, decoder_decoded_andMatrixOutputs_andMatrixInput_12_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_10 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_13_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_7, decoder_decoded_andMatrixOutputs_andMatrixInput_10_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_10, decoder_decoded_andMatrixOutputs_andMatrixInput_8_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_11 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_lo_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_12 = cat(decoder_decoded_andMatrixOutputs_lo_hi_11, decoder_decoded_andMatrixOutputs_lo_lo_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, decoder_decoded_andMatrixOutputs_andMatrixInput_5_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_11 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_6_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, decoder_decoded_andMatrixOutputs_andMatrixInput_3_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, decoder_decoded_andMatrixOutputs_andMatrixInput_1_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_12 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_hi_hi_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_12 = cat(decoder_decoded_andMatrixOutputs_hi_hi_12, decoder_decoded_andMatrixOutputs_hi_lo_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_12 = cat(decoder_decoded_andMatrixOutputs_hi_12, decoder_decoded_andMatrixOutputs_lo_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_27_2 = andr(_decoder_decoded_andMatrixOutputs_T_12) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_6, decoder_decoded_andMatrixOutputs_andMatrixInput_12_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_11 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_13_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_8, decoder_decoded_andMatrixOutputs_andMatrixInput_10_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_11, decoder_decoded_andMatrixOutputs_andMatrixInput_8_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_12 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_lo_hi_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_13 = cat(decoder_decoded_andMatrixOutputs_lo_hi_12, decoder_decoded_andMatrixOutputs_lo_lo_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, decoder_decoded_andMatrixOutputs_andMatrixInput_5_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_12 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_6_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, decoder_decoded_andMatrixOutputs_andMatrixInput_3_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, decoder_decoded_andMatrixOutputs_andMatrixInput_1_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_13 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_hi_hi_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_13 = cat(decoder_decoded_andMatrixOutputs_hi_hi_13, decoder_decoded_andMatrixOutputs_hi_lo_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_13 = cat(decoder_decoded_andMatrixOutputs_hi_13, decoder_decoded_andMatrixOutputs_lo_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_22_2 = andr(_decoder_decoded_andMatrixOutputs_T_13) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, decoder_decoded_andMatrixOutputs_andMatrixInput_13_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_12 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_8, decoder_decoded_andMatrixOutputs_andMatrixInput_11_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_11, decoder_decoded_andMatrixOutputs_andMatrixInput_9_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_13 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_lo_hi_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_14 = cat(decoder_decoded_andMatrixOutputs_lo_hi_13, decoder_decoded_andMatrixOutputs_lo_lo_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, decoder_decoded_andMatrixOutputs_andMatrixInput_7_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, decoder_decoded_andMatrixOutputs_andMatrixInput_5_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_13 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_8, decoder_decoded_andMatrixOutputs_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, decoder_decoded_andMatrixOutputs_andMatrixInput_3_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, decoder_decoded_andMatrixOutputs_andMatrixInput_1_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_14 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_hi_hi_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_14 = cat(decoder_decoded_andMatrixOutputs_hi_hi_14, decoder_decoded_andMatrixOutputs_hi_lo_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_14 = cat(decoder_decoded_andMatrixOutputs_hi_14, decoder_decoded_andMatrixOutputs_lo_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_14_2 = andr(_decoder_decoded_andMatrixOutputs_T_14) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, decoder_decoded_andMatrixOutputs_andMatrixInput_13_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_13 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_14_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, decoder_decoded_andMatrixOutputs_andMatrixInput_11_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, decoder_decoded_andMatrixOutputs_andMatrixInput_9_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_14 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_10, decoder_decoded_andMatrixOutputs_lo_hi_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_15 = cat(decoder_decoded_andMatrixOutputs_lo_hi_14, decoder_decoded_andMatrixOutputs_lo_lo_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, decoder_decoded_andMatrixOutputs_andMatrixInput_7_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, decoder_decoded_andMatrixOutputs_andMatrixInput_5_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_14 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_9, decoder_decoded_andMatrixOutputs_hi_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, decoder_decoded_andMatrixOutputs_andMatrixInput_3_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, decoder_decoded_andMatrixOutputs_andMatrixInput_1_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_hi_hi_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_15 = cat(decoder_decoded_andMatrixOutputs_hi_hi_15, decoder_decoded_andMatrixOutputs_hi_lo_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_15 = cat(decoder_decoded_andMatrixOutputs_hi_15, decoder_decoded_andMatrixOutputs_lo_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_19_2 = andr(_decoder_decoded_andMatrixOutputs_T_15) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_6, decoder_decoded_andMatrixOutputs_andMatrixInput_13_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_14 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_14_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_10, decoder_decoded_andMatrixOutputs_andMatrixInput_11_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_13, decoder_decoded_andMatrixOutputs_andMatrixInput_9_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_15 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_11, decoder_decoded_andMatrixOutputs_lo_hi_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_16 = cat(decoder_decoded_andMatrixOutputs_lo_hi_15, decoder_decoded_andMatrixOutputs_lo_lo_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, decoder_decoded_andMatrixOutputs_andMatrixInput_7_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, decoder_decoded_andMatrixOutputs_andMatrixInput_5_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_15 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_10, decoder_decoded_andMatrixOutputs_hi_lo_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, decoder_decoded_andMatrixOutputs_andMatrixInput_3_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, decoder_decoded_andMatrixOutputs_andMatrixInput_1_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_hi_hi_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_16 = cat(decoder_decoded_andMatrixOutputs_hi_hi_16, decoder_decoded_andMatrixOutputs_hi_lo_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_16 = cat(decoder_decoded_andMatrixOutputs_hi_16, decoder_decoded_andMatrixOutputs_lo_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_10_2 = andr(_decoder_decoded_andMatrixOutputs_T_16) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, decoder_decoded_andMatrixOutputs_andMatrixInput_13_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_15 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_14_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, decoder_decoded_andMatrixOutputs_andMatrixInput_11_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_14, decoder_decoded_andMatrixOutputs_andMatrixInput_9_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_16 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_12, decoder_decoded_andMatrixOutputs_lo_hi_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_17 = cat(decoder_decoded_andMatrixOutputs_lo_hi_16, decoder_decoded_andMatrixOutputs_lo_lo_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_16, decoder_decoded_andMatrixOutputs_andMatrixInput_7_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_17, decoder_decoded_andMatrixOutputs_andMatrixInput_5_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_16 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_11, decoder_decoded_andMatrixOutputs_hi_lo_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, decoder_decoded_andMatrixOutputs_andMatrixInput_3_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, decoder_decoded_andMatrixOutputs_andMatrixInput_1_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_17 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_hi_hi_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_17 = cat(decoder_decoded_andMatrixOutputs_hi_hi_17, decoder_decoded_andMatrixOutputs_hi_lo_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_17 = cat(decoder_decoded_andMatrixOutputs_hi_17, decoder_decoded_andMatrixOutputs_lo_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_21_2 = andr(_decoder_decoded_andMatrixOutputs_T_17) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoder_decoded_plaInput, 27, 27) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_8, decoder_decoded_andMatrixOutputs_andMatrixInput_13_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_16 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_14_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, decoder_decoded_andMatrixOutputs_andMatrixInput_11_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_15, decoder_decoded_andMatrixOutputs_andMatrixInput_9_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_17 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_13, decoder_decoded_andMatrixOutputs_lo_hi_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_18 = cat(decoder_decoded_andMatrixOutputs_lo_hi_17, decoder_decoded_andMatrixOutputs_lo_lo_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, decoder_decoded_andMatrixOutputs_andMatrixInput_7_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_18, decoder_decoded_andMatrixOutputs_andMatrixInput_5_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_17 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_12, decoder_decoded_andMatrixOutputs_hi_lo_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_18, decoder_decoded_andMatrixOutputs_andMatrixInput_3_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, decoder_decoded_andMatrixOutputs_andMatrixInput_1_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_18 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_hi_hi_lo_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_18 = cat(decoder_decoded_andMatrixOutputs_hi_hi_18, decoder_decoded_andMatrixOutputs_hi_lo_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_18 = cat(decoder_decoded_andMatrixOutputs_hi_18, decoder_decoded_andMatrixOutputs_lo_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_31_2 = andr(_decoder_decoded_andMatrixOutputs_T_18) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoder_decoded_plaInput, 20, 20) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_15 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_16 = bits(decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_17 = bits(decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_lo_lo_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16, decoder_decoded_andMatrixOutputs_andMatrixInput_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, decoder_decoded_andMatrixOutputs_andMatrixInput_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_17 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_12, decoder_decoded_andMatrixOutputs_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_9, decoder_decoded_andMatrixOutputs_andMatrixInput_13_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_14, decoder_decoded_andMatrixOutputs_andMatrixInput_10_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_11_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_18 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_14, decoder_decoded_andMatrixOutputs_lo_hi_lo_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_19 = cat(decoder_decoded_andMatrixOutputs_lo_hi_18, decoder_decoded_andMatrixOutputs_lo_lo_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, decoder_decoded_andMatrixOutputs_andMatrixInput_8_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_18, decoder_decoded_andMatrixOutputs_andMatrixInput_6_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_18 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_13, decoder_decoded_andMatrixOutputs_hi_lo_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, decoder_decoded_andMatrixOutputs_andMatrixInput_4_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, decoder_decoded_andMatrixOutputs_andMatrixInput_1_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_hi_hi_lo_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_19 = cat(decoder_decoded_andMatrixOutputs_hi_hi_19, decoder_decoded_andMatrixOutputs_hi_lo_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_19 = cat(decoder_decoded_andMatrixOutputs_hi_19, decoder_decoded_andMatrixOutputs_lo_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_7_2 = andr(_decoder_decoded_andMatrixOutputs_T_19) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoder_decoded_plaInput, 20, 20) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = bits(decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_18 = bits(decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_1, decoder_decoded_andMatrixOutputs_andMatrixInput_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_1, decoder_decoded_andMatrixOutputs_andMatrixInput_16_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_18 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_13, decoder_decoded_andMatrixOutputs_lo_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_9, decoder_decoded_andMatrixOutputs_andMatrixInput_14_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_14, decoder_decoded_andMatrixOutputs_andMatrixInput_11_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_12_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_19 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_lo_hi_lo_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_20 = cat(decoder_decoded_andMatrixOutputs_lo_hi_19, decoder_decoded_andMatrixOutputs_lo_lo_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_17, decoder_decoded_andMatrixOutputs_andMatrixInput_9_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_19, decoder_decoded_andMatrixOutputs_andMatrixInput_6_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_7_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_19 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_14, decoder_decoded_andMatrixOutputs_hi_lo_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_20, decoder_decoded_andMatrixOutputs_andMatrixInput_4_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, decoder_decoded_andMatrixOutputs_andMatrixInput_1_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_20 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_hi_hi_lo_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_20 = cat(decoder_decoded_andMatrixOutputs_hi_hi_20, decoder_decoded_andMatrixOutputs_hi_lo_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_20 = cat(decoder_decoded_andMatrixOutputs_hi_20, decoder_decoded_andMatrixOutputs_lo_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_1_2 = andr(_decoder_decoded_andMatrixOutputs_T_20) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = bits(decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = bits(decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = bits(decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_2, decoder_decoded_andMatrixOutputs_andMatrixInput_17_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_7, decoder_decoded_andMatrixOutputs_andMatrixInput_15_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_19 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_14, decoder_decoded_andMatrixOutputs_lo_lo_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, decoder_decoded_andMatrixOutputs_andMatrixInput_13_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, decoder_decoded_andMatrixOutputs_andMatrixInput_10_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_11_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_20 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_16, decoder_decoded_andMatrixOutputs_lo_hi_lo_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_21 = cat(decoder_decoded_andMatrixOutputs_lo_hi_20, decoder_decoded_andMatrixOutputs_lo_lo_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, decoder_decoded_andMatrixOutputs_andMatrixInput_8_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_20, decoder_decoded_andMatrixOutputs_andMatrixInput_6_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_20 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_15, decoder_decoded_andMatrixOutputs_hi_lo_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, decoder_decoded_andMatrixOutputs_andMatrixInput_4_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, decoder_decoded_andMatrixOutputs_andMatrixInput_1_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_21 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_hi_hi_lo_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_21 = cat(decoder_decoded_andMatrixOutputs_hi_hi_21, decoder_decoded_andMatrixOutputs_hi_lo_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_21 = cat(decoder_decoded_andMatrixOutputs_hi_21, decoder_decoded_andMatrixOutputs_lo_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_5_2 = andr(_decoder_decoded_andMatrixOutputs_T_21) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = bits(decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = bits(decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = bits(decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = bits(decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, decoder_decoded_andMatrixOutputs_andMatrixInput_18_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_3, decoder_decoded_andMatrixOutputs_andMatrixInput_16_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_20 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_15, decoder_decoded_andMatrixOutputs_lo_lo_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_11, decoder_decoded_andMatrixOutputs_andMatrixInput_14_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_16, decoder_decoded_andMatrixOutputs_andMatrixInput_11_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_12_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_21 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_17, decoder_decoded_andMatrixOutputs_lo_hi_lo_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_22 = cat(decoder_decoded_andMatrixOutputs_lo_hi_21, decoder_decoded_andMatrixOutputs_lo_lo_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, decoder_decoded_andMatrixOutputs_andMatrixInput_9_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_21, decoder_decoded_andMatrixOutputs_andMatrixInput_6_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_7_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_21 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_16, decoder_decoded_andMatrixOutputs_hi_lo_lo_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, decoder_decoded_andMatrixOutputs_andMatrixInput_4_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, decoder_decoded_andMatrixOutputs_andMatrixInput_1_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_2_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_22 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_hi_hi_lo_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_22 = cat(decoder_decoded_andMatrixOutputs_hi_hi_22, decoder_decoded_andMatrixOutputs_hi_lo_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_22 = cat(decoder_decoded_andMatrixOutputs_hi_22, decoder_decoded_andMatrixOutputs_lo_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_12_2 = andr(_decoder_decoded_andMatrixOutputs_T_22) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = bits(decoder_decoded_plaInput, 27, 27) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = bits(decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = bits(decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = bits(decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = bits(decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_4, decoder_decoded_andMatrixOutputs_andMatrixInput_17_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, decoder_decoded_andMatrixOutputs_andMatrixInput_15_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_21 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_16, decoder_decoded_andMatrixOutputs_lo_lo_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, decoder_decoded_andMatrixOutputs_andMatrixInput_13_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_18, decoder_decoded_andMatrixOutputs_andMatrixInput_10_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_11_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_22 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_18, decoder_decoded_andMatrixOutputs_lo_hi_lo_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_23 = cat(decoder_decoded_andMatrixOutputs_lo_hi_22, decoder_decoded_andMatrixOutputs_lo_lo_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_21, decoder_decoded_andMatrixOutputs_andMatrixInput_8_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_22, decoder_decoded_andMatrixOutputs_andMatrixInput_6_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_22 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_17, decoder_decoded_andMatrixOutputs_hi_lo_lo_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, decoder_decoded_andMatrixOutputs_andMatrixInput_4_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, decoder_decoded_andMatrixOutputs_andMatrixInput_1_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_23 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_hi_hi_lo_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_23 = cat(decoder_decoded_andMatrixOutputs_hi_hi_23, decoder_decoded_andMatrixOutputs_hi_lo_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_23 = cat(decoder_decoded_andMatrixOutputs_hi_23, decoder_decoded_andMatrixOutputs_lo_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_28_2 = andr(_decoder_decoded_andMatrixOutputs_T_23) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = bits(decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = bits(decoder_decoded_plaInput, 27, 27) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = bits(decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = bits(decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = bits(decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = bits(decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_5, decoder_decoded_andMatrixOutputs_andMatrixInput_18_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_5, decoder_decoded_andMatrixOutputs_andMatrixInput_16_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_22 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_17, decoder_decoded_andMatrixOutputs_lo_lo_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_13, decoder_decoded_andMatrixOutputs_andMatrixInput_14_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_18, decoder_decoded_andMatrixOutputs_andMatrixInput_11_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_12_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_23 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_19, decoder_decoded_andMatrixOutputs_lo_hi_lo_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_24 = cat(decoder_decoded_andMatrixOutputs_lo_hi_23, decoder_decoded_andMatrixOutputs_lo_lo_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_21, decoder_decoded_andMatrixOutputs_andMatrixInput_9_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_23, decoder_decoded_andMatrixOutputs_andMatrixInput_6_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_7_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_23 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_18, decoder_decoded_andMatrixOutputs_hi_lo_lo_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, decoder_decoded_andMatrixOutputs_andMatrixInput_4_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, decoder_decoded_andMatrixOutputs_andMatrixInput_1_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_24 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_hi_hi_lo_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_24 = cat(decoder_decoded_andMatrixOutputs_hi_hi_24, decoder_decoded_andMatrixOutputs_hi_lo_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_24 = cat(decoder_decoded_andMatrixOutputs_hi_24, decoder_decoded_andMatrixOutputs_lo_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_6_2 = andr(_decoder_decoded_andMatrixOutputs_T_24) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = bits(decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = bits(decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = bits(decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_15, decoder_decoded_andMatrixOutputs_andMatrixInput_13_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_23 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_14_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_19, decoder_decoded_andMatrixOutputs_andMatrixInput_11_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_22, decoder_decoded_andMatrixOutputs_andMatrixInput_9_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_24 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_20, decoder_decoded_andMatrixOutputs_lo_hi_lo_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_25 = cat(decoder_decoded_andMatrixOutputs_lo_hi_24, decoder_decoded_andMatrixOutputs_lo_lo_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_24, decoder_decoded_andMatrixOutputs_andMatrixInput_7_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_25, decoder_decoded_andMatrixOutputs_andMatrixInput_5_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_24 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_19, decoder_decoded_andMatrixOutputs_hi_lo_lo_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_25, decoder_decoded_andMatrixOutputs_andMatrixInput_3_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, decoder_decoded_andMatrixOutputs_andMatrixInput_1_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_25 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_22, decoder_decoded_andMatrixOutputs_hi_hi_lo_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_25 = cat(decoder_decoded_andMatrixOutputs_hi_hi_25, decoder_decoded_andMatrixOutputs_hi_lo_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_25 = cat(decoder_decoded_andMatrixOutputs_hi_25, decoder_decoded_andMatrixOutputs_lo_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_32_2 = andr(_decoder_decoded_andMatrixOutputs_T_25) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = bits(decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = bits(decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = bits(decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_16, decoder_decoded_andMatrixOutputs_andMatrixInput_13_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_24 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_14_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, decoder_decoded_andMatrixOutputs_andMatrixInput_11_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_23, decoder_decoded_andMatrixOutputs_andMatrixInput_9_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_25 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_21, decoder_decoded_andMatrixOutputs_lo_hi_lo_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_26 = cat(decoder_decoded_andMatrixOutputs_lo_hi_25, decoder_decoded_andMatrixOutputs_lo_lo_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_25, decoder_decoded_andMatrixOutputs_andMatrixInput_7_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, decoder_decoded_andMatrixOutputs_andMatrixInput_5_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_25 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_20, decoder_decoded_andMatrixOutputs_hi_lo_lo_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, decoder_decoded_andMatrixOutputs_andMatrixInput_3_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, decoder_decoded_andMatrixOutputs_andMatrixInput_1_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_26 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_23, decoder_decoded_andMatrixOutputs_hi_hi_lo_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_26 = cat(decoder_decoded_andMatrixOutputs_hi_hi_26, decoder_decoded_andMatrixOutputs_hi_lo_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_26 = cat(decoder_decoded_andMatrixOutputs_hi_26, decoder_decoded_andMatrixOutputs_lo_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_29_2 = andr(_decoder_decoded_andMatrixOutputs_T_26) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = bits(decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = bits(decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = bits(decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, decoder_decoded_andMatrixOutputs_andMatrixInput_13_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_25 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_14_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, decoder_decoded_andMatrixOutputs_andMatrixInput_11_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_24, decoder_decoded_andMatrixOutputs_andMatrixInput_9_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_26 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_22, decoder_decoded_andMatrixOutputs_lo_hi_lo_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_27 = cat(decoder_decoded_andMatrixOutputs_lo_hi_26, decoder_decoded_andMatrixOutputs_lo_lo_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_26, decoder_decoded_andMatrixOutputs_andMatrixInput_7_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, decoder_decoded_andMatrixOutputs_andMatrixInput_5_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_26 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_21, decoder_decoded_andMatrixOutputs_hi_lo_lo_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, decoder_decoded_andMatrixOutputs_andMatrixInput_3_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, decoder_decoded_andMatrixOutputs_andMatrixInput_1_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_27 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_hi_hi_lo_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_27 = cat(decoder_decoded_andMatrixOutputs_hi_hi_27, decoder_decoded_andMatrixOutputs_hi_lo_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_27 = cat(decoder_decoded_andMatrixOutputs_hi_27, decoder_decoded_andMatrixOutputs_lo_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_23_2 = andr(_decoder_decoded_andMatrixOutputs_T_27) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = bits(decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = bits(decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = bits(decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_14, decoder_decoded_andMatrixOutputs_andMatrixInput_15_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, decoder_decoded_andMatrixOutputs_andMatrixInput_13_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_26 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_21, decoder_decoded_andMatrixOutputs_lo_lo_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, decoder_decoded_andMatrixOutputs_andMatrixInput_11_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_25, decoder_decoded_andMatrixOutputs_andMatrixInput_9_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_27 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_23, decoder_decoded_andMatrixOutputs_lo_hi_lo_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_28 = cat(decoder_decoded_andMatrixOutputs_lo_hi_27, decoder_decoded_andMatrixOutputs_lo_lo_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, decoder_decoded_andMatrixOutputs_andMatrixInput_7_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, decoder_decoded_andMatrixOutputs_andMatrixInput_5_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_27 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_22, decoder_decoded_andMatrixOutputs_hi_lo_lo_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, decoder_decoded_andMatrixOutputs_andMatrixInput_3_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, decoder_decoded_andMatrixOutputs_andMatrixInput_1_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_28 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_hi_hi_lo_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_28 = cat(decoder_decoded_andMatrixOutputs_hi_hi_28, decoder_decoded_andMatrixOutputs_hi_lo_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_28 = cat(decoder_decoded_andMatrixOutputs_hi_28, decoder_decoded_andMatrixOutputs_lo_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_4_2 = andr(_decoder_decoded_andMatrixOutputs_T_28) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = bits(decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = bits(decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = bits(decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, decoder_decoded_andMatrixOutputs_andMatrixInput_15_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, decoder_decoded_andMatrixOutputs_andMatrixInput_13_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_27 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_22, decoder_decoded_andMatrixOutputs_lo_lo_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, decoder_decoded_andMatrixOutputs_andMatrixInput_11_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_26, decoder_decoded_andMatrixOutputs_andMatrixInput_9_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_28 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_24, decoder_decoded_andMatrixOutputs_lo_hi_lo_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_29 = cat(decoder_decoded_andMatrixOutputs_lo_hi_28, decoder_decoded_andMatrixOutputs_lo_lo_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_28, decoder_decoded_andMatrixOutputs_andMatrixInput_7_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, decoder_decoded_andMatrixOutputs_andMatrixInput_5_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_28 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_23, decoder_decoded_andMatrixOutputs_hi_lo_lo_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, decoder_decoded_andMatrixOutputs_andMatrixInput_3_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, decoder_decoded_andMatrixOutputs_andMatrixInput_1_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_29 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_26, decoder_decoded_andMatrixOutputs_hi_hi_lo_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_29 = cat(decoder_decoded_andMatrixOutputs_hi_hi_29, decoder_decoded_andMatrixOutputs_hi_lo_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_29 = cat(decoder_decoded_andMatrixOutputs_hi_29, decoder_decoded_andMatrixOutputs_lo_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_25_2 = andr(_decoder_decoded_andMatrixOutputs_T_29) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = bits(decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = bits(decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = bits(decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = bits(decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_16, decoder_decoded_andMatrixOutputs_andMatrixInput_15_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, decoder_decoded_andMatrixOutputs_andMatrixInput_13_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_28 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_23, decoder_decoded_andMatrixOutputs_lo_lo_lo_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, decoder_decoded_andMatrixOutputs_andMatrixInput_11_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_27, decoder_decoded_andMatrixOutputs_andMatrixInput_9_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_29 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_25, decoder_decoded_andMatrixOutputs_lo_hi_lo_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_30 = cat(decoder_decoded_andMatrixOutputs_lo_hi_29, decoder_decoded_andMatrixOutputs_lo_lo_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_29, decoder_decoded_andMatrixOutputs_andMatrixInput_7_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, decoder_decoded_andMatrixOutputs_andMatrixInput_5_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_29 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_24, decoder_decoded_andMatrixOutputs_hi_lo_lo_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, decoder_decoded_andMatrixOutputs_andMatrixInput_3_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, decoder_decoded_andMatrixOutputs_andMatrixInput_1_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_30 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_27, decoder_decoded_andMatrixOutputs_hi_hi_lo_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_30 = cat(decoder_decoded_andMatrixOutputs_hi_hi_30, decoder_decoded_andMatrixOutputs_hi_lo_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_30 = cat(decoder_decoded_andMatrixOutputs_hi_30, decoder_decoded_andMatrixOutputs_lo_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_30_2 = andr(_decoder_decoded_andMatrixOutputs_T_30) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = bits(decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = bits(decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = bits(decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = bits(decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_9, decoder_decoded_andMatrixOutputs_andMatrixInput_16_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_20, decoder_decoded_andMatrixOutputs_andMatrixInput_14_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_29 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_24, decoder_decoded_andMatrixOutputs_lo_lo_lo_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_24, decoder_decoded_andMatrixOutputs_andMatrixInput_12_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_26, decoder_decoded_andMatrixOutputs_andMatrixInput_10_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_30 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_26, decoder_decoded_andMatrixOutputs_lo_hi_lo_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_31 = cat(decoder_decoded_andMatrixOutputs_lo_hi_30, decoder_decoded_andMatrixOutputs_lo_lo_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_29, decoder_decoded_andMatrixOutputs_andMatrixInput_8_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_30, decoder_decoded_andMatrixOutputs_andMatrixInput_6_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_30 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_25, decoder_decoded_andMatrixOutputs_hi_lo_lo_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_31, decoder_decoded_andMatrixOutputs_andMatrixInput_4_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, decoder_decoded_andMatrixOutputs_andMatrixInput_1_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_2_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_31 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_28, decoder_decoded_andMatrixOutputs_hi_hi_lo_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_31 = cat(decoder_decoded_andMatrixOutputs_hi_hi_31, decoder_decoded_andMatrixOutputs_hi_lo_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_31 = cat(decoder_decoded_andMatrixOutputs_hi_31, decoder_decoded_andMatrixOutputs_lo_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_26_2 = andr(_decoder_decoded_andMatrixOutputs_T_31) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = bits(decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = bits(decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = bits(decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = bits(decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_19 = bits(decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_3, decoder_decoded_andMatrixOutputs_andMatrixInput_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_10, decoder_decoded_andMatrixOutputs_andMatrixInput_16_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_17_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_30 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_25, decoder_decoded_andMatrixOutputs_lo_lo_lo_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_21, decoder_decoded_andMatrixOutputs_andMatrixInput_14_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_26, decoder_decoded_andMatrixOutputs_andMatrixInput_11_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_12_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_31 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_27, decoder_decoded_andMatrixOutputs_lo_hi_lo_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_32 = cat(decoder_decoded_andMatrixOutputs_lo_hi_31, decoder_decoded_andMatrixOutputs_lo_lo_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, decoder_decoded_andMatrixOutputs_andMatrixInput_9_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_31, decoder_decoded_andMatrixOutputs_andMatrixInput_6_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_7_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_31 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_26, decoder_decoded_andMatrixOutputs_hi_lo_lo_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, decoder_decoded_andMatrixOutputs_andMatrixInput_4_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, decoder_decoded_andMatrixOutputs_andMatrixInput_1_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_2_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_32 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_29, decoder_decoded_andMatrixOutputs_hi_hi_lo_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_32 = cat(decoder_decoded_andMatrixOutputs_hi_hi_32, decoder_decoded_andMatrixOutputs_hi_lo_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_32 = cat(decoder_decoded_andMatrixOutputs_hi_32, decoder_decoded_andMatrixOutputs_lo_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_2_2 = andr(_decoder_decoded_andMatrixOutputs_T_32) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = bits(decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = bits(decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = bits(decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = bits(decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = bits(decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_20 = bits(decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_1, decoder_decoded_andMatrixOutputs_andMatrixInput_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, decoder_decoded_andMatrixOutputs_andMatrixInput_17_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_18_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_31 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_26, decoder_decoded_andMatrixOutputs_lo_lo_lo_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_19, decoder_decoded_andMatrixOutputs_andMatrixInput_15_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_26, decoder_decoded_andMatrixOutputs_andMatrixInput_12_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_13_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_32 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_28, decoder_decoded_andMatrixOutputs_lo_hi_lo_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_33 = cat(decoder_decoded_andMatrixOutputs_lo_hi_32, decoder_decoded_andMatrixOutputs_lo_lo_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_28, decoder_decoded_andMatrixOutputs_andMatrixInput_10_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, decoder_decoded_andMatrixOutputs_andMatrixInput_7_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_8_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_32 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_27, decoder_decoded_andMatrixOutputs_hi_lo_lo_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, decoder_decoded_andMatrixOutputs_andMatrixInput_4_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_5_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, decoder_decoded_andMatrixOutputs_andMatrixInput_1_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_2_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_33 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_30, decoder_decoded_andMatrixOutputs_hi_hi_lo_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_33 = cat(decoder_decoded_andMatrixOutputs_hi_hi_33, decoder_decoded_andMatrixOutputs_hi_lo_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_33 = cat(decoder_decoded_andMatrixOutputs_hi_33, decoder_decoded_andMatrixOutputs_lo_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_34_2 = andr(_decoder_decoded_andMatrixOutputs_T_33) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = bits(decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = bits(decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = bits(decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = bits(decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = bits(decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = bits(decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = bits(decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_2, decoder_decoded_andMatrixOutputs_andMatrixInput_20_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, decoder_decoded_andMatrixOutputs_andMatrixInput_17_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_18_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_32 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_27, decoder_decoded_andMatrixOutputs_lo_lo_lo_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_20, decoder_decoded_andMatrixOutputs_andMatrixInput_15_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_27, decoder_decoded_andMatrixOutputs_andMatrixInput_12_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_13_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_33 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_29, decoder_decoded_andMatrixOutputs_lo_hi_lo_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_34 = cat(decoder_decoded_andMatrixOutputs_lo_hi_33, decoder_decoded_andMatrixOutputs_lo_lo_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_29, decoder_decoded_andMatrixOutputs_andMatrixInput_10_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, decoder_decoded_andMatrixOutputs_andMatrixInput_7_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_8_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_33 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_28, decoder_decoded_andMatrixOutputs_hi_lo_lo_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_34, decoder_decoded_andMatrixOutputs_andMatrixInput_4_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, decoder_decoded_andMatrixOutputs_andMatrixInput_1_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_2_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_34 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_31, decoder_decoded_andMatrixOutputs_hi_hi_lo_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_34 = cat(decoder_decoded_andMatrixOutputs_hi_hi_34, decoder_decoded_andMatrixOutputs_hi_lo_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_34 = cat(decoder_decoded_andMatrixOutputs_hi_34, decoder_decoded_andMatrixOutputs_lo_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_17_2 = andr(_decoder_decoded_andMatrixOutputs_T_34) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = bits(decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = bits(decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = bits(decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = bits(decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = bits(decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = bits(decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = bits(decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_3, decoder_decoded_andMatrixOutputs_andMatrixInput_20_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_10, decoder_decoded_andMatrixOutputs_andMatrixInput_17_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_18_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_33 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_28, decoder_decoded_andMatrixOutputs_lo_lo_lo_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_21, decoder_decoded_andMatrixOutputs_andMatrixInput_15_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_28, decoder_decoded_andMatrixOutputs_andMatrixInput_12_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_13_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_34 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_30, decoder_decoded_andMatrixOutputs_lo_hi_lo_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_35 = cat(decoder_decoded_andMatrixOutputs_lo_hi_34, decoder_decoded_andMatrixOutputs_lo_lo_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_30, decoder_decoded_andMatrixOutputs_andMatrixInput_10_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, decoder_decoded_andMatrixOutputs_andMatrixInput_7_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_8_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_34 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_29, decoder_decoded_andMatrixOutputs_hi_lo_lo_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_35, decoder_decoded_andMatrixOutputs_andMatrixInput_4_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, decoder_decoded_andMatrixOutputs_andMatrixInput_1_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_2_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_35 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_32, decoder_decoded_andMatrixOutputs_hi_hi_lo_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_35 = cat(decoder_decoded_andMatrixOutputs_hi_hi_35, decoder_decoded_andMatrixOutputs_hi_lo_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_35 = cat(decoder_decoded_andMatrixOutputs_hi_35, decoder_decoded_andMatrixOutputs_lo_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_13_2 = andr(_decoder_decoded_andMatrixOutputs_T_35) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = bits(decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = bits(decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = bits(decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = bits(decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = bits(decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = bits(decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = bits(decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = bits(decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = bits(decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_4, decoder_decoded_andMatrixOutputs_andMatrixInput_20_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, decoder_decoded_andMatrixOutputs_andMatrixInput_17_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_18_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_lo_34 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_29, decoder_decoded_andMatrixOutputs_lo_lo_lo_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_22, decoder_decoded_andMatrixOutputs_andMatrixInput_15_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_29, decoder_decoded_andMatrixOutputs_andMatrixInput_12_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_13_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_hi_35 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_31, decoder_decoded_andMatrixOutputs_lo_hi_lo_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_lo_36 = cat(decoder_decoded_andMatrixOutputs_lo_hi_35, decoder_decoded_andMatrixOutputs_lo_lo_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_31, decoder_decoded_andMatrixOutputs_andMatrixInput_10_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_35, decoder_decoded_andMatrixOutputs_andMatrixInput_7_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_8_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_lo_35 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_30, decoder_decoded_andMatrixOutputs_hi_lo_lo_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_36, decoder_decoded_andMatrixOutputs_andMatrixInput_4_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, decoder_decoded_andMatrixOutputs_andMatrixInput_1_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_2_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_hi_36 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_33, decoder_decoded_andMatrixOutputs_hi_hi_lo_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_hi_36 = cat(decoder_decoded_andMatrixOutputs_hi_hi_36, decoder_decoded_andMatrixOutputs_hi_lo_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoder_decoded_andMatrixOutputs_T_36 = cat(decoder_decoded_andMatrixOutputs_hi_36, decoder_decoded_andMatrixOutputs_lo_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoder_decoded_andMatrixOutputs_15_2 = andr(_decoder_decoded_andMatrixOutputs_T_36) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoder_decoded_orMatrixOutputs_lo_lo = cat(decoder_decoded_andMatrixOutputs_29_2, decoder_decoded_andMatrixOutputs_23_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_lo_hi = cat(decoder_decoded_andMatrixOutputs_28_2, decoder_decoded_andMatrixOutputs_32_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_lo = cat(decoder_decoded_orMatrixOutputs_lo_hi, decoder_decoded_orMatrixOutputs_lo_lo) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_lo = cat(decoder_decoded_andMatrixOutputs_7_2, decoder_decoded_andMatrixOutputs_5_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_0_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_hi = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi, decoder_decoded_andMatrixOutputs_31_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi = cat(decoder_decoded_orMatrixOutputs_hi_hi, decoder_decoded_orMatrixOutputs_hi_lo) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T = cat(decoder_decoded_orMatrixOutputs_hi, decoder_decoded_orMatrixOutputs_lo) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T_1 = orr(_decoder_decoded_orMatrixOutputs_T) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoder_decoded_orMatrixOutputs_T_2 = orr(decoder_decoded_andMatrixOutputs_28_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoder_decoded_orMatrixOutputs_T_3 = orr(decoder_decoded_andMatrixOutputs_3_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node decoder_decoded_orMatrixOutputs_hi_1 = cat(decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_33_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T_4 = cat(decoder_decoded_orMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_36_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T_5 = orr(_decoder_decoded_orMatrixOutputs_T_4) @[src/main/scala/chisel3/util/pla.scala 114:36] node decoder_decoded_orMatrixOutputs_lo_1 = cat(decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_12_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_2 = cat(decoder_decoded_andMatrixOutputs_22_2, decoder_decoded_andMatrixOutputs_14_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T_6 = cat(decoder_decoded_orMatrixOutputs_hi_2, decoder_decoded_orMatrixOutputs_lo_1) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T_7 = orr(_decoder_decoded_orMatrixOutputs_T_6) @[src/main/scala/chisel3/util/pla.scala 114:36] node decoder_decoded_orMatrixOutputs_lo_2 = cat(decoder_decoded_andMatrixOutputs_4_2, decoder_decoded_andMatrixOutputs_2_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_24_2, decoder_decoded_andMatrixOutputs_32_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_3 = cat(decoder_decoded_orMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_29_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T_8 = cat(decoder_decoded_orMatrixOutputs_hi_3, decoder_decoded_orMatrixOutputs_lo_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T_9 = orr(_decoder_decoded_orMatrixOutputs_T_8) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoder_decoded_orMatrixOutputs_T_10 = cat(decoder_decoded_andMatrixOutputs_30_2, decoder_decoded_andMatrixOutputs_15_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T_11 = orr(_decoder_decoded_orMatrixOutputs_T_10) @[src/main/scala/chisel3/util/pla.scala 114:36] node decoder_decoded_orMatrixOutputs_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_13_2, decoder_decoded_andMatrixOutputs_15_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_lo_hi_hi = cat(decoder_decoded_andMatrixOutputs_12_2, decoder_decoded_andMatrixOutputs_6_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_lo_hi_1 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi, decoder_decoded_andMatrixOutputs_26_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_lo_3 = cat(decoder_decoded_orMatrixOutputs_lo_hi_1, decoder_decoded_orMatrixOutputs_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_lo_hi = cat(decoder_decoded_andMatrixOutputs_19_2, decoder_decoded_andMatrixOutputs_10_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_lo_1 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi, decoder_decoded_andMatrixOutputs_21_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_11_2, decoder_decoded_andMatrixOutputs_16_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_hi_2 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_20_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_4 = cat(decoder_decoded_orMatrixOutputs_hi_hi_2, decoder_decoded_orMatrixOutputs_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T_12 = cat(decoder_decoded_orMatrixOutputs_hi_4, decoder_decoded_orMatrixOutputs_lo_3) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T_13 = orr(_decoder_decoded_orMatrixOutputs_T_12) @[src/main/scala/chisel3/util/pla.scala 114:36] node decoder_decoded_orMatrixOutputs_lo_lo_hi = cat(decoder_decoded_andMatrixOutputs_34_2, decoder_decoded_andMatrixOutputs_17_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_lo_lo_2 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi, decoder_decoded_andMatrixOutputs_13_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_6_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_lo_hi_2 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_25_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_lo_4 = cat(decoder_decoded_orMatrixOutputs_lo_hi_2, decoder_decoded_orMatrixOutputs_lo_lo_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_19_2, decoder_decoded_andMatrixOutputs_10_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_lo_2 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_21_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_24_2, decoder_decoded_andMatrixOutputs_16_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_hi_3 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_20_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_5 = cat(decoder_decoded_orMatrixOutputs_hi_hi_3, decoder_decoded_orMatrixOutputs_hi_lo_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T_14 = cat(decoder_decoded_orMatrixOutputs_hi_5, decoder_decoded_orMatrixOutputs_lo_4) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T_15 = orr(_decoder_decoded_orMatrixOutputs_T_14) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoder_decoded_orMatrixOutputs_T_16 = orr(decoder_decoded_andMatrixOutputs_36_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoder_decoded_orMatrixOutputs_T_17 = orr(decoder_decoded_andMatrixOutputs_24_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoder_decoded_orMatrixOutputs_T_18 = orr(decoder_decoded_andMatrixOutputs_35_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node decoder_decoded_orMatrixOutputs_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_9_2, decoder_decoded_andMatrixOutputs_27_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_lo_5 = cat(decoder_decoded_orMatrixOutputs_lo_hi_3, decoder_decoded_andMatrixOutputs_22_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_0_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_6 = cat(decoder_decoded_orMatrixOutputs_hi_hi_4, decoder_decoded_andMatrixOutputs_24_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T_19 = cat(decoder_decoded_orMatrixOutputs_hi_6, decoder_decoded_orMatrixOutputs_lo_5) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T_20 = orr(_decoder_decoded_orMatrixOutputs_T_19) @[src/main/scala/chisel3/util/pla.scala 114:36] node decoder_decoded_orMatrixOutputs_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_4_2, decoder_decoded_andMatrixOutputs_2_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_7_2, decoder_decoded_andMatrixOutputs_5_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_lo_hi_4 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_28_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_lo_6 = cat(decoder_decoded_orMatrixOutputs_lo_hi_4, decoder_decoded_orMatrixOutputs_lo_lo_3) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_27_2, decoder_decoded_andMatrixOutputs_22_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_0_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_hi_5 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_9_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_7 = cat(decoder_decoded_orMatrixOutputs_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_lo_3) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T_21 = cat(decoder_decoded_orMatrixOutputs_hi_7, decoder_decoded_orMatrixOutputs_lo_6) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T_22 = orr(_decoder_decoded_orMatrixOutputs_T_21) @[src/main/scala/chisel3/util/pla.scala 114:36] node decoder_decoded_orMatrixOutputs_lo_lo_4 = cat(decoder_decoded_andMatrixOutputs_30_2, decoder_decoded_andMatrixOutputs_15_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_12_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_lo_hi_5 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_28_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_lo_7 = cat(decoder_decoded_orMatrixOutputs_lo_hi_5, decoder_decoded_orMatrixOutputs_lo_lo_4) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_lo_4 = cat(decoder_decoded_andMatrixOutputs_22_2, decoder_decoded_andMatrixOutputs_14_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_0_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_hi_6 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_18_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node decoder_decoded_orMatrixOutputs_hi_8 = cat(decoder_decoded_orMatrixOutputs_hi_hi_6, decoder_decoded_orMatrixOutputs_hi_lo_4) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T_23 = cat(decoder_decoded_orMatrixOutputs_hi_8, decoder_decoded_orMatrixOutputs_lo_7) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoder_decoded_orMatrixOutputs_T_24 = orr(_decoder_decoded_orMatrixOutputs_T_23) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoder_decoded_orMatrixOutputs_T_25 = orr(decoder_decoded_andMatrixOutputs_8_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node decoder_decoded_orMatrixOutputs_lo_lo_lo = cat(_decoder_decoded_orMatrixOutputs_T_1, UInt<1>(0h0)) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = cat(_decoder_decoded_orMatrixOutputs_T_3, _decoder_decoded_orMatrixOutputs_T_2) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoder_decoded_orMatrixOutputs_lo_lo_5 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_1, decoder_decoded_orMatrixOutputs_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoder_decoded_orMatrixOutputs_lo_hi_lo = cat(_decoder_decoded_orMatrixOutputs_T_7, _decoder_decoded_orMatrixOutputs_T_5) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(_decoder_decoded_orMatrixOutputs_T_13, _decoder_decoded_orMatrixOutputs_T_11) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, _decoder_decoded_orMatrixOutputs_T_9) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoder_decoded_orMatrixOutputs_lo_hi_6 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_4, decoder_decoded_orMatrixOutputs_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoder_decoded_orMatrixOutputs_lo_8 = cat(decoder_decoded_orMatrixOutputs_lo_hi_6, decoder_decoded_orMatrixOutputs_lo_lo_5) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoder_decoded_orMatrixOutputs_hi_lo_lo = cat(_decoder_decoded_orMatrixOutputs_T_15, UInt<1>(0h0)) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(_decoder_decoded_orMatrixOutputs_T_17, _decoder_decoded_orMatrixOutputs_T_16) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, UInt<1>(0h0)) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoder_decoded_orMatrixOutputs_hi_lo_5 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_2, decoder_decoded_orMatrixOutputs_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoder_decoded_orMatrixOutputs_hi_hi_lo = cat(_decoder_decoded_orMatrixOutputs_T_20, _decoder_decoded_orMatrixOutputs_T_18) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(_decoder_decoded_orMatrixOutputs_T_25, _decoder_decoded_orMatrixOutputs_T_24) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, _decoder_decoded_orMatrixOutputs_T_22) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoder_decoded_orMatrixOutputs_hi_hi_7 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoder_decoded_orMatrixOutputs_hi_9 = cat(decoder_decoded_orMatrixOutputs_hi_hi_7, decoder_decoded_orMatrixOutputs_hi_lo_5) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoder_decoded_orMatrixOutputs = cat(decoder_decoded_orMatrixOutputs_hi_9, decoder_decoded_orMatrixOutputs_lo_8) @[src/main/scala/chisel3/util/pla.scala 102:36] node _decoder_decoded_invMatrixOutputs_T = bits(decoder_decoded_orMatrixOutputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoder_decoded_invMatrixOutputs_T_1 = bits(decoder_decoded_orMatrixOutputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoder_decoded_invMatrixOutputs_T_2 = bits(decoder_decoded_orMatrixOutputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoder_decoded_invMatrixOutputs_T_3 = bits(decoder_decoded_orMatrixOutputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoder_decoded_invMatrixOutputs_T_4 = bits(decoder_decoded_orMatrixOutputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoder_decoded_invMatrixOutputs_T_5 = bits(decoder_decoded_orMatrixOutputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoder_decoded_invMatrixOutputs_T_6 = bits(decoder_decoded_orMatrixOutputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoder_decoded_invMatrixOutputs_T_7 = bits(decoder_decoded_orMatrixOutputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoder_decoded_invMatrixOutputs_T_8 = bits(decoder_decoded_orMatrixOutputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoder_decoded_invMatrixOutputs_T_9 = bits(decoder_decoded_orMatrixOutputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoder_decoded_invMatrixOutputs_T_10 = bits(decoder_decoded_orMatrixOutputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoder_decoded_invMatrixOutputs_T_11 = bits(decoder_decoded_orMatrixOutputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoder_decoded_invMatrixOutputs_T_12 = bits(decoder_decoded_orMatrixOutputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoder_decoded_invMatrixOutputs_T_13 = bits(decoder_decoded_orMatrixOutputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoder_decoded_invMatrixOutputs_T_14 = bits(decoder_decoded_orMatrixOutputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoder_decoded_invMatrixOutputs_T_15 = bits(decoder_decoded_orMatrixOutputs, 15, 15) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoder_decoded_invMatrixOutputs_T_16 = bits(decoder_decoded_orMatrixOutputs, 16, 16) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoder_decoded_invMatrixOutputs_T_17 = bits(decoder_decoded_orMatrixOutputs, 17, 17) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoder_decoded_invMatrixOutputs_T_18 = bits(decoder_decoded_orMatrixOutputs, 18, 18) @[src/main/scala/chisel3/util/pla.scala 124:31] node decoder_decoded_invMatrixOutputs_lo_lo_lo = cat(_decoder_decoded_invMatrixOutputs_T_1, _decoder_decoded_invMatrixOutputs_T) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoder_decoded_invMatrixOutputs_lo_lo_hi = cat(_decoder_decoded_invMatrixOutputs_T_3, _decoder_decoded_invMatrixOutputs_T_2) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoder_decoded_invMatrixOutputs_lo_lo = cat(decoder_decoded_invMatrixOutputs_lo_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoder_decoded_invMatrixOutputs_lo_hi_lo = cat(_decoder_decoded_invMatrixOutputs_T_5, _decoder_decoded_invMatrixOutputs_T_4) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(_decoder_decoded_invMatrixOutputs_T_8, _decoder_decoded_invMatrixOutputs_T_7) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoder_decoded_invMatrixOutputs_lo_hi_hi = cat(decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _decoder_decoded_invMatrixOutputs_T_6) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoder_decoded_invMatrixOutputs_lo_hi = cat(decoder_decoded_invMatrixOutputs_lo_hi_hi, decoder_decoded_invMatrixOutputs_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoder_decoded_invMatrixOutputs_lo = cat(decoder_decoded_invMatrixOutputs_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoder_decoded_invMatrixOutputs_hi_lo_lo = cat(_decoder_decoded_invMatrixOutputs_T_10, _decoder_decoded_invMatrixOutputs_T_9) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(_decoder_decoded_invMatrixOutputs_T_13, _decoder_decoded_invMatrixOutputs_T_12) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoder_decoded_invMatrixOutputs_hi_lo_hi = cat(decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _decoder_decoded_invMatrixOutputs_T_11) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoder_decoded_invMatrixOutputs_hi_lo = cat(decoder_decoded_invMatrixOutputs_hi_lo_hi, decoder_decoded_invMatrixOutputs_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoder_decoded_invMatrixOutputs_hi_hi_lo = cat(_decoder_decoded_invMatrixOutputs_T_15, _decoder_decoded_invMatrixOutputs_T_14) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(_decoder_decoded_invMatrixOutputs_T_18, _decoder_decoded_invMatrixOutputs_T_17) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoder_decoded_invMatrixOutputs_hi_hi_hi = cat(decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, _decoder_decoded_invMatrixOutputs_T_16) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoder_decoded_invMatrixOutputs_hi_hi = cat(decoder_decoded_invMatrixOutputs_hi_hi_hi, decoder_decoded_invMatrixOutputs_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoder_decoded_invMatrixOutputs_hi = cat(decoder_decoded_invMatrixOutputs_hi_hi, decoder_decoded_invMatrixOutputs_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoder_decoded_invMatrixOutputs = cat(decoder_decoded_invMatrixOutputs_hi, decoder_decoded_invMatrixOutputs_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] connect decoder_decoded, decoder_decoded_invMatrixOutputs @[src/main/scala/chisel3/util/pla.scala 129:13] connect decoder_decoded_plaInput, io.inst @[src/main/scala/chisel3/util/experimental/decode/decoder.scala 35:16] node decoder_0 = bits(decoder_decoded, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoder_1 = bits(decoder_decoded, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoder_2 = bits(decoder_decoded, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoder_3 = bits(decoder_decoded, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoder_4 = bits(decoder_decoded, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoder_5 = bits(decoder_decoded, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoder_6 = bits(decoder_decoded, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoder_7 = bits(decoder_decoded, 11, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoder_8 = bits(decoder_decoded, 9, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoder_9 = bits(decoder_decoded, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoder_10 = bits(decoder_decoded, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoder_11 = bits(decoder_decoded, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoder_12 = bits(decoder_decoded, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoder_13 = bits(decoder_decoded, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoder_14 = bits(decoder_decoded, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoder_15 = bits(decoder_decoded, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoder_16 = bits(decoder_decoded, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] connect io.sigs.ldst, decoder_0 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 179:40] connect io.sigs.wen, decoder_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 179:40] connect io.sigs.ren1, decoder_2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 179:40] connect io.sigs.ren2, decoder_3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 179:40] connect io.sigs.ren3, decoder_4 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 179:40] connect io.sigs.swap12, decoder_5 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 179:40] connect io.sigs.swap23, decoder_6 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 179:40] connect io.sigs.typeTagIn, decoder_7 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 179:40] connect io.sigs.typeTagOut, decoder_8 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 179:40] connect io.sigs.fromint, decoder_9 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 179:40] connect io.sigs.toint, decoder_10 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 179:40] connect io.sigs.fastpipe, decoder_11 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 179:40] connect io.sigs.fma, decoder_12 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 179:40] connect io.sigs.div, decoder_13 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 179:40] connect io.sigs.sqrt, decoder_14 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 179:40] connect io.sigs.wflags, decoder_15 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 179:40] connect io.sigs.vec, decoder_16 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 179:40] module MulAddRecFNToRaw_preMul : @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 71:7] output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 73:16] node rawA_exp = bits(io.a, 31, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _rawA_isZero_T = bits(rawA_exp, 8, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect rawA.isNaN, _rawA_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect rawA.isInf, _rawA_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect rawA.isZero, rawA_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _rawA_out_sign_T = bits(io.a, 32, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect rawA.sign, _rawA_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _rawA_out_sExp_T = cvt(rawA_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect rawA.sExp, _rawA_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _rawA_out_sig_T_2 = bits(io.a, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect rawA.sig, _rawA_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node rawB_exp = bits(io.b, 31, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _rawB_isZero_T = bits(rawB_exp, 8, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect rawB.isNaN, _rawB_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect rawB.isInf, _rawB_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect rawB.isZero, rawB_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _rawB_out_sign_T = bits(io.b, 32, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect rawB.sign, _rawB_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _rawB_out_sExp_T = cvt(rawB_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect rawB.sExp, _rawB_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _rawB_out_sig_T_2 = bits(io.b, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect rawB.sig, _rawB_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node rawC_exp = bits(io.c, 31, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _rawC_isZero_T = bits(rawC_exp, 8, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect rawC.isNaN, _rawC_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect rawC.isInf, _rawC_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect rawC.isZero, rawC_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _rawC_out_sign_T = bits(io.c, 32, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect rawC.sign, _rawC_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _rawC_out_sExp_T = cvt(rawC_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect rawC.sExp, _rawC_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _rawC_out_sig_T_2 = bits(io.c, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect rawC.sig, _rawC_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node _signProd_T = xor(rawA.sign, rawB.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 96:30] node _signProd_T_1 = bits(io.op, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 96:49] node signProd = xor(_signProd_T, _signProd_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 96:42] node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 99:19] node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 99:32] node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 99:32] node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 99:32] node _doSubMags_T = xor(signProd, rawC.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 101:30] node _doSubMags_T_1 = bits(io.op, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 101:49] node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 101:42] node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 105:42] node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 105:42] node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 105:42] node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 106:42] node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 107:35] node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 107:69] node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 107:50] node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 109:9] node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 109:60] node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 109:39] node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 109:23] node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 113:34] node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 114:33] node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 113:16] node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 111:12] node _mainAlignedSigC_T = not(rawC.sig) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 119:25] node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 119:13] node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 119:53] node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 119:46] node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 119:94] node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 119:100] node _reduced4CExtra_T = shl(rawC.sig, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 121:30] wire reduced4CExtra_reducedVec : UInt<1>[7] @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 118:30] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 123:15] node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 123:57] connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 122:38] node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node _reduced4CExtra_T_2 = shr(CAlignDist, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 123:28] node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 76:56] node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 78:22] node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 121:68] node reduced4CExtra = orr(_reduced4CExtra_T_19) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 129:11] node _alignedSigC_T = shr(mainAlignedSigC, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 131:28] node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 133:32] node _alignedSigC_T_2 = andr(_alignedSigC_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 133:39] node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 133:47] node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 133:44] node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 134:32] node _alignedSigC_T_6 = orr(_alignedSigC_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 134:39] node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 134:44] node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 132:16] node alignedSigC_hi = asUInt(_alignedSigC_T) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 131:12] node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 131:12] connect io.mulAddA, rawA.sig @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 140:16] connect io.mulAddB, rawB.sig @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 141:16] node _io_mulAddC_T = bits(alignedSigC, 48, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 142:30] connect io.mulAddC, _io_mulAddC_T @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 142:16] node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:56] node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:49] node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:46] node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:56] node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:49] node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:46] node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 145:32] node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:56] node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:49] node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:46] node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 145:58] connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 144:30] node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 147:42] connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 147:28] connect io.toPostMul.isInfA, rawA.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 148:28] connect io.toPostMul.isZeroA, rawA.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 149:28] connect io.toPostMul.isInfB, rawB.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 150:28] connect io.toPostMul.isZeroB, rawB.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 151:28] connect io.toPostMul.signProd, signProd @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 152:28] connect io.toPostMul.isNaNC, rawC.isNaN @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 153:28] connect io.toPostMul.isInfC, rawC.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 154:28] connect io.toPostMul.isZeroC, rawC.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 155:28] node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 157:53] node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 157:53] node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 157:53] node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 157:12] connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 156:28] connect io.toPostMul.doSubMags, doSubMags @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 158:28] connect io.toPostMul.CIsDominant, CIsDominant @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 159:30] node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 160:47] connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 160:34] node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 162:20] connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 161:34] node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 163:48] connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 163:34] module MulAddRecFNToRaw_postMul : @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 168:7] output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 170:16] node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 184:45] node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 188:42] node _sigSum_T = bits(io.mulAddResult, 48, 48) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 190:32] node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 191:47] node _sigSum_T_2 = tail(_sigSum_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 191:47] node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 190:16] node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 194:28] node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 190:12] node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 190:12] node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 201:69] node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 201:43] node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 201:43] node CDom_sExp = asSInt(_CDom_sExp_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 201:43] node _CDom_absSigSum_T = bits(sigSum, 74, 25) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 204:20] node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 204:13] node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 207:46] node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 205:22] node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 208:23] node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 207:71] node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 203:12] node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 213:21] node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 213:14] node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 213:36] node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 214:19] node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 214:37] node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 212:12] node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 217:24] node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 217:56] node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 220:36] node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 220:53] wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 118:30] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 123:15] node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 123:57] connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 122:38] node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 221:51] node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 52:21] node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 76:56] node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 78:22] node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 220:72] node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 221:73] node _CDom_sig_T = shr(CDom_mainSig, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 223:25] node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 224:25] node _CDom_sig_T_2 = orr(_CDom_sig_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 224:32] node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 224:36] node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 224:61] node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 223:12] node notCDom_signSigSum = bits(sigSum, 51, 51) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 230:36] node _notCDom_absSigSum_T = bits(sigSum, 50, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 233:20] node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 233:13] node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 234:19] node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 234:41] node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 234:41] node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 232:12] wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 101:30] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 106:15] node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 106:57] connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 105:38] node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) @[src/main/scala/chisel3/util/Mux.scala 50:70] node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) @[src/main/scala/chisel3/util/Mux.scala 50:70] node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 238:56] node _notCDom_sExp_T = cvt(notCDom_nearNormDist) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 239:76] node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 239:46] node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 239:46] node notCDom_sExp = asSInt(_notCDom_sExp_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 239:46] node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 241:27] node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 241:50] node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 245:39] node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 245:55] wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 101:30] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 106:15] node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 106:57] connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 105:38] node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 246:46] node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 52:21] node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 76:56] node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 78:22] node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 245:78] node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 247:11] node _notCDom_sig_T = shr(notCDom_mainSig, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 249:28] node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 250:28] node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 250:35] node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 250:39] node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 249:12] node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 253:21] node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 253:50] node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 257:36] node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 255:12] node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 262:49] node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 263:44] node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 265:32] node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 265:58] node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 270:31] node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 269:35] node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 271:32] node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 270:57] node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 272:10] node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 273:36] node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 272:36] node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 273:61] node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 274:35] node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 271:57] connect io.invalidExc, _io_invalidExc_T_9 @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 268:19] node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 276:48] connect io.rawOut.isNaN, _io_rawOut_isNaN_T @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 276:21] connect io.rawOut.isInf, notNaN_isInfOut @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 277:21] node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 281:14] node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 281:42] node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 280:25] connect io.rawOut.isZero, _io_rawOut_isZero_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 279:22] node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 283:27] node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 284:31] node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 283:54] node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 285:29] node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 285:26] node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 285:48] node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 286:36] node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 284:43] node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 287:26] node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 288:37] node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 287:46] node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 286:48] node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 289:10] node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 289:31] node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 289:28] node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 290:17] node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 289:49] node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 288:50] connect io.rawOut.sign, _io_rawOut_sign_T_17 @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 282:20] node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 291:26] connect io.rawOut.sExp, _io_rawOut_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 291:20] node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 292:25] connect io.rawOut.sig, _io_rawOut_sig_T @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 292:19] module RoundAnyRawFNToRecFN : @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 48:5] output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 57:16] node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 89:53] node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 90:53] node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 91:53] node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 92:53] node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 93:53] node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 94:53] node _roundMagUp_T = and(roundingMode_min, io.in.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:27] node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:66] node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:63] node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:42] node adjustedSig = shl(io.in.sig, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 113:22] node doShiftSigDown1 = bits(adjustedSig, 26, 26) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 119:57] wire common_expOut : UInt<9> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 121:31] wire common_fractOut : UInt<23> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 122:31] wire common_overflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 123:37] wire common_totalUnderflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 124:37] wire common_underflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 125:37] wire common_inexact : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 126:37] node _roundMask_T = bits(io.in.sExp, 8, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 155:37] node _roundMask_T_1 = not(_roundMask_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 52:21] node roundMask_msb = bits(_roundMask_T_1, 8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 76:56] node _roundMask_T_2 = bits(roundMask_shift, 63, 42) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 78:22] node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_4 = shl(UInt<8>(0hff), 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_6 = shr(_roundMask_T_3, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_9 = shl(_roundMask_T_8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_10 = not(_roundMask_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_14 = shl(_roundMask_T_13, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_16 = shr(_roundMask_T_12, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_19 = shl(_roundMask_T_18, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_20 = not(_roundMask_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_24 = shl(_roundMask_T_23, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_26 = shr(_roundMask_T_22, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_29 = shl(_roundMask_T_28, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_30 = not(_roundMask_T_25) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_34 = shl(_roundMask_T_33, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_36 = shr(_roundMask_T_32, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_39 = shl(_roundMask_T_38, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_40 = not(_roundMask_T_35) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_60 = not(_roundMask_T_59) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:32] node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:21] node _roundMask_T_62 = not(_roundMask_T_61) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:17] node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 68:58] node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 76:56] node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 78:22] node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 62:24] node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 67:24] node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 62:24] node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 158:23] node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 158:42] node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 161:41] node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 161:53] node _roundPosMask_T = not(shiftedRoundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 162:28] node roundPosMask = and(_roundPosMask_T, roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 162:46] node _roundPosBit_T = and(adjustedSig, roundPosMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 163:40] node roundPosBit = orr(_roundPosBit_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 163:56] node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 164:42] node anyRoundExtra = orr(_anyRoundExtra_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 164:62] node anyRound = or(roundPosBit, anyRoundExtra) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 165:36] node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 168:38] node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 168:67] node _roundIncr_T_2 = and(roundMagUp, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 170:29] node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 169:31] node _roundedSig_T = or(adjustedSig, roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:32] node _roundedSig_T_1 = shr(_roundedSig_T, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:44] node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:49] node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:49] node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 175:30] node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:64] node _roundedSig_T_6 = shr(roundMask, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 176:35] node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:25] node _roundedSig_T_8 = not(_roundedSig_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:21] node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:57] node _roundedSig_T_10 = not(roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:32] node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:30] node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:43] node _roundedSig_T_13 = and(roundingMode_odd, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:42] node _roundedSig_T_14 = shr(roundPosMask, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:67] node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:24] node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:47] node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 172:16] node _sRoundedExp_T = shr(roundedSig, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:54] node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:76] node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:40] node _common_expOut_T = bits(sRoundedExp, 8, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 186:37] connect common_expOut, _common_expOut_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 186:23] node _common_fractOut_T = bits(roundedSig, 23, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 189:27] node _common_fractOut_T_1 = bits(roundedSig, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 190:27] node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 188:16] connect common_fractOut, _common_fractOut_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 187:25] node _common_overflow_T = shr(sRoundedExp, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 195:30] node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 195:50] connect common_overflow, _common_overflow_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 192:25] node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 199:31] connect common_totalUnderflow, _common_totalUnderflow_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 196:31] node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:45] node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:61] node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:16] node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:44] node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:30] node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:63] node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:70] node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:49] node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 206:38] node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 206:67] node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 208:29] node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 207:46] node _roundCarry_T = bits(roundedSig, 25, 25) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 211:27] node _roundCarry_T_1 = bits(roundedSig, 24, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 212:27] node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 210:16] node _common_underflow_T = shr(io.in.sExp, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:49] node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:64] node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:32] node _common_underflow_T_3 = bits(roundMask, 3, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:57] node _common_underflow_T_4 = bits(roundMask, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:71] node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:30] node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:72] node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 221:49] node _common_underflow_T_8 = bits(roundMask, 4, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 223:49] node _common_underflow_T_9 = bits(roundMask, 3, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 224:49] node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 222:39] node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 222:34] node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 221:77] node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 225:38] node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 226:45] node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 226:60] node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 221:27] node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:76] node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 216:40] connect common_underflow, _common_underflow_T_18 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 214:26] node _common_inexact_T = or(common_totalUnderflow, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 229:49] connect common_inexact, _common_inexact_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 229:24] node isNaNOut = or(io.invalidExc, io.in.isNaN) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 234:34] node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 235:49] node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:22] node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:36] node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:33] node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:64] node commonCase = and(_commonCase_T_2, _commonCase_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:61] node overflow = and(commonCase, common_overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 237:32] node underflow = and(commonCase, common_underflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 238:32] node _inexact_T = and(commonCase, common_inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 239:43] node inexact = or(overflow, _inexact_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 239:28] node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 242:32] node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 242:60] node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:20] node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:60] node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:45] node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 245:42] node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 245:39] node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 247:45] node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 247:32] node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 249:22] node _expOut_T = or(io.in.isZero, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:32] node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:18] node _expOut_T_2 = not(_expOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:14] node _expOut_T_3 = and(common_expOut, _expOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 251:24] node _expOut_T_4 = not(UInt<9>(0h6b)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 257:19] node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 256:18] node _expOut_T_6 = not(_expOut_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 256:14] node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 255:17] node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 260:18] node _expOut_T_9 = not(_expOut_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 260:14] node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 259:17] node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 264:18] node _expOut_T_12 = not(_expOut_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 264:14] node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 263:17] node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 268:16] node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 267:18] node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 272:16] node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 271:15] node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 276:16] node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 275:15] node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 277:16] node expOut = or(_expOut_T_19, _expOut_T_20) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 276:73] node _fractOut_T = or(isNaNOut, io.in.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:22] node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:38] node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 280:16] node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:12] node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 283:13] node fractOut = or(_fractOut_T_3, _fractOut_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 282:11] node _io_out_T = cat(signOut, expOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:23] node _io_out_T_1 = cat(_io_out_T, fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:33] connect io.out, _io_out_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:12] node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:23] node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:41] node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:53] node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:66] connect io.exceptionFlags, _io_exceptionFlags_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 286:23] module RoundRawFNToRecFN : @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 294:5] output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 297:16] inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 308:15] connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 311:44] connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 312:44] connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 314:44] connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 315:44] connect io.out, roundAnyRawFNToRecFN.io.out @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 316:23] connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 317:23] module MulAddRecFNPipe_l2_e8_s24 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 633:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 633:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 633:7] output io : { flip validin : UInt<1>, flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>, validout : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 638:16] inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 654:41] inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 655:42] connect mulAddRecFNToRaw_preMul.io.op, io.op @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 657:35] connect mulAddRecFNToRaw_preMul.io.a, io.a @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 658:35] connect mulAddRecFNToRaw_preMul.io.b, io.b @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 659:35] connect mulAddRecFNToRaw_preMul.io.c, io.c @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 660:35] node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 663:45] node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 664:50] wire valid_stage0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 667:28] wire roundingMode_stage0 : UInt<3> @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 668:35] wire detectTininess_stage0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 669:37] regreset mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v, io.validin @[src/main/scala/chisel3/util/Valid.scala 141:24] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when io.validin : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b, mulAddRecFNToRaw_preMul.io.toPostMul @[src/main/scala/chisel3/util/Valid.scala 142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out : { valid : UInt<1>, bits : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.valid, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.bit0AlignedSigC @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.highAlignedSigC @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CDom_CAlignDist @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CIsDominant @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.doSubMags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.sExpSum @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroC @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfC @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNC @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.signProd @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroB @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfB @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroA @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfA @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNAOrB @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isSigNaNAny @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] regreset mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v, io.validin @[src/main/scala/chisel3/util/Valid.scala 141:24] reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b : UInt<49>, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when io.validin : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b, mulAddResult @[src/main/scala/chisel3/util/Valid.scala 142:26] wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out : { valid : UInt<1>, bits : UInt<49>} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.valid, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 673:46] regreset mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v, io.validin @[src/main/scala/chisel3/util/Valid.scala 141:24] reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b : UInt<3>, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when io.validin : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b, io.roundingMode @[src/main/scala/chisel3/util/Valid.scala 142:26] wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.valid, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect mulAddRecFNToRaw_postMul.io.roundingMode, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 674:46] regreset roundingMode_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect roundingMode_stage0_pipe_v, io.validin @[src/main/scala/chisel3/util/Valid.scala 141:24] reg roundingMode_stage0_pipe_b : UInt<3>, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when io.validin : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect roundingMode_stage0_pipe_b, io.roundingMode @[src/main/scala/chisel3/util/Valid.scala 142:26] wire roundingMode_stage0_pipe_out : { valid : UInt<1>, bits : UInt<3>} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect roundingMode_stage0_pipe_out.valid, roundingMode_stage0_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect roundingMode_stage0_pipe_out.bits, roundingMode_stage0_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect roundingMode_stage0, roundingMode_stage0_pipe_out.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 675:46] regreset detectTininess_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect detectTininess_stage0_pipe_v, io.validin @[src/main/scala/chisel3/util/Valid.scala 141:24] reg detectTininess_stage0_pipe_b : UInt<1>, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when io.validin : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect detectTininess_stage0_pipe_b, io.detectTininess @[src/main/scala/chisel3/util/Valid.scala 142:26] wire detectTininess_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect detectTininess_stage0_pipe_out.valid, detectTininess_stage0_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect detectTininess_stage0_pipe_out.bits, detectTininess_stage0_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect detectTininess_stage0, detectTininess_stage0_pipe_out.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 676:46] regreset valid_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect valid_stage0_pipe_v, io.validin @[src/main/scala/chisel3/util/Valid.scala 141:24] reg valid_stage0_pipe_b : UInt<1>, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when io.validin : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect valid_stage0_pipe_b, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 142:26] wire valid_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect valid_stage0_pipe_out.valid, valid_stage0_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect valid_stage0_pipe_out.bits, valid_stage0_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect valid_stage0, valid_stage0_pipe_out.valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 677:46] inst roundRawFNToRecFN of RoundRawFNToRecFN @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 682:35] regreset roundRawFNToRecFN_io_invalidExc_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect roundRawFNToRecFN_io_invalidExc_pipe_v, valid_stage0 @[src/main/scala/chisel3/util/Valid.scala 141:24] reg roundRawFNToRecFN_io_invalidExc_pipe_b : UInt<1>, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when valid_stage0 : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect roundRawFNToRecFN_io_invalidExc_pipe_b, mulAddRecFNToRaw_postMul.io.invalidExc @[src/main/scala/chisel3/util/Valid.scala 142:26] wire roundRawFNToRecFN_io_invalidExc_pipe_out : { valid : UInt<1>, bits : UInt<1>} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect roundRawFNToRecFN_io_invalidExc_pipe_out.valid, roundRawFNToRecFN_io_invalidExc_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect roundRawFNToRecFN_io_invalidExc_pipe_out.bits, roundRawFNToRecFN_io_invalidExc_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect roundRawFNToRecFN.io.invalidExc, roundRawFNToRecFN_io_invalidExc_pipe_out.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 685:45] regreset roundRawFNToRecFN_io_in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect roundRawFNToRecFN_io_in_pipe_v, valid_stage0 @[src/main/scala/chisel3/util/Valid.scala 141:24] reg roundRawFNToRecFN_io_in_pipe_b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when valid_stage0 : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect roundRawFNToRecFN_io_in_pipe_b, mulAddRecFNToRaw_postMul.io.rawOut @[src/main/scala/chisel3/util/Valid.scala 142:26] wire roundRawFNToRecFN_io_in_pipe_out : { valid : UInt<1>, bits : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect roundRawFNToRecFN_io_in_pipe_out.valid, roundRawFNToRecFN_io_in_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect roundRawFNToRecFN_io_in_pipe_out.bits, roundRawFNToRecFN_io_in_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect roundRawFNToRecFN.io.in.sig, roundRawFNToRecFN_io_in_pipe_out.bits.sig @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 686:45] connect roundRawFNToRecFN.io.in.sExp, roundRawFNToRecFN_io_in_pipe_out.bits.sExp @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 686:45] connect roundRawFNToRecFN.io.in.sign, roundRawFNToRecFN_io_in_pipe_out.bits.sign @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 686:45] connect roundRawFNToRecFN.io.in.isZero, roundRawFNToRecFN_io_in_pipe_out.bits.isZero @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 686:45] connect roundRawFNToRecFN.io.in.isInf, roundRawFNToRecFN_io_in_pipe_out.bits.isInf @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 686:45] connect roundRawFNToRecFN.io.in.isNaN, roundRawFNToRecFN_io_in_pipe_out.bits.isNaN @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 686:45] regreset roundRawFNToRecFN_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect roundRawFNToRecFN_io_roundingMode_pipe_v, valid_stage0 @[src/main/scala/chisel3/util/Valid.scala 141:24] reg roundRawFNToRecFN_io_roundingMode_pipe_b : UInt<3>, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when valid_stage0 : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect roundRawFNToRecFN_io_roundingMode_pipe_b, roundingMode_stage0 @[src/main/scala/chisel3/util/Valid.scala 142:26] wire roundRawFNToRecFN_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect roundRawFNToRecFN_io_roundingMode_pipe_out.valid, roundRawFNToRecFN_io_roundingMode_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect roundRawFNToRecFN_io_roundingMode_pipe_out.bits, roundRawFNToRecFN_io_roundingMode_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect roundRawFNToRecFN.io.roundingMode, roundRawFNToRecFN_io_roundingMode_pipe_out.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 687:45] regreset roundRawFNToRecFN_io_detectTininess_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect roundRawFNToRecFN_io_detectTininess_pipe_v, valid_stage0 @[src/main/scala/chisel3/util/Valid.scala 141:24] reg roundRawFNToRecFN_io_detectTininess_pipe_b : UInt<1>, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when valid_stage0 : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect roundRawFNToRecFN_io_detectTininess_pipe_b, detectTininess_stage0 @[src/main/scala/chisel3/util/Valid.scala 142:26] wire roundRawFNToRecFN_io_detectTininess_pipe_out : { valid : UInt<1>, bits : UInt<1>} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect roundRawFNToRecFN_io_detectTininess_pipe_out.valid, roundRawFNToRecFN_io_detectTininess_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect roundRawFNToRecFN_io_detectTininess_pipe_out.bits, roundRawFNToRecFN_io_detectTininess_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect roundRawFNToRecFN.io.detectTininess, roundRawFNToRecFN_io_detectTininess_pipe_out.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 688:45] regreset io_validout_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect io_validout_pipe_v, valid_stage0 @[src/main/scala/chisel3/util/Valid.scala 141:24] reg io_validout_pipe_b : UInt<1>, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when valid_stage0 : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect io_validout_pipe_b, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 142:26] wire io_validout_pipe_out : { valid : UInt<1>, bits : UInt<1>} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect io_validout_pipe_out.valid, io_validout_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect io_validout_pipe_out.bits, io_validout_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect io.validout, io_validout_pipe_out.valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 689:45] connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 691:38] connect io.out, roundRawFNToRecFN.io.out @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 693:23] connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 694:23] module FPUFMAPipe_l3_f32 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 697:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 697:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 697:7] output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 702:14] reg valid : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 707:22] connect valid, io.in.valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 707:22] reg in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 708:15] when io.in.valid : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 709:22] node one = shl(UInt<1>(0h1), 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 710:19] node _zero_T = xor(io.in.bits.in1, io.in.bits.in2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 711:32] node _zero_T_1 = shl(UInt<1>(0h1), 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 711:57] node zero = and(_zero_T, _zero_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 711:50] connect in, io.in.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 714:8] when io.in.bits.swap23 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 715:23] connect in.in2, one @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 715:32] node _T = or(io.in.bits.ren3, io.in.bits.swap23) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 716:21] node _T_1 = eq(_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 716:11] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 716:37] connect in.in3, zero @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 716:46] inst fma of MulAddRecFNPipe_l2_e8_s24 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 719:19] connect fma.clock, clock connect fma.reset, reset connect fma.io.validin, valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 720:18] connect fma.io.op, in.fmaCmd @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 721:13] connect fma.io.roundingMode, in.rm @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 722:23] connect fma.io.detectTininess, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 723:25] connect fma.io.a, in.in1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 724:12] connect fma.io.b, in.in2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 725:12] connect fma.io.c, in.in3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 726:12] wire res : { data : UInt<65>, exc : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 728:17] connect res.data, fma.io.out @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 729:12] connect res.exc, fma.io.exceptionFlags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 730:11] wire io_out_out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect io_out_out.valid, fma.io.validout @[src/main/scala/chisel3/util/Valid.scala 136:17] connect io_out_out.bits, res @[src/main/scala/chisel3/util/Valid.scala 137:16] connect io.out, io_out_out @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 732:10] module CompareRecFN : @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 42:7] output io : { flip a : UInt<65>, flip b : UInt<65>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>} @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 44:16] node rawA_exp = bits(io.a, 63, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _rawA_isZero_T = bits(rawA_exp, 11, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _rawA_isSpecial_T = bits(rawA_exp, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _rawA_out_isNaN_T = bits(rawA_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect rawA.isNaN, _rawA_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _rawA_out_isInf_T = bits(rawA_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect rawA.isInf, _rawA_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect rawA.isZero, rawA_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _rawA_out_sign_T = bits(io.a, 64, 64) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect rawA.sign, _rawA_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _rawA_out_sExp_T = cvt(rawA_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect rawA.sExp, _rawA_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _rawA_out_sig_T_2 = bits(io.a, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect rawA.sig, _rawA_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node rawB_exp = bits(io.b, 63, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _rawB_isZero_T = bits(rawB_exp, 11, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _rawB_isSpecial_T = bits(rawB_exp, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _rawB_out_isNaN_T = bits(rawB_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect rawB.isNaN, _rawB_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _rawB_out_isInf_T = bits(rawB_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect rawB.isInf, _rawB_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect rawB.isZero, rawB_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _rawB_out_sign_T = bits(io.b, 64, 64) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect rawB.sign, _rawB_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _rawB_out_sExp_T = cvt(rawB_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect rawB.sExp, _rawB_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _rawB_out_sig_T_2 = bits(io.b, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect rawB.sig, _rawB_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node _ordered_T = eq(rawA.isNaN, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 57:19] node _ordered_T_1 = eq(rawB.isNaN, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 57:35] node ordered = and(_ordered_T, _ordered_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 57:32] node bothInfs = and(rawA.isInf, rawB.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 58:33] node bothZeros = and(rawA.isZero, rawB.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 59:33] node eqExps = eq(rawA.sExp, rawB.sExp) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 60:29] node _common_ltMags_T = lt(rawA.sExp, rawB.sExp) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 62:20] node _common_ltMags_T_1 = lt(rawA.sig, rawB.sig) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 62:57] node _common_ltMags_T_2 = and(eqExps, _common_ltMags_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 62:44] node common_ltMags = or(_common_ltMags_T, _common_ltMags_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 62:33] node _common_eqMags_T = eq(rawA.sig, rawB.sig) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 63:45] node common_eqMags = and(eqExps, _common_eqMags_T) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 63:32] node _ordered_lt_T = eq(bothZeros, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 66:9] node _ordered_lt_T_1 = eq(rawB.sign, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 67:28] node _ordered_lt_T_2 = and(rawA.sign, _ordered_lt_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 67:25] node _ordered_lt_T_3 = eq(bothInfs, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 68:19] node _ordered_lt_T_4 = eq(common_ltMags, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 69:38] node _ordered_lt_T_5 = and(rawA.sign, _ordered_lt_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 69:35] node _ordered_lt_T_6 = eq(common_eqMags, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 69:57] node _ordered_lt_T_7 = and(_ordered_lt_T_5, _ordered_lt_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 69:54] node _ordered_lt_T_8 = eq(rawB.sign, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 70:29] node _ordered_lt_T_9 = and(_ordered_lt_T_8, common_ltMags) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 70:41] node _ordered_lt_T_10 = or(_ordered_lt_T_7, _ordered_lt_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 69:74] node _ordered_lt_T_11 = and(_ordered_lt_T_3, _ordered_lt_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 68:30] node _ordered_lt_T_12 = or(_ordered_lt_T_2, _ordered_lt_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 67:41] node ordered_lt = and(_ordered_lt_T, _ordered_lt_T_12) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 66:21] node _ordered_eq_T = eq(rawA.sign, rawB.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 72:34] node _ordered_eq_T_1 = or(bothInfs, common_eqMags) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 72:62] node _ordered_eq_T_2 = and(_ordered_eq_T, _ordered_eq_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 72:49] node ordered_eq = or(bothZeros, _ordered_eq_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 72:19] node _invalid_T = bits(rawA.sig, 51, 51) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:56] node _invalid_T_1 = eq(_invalid_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:49] node _invalid_T_2 = and(rawA.isNaN, _invalid_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:46] node _invalid_T_3 = bits(rawB.sig, 51, 51) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:56] node _invalid_T_4 = eq(_invalid_T_3, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:49] node _invalid_T_5 = and(rawB.isNaN, _invalid_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:46] node _invalid_T_6 = or(_invalid_T_2, _invalid_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 75:32] node _invalid_T_7 = eq(ordered, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 76:30] node _invalid_T_8 = and(io.signaling, _invalid_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 76:27] node invalid = or(_invalid_T_6, _invalid_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 75:58] node _io_lt_T = and(ordered, ordered_lt) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 78:22] connect io.lt, _io_lt_T @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 78:11] node _io_eq_T = and(ordered, ordered_eq) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 79:22] connect io.eq, _io_eq_T @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 79:11] node _io_gt_T = eq(ordered_lt, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 80:25] node _io_gt_T_1 = and(ordered, _io_gt_T) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 80:22] node _io_gt_T_2 = eq(ordered_eq, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 80:41] node _io_gt_T_3 = and(_io_gt_T_1, _io_gt_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 80:38] connect io.gt, _io_gt_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 80:11] node _io_exceptionFlags_T = cat(invalid, UInt<4>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 81:34] connect io.exceptionFlags, _io_exceptionFlags_T @[dependencies/hardfloat/hardfloat/src/main/scala/CompareRecFN.scala 81:23] module RecFNToIN : @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 46:7] input clock : Clock @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 46:7] input reset : Reset @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 46:7] output io : { flip in : UInt<65>, flip roundingMode : UInt<3>, flip signedOut : UInt<1>, out : UInt<64>, intExceptionFlags : UInt<3>} @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 48:16] node rawIn_exp = bits(io.in, 63, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _rawIn_isZero_T = bits(rawIn_exp, 11, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _rawIn_isSpecial_T = bits(rawIn_exp, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _rawIn_out_isNaN_T = bits(rawIn_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect rawIn.isNaN, _rawIn_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _rawIn_out_isInf_T = bits(rawIn_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect rawIn.isInf, _rawIn_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect rawIn.isZero, rawIn_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _rawIn_out_sign_T = bits(io.in, 64, 64) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect rawIn.sign, _rawIn_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _rawIn_out_sExp_T = cvt(rawIn_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect rawIn.sExp, _rawIn_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _rawIn_out_sig_T_2 = bits(io.in, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect rawIn.sig, _rawIn_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node magGeOne = bits(rawIn.sExp, 11, 11) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 60:30] node posExp = bits(rawIn.sExp, 10, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 61:28] node _magJustBelowOne_T = eq(magGeOne, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 62:27] node _magJustBelowOne_T_1 = andr(posExp) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 62:47] node magJustBelowOne = and(_magJustBelowOne_T, _magJustBelowOne_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 62:37] node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 66:53] node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 67:53] node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 68:53] node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 69:53] node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 70:53] node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 71:53] node _shiftedSig_T = bits(rawIn.sig, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 82:31] node _shiftedSig_T_1 = cat(magGeOne, _shiftedSig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 82:19] node _shiftedSig_T_2 = bits(rawIn.sExp, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 84:27] node _shiftedSig_T_3 = mux(magGeOne, _shiftedSig_T_2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 83:16] node shiftedSig = dshl(_shiftedSig_T_1, _shiftedSig_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 82:49] node _alignedSig_T = shr(shiftedSig, 51) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 88:20] node _alignedSig_T_1 = bits(shiftedSig, 50, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 88:51] node _alignedSig_T_2 = orr(_alignedSig_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 88:69] node alignedSig = cat(_alignedSig_T, _alignedSig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 88:38] node _unroundedInt_T = shr(alignedSig, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 89:52] node unroundedInt = or(UInt<64>(0h0), _unroundedInt_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 89:40] node _common_inexact_T = bits(alignedSig, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 91:50] node _common_inexact_T_1 = orr(_common_inexact_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 91:57] node _common_inexact_T_2 = eq(rawIn.isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 91:62] node common_inexact = mux(magGeOne, _common_inexact_T_1, _common_inexact_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 91:29] node _roundIncr_near_even_T = bits(alignedSig, 2, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 93:39] node _roundIncr_near_even_T_1 = andr(_roundIncr_near_even_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 93:46] node _roundIncr_near_even_T_2 = bits(alignedSig, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 93:64] node _roundIncr_near_even_T_3 = andr(_roundIncr_near_even_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 93:71] node _roundIncr_near_even_T_4 = or(_roundIncr_near_even_T_1, _roundIncr_near_even_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 93:51] node _roundIncr_near_even_T_5 = and(magGeOne, _roundIncr_near_even_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 93:25] node _roundIncr_near_even_T_6 = bits(alignedSig, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 94:39] node _roundIncr_near_even_T_7 = orr(_roundIncr_near_even_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 94:46] node _roundIncr_near_even_T_8 = and(magJustBelowOne, _roundIncr_near_even_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 94:26] node roundIncr_near_even = or(_roundIncr_near_even_T_5, _roundIncr_near_even_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 93:78] node _roundIncr_near_maxMag_T = bits(alignedSig, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 95:56] node _roundIncr_near_maxMag_T_1 = and(magGeOne, _roundIncr_near_maxMag_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 95:43] node roundIncr_near_maxMag = or(_roundIncr_near_maxMag_T_1, magJustBelowOne) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 95:61] node _roundIncr_T = and(roundingMode_near_even, roundIncr_near_even) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 97:35] node _roundIncr_T_1 = and(roundingMode_near_maxMag, roundIncr_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 98:35] node _roundIncr_T_2 = or(_roundIncr_T, _roundIncr_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 97:61] node _roundIncr_T_3 = or(roundingMode_min, roundingMode_odd) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 99:28] node _roundIncr_T_4 = and(rawIn.sign, common_inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 100:26] node _roundIncr_T_5 = and(_roundIncr_T_3, _roundIncr_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 99:49] node _roundIncr_T_6 = or(_roundIncr_T_2, _roundIncr_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 98:61] node _roundIncr_T_7 = eq(rawIn.sign, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 101:31] node _roundIncr_T_8 = and(_roundIncr_T_7, common_inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 101:43] node _roundIncr_T_9 = and(roundingMode_max, _roundIncr_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 101:27] node roundIncr = or(_roundIncr_T_6, _roundIncr_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 100:46] node _complUnroundedInt_T = not(unroundedInt) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 102:45] node complUnroundedInt = mux(rawIn.sign, _complUnroundedInt_T, unroundedInt) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 102:32] node _roundedInt_T = xor(roundIncr, rawIn.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 104:23] node _roundedInt_T_1 = add(complUnroundedInt, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 105:31] node _roundedInt_T_2 = tail(_roundedInt_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 105:31] node _roundedInt_T_3 = mux(_roundedInt_T, _roundedInt_T_2, complUnroundedInt) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 104:12] node _roundedInt_T_4 = and(roundingMode_odd, common_inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 107:31] node roundedInt = or(_roundedInt_T_3, _roundedInt_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 107:11] node magGeOne_atOverflowEdge = eq(posExp, UInt<6>(0h3f)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 109:43] node _roundCarryBut2_T = bits(unroundedInt, 61, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 112:38] node _roundCarryBut2_T_1 = andr(_roundCarryBut2_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 112:56] node roundCarryBut2 = and(_roundCarryBut2_T_1, roundIncr) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 112:61] node _common_overflow_T = geq(posExp, UInt<7>(0h40)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 115:21] node _common_overflow_T_1 = bits(unroundedInt, 62, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 119:42] node _common_overflow_T_2 = orr(_common_overflow_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 119:60] node _common_overflow_T_3 = or(_common_overflow_T_2, roundIncr) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 119:64] node _common_overflow_T_4 = and(magGeOne_atOverflowEdge, _common_overflow_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 118:49] node _common_overflow_T_5 = eq(posExp, UInt<6>(0h3e)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 121:38] node _common_overflow_T_6 = and(_common_overflow_T_5, roundCarryBut2) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 121:60] node _common_overflow_T_7 = or(magGeOne_atOverflowEdge, _common_overflow_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 120:49] node _common_overflow_T_8 = mux(rawIn.sign, _common_overflow_T_4, _common_overflow_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 117:24] node _common_overflow_T_9 = bits(unroundedInt, 62, 62) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 125:42] node _common_overflow_T_10 = and(magGeOne_atOverflowEdge, _common_overflow_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 124:50] node _common_overflow_T_11 = and(_common_overflow_T_10, roundCarryBut2) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 125:57] node _common_overflow_T_12 = or(rawIn.sign, _common_overflow_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 123:32] node _common_overflow_T_13 = mux(io.signedOut, _common_overflow_T_8, _common_overflow_T_12) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 116:20] node _common_overflow_T_14 = or(_common_overflow_T, _common_overflow_T_13) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 115:36] node _common_overflow_T_15 = eq(io.signedOut, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 127:13] node _common_overflow_T_16 = and(_common_overflow_T_15, rawIn.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 127:27] node _common_overflow_T_17 = and(_common_overflow_T_16, roundIncr) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 127:41] node common_overflow = mux(magGeOne, _common_overflow_T_14, _common_overflow_T_17) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 114:12] node invalidExc = or(rawIn.isNaN, rawIn.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 132:34] node _overflow_T = eq(invalidExc, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 133:20] node overflow = and(_overflow_T, common_overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 133:32] node _inexact_T = eq(invalidExc, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 134:20] node _inexact_T_1 = eq(common_overflow, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 134:35] node _inexact_T_2 = and(_inexact_T, _inexact_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 134:32] node inexact = and(_inexact_T_2, common_inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 134:52] node _excSign_T = eq(rawIn.isNaN, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 136:19] node excSign = and(_excSign_T, rawIn.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 136:32] node _excOut_T = eq(io.signedOut, excSign) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 138:27] node _excOut_T_1 = mux(_excOut_T, UInt<64>(0h8000000000000000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 138:12] node _excOut_T_2 = eq(excSign, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 142:13] node _excOut_T_3 = mux(_excOut_T_2, UInt<63>(0h7fffffffffffffff), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 142:12] node excOut = or(_excOut_T_1, _excOut_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 141:11] node _io_out_T = or(invalidExc, common_overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 144:30] node _io_out_T_1 = mux(_io_out_T, excOut, roundedInt) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 144:18] connect io.out, _io_out_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 144:12] node _io_intExceptionFlags_T = cat(invalidExc, overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 145:40] node _io_intExceptionFlags_T_1 = cat(_io_intExceptionFlags_T, inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 145:52] connect io.intExceptionFlags, _io_intExceptionFlags_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 145:26] module RecFNToIN_1 : @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 46:7] input clock : Clock @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 46:7] input reset : Reset @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 46:7] output io : { flip in : UInt<65>, flip roundingMode : UInt<3>, flip signedOut : UInt<1>, out : UInt<32>, intExceptionFlags : UInt<3>} @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 48:16] node rawIn_exp = bits(io.in, 63, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _rawIn_isZero_T = bits(rawIn_exp, 11, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _rawIn_isSpecial_T = bits(rawIn_exp, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _rawIn_out_isNaN_T = bits(rawIn_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect rawIn.isNaN, _rawIn_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _rawIn_out_isInf_T = bits(rawIn_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect rawIn.isInf, _rawIn_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect rawIn.isZero, rawIn_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _rawIn_out_sign_T = bits(io.in, 64, 64) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect rawIn.sign, _rawIn_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _rawIn_out_sExp_T = cvt(rawIn_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect rawIn.sExp, _rawIn_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _rawIn_out_sig_T_2 = bits(io.in, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect rawIn.sig, _rawIn_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node magGeOne = bits(rawIn.sExp, 11, 11) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 60:30] node posExp = bits(rawIn.sExp, 10, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 61:28] node _magJustBelowOne_T = eq(magGeOne, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 62:27] node _magJustBelowOne_T_1 = andr(posExp) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 62:47] node magJustBelowOne = and(_magJustBelowOne_T, _magJustBelowOne_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 62:37] node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 66:53] node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 67:53] node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 68:53] node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 69:53] node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 70:53] node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 71:53] node _shiftedSig_T = bits(rawIn.sig, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 82:31] node _shiftedSig_T_1 = cat(magGeOne, _shiftedSig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 82:19] node _shiftedSig_T_2 = bits(rawIn.sExp, 4, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 84:27] node _shiftedSig_T_3 = mux(magGeOne, _shiftedSig_T_2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 83:16] node shiftedSig = dshl(_shiftedSig_T_1, _shiftedSig_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 82:49] node _alignedSig_T = shr(shiftedSig, 51) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 88:20] node _alignedSig_T_1 = bits(shiftedSig, 50, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 88:51] node _alignedSig_T_2 = orr(_alignedSig_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 88:69] node alignedSig = cat(_alignedSig_T, _alignedSig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 88:38] node _unroundedInt_T = shr(alignedSig, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 89:52] node unroundedInt = or(UInt<32>(0h0), _unroundedInt_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 89:40] node _common_inexact_T = bits(alignedSig, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 91:50] node _common_inexact_T_1 = orr(_common_inexact_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 91:57] node _common_inexact_T_2 = eq(rawIn.isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 91:62] node common_inexact = mux(magGeOne, _common_inexact_T_1, _common_inexact_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 91:29] node _roundIncr_near_even_T = bits(alignedSig, 2, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 93:39] node _roundIncr_near_even_T_1 = andr(_roundIncr_near_even_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 93:46] node _roundIncr_near_even_T_2 = bits(alignedSig, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 93:64] node _roundIncr_near_even_T_3 = andr(_roundIncr_near_even_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 93:71] node _roundIncr_near_even_T_4 = or(_roundIncr_near_even_T_1, _roundIncr_near_even_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 93:51] node _roundIncr_near_even_T_5 = and(magGeOne, _roundIncr_near_even_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 93:25] node _roundIncr_near_even_T_6 = bits(alignedSig, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 94:39] node _roundIncr_near_even_T_7 = orr(_roundIncr_near_even_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 94:46] node _roundIncr_near_even_T_8 = and(magJustBelowOne, _roundIncr_near_even_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 94:26] node roundIncr_near_even = or(_roundIncr_near_even_T_5, _roundIncr_near_even_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 93:78] node _roundIncr_near_maxMag_T = bits(alignedSig, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 95:56] node _roundIncr_near_maxMag_T_1 = and(magGeOne, _roundIncr_near_maxMag_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 95:43] node roundIncr_near_maxMag = or(_roundIncr_near_maxMag_T_1, magJustBelowOne) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 95:61] node _roundIncr_T = and(roundingMode_near_even, roundIncr_near_even) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 97:35] node _roundIncr_T_1 = and(roundingMode_near_maxMag, roundIncr_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 98:35] node _roundIncr_T_2 = or(_roundIncr_T, _roundIncr_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 97:61] node _roundIncr_T_3 = or(roundingMode_min, roundingMode_odd) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 99:28] node _roundIncr_T_4 = and(rawIn.sign, common_inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 100:26] node _roundIncr_T_5 = and(_roundIncr_T_3, _roundIncr_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 99:49] node _roundIncr_T_6 = or(_roundIncr_T_2, _roundIncr_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 98:61] node _roundIncr_T_7 = eq(rawIn.sign, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 101:31] node _roundIncr_T_8 = and(_roundIncr_T_7, common_inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 101:43] node _roundIncr_T_9 = and(roundingMode_max, _roundIncr_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 101:27] node roundIncr = or(_roundIncr_T_6, _roundIncr_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 100:46] node _complUnroundedInt_T = not(unroundedInt) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 102:45] node complUnroundedInt = mux(rawIn.sign, _complUnroundedInt_T, unroundedInt) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 102:32] node _roundedInt_T = xor(roundIncr, rawIn.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 104:23] node _roundedInt_T_1 = add(complUnroundedInt, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 105:31] node _roundedInt_T_2 = tail(_roundedInt_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 105:31] node _roundedInt_T_3 = mux(_roundedInt_T, _roundedInt_T_2, complUnroundedInt) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 104:12] node _roundedInt_T_4 = and(roundingMode_odd, common_inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 107:31] node roundedInt = or(_roundedInt_T_3, _roundedInt_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 107:11] node magGeOne_atOverflowEdge = eq(posExp, UInt<5>(0h1f)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 109:43] node _roundCarryBut2_T = bits(unroundedInt, 29, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 112:38] node _roundCarryBut2_T_1 = andr(_roundCarryBut2_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 112:56] node roundCarryBut2 = and(_roundCarryBut2_T_1, roundIncr) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 112:61] node _common_overflow_T = geq(posExp, UInt<6>(0h20)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 115:21] node _common_overflow_T_1 = bits(unroundedInt, 30, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 119:42] node _common_overflow_T_2 = orr(_common_overflow_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 119:60] node _common_overflow_T_3 = or(_common_overflow_T_2, roundIncr) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 119:64] node _common_overflow_T_4 = and(magGeOne_atOverflowEdge, _common_overflow_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 118:49] node _common_overflow_T_5 = eq(posExp, UInt<5>(0h1e)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 121:38] node _common_overflow_T_6 = and(_common_overflow_T_5, roundCarryBut2) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 121:60] node _common_overflow_T_7 = or(magGeOne_atOverflowEdge, _common_overflow_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 120:49] node _common_overflow_T_8 = mux(rawIn.sign, _common_overflow_T_4, _common_overflow_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 117:24] node _common_overflow_T_9 = bits(unroundedInt, 30, 30) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 125:42] node _common_overflow_T_10 = and(magGeOne_atOverflowEdge, _common_overflow_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 124:50] node _common_overflow_T_11 = and(_common_overflow_T_10, roundCarryBut2) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 125:57] node _common_overflow_T_12 = or(rawIn.sign, _common_overflow_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 123:32] node _common_overflow_T_13 = mux(io.signedOut, _common_overflow_T_8, _common_overflow_T_12) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 116:20] node _common_overflow_T_14 = or(_common_overflow_T, _common_overflow_T_13) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 115:36] node _common_overflow_T_15 = eq(io.signedOut, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 127:13] node _common_overflow_T_16 = and(_common_overflow_T_15, rawIn.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 127:27] node _common_overflow_T_17 = and(_common_overflow_T_16, roundIncr) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 127:41] node common_overflow = mux(magGeOne, _common_overflow_T_14, _common_overflow_T_17) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 114:12] node invalidExc = or(rawIn.isNaN, rawIn.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 132:34] node _overflow_T = eq(invalidExc, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 133:20] node overflow = and(_overflow_T, common_overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 133:32] node _inexact_T = eq(invalidExc, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 134:20] node _inexact_T_1 = eq(common_overflow, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 134:35] node _inexact_T_2 = and(_inexact_T, _inexact_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 134:32] node inexact = and(_inexact_T_2, common_inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 134:52] node _excSign_T = eq(rawIn.isNaN, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 136:19] node excSign = and(_excSign_T, rawIn.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 136:32] node _excOut_T = eq(io.signedOut, excSign) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 138:27] node _excOut_T_1 = mux(_excOut_T, UInt<32>(0h80000000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 138:12] node _excOut_T_2 = eq(excSign, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 142:13] node _excOut_T_3 = mux(_excOut_T_2, UInt<31>(0h7fffffff), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 142:12] node excOut = or(_excOut_T_1, _excOut_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 141:11] node _io_out_T = or(invalidExc, common_overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 144:30] node _io_out_T_1 = mux(_io_out_T, excOut, roundedInt) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 144:18] connect io.out, _io_out_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 144:12] node _io_intExceptionFlags_T = cat(invalidExc, overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 145:40] node _io_intExceptionFlags_T_1 = cat(_io_intExceptionFlags_T, inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 145:52] connect io.intExceptionFlags, _io_intExceptionFlags_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToIN.scala 145:26] module FPToInt : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 453:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 453:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 453:7] output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 461:14] reg in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 466:21] when io.in.valid : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 466:21] connect in, io.in.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 466:21] reg valid : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 467:22] connect valid, io.in.valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 467:22] inst dcmp of CompareRecFN @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 469:20] connect dcmp.io.a, in.in1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 470:13] connect dcmp.io.b, in.in2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 471:13] node _dcmp_io_signaling_T = bits(in.rm, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 472:30] node _dcmp_io_signaling_T_1 = eq(_dcmp_io_signaling_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 472:24] connect dcmp.io.signaling, _dcmp_io_signaling_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 472:21] node toint_ieee_unrecoded_rawIn_exp = bits(in.in1, 63, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _toint_ieee_unrecoded_rawIn_isZero_T = bits(toint_ieee_unrecoded_rawIn_exp, 11, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node toint_ieee_unrecoded_rawIn_isZero = eq(_toint_ieee_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _toint_ieee_unrecoded_rawIn_isSpecial_T = bits(toint_ieee_unrecoded_rawIn_exp, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node toint_ieee_unrecoded_rawIn_isSpecial = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire toint_ieee_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _toint_ieee_unrecoded_rawIn_out_isNaN_T = bits(toint_ieee_unrecoded_rawIn_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_unrecoded_rawIn_isSpecial, _toint_ieee_unrecoded_rawIn_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect toint_ieee_unrecoded_rawIn.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _toint_ieee_unrecoded_rawIn_out_isInf_T = bits(toint_ieee_unrecoded_rawIn_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _toint_ieee_unrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _toint_ieee_unrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_unrecoded_rawIn_isSpecial, _toint_ieee_unrecoded_rawIn_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect toint_ieee_unrecoded_rawIn.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect toint_ieee_unrecoded_rawIn.isZero, toint_ieee_unrecoded_rawIn_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _toint_ieee_unrecoded_rawIn_out_sign_T = bits(in.in1, 64, 64) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect toint_ieee_unrecoded_rawIn.sign, _toint_ieee_unrecoded_rawIn_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _toint_ieee_unrecoded_rawIn_out_sExp_T = cvt(toint_ieee_unrecoded_rawIn_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect toint_ieee_unrecoded_rawIn.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _toint_ieee_unrecoded_rawIn_out_sig_T = eq(toint_ieee_unrecoded_rawIn_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _toint_ieee_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _toint_ieee_unrecoded_rawIn_out_sig_T_2 = bits(in.in1, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _toint_ieee_unrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_1, _toint_ieee_unrecoded_rawIn_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect toint_ieee_unrecoded_rawIn.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node toint_ieee_unrecoded_isSubnormal = lt(toint_ieee_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 51:38] node _toint_ieee_unrecoded_denormShiftDist_T = bits(toint_ieee_unrecoded_rawIn.sExp, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:47] node _toint_ieee_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node toint_ieee_unrecoded_denormShiftDist = tail(_toint_ieee_unrecoded_denormShiftDist_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node _toint_ieee_unrecoded_denormFract_T = shr(toint_ieee_unrecoded_rawIn.sig, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:38] node _toint_ieee_unrecoded_denormFract_T_1 = dshr(_toint_ieee_unrecoded_denormFract_T, toint_ieee_unrecoded_denormShiftDist) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:42] node toint_ieee_unrecoded_denormFract = bits(_toint_ieee_unrecoded_denormFract_T_1, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:60] node _toint_ieee_unrecoded_expOut_T = bits(toint_ieee_unrecoded_rawIn.sExp, 10, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:27] node _toint_ieee_unrecoded_expOut_T_1 = sub(_toint_ieee_unrecoded_expOut_T, UInt<11>(0h401)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _toint_ieee_unrecoded_expOut_T_2 = tail(_toint_ieee_unrecoded_expOut_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _toint_ieee_unrecoded_expOut_T_3 = mux(toint_ieee_unrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 56:16] node _toint_ieee_unrecoded_expOut_T_4 = or(toint_ieee_unrecoded_rawIn.isNaN, toint_ieee_unrecoded_rawIn.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:44] node _toint_ieee_unrecoded_expOut_T_5 = mux(_toint_ieee_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:21] node toint_ieee_unrecoded_expOut = or(_toint_ieee_unrecoded_expOut_T_3, _toint_ieee_unrecoded_expOut_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:15] node _toint_ieee_unrecoded_fractOut_T = bits(toint_ieee_unrecoded_rawIn.sig, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:48] node _toint_ieee_unrecoded_fractOut_T_1 = mux(toint_ieee_unrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:20] node toint_ieee_unrecoded_fractOut = mux(toint_ieee_unrecoded_isSubnormal, toint_ieee_unrecoded_denormFract, _toint_ieee_unrecoded_fractOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 62:16] node toint_ieee_unrecoded_hi = cat(toint_ieee_unrecoded_rawIn.sign, toint_ieee_unrecoded_expOut) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node toint_ieee_unrecoded = cat(toint_ieee_unrecoded_hi, toint_ieee_unrecoded_fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node _toint_ieee_prevRecoded_T = bits(in.in1, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 442:10] node _toint_ieee_prevRecoded_T_1 = bits(in.in1, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 443:10] node _toint_ieee_prevRecoded_T_2 = bits(in.in1, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 444:10] node toint_ieee_prevRecoded_hi = cat(_toint_ieee_prevRecoded_T, _toint_ieee_prevRecoded_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 441:28] node toint_ieee_prevRecoded = cat(toint_ieee_prevRecoded_hi, _toint_ieee_prevRecoded_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 441:28] node toint_ieee_prevUnrecoded_rawIn_exp = bits(toint_ieee_prevRecoded, 31, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _toint_ieee_prevUnrecoded_rawIn_isZero_T = bits(toint_ieee_prevUnrecoded_rawIn_exp, 8, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node toint_ieee_prevUnrecoded_rawIn_isZero = eq(_toint_ieee_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _toint_ieee_prevUnrecoded_rawIn_isSpecial_T = bits(toint_ieee_prevUnrecoded_rawIn_exp, 8, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node toint_ieee_prevUnrecoded_rawIn_isSpecial = eq(_toint_ieee_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire toint_ieee_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T = bits(toint_ieee_prevUnrecoded_rawIn_exp, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_prevUnrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect toint_ieee_prevUnrecoded_rawIn.isNaN, _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _toint_ieee_prevUnrecoded_rawIn_out_isInf_T = bits(toint_ieee_prevUnrecoded_rawIn_exp, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_prevUnrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect toint_ieee_prevUnrecoded_rawIn.isInf, _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect toint_ieee_prevUnrecoded_rawIn.isZero, toint_ieee_prevUnrecoded_rawIn_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _toint_ieee_prevUnrecoded_rawIn_out_sign_T = bits(toint_ieee_prevRecoded, 32, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect toint_ieee_prevUnrecoded_rawIn.sign, _toint_ieee_prevUnrecoded_rawIn_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _toint_ieee_prevUnrecoded_rawIn_out_sExp_T = cvt(toint_ieee_prevUnrecoded_rawIn_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect toint_ieee_prevUnrecoded_rawIn.sExp, _toint_ieee_prevUnrecoded_rawIn_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _toint_ieee_prevUnrecoded_rawIn_out_sig_T = eq(toint_ieee_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _toint_ieee_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_rawIn_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _toint_ieee_prevUnrecoded_rawIn_out_sig_T_2 = bits(toint_ieee_prevRecoded, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _toint_ieee_prevUnrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_prevUnrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_rawIn_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect toint_ieee_prevUnrecoded_rawIn.sig, _toint_ieee_prevUnrecoded_rawIn_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node toint_ieee_prevUnrecoded_isSubnormal = lt(toint_ieee_prevUnrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 51:38] node _toint_ieee_prevUnrecoded_denormShiftDist_T = bits(toint_ieee_prevUnrecoded_rawIn.sExp, 4, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:47] node _toint_ieee_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_denormShiftDist_T) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node toint_ieee_prevUnrecoded_denormShiftDist = tail(_toint_ieee_prevUnrecoded_denormShiftDist_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node _toint_ieee_prevUnrecoded_denormFract_T = shr(toint_ieee_prevUnrecoded_rawIn.sig, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:38] node _toint_ieee_prevUnrecoded_denormFract_T_1 = dshr(_toint_ieee_prevUnrecoded_denormFract_T, toint_ieee_prevUnrecoded_denormShiftDist) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:42] node toint_ieee_prevUnrecoded_denormFract = bits(_toint_ieee_prevUnrecoded_denormFract_T_1, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:60] node _toint_ieee_prevUnrecoded_expOut_T = bits(toint_ieee_prevUnrecoded_rawIn.sExp, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:27] node _toint_ieee_prevUnrecoded_expOut_T_1 = sub(_toint_ieee_prevUnrecoded_expOut_T, UInt<8>(0h81)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _toint_ieee_prevUnrecoded_expOut_T_2 = tail(_toint_ieee_prevUnrecoded_expOut_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _toint_ieee_prevUnrecoded_expOut_T_3 = mux(toint_ieee_prevUnrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_prevUnrecoded_expOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 56:16] node _toint_ieee_prevUnrecoded_expOut_T_4 = or(toint_ieee_prevUnrecoded_rawIn.isNaN, toint_ieee_prevUnrecoded_rawIn.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:44] node _toint_ieee_prevUnrecoded_expOut_T_5 = mux(_toint_ieee_prevUnrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:21] node toint_ieee_prevUnrecoded_expOut = or(_toint_ieee_prevUnrecoded_expOut_T_3, _toint_ieee_prevUnrecoded_expOut_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:15] node _toint_ieee_prevUnrecoded_fractOut_T = bits(toint_ieee_prevUnrecoded_rawIn.sig, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:48] node _toint_ieee_prevUnrecoded_fractOut_T_1 = mux(toint_ieee_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_fractOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:20] node toint_ieee_prevUnrecoded_fractOut = mux(toint_ieee_prevUnrecoded_isSubnormal, toint_ieee_prevUnrecoded_denormFract, _toint_ieee_prevUnrecoded_fractOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 62:16] node toint_ieee_prevUnrecoded_hi = cat(toint_ieee_prevUnrecoded_rawIn.sign, toint_ieee_prevUnrecoded_expOut) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node toint_ieee_prevUnrecoded = cat(toint_ieee_prevUnrecoded_hi, toint_ieee_prevUnrecoded_fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node _toint_ieee_T = shr(toint_ieee_unrecoded, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:21] node _toint_ieee_T_1 = bits(in.in1, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node _toint_ieee_T_2 = andr(_toint_ieee_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node _toint_ieee_T_3 = bits(toint_ieee_unrecoded, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:81] node _toint_ieee_T_4 = mux(_toint_ieee_T_2, toint_ieee_prevUnrecoded, _toint_ieee_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:44] node _toint_ieee_T_5 = cat(_toint_ieee_T, _toint_ieee_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:10] node _toint_ieee_T_6 = bits(_toint_ieee_T_5, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 476:109] node _toint_ieee_T_7 = cat(_toint_ieee_T_6, _toint_ieee_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 476:63] node toint_ieee_unrecoded_rawIn_exp_1 = bits(in.in1, 63, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _toint_ieee_unrecoded_rawIn_isZero_T_1 = bits(toint_ieee_unrecoded_rawIn_exp_1, 11, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node toint_ieee_unrecoded_rawIn_isZero_1 = eq(_toint_ieee_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _toint_ieee_unrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_unrecoded_rawIn_exp_1, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node toint_ieee_unrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire toint_ieee_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _toint_ieee_unrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_1, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_unrecoded_rawIn_isSpecial_1, _toint_ieee_unrecoded_rawIn_out_isNaN_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect toint_ieee_unrecoded_rawIn_1.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _toint_ieee_unrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_unrecoded_rawIn_exp_1, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _toint_ieee_unrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _toint_ieee_unrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_unrecoded_rawIn_isSpecial_1, _toint_ieee_unrecoded_rawIn_out_isInf_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect toint_ieee_unrecoded_rawIn_1.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_5 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect toint_ieee_unrecoded_rawIn_1.isZero, toint_ieee_unrecoded_rawIn_isZero_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _toint_ieee_unrecoded_rawIn_out_sign_T_1 = bits(in.in1, 64, 64) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect toint_ieee_unrecoded_rawIn_1.sign, _toint_ieee_unrecoded_rawIn_out_sign_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _toint_ieee_unrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_unrecoded_rawIn_exp_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect toint_ieee_unrecoded_rawIn_1.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _toint_ieee_unrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _toint_ieee_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _toint_ieee_unrecoded_rawIn_out_sig_T_6 = bits(in.in1, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _toint_ieee_unrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_5, _toint_ieee_unrecoded_rawIn_out_sig_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect toint_ieee_unrecoded_rawIn_1.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_7 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node toint_ieee_unrecoded_isSubnormal_1 = lt(toint_ieee_unrecoded_rawIn_1.sExp, asSInt(UInt<12>(0h402))) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 51:38] node _toint_ieee_unrecoded_denormShiftDist_T_2 = bits(toint_ieee_unrecoded_rawIn_1.sExp, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:47] node _toint_ieee_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node toint_ieee_unrecoded_denormShiftDist_1 = tail(_toint_ieee_unrecoded_denormShiftDist_T_3, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node _toint_ieee_unrecoded_denormFract_T_2 = shr(toint_ieee_unrecoded_rawIn_1.sig, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:38] node _toint_ieee_unrecoded_denormFract_T_3 = dshr(_toint_ieee_unrecoded_denormFract_T_2, toint_ieee_unrecoded_denormShiftDist_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:42] node toint_ieee_unrecoded_denormFract_1 = bits(_toint_ieee_unrecoded_denormFract_T_3, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:60] node _toint_ieee_unrecoded_expOut_T_6 = bits(toint_ieee_unrecoded_rawIn_1.sExp, 10, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:27] node _toint_ieee_unrecoded_expOut_T_7 = sub(_toint_ieee_unrecoded_expOut_T_6, UInt<11>(0h401)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _toint_ieee_unrecoded_expOut_T_8 = tail(_toint_ieee_unrecoded_expOut_T_7, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _toint_ieee_unrecoded_expOut_T_9 = mux(toint_ieee_unrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 56:16] node _toint_ieee_unrecoded_expOut_T_10 = or(toint_ieee_unrecoded_rawIn_1.isNaN, toint_ieee_unrecoded_rawIn_1.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:44] node _toint_ieee_unrecoded_expOut_T_11 = mux(_toint_ieee_unrecoded_expOut_T_10, UInt<11>(0h7ff), UInt<11>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:21] node toint_ieee_unrecoded_expOut_1 = or(_toint_ieee_unrecoded_expOut_T_9, _toint_ieee_unrecoded_expOut_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:15] node _toint_ieee_unrecoded_fractOut_T_2 = bits(toint_ieee_unrecoded_rawIn_1.sig, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:48] node _toint_ieee_unrecoded_fractOut_T_3 = mux(toint_ieee_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:20] node toint_ieee_unrecoded_fractOut_1 = mux(toint_ieee_unrecoded_isSubnormal_1, toint_ieee_unrecoded_denormFract_1, _toint_ieee_unrecoded_fractOut_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 62:16] node toint_ieee_unrecoded_hi_1 = cat(toint_ieee_unrecoded_rawIn_1.sign, toint_ieee_unrecoded_expOut_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node toint_ieee_unrecoded_1 = cat(toint_ieee_unrecoded_hi_1, toint_ieee_unrecoded_fractOut_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node _toint_ieee_prevRecoded_T_3 = bits(in.in1, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 442:10] node _toint_ieee_prevRecoded_T_4 = bits(in.in1, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 443:10] node _toint_ieee_prevRecoded_T_5 = bits(in.in1, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 444:10] node toint_ieee_prevRecoded_hi_1 = cat(_toint_ieee_prevRecoded_T_3, _toint_ieee_prevRecoded_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 441:28] node toint_ieee_prevRecoded_1 = cat(toint_ieee_prevRecoded_hi_1, _toint_ieee_prevRecoded_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 441:28] node toint_ieee_prevUnrecoded_rawIn_exp_1 = bits(toint_ieee_prevRecoded_1, 31, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _toint_ieee_prevUnrecoded_rawIn_isZero_T_1 = bits(toint_ieee_prevUnrecoded_rawIn_exp_1, 8, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node toint_ieee_prevUnrecoded_rawIn_isZero_1 = eq(_toint_ieee_prevUnrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _toint_ieee_prevUnrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_prevUnrecoded_rawIn_exp_1, 8, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node toint_ieee_prevUnrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_prevUnrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire toint_ieee_prevUnrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_prevUnrecoded_rawIn_exp_1, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_prevUnrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect toint_ieee_prevUnrecoded_rawIn_1.isNaN, _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_prevUnrecoded_rawIn_exp_1, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_prevUnrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_prevUnrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect toint_ieee_prevUnrecoded_rawIn_1.isInf, _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_5 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect toint_ieee_prevUnrecoded_rawIn_1.isZero, toint_ieee_prevUnrecoded_rawIn_isZero_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _toint_ieee_prevUnrecoded_rawIn_out_sign_T_1 = bits(toint_ieee_prevRecoded_1, 32, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect toint_ieee_prevUnrecoded_rawIn_1.sign, _toint_ieee_prevUnrecoded_rawIn_out_sign_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _toint_ieee_prevUnrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_prevUnrecoded_rawIn_exp_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect toint_ieee_prevUnrecoded_rawIn_1.sExp, _toint_ieee_prevUnrecoded_rawIn_out_sExp_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _toint_ieee_prevUnrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_prevUnrecoded_rawIn_isZero_1, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _toint_ieee_prevUnrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_rawIn_out_sig_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _toint_ieee_prevUnrecoded_rawIn_out_sig_T_6 = bits(toint_ieee_prevRecoded_1, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _toint_ieee_prevUnrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_prevUnrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_rawIn_out_sig_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect toint_ieee_prevUnrecoded_rawIn_1.sig, _toint_ieee_prevUnrecoded_rawIn_out_sig_T_7 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node toint_ieee_prevUnrecoded_isSubnormal_1 = lt(toint_ieee_prevUnrecoded_rawIn_1.sExp, asSInt(UInt<9>(0h82))) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 51:38] node _toint_ieee_prevUnrecoded_denormShiftDist_T_2 = bits(toint_ieee_prevUnrecoded_rawIn_1.sExp, 4, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:47] node _toint_ieee_prevUnrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_denormShiftDist_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node toint_ieee_prevUnrecoded_denormShiftDist_1 = tail(_toint_ieee_prevUnrecoded_denormShiftDist_T_3, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node _toint_ieee_prevUnrecoded_denormFract_T_2 = shr(toint_ieee_prevUnrecoded_rawIn_1.sig, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:38] node _toint_ieee_prevUnrecoded_denormFract_T_3 = dshr(_toint_ieee_prevUnrecoded_denormFract_T_2, toint_ieee_prevUnrecoded_denormShiftDist_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:42] node toint_ieee_prevUnrecoded_denormFract_1 = bits(_toint_ieee_prevUnrecoded_denormFract_T_3, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:60] node _toint_ieee_prevUnrecoded_expOut_T_6 = bits(toint_ieee_prevUnrecoded_rawIn_1.sExp, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:27] node _toint_ieee_prevUnrecoded_expOut_T_7 = sub(_toint_ieee_prevUnrecoded_expOut_T_6, UInt<8>(0h81)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _toint_ieee_prevUnrecoded_expOut_T_8 = tail(_toint_ieee_prevUnrecoded_expOut_T_7, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _toint_ieee_prevUnrecoded_expOut_T_9 = mux(toint_ieee_prevUnrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_prevUnrecoded_expOut_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 56:16] node _toint_ieee_prevUnrecoded_expOut_T_10 = or(toint_ieee_prevUnrecoded_rawIn_1.isNaN, toint_ieee_prevUnrecoded_rawIn_1.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:44] node _toint_ieee_prevUnrecoded_expOut_T_11 = mux(_toint_ieee_prevUnrecoded_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:21] node toint_ieee_prevUnrecoded_expOut_1 = or(_toint_ieee_prevUnrecoded_expOut_T_9, _toint_ieee_prevUnrecoded_expOut_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:15] node _toint_ieee_prevUnrecoded_fractOut_T_2 = bits(toint_ieee_prevUnrecoded_rawIn_1.sig, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:48] node _toint_ieee_prevUnrecoded_fractOut_T_3 = mux(toint_ieee_prevUnrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_fractOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:20] node toint_ieee_prevUnrecoded_fractOut_1 = mux(toint_ieee_prevUnrecoded_isSubnormal_1, toint_ieee_prevUnrecoded_denormFract_1, _toint_ieee_prevUnrecoded_fractOut_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 62:16] node toint_ieee_prevUnrecoded_hi_1 = cat(toint_ieee_prevUnrecoded_rawIn_1.sign, toint_ieee_prevUnrecoded_expOut_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node toint_ieee_prevUnrecoded_1 = cat(toint_ieee_prevUnrecoded_hi_1, toint_ieee_prevUnrecoded_fractOut_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node _toint_ieee_T_8 = shr(toint_ieee_unrecoded_1, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:21] node _toint_ieee_T_9 = bits(in.in1, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node _toint_ieee_T_10 = andr(_toint_ieee_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node _toint_ieee_T_11 = bits(toint_ieee_unrecoded_1, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:81] node _toint_ieee_T_12 = mux(_toint_ieee_T_10, toint_ieee_prevUnrecoded_1, _toint_ieee_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:44] node _toint_ieee_T_13 = cat(_toint_ieee_T_8, _toint_ieee_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:10] node _toint_ieee_T_14 = bits(_toint_ieee_T_13, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 476:109] node _toint_ieee_truncIdx_T = or(in.typeTagOut, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:21] node toint_ieee_truncIdx = bits(_toint_ieee_truncIdx_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:47] node _toint_ieee_T_15 = eq(toint_ieee_truncIdx, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node toint_ieee = mux(_toint_ieee_T_15, _toint_ieee_T_14, _toint_ieee_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] wire toint : UInt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 478:26] connect toint, toint_ieee @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 478:26] node _intType_T = bits(in.fmt, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 479:35] wire intType : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 479:28] connect intType, _intType_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 479:28] node io_out_bits_store_unrecoded_rawIn_exp = bits(in.in1, 63, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _io_out_bits_store_unrecoded_rawIn_isZero_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 11, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node io_out_bits_store_unrecoded_rawIn_isZero = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _io_out_bits_store_unrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node io_out_bits_store_unrecoded_rawIn_isSpecial = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire io_out_bits_store_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_unrecoded_rawIn_isSpecial, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect io_out_bits_store_unrecoded_rawIn.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _io_out_bits_store_unrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_unrecoded_rawIn_isSpecial, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect io_out_bits_store_unrecoded_rawIn.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect io_out_bits_store_unrecoded_rawIn.isZero, io_out_bits_store_unrecoded_rawIn_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _io_out_bits_store_unrecoded_rawIn_out_sign_T = bits(in.in1, 64, 64) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect io_out_bits_store_unrecoded_rawIn.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _io_out_bits_store_unrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_unrecoded_rawIn_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect io_out_bits_store_unrecoded_rawIn.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _io_out_bits_store_unrecoded_rawIn_out_sig_T = eq(io_out_bits_store_unrecoded_rawIn_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _io_out_bits_store_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _io_out_bits_store_unrecoded_rawIn_out_sig_T_2 = bits(in.in1, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_unrecoded_rawIn_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect io_out_bits_store_unrecoded_rawIn.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node io_out_bits_store_unrecoded_isSubnormal = lt(io_out_bits_store_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 51:38] node _io_out_bits_store_unrecoded_denormShiftDist_T = bits(io_out_bits_store_unrecoded_rawIn.sExp, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:47] node _io_out_bits_store_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node io_out_bits_store_unrecoded_denormShiftDist = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node _io_out_bits_store_unrecoded_denormFract_T = shr(io_out_bits_store_unrecoded_rawIn.sig, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:38] node _io_out_bits_store_unrecoded_denormFract_T_1 = dshr(_io_out_bits_store_unrecoded_denormFract_T, io_out_bits_store_unrecoded_denormShiftDist) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:42] node io_out_bits_store_unrecoded_denormFract = bits(_io_out_bits_store_unrecoded_denormFract_T_1, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:60] node _io_out_bits_store_unrecoded_expOut_T = bits(io_out_bits_store_unrecoded_rawIn.sExp, 10, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:27] node _io_out_bits_store_unrecoded_expOut_T_1 = sub(_io_out_bits_store_unrecoded_expOut_T, UInt<11>(0h401)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _io_out_bits_store_unrecoded_expOut_T_2 = tail(_io_out_bits_store_unrecoded_expOut_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _io_out_bits_store_unrecoded_expOut_T_3 = mux(io_out_bits_store_unrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 56:16] node _io_out_bits_store_unrecoded_expOut_T_4 = or(io_out_bits_store_unrecoded_rawIn.isNaN, io_out_bits_store_unrecoded_rawIn.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:44] node _io_out_bits_store_unrecoded_expOut_T_5 = mux(_io_out_bits_store_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:21] node io_out_bits_store_unrecoded_expOut = or(_io_out_bits_store_unrecoded_expOut_T_3, _io_out_bits_store_unrecoded_expOut_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:15] node _io_out_bits_store_unrecoded_fractOut_T = bits(io_out_bits_store_unrecoded_rawIn.sig, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:48] node _io_out_bits_store_unrecoded_fractOut_T_1 = mux(io_out_bits_store_unrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:20] node io_out_bits_store_unrecoded_fractOut = mux(io_out_bits_store_unrecoded_isSubnormal, io_out_bits_store_unrecoded_denormFract, _io_out_bits_store_unrecoded_fractOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 62:16] node io_out_bits_store_unrecoded_hi = cat(io_out_bits_store_unrecoded_rawIn.sign, io_out_bits_store_unrecoded_expOut) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node io_out_bits_store_unrecoded = cat(io_out_bits_store_unrecoded_hi, io_out_bits_store_unrecoded_fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node _io_out_bits_store_prevRecoded_T = bits(in.in1, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 442:10] node _io_out_bits_store_prevRecoded_T_1 = bits(in.in1, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 443:10] node _io_out_bits_store_prevRecoded_T_2 = bits(in.in1, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 444:10] node io_out_bits_store_prevRecoded_hi = cat(_io_out_bits_store_prevRecoded_T, _io_out_bits_store_prevRecoded_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 441:28] node io_out_bits_store_prevRecoded = cat(io_out_bits_store_prevRecoded_hi, _io_out_bits_store_prevRecoded_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 441:28] node io_out_bits_store_prevUnrecoded_rawIn_exp = bits(io_out_bits_store_prevRecoded, 31, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _io_out_bits_store_prevUnrecoded_rawIn_isZero_T = bits(io_out_bits_store_prevUnrecoded_rawIn_exp, 8, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node io_out_bits_store_prevUnrecoded_rawIn_isZero = eq(_io_out_bits_store_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _io_out_bits_store_prevUnrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_prevUnrecoded_rawIn_exp, 8, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node io_out_bits_store_prevUnrecoded_rawIn_isSpecial = eq(_io_out_bits_store_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire io_out_bits_store_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_prevUnrecoded_rawIn_exp, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_prevUnrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect io_out_bits_store_prevUnrecoded_rawIn.isNaN, _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_prevUnrecoded_rawIn_exp, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_prevUnrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect io_out_bits_store_prevUnrecoded_rawIn.isInf, _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect io_out_bits_store_prevUnrecoded_rawIn.isZero, io_out_bits_store_prevUnrecoded_rawIn_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _io_out_bits_store_prevUnrecoded_rawIn_out_sign_T = bits(io_out_bits_store_prevRecoded, 32, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect io_out_bits_store_prevUnrecoded_rawIn.sign, _io_out_bits_store_prevUnrecoded_rawIn_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _io_out_bits_store_prevUnrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_prevUnrecoded_rawIn_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect io_out_bits_store_prevUnrecoded_rawIn.sExp, _io_out_bits_store_prevUnrecoded_rawIn_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T = eq(io_out_bits_store_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_2 = bits(io_out_bits_store_prevRecoded, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect io_out_bits_store_prevUnrecoded_rawIn.sig, _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node io_out_bits_store_prevUnrecoded_isSubnormal = lt(io_out_bits_store_prevUnrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 51:38] node _io_out_bits_store_prevUnrecoded_denormShiftDist_T = bits(io_out_bits_store_prevUnrecoded_rawIn.sExp, 4, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:47] node _io_out_bits_store_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_denormShiftDist_T) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node io_out_bits_store_prevUnrecoded_denormShiftDist = tail(_io_out_bits_store_prevUnrecoded_denormShiftDist_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node _io_out_bits_store_prevUnrecoded_denormFract_T = shr(io_out_bits_store_prevUnrecoded_rawIn.sig, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:38] node _io_out_bits_store_prevUnrecoded_denormFract_T_1 = dshr(_io_out_bits_store_prevUnrecoded_denormFract_T, io_out_bits_store_prevUnrecoded_denormShiftDist) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:42] node io_out_bits_store_prevUnrecoded_denormFract = bits(_io_out_bits_store_prevUnrecoded_denormFract_T_1, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:60] node _io_out_bits_store_prevUnrecoded_expOut_T = bits(io_out_bits_store_prevUnrecoded_rawIn.sExp, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:27] node _io_out_bits_store_prevUnrecoded_expOut_T_1 = sub(_io_out_bits_store_prevUnrecoded_expOut_T, UInt<8>(0h81)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _io_out_bits_store_prevUnrecoded_expOut_T_2 = tail(_io_out_bits_store_prevUnrecoded_expOut_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _io_out_bits_store_prevUnrecoded_expOut_T_3 = mux(io_out_bits_store_prevUnrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_expOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 56:16] node _io_out_bits_store_prevUnrecoded_expOut_T_4 = or(io_out_bits_store_prevUnrecoded_rawIn.isNaN, io_out_bits_store_prevUnrecoded_rawIn.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:44] node _io_out_bits_store_prevUnrecoded_expOut_T_5 = mux(_io_out_bits_store_prevUnrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:21] node io_out_bits_store_prevUnrecoded_expOut = or(_io_out_bits_store_prevUnrecoded_expOut_T_3, _io_out_bits_store_prevUnrecoded_expOut_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:15] node _io_out_bits_store_prevUnrecoded_fractOut_T = bits(io_out_bits_store_prevUnrecoded_rawIn.sig, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:48] node _io_out_bits_store_prevUnrecoded_fractOut_T_1 = mux(io_out_bits_store_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_fractOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:20] node io_out_bits_store_prevUnrecoded_fractOut = mux(io_out_bits_store_prevUnrecoded_isSubnormal, io_out_bits_store_prevUnrecoded_denormFract, _io_out_bits_store_prevUnrecoded_fractOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 62:16] node io_out_bits_store_prevUnrecoded_hi = cat(io_out_bits_store_prevUnrecoded_rawIn.sign, io_out_bits_store_prevUnrecoded_expOut) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node io_out_bits_store_prevUnrecoded = cat(io_out_bits_store_prevUnrecoded_hi, io_out_bits_store_prevUnrecoded_fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node _io_out_bits_store_T = shr(io_out_bits_store_unrecoded, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:21] node _io_out_bits_store_T_1 = bits(in.in1, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node _io_out_bits_store_T_2 = andr(_io_out_bits_store_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node _io_out_bits_store_T_3 = bits(io_out_bits_store_unrecoded, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:81] node _io_out_bits_store_T_4 = mux(_io_out_bits_store_T_2, io_out_bits_store_prevUnrecoded, _io_out_bits_store_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:44] node _io_out_bits_store_T_5 = cat(_io_out_bits_store_T, _io_out_bits_store_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:10] node _io_out_bits_store_T_6 = bits(_io_out_bits_store_T_5, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 480:82] node _io_out_bits_store_T_7 = cat(_io_out_bits_store_T_6, _io_out_bits_store_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 480:49] node io_out_bits_store_unrecoded_rawIn_exp_1 = bits(in.in1, 63, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _io_out_bits_store_unrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 11, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node io_out_bits_store_unrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _io_out_bits_store_unrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node io_out_bits_store_unrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire io_out_bits_store_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect io_out_bits_store_unrecoded_rawIn_1.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect io_out_bits_store_unrecoded_rawIn_1.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect io_out_bits_store_unrecoded_rawIn_1.isZero, io_out_bits_store_unrecoded_rawIn_isZero_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 = bits(in.in1, 64, 64) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect io_out_bits_store_unrecoded_rawIn_1.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_unrecoded_rawIn_exp_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect io_out_bits_store_unrecoded_rawIn_1.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _io_out_bits_store_unrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _io_out_bits_store_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _io_out_bits_store_unrecoded_rawIn_out_sig_T_6 = bits(in.in1, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_unrecoded_rawIn_out_sig_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect io_out_bits_store_unrecoded_rawIn_1.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node io_out_bits_store_unrecoded_isSubnormal_1 = lt(io_out_bits_store_unrecoded_rawIn_1.sExp, asSInt(UInt<12>(0h402))) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 51:38] node _io_out_bits_store_unrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_unrecoded_rawIn_1.sExp, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:47] node _io_out_bits_store_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node io_out_bits_store_unrecoded_denormShiftDist_1 = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_3, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node _io_out_bits_store_unrecoded_denormFract_T_2 = shr(io_out_bits_store_unrecoded_rawIn_1.sig, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:38] node _io_out_bits_store_unrecoded_denormFract_T_3 = dshr(_io_out_bits_store_unrecoded_denormFract_T_2, io_out_bits_store_unrecoded_denormShiftDist_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:42] node io_out_bits_store_unrecoded_denormFract_1 = bits(_io_out_bits_store_unrecoded_denormFract_T_3, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:60] node _io_out_bits_store_unrecoded_expOut_T_6 = bits(io_out_bits_store_unrecoded_rawIn_1.sExp, 10, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:27] node _io_out_bits_store_unrecoded_expOut_T_7 = sub(_io_out_bits_store_unrecoded_expOut_T_6, UInt<11>(0h401)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _io_out_bits_store_unrecoded_expOut_T_8 = tail(_io_out_bits_store_unrecoded_expOut_T_7, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _io_out_bits_store_unrecoded_expOut_T_9 = mux(io_out_bits_store_unrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 56:16] node _io_out_bits_store_unrecoded_expOut_T_10 = or(io_out_bits_store_unrecoded_rawIn_1.isNaN, io_out_bits_store_unrecoded_rawIn_1.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:44] node _io_out_bits_store_unrecoded_expOut_T_11 = mux(_io_out_bits_store_unrecoded_expOut_T_10, UInt<11>(0h7ff), UInt<11>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:21] node io_out_bits_store_unrecoded_expOut_1 = or(_io_out_bits_store_unrecoded_expOut_T_9, _io_out_bits_store_unrecoded_expOut_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:15] node _io_out_bits_store_unrecoded_fractOut_T_2 = bits(io_out_bits_store_unrecoded_rawIn_1.sig, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:48] node _io_out_bits_store_unrecoded_fractOut_T_3 = mux(io_out_bits_store_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:20] node io_out_bits_store_unrecoded_fractOut_1 = mux(io_out_bits_store_unrecoded_isSubnormal_1, io_out_bits_store_unrecoded_denormFract_1, _io_out_bits_store_unrecoded_fractOut_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 62:16] node io_out_bits_store_unrecoded_hi_1 = cat(io_out_bits_store_unrecoded_rawIn_1.sign, io_out_bits_store_unrecoded_expOut_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node io_out_bits_store_unrecoded_1 = cat(io_out_bits_store_unrecoded_hi_1, io_out_bits_store_unrecoded_fractOut_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node _io_out_bits_store_prevRecoded_T_3 = bits(in.in1, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 442:10] node _io_out_bits_store_prevRecoded_T_4 = bits(in.in1, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 443:10] node _io_out_bits_store_prevRecoded_T_5 = bits(in.in1, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 444:10] node io_out_bits_store_prevRecoded_hi_1 = cat(_io_out_bits_store_prevRecoded_T_3, _io_out_bits_store_prevRecoded_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 441:28] node io_out_bits_store_prevRecoded_1 = cat(io_out_bits_store_prevRecoded_hi_1, _io_out_bits_store_prevRecoded_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 441:28] node io_out_bits_store_prevUnrecoded_rawIn_exp_1 = bits(io_out_bits_store_prevRecoded_1, 31, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _io_out_bits_store_prevUnrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_prevUnrecoded_rawIn_exp_1, 8, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node io_out_bits_store_prevUnrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_prevUnrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _io_out_bits_store_prevUnrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_prevUnrecoded_rawIn_exp_1, 8, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node io_out_bits_store_prevUnrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_prevUnrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire io_out_bits_store_prevUnrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_prevUnrecoded_rawIn_exp_1, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_prevUnrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect io_out_bits_store_prevUnrecoded_rawIn_1.isNaN, _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_prevUnrecoded_rawIn_exp_1, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_prevUnrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect io_out_bits_store_prevUnrecoded_rawIn_1.isInf, _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_5 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect io_out_bits_store_prevUnrecoded_rawIn_1.isZero, io_out_bits_store_prevUnrecoded_rawIn_isZero_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _io_out_bits_store_prevUnrecoded_rawIn_out_sign_T_1 = bits(io_out_bits_store_prevRecoded_1, 32, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect io_out_bits_store_prevUnrecoded_rawIn_1.sign, _io_out_bits_store_prevUnrecoded_rawIn_out_sign_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _io_out_bits_store_prevUnrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_prevUnrecoded_rawIn_exp_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect io_out_bits_store_prevUnrecoded_rawIn_1.sExp, _io_out_bits_store_prevUnrecoded_rawIn_out_sExp_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_prevUnrecoded_rawIn_isZero_1, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_6 = bits(io_out_bits_store_prevRecoded_1, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect io_out_bits_store_prevUnrecoded_rawIn_1.sig, _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_7 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node io_out_bits_store_prevUnrecoded_isSubnormal_1 = lt(io_out_bits_store_prevUnrecoded_rawIn_1.sExp, asSInt(UInt<9>(0h82))) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 51:38] node _io_out_bits_store_prevUnrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_prevUnrecoded_rawIn_1.sExp, 4, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:47] node _io_out_bits_store_prevUnrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_denormShiftDist_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node io_out_bits_store_prevUnrecoded_denormShiftDist_1 = tail(_io_out_bits_store_prevUnrecoded_denormShiftDist_T_3, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node _io_out_bits_store_prevUnrecoded_denormFract_T_2 = shr(io_out_bits_store_prevUnrecoded_rawIn_1.sig, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:38] node _io_out_bits_store_prevUnrecoded_denormFract_T_3 = dshr(_io_out_bits_store_prevUnrecoded_denormFract_T_2, io_out_bits_store_prevUnrecoded_denormShiftDist_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:42] node io_out_bits_store_prevUnrecoded_denormFract_1 = bits(_io_out_bits_store_prevUnrecoded_denormFract_T_3, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:60] node _io_out_bits_store_prevUnrecoded_expOut_T_6 = bits(io_out_bits_store_prevUnrecoded_rawIn_1.sExp, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:27] node _io_out_bits_store_prevUnrecoded_expOut_T_7 = sub(_io_out_bits_store_prevUnrecoded_expOut_T_6, UInt<8>(0h81)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _io_out_bits_store_prevUnrecoded_expOut_T_8 = tail(_io_out_bits_store_prevUnrecoded_expOut_T_7, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _io_out_bits_store_prevUnrecoded_expOut_T_9 = mux(io_out_bits_store_prevUnrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_expOut_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 56:16] node _io_out_bits_store_prevUnrecoded_expOut_T_10 = or(io_out_bits_store_prevUnrecoded_rawIn_1.isNaN, io_out_bits_store_prevUnrecoded_rawIn_1.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:44] node _io_out_bits_store_prevUnrecoded_expOut_T_11 = mux(_io_out_bits_store_prevUnrecoded_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:21] node io_out_bits_store_prevUnrecoded_expOut_1 = or(_io_out_bits_store_prevUnrecoded_expOut_T_9, _io_out_bits_store_prevUnrecoded_expOut_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:15] node _io_out_bits_store_prevUnrecoded_fractOut_T_2 = bits(io_out_bits_store_prevUnrecoded_rawIn_1.sig, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:48] node _io_out_bits_store_prevUnrecoded_fractOut_T_3 = mux(io_out_bits_store_prevUnrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_fractOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:20] node io_out_bits_store_prevUnrecoded_fractOut_1 = mux(io_out_bits_store_prevUnrecoded_isSubnormal_1, io_out_bits_store_prevUnrecoded_denormFract_1, _io_out_bits_store_prevUnrecoded_fractOut_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 62:16] node io_out_bits_store_prevUnrecoded_hi_1 = cat(io_out_bits_store_prevUnrecoded_rawIn_1.sign, io_out_bits_store_prevUnrecoded_expOut_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node io_out_bits_store_prevUnrecoded_1 = cat(io_out_bits_store_prevUnrecoded_hi_1, io_out_bits_store_prevUnrecoded_fractOut_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node _io_out_bits_store_T_8 = shr(io_out_bits_store_unrecoded_1, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:21] node _io_out_bits_store_T_9 = bits(in.in1, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node _io_out_bits_store_T_10 = andr(_io_out_bits_store_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node _io_out_bits_store_T_11 = bits(io_out_bits_store_unrecoded_1, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:81] node _io_out_bits_store_T_12 = mux(_io_out_bits_store_T_10, io_out_bits_store_prevUnrecoded_1, _io_out_bits_store_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:44] node _io_out_bits_store_T_13 = cat(_io_out_bits_store_T_8, _io_out_bits_store_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:10] node _io_out_bits_store_T_14 = bits(_io_out_bits_store_T_13, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 480:82] node _io_out_bits_store_truncIdx_T = or(in.typeTagOut, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:21] node io_out_bits_store_truncIdx = bits(_io_out_bits_store_truncIdx_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:47] node _io_out_bits_store_T_15 = eq(io_out_bits_store_truncIdx, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_bits_store_T_16 = mux(_io_out_bits_store_T_15, _io_out_bits_store_T_14, _io_out_bits_store_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] connect io.out.bits.store, _io_out_bits_store_T_16 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 480:21] node _io_out_bits_toint_T = bits(toint, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 481:59] node _io_out_bits_toint_T_1 = bits(_io_out_bits_toint_T, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:38] node _io_out_bits_toint_T_2 = mux(_io_out_bits_toint_T_1, UInt<32>(0hffffffff), UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:20] node _io_out_bits_toint_T_3 = cat(_io_out_bits_toint_T_2, _io_out_bits_toint_T) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:15] node _io_out_bits_toint_T_4 = bits(toint, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 481:59] node _io_out_bits_toint_T_5 = eq(intType, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_bits_toint_T_6 = mux(_io_out_bits_toint_T_5, _io_out_bits_toint_T_4, _io_out_bits_toint_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] connect io.out.bits.toint, _io_out_bits_toint_T_6 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 481:21] connect io.out.bits.exc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 482:19] node _T = bits(in.rm, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 484:14] when _T : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 484:19] node classify_out_sign = bits(in.in1, 64, 64) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 274:17] node classify_out_fractIn = bits(in.in1, 51, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 275:20] node classify_out_expIn = bits(in.in1, 63, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 276:18] node _classify_out_fractOut_T = shl(classify_out_fractIn, 24) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:28] node classify_out_fractOut = shr(_classify_out_fractOut_T, 53) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:38] node classify_out_expOut_expCode = bits(classify_out_expIn, 11, 9) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 279:26] node _classify_out_expOut_commonCase_T = add(classify_out_expIn, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _classify_out_expOut_commonCase_T_1 = tail(_classify_out_expOut_commonCase_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _classify_out_expOut_commonCase_T_2 = sub(_classify_out_expOut_commonCase_T_1, UInt<12>(0h800)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node classify_out_expOut_commonCase = tail(_classify_out_expOut_commonCase_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node _classify_out_expOut_T = eq(classify_out_expOut_expCode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:19] node _classify_out_expOut_T_1 = geq(classify_out_expOut_expCode, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:38] node _classify_out_expOut_T_2 = or(_classify_out_expOut_T, _classify_out_expOut_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:27] node _classify_out_expOut_T_3 = bits(classify_out_expOut_commonCase, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:69] node _classify_out_expOut_T_4 = cat(classify_out_expOut_expCode, _classify_out_expOut_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:49] node _classify_out_expOut_T_5 = bits(classify_out_expOut_commonCase, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:97] node classify_out_expOut = mux(_classify_out_expOut_T_2, _classify_out_expOut_T_4, _classify_out_expOut_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:10] node classify_out_hi = cat(classify_out_sign, classify_out_expOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node _classify_out_T = cat(classify_out_hi, classify_out_fractOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node classify_out_sign_1 = bits(_classify_out_T, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 253:17] node classify_out_code = bits(_classify_out_T, 31, 29) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 254:17] node classify_out_codeHi = bits(classify_out_code, 2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 255:22] node classify_out_isSpecial = eq(classify_out_codeHi, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 256:28] node _classify_out_isHighSubnormalIn_T = bits(_classify_out_T, 29, 23) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 258:30] node classify_out_isHighSubnormalIn = lt(_classify_out_isHighSubnormalIn_T, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 258:55] node _classify_out_isSubnormal_T = eq(classify_out_code, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 259:28] node _classify_out_isSubnormal_T_1 = eq(classify_out_codeHi, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 259:46] node _classify_out_isSubnormal_T_2 = and(_classify_out_isSubnormal_T_1, classify_out_isHighSubnormalIn) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 259:54] node classify_out_isSubnormal = or(_classify_out_isSubnormal_T, _classify_out_isSubnormal_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 259:36] node _classify_out_isNormal_T = eq(classify_out_codeHi, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 260:27] node _classify_out_isNormal_T_1 = eq(classify_out_isHighSubnormalIn, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 260:38] node _classify_out_isNormal_T_2 = and(_classify_out_isNormal_T, _classify_out_isNormal_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 260:35] node _classify_out_isNormal_T_3 = eq(classify_out_codeHi, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 260:67] node classify_out_isNormal = or(_classify_out_isNormal_T_2, _classify_out_isNormal_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 260:57] node classify_out_isZero = eq(classify_out_code, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 261:23] node _classify_out_isInf_T = bits(classify_out_code, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 262:35] node _classify_out_isInf_T_1 = eq(_classify_out_isInf_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 262:30] node classify_out_isInf = and(classify_out_isSpecial, _classify_out_isInf_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 262:27] node classify_out_isNaN = andr(classify_out_code) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 263:22] node _classify_out_isSNaN_T = bits(_classify_out_T, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 264:29] node _classify_out_isSNaN_T_1 = eq(_classify_out_isSNaN_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 264:27] node classify_out_isSNaN = and(classify_out_isNaN, _classify_out_isSNaN_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 264:24] node _classify_out_isQNaN_T = bits(_classify_out_T, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 265:28] node classify_out_isQNaN = and(classify_out_isNaN, _classify_out_isQNaN_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 265:24] node _classify_out_T_1 = eq(classify_out_sign_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:34] node _classify_out_T_2 = and(classify_out_isInf, _classify_out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:31] node _classify_out_T_3 = eq(classify_out_sign_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:53] node _classify_out_T_4 = and(classify_out_isNormal, _classify_out_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:50] node _classify_out_T_5 = eq(classify_out_sign_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 268:24] node _classify_out_T_6 = and(classify_out_isSubnormal, _classify_out_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 268:21] node _classify_out_T_7 = eq(classify_out_sign_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 268:41] node _classify_out_T_8 = and(classify_out_isZero, _classify_out_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 268:38] node _classify_out_T_9 = and(classify_out_isZero, classify_out_sign_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 268:55] node _classify_out_T_10 = and(classify_out_isSubnormal, classify_out_sign_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 269:21] node _classify_out_T_11 = and(classify_out_isNormal, classify_out_sign_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 269:39] node _classify_out_T_12 = and(classify_out_isInf, classify_out_sign_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 269:54] node classify_out_lo_lo = cat(_classify_out_T_11, _classify_out_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:8] node classify_out_lo_hi_hi = cat(_classify_out_T_8, _classify_out_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:8] node classify_out_lo_hi = cat(classify_out_lo_hi_hi, _classify_out_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:8] node classify_out_lo = cat(classify_out_lo_hi, classify_out_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:8] node classify_out_hi_lo = cat(_classify_out_T_4, _classify_out_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:8] node classify_out_hi_hi_hi = cat(classify_out_isQNaN, classify_out_isSNaN) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:8] node classify_out_hi_hi = cat(classify_out_hi_hi_hi, _classify_out_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:8] node classify_out_hi_1 = cat(classify_out_hi_hi, classify_out_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:8] node _classify_out_T_13 = cat(classify_out_hi_1, classify_out_lo) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:8] node classify_out_sign_2 = bits(in.in1, 64, 64) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 253:17] node classify_out_code_1 = bits(in.in1, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 254:17] node classify_out_codeHi_1 = bits(classify_out_code_1, 2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 255:22] node classify_out_isSpecial_1 = eq(classify_out_codeHi_1, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 256:28] node _classify_out_isHighSubnormalIn_T_1 = bits(in.in1, 61, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 258:30] node classify_out_isHighSubnormalIn_1 = lt(_classify_out_isHighSubnormalIn_T_1, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 258:55] node _classify_out_isSubnormal_T_3 = eq(classify_out_code_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 259:28] node _classify_out_isSubnormal_T_4 = eq(classify_out_codeHi_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 259:46] node _classify_out_isSubnormal_T_5 = and(_classify_out_isSubnormal_T_4, classify_out_isHighSubnormalIn_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 259:54] node classify_out_isSubnormal_1 = or(_classify_out_isSubnormal_T_3, _classify_out_isSubnormal_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 259:36] node _classify_out_isNormal_T_4 = eq(classify_out_codeHi_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 260:27] node _classify_out_isNormal_T_5 = eq(classify_out_isHighSubnormalIn_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 260:38] node _classify_out_isNormal_T_6 = and(_classify_out_isNormal_T_4, _classify_out_isNormal_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 260:35] node _classify_out_isNormal_T_7 = eq(classify_out_codeHi_1, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 260:67] node classify_out_isNormal_1 = or(_classify_out_isNormal_T_6, _classify_out_isNormal_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 260:57] node classify_out_isZero_1 = eq(classify_out_code_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 261:23] node _classify_out_isInf_T_2 = bits(classify_out_code_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 262:35] node _classify_out_isInf_T_3 = eq(_classify_out_isInf_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 262:30] node classify_out_isInf_1 = and(classify_out_isSpecial_1, _classify_out_isInf_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 262:27] node classify_out_isNaN_1 = andr(classify_out_code_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 263:22] node _classify_out_isSNaN_T_2 = bits(in.in1, 51, 51) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 264:29] node _classify_out_isSNaN_T_3 = eq(_classify_out_isSNaN_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 264:27] node classify_out_isSNaN_1 = and(classify_out_isNaN_1, _classify_out_isSNaN_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 264:24] node _classify_out_isQNaN_T_1 = bits(in.in1, 51, 51) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 265:28] node classify_out_isQNaN_1 = and(classify_out_isNaN_1, _classify_out_isQNaN_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 265:24] node _classify_out_T_14 = eq(classify_out_sign_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:34] node _classify_out_T_15 = and(classify_out_isInf_1, _classify_out_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:31] node _classify_out_T_16 = eq(classify_out_sign_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:53] node _classify_out_T_17 = and(classify_out_isNormal_1, _classify_out_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:50] node _classify_out_T_18 = eq(classify_out_sign_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 268:24] node _classify_out_T_19 = and(classify_out_isSubnormal_1, _classify_out_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 268:21] node _classify_out_T_20 = eq(classify_out_sign_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 268:41] node _classify_out_T_21 = and(classify_out_isZero_1, _classify_out_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 268:38] node _classify_out_T_22 = and(classify_out_isZero_1, classify_out_sign_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 268:55] node _classify_out_T_23 = and(classify_out_isSubnormal_1, classify_out_sign_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 269:21] node _classify_out_T_24 = and(classify_out_isNormal_1, classify_out_sign_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 269:39] node _classify_out_T_25 = and(classify_out_isInf_1, classify_out_sign_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 269:54] node classify_out_lo_lo_1 = cat(_classify_out_T_24, _classify_out_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:8] node classify_out_lo_hi_hi_1 = cat(_classify_out_T_21, _classify_out_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:8] node classify_out_lo_hi_1 = cat(classify_out_lo_hi_hi_1, _classify_out_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:8] node classify_out_lo_1 = cat(classify_out_lo_hi_1, classify_out_lo_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:8] node classify_out_hi_lo_1 = cat(_classify_out_T_17, _classify_out_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:8] node classify_out_hi_hi_hi_1 = cat(classify_out_isQNaN_1, classify_out_isSNaN_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:8] node classify_out_hi_hi_1 = cat(classify_out_hi_hi_hi_1, _classify_out_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:8] node classify_out_hi_2 = cat(classify_out_hi_hi_1, classify_out_hi_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:8] node _classify_out_T_26 = cat(classify_out_hi_2, classify_out_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 267:8] node _classify_out_truncIdx_T = or(in.typeTagOut, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:21] node classify_out_truncIdx = bits(_classify_out_truncIdx_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:47] node _classify_out_T_27 = eq(classify_out_truncIdx, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node classify_out = mux(_classify_out_T_27, _classify_out_T_26, _classify_out_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _toint_T = shr(toint_ieee, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 486:41] node _toint_T_1 = shl(_toint_T, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 486:52] node _toint_T_2 = or(classify_out, _toint_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 486:27] connect toint, _toint_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 486:11] connect intType, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 487:13] when in.wflags : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 490:20] node _toint_T_3 = not(in.rm) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 491:15] node _toint_T_4 = cat(dcmp.io.lt, dcmp.io.eq) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 491:27] node _toint_T_5 = and(_toint_T_3, _toint_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 491:22] node _toint_T_6 = orr(_toint_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 491:53] node _toint_T_7 = shr(toint_ieee, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 491:71] node _toint_T_8 = shl(_toint_T_7, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 491:82] node _toint_T_9 = or(_toint_T_6, _toint_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 491:57] connect toint, _toint_T_9 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 491:11] connect io.out.bits.exc, dcmp.io.exceptionFlags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 492:21] connect intType, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 493:13] node _T_1 = eq(in.ren2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 495:11] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 495:21] node cvtType = bits(in.typ, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect intType, cvtType @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 497:15] inst conv of RecFNToIN @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 498:24] connect conv.clock, clock connect conv.reset, reset connect conv.io.in, in.in1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 499:18] connect conv.io.roundingMode, in.rm @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 500:28] node _conv_io_signedOut_T = bits(in.typ, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 501:35] node _conv_io_signedOut_T_1 = not(_conv_io_signedOut_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 501:28] connect conv.io.signedOut, _conv_io_signedOut_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 501:25] connect toint, conv.io.out @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 502:13] node _io_out_bits_exc_T = bits(conv.io.intExceptionFlags, 2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 503:55] node _io_out_bits_exc_T_1 = orr(_io_out_bits_exc_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 503:62] node _io_out_bits_exc_T_2 = bits(conv.io.intExceptionFlags, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 503:102] node io_out_bits_exc_hi = cat(_io_out_bits_exc_T_1, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 503:29] node _io_out_bits_exc_T_3 = cat(io_out_bits_exc_hi, _io_out_bits_exc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 503:29] connect io.out.bits.exc, _io_out_bits_exc_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 503:23] node _T_2 = eq(cvtType, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 507:23] when _T_2 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 507:32] inst narrow of RecFNToIN_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 508:30] connect narrow.clock, clock connect narrow.reset, reset connect narrow.io.in, in.in1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 509:24] connect narrow.io.roundingMode, in.rm @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 510:34] node _narrow_io_signedOut_T = bits(in.typ, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 511:41] node _narrow_io_signedOut_T_1 = not(_narrow_io_signedOut_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 511:34] connect narrow.io.signedOut, _narrow_io_signedOut_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 511:31] node _excSign_T = bits(in.in1, 64, 64) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 513:31] node _excSign_T_1 = bits(in.in1, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node _excSign_T_2 = andr(_excSign_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node _excSign_T_3 = eq(_excSign_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 513:62] node excSign = and(_excSign_T, _excSign_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 513:59] node _excOut_T = eq(conv.io.signedOut, excSign) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 514:46] node _excOut_T_1 = eq(excSign, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 514:69] node _excOut_T_2 = mux(_excOut_T_1, UInt<31>(0h7fffffff), UInt<31>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 514:63] node excOut = cat(_excOut_T, _excOut_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 514:27] node _invalid_T = bits(conv.io.intExceptionFlags, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 515:50] node _invalid_T_1 = bits(narrow.io.intExceptionFlags, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 515:84] node invalid = or(_invalid_T, _invalid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 515:54] when invalid : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 516:26] node _toint_T_10 = shr(conv.io.out, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 516:53] node _toint_T_11 = cat(_toint_T_10, excOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 516:40] connect toint, _toint_T_11 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 516:34] node _io_out_bits_exc_T_4 = eq(invalid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 517:53] node _io_out_bits_exc_T_5 = bits(conv.io.intExceptionFlags, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 517:90] node _io_out_bits_exc_T_6 = and(_io_out_bits_exc_T_4, _io_out_bits_exc_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 517:62] node io_out_bits_exc_hi_1 = cat(invalid, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 517:33] node _io_out_bits_exc_T_7 = cat(io_out_bits_exc_hi_1, _io_out_bits_exc_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 517:33] connect io.out.bits.exc, _io_out_bits_exc_T_7 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 517:27] connect io.out.valid, valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 523:16] node _io_out_bits_lt_T = asSInt(dcmp.io.a) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 524:46] node _io_out_bits_lt_T_1 = lt(_io_out_bits_lt_T, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 524:53] node _io_out_bits_lt_T_2 = asSInt(dcmp.io.b) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 524:72] node _io_out_bits_lt_T_3 = geq(_io_out_bits_lt_T_2, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 524:79] node _io_out_bits_lt_T_4 = and(_io_out_bits_lt_T_1, _io_out_bits_lt_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 524:59] node _io_out_bits_lt_T_5 = or(dcmp.io.lt, _io_out_bits_lt_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 524:32] connect io.out.bits.lt, _io_out_bits_lt_T_5 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 524:18] connect io.out.bits.in, in @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 525:18] module RoundAnyRawFNToRecFN_1 : @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 48:5] output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 57:16] node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 89:53] node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 90:53] node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 91:53] node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 92:53] node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 93:53] node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 94:53] node _roundMagUp_T = and(roundingMode_min, io.in.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:27] node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:66] node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:63] node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:42] node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0h80))) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 103:25] node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 105:14] node sAdjustedExp = cvt(_sAdjustedExp_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 105:31] node _adjustedSig_T = bits(io.in.sig, 64, 39) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 115:23] node _adjustedSig_T_1 = bits(io.in.sig, 38, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 116:26] node _adjustedSig_T_2 = orr(_adjustedSig_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 116:60] node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 115:66] wire common_expOut : UInt<9> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 121:31] wire common_fractOut : UInt<23> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 122:31] wire common_overflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 123:37] wire common_totalUnderflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 124:37] wire common_underflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 125:37] wire common_inexact : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 126:37] node _roundMask_T = cat(UInt<24>(0h0), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 152:36] node roundMask = cat(_roundMask_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 152:55] node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 161:41] node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 161:53] node _roundPosMask_T = not(shiftedRoundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 162:28] node roundPosMask = and(_roundPosMask_T, roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 162:46] node _roundPosBit_T = and(adjustedSig, roundPosMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 163:40] node roundPosBit = orr(_roundPosBit_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 163:56] node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 164:42] node anyRoundExtra = orr(_anyRoundExtra_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 164:62] node anyRound = or(roundPosBit, anyRoundExtra) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 165:36] node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 168:38] node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 168:67] node _roundIncr_T_2 = and(roundMagUp, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 170:29] node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 169:31] node _roundedSig_T = or(adjustedSig, roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:32] node _roundedSig_T_1 = shr(_roundedSig_T, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:44] node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:49] node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:49] node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 175:30] node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:64] node _roundedSig_T_6 = shr(roundMask, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 176:35] node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:25] node _roundedSig_T_8 = not(_roundedSig_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:21] node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:57] node _roundedSig_T_10 = not(roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:32] node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:30] node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:43] node _roundedSig_T_13 = and(roundingMode_odd, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:42] node _roundedSig_T_14 = shr(roundPosMask, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:67] node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:24] node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:47] node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 172:16] node _sRoundedExp_T = shr(roundedSig, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:54] node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:76] node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:40] node _common_expOut_T = bits(sRoundedExp, 8, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 186:37] connect common_expOut, _common_expOut_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 186:23] node _common_fractOut_T = bits(roundedSig, 23, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 189:27] node _common_fractOut_T_1 = bits(roundedSig, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 190:27] node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 188:16] connect common_fractOut, _common_fractOut_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 187:25] connect common_overflow, UInt<1>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 192:25] connect common_totalUnderflow, UInt<1>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 196:31] node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:45] node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:61] node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:16] node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:44] node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:30] node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:63] node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:70] node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:49] node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 206:38] node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 206:67] node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 208:29] node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 207:46] node _roundCarry_T = bits(roundedSig, 25, 25) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 211:27] node _roundCarry_T_1 = bits(roundedSig, 24, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 212:27] node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 210:16] connect common_underflow, UInt<1>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 214:26] node _common_inexact_T = or(common_totalUnderflow, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 229:49] connect common_inexact, _common_inexact_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 229:24] node isNaNOut = or(io.invalidExc, io.in.isNaN) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 234:34] node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 235:49] node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:22] node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:36] node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:33] node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:64] node commonCase = and(_commonCase_T_2, _commonCase_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:61] node overflow = and(commonCase, common_overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 237:32] node underflow = and(commonCase, common_underflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 238:32] node _inexact_T = and(commonCase, common_inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 239:43] node inexact = or(overflow, _inexact_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 239:28] node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 242:32] node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 242:60] node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:20] node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:60] node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:45] node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 245:42] node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 245:39] node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 247:45] node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 247:32] node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 249:22] node _expOut_T = or(io.in.isZero, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:32] node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:18] node _expOut_T_2 = not(_expOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:14] node _expOut_T_3 = and(common_expOut, _expOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 251:24] node _expOut_T_4 = not(UInt<9>(0h6b)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 257:19] node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 256:18] node _expOut_T_6 = not(_expOut_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 256:14] node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 255:17] node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 260:18] node _expOut_T_9 = not(_expOut_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 260:14] node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 259:17] node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 264:18] node _expOut_T_12 = not(_expOut_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 264:14] node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 263:17] node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 268:16] node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 267:18] node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 272:16] node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 271:15] node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 276:16] node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 275:15] node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 277:16] node expOut = or(_expOut_T_19, _expOut_T_20) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 276:73] node _fractOut_T = or(isNaNOut, io.in.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:22] node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:38] node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 280:16] node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:12] node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 283:13] node fractOut = or(_fractOut_T_3, _fractOut_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 282:11] node _io_out_T = cat(signOut, expOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:23] node _io_out_T_1 = cat(_io_out_T, fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:33] connect io.out, _io_out_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:12] node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:23] node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:41] node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:53] node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:66] connect io.exceptionFlags, _io_exceptionFlags_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 286:23] module INToRecFN : @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 43:7] output io : { flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 45:16] node _intAsRawFloat_sign_T = bits(io.in, 63, 63) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 51:34] node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 51:29] node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 52:31] node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 52:31] node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 52:24] node _intAsRawFloat_extAbsIn_T = cat(UInt<64>(0h0), intAsRawFloat_absIn) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 53:44] node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 63, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 53:53] node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_2 = bits(intAsRawFloat_extAbsIn, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_3 = bits(intAsRawFloat_extAbsIn, 3, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_4 = bits(intAsRawFloat_extAbsIn, 4, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_5 = bits(intAsRawFloat_extAbsIn, 5, 5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_6 = bits(intAsRawFloat_extAbsIn, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_7 = bits(intAsRawFloat_extAbsIn, 7, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_8 = bits(intAsRawFloat_extAbsIn, 8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_9 = bits(intAsRawFloat_extAbsIn, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_10 = bits(intAsRawFloat_extAbsIn, 10, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_11 = bits(intAsRawFloat_extAbsIn, 11, 11) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_12 = bits(intAsRawFloat_extAbsIn, 12, 12) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_13 = bits(intAsRawFloat_extAbsIn, 13, 13) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_14 = bits(intAsRawFloat_extAbsIn, 14, 14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_15 = bits(intAsRawFloat_extAbsIn, 15, 15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_16 = bits(intAsRawFloat_extAbsIn, 16, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_17 = bits(intAsRawFloat_extAbsIn, 17, 17) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_18 = bits(intAsRawFloat_extAbsIn, 18, 18) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_19 = bits(intAsRawFloat_extAbsIn, 19, 19) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_20 = bits(intAsRawFloat_extAbsIn, 20, 20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_21 = bits(intAsRawFloat_extAbsIn, 21, 21) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_22 = bits(intAsRawFloat_extAbsIn, 22, 22) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_23 = bits(intAsRawFloat_extAbsIn, 23, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_24 = bits(intAsRawFloat_extAbsIn, 24, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_25 = bits(intAsRawFloat_extAbsIn, 25, 25) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_26 = bits(intAsRawFloat_extAbsIn, 26, 26) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_27 = bits(intAsRawFloat_extAbsIn, 27, 27) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_28 = bits(intAsRawFloat_extAbsIn, 28, 28) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_29 = bits(intAsRawFloat_extAbsIn, 29, 29) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_30 = bits(intAsRawFloat_extAbsIn, 30, 30) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_31 = bits(intAsRawFloat_extAbsIn, 31, 31) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_32 = bits(intAsRawFloat_extAbsIn, 32, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_33 = bits(intAsRawFloat_extAbsIn, 33, 33) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_34 = bits(intAsRawFloat_extAbsIn, 34, 34) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_35 = bits(intAsRawFloat_extAbsIn, 35, 35) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_36 = bits(intAsRawFloat_extAbsIn, 36, 36) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_37 = bits(intAsRawFloat_extAbsIn, 37, 37) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_38 = bits(intAsRawFloat_extAbsIn, 38, 38) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_39 = bits(intAsRawFloat_extAbsIn, 39, 39) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_40 = bits(intAsRawFloat_extAbsIn, 40, 40) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_41 = bits(intAsRawFloat_extAbsIn, 41, 41) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_42 = bits(intAsRawFloat_extAbsIn, 42, 42) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_43 = bits(intAsRawFloat_extAbsIn, 43, 43) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_44 = bits(intAsRawFloat_extAbsIn, 44, 44) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_45 = bits(intAsRawFloat_extAbsIn, 45, 45) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_46 = bits(intAsRawFloat_extAbsIn, 46, 46) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_47 = bits(intAsRawFloat_extAbsIn, 47, 47) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_48 = bits(intAsRawFloat_extAbsIn, 48, 48) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_49 = bits(intAsRawFloat_extAbsIn, 49, 49) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_50 = bits(intAsRawFloat_extAbsIn, 50, 50) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_51 = bits(intAsRawFloat_extAbsIn, 51, 51) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_52 = bits(intAsRawFloat_extAbsIn, 52, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_53 = bits(intAsRawFloat_extAbsIn, 53, 53) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_54 = bits(intAsRawFloat_extAbsIn, 54, 54) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_55 = bits(intAsRawFloat_extAbsIn, 55, 55) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_56 = bits(intAsRawFloat_extAbsIn, 56, 56) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_57 = bits(intAsRawFloat_extAbsIn, 57, 57) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_58 = bits(intAsRawFloat_extAbsIn, 58, 58) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_59 = bits(intAsRawFloat_extAbsIn, 59, 59) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_60 = bits(intAsRawFloat_extAbsIn, 60, 60) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_61 = bits(intAsRawFloat_extAbsIn, 61, 61) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_62 = bits(intAsRawFloat_extAbsIn, 62, 62) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_63 = bits(intAsRawFloat_extAbsIn, 63, 63) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_64 = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<6>(0h3e), UInt<6>(0h3f)) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_65 = mux(_intAsRawFloat_adjustedNormDist_T_2, UInt<6>(0h3d), _intAsRawFloat_adjustedNormDist_T_64) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_66 = mux(_intAsRawFloat_adjustedNormDist_T_3, UInt<6>(0h3c), _intAsRawFloat_adjustedNormDist_T_65) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_67 = mux(_intAsRawFloat_adjustedNormDist_T_4, UInt<6>(0h3b), _intAsRawFloat_adjustedNormDist_T_66) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_68 = mux(_intAsRawFloat_adjustedNormDist_T_5, UInt<6>(0h3a), _intAsRawFloat_adjustedNormDist_T_67) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_69 = mux(_intAsRawFloat_adjustedNormDist_T_6, UInt<6>(0h39), _intAsRawFloat_adjustedNormDist_T_68) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_70 = mux(_intAsRawFloat_adjustedNormDist_T_7, UInt<6>(0h38), _intAsRawFloat_adjustedNormDist_T_69) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_71 = mux(_intAsRawFloat_adjustedNormDist_T_8, UInt<6>(0h37), _intAsRawFloat_adjustedNormDist_T_70) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_72 = mux(_intAsRawFloat_adjustedNormDist_T_9, UInt<6>(0h36), _intAsRawFloat_adjustedNormDist_T_71) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_73 = mux(_intAsRawFloat_adjustedNormDist_T_10, UInt<6>(0h35), _intAsRawFloat_adjustedNormDist_T_72) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_74 = mux(_intAsRawFloat_adjustedNormDist_T_11, UInt<6>(0h34), _intAsRawFloat_adjustedNormDist_T_73) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_75 = mux(_intAsRawFloat_adjustedNormDist_T_12, UInt<6>(0h33), _intAsRawFloat_adjustedNormDist_T_74) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_76 = mux(_intAsRawFloat_adjustedNormDist_T_13, UInt<6>(0h32), _intAsRawFloat_adjustedNormDist_T_75) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_77 = mux(_intAsRawFloat_adjustedNormDist_T_14, UInt<6>(0h31), _intAsRawFloat_adjustedNormDist_T_76) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_78 = mux(_intAsRawFloat_adjustedNormDist_T_15, UInt<6>(0h30), _intAsRawFloat_adjustedNormDist_T_77) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_79 = mux(_intAsRawFloat_adjustedNormDist_T_16, UInt<6>(0h2f), _intAsRawFloat_adjustedNormDist_T_78) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_80 = mux(_intAsRawFloat_adjustedNormDist_T_17, UInt<6>(0h2e), _intAsRawFloat_adjustedNormDist_T_79) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_81 = mux(_intAsRawFloat_adjustedNormDist_T_18, UInt<6>(0h2d), _intAsRawFloat_adjustedNormDist_T_80) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_82 = mux(_intAsRawFloat_adjustedNormDist_T_19, UInt<6>(0h2c), _intAsRawFloat_adjustedNormDist_T_81) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_83 = mux(_intAsRawFloat_adjustedNormDist_T_20, UInt<6>(0h2b), _intAsRawFloat_adjustedNormDist_T_82) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_84 = mux(_intAsRawFloat_adjustedNormDist_T_21, UInt<6>(0h2a), _intAsRawFloat_adjustedNormDist_T_83) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_85 = mux(_intAsRawFloat_adjustedNormDist_T_22, UInt<6>(0h29), _intAsRawFloat_adjustedNormDist_T_84) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_86 = mux(_intAsRawFloat_adjustedNormDist_T_23, UInt<6>(0h28), _intAsRawFloat_adjustedNormDist_T_85) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_87 = mux(_intAsRawFloat_adjustedNormDist_T_24, UInt<6>(0h27), _intAsRawFloat_adjustedNormDist_T_86) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_88 = mux(_intAsRawFloat_adjustedNormDist_T_25, UInt<6>(0h26), _intAsRawFloat_adjustedNormDist_T_87) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_89 = mux(_intAsRawFloat_adjustedNormDist_T_26, UInt<6>(0h25), _intAsRawFloat_adjustedNormDist_T_88) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_90 = mux(_intAsRawFloat_adjustedNormDist_T_27, UInt<6>(0h24), _intAsRawFloat_adjustedNormDist_T_89) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_91 = mux(_intAsRawFloat_adjustedNormDist_T_28, UInt<6>(0h23), _intAsRawFloat_adjustedNormDist_T_90) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_92 = mux(_intAsRawFloat_adjustedNormDist_T_29, UInt<6>(0h22), _intAsRawFloat_adjustedNormDist_T_91) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_93 = mux(_intAsRawFloat_adjustedNormDist_T_30, UInt<6>(0h21), _intAsRawFloat_adjustedNormDist_T_92) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_94 = mux(_intAsRawFloat_adjustedNormDist_T_31, UInt<6>(0h20), _intAsRawFloat_adjustedNormDist_T_93) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_95 = mux(_intAsRawFloat_adjustedNormDist_T_32, UInt<5>(0h1f), _intAsRawFloat_adjustedNormDist_T_94) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_96 = mux(_intAsRawFloat_adjustedNormDist_T_33, UInt<5>(0h1e), _intAsRawFloat_adjustedNormDist_T_95) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_97 = mux(_intAsRawFloat_adjustedNormDist_T_34, UInt<5>(0h1d), _intAsRawFloat_adjustedNormDist_T_96) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_98 = mux(_intAsRawFloat_adjustedNormDist_T_35, UInt<5>(0h1c), _intAsRawFloat_adjustedNormDist_T_97) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_99 = mux(_intAsRawFloat_adjustedNormDist_T_36, UInt<5>(0h1b), _intAsRawFloat_adjustedNormDist_T_98) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_100 = mux(_intAsRawFloat_adjustedNormDist_T_37, UInt<5>(0h1a), _intAsRawFloat_adjustedNormDist_T_99) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_101 = mux(_intAsRawFloat_adjustedNormDist_T_38, UInt<5>(0h19), _intAsRawFloat_adjustedNormDist_T_100) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_102 = mux(_intAsRawFloat_adjustedNormDist_T_39, UInt<5>(0h18), _intAsRawFloat_adjustedNormDist_T_101) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_103 = mux(_intAsRawFloat_adjustedNormDist_T_40, UInt<5>(0h17), _intAsRawFloat_adjustedNormDist_T_102) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_104 = mux(_intAsRawFloat_adjustedNormDist_T_41, UInt<5>(0h16), _intAsRawFloat_adjustedNormDist_T_103) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_105 = mux(_intAsRawFloat_adjustedNormDist_T_42, UInt<5>(0h15), _intAsRawFloat_adjustedNormDist_T_104) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_106 = mux(_intAsRawFloat_adjustedNormDist_T_43, UInt<5>(0h14), _intAsRawFloat_adjustedNormDist_T_105) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_107 = mux(_intAsRawFloat_adjustedNormDist_T_44, UInt<5>(0h13), _intAsRawFloat_adjustedNormDist_T_106) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_108 = mux(_intAsRawFloat_adjustedNormDist_T_45, UInt<5>(0h12), _intAsRawFloat_adjustedNormDist_T_107) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_109 = mux(_intAsRawFloat_adjustedNormDist_T_46, UInt<5>(0h11), _intAsRawFloat_adjustedNormDist_T_108) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_110 = mux(_intAsRawFloat_adjustedNormDist_T_47, UInt<5>(0h10), _intAsRawFloat_adjustedNormDist_T_109) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_111 = mux(_intAsRawFloat_adjustedNormDist_T_48, UInt<4>(0hf), _intAsRawFloat_adjustedNormDist_T_110) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_112 = mux(_intAsRawFloat_adjustedNormDist_T_49, UInt<4>(0he), _intAsRawFloat_adjustedNormDist_T_111) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_113 = mux(_intAsRawFloat_adjustedNormDist_T_50, UInt<4>(0hd), _intAsRawFloat_adjustedNormDist_T_112) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_114 = mux(_intAsRawFloat_adjustedNormDist_T_51, UInt<4>(0hc), _intAsRawFloat_adjustedNormDist_T_113) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_115 = mux(_intAsRawFloat_adjustedNormDist_T_52, UInt<4>(0hb), _intAsRawFloat_adjustedNormDist_T_114) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_116 = mux(_intAsRawFloat_adjustedNormDist_T_53, UInt<4>(0ha), _intAsRawFloat_adjustedNormDist_T_115) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_117 = mux(_intAsRawFloat_adjustedNormDist_T_54, UInt<4>(0h9), _intAsRawFloat_adjustedNormDist_T_116) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_118 = mux(_intAsRawFloat_adjustedNormDist_T_55, UInt<4>(0h8), _intAsRawFloat_adjustedNormDist_T_117) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_119 = mux(_intAsRawFloat_adjustedNormDist_T_56, UInt<3>(0h7), _intAsRawFloat_adjustedNormDist_T_118) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_120 = mux(_intAsRawFloat_adjustedNormDist_T_57, UInt<3>(0h6), _intAsRawFloat_adjustedNormDist_T_119) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_121 = mux(_intAsRawFloat_adjustedNormDist_T_58, UInt<3>(0h5), _intAsRawFloat_adjustedNormDist_T_120) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_122 = mux(_intAsRawFloat_adjustedNormDist_T_59, UInt<3>(0h4), _intAsRawFloat_adjustedNormDist_T_121) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_123 = mux(_intAsRawFloat_adjustedNormDist_T_60, UInt<2>(0h3), _intAsRawFloat_adjustedNormDist_T_122) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_124 = mux(_intAsRawFloat_adjustedNormDist_T_61, UInt<2>(0h2), _intAsRawFloat_adjustedNormDist_T_123) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_125 = mux(_intAsRawFloat_adjustedNormDist_T_62, UInt<1>(0h1), _intAsRawFloat_adjustedNormDist_T_124) @[src/main/scala/chisel3/util/Mux.scala 50:70] node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_63, UInt<1>(0h0), _intAsRawFloat_adjustedNormDist_T_125) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 56:22] node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 63, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 56:41] wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 59:23] connect intAsRawFloat.isNaN, UInt<1>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 60:20] connect intAsRawFloat.isInf, UInt<1>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 61:20] node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 63, 63) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 62:28] node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 62:23] connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 62:20] connect intAsRawFloat.sign, intAsRawFloat_sign @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 63:20] node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 64:53] node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 64:36] node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 64:33] node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 64:72] connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 64:20] connect intAsRawFloat.sig, intAsRawFloat_sig @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 65:20] inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_1 @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 59:15] connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 67:44] connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 68:44] connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 69:44] connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 69:44] connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 69:44] connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 69:44] connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 69:44] connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 69:44] connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 70:44] connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 71:44] connect io.out, roundAnyRawFNToRecFN.io.out @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 72:23] connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 73:23] module RoundAnyRawFNToRecFN_2 : @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 48:5] output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 57:16] node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 89:53] node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 90:53] node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 91:53] node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 92:53] node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 93:53] node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 94:53] node _roundMagUp_T = and(roundingMode_min, io.in.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:27] node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:66] node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:63] node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:42] node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<12>(0h780))) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 103:25] node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 11, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 105:14] node sAdjustedExp = cvt(_sAdjustedExp_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 105:31] node _adjustedSig_T = bits(io.in.sig, 64, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 115:23] node _adjustedSig_T_1 = bits(io.in.sig, 9, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 116:26] node _adjustedSig_T_2 = orr(_adjustedSig_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 116:60] node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 115:66] wire common_expOut : UInt<12> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 121:31] wire common_fractOut : UInt<52> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 122:31] wire common_overflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 123:37] wire common_totalUnderflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 124:37] wire common_underflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 125:37] wire common_inexact : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 126:37] node _roundMask_T = cat(UInt<53>(0h0), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 152:36] node roundMask = cat(_roundMask_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 152:55] node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 161:41] node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 161:53] node _roundPosMask_T = not(shiftedRoundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 162:28] node roundPosMask = and(_roundPosMask_T, roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 162:46] node _roundPosBit_T = and(adjustedSig, roundPosMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 163:40] node roundPosBit = orr(_roundPosBit_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 163:56] node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 164:42] node anyRoundExtra = orr(_anyRoundExtra_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 164:62] node anyRound = or(roundPosBit, anyRoundExtra) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 165:36] node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 168:38] node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 168:67] node _roundIncr_T_2 = and(roundMagUp, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 170:29] node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 169:31] node _roundedSig_T = or(adjustedSig, roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:32] node _roundedSig_T_1 = shr(_roundedSig_T, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:44] node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:49] node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:49] node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 175:30] node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:64] node _roundedSig_T_6 = shr(roundMask, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 176:35] node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<55>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:25] node _roundedSig_T_8 = not(_roundedSig_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:21] node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:57] node _roundedSig_T_10 = not(roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:32] node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:30] node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:43] node _roundedSig_T_13 = and(roundingMode_odd, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:42] node _roundedSig_T_14 = shr(roundPosMask, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:67] node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:24] node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:47] node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 172:16] node _sRoundedExp_T = shr(roundedSig, 53) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:54] node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:76] node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:40] node _common_expOut_T = bits(sRoundedExp, 11, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 186:37] connect common_expOut, _common_expOut_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 186:23] node _common_fractOut_T = bits(roundedSig, 52, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 189:27] node _common_fractOut_T_1 = bits(roundedSig, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 190:27] node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 188:16] connect common_fractOut, _common_fractOut_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 187:25] connect common_overflow, UInt<1>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 192:25] connect common_totalUnderflow, UInt<1>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 196:31] node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:45] node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:61] node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:16] node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:44] node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:30] node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:63] node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:70] node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:49] node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 206:38] node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 206:67] node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 208:29] node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 207:46] node _roundCarry_T = bits(roundedSig, 54, 54) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 211:27] node _roundCarry_T_1 = bits(roundedSig, 53, 53) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 212:27] node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 210:16] connect common_underflow, UInt<1>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 214:26] node _common_inexact_T = or(common_totalUnderflow, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 229:49] connect common_inexact, _common_inexact_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 229:24] node isNaNOut = or(io.invalidExc, io.in.isNaN) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 234:34] node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 235:49] node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:22] node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:36] node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:33] node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:64] node commonCase = and(_commonCase_T_2, _commonCase_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:61] node overflow = and(commonCase, common_overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 237:32] node underflow = and(commonCase, common_underflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 238:32] node _inexact_T = and(commonCase, common_inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 239:43] node inexact = or(overflow, _inexact_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 239:28] node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 242:32] node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 242:60] node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:20] node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:60] node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:45] node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 245:42] node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 245:39] node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 247:45] node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 247:32] node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 249:22] node _expOut_T = or(io.in.isZero, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:32] node _expOut_T_1 = mux(_expOut_T, UInt<12>(0he00), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:18] node _expOut_T_2 = not(_expOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:14] node _expOut_T_3 = and(common_expOut, _expOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 251:24] node _expOut_T_4 = not(UInt<12>(0h3ce)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 257:19] node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 256:18] node _expOut_T_6 = not(_expOut_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 256:14] node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 255:17] node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<12>(0h400), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 260:18] node _expOut_T_9 = not(_expOut_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 260:14] node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 259:17] node _expOut_T_11 = mux(notNaN_isInfOut, UInt<12>(0h200), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 264:18] node _expOut_T_12 = not(_expOut_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 264:14] node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 263:17] node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<12>(0h3ce), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 268:16] node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 267:18] node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<12>(0hbff), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 272:16] node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 271:15] node _expOut_T_18 = mux(notNaN_isInfOut, UInt<12>(0hc00), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 276:16] node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 275:15] node _expOut_T_20 = mux(isNaNOut, UInt<12>(0he00), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 277:16] node expOut = or(_expOut_T_19, _expOut_T_20) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 276:73] node _fractOut_T = or(isNaNOut, io.in.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:22] node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:38] node _fractOut_T_2 = mux(isNaNOut, UInt<52>(0h8000000000000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 280:16] node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:12] node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<52>(0hfffffffffffff), UInt<52>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 283:13] node fractOut = or(_fractOut_T_3, _fractOut_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 282:11] node _io_out_T = cat(signOut, expOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:23] node _io_out_T_1 = cat(_io_out_T, fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:33] connect io.out, _io_out_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:12] node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:23] node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:41] node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:53] node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:66] connect io.exceptionFlags, _io_exceptionFlags_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 286:23] module INToRecFN_1 : @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 43:7] output io : { flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 45:16] node _intAsRawFloat_sign_T = bits(io.in, 63, 63) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 51:34] node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 51:29] node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 52:31] node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 52:31] node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 52:24] node _intAsRawFloat_extAbsIn_T = cat(UInt<64>(0h0), intAsRawFloat_absIn) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 53:44] node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 63, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 53:53] node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_2 = bits(intAsRawFloat_extAbsIn, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_3 = bits(intAsRawFloat_extAbsIn, 3, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_4 = bits(intAsRawFloat_extAbsIn, 4, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_5 = bits(intAsRawFloat_extAbsIn, 5, 5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_6 = bits(intAsRawFloat_extAbsIn, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_7 = bits(intAsRawFloat_extAbsIn, 7, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_8 = bits(intAsRawFloat_extAbsIn, 8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_9 = bits(intAsRawFloat_extAbsIn, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_10 = bits(intAsRawFloat_extAbsIn, 10, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_11 = bits(intAsRawFloat_extAbsIn, 11, 11) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_12 = bits(intAsRawFloat_extAbsIn, 12, 12) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_13 = bits(intAsRawFloat_extAbsIn, 13, 13) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_14 = bits(intAsRawFloat_extAbsIn, 14, 14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_15 = bits(intAsRawFloat_extAbsIn, 15, 15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_16 = bits(intAsRawFloat_extAbsIn, 16, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_17 = bits(intAsRawFloat_extAbsIn, 17, 17) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_18 = bits(intAsRawFloat_extAbsIn, 18, 18) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_19 = bits(intAsRawFloat_extAbsIn, 19, 19) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_20 = bits(intAsRawFloat_extAbsIn, 20, 20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_21 = bits(intAsRawFloat_extAbsIn, 21, 21) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_22 = bits(intAsRawFloat_extAbsIn, 22, 22) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_23 = bits(intAsRawFloat_extAbsIn, 23, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_24 = bits(intAsRawFloat_extAbsIn, 24, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_25 = bits(intAsRawFloat_extAbsIn, 25, 25) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_26 = bits(intAsRawFloat_extAbsIn, 26, 26) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_27 = bits(intAsRawFloat_extAbsIn, 27, 27) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_28 = bits(intAsRawFloat_extAbsIn, 28, 28) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_29 = bits(intAsRawFloat_extAbsIn, 29, 29) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_30 = bits(intAsRawFloat_extAbsIn, 30, 30) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_31 = bits(intAsRawFloat_extAbsIn, 31, 31) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_32 = bits(intAsRawFloat_extAbsIn, 32, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_33 = bits(intAsRawFloat_extAbsIn, 33, 33) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_34 = bits(intAsRawFloat_extAbsIn, 34, 34) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_35 = bits(intAsRawFloat_extAbsIn, 35, 35) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_36 = bits(intAsRawFloat_extAbsIn, 36, 36) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_37 = bits(intAsRawFloat_extAbsIn, 37, 37) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_38 = bits(intAsRawFloat_extAbsIn, 38, 38) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_39 = bits(intAsRawFloat_extAbsIn, 39, 39) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_40 = bits(intAsRawFloat_extAbsIn, 40, 40) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_41 = bits(intAsRawFloat_extAbsIn, 41, 41) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_42 = bits(intAsRawFloat_extAbsIn, 42, 42) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_43 = bits(intAsRawFloat_extAbsIn, 43, 43) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_44 = bits(intAsRawFloat_extAbsIn, 44, 44) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_45 = bits(intAsRawFloat_extAbsIn, 45, 45) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_46 = bits(intAsRawFloat_extAbsIn, 46, 46) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_47 = bits(intAsRawFloat_extAbsIn, 47, 47) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_48 = bits(intAsRawFloat_extAbsIn, 48, 48) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_49 = bits(intAsRawFloat_extAbsIn, 49, 49) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_50 = bits(intAsRawFloat_extAbsIn, 50, 50) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_51 = bits(intAsRawFloat_extAbsIn, 51, 51) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_52 = bits(intAsRawFloat_extAbsIn, 52, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_53 = bits(intAsRawFloat_extAbsIn, 53, 53) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_54 = bits(intAsRawFloat_extAbsIn, 54, 54) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_55 = bits(intAsRawFloat_extAbsIn, 55, 55) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_56 = bits(intAsRawFloat_extAbsIn, 56, 56) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_57 = bits(intAsRawFloat_extAbsIn, 57, 57) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_58 = bits(intAsRawFloat_extAbsIn, 58, 58) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_59 = bits(intAsRawFloat_extAbsIn, 59, 59) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_60 = bits(intAsRawFloat_extAbsIn, 60, 60) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_61 = bits(intAsRawFloat_extAbsIn, 61, 61) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_62 = bits(intAsRawFloat_extAbsIn, 62, 62) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_63 = bits(intAsRawFloat_extAbsIn, 63, 63) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _intAsRawFloat_adjustedNormDist_T_64 = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<6>(0h3e), UInt<6>(0h3f)) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_65 = mux(_intAsRawFloat_adjustedNormDist_T_2, UInt<6>(0h3d), _intAsRawFloat_adjustedNormDist_T_64) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_66 = mux(_intAsRawFloat_adjustedNormDist_T_3, UInt<6>(0h3c), _intAsRawFloat_adjustedNormDist_T_65) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_67 = mux(_intAsRawFloat_adjustedNormDist_T_4, UInt<6>(0h3b), _intAsRawFloat_adjustedNormDist_T_66) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_68 = mux(_intAsRawFloat_adjustedNormDist_T_5, UInt<6>(0h3a), _intAsRawFloat_adjustedNormDist_T_67) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_69 = mux(_intAsRawFloat_adjustedNormDist_T_6, UInt<6>(0h39), _intAsRawFloat_adjustedNormDist_T_68) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_70 = mux(_intAsRawFloat_adjustedNormDist_T_7, UInt<6>(0h38), _intAsRawFloat_adjustedNormDist_T_69) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_71 = mux(_intAsRawFloat_adjustedNormDist_T_8, UInt<6>(0h37), _intAsRawFloat_adjustedNormDist_T_70) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_72 = mux(_intAsRawFloat_adjustedNormDist_T_9, UInt<6>(0h36), _intAsRawFloat_adjustedNormDist_T_71) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_73 = mux(_intAsRawFloat_adjustedNormDist_T_10, UInt<6>(0h35), _intAsRawFloat_adjustedNormDist_T_72) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_74 = mux(_intAsRawFloat_adjustedNormDist_T_11, UInt<6>(0h34), _intAsRawFloat_adjustedNormDist_T_73) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_75 = mux(_intAsRawFloat_adjustedNormDist_T_12, UInt<6>(0h33), _intAsRawFloat_adjustedNormDist_T_74) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_76 = mux(_intAsRawFloat_adjustedNormDist_T_13, UInt<6>(0h32), _intAsRawFloat_adjustedNormDist_T_75) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_77 = mux(_intAsRawFloat_adjustedNormDist_T_14, UInt<6>(0h31), _intAsRawFloat_adjustedNormDist_T_76) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_78 = mux(_intAsRawFloat_adjustedNormDist_T_15, UInt<6>(0h30), _intAsRawFloat_adjustedNormDist_T_77) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_79 = mux(_intAsRawFloat_adjustedNormDist_T_16, UInt<6>(0h2f), _intAsRawFloat_adjustedNormDist_T_78) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_80 = mux(_intAsRawFloat_adjustedNormDist_T_17, UInt<6>(0h2e), _intAsRawFloat_adjustedNormDist_T_79) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_81 = mux(_intAsRawFloat_adjustedNormDist_T_18, UInt<6>(0h2d), _intAsRawFloat_adjustedNormDist_T_80) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_82 = mux(_intAsRawFloat_adjustedNormDist_T_19, UInt<6>(0h2c), _intAsRawFloat_adjustedNormDist_T_81) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_83 = mux(_intAsRawFloat_adjustedNormDist_T_20, UInt<6>(0h2b), _intAsRawFloat_adjustedNormDist_T_82) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_84 = mux(_intAsRawFloat_adjustedNormDist_T_21, UInt<6>(0h2a), _intAsRawFloat_adjustedNormDist_T_83) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_85 = mux(_intAsRawFloat_adjustedNormDist_T_22, UInt<6>(0h29), _intAsRawFloat_adjustedNormDist_T_84) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_86 = mux(_intAsRawFloat_adjustedNormDist_T_23, UInt<6>(0h28), _intAsRawFloat_adjustedNormDist_T_85) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_87 = mux(_intAsRawFloat_adjustedNormDist_T_24, UInt<6>(0h27), _intAsRawFloat_adjustedNormDist_T_86) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_88 = mux(_intAsRawFloat_adjustedNormDist_T_25, UInt<6>(0h26), _intAsRawFloat_adjustedNormDist_T_87) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_89 = mux(_intAsRawFloat_adjustedNormDist_T_26, UInt<6>(0h25), _intAsRawFloat_adjustedNormDist_T_88) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_90 = mux(_intAsRawFloat_adjustedNormDist_T_27, UInt<6>(0h24), _intAsRawFloat_adjustedNormDist_T_89) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_91 = mux(_intAsRawFloat_adjustedNormDist_T_28, UInt<6>(0h23), _intAsRawFloat_adjustedNormDist_T_90) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_92 = mux(_intAsRawFloat_adjustedNormDist_T_29, UInt<6>(0h22), _intAsRawFloat_adjustedNormDist_T_91) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_93 = mux(_intAsRawFloat_adjustedNormDist_T_30, UInt<6>(0h21), _intAsRawFloat_adjustedNormDist_T_92) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_94 = mux(_intAsRawFloat_adjustedNormDist_T_31, UInt<6>(0h20), _intAsRawFloat_adjustedNormDist_T_93) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_95 = mux(_intAsRawFloat_adjustedNormDist_T_32, UInt<5>(0h1f), _intAsRawFloat_adjustedNormDist_T_94) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_96 = mux(_intAsRawFloat_adjustedNormDist_T_33, UInt<5>(0h1e), _intAsRawFloat_adjustedNormDist_T_95) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_97 = mux(_intAsRawFloat_adjustedNormDist_T_34, UInt<5>(0h1d), _intAsRawFloat_adjustedNormDist_T_96) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_98 = mux(_intAsRawFloat_adjustedNormDist_T_35, UInt<5>(0h1c), _intAsRawFloat_adjustedNormDist_T_97) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_99 = mux(_intAsRawFloat_adjustedNormDist_T_36, UInt<5>(0h1b), _intAsRawFloat_adjustedNormDist_T_98) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_100 = mux(_intAsRawFloat_adjustedNormDist_T_37, UInt<5>(0h1a), _intAsRawFloat_adjustedNormDist_T_99) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_101 = mux(_intAsRawFloat_adjustedNormDist_T_38, UInt<5>(0h19), _intAsRawFloat_adjustedNormDist_T_100) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_102 = mux(_intAsRawFloat_adjustedNormDist_T_39, UInt<5>(0h18), _intAsRawFloat_adjustedNormDist_T_101) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_103 = mux(_intAsRawFloat_adjustedNormDist_T_40, UInt<5>(0h17), _intAsRawFloat_adjustedNormDist_T_102) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_104 = mux(_intAsRawFloat_adjustedNormDist_T_41, UInt<5>(0h16), _intAsRawFloat_adjustedNormDist_T_103) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_105 = mux(_intAsRawFloat_adjustedNormDist_T_42, UInt<5>(0h15), _intAsRawFloat_adjustedNormDist_T_104) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_106 = mux(_intAsRawFloat_adjustedNormDist_T_43, UInt<5>(0h14), _intAsRawFloat_adjustedNormDist_T_105) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_107 = mux(_intAsRawFloat_adjustedNormDist_T_44, UInt<5>(0h13), _intAsRawFloat_adjustedNormDist_T_106) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_108 = mux(_intAsRawFloat_adjustedNormDist_T_45, UInt<5>(0h12), _intAsRawFloat_adjustedNormDist_T_107) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_109 = mux(_intAsRawFloat_adjustedNormDist_T_46, UInt<5>(0h11), _intAsRawFloat_adjustedNormDist_T_108) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_110 = mux(_intAsRawFloat_adjustedNormDist_T_47, UInt<5>(0h10), _intAsRawFloat_adjustedNormDist_T_109) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_111 = mux(_intAsRawFloat_adjustedNormDist_T_48, UInt<4>(0hf), _intAsRawFloat_adjustedNormDist_T_110) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_112 = mux(_intAsRawFloat_adjustedNormDist_T_49, UInt<4>(0he), _intAsRawFloat_adjustedNormDist_T_111) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_113 = mux(_intAsRawFloat_adjustedNormDist_T_50, UInt<4>(0hd), _intAsRawFloat_adjustedNormDist_T_112) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_114 = mux(_intAsRawFloat_adjustedNormDist_T_51, UInt<4>(0hc), _intAsRawFloat_adjustedNormDist_T_113) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_115 = mux(_intAsRawFloat_adjustedNormDist_T_52, UInt<4>(0hb), _intAsRawFloat_adjustedNormDist_T_114) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_116 = mux(_intAsRawFloat_adjustedNormDist_T_53, UInt<4>(0ha), _intAsRawFloat_adjustedNormDist_T_115) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_117 = mux(_intAsRawFloat_adjustedNormDist_T_54, UInt<4>(0h9), _intAsRawFloat_adjustedNormDist_T_116) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_118 = mux(_intAsRawFloat_adjustedNormDist_T_55, UInt<4>(0h8), _intAsRawFloat_adjustedNormDist_T_117) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_119 = mux(_intAsRawFloat_adjustedNormDist_T_56, UInt<3>(0h7), _intAsRawFloat_adjustedNormDist_T_118) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_120 = mux(_intAsRawFloat_adjustedNormDist_T_57, UInt<3>(0h6), _intAsRawFloat_adjustedNormDist_T_119) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_121 = mux(_intAsRawFloat_adjustedNormDist_T_58, UInt<3>(0h5), _intAsRawFloat_adjustedNormDist_T_120) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_122 = mux(_intAsRawFloat_adjustedNormDist_T_59, UInt<3>(0h4), _intAsRawFloat_adjustedNormDist_T_121) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_123 = mux(_intAsRawFloat_adjustedNormDist_T_60, UInt<2>(0h3), _intAsRawFloat_adjustedNormDist_T_122) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_124 = mux(_intAsRawFloat_adjustedNormDist_T_61, UInt<2>(0h2), _intAsRawFloat_adjustedNormDist_T_123) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_adjustedNormDist_T_125 = mux(_intAsRawFloat_adjustedNormDist_T_62, UInt<1>(0h1), _intAsRawFloat_adjustedNormDist_T_124) @[src/main/scala/chisel3/util/Mux.scala 50:70] node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_63, UInt<1>(0h0), _intAsRawFloat_adjustedNormDist_T_125) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 56:22] node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 63, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 56:41] wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 59:23] connect intAsRawFloat.isNaN, UInt<1>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 60:20] connect intAsRawFloat.isInf, UInt<1>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 61:20] node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 63, 63) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 62:28] node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 62:23] connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 62:20] connect intAsRawFloat.sign, intAsRawFloat_sign @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 63:20] node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 64:53] node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 64:36] node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 64:33] node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 64:72] connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 64:20] connect intAsRawFloat.sig, intAsRawFloat_sig @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromIN.scala 65:20] inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_2 @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 59:15] connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 67:44] connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 68:44] connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 69:44] connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 69:44] connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 69:44] connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 69:44] connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 69:44] connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 69:44] connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 70:44] connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 71:44] connect io.out, roundAnyRawFNToRecFN.io.out @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 72:23] connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags @[dependencies/hardfloat/hardfloat/src/main/scala/INToRecFN.scala 73:23] module IntToFP : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 528:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 528:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 528:7] output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<64>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 529:14] regreset in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect in_pipe_v, io.in.valid @[src/main/scala/chisel3/util/Valid.scala 141:24] reg in_pipe_b : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<64>}, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when io.in.valid : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect in_pipe_b, io.in.bits @[src/main/scala/chisel3/util/Valid.scala 142:26] wire in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<64>}} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect in.valid, in_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect in.bits, in_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] wire mux : { data : UInt<65>, exc : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 537:17] connect mux.exc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 538:11] node _mux_data_truncIdx_T = or(in.bits.typeTagIn, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:21] node mux_data_truncIdx = bits(_mux_data_truncIdx_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:47] node _mux_data_T = eq(mux_data_truncIdx, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _mux_data_T_1 = mux(_mux_data_T, UInt<1>(0h0), UInt<64>(0hffffffff00000000)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _mux_data_T_2 = or(_mux_data_T_1, in.bits.in1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 431:23] node mux_data_rawIn_sign = bits(_mux_data_T_2, 63, 63) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 44:18] node mux_data_rawIn_expIn = bits(_mux_data_T_2, 62, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 45:19] node mux_data_rawIn_fractIn = bits(_mux_data_T_2, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 46:21] node mux_data_rawIn_isZeroExpIn = eq(mux_data_rawIn_expIn, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 48:30] node mux_data_rawIn_isZeroFractIn = eq(mux_data_rawIn_fractIn, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 49:34] node _mux_data_rawIn_normDist_T = bits(mux_data_rawIn_fractIn, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_1 = bits(mux_data_rawIn_fractIn, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_2 = bits(mux_data_rawIn_fractIn, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_3 = bits(mux_data_rawIn_fractIn, 3, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_4 = bits(mux_data_rawIn_fractIn, 4, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_5 = bits(mux_data_rawIn_fractIn, 5, 5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_6 = bits(mux_data_rawIn_fractIn, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_7 = bits(mux_data_rawIn_fractIn, 7, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_8 = bits(mux_data_rawIn_fractIn, 8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_9 = bits(mux_data_rawIn_fractIn, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_10 = bits(mux_data_rawIn_fractIn, 10, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_11 = bits(mux_data_rawIn_fractIn, 11, 11) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_12 = bits(mux_data_rawIn_fractIn, 12, 12) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_13 = bits(mux_data_rawIn_fractIn, 13, 13) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_14 = bits(mux_data_rawIn_fractIn, 14, 14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_15 = bits(mux_data_rawIn_fractIn, 15, 15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_16 = bits(mux_data_rawIn_fractIn, 16, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_17 = bits(mux_data_rawIn_fractIn, 17, 17) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_18 = bits(mux_data_rawIn_fractIn, 18, 18) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_19 = bits(mux_data_rawIn_fractIn, 19, 19) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_20 = bits(mux_data_rawIn_fractIn, 20, 20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_21 = bits(mux_data_rawIn_fractIn, 21, 21) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_22 = bits(mux_data_rawIn_fractIn, 22, 22) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_23 = bits(mux_data_rawIn_fractIn, 23, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_24 = bits(mux_data_rawIn_fractIn, 24, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_25 = bits(mux_data_rawIn_fractIn, 25, 25) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_26 = bits(mux_data_rawIn_fractIn, 26, 26) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_27 = bits(mux_data_rawIn_fractIn, 27, 27) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_28 = bits(mux_data_rawIn_fractIn, 28, 28) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_29 = bits(mux_data_rawIn_fractIn, 29, 29) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_30 = bits(mux_data_rawIn_fractIn, 30, 30) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_31 = bits(mux_data_rawIn_fractIn, 31, 31) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_32 = bits(mux_data_rawIn_fractIn, 32, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_33 = bits(mux_data_rawIn_fractIn, 33, 33) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_34 = bits(mux_data_rawIn_fractIn, 34, 34) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_35 = bits(mux_data_rawIn_fractIn, 35, 35) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_36 = bits(mux_data_rawIn_fractIn, 36, 36) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_37 = bits(mux_data_rawIn_fractIn, 37, 37) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_38 = bits(mux_data_rawIn_fractIn, 38, 38) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_39 = bits(mux_data_rawIn_fractIn, 39, 39) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_40 = bits(mux_data_rawIn_fractIn, 40, 40) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_41 = bits(mux_data_rawIn_fractIn, 41, 41) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_42 = bits(mux_data_rawIn_fractIn, 42, 42) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_43 = bits(mux_data_rawIn_fractIn, 43, 43) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_44 = bits(mux_data_rawIn_fractIn, 44, 44) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_45 = bits(mux_data_rawIn_fractIn, 45, 45) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_46 = bits(mux_data_rawIn_fractIn, 46, 46) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_47 = bits(mux_data_rawIn_fractIn, 47, 47) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_48 = bits(mux_data_rawIn_fractIn, 48, 48) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_49 = bits(mux_data_rawIn_fractIn, 49, 49) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_50 = bits(mux_data_rawIn_fractIn, 50, 50) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_51 = bits(mux_data_rawIn_fractIn, 51, 51) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_52 = mux(_mux_data_rawIn_normDist_T_1, UInt<6>(0h32), UInt<6>(0h33)) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_53 = mux(_mux_data_rawIn_normDist_T_2, UInt<6>(0h31), _mux_data_rawIn_normDist_T_52) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_54 = mux(_mux_data_rawIn_normDist_T_3, UInt<6>(0h30), _mux_data_rawIn_normDist_T_53) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_55 = mux(_mux_data_rawIn_normDist_T_4, UInt<6>(0h2f), _mux_data_rawIn_normDist_T_54) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_56 = mux(_mux_data_rawIn_normDist_T_5, UInt<6>(0h2e), _mux_data_rawIn_normDist_T_55) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_57 = mux(_mux_data_rawIn_normDist_T_6, UInt<6>(0h2d), _mux_data_rawIn_normDist_T_56) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_58 = mux(_mux_data_rawIn_normDist_T_7, UInt<6>(0h2c), _mux_data_rawIn_normDist_T_57) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_59 = mux(_mux_data_rawIn_normDist_T_8, UInt<6>(0h2b), _mux_data_rawIn_normDist_T_58) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_60 = mux(_mux_data_rawIn_normDist_T_9, UInt<6>(0h2a), _mux_data_rawIn_normDist_T_59) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_61 = mux(_mux_data_rawIn_normDist_T_10, UInt<6>(0h29), _mux_data_rawIn_normDist_T_60) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_62 = mux(_mux_data_rawIn_normDist_T_11, UInt<6>(0h28), _mux_data_rawIn_normDist_T_61) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_63 = mux(_mux_data_rawIn_normDist_T_12, UInt<6>(0h27), _mux_data_rawIn_normDist_T_62) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_64 = mux(_mux_data_rawIn_normDist_T_13, UInt<6>(0h26), _mux_data_rawIn_normDist_T_63) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_65 = mux(_mux_data_rawIn_normDist_T_14, UInt<6>(0h25), _mux_data_rawIn_normDist_T_64) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_66 = mux(_mux_data_rawIn_normDist_T_15, UInt<6>(0h24), _mux_data_rawIn_normDist_T_65) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_67 = mux(_mux_data_rawIn_normDist_T_16, UInt<6>(0h23), _mux_data_rawIn_normDist_T_66) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_68 = mux(_mux_data_rawIn_normDist_T_17, UInt<6>(0h22), _mux_data_rawIn_normDist_T_67) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_69 = mux(_mux_data_rawIn_normDist_T_18, UInt<6>(0h21), _mux_data_rawIn_normDist_T_68) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_70 = mux(_mux_data_rawIn_normDist_T_19, UInt<6>(0h20), _mux_data_rawIn_normDist_T_69) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_71 = mux(_mux_data_rawIn_normDist_T_20, UInt<5>(0h1f), _mux_data_rawIn_normDist_T_70) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_72 = mux(_mux_data_rawIn_normDist_T_21, UInt<5>(0h1e), _mux_data_rawIn_normDist_T_71) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_73 = mux(_mux_data_rawIn_normDist_T_22, UInt<5>(0h1d), _mux_data_rawIn_normDist_T_72) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_74 = mux(_mux_data_rawIn_normDist_T_23, UInt<5>(0h1c), _mux_data_rawIn_normDist_T_73) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_75 = mux(_mux_data_rawIn_normDist_T_24, UInt<5>(0h1b), _mux_data_rawIn_normDist_T_74) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_76 = mux(_mux_data_rawIn_normDist_T_25, UInt<5>(0h1a), _mux_data_rawIn_normDist_T_75) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_77 = mux(_mux_data_rawIn_normDist_T_26, UInt<5>(0h19), _mux_data_rawIn_normDist_T_76) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_78 = mux(_mux_data_rawIn_normDist_T_27, UInt<5>(0h18), _mux_data_rawIn_normDist_T_77) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_79 = mux(_mux_data_rawIn_normDist_T_28, UInt<5>(0h17), _mux_data_rawIn_normDist_T_78) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_80 = mux(_mux_data_rawIn_normDist_T_29, UInt<5>(0h16), _mux_data_rawIn_normDist_T_79) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_81 = mux(_mux_data_rawIn_normDist_T_30, UInt<5>(0h15), _mux_data_rawIn_normDist_T_80) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_82 = mux(_mux_data_rawIn_normDist_T_31, UInt<5>(0h14), _mux_data_rawIn_normDist_T_81) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_83 = mux(_mux_data_rawIn_normDist_T_32, UInt<5>(0h13), _mux_data_rawIn_normDist_T_82) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_84 = mux(_mux_data_rawIn_normDist_T_33, UInt<5>(0h12), _mux_data_rawIn_normDist_T_83) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_85 = mux(_mux_data_rawIn_normDist_T_34, UInt<5>(0h11), _mux_data_rawIn_normDist_T_84) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_86 = mux(_mux_data_rawIn_normDist_T_35, UInt<5>(0h10), _mux_data_rawIn_normDist_T_85) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_87 = mux(_mux_data_rawIn_normDist_T_36, UInt<4>(0hf), _mux_data_rawIn_normDist_T_86) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_88 = mux(_mux_data_rawIn_normDist_T_37, UInt<4>(0he), _mux_data_rawIn_normDist_T_87) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_89 = mux(_mux_data_rawIn_normDist_T_38, UInt<4>(0hd), _mux_data_rawIn_normDist_T_88) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_90 = mux(_mux_data_rawIn_normDist_T_39, UInt<4>(0hc), _mux_data_rawIn_normDist_T_89) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_91 = mux(_mux_data_rawIn_normDist_T_40, UInt<4>(0hb), _mux_data_rawIn_normDist_T_90) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_92 = mux(_mux_data_rawIn_normDist_T_41, UInt<4>(0ha), _mux_data_rawIn_normDist_T_91) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_93 = mux(_mux_data_rawIn_normDist_T_42, UInt<4>(0h9), _mux_data_rawIn_normDist_T_92) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_94 = mux(_mux_data_rawIn_normDist_T_43, UInt<4>(0h8), _mux_data_rawIn_normDist_T_93) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_95 = mux(_mux_data_rawIn_normDist_T_44, UInt<3>(0h7), _mux_data_rawIn_normDist_T_94) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_96 = mux(_mux_data_rawIn_normDist_T_45, UInt<3>(0h6), _mux_data_rawIn_normDist_T_95) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_97 = mux(_mux_data_rawIn_normDist_T_46, UInt<3>(0h5), _mux_data_rawIn_normDist_T_96) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_98 = mux(_mux_data_rawIn_normDist_T_47, UInt<3>(0h4), _mux_data_rawIn_normDist_T_97) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_99 = mux(_mux_data_rawIn_normDist_T_48, UInt<2>(0h3), _mux_data_rawIn_normDist_T_98) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_100 = mux(_mux_data_rawIn_normDist_T_49, UInt<2>(0h2), _mux_data_rawIn_normDist_T_99) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_101 = mux(_mux_data_rawIn_normDist_T_50, UInt<1>(0h1), _mux_data_rawIn_normDist_T_100) @[src/main/scala/chisel3/util/Mux.scala 50:70] node mux_data_rawIn_normDist = mux(_mux_data_rawIn_normDist_T_51, UInt<1>(0h0), _mux_data_rawIn_normDist_T_101) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_subnormFract_T = dshl(mux_data_rawIn_fractIn, mux_data_rawIn_normDist) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 52:33] node _mux_data_rawIn_subnormFract_T_1 = bits(_mux_data_rawIn_subnormFract_T, 50, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 52:46] node mux_data_rawIn_subnormFract = shl(_mux_data_rawIn_subnormFract_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 52:64] node _mux_data_rawIn_adjustedExp_T = xor(mux_data_rawIn_normDist, UInt<12>(0hfff)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 55:18] node _mux_data_rawIn_adjustedExp_T_1 = mux(mux_data_rawIn_isZeroExpIn, _mux_data_rawIn_adjustedExp_T, mux_data_rawIn_expIn) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 54:10] node _mux_data_rawIn_adjustedExp_T_2 = mux(mux_data_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 58:14] node _mux_data_rawIn_adjustedExp_T_3 = or(UInt<11>(0h400), _mux_data_rawIn_adjustedExp_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 58:9] node _mux_data_rawIn_adjustedExp_T_4 = add(_mux_data_rawIn_adjustedExp_T_1, _mux_data_rawIn_adjustedExp_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 57:9] node mux_data_rawIn_adjustedExp = tail(_mux_data_rawIn_adjustedExp_T_4, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 57:9] node mux_data_rawIn_isZero = and(mux_data_rawIn_isZeroExpIn, mux_data_rawIn_isZeroFractIn) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 60:30] node _mux_data_rawIn_isSpecial_T = bits(mux_data_rawIn_adjustedExp, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 61:32] node mux_data_rawIn_isSpecial = eq(_mux_data_rawIn_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 61:57] wire mux_data_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 63:19] node _mux_data_rawIn_out_isNaN_T = eq(mux_data_rawIn_isZeroFractIn, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 64:31] node _mux_data_rawIn_out_isNaN_T_1 = and(mux_data_rawIn_isSpecial, _mux_data_rawIn_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 64:28] connect mux_data_rawIn.isNaN, _mux_data_rawIn_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 64:15] node _mux_data_rawIn_out_isInf_T = and(mux_data_rawIn_isSpecial, mux_data_rawIn_isZeroFractIn) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 65:28] connect mux_data_rawIn.isInf, _mux_data_rawIn_out_isInf_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 65:15] connect mux_data_rawIn.isZero, mux_data_rawIn_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 66:16] connect mux_data_rawIn.sign, mux_data_rawIn_sign @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 67:14] node _mux_data_rawIn_out_sExp_T = bits(mux_data_rawIn_adjustedExp, 11, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 68:28] node _mux_data_rawIn_out_sExp_T_1 = cvt(_mux_data_rawIn_out_sExp_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 68:42] connect mux_data_rawIn.sExp, _mux_data_rawIn_out_sExp_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 68:14] node _mux_data_rawIn_out_sig_T = eq(mux_data_rawIn_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 70:19] node _mux_data_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _mux_data_rawIn_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 70:16] node _mux_data_rawIn_out_sig_T_2 = mux(mux_data_rawIn_isZeroExpIn, mux_data_rawIn_subnormFract, mux_data_rawIn_fractIn) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 70:33] node _mux_data_rawIn_out_sig_T_3 = cat(_mux_data_rawIn_out_sig_T_1, _mux_data_rawIn_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 70:27] connect mux_data_rawIn.sig, _mux_data_rawIn_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 69:13] node _mux_data_T_3 = bits(mux_data_rawIn.sExp, 11, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 48:50] node _mux_data_T_4 = mux(mux_data_rawIn.isZero, UInt<3>(0h0), _mux_data_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 48:15] node _mux_data_T_5 = mux(mux_data_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 49:20] node _mux_data_T_6 = or(_mux_data_T_4, _mux_data_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 48:76] node _mux_data_T_7 = cat(mux_data_rawIn.sign, _mux_data_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 47:20] node _mux_data_T_8 = bits(mux_data_rawIn.sExp, 8, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 50:23] node _mux_data_T_9 = cat(_mux_data_T_7, _mux_data_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 49:45] node _mux_data_T_10 = bits(mux_data_rawIn.sig, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 51:22] node _mux_data_T_11 = cat(_mux_data_T_9, _mux_data_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 50:41] node mux_data_rawIn_sign_1 = bits(_mux_data_T_2, 31, 31) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 44:18] node mux_data_rawIn_expIn_1 = bits(_mux_data_T_2, 30, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 45:19] node mux_data_rawIn_fractIn_1 = bits(_mux_data_T_2, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 46:21] node mux_data_rawIn_isZeroExpIn_1 = eq(mux_data_rawIn_expIn_1, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 48:30] node mux_data_rawIn_isZeroFractIn_1 = eq(mux_data_rawIn_fractIn_1, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 49:34] node _mux_data_rawIn_normDist_T_102 = bits(mux_data_rawIn_fractIn_1, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_103 = bits(mux_data_rawIn_fractIn_1, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_104 = bits(mux_data_rawIn_fractIn_1, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_105 = bits(mux_data_rawIn_fractIn_1, 3, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_106 = bits(mux_data_rawIn_fractIn_1, 4, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_107 = bits(mux_data_rawIn_fractIn_1, 5, 5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_108 = bits(mux_data_rawIn_fractIn_1, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_109 = bits(mux_data_rawIn_fractIn_1, 7, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_110 = bits(mux_data_rawIn_fractIn_1, 8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_111 = bits(mux_data_rawIn_fractIn_1, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_112 = bits(mux_data_rawIn_fractIn_1, 10, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_113 = bits(mux_data_rawIn_fractIn_1, 11, 11) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_114 = bits(mux_data_rawIn_fractIn_1, 12, 12) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_115 = bits(mux_data_rawIn_fractIn_1, 13, 13) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_116 = bits(mux_data_rawIn_fractIn_1, 14, 14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_117 = bits(mux_data_rawIn_fractIn_1, 15, 15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_118 = bits(mux_data_rawIn_fractIn_1, 16, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_119 = bits(mux_data_rawIn_fractIn_1, 17, 17) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_120 = bits(mux_data_rawIn_fractIn_1, 18, 18) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_121 = bits(mux_data_rawIn_fractIn_1, 19, 19) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_122 = bits(mux_data_rawIn_fractIn_1, 20, 20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_123 = bits(mux_data_rawIn_fractIn_1, 21, 21) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_124 = bits(mux_data_rawIn_fractIn_1, 22, 22) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _mux_data_rawIn_normDist_T_125 = mux(_mux_data_rawIn_normDist_T_103, UInt<5>(0h15), UInt<5>(0h16)) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_126 = mux(_mux_data_rawIn_normDist_T_104, UInt<5>(0h14), _mux_data_rawIn_normDist_T_125) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_127 = mux(_mux_data_rawIn_normDist_T_105, UInt<5>(0h13), _mux_data_rawIn_normDist_T_126) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_128 = mux(_mux_data_rawIn_normDist_T_106, UInt<5>(0h12), _mux_data_rawIn_normDist_T_127) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_129 = mux(_mux_data_rawIn_normDist_T_107, UInt<5>(0h11), _mux_data_rawIn_normDist_T_128) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_130 = mux(_mux_data_rawIn_normDist_T_108, UInt<5>(0h10), _mux_data_rawIn_normDist_T_129) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_131 = mux(_mux_data_rawIn_normDist_T_109, UInt<4>(0hf), _mux_data_rawIn_normDist_T_130) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_132 = mux(_mux_data_rawIn_normDist_T_110, UInt<4>(0he), _mux_data_rawIn_normDist_T_131) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_133 = mux(_mux_data_rawIn_normDist_T_111, UInt<4>(0hd), _mux_data_rawIn_normDist_T_132) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_134 = mux(_mux_data_rawIn_normDist_T_112, UInt<4>(0hc), _mux_data_rawIn_normDist_T_133) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_135 = mux(_mux_data_rawIn_normDist_T_113, UInt<4>(0hb), _mux_data_rawIn_normDist_T_134) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_136 = mux(_mux_data_rawIn_normDist_T_114, UInt<4>(0ha), _mux_data_rawIn_normDist_T_135) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_137 = mux(_mux_data_rawIn_normDist_T_115, UInt<4>(0h9), _mux_data_rawIn_normDist_T_136) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_138 = mux(_mux_data_rawIn_normDist_T_116, UInt<4>(0h8), _mux_data_rawIn_normDist_T_137) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_139 = mux(_mux_data_rawIn_normDist_T_117, UInt<3>(0h7), _mux_data_rawIn_normDist_T_138) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_140 = mux(_mux_data_rawIn_normDist_T_118, UInt<3>(0h6), _mux_data_rawIn_normDist_T_139) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_141 = mux(_mux_data_rawIn_normDist_T_119, UInt<3>(0h5), _mux_data_rawIn_normDist_T_140) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_142 = mux(_mux_data_rawIn_normDist_T_120, UInt<3>(0h4), _mux_data_rawIn_normDist_T_141) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_143 = mux(_mux_data_rawIn_normDist_T_121, UInt<2>(0h3), _mux_data_rawIn_normDist_T_142) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_144 = mux(_mux_data_rawIn_normDist_T_122, UInt<2>(0h2), _mux_data_rawIn_normDist_T_143) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_normDist_T_145 = mux(_mux_data_rawIn_normDist_T_123, UInt<1>(0h1), _mux_data_rawIn_normDist_T_144) @[src/main/scala/chisel3/util/Mux.scala 50:70] node mux_data_rawIn_normDist_1 = mux(_mux_data_rawIn_normDist_T_124, UInt<1>(0h0), _mux_data_rawIn_normDist_T_145) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _mux_data_rawIn_subnormFract_T_2 = dshl(mux_data_rawIn_fractIn_1, mux_data_rawIn_normDist_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 52:33] node _mux_data_rawIn_subnormFract_T_3 = bits(_mux_data_rawIn_subnormFract_T_2, 21, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 52:46] node mux_data_rawIn_subnormFract_1 = shl(_mux_data_rawIn_subnormFract_T_3, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 52:64] node _mux_data_rawIn_adjustedExp_T_5 = xor(mux_data_rawIn_normDist_1, UInt<9>(0h1ff)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 55:18] node _mux_data_rawIn_adjustedExp_T_6 = mux(mux_data_rawIn_isZeroExpIn_1, _mux_data_rawIn_adjustedExp_T_5, mux_data_rawIn_expIn_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 54:10] node _mux_data_rawIn_adjustedExp_T_7 = mux(mux_data_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 58:14] node _mux_data_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _mux_data_rawIn_adjustedExp_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 58:9] node _mux_data_rawIn_adjustedExp_T_9 = add(_mux_data_rawIn_adjustedExp_T_6, _mux_data_rawIn_adjustedExp_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 57:9] node mux_data_rawIn_adjustedExp_1 = tail(_mux_data_rawIn_adjustedExp_T_9, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 57:9] node mux_data_rawIn_isZero_1 = and(mux_data_rawIn_isZeroExpIn_1, mux_data_rawIn_isZeroFractIn_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 60:30] node _mux_data_rawIn_isSpecial_T_1 = bits(mux_data_rawIn_adjustedExp_1, 8, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 61:32] node mux_data_rawIn_isSpecial_1 = eq(_mux_data_rawIn_isSpecial_T_1, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 61:57] wire mux_data_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 63:19] node _mux_data_rawIn_out_isNaN_T_2 = eq(mux_data_rawIn_isZeroFractIn_1, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 64:31] node _mux_data_rawIn_out_isNaN_T_3 = and(mux_data_rawIn_isSpecial_1, _mux_data_rawIn_out_isNaN_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 64:28] connect mux_data_rawIn_1.isNaN, _mux_data_rawIn_out_isNaN_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 64:15] node _mux_data_rawIn_out_isInf_T_1 = and(mux_data_rawIn_isSpecial_1, mux_data_rawIn_isZeroFractIn_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 65:28] connect mux_data_rawIn_1.isInf, _mux_data_rawIn_out_isInf_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 65:15] connect mux_data_rawIn_1.isZero, mux_data_rawIn_isZero_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 66:16] connect mux_data_rawIn_1.sign, mux_data_rawIn_sign_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 67:14] node _mux_data_rawIn_out_sExp_T_2 = bits(mux_data_rawIn_adjustedExp_1, 8, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 68:28] node _mux_data_rawIn_out_sExp_T_3 = cvt(_mux_data_rawIn_out_sExp_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 68:42] connect mux_data_rawIn_1.sExp, _mux_data_rawIn_out_sExp_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 68:14] node _mux_data_rawIn_out_sig_T_4 = eq(mux_data_rawIn_isZero_1, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 70:19] node _mux_data_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _mux_data_rawIn_out_sig_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 70:16] node _mux_data_rawIn_out_sig_T_6 = mux(mux_data_rawIn_isZeroExpIn_1, mux_data_rawIn_subnormFract_1, mux_data_rawIn_fractIn_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 70:33] node _mux_data_rawIn_out_sig_T_7 = cat(_mux_data_rawIn_out_sig_T_5, _mux_data_rawIn_out_sig_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 70:27] connect mux_data_rawIn_1.sig, _mux_data_rawIn_out_sig_T_7 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 69:13] node _mux_data_T_12 = bits(mux_data_rawIn_1.sExp, 8, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 48:50] node _mux_data_T_13 = mux(mux_data_rawIn_1.isZero, UInt<3>(0h0), _mux_data_T_12) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 48:15] node _mux_data_T_14 = mux(mux_data_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 49:20] node _mux_data_T_15 = or(_mux_data_T_13, _mux_data_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 48:76] node _mux_data_T_16 = cat(mux_data_rawIn_1.sign, _mux_data_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 47:20] node _mux_data_T_17 = bits(mux_data_rawIn_1.sExp, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 50:23] node _mux_data_T_18 = cat(_mux_data_T_16, _mux_data_T_17) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 49:45] node _mux_data_T_19 = bits(mux_data_rawIn_1.sig, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 51:22] node _mux_data_T_20 = cat(_mux_data_T_18, _mux_data_T_19) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 50:41] node _mux_data_swizzledNaN_T = bits(_mux_data_T_11, 64, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 337:8] node _mux_data_swizzledNaN_T_1 = bits(_mux_data_T_11, 51, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 338:8] node _mux_data_swizzledNaN_T_2 = andr(_mux_data_swizzledNaN_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 338:42] node _mux_data_swizzledNaN_T_3 = bits(_mux_data_T_11, 59, 53) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 339:8] node _mux_data_swizzledNaN_T_4 = bits(_mux_data_T_20, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 340:8] node _mux_data_swizzledNaN_T_5 = bits(_mux_data_T_11, 51, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 341:8] node _mux_data_swizzledNaN_T_6 = bits(_mux_data_T_20, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 342:8] node _mux_data_swizzledNaN_T_7 = bits(_mux_data_T_20, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 343:8] node mux_data_swizzledNaN_lo_hi = cat(_mux_data_swizzledNaN_T_5, _mux_data_swizzledNaN_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 336:26] node mux_data_swizzledNaN_lo = cat(mux_data_swizzledNaN_lo_hi, _mux_data_swizzledNaN_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 336:26] node mux_data_swizzledNaN_hi_lo = cat(_mux_data_swizzledNaN_T_3, _mux_data_swizzledNaN_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 336:26] node mux_data_swizzledNaN_hi_hi = cat(_mux_data_swizzledNaN_T, _mux_data_swizzledNaN_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 336:26] node mux_data_swizzledNaN_hi = cat(mux_data_swizzledNaN_hi_hi, mux_data_swizzledNaN_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 336:26] node mux_data_swizzledNaN = cat(mux_data_swizzledNaN_hi, mux_data_swizzledNaN_lo) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 336:26] node _mux_data_T_21 = bits(_mux_data_T_11, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node _mux_data_T_22 = andr(_mux_data_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node _mux_data_T_23 = mux(_mux_data_T_22, mux_data_swizzledNaN, _mux_data_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 344:8] connect mux.data, _mux_data_T_23 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 539:12] node _intValue_res_T = asSInt(in.bits.in1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 542:39] wire intValue_res : SInt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 542:26] connect intValue_res, _intValue_res_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 542:26] node intValue_smallInt = bits(in.bits.in1, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 544:33] node _intValue_T = bits(in.bits.typ, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _intValue_T_1 = eq(_intValue_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 545:57] when _intValue_T_1 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 545:66] node _intValue_res_T_1 = bits(in.bits.typ, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 546:31] node _intValue_res_T_2 = cvt(intValue_smallInt) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 546:45] node _intValue_res_T_3 = asSInt(intValue_smallInt) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 546:60] node _intValue_res_T_4 = mux(_intValue_res_T_1, _intValue_res_T_2, _intValue_res_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 546:19] connect intValue_res, _intValue_res_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 546:13] node intValue = asUInt(intValue_res) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 549:9] when in.bits.wflags : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 552:25] inst i2fResults_i2f of INToRecFN @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 556:23] node _i2fResults_i2f_io_signedIn_T = bits(in.bits.typ, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 557:38] node _i2fResults_i2f_io_signedIn_T_1 = not(_i2fResults_i2f_io_signedIn_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 557:26] connect i2fResults_i2f.io.signedIn, _i2fResults_i2f_io_signedIn_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 557:23] connect i2fResults_i2f.io.in, intValue @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 558:17] connect i2fResults_i2f.io.roundingMode, in.bits.rm @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 559:27] connect i2fResults_i2f.io.detectTininess, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 560:29] inst i2fResults_i2f_1 of INToRecFN_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 556:23] node _i2fResults_i2f_io_signedIn_T_2 = bits(in.bits.typ, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 557:38] node _i2fResults_i2f_io_signedIn_T_3 = not(_i2fResults_i2f_io_signedIn_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 557:26] connect i2fResults_i2f_1.io.signedIn, _i2fResults_i2f_io_signedIn_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 557:23] connect i2fResults_i2f_1.io.in, intValue @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 558:17] connect i2fResults_i2f_1.io.roundingMode, in.bits.rm @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 559:27] connect i2fResults_i2f_1.io.detectTininess, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 560:29] node _i2fResults_maskedNaN_T = not(UInt<65>(0h1010000000000000)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 413:27] node i2fResults_maskedNaN = and(i2fResults_i2f_1.io.out, _i2fResults_maskedNaN_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 413:25] node _i2fResults_T = bits(i2fResults_i2f_1.io.out, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node _i2fResults_T_1 = andr(_i2fResults_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node i2fResults_1_1 = mux(_i2fResults_T_1, i2fResults_maskedNaN, i2fResults_i2f_1.io.out) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 414:10] node _dataPadded_T = shr(i2fResults_1_1, 33) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 565:55] node dataPadded_0 = cat(_dataPadded_T, i2fResults_i2f.io.out) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 565:44] node _mux_data_truncIdx_T_1 = or(in.bits.typeTagIn, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:21] node mux_data_truncIdx_1 = bits(_mux_data_truncIdx_T_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:47] node _mux_data_T_24 = eq(mux_data_truncIdx_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _mux_data_T_25 = mux(_mux_data_T_24, i2fResults_1_1, dataPadded_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] connect mux.data, _mux_data_T_25 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 566:14] node _mux_exc_truncIdx_T = or(in.bits.typeTagIn, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:21] node mux_exc_truncIdx = bits(_mux_exc_truncIdx_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:47] node _mux_exc_T = eq(mux_exc_truncIdx, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _mux_exc_T_1 = mux(_mux_exc_T, i2fResults_i2f_1.io.exceptionFlags, i2fResults_i2f.io.exceptionFlags) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] connect mux.exc, _mux_exc_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 567:13] regreset io_out_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect io_out_pipe_v, in.valid @[src/main/scala/chisel3/util/Valid.scala 141:24] reg io_out_pipe_b : { data : UInt<65>, exc : UInt<5>}, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when in.valid : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect io_out_pipe_b, mux @[src/main/scala/chisel3/util/Valid.scala 142:26] wire io_out_pipe_out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect io_out_pipe_out.valid, io_out_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect io_out_pipe_out.bits, io_out_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect io.out, io_out_pipe_out @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 570:10] module RoundAnyRawFNToRecFN_3 : @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 48:5] output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 57:16] node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 89:53] node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 90:53] node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 91:53] node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 92:53] node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 93:53] node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 94:53] node _roundMagUp_T = and(roundingMode_min, io.in.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:27] node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:66] node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:63] node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:42] node sAdjustedExp = add(io.in.sExp, asSInt(UInt<12>(0h900))) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 109:24] node _adjustedSig_T = bits(io.in.sig, 53, 28) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 115:23] node _adjustedSig_T_1 = bits(io.in.sig, 27, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 116:26] node _adjustedSig_T_2 = orr(_adjustedSig_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 116:60] node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 115:66] wire common_expOut : UInt<9> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 121:31] wire common_fractOut : UInt<23> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 122:31] wire common_overflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 123:37] wire common_totalUnderflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 124:37] wire common_underflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 125:37] wire common_inexact : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 126:37] node _roundMask_T = bits(sAdjustedExp, 8, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 155:37] node _roundMask_T_1 = not(_roundMask_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 52:21] node roundMask_msb = bits(_roundMask_T_1, 8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 76:56] node _roundMask_T_2 = bits(roundMask_shift, 63, 42) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 78:22] node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_4 = shl(UInt<8>(0hff), 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_6 = shr(_roundMask_T_3, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_9 = shl(_roundMask_T_8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_10 = not(_roundMask_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_14 = shl(_roundMask_T_13, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_16 = shr(_roundMask_T_12, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_19 = shl(_roundMask_T_18, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_20 = not(_roundMask_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_24 = shl(_roundMask_T_23, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_26 = shr(_roundMask_T_22, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_29 = shl(_roundMask_T_28, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_30 = not(_roundMask_T_25) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_34 = shl(_roundMask_T_33, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_36 = shr(_roundMask_T_32, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_39 = shl(_roundMask_T_38, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_40 = not(_roundMask_T_35) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_60 = not(_roundMask_T_59) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:32] node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:21] node _roundMask_T_62 = not(_roundMask_T_61) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:17] node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 68:58] node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 76:56] node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 78:22] node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 62:24] node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 67:24] node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 62:24] node _roundMask_T_74 = or(_roundMask_T_73, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 158:23] node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 158:42] node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 161:41] node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 161:53] node _roundPosMask_T = not(shiftedRoundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 162:28] node roundPosMask = and(_roundPosMask_T, roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 162:46] node _roundPosBit_T = and(adjustedSig, roundPosMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 163:40] node roundPosBit = orr(_roundPosBit_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 163:56] node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 164:42] node anyRoundExtra = orr(_anyRoundExtra_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 164:62] node anyRound = or(roundPosBit, anyRoundExtra) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 165:36] node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 168:38] node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 168:67] node _roundIncr_T_2 = and(roundMagUp, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 170:29] node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 169:31] node _roundedSig_T = or(adjustedSig, roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:32] node _roundedSig_T_1 = shr(_roundedSig_T, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:44] node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:49] node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:49] node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 175:30] node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:64] node _roundedSig_T_6 = shr(roundMask, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 176:35] node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:25] node _roundedSig_T_8 = not(_roundedSig_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:21] node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:57] node _roundedSig_T_10 = not(roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:32] node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:30] node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:43] node _roundedSig_T_13 = and(roundingMode_odd, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:42] node _roundedSig_T_14 = shr(roundPosMask, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:67] node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:24] node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:47] node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 172:16] node _sRoundedExp_T = shr(roundedSig, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:54] node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:76] node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:40] node _common_expOut_T = bits(sRoundedExp, 8, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 186:37] connect common_expOut, _common_expOut_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 186:23] node _common_fractOut_T = bits(roundedSig, 23, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 189:27] node _common_fractOut_T_1 = bits(roundedSig, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 190:27] node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 188:16] connect common_fractOut, _common_fractOut_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 187:25] node _common_overflow_T = shr(sRoundedExp, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 195:30] node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 195:50] connect common_overflow, _common_overflow_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 192:25] node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 199:31] connect common_totalUnderflow, _common_totalUnderflow_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 196:31] node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:45] node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:61] node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:16] node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:44] node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:30] node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:63] node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:70] node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:49] node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 206:38] node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 206:67] node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 208:29] node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 207:46] node _roundCarry_T = bits(roundedSig, 25, 25) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 211:27] node _roundCarry_T_1 = bits(roundedSig, 24, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 212:27] node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 210:16] node _common_underflow_T = shr(sAdjustedExp, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:49] node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:64] node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:32] node _common_underflow_T_3 = bits(roundMask, 3, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:57] node _common_underflow_T_4 = bits(roundMask, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:71] node _common_underflow_T_5 = mux(UInt<1>(0h0), _common_underflow_T_3, _common_underflow_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:30] node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:72] node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 221:49] node _common_underflow_T_8 = bits(roundMask, 4, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 223:49] node _common_underflow_T_9 = bits(roundMask, 3, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 224:49] node _common_underflow_T_10 = mux(UInt<1>(0h0), _common_underflow_T_8, _common_underflow_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 222:39] node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 222:34] node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 221:77] node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 225:38] node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 226:45] node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 226:60] node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 221:27] node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:76] node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 216:40] connect common_underflow, _common_underflow_T_18 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 214:26] node _common_inexact_T = or(common_totalUnderflow, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 229:49] connect common_inexact, _common_inexact_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 229:24] node isNaNOut = or(io.invalidExc, io.in.isNaN) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 234:34] node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 235:49] node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:22] node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:36] node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:33] node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:64] node commonCase = and(_commonCase_T_2, _commonCase_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:61] node overflow = and(commonCase, common_overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 237:32] node underflow = and(commonCase, common_underflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 238:32] node _inexact_T = and(commonCase, common_inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 239:43] node inexact = or(overflow, _inexact_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 239:28] node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 242:32] node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 242:60] node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:20] node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:60] node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:45] node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 245:42] node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 245:39] node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 247:45] node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 247:32] node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 249:22] node _expOut_T = or(io.in.isZero, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:32] node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:18] node _expOut_T_2 = not(_expOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:14] node _expOut_T_3 = and(common_expOut, _expOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 251:24] node _expOut_T_4 = not(UInt<9>(0h6b)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 257:19] node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 256:18] node _expOut_T_6 = not(_expOut_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 256:14] node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 255:17] node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 260:18] node _expOut_T_9 = not(_expOut_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 260:14] node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 259:17] node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 264:18] node _expOut_T_12 = not(_expOut_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 264:14] node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 263:17] node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 268:16] node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 267:18] node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 272:16] node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 271:15] node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 276:16] node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 275:15] node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 277:16] node expOut = or(_expOut_T_19, _expOut_T_20) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 276:73] node _fractOut_T = or(isNaNOut, io.in.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:22] node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:38] node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 280:16] node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:12] node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 283:13] node fractOut = or(_fractOut_T_3, _fractOut_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 282:11] node _io_out_T = cat(signOut, expOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:23] node _io_out_T_1 = cat(_io_out_T, fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:33] connect io.out, _io_out_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:12] node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:23] node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:41] node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:53] node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:66] connect io.exceptionFlags, _io_exceptionFlags_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 286:23] module RecFNToRecFN : @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToRecFN.scala 44:5] output io : { flip in : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToRecFN.scala 48:16] node rawIn_exp = bits(io.in, 63, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _rawIn_isZero_T = bits(rawIn_exp, 11, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _rawIn_isSpecial_T = bits(rawIn_exp, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _rawIn_out_isNaN_T = bits(rawIn_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect rawIn.isNaN, _rawIn_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _rawIn_out_isInf_T = bits(rawIn_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect rawIn.isInf, _rawIn_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect rawIn.isZero, rawIn_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _rawIn_out_sign_T = bits(io.in, 64, 64) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect rawIn.sign, _rawIn_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _rawIn_out_sExp_T = cvt(rawIn_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect rawIn.sExp, _rawIn_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _rawIn_out_sig_T_2 = bits(io.in, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect rawIn.sig, _rawIn_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_3 @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToRecFN.scala 72:19] node _roundAnyRawFNToRecFN_io_invalidExc_T = bits(rawIn.sig, 51, 51) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:56] node _roundAnyRawFNToRecFN_io_invalidExc_T_1 = eq(_roundAnyRawFNToRecFN_io_invalidExc_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:49] node _roundAnyRawFNToRecFN_io_invalidExc_T_2 = and(rawIn.isNaN, _roundAnyRawFNToRecFN_io_invalidExc_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:46] connect roundAnyRawFNToRecFN.io.invalidExc, _roundAnyRawFNToRecFN_io_invalidExc_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToRecFN.scala 80:48] connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToRecFN.scala 81:48] connect roundAnyRawFNToRecFN.io.in.sig, rawIn.sig @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToRecFN.scala 82:48] connect roundAnyRawFNToRecFN.io.in.sExp, rawIn.sExp @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToRecFN.scala 82:48] connect roundAnyRawFNToRecFN.io.in.sign, rawIn.sign @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToRecFN.scala 82:48] connect roundAnyRawFNToRecFN.io.in.isZero, rawIn.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToRecFN.scala 82:48] connect roundAnyRawFNToRecFN.io.in.isInf, rawIn.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToRecFN.scala 82:48] connect roundAnyRawFNToRecFN.io.in.isNaN, rawIn.isNaN @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToRecFN.scala 82:48] connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToRecFN.scala 83:48] connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToRecFN.scala 84:48] connect io.out, roundAnyRawFNToRecFN.io.out @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToRecFN.scala 85:27] connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags @[dependencies/hardfloat/hardfloat/src/main/scala/RecFNToRecFN.scala 86:27] module FPToFP : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 573:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 573:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 573:7] output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}, flip lt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 574:14] regreset in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect in_pipe_v, io.in.valid @[src/main/scala/chisel3/util/Valid.scala 141:24] reg in_pipe_b : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when io.in.valid : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect in_pipe_b, io.in.bits @[src/main/scala/chisel3/util/Valid.scala 142:26] wire in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect in.valid, in_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect in.bits, in_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] node _signNum_T = bits(in.bits.rm, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 582:31] node _signNum_T_1 = xor(in.bits.in1, in.bits.in2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 582:48] node _signNum_T_2 = bits(in.bits.rm, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 582:77] node _signNum_T_3 = not(in.bits.in2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 582:82] node _signNum_T_4 = mux(_signNum_T_2, _signNum_T_3, in.bits.in2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 582:66] node signNum = mux(_signNum_T, _signNum_T_1, _signNum_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 582:20] node _fsgnj_T = bits(signNum, 64, 64) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 583:26] node _fsgnj_T_1 = bits(in.bits.in1, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 583:45] node fsgnj = cat(_fsgnj_T, _fsgnj_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 583:18] wire fsgnjMux : { data : UInt<65>, exc : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 585:22] connect fsgnjMux.exc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 586:16] connect fsgnjMux.data, fsgnj @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 587:17] when in.bits.wflags : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 589:25] node _isnan1_T = bits(in.bits.in1, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node isnan1 = andr(_isnan1_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node _isnan2_T = bits(in.bits.in2, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node isnan2 = andr(_isnan2_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node _isInvalid_T = bits(in.bits.in1, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node _isInvalid_T_1 = andr(_isInvalid_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node _isInvalid_T_2 = bits(in.bits.in1, 51, 51) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 250:39] node _isInvalid_T_3 = eq(_isInvalid_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 250:37] node _isInvalid_T_4 = and(_isInvalid_T_1, _isInvalid_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 250:34] node _isInvalid_T_5 = bits(in.bits.in2, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node _isInvalid_T_6 = andr(_isInvalid_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node _isInvalid_T_7 = bits(in.bits.in2, 51, 51) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 250:39] node _isInvalid_T_8 = eq(_isInvalid_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 250:37] node _isInvalid_T_9 = and(_isInvalid_T_6, _isInvalid_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 250:34] node isInvalid = or(_isInvalid_T_4, _isInvalid_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 592:49] node isNaNOut = and(isnan1, isnan2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 593:27] node _isLHS_T = bits(in.bits.rm, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 594:37] node _isLHS_T_1 = neq(_isLHS_T, io.lt) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 594:41] node _isLHS_T_2 = eq(isnan1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 594:54] node _isLHS_T_3 = and(_isLHS_T_1, _isLHS_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 594:51] node isLHS = or(isnan2, _isLHS_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 594:24] node _fsgnjMux_exc_T = shl(isInvalid, 4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 595:31] connect fsgnjMux.exc, _fsgnjMux_exc_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 595:18] node _fsgnjMux_data_T = mux(isLHS, in.bits.in1, in.bits.in2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 596:53] node _fsgnjMux_data_T_1 = mux(isNaNOut, UInt<65>(0he008000000000000), _fsgnjMux_data_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 596:25] connect fsgnjMux.data, _fsgnjMux_data_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 596:19] wire mux : { data : UInt<65>, exc : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 601:24] connect mux, fsgnjMux @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 601:24] node _T = eq(in.bits.typeTagOut, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 603:18] when _T : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 603:36] node _mux_data_T = shr(fsgnjMux.data, 33) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 604:37] node mux_data_sign = bits(fsgnjMux.data, 64, 64) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 274:17] node mux_data_fractIn = bits(fsgnjMux.data, 51, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 275:20] node mux_data_expIn = bits(fsgnjMux.data, 63, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 276:18] node _mux_data_fractOut_T = shl(mux_data_fractIn, 24) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:28] node mux_data_fractOut = shr(_mux_data_fractOut_T, 53) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:38] node mux_data_expOut_expCode = bits(mux_data_expIn, 11, 9) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 279:26] node _mux_data_expOut_commonCase_T = add(mux_data_expIn, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _mux_data_expOut_commonCase_T_1 = tail(_mux_data_expOut_commonCase_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _mux_data_expOut_commonCase_T_2 = sub(_mux_data_expOut_commonCase_T_1, UInt<12>(0h800)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node mux_data_expOut_commonCase = tail(_mux_data_expOut_commonCase_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node _mux_data_expOut_T = eq(mux_data_expOut_expCode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:19] node _mux_data_expOut_T_1 = geq(mux_data_expOut_expCode, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:38] node _mux_data_expOut_T_2 = or(_mux_data_expOut_T, _mux_data_expOut_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:27] node _mux_data_expOut_T_3 = bits(mux_data_expOut_commonCase, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:69] node _mux_data_expOut_T_4 = cat(mux_data_expOut_expCode, _mux_data_expOut_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:49] node _mux_data_expOut_T_5 = bits(mux_data_expOut_commonCase, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:97] node mux_data_expOut = mux(_mux_data_expOut_T_2, _mux_data_expOut_T_4, _mux_data_expOut_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:10] node mux_data_hi = cat(mux_data_sign, mux_data_expOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node _mux_data_T_1 = cat(mux_data_hi, mux_data_fractOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node _mux_data_T_2 = cat(_mux_data_T, _mux_data_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 604:22] connect mux.data, _mux_data_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 604:16] node _T_1 = eq(in.bits.ren2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 608:27] node _T_2 = and(in.bits.wflags, _T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 608:24] when _T_2 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 608:42] node _widened_T = bits(in.bits.in1, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node _widened_T_1 = andr(_widened_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node widened = mux(_widened_T_1, UInt<65>(0he008000000000000), in.bits.in1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 611:24] connect fsgnjMux.data, widened @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 612:21] node _fsgnjMux_exc_T_1 = bits(in.bits.in1, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node _fsgnjMux_exc_T_2 = andr(_fsgnjMux_exc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node _fsgnjMux_exc_T_3 = bits(in.bits.in1, 51, 51) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 250:39] node _fsgnjMux_exc_T_4 = eq(_fsgnjMux_exc_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 250:37] node _fsgnjMux_exc_T_5 = and(_fsgnjMux_exc_T_2, _fsgnjMux_exc_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 250:34] node _fsgnjMux_exc_T_6 = shl(_fsgnjMux_exc_T_5, 4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 613:51] connect fsgnjMux.exc, _fsgnjMux_exc_T_6 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 613:20] node _T_3 = eq(in.bits.typeTagOut, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 618:53] node _T_4 = lt(in.bits.typeTagOut, in.bits.typeTagIn) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 618:116] node _T_5 = or(UInt<1>(0h1), _T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 618:106] node _T_6 = and(_T_3, _T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 618:76] when _T_6 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 618:126] inst narrower of RecFNToRecFN @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 619:30] connect narrower.io.in, in.bits.in1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 620:24] connect narrower.io.roundingMode, in.bits.rm @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 621:34] connect narrower.io.detectTininess, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 622:36] node _mux_data_T_3 = shr(fsgnjMux.data, 33) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 624:39] node _mux_data_T_4 = cat(_mux_data_T_3, narrower.io.out) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 624:24] connect mux.data, _mux_data_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 624:18] connect mux.exc, narrower.io.exceptionFlags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 625:17] regreset io_out_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect io_out_pipe_v, in.valid @[src/main/scala/chisel3/util/Valid.scala 141:24] reg io_out_pipe_b : { data : UInt<65>, exc : UInt<5>}, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when in.valid : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect io_out_pipe_b, mux @[src/main/scala/chisel3/util/Valid.scala 142:26] wire io_out_pipe_out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect io_out_pipe_out.valid, io_out_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect io_out_pipe_out.bits, io_out_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect io.out, io_out_pipe_out @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 630:10] module MulAddRecFNToRaw_preMul_1 : @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 71:7] output io : { flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, mulAddA : UInt<53>, mulAddB : UInt<53>, mulAddC : UInt<106>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<13>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<6>, highAlignedSigC : UInt<55>, bit0AlignedSigC : UInt<1>}} @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 73:16] node rawA_exp = bits(io.a, 63, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _rawA_isZero_T = bits(rawA_exp, 11, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _rawA_isSpecial_T = bits(rawA_exp, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _rawA_out_isNaN_T = bits(rawA_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect rawA.isNaN, _rawA_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _rawA_out_isInf_T = bits(rawA_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect rawA.isInf, _rawA_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect rawA.isZero, rawA_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _rawA_out_sign_T = bits(io.a, 64, 64) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect rawA.sign, _rawA_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _rawA_out_sExp_T = cvt(rawA_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect rawA.sExp, _rawA_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _rawA_out_sig_T_2 = bits(io.a, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect rawA.sig, _rawA_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node rawB_exp = bits(io.b, 63, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _rawB_isZero_T = bits(rawB_exp, 11, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _rawB_isSpecial_T = bits(rawB_exp, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _rawB_out_isNaN_T = bits(rawB_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect rawB.isNaN, _rawB_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _rawB_out_isInf_T = bits(rawB_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect rawB.isInf, _rawB_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect rawB.isZero, rawB_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _rawB_out_sign_T = bits(io.b, 64, 64) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect rawB.sign, _rawB_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _rawB_out_sExp_T = cvt(rawB_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect rawB.sExp, _rawB_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _rawB_out_sig_T_2 = bits(io.b, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect rawB.sig, _rawB_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node rawC_exp = bits(io.c, 63, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _rawC_isZero_T = bits(rawC_exp, 11, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _rawC_isSpecial_T = bits(rawC_exp, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _rawC_out_isNaN_T = bits(rawC_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect rawC.isNaN, _rawC_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _rawC_out_isInf_T = bits(rawC_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect rawC.isInf, _rawC_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect rawC.isZero, rawC_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _rawC_out_sign_T = bits(io.c, 64, 64) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect rawC.sign, _rawC_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _rawC_out_sExp_T = cvt(rawC_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect rawC.sExp, _rawC_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _rawC_out_sig_T_2 = bits(io.c, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect rawC.sig, _rawC_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node _signProd_T = xor(rawA.sign, rawB.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 96:30] node _signProd_T_1 = bits(io.op, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 96:49] node signProd = xor(_signProd_T, _signProd_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 96:42] node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 99:19] node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<12>(0h838))) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 99:32] node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 99:32] node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 99:32] node _doSubMags_T = xor(signProd, rawC.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 101:30] node _doSubMags_T_1 = bits(io.op, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 101:49] node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 101:42] node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 105:42] node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 105:42] node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 105:42] node posNatCAlignDist = bits(sNatCAlignDist, 12, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 106:42] node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 107:35] node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 107:69] node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 107:50] node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 109:9] node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<6>(0h35)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 109:60] node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 109:39] node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 109:23] node _CAlignDist_T = lt(posNatCAlignDist, UInt<8>(0ha1)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 113:34] node _CAlignDist_T_1 = bits(posNatCAlignDist, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 114:33] node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<8>(0ha1)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 113:16] node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 111:12] node _mainAlignedSigC_T = not(rawC.sig) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 119:25] node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 119:13] node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<111>(0h7fffffffffffffffffffffffffff), UInt<111>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 119:53] node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 119:46] node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 119:94] node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 119:100] node _reduced4CExtra_T = shl(rawC.sig, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 121:30] wire reduced4CExtra_reducedVec : UInt<1>[14] @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 118:30] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 27, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_7_T = bits(_reduced4CExtra_T, 31, 28) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_7_T_1 = orr(_reduced4CExtra_reducedVec_7_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[7], _reduced4CExtra_reducedVec_7_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_8_T = bits(_reduced4CExtra_T, 35, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_8_T_1 = orr(_reduced4CExtra_reducedVec_8_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[8], _reduced4CExtra_reducedVec_8_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_9_T = bits(_reduced4CExtra_T, 39, 36) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_9_T_1 = orr(_reduced4CExtra_reducedVec_9_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[9], _reduced4CExtra_reducedVec_9_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_10_T = bits(_reduced4CExtra_T, 43, 40) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_10_T_1 = orr(_reduced4CExtra_reducedVec_10_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[10], _reduced4CExtra_reducedVec_10_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_11_T = bits(_reduced4CExtra_T, 47, 44) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_11_T_1 = orr(_reduced4CExtra_reducedVec_11_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[11], _reduced4CExtra_reducedVec_11_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_12_T = bits(_reduced4CExtra_T, 51, 48) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _reduced4CExtra_reducedVec_12_T_1 = orr(_reduced4CExtra_reducedVec_12_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect reduced4CExtra_reducedVec[12], _reduced4CExtra_reducedVec_12_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _reduced4CExtra_reducedVec_13_T = bits(_reduced4CExtra_T, 53, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 123:15] node _reduced4CExtra_reducedVec_13_T_1 = orr(_reduced4CExtra_reducedVec_13_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 123:57] connect reduced4CExtra_reducedVec[13], _reduced4CExtra_reducedVec_13_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 122:38] node reduced4CExtra_lo_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node reduced4CExtra_lo_lo = cat(reduced4CExtra_lo_lo_hi, reduced4CExtra_reducedVec[0]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node reduced4CExtra_lo_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node reduced4CExtra_lo_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node reduced4CExtra_lo_hi = cat(reduced4CExtra_lo_hi_hi, reduced4CExtra_lo_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_lo_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node reduced4CExtra_hi_lo_hi = cat(reduced4CExtra_reducedVec[9], reduced4CExtra_reducedVec[8]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node reduced4CExtra_hi_lo = cat(reduced4CExtra_hi_lo_hi, reduced4CExtra_reducedVec[7]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node reduced4CExtra_hi_hi_lo = cat(reduced4CExtra_reducedVec[11], reduced4CExtra_reducedVec[10]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node reduced4CExtra_hi_hi_hi = cat(reduced4CExtra_reducedVec[13], reduced4CExtra_reducedVec[12]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node reduced4CExtra_hi_hi = cat(reduced4CExtra_hi_hi_hi, reduced4CExtra_hi_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node _reduced4CExtra_T_2 = shr(CAlignDist, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 123:28] node reduced4CExtra_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), _reduced4CExtra_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 76:56] node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 36, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 78:22] node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_5 = shl(UInt<4>(0hf), 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_6 = xor(UInt<8>(0hff), _reduced4CExtra_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_7 = shr(_reduced4CExtra_T_4, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_8 = and(_reduced4CExtra_T_7, _reduced4CExtra_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_10 = shl(_reduced4CExtra_T_9, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_11 = not(_reduced4CExtra_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_12 = and(_reduced4CExtra_T_10, _reduced4CExtra_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_13 = or(_reduced4CExtra_T_8, _reduced4CExtra_T_12) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_6, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_15 = shl(_reduced4CExtra_T_14, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_16 = xor(_reduced4CExtra_T_6, _reduced4CExtra_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_17 = shr(_reduced4CExtra_T_13, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_18 = and(_reduced4CExtra_T_17, _reduced4CExtra_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_19 = bits(_reduced4CExtra_T_13, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_20 = shl(_reduced4CExtra_T_19, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_21 = not(_reduced4CExtra_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_22 = and(_reduced4CExtra_T_20, _reduced4CExtra_T_21) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_23 = or(_reduced4CExtra_T_18, _reduced4CExtra_T_22) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_24 = bits(_reduced4CExtra_T_16, 6, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_25 = shl(_reduced4CExtra_T_24, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_26 = xor(_reduced4CExtra_T_16, _reduced4CExtra_T_25) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_27 = shr(_reduced4CExtra_T_23, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_28 = and(_reduced4CExtra_T_27, _reduced4CExtra_T_26) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_29 = bits(_reduced4CExtra_T_23, 6, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_30 = shl(_reduced4CExtra_T_29, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_31 = not(_reduced4CExtra_T_26) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_32 = and(_reduced4CExtra_T_30, _reduced4CExtra_T_31) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_33 = or(_reduced4CExtra_T_28, _reduced4CExtra_T_32) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_34 = bits(_reduced4CExtra_T_3, 12, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_35 = bits(_reduced4CExtra_T_34, 3, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_36 = bits(_reduced4CExtra_T_35, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_37 = bits(_reduced4CExtra_T_36, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_38 = bits(_reduced4CExtra_T_36, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_39 = cat(_reduced4CExtra_T_37, _reduced4CExtra_T_38) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_40 = bits(_reduced4CExtra_T_35, 3, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_41 = bits(_reduced4CExtra_T_40, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_42 = bits(_reduced4CExtra_T_40, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_43 = cat(_reduced4CExtra_T_41, _reduced4CExtra_T_42) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_44 = cat(_reduced4CExtra_T_39, _reduced4CExtra_T_43) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_45 = bits(_reduced4CExtra_T_34, 4, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_46 = cat(_reduced4CExtra_T_44, _reduced4CExtra_T_45) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_47 = cat(_reduced4CExtra_T_33, _reduced4CExtra_T_46) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _reduced4CExtra_T_48 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_47) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 121:68] node reduced4CExtra = orr(_reduced4CExtra_T_48) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 129:11] node _alignedSigC_T = shr(mainAlignedSigC, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 131:28] node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 133:32] node _alignedSigC_T_2 = andr(_alignedSigC_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 133:39] node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 133:47] node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 133:44] node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 134:32] node _alignedSigC_T_6 = orr(_alignedSigC_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 134:39] node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 134:44] node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 132:16] node alignedSigC_hi = asUInt(_alignedSigC_T) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 131:12] node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 131:12] connect io.mulAddA, rawA.sig @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 140:16] connect io.mulAddB, rawB.sig @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 141:16] node _io_mulAddC_T = bits(alignedSigC, 106, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 142:30] connect io.mulAddC, _io_mulAddC_T @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 142:16] node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 51, 51) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:56] node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:49] node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:46] node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 51, 51) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:56] node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:49] node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:46] node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 145:32] node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 51, 51) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:56] node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:49] node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:46] node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 145:58] connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 144:30] node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 147:42] connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 147:28] connect io.toPostMul.isInfA, rawA.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 148:28] connect io.toPostMul.isZeroA, rawA.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 149:28] connect io.toPostMul.isInfB, rawB.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 150:28] connect io.toPostMul.isZeroB, rawB.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 151:28] connect io.toPostMul.signProd, signProd @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 152:28] connect io.toPostMul.isNaNC, rawC.isNaN @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 153:28] connect io.toPostMul.isInfC, rawC.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 154:28] connect io.toPostMul.isZeroC, rawC.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 155:28] node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<7>(0h35))) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 157:53] node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 157:53] node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 157:53] node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 157:12] connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 156:28] connect io.toPostMul.doSubMags, doSubMags @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 158:28] connect io.toPostMul.CIsDominant, CIsDominant @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 159:30] node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 160:47] connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 160:34] node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 161, 107) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 162:20] connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 161:34] node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 163:48] connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 163:34] module MulAddRecFNToRaw_postMul_1 : @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 168:7] output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<13>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<6>, highAlignedSigC : UInt<55>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<107>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}} @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 170:16] node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 184:45] node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 188:42] node _sigSum_T = bits(io.mulAddResult, 106, 106) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 190:32] node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 191:47] node _sigSum_T_2 = tail(_sigSum_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 191:47] node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 190:16] node _sigSum_T_4 = bits(io.mulAddResult, 105, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 194:28] node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 190:12] node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 190:12] node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 201:69] node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 201:43] node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 201:43] node CDom_sExp = asSInt(_CDom_sExp_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 201:43] node _CDom_absSigSum_T = bits(sigSum, 161, 54) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 204:20] node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 204:13] node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 54, 53) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 207:46] node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 205:22] node _CDom_absSigSum_T_4 = bits(sigSum, 159, 55) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 208:23] node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 207:71] node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 203:12] node _CDom_absSigSumExtra_T = bits(sigSum, 53, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 213:21] node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 213:14] node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 213:36] node _CDom_absSigSumExtra_T_3 = bits(sigSum, 54, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 214:19] node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 214:37] node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 212:12] node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 217:24] node CDom_mainSig = bits(_CDom_mainSig_T, 107, 50) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 217:56] node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 52, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 220:36] node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 220:53] wire CDom_reduced4SigExtra_reducedVec : UInt<1>[14] @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 118:30] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 27, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_7_T = bits(_CDom_reduced4SigExtra_T_1, 31, 28) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_7_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_7_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[7], _CDom_reduced4SigExtra_reducedVec_7_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_8_T = bits(_CDom_reduced4SigExtra_T_1, 35, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_8_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_8_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[8], _CDom_reduced4SigExtra_reducedVec_8_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_9_T = bits(_CDom_reduced4SigExtra_T_1, 39, 36) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_9_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_9_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[9], _CDom_reduced4SigExtra_reducedVec_9_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_10_T = bits(_CDom_reduced4SigExtra_T_1, 43, 40) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_10_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_10_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[10], _CDom_reduced4SigExtra_reducedVec_10_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_11_T = bits(_CDom_reduced4SigExtra_T_1, 47, 44) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_11_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_11_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[11], _CDom_reduced4SigExtra_reducedVec_11_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_12_T = bits(_CDom_reduced4SigExtra_T_1, 51, 48) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:33] node _CDom_reduced4SigExtra_reducedVec_12_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_12_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:54] connect CDom_reduced4SigExtra_reducedVec[12], _CDom_reduced4SigExtra_reducedVec_12_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 120:28] node _CDom_reduced4SigExtra_reducedVec_13_T = bits(_CDom_reduced4SigExtra_T_1, 54, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 123:15] node _CDom_reduced4SigExtra_reducedVec_13_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_13_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 123:57] connect CDom_reduced4SigExtra_reducedVec[13], _CDom_reduced4SigExtra_reducedVec_13_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 122:38] node CDom_reduced4SigExtra_lo_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node CDom_reduced4SigExtra_lo_lo = cat(CDom_reduced4SigExtra_lo_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node CDom_reduced4SigExtra_lo_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node CDom_reduced4SigExtra_lo_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_lo_hi_hi, CDom_reduced4SigExtra_lo_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_lo_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node CDom_reduced4SigExtra_hi_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[9], CDom_reduced4SigExtra_reducedVec[8]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_hi_lo_hi, CDom_reduced4SigExtra_reducedVec[7]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node CDom_reduced4SigExtra_hi_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[11], CDom_reduced4SigExtra_reducedVec[10]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node CDom_reduced4SigExtra_hi_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[13], CDom_reduced4SigExtra_reducedVec[12]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_hi_hi_hi, CDom_reduced4SigExtra_hi_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 124:20] node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 221:51] node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 52:21] node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _CDom_reduced4SigExtra_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 76:56] node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 13, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 78:22] node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_7 = shl(UInt<4>(0hf), 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_8 = xor(UInt<8>(0hff), _CDom_reduced4SigExtra_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_9 = shr(_CDom_reduced4SigExtra_T_6, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_10 = and(_CDom_reduced4SigExtra_T_9, _CDom_reduced4SigExtra_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_12 = shl(_CDom_reduced4SigExtra_T_11, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_13 = not(_CDom_reduced4SigExtra_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_14 = and(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_15 = or(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_8, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_17 = shl(_CDom_reduced4SigExtra_T_16, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_18 = xor(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_17) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_19 = shr(_CDom_reduced4SigExtra_T_15, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_20 = and(_CDom_reduced4SigExtra_T_19, _CDom_reduced4SigExtra_T_18) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_21 = bits(_CDom_reduced4SigExtra_T_15, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_22 = shl(_CDom_reduced4SigExtra_T_21, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_23 = not(_CDom_reduced4SigExtra_T_18) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_24 = and(_CDom_reduced4SigExtra_T_22, _CDom_reduced4SigExtra_T_23) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_25 = or(_CDom_reduced4SigExtra_T_20, _CDom_reduced4SigExtra_T_24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_26 = bits(_CDom_reduced4SigExtra_T_18, 6, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_27 = shl(_CDom_reduced4SigExtra_T_26, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_28 = xor(_CDom_reduced4SigExtra_T_18, _CDom_reduced4SigExtra_T_27) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_29 = shr(_CDom_reduced4SigExtra_T_25, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_30 = and(_CDom_reduced4SigExtra_T_29, _CDom_reduced4SigExtra_T_28) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_31 = bits(_CDom_reduced4SigExtra_T_25, 6, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_32 = shl(_CDom_reduced4SigExtra_T_31, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_33 = not(_CDom_reduced4SigExtra_T_28) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_34 = and(_CDom_reduced4SigExtra_T_32, _CDom_reduced4SigExtra_T_33) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_35 = or(_CDom_reduced4SigExtra_T_30, _CDom_reduced4SigExtra_T_34) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_36 = bits(_CDom_reduced4SigExtra_T_5, 12, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_37 = bits(_CDom_reduced4SigExtra_T_36, 3, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_38 = bits(_CDom_reduced4SigExtra_T_37, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_39 = bits(_CDom_reduced4SigExtra_T_38, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_40 = bits(_CDom_reduced4SigExtra_T_38, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_41 = cat(_CDom_reduced4SigExtra_T_39, _CDom_reduced4SigExtra_T_40) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_42 = bits(_CDom_reduced4SigExtra_T_37, 3, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_43 = bits(_CDom_reduced4SigExtra_T_42, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_44 = bits(_CDom_reduced4SigExtra_T_42, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_45 = cat(_CDom_reduced4SigExtra_T_43, _CDom_reduced4SigExtra_T_44) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_46 = cat(_CDom_reduced4SigExtra_T_41, _CDom_reduced4SigExtra_T_45) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_47 = bits(_CDom_reduced4SigExtra_T_36, 4, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_48 = cat(_CDom_reduced4SigExtra_T_46, _CDom_reduced4SigExtra_T_47) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_49 = cat(_CDom_reduced4SigExtra_T_35, _CDom_reduced4SigExtra_T_48) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _CDom_reduced4SigExtra_T_50 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_49) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 220:72] node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_50) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 221:73] node _CDom_sig_T = shr(CDom_mainSig, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 223:25] node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 224:25] node _CDom_sig_T_2 = orr(_CDom_sig_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 224:32] node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 224:36] node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 224:61] node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 223:12] node notCDom_signSigSum = bits(sigSum, 109, 109) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 230:36] node _notCDom_absSigSum_T = bits(sigSum, 108, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 233:20] node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 233:13] node _notCDom_absSigSum_T_2 = bits(sigSum, 108, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 234:19] node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 234:41] node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 234:41] node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 232:12] wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[55] @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 101:30] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 51, 50) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_26_T = bits(notCDom_absSigSum, 53, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_26_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_26_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[26], _notCDom_reduced2AbsSigSum_reducedVec_26_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_27_T = bits(notCDom_absSigSum, 55, 54) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_27_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_27_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[27], _notCDom_reduced2AbsSigSum_reducedVec_27_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_28_T = bits(notCDom_absSigSum, 57, 56) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_28_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_28_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[28], _notCDom_reduced2AbsSigSum_reducedVec_28_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_29_T = bits(notCDom_absSigSum, 59, 58) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_29_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_29_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[29], _notCDom_reduced2AbsSigSum_reducedVec_29_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_30_T = bits(notCDom_absSigSum, 61, 60) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_30_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_30_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[30], _notCDom_reduced2AbsSigSum_reducedVec_30_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_31_T = bits(notCDom_absSigSum, 63, 62) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_31_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_31_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[31], _notCDom_reduced2AbsSigSum_reducedVec_31_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_32_T = bits(notCDom_absSigSum, 65, 64) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_32_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_32_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[32], _notCDom_reduced2AbsSigSum_reducedVec_32_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_33_T = bits(notCDom_absSigSum, 67, 66) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_33_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_33_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[33], _notCDom_reduced2AbsSigSum_reducedVec_33_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_34_T = bits(notCDom_absSigSum, 69, 68) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_34_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_34_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[34], _notCDom_reduced2AbsSigSum_reducedVec_34_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_35_T = bits(notCDom_absSigSum, 71, 70) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_35_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_35_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[35], _notCDom_reduced2AbsSigSum_reducedVec_35_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_36_T = bits(notCDom_absSigSum, 73, 72) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_36_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_36_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[36], _notCDom_reduced2AbsSigSum_reducedVec_36_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_37_T = bits(notCDom_absSigSum, 75, 74) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_37_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_37_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[37], _notCDom_reduced2AbsSigSum_reducedVec_37_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_38_T = bits(notCDom_absSigSum, 77, 76) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_38_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_38_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[38], _notCDom_reduced2AbsSigSum_reducedVec_38_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_39_T = bits(notCDom_absSigSum, 79, 78) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_39_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_39_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[39], _notCDom_reduced2AbsSigSum_reducedVec_39_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_40_T = bits(notCDom_absSigSum, 81, 80) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_40_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_40_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[40], _notCDom_reduced2AbsSigSum_reducedVec_40_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_41_T = bits(notCDom_absSigSum, 83, 82) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_41_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_41_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[41], _notCDom_reduced2AbsSigSum_reducedVec_41_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_42_T = bits(notCDom_absSigSum, 85, 84) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_42_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_42_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[42], _notCDom_reduced2AbsSigSum_reducedVec_42_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_43_T = bits(notCDom_absSigSum, 87, 86) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_43_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_43_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[43], _notCDom_reduced2AbsSigSum_reducedVec_43_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_44_T = bits(notCDom_absSigSum, 89, 88) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_44_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_44_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[44], _notCDom_reduced2AbsSigSum_reducedVec_44_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_45_T = bits(notCDom_absSigSum, 91, 90) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_45_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_45_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[45], _notCDom_reduced2AbsSigSum_reducedVec_45_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_46_T = bits(notCDom_absSigSum, 93, 92) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_46_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_46_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[46], _notCDom_reduced2AbsSigSum_reducedVec_46_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_47_T = bits(notCDom_absSigSum, 95, 94) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_47_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_47_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[47], _notCDom_reduced2AbsSigSum_reducedVec_47_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_48_T = bits(notCDom_absSigSum, 97, 96) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_48_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_48_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[48], _notCDom_reduced2AbsSigSum_reducedVec_48_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_49_T = bits(notCDom_absSigSum, 99, 98) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_49_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_49_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[49], _notCDom_reduced2AbsSigSum_reducedVec_49_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_50_T = bits(notCDom_absSigSum, 101, 100) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_50_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_50_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[50], _notCDom_reduced2AbsSigSum_reducedVec_50_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_51_T = bits(notCDom_absSigSum, 103, 102) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_51_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_51_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[51], _notCDom_reduced2AbsSigSum_reducedVec_51_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_52_T = bits(notCDom_absSigSum, 105, 104) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_52_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_52_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[52], _notCDom_reduced2AbsSigSum_reducedVec_52_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_53_T = bits(notCDom_absSigSum, 107, 106) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced2AbsSigSum_reducedVec_53_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_53_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced2AbsSigSum_reducedVec[53], _notCDom_reduced2AbsSigSum_reducedVec_53_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced2AbsSigSum_reducedVec_54_T = bits(notCDom_absSigSum, 108, 108) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 106:15] node _notCDom_reduced2AbsSigSum_reducedVec_54_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_54_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 106:57] connect notCDom_reduced2AbsSigSum_reducedVec[54], _notCDom_reduced2AbsSigSum_reducedVec_54_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 105:38] node notCDom_reduced2AbsSigSum_lo_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_lo_hi_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_lo_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[17], notCDom_reduced2AbsSigSum_reducedVec[16]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[19], notCDom_reduced2AbsSigSum_reducedVec[18]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_lo_hi_lo_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[22], notCDom_reduced2AbsSigSum_reducedVec[21]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[20]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[24], notCDom_reduced2AbsSigSum_reducedVec[23]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[26], notCDom_reduced2AbsSigSum_reducedVec[25]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[29], notCDom_reduced2AbsSigSum_reducedVec[28]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[27]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_lo_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[31], notCDom_reduced2AbsSigSum_reducedVec[30]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[33], notCDom_reduced2AbsSigSum_reducedVec[32]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_lo_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[36], notCDom_reduced2AbsSigSum_reducedVec[35]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[34]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[38], notCDom_reduced2AbsSigSum_reducedVec[37]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[40], notCDom_reduced2AbsSigSum_reducedVec[39]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_hi_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[43], notCDom_reduced2AbsSigSum_reducedVec[42]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[41]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[45], notCDom_reduced2AbsSigSum_reducedVec[44]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[47], notCDom_reduced2AbsSigSum_reducedVec[46]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_hi_lo_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[50], notCDom_reduced2AbsSigSum_reducedVec[49]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[48]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[52], notCDom_reduced2AbsSigSum_reducedVec[51]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[54], notCDom_reduced2AbsSigSum_reducedVec[53]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_26 = bits(notCDom_reduced2AbsSigSum, 26, 26) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_27 = bits(notCDom_reduced2AbsSigSum, 27, 27) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_28 = bits(notCDom_reduced2AbsSigSum, 28, 28) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_29 = bits(notCDom_reduced2AbsSigSum, 29, 29) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_30 = bits(notCDom_reduced2AbsSigSum, 30, 30) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_31 = bits(notCDom_reduced2AbsSigSum, 31, 31) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_32 = bits(notCDom_reduced2AbsSigSum, 32, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_33 = bits(notCDom_reduced2AbsSigSum, 33, 33) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_34 = bits(notCDom_reduced2AbsSigSum, 34, 34) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_35 = bits(notCDom_reduced2AbsSigSum, 35, 35) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_36 = bits(notCDom_reduced2AbsSigSum, 36, 36) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_37 = bits(notCDom_reduced2AbsSigSum, 37, 37) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_38 = bits(notCDom_reduced2AbsSigSum, 38, 38) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_39 = bits(notCDom_reduced2AbsSigSum, 39, 39) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_40 = bits(notCDom_reduced2AbsSigSum, 40, 40) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_41 = bits(notCDom_reduced2AbsSigSum, 41, 41) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_42 = bits(notCDom_reduced2AbsSigSum, 42, 42) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_43 = bits(notCDom_reduced2AbsSigSum, 43, 43) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_44 = bits(notCDom_reduced2AbsSigSum, 44, 44) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_45 = bits(notCDom_reduced2AbsSigSum, 45, 45) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_46 = bits(notCDom_reduced2AbsSigSum, 46, 46) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_47 = bits(notCDom_reduced2AbsSigSum, 47, 47) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_48 = bits(notCDom_reduced2AbsSigSum, 48, 48) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_49 = bits(notCDom_reduced2AbsSigSum, 49, 49) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_50 = bits(notCDom_reduced2AbsSigSum, 50, 50) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_51 = bits(notCDom_reduced2AbsSigSum, 51, 51) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_52 = bits(notCDom_reduced2AbsSigSum, 52, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_53 = bits(notCDom_reduced2AbsSigSum, 53, 53) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_54 = bits(notCDom_reduced2AbsSigSum, 54, 54) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _notCDom_normDistReduced2_T_55 = mux(_notCDom_normDistReduced2_T_1, UInt<6>(0h35), UInt<6>(0h36)) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_56 = mux(_notCDom_normDistReduced2_T_2, UInt<6>(0h34), _notCDom_normDistReduced2_T_55) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_57 = mux(_notCDom_normDistReduced2_T_3, UInt<6>(0h33), _notCDom_normDistReduced2_T_56) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_58 = mux(_notCDom_normDistReduced2_T_4, UInt<6>(0h32), _notCDom_normDistReduced2_T_57) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_59 = mux(_notCDom_normDistReduced2_T_5, UInt<6>(0h31), _notCDom_normDistReduced2_T_58) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_60 = mux(_notCDom_normDistReduced2_T_6, UInt<6>(0h30), _notCDom_normDistReduced2_T_59) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_61 = mux(_notCDom_normDistReduced2_T_7, UInt<6>(0h2f), _notCDom_normDistReduced2_T_60) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_62 = mux(_notCDom_normDistReduced2_T_8, UInt<6>(0h2e), _notCDom_normDistReduced2_T_61) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_63 = mux(_notCDom_normDistReduced2_T_9, UInt<6>(0h2d), _notCDom_normDistReduced2_T_62) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_64 = mux(_notCDom_normDistReduced2_T_10, UInt<6>(0h2c), _notCDom_normDistReduced2_T_63) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_65 = mux(_notCDom_normDistReduced2_T_11, UInt<6>(0h2b), _notCDom_normDistReduced2_T_64) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_66 = mux(_notCDom_normDistReduced2_T_12, UInt<6>(0h2a), _notCDom_normDistReduced2_T_65) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_67 = mux(_notCDom_normDistReduced2_T_13, UInt<6>(0h29), _notCDom_normDistReduced2_T_66) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_68 = mux(_notCDom_normDistReduced2_T_14, UInt<6>(0h28), _notCDom_normDistReduced2_T_67) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_69 = mux(_notCDom_normDistReduced2_T_15, UInt<6>(0h27), _notCDom_normDistReduced2_T_68) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_70 = mux(_notCDom_normDistReduced2_T_16, UInt<6>(0h26), _notCDom_normDistReduced2_T_69) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_71 = mux(_notCDom_normDistReduced2_T_17, UInt<6>(0h25), _notCDom_normDistReduced2_T_70) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_72 = mux(_notCDom_normDistReduced2_T_18, UInt<6>(0h24), _notCDom_normDistReduced2_T_71) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_73 = mux(_notCDom_normDistReduced2_T_19, UInt<6>(0h23), _notCDom_normDistReduced2_T_72) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_74 = mux(_notCDom_normDistReduced2_T_20, UInt<6>(0h22), _notCDom_normDistReduced2_T_73) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_75 = mux(_notCDom_normDistReduced2_T_21, UInt<6>(0h21), _notCDom_normDistReduced2_T_74) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_76 = mux(_notCDom_normDistReduced2_T_22, UInt<6>(0h20), _notCDom_normDistReduced2_T_75) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_77 = mux(_notCDom_normDistReduced2_T_23, UInt<5>(0h1f), _notCDom_normDistReduced2_T_76) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_78 = mux(_notCDom_normDistReduced2_T_24, UInt<5>(0h1e), _notCDom_normDistReduced2_T_77) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_79 = mux(_notCDom_normDistReduced2_T_25, UInt<5>(0h1d), _notCDom_normDistReduced2_T_78) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_80 = mux(_notCDom_normDistReduced2_T_26, UInt<5>(0h1c), _notCDom_normDistReduced2_T_79) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_81 = mux(_notCDom_normDistReduced2_T_27, UInt<5>(0h1b), _notCDom_normDistReduced2_T_80) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_82 = mux(_notCDom_normDistReduced2_T_28, UInt<5>(0h1a), _notCDom_normDistReduced2_T_81) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_83 = mux(_notCDom_normDistReduced2_T_29, UInt<5>(0h19), _notCDom_normDistReduced2_T_82) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_84 = mux(_notCDom_normDistReduced2_T_30, UInt<5>(0h18), _notCDom_normDistReduced2_T_83) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_85 = mux(_notCDom_normDistReduced2_T_31, UInt<5>(0h17), _notCDom_normDistReduced2_T_84) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_86 = mux(_notCDom_normDistReduced2_T_32, UInt<5>(0h16), _notCDom_normDistReduced2_T_85) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_87 = mux(_notCDom_normDistReduced2_T_33, UInt<5>(0h15), _notCDom_normDistReduced2_T_86) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_88 = mux(_notCDom_normDistReduced2_T_34, UInt<5>(0h14), _notCDom_normDistReduced2_T_87) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_89 = mux(_notCDom_normDistReduced2_T_35, UInt<5>(0h13), _notCDom_normDistReduced2_T_88) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_90 = mux(_notCDom_normDistReduced2_T_36, UInt<5>(0h12), _notCDom_normDistReduced2_T_89) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_91 = mux(_notCDom_normDistReduced2_T_37, UInt<5>(0h11), _notCDom_normDistReduced2_T_90) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_92 = mux(_notCDom_normDistReduced2_T_38, UInt<5>(0h10), _notCDom_normDistReduced2_T_91) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_93 = mux(_notCDom_normDistReduced2_T_39, UInt<4>(0hf), _notCDom_normDistReduced2_T_92) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_94 = mux(_notCDom_normDistReduced2_T_40, UInt<4>(0he), _notCDom_normDistReduced2_T_93) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_95 = mux(_notCDom_normDistReduced2_T_41, UInt<4>(0hd), _notCDom_normDistReduced2_T_94) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_96 = mux(_notCDom_normDistReduced2_T_42, UInt<4>(0hc), _notCDom_normDistReduced2_T_95) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_97 = mux(_notCDom_normDistReduced2_T_43, UInt<4>(0hb), _notCDom_normDistReduced2_T_96) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_98 = mux(_notCDom_normDistReduced2_T_44, UInt<4>(0ha), _notCDom_normDistReduced2_T_97) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_99 = mux(_notCDom_normDistReduced2_T_45, UInt<4>(0h9), _notCDom_normDistReduced2_T_98) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_100 = mux(_notCDom_normDistReduced2_T_46, UInt<4>(0h8), _notCDom_normDistReduced2_T_99) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_101 = mux(_notCDom_normDistReduced2_T_47, UInt<3>(0h7), _notCDom_normDistReduced2_T_100) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_102 = mux(_notCDom_normDistReduced2_T_48, UInt<3>(0h6), _notCDom_normDistReduced2_T_101) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_103 = mux(_notCDom_normDistReduced2_T_49, UInt<3>(0h5), _notCDom_normDistReduced2_T_102) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_104 = mux(_notCDom_normDistReduced2_T_50, UInt<3>(0h4), _notCDom_normDistReduced2_T_103) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_105 = mux(_notCDom_normDistReduced2_T_51, UInt<2>(0h3), _notCDom_normDistReduced2_T_104) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_106 = mux(_notCDom_normDistReduced2_T_52, UInt<2>(0h2), _notCDom_normDistReduced2_T_105) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _notCDom_normDistReduced2_T_107 = mux(_notCDom_normDistReduced2_T_53, UInt<1>(0h1), _notCDom_normDistReduced2_T_106) @[src/main/scala/chisel3/util/Mux.scala 50:70] node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_54, UInt<1>(0h0), _notCDom_normDistReduced2_T_107) @[src/main/scala/chisel3/util/Mux.scala 50:70] node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 238:56] node _notCDom_sExp_T = cvt(notCDom_nearNormDist) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 239:76] node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 239:46] node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 239:46] node notCDom_sExp = asSInt(_notCDom_sExp_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 239:46] node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 241:27] node notCDom_mainSig = bits(_notCDom_mainSig_T, 109, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 241:50] node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 26, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 245:39] node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 245:55] wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[14] @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 101:30] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 13, 12) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_7_T = bits(_notCDom_reduced4SigExtra_T_1, 15, 14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_7_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_7_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[7], _notCDom_reduced4SigExtra_reducedVec_7_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_8_T = bits(_notCDom_reduced4SigExtra_T_1, 17, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_8_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_8_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[8], _notCDom_reduced4SigExtra_reducedVec_8_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_9_T = bits(_notCDom_reduced4SigExtra_T_1, 19, 18) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_9_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_9_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[9], _notCDom_reduced4SigExtra_reducedVec_9_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_10_T = bits(_notCDom_reduced4SigExtra_T_1, 21, 20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_10_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_10_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[10], _notCDom_reduced4SigExtra_reducedVec_10_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_11_T = bits(_notCDom_reduced4SigExtra_T_1, 23, 22) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_11_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_11_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[11], _notCDom_reduced4SigExtra_reducedVec_11_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_12_T = bits(_notCDom_reduced4SigExtra_T_1, 25, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:33] node _notCDom_reduced4SigExtra_reducedVec_12_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_12_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:54] connect notCDom_reduced4SigExtra_reducedVec[12], _notCDom_reduced4SigExtra_reducedVec_12_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 103:28] node _notCDom_reduced4SigExtra_reducedVec_13_T = bits(_notCDom_reduced4SigExtra_T_1, 26, 26) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 106:15] node _notCDom_reduced4SigExtra_reducedVec_13_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_13_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 106:57] connect notCDom_reduced4SigExtra_reducedVec[13], _notCDom_reduced4SigExtra_reducedVec_13_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 105:38] node notCDom_reduced4SigExtra_lo_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced4SigExtra_lo_lo = cat(notCDom_reduced4SigExtra_lo_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced4SigExtra_lo_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced4SigExtra_lo_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_lo_hi_hi, notCDom_reduced4SigExtra_lo_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_lo_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced4SigExtra_hi_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[9], notCDom_reduced4SigExtra_reducedVec[8]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_hi_lo_hi, notCDom_reduced4SigExtra_reducedVec[7]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced4SigExtra_hi_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[11], notCDom_reduced4SigExtra_reducedVec[10]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced4SigExtra_hi_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[13], notCDom_reduced4SigExtra_reducedVec[12]) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_hi_hi_hi, notCDom_reduced4SigExtra_hi_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 107:20] node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 246:46] node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 52:21] node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _notCDom_reduced4SigExtra_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 76:56] node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 13, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 78:22] node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_7 = shl(UInt<4>(0hf), 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_8 = xor(UInt<8>(0hff), _notCDom_reduced4SigExtra_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_9 = shr(_notCDom_reduced4SigExtra_T_6, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_10 = and(_notCDom_reduced4SigExtra_T_9, _notCDom_reduced4SigExtra_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_12 = shl(_notCDom_reduced4SigExtra_T_11, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_13 = not(_notCDom_reduced4SigExtra_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_14 = and(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_15 = or(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_8, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_17 = shl(_notCDom_reduced4SigExtra_T_16, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_18 = xor(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_17) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_19 = shr(_notCDom_reduced4SigExtra_T_15, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_20 = and(_notCDom_reduced4SigExtra_T_19, _notCDom_reduced4SigExtra_T_18) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_21 = bits(_notCDom_reduced4SigExtra_T_15, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_22 = shl(_notCDom_reduced4SigExtra_T_21, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_23 = not(_notCDom_reduced4SigExtra_T_18) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_24 = and(_notCDom_reduced4SigExtra_T_22, _notCDom_reduced4SigExtra_T_23) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_25 = or(_notCDom_reduced4SigExtra_T_20, _notCDom_reduced4SigExtra_T_24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_26 = bits(_notCDom_reduced4SigExtra_T_18, 6, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_27 = shl(_notCDom_reduced4SigExtra_T_26, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_28 = xor(_notCDom_reduced4SigExtra_T_18, _notCDom_reduced4SigExtra_T_27) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_29 = shr(_notCDom_reduced4SigExtra_T_25, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_30 = and(_notCDom_reduced4SigExtra_T_29, _notCDom_reduced4SigExtra_T_28) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_31 = bits(_notCDom_reduced4SigExtra_T_25, 6, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_32 = shl(_notCDom_reduced4SigExtra_T_31, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_33 = not(_notCDom_reduced4SigExtra_T_28) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_34 = and(_notCDom_reduced4SigExtra_T_32, _notCDom_reduced4SigExtra_T_33) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_35 = or(_notCDom_reduced4SigExtra_T_30, _notCDom_reduced4SigExtra_T_34) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_36 = bits(_notCDom_reduced4SigExtra_T_5, 12, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_37 = bits(_notCDom_reduced4SigExtra_T_36, 3, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_38 = bits(_notCDom_reduced4SigExtra_T_37, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_39 = bits(_notCDom_reduced4SigExtra_T_38, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_40 = bits(_notCDom_reduced4SigExtra_T_38, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_41 = cat(_notCDom_reduced4SigExtra_T_39, _notCDom_reduced4SigExtra_T_40) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_42 = bits(_notCDom_reduced4SigExtra_T_37, 3, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_43 = bits(_notCDom_reduced4SigExtra_T_42, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_44 = bits(_notCDom_reduced4SigExtra_T_42, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_45 = cat(_notCDom_reduced4SigExtra_T_43, _notCDom_reduced4SigExtra_T_44) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_46 = cat(_notCDom_reduced4SigExtra_T_41, _notCDom_reduced4SigExtra_T_45) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_47 = bits(_notCDom_reduced4SigExtra_T_36, 4, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_48 = cat(_notCDom_reduced4SigExtra_T_46, _notCDom_reduced4SigExtra_T_47) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_49 = cat(_notCDom_reduced4SigExtra_T_35, _notCDom_reduced4SigExtra_T_48) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _notCDom_reduced4SigExtra_T_50 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_49) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 245:78] node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_50) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 247:11] node _notCDom_sig_T = shr(notCDom_mainSig, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 249:28] node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 250:28] node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 250:35] node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 250:39] node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 249:12] node _notCDom_completeCancellation_T = bits(notCDom_sig, 55, 54) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 253:21] node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 253:50] node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 257:36] node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 255:12] node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 262:49] node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 263:44] node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 265:32] node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 265:58] node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 270:31] node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 269:35] node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 271:32] node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 270:57] node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 272:10] node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 273:36] node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 272:36] node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 273:61] node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 274:35] node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 271:57] connect io.invalidExc, _io_invalidExc_T_9 @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 268:19] node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 276:48] connect io.rawOut.isNaN, _io_rawOut_isNaN_T @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 276:21] connect io.rawOut.isInf, notNaN_isInfOut @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 277:21] node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 281:14] node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 281:42] node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 280:25] connect io.rawOut.isZero, _io_rawOut_isZero_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 279:22] node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 283:27] node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 284:31] node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 283:54] node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 285:29] node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 285:26] node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 285:48] node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 286:36] node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 284:43] node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 287:26] node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 288:37] node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 287:46] node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 286:48] node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 289:10] node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 289:31] node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 289:28] node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 290:17] node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 289:49] node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 288:50] connect io.rawOut.sign, _io_rawOut_sign_T_17 @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 282:20] node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 291:26] connect io.rawOut.sExp, _io_rawOut_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 291:20] node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 292:25] connect io.rawOut.sig, _io_rawOut_sig_T @[dependencies/hardfloat/hardfloat/src/main/scala/MulAddRecFN.scala 292:19] module RoundAnyRawFNToRecFN_4 : @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 48:5] output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 57:16] node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 89:53] node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 90:53] node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 91:53] node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 92:53] node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 93:53] node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 94:53] node _roundMagUp_T = and(roundingMode_min, io.in.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:27] node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:66] node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:63] node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:42] node adjustedSig = shl(io.in.sig, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 113:22] node doShiftSigDown1 = bits(adjustedSig, 55, 55) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 119:57] wire common_expOut : UInt<12> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 121:31] wire common_fractOut : UInt<52> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 122:31] wire common_overflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 123:37] wire common_totalUnderflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 124:37] wire common_underflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 125:37] wire common_inexact : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 126:37] node _roundMask_T = bits(io.in.sExp, 11, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 155:37] node _roundMask_T_1 = not(_roundMask_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 52:21] node roundMask_msb = bits(_roundMask_T_1, 11, 11) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs = bits(_roundMask_T_1, 10, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_1 = bits(roundMask_lsbs, 10, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_1 = bits(roundMask_lsbs, 9, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_2 = bits(roundMask_lsbs_1, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 8, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_3 = bits(roundMask_lsbs_2, 8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_3 = bits(roundMask_lsbs_2, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_4 = bits(roundMask_lsbs_3, 7, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_4 = bits(roundMask_lsbs_3, 6, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_5 = bits(roundMask_lsbs_4, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_5 = bits(roundMask_lsbs_4, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 76:56] node _roundMask_T_2 = bits(roundMask_shift, 63, 13) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 78:22] node _roundMask_T_3 = bits(_roundMask_T_2, 31, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_4 = shl(UInt<16>(0hffff), 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_5 = xor(UInt<32>(0hffffffff), _roundMask_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_6 = shr(_roundMask_T_3, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_8 = bits(_roundMask_T_3, 15, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_9 = shl(_roundMask_T_8, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_10 = not(_roundMask_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_13 = bits(_roundMask_T_5, 23, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_14 = shl(_roundMask_T_13, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_16 = shr(_roundMask_T_12, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_18 = bits(_roundMask_T_12, 23, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_19 = shl(_roundMask_T_18, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_20 = not(_roundMask_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_23 = bits(_roundMask_T_15, 27, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_24 = shl(_roundMask_T_23, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_26 = shr(_roundMask_T_22, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_28 = bits(_roundMask_T_22, 27, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_29 = shl(_roundMask_T_28, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_30 = not(_roundMask_T_25) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_33 = bits(_roundMask_T_25, 29, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_34 = shl(_roundMask_T_33, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_36 = shr(_roundMask_T_32, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_38 = bits(_roundMask_T_32, 29, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_39 = shl(_roundMask_T_38, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_40 = not(_roundMask_T_35) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_43 = bits(_roundMask_T_35, 30, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_44 = shl(_roundMask_T_43, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_45 = xor(_roundMask_T_35, _roundMask_T_44) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_46 = shr(_roundMask_T_42, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_47 = and(_roundMask_T_46, _roundMask_T_45) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_48 = bits(_roundMask_T_42, 30, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_49 = shl(_roundMask_T_48, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_50 = not(_roundMask_T_45) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_51 = and(_roundMask_T_49, _roundMask_T_50) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_52 = or(_roundMask_T_47, _roundMask_T_51) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_53 = bits(_roundMask_T_2, 50, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_54 = bits(_roundMask_T_53, 15, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_55 = shl(UInt<8>(0hff), 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_56 = xor(UInt<16>(0hffff), _roundMask_T_55) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_57 = shr(_roundMask_T_54, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_58 = and(_roundMask_T_57, _roundMask_T_56) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_59 = bits(_roundMask_T_54, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_60 = shl(_roundMask_T_59, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_61 = not(_roundMask_T_56) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_62 = and(_roundMask_T_60, _roundMask_T_61) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_63 = or(_roundMask_T_58, _roundMask_T_62) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_64 = bits(_roundMask_T_56, 11, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_65 = shl(_roundMask_T_64, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_66 = xor(_roundMask_T_56, _roundMask_T_65) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_67 = shr(_roundMask_T_63, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_68 = and(_roundMask_T_67, _roundMask_T_66) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_69 = bits(_roundMask_T_63, 11, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_70 = shl(_roundMask_T_69, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_71 = not(_roundMask_T_66) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_72 = and(_roundMask_T_70, _roundMask_T_71) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_73 = or(_roundMask_T_68, _roundMask_T_72) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_74 = bits(_roundMask_T_66, 13, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_75 = shl(_roundMask_T_74, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_76 = xor(_roundMask_T_66, _roundMask_T_75) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_77 = shr(_roundMask_T_73, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_78 = and(_roundMask_T_77, _roundMask_T_76) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_79 = bits(_roundMask_T_73, 13, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_80 = shl(_roundMask_T_79, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_81 = not(_roundMask_T_76) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_82 = and(_roundMask_T_80, _roundMask_T_81) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_83 = or(_roundMask_T_78, _roundMask_T_82) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_84 = bits(_roundMask_T_76, 14, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_85 = shl(_roundMask_T_84, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_86 = xor(_roundMask_T_76, _roundMask_T_85) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_87 = shr(_roundMask_T_83, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_88 = and(_roundMask_T_87, _roundMask_T_86) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_89 = bits(_roundMask_T_83, 14, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_90 = shl(_roundMask_T_89, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_91 = not(_roundMask_T_86) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_92 = and(_roundMask_T_90, _roundMask_T_91) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_93 = or(_roundMask_T_88, _roundMask_T_92) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_94 = bits(_roundMask_T_53, 18, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_95 = bits(_roundMask_T_94, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_96 = bits(_roundMask_T_95, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_97 = bits(_roundMask_T_95, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_98 = cat(_roundMask_T_96, _roundMask_T_97) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_99 = bits(_roundMask_T_94, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_100 = cat(_roundMask_T_98, _roundMask_T_99) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_101 = cat(_roundMask_T_93, _roundMask_T_100) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_102 = cat(_roundMask_T_52, _roundMask_T_101) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_103 = not(_roundMask_T_102) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:32] node _roundMask_T_104 = mux(roundMask_msb_5, UInt<1>(0h0), _roundMask_T_103) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:21] node _roundMask_T_105 = not(_roundMask_T_104) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:17] node _roundMask_T_106 = not(_roundMask_T_105) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:32] node _roundMask_T_107 = mux(roundMask_msb_4, UInt<1>(0h0), _roundMask_T_106) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:21] node _roundMask_T_108 = not(_roundMask_T_107) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:17] node _roundMask_T_109 = not(_roundMask_T_108) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:32] node _roundMask_T_110 = mux(roundMask_msb_3, UInt<1>(0h0), _roundMask_T_109) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:21] node _roundMask_T_111 = not(_roundMask_T_110) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:17] node _roundMask_T_112 = not(_roundMask_T_111) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:32] node _roundMask_T_113 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_112) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:21] node _roundMask_T_114 = not(_roundMask_T_113) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:17] node _roundMask_T_115 = cat(_roundMask_T_114, UInt<3>(0h7)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 68:58] node roundMask_msb_6 = bits(roundMask_lsbs_1, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_6 = bits(roundMask_lsbs_1, 8, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_7 = bits(roundMask_lsbs_6, 8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_7 = bits(roundMask_lsbs_6, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_8 = bits(roundMask_lsbs_7, 7, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_8 = bits(roundMask_lsbs_7, 6, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_9 = bits(roundMask_lsbs_8, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_9 = bits(roundMask_lsbs_8, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_9) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 76:56] node _roundMask_T_116 = bits(roundMask_shift_1, 2, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 78:22] node _roundMask_T_117 = bits(_roundMask_T_116, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_118 = bits(_roundMask_T_117, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_119 = bits(_roundMask_T_117, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_120 = cat(_roundMask_T_118, _roundMask_T_119) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_121 = bits(_roundMask_T_116, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_122 = cat(_roundMask_T_120, _roundMask_T_121) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_123 = mux(roundMask_msb_9, _roundMask_T_122, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 62:24] node _roundMask_T_124 = mux(roundMask_msb_8, _roundMask_T_123, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 62:24] node _roundMask_T_125 = mux(roundMask_msb_7, _roundMask_T_124, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 62:24] node _roundMask_T_126 = mux(roundMask_msb_6, _roundMask_T_125, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 62:24] node _roundMask_T_127 = mux(roundMask_msb_1, _roundMask_T_115, _roundMask_T_126) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 67:24] node _roundMask_T_128 = mux(roundMask_msb, _roundMask_T_127, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 62:24] node _roundMask_T_129 = or(_roundMask_T_128, doShiftSigDown1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 158:23] node roundMask = cat(_roundMask_T_129, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 158:42] node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 161:41] node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 161:53] node _roundPosMask_T = not(shiftedRoundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 162:28] node roundPosMask = and(_roundPosMask_T, roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 162:46] node _roundPosBit_T = and(adjustedSig, roundPosMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 163:40] node roundPosBit = orr(_roundPosBit_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 163:56] node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 164:42] node anyRoundExtra = orr(_anyRoundExtra_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 164:62] node anyRound = or(roundPosBit, anyRoundExtra) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 165:36] node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 168:38] node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 168:67] node _roundIncr_T_2 = and(roundMagUp, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 170:29] node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 169:31] node _roundedSig_T = or(adjustedSig, roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:32] node _roundedSig_T_1 = shr(_roundedSig_T, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:44] node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:49] node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:49] node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 175:30] node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:64] node _roundedSig_T_6 = shr(roundMask, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 176:35] node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<55>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:25] node _roundedSig_T_8 = not(_roundedSig_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:21] node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:57] node _roundedSig_T_10 = not(roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:32] node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:30] node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:43] node _roundedSig_T_13 = and(roundingMode_odd, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:42] node _roundedSig_T_14 = shr(roundPosMask, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:67] node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:24] node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:47] node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 172:16] node _sRoundedExp_T = shr(roundedSig, 53) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:54] node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:76] node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:40] node _common_expOut_T = bits(sRoundedExp, 11, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 186:37] connect common_expOut, _common_expOut_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 186:23] node _common_fractOut_T = bits(roundedSig, 52, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 189:27] node _common_fractOut_T_1 = bits(roundedSig, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 190:27] node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 188:16] connect common_fractOut, _common_fractOut_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 187:25] node _common_overflow_T = shr(sRoundedExp, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 195:30] node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 195:50] connect common_overflow, _common_overflow_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 192:25] node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<11>(0h3ce))) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 199:31] connect common_totalUnderflow, _common_totalUnderflow_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 196:31] node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:45] node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:61] node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:16] node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:44] node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:30] node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:63] node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:70] node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:49] node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 206:38] node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 206:67] node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 208:29] node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 207:46] node _roundCarry_T = bits(roundedSig, 54, 54) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 211:27] node _roundCarry_T_1 = bits(roundedSig, 53, 53) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 212:27] node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 210:16] node _common_underflow_T = shr(io.in.sExp, 11) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:49] node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:64] node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:32] node _common_underflow_T_3 = bits(roundMask, 3, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:57] node _common_underflow_T_4 = bits(roundMask, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:71] node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:30] node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:72] node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 221:49] node _common_underflow_T_8 = bits(roundMask, 4, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 223:49] node _common_underflow_T_9 = bits(roundMask, 3, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 224:49] node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 222:39] node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 222:34] node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 221:77] node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 225:38] node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 226:45] node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 226:60] node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 221:27] node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:76] node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 216:40] connect common_underflow, _common_underflow_T_18 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 214:26] node _common_inexact_T = or(common_totalUnderflow, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 229:49] connect common_inexact, _common_inexact_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 229:24] node isNaNOut = or(io.invalidExc, io.in.isNaN) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 234:34] node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 235:49] node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:22] node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:36] node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:33] node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:64] node commonCase = and(_commonCase_T_2, _commonCase_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:61] node overflow = and(commonCase, common_overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 237:32] node underflow = and(commonCase, common_underflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 238:32] node _inexact_T = and(commonCase, common_inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 239:43] node inexact = or(overflow, _inexact_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 239:28] node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 242:32] node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 242:60] node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:20] node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:60] node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:45] node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 245:42] node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 245:39] node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 247:45] node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 247:32] node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 249:22] node _expOut_T = or(io.in.isZero, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:32] node _expOut_T_1 = mux(_expOut_T, UInt<12>(0he00), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:18] node _expOut_T_2 = not(_expOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:14] node _expOut_T_3 = and(common_expOut, _expOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 251:24] node _expOut_T_4 = not(UInt<12>(0h3ce)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 257:19] node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 256:18] node _expOut_T_6 = not(_expOut_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 256:14] node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 255:17] node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<12>(0h400), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 260:18] node _expOut_T_9 = not(_expOut_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 260:14] node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 259:17] node _expOut_T_11 = mux(notNaN_isInfOut, UInt<12>(0h200), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 264:18] node _expOut_T_12 = not(_expOut_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 264:14] node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 263:17] node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<12>(0h3ce), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 268:16] node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 267:18] node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<12>(0hbff), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 272:16] node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 271:15] node _expOut_T_18 = mux(notNaN_isInfOut, UInt<12>(0hc00), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 276:16] node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 275:15] node _expOut_T_20 = mux(isNaNOut, UInt<12>(0he00), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 277:16] node expOut = or(_expOut_T_19, _expOut_T_20) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 276:73] node _fractOut_T = or(isNaNOut, io.in.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:22] node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:38] node _fractOut_T_2 = mux(isNaNOut, UInt<52>(0h8000000000000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 280:16] node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:12] node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<52>(0hfffffffffffff), UInt<52>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 283:13] node fractOut = or(_fractOut_T_3, _fractOut_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 282:11] node _io_out_T = cat(signOut, expOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:23] node _io_out_T_1 = cat(_io_out_T, fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:33] connect io.out, _io_out_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:12] node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:23] node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:41] node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:53] node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:66] connect io.exceptionFlags, _io_exceptionFlags_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 286:23] module RoundRawFNToRecFN_1 : @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 294:5] output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 297:16] inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_4 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 308:15] connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 311:44] connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 312:44] connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 314:44] connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 315:44] connect io.out, roundAnyRawFNToRecFN.io.out @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 316:23] connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 317:23] module MulAddRecFNPipe_l2_e11_s53 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 633:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 633:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 633:7] output io : { flip validin : UInt<1>, flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>, validout : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 638:16] inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 654:41] inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 655:42] connect mulAddRecFNToRaw_preMul.io.op, io.op @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 657:35] connect mulAddRecFNToRaw_preMul.io.a, io.a @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 658:35] connect mulAddRecFNToRaw_preMul.io.b, io.b @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 659:35] connect mulAddRecFNToRaw_preMul.io.c, io.c @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 660:35] node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 663:45] node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 664:50] wire valid_stage0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 667:28] wire roundingMode_stage0 : UInt<3> @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 668:35] wire detectTininess_stage0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 669:37] regreset mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v, io.validin @[src/main/scala/chisel3/util/Valid.scala 141:24] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<13>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<6>, highAlignedSigC : UInt<55>, bit0AlignedSigC : UInt<1>}, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when io.validin : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b, mulAddRecFNToRaw_preMul.io.toPostMul @[src/main/scala/chisel3/util/Valid.scala 142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out : { valid : UInt<1>, bits : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<13>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<6>, highAlignedSigC : UInt<55>, bit0AlignedSigC : UInt<1>}} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.valid, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.bit0AlignedSigC @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.highAlignedSigC @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CDom_CAlignDist @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CIsDominant @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.doSubMags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.sExpSum @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroC @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfC @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNC @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.signProd @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroB @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfB @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroA @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfA @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNAOrB @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isSigNaNAny @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 672:46] regreset mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v, io.validin @[src/main/scala/chisel3/util/Valid.scala 141:24] reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b : UInt<107>, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when io.validin : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b, mulAddResult @[src/main/scala/chisel3/util/Valid.scala 142:26] wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out : { valid : UInt<1>, bits : UInt<107>} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.valid, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 673:46] regreset mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v, io.validin @[src/main/scala/chisel3/util/Valid.scala 141:24] reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b : UInt<3>, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when io.validin : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b, io.roundingMode @[src/main/scala/chisel3/util/Valid.scala 142:26] wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.valid, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect mulAddRecFNToRaw_postMul.io.roundingMode, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 674:46] regreset roundingMode_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect roundingMode_stage0_pipe_v, io.validin @[src/main/scala/chisel3/util/Valid.scala 141:24] reg roundingMode_stage0_pipe_b : UInt<3>, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when io.validin : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect roundingMode_stage0_pipe_b, io.roundingMode @[src/main/scala/chisel3/util/Valid.scala 142:26] wire roundingMode_stage0_pipe_out : { valid : UInt<1>, bits : UInt<3>} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect roundingMode_stage0_pipe_out.valid, roundingMode_stage0_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect roundingMode_stage0_pipe_out.bits, roundingMode_stage0_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect roundingMode_stage0, roundingMode_stage0_pipe_out.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 675:46] regreset detectTininess_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect detectTininess_stage0_pipe_v, io.validin @[src/main/scala/chisel3/util/Valid.scala 141:24] reg detectTininess_stage0_pipe_b : UInt<1>, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when io.validin : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect detectTininess_stage0_pipe_b, io.detectTininess @[src/main/scala/chisel3/util/Valid.scala 142:26] wire detectTininess_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect detectTininess_stage0_pipe_out.valid, detectTininess_stage0_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect detectTininess_stage0_pipe_out.bits, detectTininess_stage0_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect detectTininess_stage0, detectTininess_stage0_pipe_out.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 676:46] regreset valid_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect valid_stage0_pipe_v, io.validin @[src/main/scala/chisel3/util/Valid.scala 141:24] reg valid_stage0_pipe_b : UInt<1>, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when io.validin : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect valid_stage0_pipe_b, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 142:26] wire valid_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect valid_stage0_pipe_out.valid, valid_stage0_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect valid_stage0_pipe_out.bits, valid_stage0_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect valid_stage0, valid_stage0_pipe_out.valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 677:46] inst roundRawFNToRecFN of RoundRawFNToRecFN_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 682:35] regreset roundRawFNToRecFN_io_invalidExc_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect roundRawFNToRecFN_io_invalidExc_pipe_v, valid_stage0 @[src/main/scala/chisel3/util/Valid.scala 141:24] reg roundRawFNToRecFN_io_invalidExc_pipe_b : UInt<1>, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when valid_stage0 : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect roundRawFNToRecFN_io_invalidExc_pipe_b, mulAddRecFNToRaw_postMul.io.invalidExc @[src/main/scala/chisel3/util/Valid.scala 142:26] wire roundRawFNToRecFN_io_invalidExc_pipe_out : { valid : UInt<1>, bits : UInt<1>} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect roundRawFNToRecFN_io_invalidExc_pipe_out.valid, roundRawFNToRecFN_io_invalidExc_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect roundRawFNToRecFN_io_invalidExc_pipe_out.bits, roundRawFNToRecFN_io_invalidExc_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect roundRawFNToRecFN.io.invalidExc, roundRawFNToRecFN_io_invalidExc_pipe_out.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 685:45] regreset roundRawFNToRecFN_io_in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect roundRawFNToRecFN_io_in_pipe_v, valid_stage0 @[src/main/scala/chisel3/util/Valid.scala 141:24] reg roundRawFNToRecFN_io_in_pipe_b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when valid_stage0 : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect roundRawFNToRecFN_io_in_pipe_b, mulAddRecFNToRaw_postMul.io.rawOut @[src/main/scala/chisel3/util/Valid.scala 142:26] wire roundRawFNToRecFN_io_in_pipe_out : { valid : UInt<1>, bits : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect roundRawFNToRecFN_io_in_pipe_out.valid, roundRawFNToRecFN_io_in_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect roundRawFNToRecFN_io_in_pipe_out.bits, roundRawFNToRecFN_io_in_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect roundRawFNToRecFN.io.in.sig, roundRawFNToRecFN_io_in_pipe_out.bits.sig @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 686:45] connect roundRawFNToRecFN.io.in.sExp, roundRawFNToRecFN_io_in_pipe_out.bits.sExp @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 686:45] connect roundRawFNToRecFN.io.in.sign, roundRawFNToRecFN_io_in_pipe_out.bits.sign @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 686:45] connect roundRawFNToRecFN.io.in.isZero, roundRawFNToRecFN_io_in_pipe_out.bits.isZero @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 686:45] connect roundRawFNToRecFN.io.in.isInf, roundRawFNToRecFN_io_in_pipe_out.bits.isInf @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 686:45] connect roundRawFNToRecFN.io.in.isNaN, roundRawFNToRecFN_io_in_pipe_out.bits.isNaN @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 686:45] regreset roundRawFNToRecFN_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect roundRawFNToRecFN_io_roundingMode_pipe_v, valid_stage0 @[src/main/scala/chisel3/util/Valid.scala 141:24] reg roundRawFNToRecFN_io_roundingMode_pipe_b : UInt<3>, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when valid_stage0 : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect roundRawFNToRecFN_io_roundingMode_pipe_b, roundingMode_stage0 @[src/main/scala/chisel3/util/Valid.scala 142:26] wire roundRawFNToRecFN_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect roundRawFNToRecFN_io_roundingMode_pipe_out.valid, roundRawFNToRecFN_io_roundingMode_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect roundRawFNToRecFN_io_roundingMode_pipe_out.bits, roundRawFNToRecFN_io_roundingMode_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect roundRawFNToRecFN.io.roundingMode, roundRawFNToRecFN_io_roundingMode_pipe_out.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 687:45] regreset roundRawFNToRecFN_io_detectTininess_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect roundRawFNToRecFN_io_detectTininess_pipe_v, valid_stage0 @[src/main/scala/chisel3/util/Valid.scala 141:24] reg roundRawFNToRecFN_io_detectTininess_pipe_b : UInt<1>, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when valid_stage0 : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect roundRawFNToRecFN_io_detectTininess_pipe_b, detectTininess_stage0 @[src/main/scala/chisel3/util/Valid.scala 142:26] wire roundRawFNToRecFN_io_detectTininess_pipe_out : { valid : UInt<1>, bits : UInt<1>} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect roundRawFNToRecFN_io_detectTininess_pipe_out.valid, roundRawFNToRecFN_io_detectTininess_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect roundRawFNToRecFN_io_detectTininess_pipe_out.bits, roundRawFNToRecFN_io_detectTininess_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect roundRawFNToRecFN.io.detectTininess, roundRawFNToRecFN_io_detectTininess_pipe_out.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 688:45] regreset io_validout_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect io_validout_pipe_v, valid_stage0 @[src/main/scala/chisel3/util/Valid.scala 141:24] reg io_validout_pipe_b : UInt<1>, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when valid_stage0 : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect io_validout_pipe_b, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 142:26] wire io_validout_pipe_out : { valid : UInt<1>, bits : UInt<1>} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect io_validout_pipe_out.valid, io_validout_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect io_validout_pipe_out.bits, io_validout_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect io.validout, io_validout_pipe_out.valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 689:45] connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 691:38] connect io.out, roundRawFNToRecFN.io.out @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 693:23] connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 694:23] module FPUFMAPipe_l4_f64 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 697:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 697:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 697:7] output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 702:14] reg valid : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 707:22] connect valid, io.in.valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 707:22] reg in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 708:15] when io.in.valid : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 709:22] node one = shl(UInt<1>(0h1), 63) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 710:19] node _zero_T = xor(io.in.bits.in1, io.in.bits.in2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 711:32] node _zero_T_1 = shl(UInt<1>(0h1), 64) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 711:57] node zero = and(_zero_T, _zero_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 711:50] connect in, io.in.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 714:8] when io.in.bits.swap23 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 715:23] connect in.in2, one @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 715:32] node _T = or(io.in.bits.ren3, io.in.bits.swap23) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 716:21] node _T_1 = eq(_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 716:11] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 716:37] connect in.in3, zero @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 716:46] inst fma of MulAddRecFNPipe_l2_e11_s53 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 719:19] connect fma.clock, clock connect fma.reset, reset connect fma.io.validin, valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 720:18] connect fma.io.op, in.fmaCmd @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 721:13] connect fma.io.roundingMode, in.rm @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 722:23] connect fma.io.detectTininess, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 723:25] connect fma.io.a, in.in1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 724:12] connect fma.io.b, in.in2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 725:12] connect fma.io.c, in.in3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 726:12] wire res : { data : UInt<65>, exc : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 728:17] node _res_data_maskedNaN_T = not(UInt<65>(0h1010000000000000)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 413:27] node res_data_maskedNaN = and(fma.io.out, _res_data_maskedNaN_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 413:25] node _res_data_T = bits(fma.io.out, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node _res_data_T_1 = andr(_res_data_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node _res_data_T_2 = mux(_res_data_T_1, res_data_maskedNaN, fma.io.out) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 414:10] connect res.data, _res_data_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 729:12] connect res.exc, fma.io.exceptionFlags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 730:11] regreset io_out_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Valid.scala 141:24] connect io_out_pipe_v, fma.io.validout @[src/main/scala/chisel3/util/Valid.scala 141:24] reg io_out_pipe_b : { data : UInt<65>, exc : UInt<5>}, clock @[src/main/scala/chisel3/util/Valid.scala 142:26] when fma.io.validout : @[src/main/scala/chisel3/util/Valid.scala 142:26] connect io_out_pipe_b, res @[src/main/scala/chisel3/util/Valid.scala 142:26] wire io_out_pipe_out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}} @[src/main/scala/chisel3/util/Valid.scala 135:21] connect io_out_pipe_out.valid, io_out_pipe_v @[src/main/scala/chisel3/util/Valid.scala 136:17] connect io_out_pipe_out.bits, io_out_pipe_b @[src/main/scala/chisel3/util/Valid.scala 137:16] connect io.out, io_out_pipe_out @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 732:10] module DivSqrtRawFN_small : @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 199:5] input clock : Clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 199:5] input reset : Reset @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 199:5] output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 202:16] regreset cycleNum : UInt<5>, clock, reset, UInt<5>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 223:33] regreset inReady : UInt<1>, clock, reset, UInt<1>(0h1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 224:33] regreset rawOutValid : UInt<1>, clock, reset, UInt<1>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 225:33] reg sqrtOp_Z : UInt<1>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 227:29] reg majorExc_Z : UInt<1>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 228:29] reg isNaN_Z : UInt<1>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 230:29] reg isInf_Z : UInt<1>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 231:29] reg isZero_Z : UInt<1>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 232:29] reg sign_Z : UInt<1>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 233:29] reg sExp_Z : SInt<10>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 234:29] reg fractB_Z : UInt<24>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 235:29] reg roundingMode_Z : UInt<3>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 236:29] reg rem_Z : UInt<26>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 242:29] reg notZeroRem_Z : UInt<1>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 243:29] reg sigX_Z : UInt<26>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 244:29] node _notSigNaNIn_invalidExc_S_div_T = and(io.a.isZero, io.b.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 253:24] node _notSigNaNIn_invalidExc_S_div_T_1 = and(io.a.isInf, io.b.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 253:59] node notSigNaNIn_invalidExc_S_div = or(_notSigNaNIn_invalidExc_S_div_T, _notSigNaNIn_invalidExc_S_div_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 253:42] node _notSigNaNIn_invalidExc_S_sqrt_T = eq(io.a.isNaN, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 255:9] node _notSigNaNIn_invalidExc_S_sqrt_T_1 = eq(io.a.isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 255:27] node _notSigNaNIn_invalidExc_S_sqrt_T_2 = and(_notSigNaNIn_invalidExc_S_sqrt_T, _notSigNaNIn_invalidExc_S_sqrt_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 255:24] node notSigNaNIn_invalidExc_S_sqrt = and(_notSigNaNIn_invalidExc_S_sqrt_T_2, io.a.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 255:43] node _majorExc_S_T = bits(io.a.sig, 22, 22) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:56] node _majorExc_S_T_1 = eq(_majorExc_S_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:49] node _majorExc_S_T_2 = and(io.a.isNaN, _majorExc_S_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:46] node _majorExc_S_T_3 = or(_majorExc_S_T_2, notSigNaNIn_invalidExc_S_sqrt) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 258:38] node _majorExc_S_T_4 = bits(io.a.sig, 22, 22) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:56] node _majorExc_S_T_5 = eq(_majorExc_S_T_4, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:49] node _majorExc_S_T_6 = and(io.a.isNaN, _majorExc_S_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:46] node _majorExc_S_T_7 = bits(io.b.sig, 22, 22) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:56] node _majorExc_S_T_8 = eq(_majorExc_S_T_7, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:49] node _majorExc_S_T_9 = and(io.b.isNaN, _majorExc_S_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:46] node _majorExc_S_T_10 = or(_majorExc_S_T_6, _majorExc_S_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 259:38] node _majorExc_S_T_11 = or(_majorExc_S_T_10, notSigNaNIn_invalidExc_S_div) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 259:66] node _majorExc_S_T_12 = eq(io.a.isNaN, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 261:18] node _majorExc_S_T_13 = eq(io.a.isInf, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 261:36] node _majorExc_S_T_14 = and(_majorExc_S_T_12, _majorExc_S_T_13) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 261:33] node _majorExc_S_T_15 = and(_majorExc_S_T_14, io.b.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 261:51] node _majorExc_S_T_16 = or(_majorExc_S_T_11, _majorExc_S_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 260:46] node majorExc_S = mux(io.sqrtOp, _majorExc_S_T_3, _majorExc_S_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 257:12] node _isNaN_S_T = or(io.a.isNaN, notSigNaNIn_invalidExc_S_sqrt) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 265:26] node _isNaN_S_T_1 = or(io.a.isNaN, io.b.isNaN) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 266:26] node _isNaN_S_T_2 = or(_isNaN_S_T_1, notSigNaNIn_invalidExc_S_div) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 266:42] node isNaN_S = mux(io.sqrtOp, _isNaN_S_T, _isNaN_S_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 264:12] node _isInf_S_T = or(io.a.isInf, io.b.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 268:63] node isInf_S = mux(io.sqrtOp, io.a.isInf, _isInf_S_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 268:23] node _isZero_S_T = or(io.a.isZero, io.b.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 269:64] node isZero_S = mux(io.sqrtOp, io.a.isZero, _isZero_S_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 269:23] node _sign_S_T = eq(io.sqrtOp, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 270:33] node _sign_S_T_1 = and(_sign_S_T, io.b.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 270:45] node sign_S = xor(io.a.sign, _sign_S_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 270:30] node _specialCaseA_S_T = or(io.a.isNaN, io.a.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 272:39] node specialCaseA_S = or(_specialCaseA_S_T, io.a.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 272:55] node _specialCaseB_S_T = or(io.b.isNaN, io.b.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 273:39] node specialCaseB_S = or(_specialCaseB_S_T, io.b.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 273:55] node _normalCase_S_div_T = eq(specialCaseA_S, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 274:28] node _normalCase_S_div_T_1 = eq(specialCaseB_S, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 274:48] node normalCase_S_div = and(_normalCase_S_div_T, _normalCase_S_div_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 274:45] node _normalCase_S_sqrt_T = eq(specialCaseA_S, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 275:29] node _normalCase_S_sqrt_T_1 = eq(io.a.sign, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 275:49] node normalCase_S_sqrt = and(_normalCase_S_sqrt_T, _normalCase_S_sqrt_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 275:46] node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 276:27] node _sExpQuot_S_div_T = bits(io.b.sExp, 8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 280:28] node _sExpQuot_S_div_T_1 = bits(io.b.sExp, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 280:52] node _sExpQuot_S_div_T_2 = not(_sExpQuot_S_div_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 280:40] node _sExpQuot_S_div_T_3 = cat(_sExpQuot_S_div_T, _sExpQuot_S_div_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 280:16] node _sExpQuot_S_div_T_4 = asSInt(_sExpQuot_S_div_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 280:71] node sExpQuot_S_div = add(io.a.sExp, _sExpQuot_S_div_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 279:21] node _sSatExpQuot_S_div_T = leq(asSInt(UInt<10>(0h1c0)), sExpQuot_S_div) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 283:48] node _sSatExpQuot_S_div_T_1 = bits(sExpQuot_S_div, 9, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 285:31] node _sSatExpQuot_S_div_T_2 = mux(_sSatExpQuot_S_div_T, UInt<3>(0h6), _sSatExpQuot_S_div_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 283:16] node _sSatExpQuot_S_div_T_3 = bits(sExpQuot_S_div, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 287:27] node _sSatExpQuot_S_div_T_4 = cat(_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 283:12] node sSatExpQuot_S_div = asSInt(_sSatExpQuot_S_div_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 288:11] node _evenSqrt_S_T = bits(io.a.sExp, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 290:48] node _evenSqrt_S_T_1 = eq(_evenSqrt_S_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 290:35] node evenSqrt_S = and(io.sqrtOp, _evenSqrt_S_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 290:32] node _oddSqrt_S_T = bits(io.a.sExp, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 291:48] node oddSqrt_S = and(io.sqrtOp, _oddSqrt_S_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 291:32] node idle = eq(cycleNum, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 295:25] node entering = and(inReady, io.inValid) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 296:28] node entering_normalCase = and(entering, normalCase_S) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 297:40] node _processTwoBits_T = geq(cycleNum, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 299:35] node processTwoBits = and(_processTwoBits_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 299:42] node _skipCycle2_T = eq(cycleNum, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 300:31] node _skipCycle2_T_1 = bits(sigX_Z, 25, 25) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 300:48] node _skipCycle2_T_2 = and(_skipCycle2_T, _skipCycle2_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 300:39] node skipCycle2 = and(_skipCycle2_T_2, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 300:63] node _T = eq(idle, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 302:11] node _T_1 = or(_T, entering) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 302:18] when _T_1 : @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 302:31] node _inReady_T = eq(normalCase_S, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:28] node _inReady_T_1 = and(entering, _inReady_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:26] node _inReady_T_2 = leq(UInt<1>(0h1), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 316:38] node _inReady_T_3 = mux(_inReady_T_1, _inReady_T_2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:16] node _inReady_T_4 = bits(io.a.sExp, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 307:36] node _inReady_T_5 = leq(UInt<5>(0h18), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 316:38] node _inReady_T_6 = leq(UInt<5>(0h19), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 316:38] node _inReady_T_7 = mux(_inReady_T_4, _inReady_T_5, _inReady_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 307:24] node _inReady_T_8 = leq(UInt<5>(0h1a), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 316:38] node _inReady_T_9 = mux(io.sqrtOp, _inReady_T_7, _inReady_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 306:20] node _inReady_T_10 = mux(entering_normalCase, _inReady_T_9, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 305:16] node _inReady_T_11 = or(_inReady_T_3, _inReady_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:57] node _inReady_T_12 = eq(entering, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:17] node _inReady_T_13 = eq(skipCycle2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:31] node _inReady_T_14 = and(_inReady_T_12, _inReady_T_13) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:28] node _inReady_T_15 = mux(processTwoBits, UInt<2>(0h2), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:61] node _inReady_T_16 = sub(cycleNum, _inReady_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:56] node _inReady_T_17 = tail(_inReady_T_16, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:56] node _inReady_T_18 = leq(_inReady_T_17, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 316:38] node _inReady_T_19 = mux(_inReady_T_14, _inReady_T_18, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:16] node _inReady_T_20 = or(_inReady_T_11, _inReady_T_19) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 311:15] node _inReady_T_21 = leq(UInt<1>(0h1), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 316:38] node _inReady_T_22 = mux(skipCycle2, _inReady_T_21, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 313:16] node _inReady_T_23 = or(_inReady_T_20, _inReady_T_22) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:95] node _inReady_T_24 = bits(_inReady_T_23, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 316:46] connect inReady, _inReady_T_24 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 316:17] node _rawOutValid_T = eq(normalCase_S, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:28] node _rawOutValid_T_1 = and(entering, _rawOutValid_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:26] node _rawOutValid_T_2 = eq(UInt<1>(0h1), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 317:42] node _rawOutValid_T_3 = mux(_rawOutValid_T_1, _rawOutValid_T_2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:16] node _rawOutValid_T_4 = bits(io.a.sExp, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 307:36] node _rawOutValid_T_5 = eq(UInt<5>(0h18), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 317:42] node _rawOutValid_T_6 = eq(UInt<5>(0h19), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 317:42] node _rawOutValid_T_7 = mux(_rawOutValid_T_4, _rawOutValid_T_5, _rawOutValid_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 307:24] node _rawOutValid_T_8 = eq(UInt<5>(0h1a), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 317:42] node _rawOutValid_T_9 = mux(io.sqrtOp, _rawOutValid_T_7, _rawOutValid_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 306:20] node _rawOutValid_T_10 = mux(entering_normalCase, _rawOutValid_T_9, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 305:16] node _rawOutValid_T_11 = or(_rawOutValid_T_3, _rawOutValid_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:57] node _rawOutValid_T_12 = eq(entering, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:17] node _rawOutValid_T_13 = eq(skipCycle2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:31] node _rawOutValid_T_14 = and(_rawOutValid_T_12, _rawOutValid_T_13) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:28] node _rawOutValid_T_15 = mux(processTwoBits, UInt<2>(0h2), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:61] node _rawOutValid_T_16 = sub(cycleNum, _rawOutValid_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:56] node _rawOutValid_T_17 = tail(_rawOutValid_T_16, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:56] node _rawOutValid_T_18 = eq(_rawOutValid_T_17, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 317:42] node _rawOutValid_T_19 = mux(_rawOutValid_T_14, _rawOutValid_T_18, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:16] node _rawOutValid_T_20 = or(_rawOutValid_T_11, _rawOutValid_T_19) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 311:15] node _rawOutValid_T_21 = eq(UInt<1>(0h1), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 317:42] node _rawOutValid_T_22 = mux(skipCycle2, _rawOutValid_T_21, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 313:16] node _rawOutValid_T_23 = or(_rawOutValid_T_20, _rawOutValid_T_22) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:95] node _rawOutValid_T_24 = bits(_rawOutValid_T_23, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 317:51] connect rawOutValid, _rawOutValid_T_24 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 317:21] node _cycleNum_T = eq(normalCase_S, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:28] node _cycleNum_T_1 = and(entering, _cycleNum_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:26] node _cycleNum_T_2 = mux(_cycleNum_T_1, UInt<1>(0h1), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:16] node _cycleNum_T_3 = bits(io.a.sExp, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 307:36] node _cycleNum_T_4 = mux(_cycleNum_T_3, UInt<5>(0h18), UInt<5>(0h19)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 307:24] node _cycleNum_T_5 = mux(io.sqrtOp, _cycleNum_T_4, UInt<5>(0h1a)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 306:20] node _cycleNum_T_6 = mux(entering_normalCase, _cycleNum_T_5, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 305:16] node _cycleNum_T_7 = or(_cycleNum_T_2, _cycleNum_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:57] node _cycleNum_T_8 = eq(entering, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:17] node _cycleNum_T_9 = eq(skipCycle2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:31] node _cycleNum_T_10 = and(_cycleNum_T_8, _cycleNum_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:28] node _cycleNum_T_11 = mux(processTwoBits, UInt<2>(0h2), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:61] node _cycleNum_T_12 = sub(cycleNum, _cycleNum_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:56] node _cycleNum_T_13 = tail(_cycleNum_T_12, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:56] node _cycleNum_T_14 = mux(_cycleNum_T_10, _cycleNum_T_13, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:16] node _cycleNum_T_15 = or(_cycleNum_T_7, _cycleNum_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 311:15] node _cycleNum_T_16 = mux(skipCycle2, UInt<1>(0h1), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 313:16] node _cycleNum_T_17 = or(_cycleNum_T_15, _cycleNum_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:95] connect cycleNum, _cycleNum_T_17 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 318:18] connect io.inReady, inReady @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 321:16] when entering : @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 325:21] connect sqrtOp_Z, io.sqrtOp @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 326:20] connect majorExc_Z, majorExc_S @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 327:20] connect isNaN_Z, isNaN_S @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 328:20] connect isInf_Z, isInf_S @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 329:20] connect isZero_Z, isZero_S @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 330:20] connect sign_Z, sign_S @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 331:20] node _sExp_Z_T = shr(io.a.sExp, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 334:29] node _sExp_Z_T_1 = add(_sExp_Z_T, asSInt(UInt<9>(0h80))) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 334:34] node _sExp_Z_T_2 = mux(io.sqrtOp, _sExp_Z_T_1, sSatExpQuot_S_div) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 333:16] connect sExp_Z, _sExp_Z_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 332:16] connect roundingMode_Z, io.roundingMode @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 337:24] node _T_2 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 339:23] node _T_3 = and(_T_2, sqrtOp_Z) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 339:33] node _T_4 = or(entering, _T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 339:20] when _T_4 : @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 339:46] node _fractB_Z_T = eq(io.sqrtOp, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 341:28] node _fractB_Z_T_1 = and(inReady, _fractB_Z_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 341:25] node _fractB_Z_T_2 = bits(io.b.sig, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 341:73] node _fractB_Z_T_3 = shl(_fractB_Z_T_2, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 341:90] node _fractB_Z_T_4 = mux(_fractB_Z_T_1, _fractB_Z_T_3, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 341:16] node _fractB_Z_T_5 = and(inReady, io.sqrtOp) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 342:25] node _fractB_Z_T_6 = bits(io.a.sExp, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 342:52] node _fractB_Z_T_7 = and(_fractB_Z_T_5, _fractB_Z_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 342:38] node _fractB_Z_T_8 = mux(_fractB_Z_T_7, UInt<23>(0h400000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 342:16] node _fractB_Z_T_9 = or(_fractB_Z_T_4, _fractB_Z_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 341:100] node _fractB_Z_T_10 = and(inReady, io.sqrtOp) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 343:25] node _fractB_Z_T_11 = bits(io.a.sExp, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 343:54] node _fractB_Z_T_12 = eq(_fractB_Z_T_11, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 343:41] node _fractB_Z_T_13 = and(_fractB_Z_T_10, _fractB_Z_T_12) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 343:38] node _fractB_Z_T_14 = mux(_fractB_Z_T_13, UInt<24>(0h800000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 343:16] node _fractB_Z_T_15 = or(_fractB_Z_T_9, _fractB_Z_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 342:100] node _fractB_Z_T_16 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 344:17] node _fractB_Z_T_17 = and(_fractB_Z_T_16, processTwoBits) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 344:42] node _fractB_Z_T_18 = shr(fractB_Z, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 344:71] node _fractB_Z_T_19 = mux(_fractB_Z_T_17, _fractB_Z_T_18, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 344:16] node _fractB_Z_T_20 = or(_fractB_Z_T_15, _fractB_Z_T_19) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 343:100] node _fractB_Z_T_21 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 345:17] node _fractB_Z_T_22 = eq(processTwoBits, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 345:45] node _fractB_Z_T_23 = and(_fractB_Z_T_21, _fractB_Z_T_22) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 345:42] node _fractB_Z_T_24 = shr(fractB_Z, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 345:71] node _fractB_Z_T_25 = mux(_fractB_Z_T_23, _fractB_Z_T_24, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 345:16] node _fractB_Z_T_26 = or(_fractB_Z_T_20, _fractB_Z_T_25) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 344:100] connect fractB_Z, _fractB_Z_T_26 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 340:18] node _rem_T = eq(oddSqrt_S, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 351:24] node _rem_T_1 = and(inReady, _rem_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 351:21] node _rem_T_2 = shl(io.a.sig, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 351:47] node _rem_T_3 = mux(_rem_T_1, _rem_T_2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 351:12] node _rem_T_4 = and(inReady, oddSqrt_S) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 352:21] node _rem_T_5 = bits(io.a.sig, 23, 22) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 353:27] node _rem_T_6 = sub(_rem_T_5, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 353:56] node _rem_T_7 = tail(_rem_T_6, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 353:56] node _rem_T_8 = bits(io.a.sig, 21, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 354:27] node _rem_T_9 = shl(_rem_T_8, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 354:44] node _rem_T_10 = cat(_rem_T_7, _rem_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 353:16] node _rem_T_11 = mux(_rem_T_4, _rem_T_10, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 352:12] node _rem_T_12 = or(_rem_T_3, _rem_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 351:57] node _rem_T_13 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 358:13] node _rem_T_14 = shl(rem_Z, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 358:29] node _rem_T_15 = mux(_rem_T_13, _rem_T_14, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 358:12] node rem = or(_rem_T_12, _rem_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 357:11] node _bitMask_T = dshl(UInt<1>(0h1), cycleNum) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 359:23] node bitMask = shr(_bitMask_T, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 359:34] node _trialTerm_T = eq(io.sqrtOp, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 361:24] node _trialTerm_T_1 = and(inReady, _trialTerm_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 361:21] node _trialTerm_T_2 = shl(io.b.sig, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 361:48] node _trialTerm_T_3 = mux(_trialTerm_T_1, _trialTerm_T_2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 361:12] node _trialTerm_T_4 = and(inReady, evenSqrt_S) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 362:21] node _trialTerm_T_5 = mux(_trialTerm_T_4, UInt<25>(0h1000000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 362:12] node _trialTerm_T_6 = or(_trialTerm_T_3, _trialTerm_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 361:74] node _trialTerm_T_7 = and(inReady, oddSqrt_S) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 363:21] node _trialTerm_T_8 = mux(_trialTerm_T_7, UInt<26>(0h2800000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 363:12] node _trialTerm_T_9 = or(_trialTerm_T_6, _trialTerm_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 362:74] node _trialTerm_T_10 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 364:13] node _trialTerm_T_11 = mux(_trialTerm_T_10, fractB_Z, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 364:12] node _trialTerm_T_12 = or(_trialTerm_T_9, _trialTerm_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 363:74] node _trialTerm_T_13 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 365:13] node _trialTerm_T_14 = eq(sqrtOp_Z, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 365:26] node _trialTerm_T_15 = and(_trialTerm_T_13, _trialTerm_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 365:23] node _trialTerm_T_16 = shl(UInt<1>(0h1), 24) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 365:42] node _trialTerm_T_17 = mux(_trialTerm_T_15, _trialTerm_T_16, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 365:12] node _trialTerm_T_18 = or(_trialTerm_T_12, _trialTerm_T_17) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 364:74] node _trialTerm_T_19 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 366:13] node _trialTerm_T_20 = and(_trialTerm_T_19, sqrtOp_Z) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 366:23] node _trialTerm_T_21 = shl(sigX_Z, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 366:44] node _trialTerm_T_22 = mux(_trialTerm_T_20, _trialTerm_T_21, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 366:12] node trialTerm = or(_trialTerm_T_18, _trialTerm_T_22) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 365:74] node _trialRem_T = cvt(rem) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 367:24] node _trialRem_T_1 = cvt(trialTerm) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 367:42] node trialRem = sub(_trialRem_T, _trialRem_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 367:29] node newBit = leq(asSInt(UInt<1>(0h0)), trialRem) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 368:23] node _nextRem_Z_T = asUInt(trialRem) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 370:42] node _nextRem_Z_T_1 = mux(newBit, _nextRem_Z_T, rem) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 370:24] node nextRem_Z = bits(_nextRem_Z_T_1, 25, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 370:54] node rem2 = shl(nextRem_Z, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 371:25] node _trialTerm2_newBit0_T = shr(fractB_Z, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 372:52] node _trialTerm2_newBit0_T_1 = shl(sigX_Z, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 372:64] node _trialTerm2_newBit0_T_2 = or(_trialTerm2_newBit0_T, _trialTerm2_newBit0_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 372:56] node _trialTerm2_newBit0_T_3 = shl(UInt<1>(0h1), 24) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 372:85] node _trialTerm2_newBit0_T_4 = or(fractB_Z, _trialTerm2_newBit0_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 372:78] node trialTerm2_newBit0 = mux(sqrtOp_Z, _trialTerm2_newBit0_T_2, _trialTerm2_newBit0_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 372:33] node _trialTerm2_newBit1_T = shl(fractB_Z, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 373:73] node _trialTerm2_newBit1_T_1 = mux(sqrtOp_Z, _trialTerm2_newBit1_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 373:54] node trialTerm2_newBit1 = or(trialTerm2_newBit0, _trialTerm2_newBit1_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 373:49] node _trialRem2_T = shl(trialRem, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 376:22] node _trialRem2_T_1 = cvt(trialTerm2_newBit1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 376:48] node _trialRem2_T_2 = sub(_trialRem2_T, _trialRem2_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 376:27] node _trialRem2_T_3 = tail(_trialRem2_T_2, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 376:27] node _trialRem2_T_4 = asSInt(_trialRem2_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 376:27] node _trialRem2_T_5 = shl(rem_Z, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 377:19] node _trialRem2_T_6 = bits(_trialRem2_T_5, 26, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 377:23] node _trialRem2_T_7 = cvt(_trialRem2_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 377:39] node _trialRem2_T_8 = cvt(trialTerm2_newBit0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 377:65] node _trialRem2_T_9 = sub(_trialRem2_T_7, _trialRem2_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 377:44] node _trialRem2_T_10 = tail(_trialRem2_T_9, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 377:44] node _trialRem2_T_11 = asSInt(_trialRem2_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 377:44] node trialRem2 = mux(newBit, _trialRem2_T_4, _trialRem2_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 375:12] node newBit2 = leq(asSInt(UInt<1>(0h0)), trialRem2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 378:24] node _nextNotZeroRem_Z_T = or(inReady, newBit) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 379:40] node _nextNotZeroRem_Z_T_1 = neq(trialRem, asSInt(UInt<1>(0h0))) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 379:60] node nextNotZeroRem_Z = mux(_nextNotZeroRem_Z_T, _nextNotZeroRem_Z_T_1, notZeroRem_Z) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 379:31] node _nextNotZeroRem_Z_2_T = and(processTwoBits, newBit) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 381:24] node _nextNotZeroRem_Z_2_T_1 = shl(trialRem, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 381:53] node _nextNotZeroRem_Z_2_T_2 = cvt(trialTerm2_newBit1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 381:79] node _nextNotZeroRem_Z_2_T_3 = sub(_nextNotZeroRem_Z_2_T_1, _nextNotZeroRem_Z_2_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 381:58] node _nextNotZeroRem_Z_2_T_4 = tail(_nextNotZeroRem_Z_2_T_3, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 381:58] node _nextNotZeroRem_Z_2_T_5 = asSInt(_nextNotZeroRem_Z_2_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 381:58] node _nextNotZeroRem_Z_2_T_6 = lt(asSInt(UInt<1>(0h0)), _nextNotZeroRem_Z_2_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 381:42] node _nextNotZeroRem_Z_2_T_7 = and(_nextNotZeroRem_Z_2_T, _nextNotZeroRem_Z_2_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 381:34] node _nextNotZeroRem_Z_2_T_8 = eq(newBit, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:27] node _nextNotZeroRem_Z_2_T_9 = and(processTwoBits, _nextNotZeroRem_Z_2_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:24] node _nextNotZeroRem_Z_2_T_10 = shl(rem_Z, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:51] node _nextNotZeroRem_Z_2_T_11 = bits(_nextNotZeroRem_Z_2_T_10, 26, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:55] node _nextNotZeroRem_Z_2_T_12 = cvt(_nextNotZeroRem_Z_2_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:71] node _nextNotZeroRem_Z_2_T_13 = cvt(trialTerm2_newBit0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:97] node _nextNotZeroRem_Z_2_T_14 = sub(_nextNotZeroRem_Z_2_T_12, _nextNotZeroRem_Z_2_T_13) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:76] node _nextNotZeroRem_Z_2_T_15 = tail(_nextNotZeroRem_Z_2_T_14, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:76] node _nextNotZeroRem_Z_2_T_16 = asSInt(_nextNotZeroRem_Z_2_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:76] node _nextNotZeroRem_Z_2_T_17 = lt(asSInt(UInt<1>(0h0)), _nextNotZeroRem_Z_2_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:43] node _nextNotZeroRem_Z_2_T_18 = and(_nextNotZeroRem_Z_2_T_9, _nextNotZeroRem_Z_2_T_17) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:35] node _nextNotZeroRem_Z_2_T_19 = or(_nextNotZeroRem_Z_2_T_7, _nextNotZeroRem_Z_2_T_18) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 381:85] node _nextNotZeroRem_Z_2_T_20 = and(processTwoBits, newBit2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 383:26] node _nextNotZeroRem_Z_2_T_21 = eq(_nextNotZeroRem_Z_2_T_20, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 383:9] node _nextNotZeroRem_Z_2_T_22 = and(_nextNotZeroRem_Z_2_T_21, nextNotZeroRem_Z) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 383:38] node nextNotZeroRem_Z_2 = or(_nextNotZeroRem_Z_2_T_19, _nextNotZeroRem_Z_2_T_22) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:103] node _nextRem_Z_2_T = and(processTwoBits, newBit2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 385:28] node _nextRem_Z_2_T_1 = asUInt(trialRem2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 385:51] node _nextRem_Z_2_T_2 = bits(_nextRem_Z_2_T_1, 25, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 385:57] node _nextRem_Z_2_T_3 = mux(_nextRem_Z_2_T, _nextRem_Z_2_T_2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 385:12] node _nextRem_Z_2_T_4 = eq(newBit2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 386:31] node _nextRem_Z_2_T_5 = and(processTwoBits, _nextRem_Z_2_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 386:28] node _nextRem_Z_2_T_6 = bits(rem2, 25, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 386:45] node _nextRem_Z_2_T_7 = mux(_nextRem_Z_2_T_5, _nextRem_Z_2_T_6, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 386:12] node _nextRem_Z_2_T_8 = or(_nextRem_Z_2_T_3, _nextRem_Z_2_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 385:81] node _nextRem_Z_2_T_9 = eq(processTwoBits, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 387:13] node _nextRem_Z_2_T_10 = mux(_nextRem_Z_2_T_9, nextRem_Z, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 387:12] node nextRem_Z_2 = or(_nextRem_Z_2_T_8, _nextRem_Z_2_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 386:83] node _T_5 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 389:23] node _T_6 = or(entering, _T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 389:20] when _T_6 : @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 389:34] connect notZeroRem_Z, nextNotZeroRem_Z_2 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 390:22] connect rem_Z, nextRem_Z_2 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 391:15] node _sigX_Z_T = eq(io.sqrtOp, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 393:28] node _sigX_Z_T_1 = and(inReady, _sigX_Z_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 393:25] node _sigX_Z_T_2 = shl(newBit, 25) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 393:50] node _sigX_Z_T_3 = mux(_sigX_Z_T_1, _sigX_Z_T_2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 393:16] node _sigX_Z_T_4 = and(inReady, io.sqrtOp) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 394:25] node _sigX_Z_T_5 = mux(_sigX_Z_T_4, UInt<25>(0h1000000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 394:16] node _sigX_Z_T_6 = or(_sigX_Z_T_3, _sigX_Z_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 393:74] node _sigX_Z_T_7 = and(inReady, oddSqrt_S) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 395:25] node _sigX_Z_T_8 = shl(newBit, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 395:50] node _sigX_Z_T_9 = mux(_sigX_Z_T_7, _sigX_Z_T_8, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 395:16] node _sigX_Z_T_10 = or(_sigX_Z_T_6, _sigX_Z_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 394:74] node _sigX_Z_T_11 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 396:17] node _sigX_Z_T_12 = mux(_sigX_Z_T_11, sigX_Z, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 396:16] node _sigX_Z_T_13 = or(_sigX_Z_T_10, _sigX_Z_T_12) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 395:74] node _sigX_Z_T_14 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 397:17] node _sigX_Z_T_15 = and(_sigX_Z_T_14, newBit) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 397:27] node _sigX_Z_T_16 = mux(_sigX_Z_T_15, bitMask, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 397:16] node _sigX_Z_T_17 = or(_sigX_Z_T_13, _sigX_Z_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 396:74] node _sigX_Z_T_18 = and(processTwoBits, newBit2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 398:32] node _sigX_Z_T_19 = shr(bitMask, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 398:51] node _sigX_Z_T_20 = mux(_sigX_Z_T_18, _sigX_Z_T_19, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 398:16] node _sigX_Z_T_21 = or(_sigX_Z_T_17, _sigX_Z_T_20) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 397:74] connect sigX_Z, _sigX_Z_T_21 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 392:16] node _io_rawOutValid_div_T = eq(sqrtOp_Z, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 403:43] node _io_rawOutValid_div_T_1 = and(rawOutValid, _io_rawOutValid_div_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 403:40] connect io.rawOutValid_div, _io_rawOutValid_div_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 403:25] node _io_rawOutValid_sqrt_T = and(rawOutValid, sqrtOp_Z) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 404:40] connect io.rawOutValid_sqrt, _io_rawOutValid_sqrt_T @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 404:25] connect io.roundingModeOut, roundingMode_Z @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 405:25] node _io_invalidExc_T = and(majorExc_Z, isNaN_Z) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 406:36] connect io.invalidExc, _io_invalidExc_T @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 406:22] node _io_infiniteExc_T = eq(isNaN_Z, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 407:39] node _io_infiniteExc_T_1 = and(majorExc_Z, _io_infiniteExc_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 407:36] connect io.infiniteExc, _io_infiniteExc_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 407:22] connect io.rawOut.isNaN, isNaN_Z @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 408:22] connect io.rawOut.isInf, isInf_Z @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 409:22] connect io.rawOut.isZero, isZero_Z @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 410:22] connect io.rawOut.sign, sign_Z @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 411:22] connect io.rawOut.sExp, sExp_Z @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 412:22] node _io_rawOut_sig_T = shl(sigX_Z, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 413:31] node _io_rawOut_sig_T_1 = or(_io_rawOut_sig_T, notZeroRem_Z) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 413:35] connect io.rawOut.sig, _io_rawOut_sig_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 413:22] module DivSqrtRecFNToRaw_small : @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 421:5] input clock : Clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 421:5] input reset : Reset @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 421:5] output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 424:16] inst divSqrtRawFN of DivSqrtRawFN_small @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 444:15] connect divSqrtRawFN.clock, clock connect divSqrtRawFN.reset, reset connect io.inReady, divSqrtRawFN.io.inReady @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 446:16] connect divSqrtRawFN.io.inValid, io.inValid @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 447:34] connect divSqrtRawFN.io.sqrtOp, io.sqrtOp @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 448:34] node divSqrtRawFN_io_a_exp = bits(io.a, 31, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _divSqrtRawFN_io_a_isZero_T = bits(divSqrtRawFN_io_a_exp, 8, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node divSqrtRawFN_io_a_isZero = eq(_divSqrtRawFN_io_a_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _divSqrtRawFN_io_a_isSpecial_T = bits(divSqrtRawFN_io_a_exp, 8, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node divSqrtRawFN_io_a_isSpecial = eq(_divSqrtRawFN_io_a_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire divSqrtRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _divSqrtRawFN_io_a_out_isNaN_T = bits(divSqrtRawFN_io_a_exp, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _divSqrtRawFN_io_a_out_isNaN_T_1 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect divSqrtRawFN_io_a_out.isNaN, _divSqrtRawFN_io_a_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _divSqrtRawFN_io_a_out_isInf_T = bits(divSqrtRawFN_io_a_exp, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _divSqrtRawFN_io_a_out_isInf_T_1 = eq(_divSqrtRawFN_io_a_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _divSqrtRawFN_io_a_out_isInf_T_2 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect divSqrtRawFN_io_a_out.isInf, _divSqrtRawFN_io_a_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect divSqrtRawFN_io_a_out.isZero, divSqrtRawFN_io_a_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _divSqrtRawFN_io_a_out_sign_T = bits(io.a, 32, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect divSqrtRawFN_io_a_out.sign, _divSqrtRawFN_io_a_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _divSqrtRawFN_io_a_out_sExp_T = cvt(divSqrtRawFN_io_a_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect divSqrtRawFN_io_a_out.sExp, _divSqrtRawFN_io_a_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _divSqrtRawFN_io_a_out_sig_T = eq(divSqrtRawFN_io_a_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _divSqrtRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_a_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _divSqrtRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _divSqrtRawFN_io_a_out_sig_T_3 = cat(_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect divSqrtRawFN_io_a_out.sig, _divSqrtRawFN_io_a_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] connect divSqrtRawFN.io.a.sig, divSqrtRawFN_io_a_out.sig @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 449:34] connect divSqrtRawFN.io.a.sExp, divSqrtRawFN_io_a_out.sExp @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 449:34] connect divSqrtRawFN.io.a.sign, divSqrtRawFN_io_a_out.sign @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 449:34] connect divSqrtRawFN.io.a.isZero, divSqrtRawFN_io_a_out.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 449:34] connect divSqrtRawFN.io.a.isInf, divSqrtRawFN_io_a_out.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 449:34] connect divSqrtRawFN.io.a.isNaN, divSqrtRawFN_io_a_out.isNaN @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 449:34] node divSqrtRawFN_io_b_exp = bits(io.b, 31, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _divSqrtRawFN_io_b_isZero_T = bits(divSqrtRawFN_io_b_exp, 8, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node divSqrtRawFN_io_b_isZero = eq(_divSqrtRawFN_io_b_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _divSqrtRawFN_io_b_isSpecial_T = bits(divSqrtRawFN_io_b_exp, 8, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node divSqrtRawFN_io_b_isSpecial = eq(_divSqrtRawFN_io_b_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire divSqrtRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _divSqrtRawFN_io_b_out_isNaN_T = bits(divSqrtRawFN_io_b_exp, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _divSqrtRawFN_io_b_out_isNaN_T_1 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect divSqrtRawFN_io_b_out.isNaN, _divSqrtRawFN_io_b_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _divSqrtRawFN_io_b_out_isInf_T = bits(divSqrtRawFN_io_b_exp, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _divSqrtRawFN_io_b_out_isInf_T_1 = eq(_divSqrtRawFN_io_b_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _divSqrtRawFN_io_b_out_isInf_T_2 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect divSqrtRawFN_io_b_out.isInf, _divSqrtRawFN_io_b_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect divSqrtRawFN_io_b_out.isZero, divSqrtRawFN_io_b_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _divSqrtRawFN_io_b_out_sign_T = bits(io.b, 32, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect divSqrtRawFN_io_b_out.sign, _divSqrtRawFN_io_b_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _divSqrtRawFN_io_b_out_sExp_T = cvt(divSqrtRawFN_io_b_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect divSqrtRawFN_io_b_out.sExp, _divSqrtRawFN_io_b_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _divSqrtRawFN_io_b_out_sig_T = eq(divSqrtRawFN_io_b_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _divSqrtRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_b_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _divSqrtRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _divSqrtRawFN_io_b_out_sig_T_3 = cat(_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect divSqrtRawFN_io_b_out.sig, _divSqrtRawFN_io_b_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] connect divSqrtRawFN.io.b.sig, divSqrtRawFN_io_b_out.sig @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 450:34] connect divSqrtRawFN.io.b.sExp, divSqrtRawFN_io_b_out.sExp @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 450:34] connect divSqrtRawFN.io.b.sign, divSqrtRawFN_io_b_out.sign @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 450:34] connect divSqrtRawFN.io.b.isZero, divSqrtRawFN_io_b_out.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 450:34] connect divSqrtRawFN.io.b.isInf, divSqrtRawFN_io_b_out.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 450:34] connect divSqrtRawFN.io.b.isNaN, divSqrtRawFN_io_b_out.isNaN @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 450:34] connect divSqrtRawFN.io.roundingMode, io.roundingMode @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 451:34] connect io.rawOutValid_div, divSqrtRawFN.io.rawOutValid_div @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 453:25] connect io.rawOutValid_sqrt, divSqrtRawFN.io.rawOutValid_sqrt @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 454:25] connect io.roundingModeOut, divSqrtRawFN.io.roundingModeOut @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 455:25] connect io.invalidExc, divSqrtRawFN.io.invalidExc @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 456:25] connect io.infiniteExc, divSqrtRawFN.io.infiniteExc @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 457:25] connect io.rawOut, divSqrtRawFN.io.rawOut @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 458:25] module RoundAnyRawFNToRecFN_5 : @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 48:5] output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 57:16] node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 89:53] node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 90:53] node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 91:53] node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 92:53] node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 93:53] node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 94:53] node _roundMagUp_T = and(roundingMode_min, io.in.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:27] node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:66] node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:63] node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:42] node adjustedSig = shl(io.in.sig, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 113:22] node doShiftSigDown1 = bits(adjustedSig, 26, 26) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 119:57] wire common_expOut : UInt<9> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 121:31] wire common_fractOut : UInt<23> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 122:31] wire common_overflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 123:37] wire common_totalUnderflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 124:37] wire common_underflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 125:37] wire common_inexact : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 126:37] node _roundMask_T = bits(io.in.sExp, 8, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 155:37] node _roundMask_T_1 = not(_roundMask_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 52:21] node roundMask_msb = bits(_roundMask_T_1, 8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 76:56] node _roundMask_T_2 = bits(roundMask_shift, 63, 42) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 78:22] node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_4 = shl(UInt<8>(0hff), 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_6 = shr(_roundMask_T_3, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_9 = shl(_roundMask_T_8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_10 = not(_roundMask_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_14 = shl(_roundMask_T_13, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_16 = shr(_roundMask_T_12, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_19 = shl(_roundMask_T_18, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_20 = not(_roundMask_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_24 = shl(_roundMask_T_23, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_26 = shr(_roundMask_T_22, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_29 = shl(_roundMask_T_28, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_30 = not(_roundMask_T_25) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_34 = shl(_roundMask_T_33, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_36 = shr(_roundMask_T_32, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_39 = shl(_roundMask_T_38, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_40 = not(_roundMask_T_35) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_60 = not(_roundMask_T_59) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:32] node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:21] node _roundMask_T_62 = not(_roundMask_T_61) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:17] node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 68:58] node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 76:56] node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 78:22] node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 62:24] node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 67:24] node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 62:24] node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 158:23] node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 158:42] node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 161:41] node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 161:53] node _roundPosMask_T = not(shiftedRoundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 162:28] node roundPosMask = and(_roundPosMask_T, roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 162:46] node _roundPosBit_T = and(adjustedSig, roundPosMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 163:40] node roundPosBit = orr(_roundPosBit_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 163:56] node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 164:42] node anyRoundExtra = orr(_anyRoundExtra_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 164:62] node anyRound = or(roundPosBit, anyRoundExtra) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 165:36] node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 168:38] node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 168:67] node _roundIncr_T_2 = and(roundMagUp, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 170:29] node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 169:31] node _roundedSig_T = or(adjustedSig, roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:32] node _roundedSig_T_1 = shr(_roundedSig_T, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:44] node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:49] node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:49] node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 175:30] node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:64] node _roundedSig_T_6 = shr(roundMask, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 176:35] node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:25] node _roundedSig_T_8 = not(_roundedSig_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:21] node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:57] node _roundedSig_T_10 = not(roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:32] node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:30] node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:43] node _roundedSig_T_13 = and(roundingMode_odd, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:42] node _roundedSig_T_14 = shr(roundPosMask, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:67] node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:24] node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:47] node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 172:16] node _sRoundedExp_T = shr(roundedSig, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:54] node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:76] node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:40] node _common_expOut_T = bits(sRoundedExp, 8, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 186:37] connect common_expOut, _common_expOut_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 186:23] node _common_fractOut_T = bits(roundedSig, 23, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 189:27] node _common_fractOut_T_1 = bits(roundedSig, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 190:27] node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 188:16] connect common_fractOut, _common_fractOut_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 187:25] node _common_overflow_T = shr(sRoundedExp, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 195:30] node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 195:50] connect common_overflow, _common_overflow_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 192:25] node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 199:31] connect common_totalUnderflow, _common_totalUnderflow_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 196:31] node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:45] node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:61] node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:16] node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:44] node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:30] node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:63] node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:70] node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:49] node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 206:38] node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 206:67] node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 208:29] node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 207:46] node _roundCarry_T = bits(roundedSig, 25, 25) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 211:27] node _roundCarry_T_1 = bits(roundedSig, 24, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 212:27] node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 210:16] node _common_underflow_T = shr(io.in.sExp, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:49] node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:64] node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:32] node _common_underflow_T_3 = bits(roundMask, 3, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:57] node _common_underflow_T_4 = bits(roundMask, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:71] node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:30] node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:72] node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 221:49] node _common_underflow_T_8 = bits(roundMask, 4, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 223:49] node _common_underflow_T_9 = bits(roundMask, 3, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 224:49] node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 222:39] node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 222:34] node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 221:77] node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 225:38] node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 226:45] node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 226:60] node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 221:27] node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:76] node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 216:40] connect common_underflow, _common_underflow_T_18 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 214:26] node _common_inexact_T = or(common_totalUnderflow, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 229:49] connect common_inexact, _common_inexact_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 229:24] node isNaNOut = or(io.invalidExc, io.in.isNaN) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 234:34] node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 235:49] node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:22] node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:36] node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:33] node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:64] node commonCase = and(_commonCase_T_2, _commonCase_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:61] node overflow = and(commonCase, common_overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 237:32] node underflow = and(commonCase, common_underflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 238:32] node _inexact_T = and(commonCase, common_inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 239:43] node inexact = or(overflow, _inexact_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 239:28] node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 242:32] node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 242:60] node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:20] node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:60] node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:45] node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 245:42] node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 245:39] node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 247:45] node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 247:32] node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 249:22] node _expOut_T = or(io.in.isZero, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:32] node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:18] node _expOut_T_2 = not(_expOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:14] node _expOut_T_3 = and(common_expOut, _expOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 251:24] node _expOut_T_4 = not(UInt<9>(0h6b)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 257:19] node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 256:18] node _expOut_T_6 = not(_expOut_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 256:14] node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 255:17] node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 260:18] node _expOut_T_9 = not(_expOut_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 260:14] node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 259:17] node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 264:18] node _expOut_T_12 = not(_expOut_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 264:14] node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 263:17] node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 268:16] node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 267:18] node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 272:16] node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 271:15] node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 276:16] node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 275:15] node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 277:16] node expOut = or(_expOut_T_19, _expOut_T_20) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 276:73] node _fractOut_T = or(isNaNOut, io.in.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:22] node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:38] node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 280:16] node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:12] node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 283:13] node fractOut = or(_fractOut_T_3, _fractOut_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 282:11] node _io_out_T = cat(signOut, expOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:23] node _io_out_T_1 = cat(_io_out_T, fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:33] connect io.out, _io_out_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:12] node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:23] node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:41] node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:53] node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:66] connect io.exceptionFlags, _io_exceptionFlags_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 286:23] module RoundRawFNToRecFN_2 : @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 294:5] output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 297:16] inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_5 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 308:15] connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 311:44] connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 312:44] connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 314:44] connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 315:44] connect io.out, roundAnyRawFNToRecFN.io.out @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 316:23] connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 317:23] module DivSqrtRecFN_small : @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 466:5] input clock : Clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 466:5] input reset : Reset @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 466:5] output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 469:16] inst divSqrtRecFNToRaw of DivSqrtRecFNToRaw_small @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 490:15] connect divSqrtRecFNToRaw.clock, clock connect divSqrtRecFNToRaw.reset, reset connect io.inReady, divSqrtRecFNToRaw.io.inReady @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 492:16] connect divSqrtRecFNToRaw.io.inValid, io.inValid @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 493:39] connect divSqrtRecFNToRaw.io.sqrtOp, io.sqrtOp @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 494:39] connect divSqrtRecFNToRaw.io.a, io.a @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 495:39] connect divSqrtRecFNToRaw.io.b, io.b @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 496:39] connect divSqrtRecFNToRaw.io.roundingMode, io.roundingMode @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 497:39] connect io.outValid_div, divSqrtRecFNToRaw.io.rawOutValid_div @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 501:22] connect io.outValid_sqrt, divSqrtRecFNToRaw.io.rawOutValid_sqrt @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 502:22] inst roundRawFNToRecFN of RoundRawFNToRecFN_2 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 505:15] connect roundRawFNToRecFN.io.invalidExc, divSqrtRecFNToRaw.io.invalidExc @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 506:39] connect roundRawFNToRecFN.io.infiniteExc, divSqrtRecFNToRaw.io.infiniteExc @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 507:39] connect roundRawFNToRecFN.io.in.sig, divSqrtRecFNToRaw.io.rawOut.sig @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 508:39] connect roundRawFNToRecFN.io.in.sExp, divSqrtRecFNToRaw.io.rawOut.sExp @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 508:39] connect roundRawFNToRecFN.io.in.sign, divSqrtRecFNToRaw.io.rawOut.sign @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 508:39] connect roundRawFNToRecFN.io.in.isZero, divSqrtRecFNToRaw.io.rawOut.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 508:39] connect roundRawFNToRecFN.io.in.isInf, divSqrtRecFNToRaw.io.rawOut.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 508:39] connect roundRawFNToRecFN.io.in.isNaN, divSqrtRecFNToRaw.io.rawOut.isNaN @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 508:39] connect roundRawFNToRecFN.io.roundingMode, divSqrtRecFNToRaw.io.roundingModeOut @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 509:39] connect roundRawFNToRecFN.io.detectTininess, io.detectTininess @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 510:41] connect io.out, roundRawFNToRecFN.io.out @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 511:23] connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 512:23] module DivSqrtRawFN_small_1 : @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 199:5] input clock : Clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 199:5] input reset : Reset @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 199:5] output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}} @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 202:16] regreset cycleNum : UInt<6>, clock, reset, UInt<6>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 223:33] regreset inReady : UInt<1>, clock, reset, UInt<1>(0h1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 224:33] regreset rawOutValid : UInt<1>, clock, reset, UInt<1>(0h0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 225:33] reg sqrtOp_Z : UInt<1>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 227:29] reg majorExc_Z : UInt<1>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 228:29] reg isNaN_Z : UInt<1>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 230:29] reg isInf_Z : UInt<1>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 231:29] reg isZero_Z : UInt<1>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 232:29] reg sign_Z : UInt<1>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 233:29] reg sExp_Z : SInt<13>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 234:29] reg fractB_Z : UInt<53>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 235:29] reg roundingMode_Z : UInt<3>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 236:29] reg rem_Z : UInt<55>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 242:29] reg notZeroRem_Z : UInt<1>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 243:29] reg sigX_Z : UInt<55>, clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 244:29] node _notSigNaNIn_invalidExc_S_div_T = and(io.a.isZero, io.b.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 253:24] node _notSigNaNIn_invalidExc_S_div_T_1 = and(io.a.isInf, io.b.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 253:59] node notSigNaNIn_invalidExc_S_div = or(_notSigNaNIn_invalidExc_S_div_T, _notSigNaNIn_invalidExc_S_div_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 253:42] node _notSigNaNIn_invalidExc_S_sqrt_T = eq(io.a.isNaN, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 255:9] node _notSigNaNIn_invalidExc_S_sqrt_T_1 = eq(io.a.isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 255:27] node _notSigNaNIn_invalidExc_S_sqrt_T_2 = and(_notSigNaNIn_invalidExc_S_sqrt_T, _notSigNaNIn_invalidExc_S_sqrt_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 255:24] node notSigNaNIn_invalidExc_S_sqrt = and(_notSigNaNIn_invalidExc_S_sqrt_T_2, io.a.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 255:43] node _majorExc_S_T = bits(io.a.sig, 51, 51) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:56] node _majorExc_S_T_1 = eq(_majorExc_S_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:49] node _majorExc_S_T_2 = and(io.a.isNaN, _majorExc_S_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:46] node _majorExc_S_T_3 = or(_majorExc_S_T_2, notSigNaNIn_invalidExc_S_sqrt) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 258:38] node _majorExc_S_T_4 = bits(io.a.sig, 51, 51) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:56] node _majorExc_S_T_5 = eq(_majorExc_S_T_4, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:49] node _majorExc_S_T_6 = and(io.a.isNaN, _majorExc_S_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:46] node _majorExc_S_T_7 = bits(io.b.sig, 51, 51) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:56] node _majorExc_S_T_8 = eq(_majorExc_S_T_7, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:49] node _majorExc_S_T_9 = and(io.b.isNaN, _majorExc_S_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/common.scala 82:46] node _majorExc_S_T_10 = or(_majorExc_S_T_6, _majorExc_S_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 259:38] node _majorExc_S_T_11 = or(_majorExc_S_T_10, notSigNaNIn_invalidExc_S_div) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 259:66] node _majorExc_S_T_12 = eq(io.a.isNaN, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 261:18] node _majorExc_S_T_13 = eq(io.a.isInf, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 261:36] node _majorExc_S_T_14 = and(_majorExc_S_T_12, _majorExc_S_T_13) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 261:33] node _majorExc_S_T_15 = and(_majorExc_S_T_14, io.b.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 261:51] node _majorExc_S_T_16 = or(_majorExc_S_T_11, _majorExc_S_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 260:46] node majorExc_S = mux(io.sqrtOp, _majorExc_S_T_3, _majorExc_S_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 257:12] node _isNaN_S_T = or(io.a.isNaN, notSigNaNIn_invalidExc_S_sqrt) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 265:26] node _isNaN_S_T_1 = or(io.a.isNaN, io.b.isNaN) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 266:26] node _isNaN_S_T_2 = or(_isNaN_S_T_1, notSigNaNIn_invalidExc_S_div) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 266:42] node isNaN_S = mux(io.sqrtOp, _isNaN_S_T, _isNaN_S_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 264:12] node _isInf_S_T = or(io.a.isInf, io.b.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 268:63] node isInf_S = mux(io.sqrtOp, io.a.isInf, _isInf_S_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 268:23] node _isZero_S_T = or(io.a.isZero, io.b.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 269:64] node isZero_S = mux(io.sqrtOp, io.a.isZero, _isZero_S_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 269:23] node _sign_S_T = eq(io.sqrtOp, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 270:33] node _sign_S_T_1 = and(_sign_S_T, io.b.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 270:45] node sign_S = xor(io.a.sign, _sign_S_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 270:30] node _specialCaseA_S_T = or(io.a.isNaN, io.a.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 272:39] node specialCaseA_S = or(_specialCaseA_S_T, io.a.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 272:55] node _specialCaseB_S_T = or(io.b.isNaN, io.b.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 273:39] node specialCaseB_S = or(_specialCaseB_S_T, io.b.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 273:55] node _normalCase_S_div_T = eq(specialCaseA_S, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 274:28] node _normalCase_S_div_T_1 = eq(specialCaseB_S, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 274:48] node normalCase_S_div = and(_normalCase_S_div_T, _normalCase_S_div_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 274:45] node _normalCase_S_sqrt_T = eq(specialCaseA_S, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 275:29] node _normalCase_S_sqrt_T_1 = eq(io.a.sign, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 275:49] node normalCase_S_sqrt = and(_normalCase_S_sqrt_T, _normalCase_S_sqrt_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 275:46] node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 276:27] node _sExpQuot_S_div_T = bits(io.b.sExp, 11, 11) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 280:28] node _sExpQuot_S_div_T_1 = bits(io.b.sExp, 10, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 280:52] node _sExpQuot_S_div_T_2 = not(_sExpQuot_S_div_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 280:40] node _sExpQuot_S_div_T_3 = cat(_sExpQuot_S_div_T, _sExpQuot_S_div_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 280:16] node _sExpQuot_S_div_T_4 = asSInt(_sExpQuot_S_div_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 280:71] node sExpQuot_S_div = add(io.a.sExp, _sExpQuot_S_div_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 279:21] node _sSatExpQuot_S_div_T = leq(asSInt(UInt<13>(0he00)), sExpQuot_S_div) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 283:48] node _sSatExpQuot_S_div_T_1 = bits(sExpQuot_S_div, 12, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 285:31] node _sSatExpQuot_S_div_T_2 = mux(_sSatExpQuot_S_div_T, UInt<3>(0h6), _sSatExpQuot_S_div_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 283:16] node _sSatExpQuot_S_div_T_3 = bits(sExpQuot_S_div, 8, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 287:27] node _sSatExpQuot_S_div_T_4 = cat(_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 283:12] node sSatExpQuot_S_div = asSInt(_sSatExpQuot_S_div_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 288:11] node _evenSqrt_S_T = bits(io.a.sExp, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 290:48] node _evenSqrt_S_T_1 = eq(_evenSqrt_S_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 290:35] node evenSqrt_S = and(io.sqrtOp, _evenSqrt_S_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 290:32] node _oddSqrt_S_T = bits(io.a.sExp, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 291:48] node oddSqrt_S = and(io.sqrtOp, _oddSqrt_S_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 291:32] node idle = eq(cycleNum, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 295:25] node entering = and(inReady, io.inValid) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 296:28] node entering_normalCase = and(entering, normalCase_S) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 297:40] node _processTwoBits_T = geq(cycleNum, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 299:35] node processTwoBits = and(_processTwoBits_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 299:42] node _skipCycle2_T = eq(cycleNum, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 300:31] node _skipCycle2_T_1 = bits(sigX_Z, 54, 54) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 300:48] node _skipCycle2_T_2 = and(_skipCycle2_T, _skipCycle2_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 300:39] node skipCycle2 = and(_skipCycle2_T_2, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 300:63] node _T = eq(idle, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 302:11] node _T_1 = or(_T, entering) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 302:18] when _T_1 : @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 302:31] node _inReady_T = eq(normalCase_S, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:28] node _inReady_T_1 = and(entering, _inReady_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:26] node _inReady_T_2 = leq(UInt<1>(0h1), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 316:38] node _inReady_T_3 = mux(_inReady_T_1, _inReady_T_2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:16] node _inReady_T_4 = bits(io.a.sExp, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 307:36] node _inReady_T_5 = leq(UInt<6>(0h35), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 316:38] node _inReady_T_6 = leq(UInt<6>(0h36), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 316:38] node _inReady_T_7 = mux(_inReady_T_4, _inReady_T_5, _inReady_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 307:24] node _inReady_T_8 = leq(UInt<6>(0h37), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 316:38] node _inReady_T_9 = mux(io.sqrtOp, _inReady_T_7, _inReady_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 306:20] node _inReady_T_10 = mux(entering_normalCase, _inReady_T_9, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 305:16] node _inReady_T_11 = or(_inReady_T_3, _inReady_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:57] node _inReady_T_12 = eq(entering, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:17] node _inReady_T_13 = eq(skipCycle2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:31] node _inReady_T_14 = and(_inReady_T_12, _inReady_T_13) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:28] node _inReady_T_15 = mux(processTwoBits, UInt<2>(0h2), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:61] node _inReady_T_16 = sub(cycleNum, _inReady_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:56] node _inReady_T_17 = tail(_inReady_T_16, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:56] node _inReady_T_18 = leq(_inReady_T_17, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 316:38] node _inReady_T_19 = mux(_inReady_T_14, _inReady_T_18, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:16] node _inReady_T_20 = or(_inReady_T_11, _inReady_T_19) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 311:15] node _inReady_T_21 = leq(UInt<1>(0h1), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 316:38] node _inReady_T_22 = mux(skipCycle2, _inReady_T_21, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 313:16] node _inReady_T_23 = or(_inReady_T_20, _inReady_T_22) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:95] node _inReady_T_24 = bits(_inReady_T_23, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 316:46] connect inReady, _inReady_T_24 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 316:17] node _rawOutValid_T = eq(normalCase_S, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:28] node _rawOutValid_T_1 = and(entering, _rawOutValid_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:26] node _rawOutValid_T_2 = eq(UInt<1>(0h1), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 317:42] node _rawOutValid_T_3 = mux(_rawOutValid_T_1, _rawOutValid_T_2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:16] node _rawOutValid_T_4 = bits(io.a.sExp, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 307:36] node _rawOutValid_T_5 = eq(UInt<6>(0h35), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 317:42] node _rawOutValid_T_6 = eq(UInt<6>(0h36), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 317:42] node _rawOutValid_T_7 = mux(_rawOutValid_T_4, _rawOutValid_T_5, _rawOutValid_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 307:24] node _rawOutValid_T_8 = eq(UInt<6>(0h37), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 317:42] node _rawOutValid_T_9 = mux(io.sqrtOp, _rawOutValid_T_7, _rawOutValid_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 306:20] node _rawOutValid_T_10 = mux(entering_normalCase, _rawOutValid_T_9, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 305:16] node _rawOutValid_T_11 = or(_rawOutValid_T_3, _rawOutValid_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:57] node _rawOutValid_T_12 = eq(entering, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:17] node _rawOutValid_T_13 = eq(skipCycle2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:31] node _rawOutValid_T_14 = and(_rawOutValid_T_12, _rawOutValid_T_13) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:28] node _rawOutValid_T_15 = mux(processTwoBits, UInt<2>(0h2), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:61] node _rawOutValid_T_16 = sub(cycleNum, _rawOutValid_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:56] node _rawOutValid_T_17 = tail(_rawOutValid_T_16, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:56] node _rawOutValid_T_18 = eq(_rawOutValid_T_17, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 317:42] node _rawOutValid_T_19 = mux(_rawOutValid_T_14, _rawOutValid_T_18, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:16] node _rawOutValid_T_20 = or(_rawOutValid_T_11, _rawOutValid_T_19) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 311:15] node _rawOutValid_T_21 = eq(UInt<1>(0h1), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 317:42] node _rawOutValid_T_22 = mux(skipCycle2, _rawOutValid_T_21, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 313:16] node _rawOutValid_T_23 = or(_rawOutValid_T_20, _rawOutValid_T_22) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:95] node _rawOutValid_T_24 = bits(_rawOutValid_T_23, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 317:51] connect rawOutValid, _rawOutValid_T_24 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 317:21] node _cycleNum_T = eq(normalCase_S, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:28] node _cycleNum_T_1 = and(entering, _cycleNum_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:26] node _cycleNum_T_2 = mux(_cycleNum_T_1, UInt<1>(0h1), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:16] node _cycleNum_T_3 = bits(io.a.sExp, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 307:36] node _cycleNum_T_4 = mux(_cycleNum_T_3, UInt<6>(0h35), UInt<6>(0h36)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 307:24] node _cycleNum_T_5 = mux(io.sqrtOp, _cycleNum_T_4, UInt<6>(0h37)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 306:20] node _cycleNum_T_6 = mux(entering_normalCase, _cycleNum_T_5, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 305:16] node _cycleNum_T_7 = or(_cycleNum_T_2, _cycleNum_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 304:57] node _cycleNum_T_8 = eq(entering, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:17] node _cycleNum_T_9 = eq(skipCycle2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:31] node _cycleNum_T_10 = and(_cycleNum_T_8, _cycleNum_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:28] node _cycleNum_T_11 = mux(processTwoBits, UInt<2>(0h2), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:61] node _cycleNum_T_12 = sub(cycleNum, _cycleNum_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:56] node _cycleNum_T_13 = tail(_cycleNum_T_12, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:56] node _cycleNum_T_14 = mux(_cycleNum_T_10, _cycleNum_T_13, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:16] node _cycleNum_T_15 = or(_cycleNum_T_7, _cycleNum_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 311:15] node _cycleNum_T_16 = mux(skipCycle2, UInt<1>(0h1), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 313:16] node _cycleNum_T_17 = or(_cycleNum_T_15, _cycleNum_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 312:95] connect cycleNum, _cycleNum_T_17 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 318:18] connect io.inReady, inReady @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 321:16] when entering : @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 325:21] connect sqrtOp_Z, io.sqrtOp @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 326:20] connect majorExc_Z, majorExc_S @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 327:20] connect isNaN_Z, isNaN_S @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 328:20] connect isInf_Z, isInf_S @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 329:20] connect isZero_Z, isZero_S @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 330:20] connect sign_Z, sign_S @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 331:20] node _sExp_Z_T = shr(io.a.sExp, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 334:29] node _sExp_Z_T_1 = add(_sExp_Z_T, asSInt(UInt<12>(0h400))) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 334:34] node _sExp_Z_T_2 = mux(io.sqrtOp, _sExp_Z_T_1, sSatExpQuot_S_div) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 333:16] connect sExp_Z, _sExp_Z_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 332:16] connect roundingMode_Z, io.roundingMode @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 337:24] node _T_2 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 339:23] node _T_3 = and(_T_2, sqrtOp_Z) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 339:33] node _T_4 = or(entering, _T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 339:20] when _T_4 : @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 339:46] node _fractB_Z_T = eq(io.sqrtOp, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 341:28] node _fractB_Z_T_1 = and(inReady, _fractB_Z_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 341:25] node _fractB_Z_T_2 = bits(io.b.sig, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 341:73] node _fractB_Z_T_3 = shl(_fractB_Z_T_2, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 341:90] node _fractB_Z_T_4 = mux(_fractB_Z_T_1, _fractB_Z_T_3, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 341:16] node _fractB_Z_T_5 = and(inReady, io.sqrtOp) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 342:25] node _fractB_Z_T_6 = bits(io.a.sExp, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 342:52] node _fractB_Z_T_7 = and(_fractB_Z_T_5, _fractB_Z_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 342:38] node _fractB_Z_T_8 = mux(_fractB_Z_T_7, UInt<52>(0h8000000000000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 342:16] node _fractB_Z_T_9 = or(_fractB_Z_T_4, _fractB_Z_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 341:100] node _fractB_Z_T_10 = and(inReady, io.sqrtOp) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 343:25] node _fractB_Z_T_11 = bits(io.a.sExp, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 343:54] node _fractB_Z_T_12 = eq(_fractB_Z_T_11, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 343:41] node _fractB_Z_T_13 = and(_fractB_Z_T_10, _fractB_Z_T_12) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 343:38] node _fractB_Z_T_14 = mux(_fractB_Z_T_13, UInt<53>(0h10000000000000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 343:16] node _fractB_Z_T_15 = or(_fractB_Z_T_9, _fractB_Z_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 342:100] node _fractB_Z_T_16 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 344:17] node _fractB_Z_T_17 = and(_fractB_Z_T_16, processTwoBits) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 344:42] node _fractB_Z_T_18 = shr(fractB_Z, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 344:71] node _fractB_Z_T_19 = mux(_fractB_Z_T_17, _fractB_Z_T_18, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 344:16] node _fractB_Z_T_20 = or(_fractB_Z_T_15, _fractB_Z_T_19) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 343:100] node _fractB_Z_T_21 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 345:17] node _fractB_Z_T_22 = eq(processTwoBits, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 345:45] node _fractB_Z_T_23 = and(_fractB_Z_T_21, _fractB_Z_T_22) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 345:42] node _fractB_Z_T_24 = shr(fractB_Z, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 345:71] node _fractB_Z_T_25 = mux(_fractB_Z_T_23, _fractB_Z_T_24, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 345:16] node _fractB_Z_T_26 = or(_fractB_Z_T_20, _fractB_Z_T_25) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 344:100] connect fractB_Z, _fractB_Z_T_26 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 340:18] node _rem_T = eq(oddSqrt_S, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 351:24] node _rem_T_1 = and(inReady, _rem_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 351:21] node _rem_T_2 = shl(io.a.sig, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 351:47] node _rem_T_3 = mux(_rem_T_1, _rem_T_2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 351:12] node _rem_T_4 = and(inReady, oddSqrt_S) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 352:21] node _rem_T_5 = bits(io.a.sig, 52, 51) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 353:27] node _rem_T_6 = sub(_rem_T_5, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 353:56] node _rem_T_7 = tail(_rem_T_6, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 353:56] node _rem_T_8 = bits(io.a.sig, 50, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 354:27] node _rem_T_9 = shl(_rem_T_8, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 354:44] node _rem_T_10 = cat(_rem_T_7, _rem_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 353:16] node _rem_T_11 = mux(_rem_T_4, _rem_T_10, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 352:12] node _rem_T_12 = or(_rem_T_3, _rem_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 351:57] node _rem_T_13 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 358:13] node _rem_T_14 = shl(rem_Z, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 358:29] node _rem_T_15 = mux(_rem_T_13, _rem_T_14, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 358:12] node rem = or(_rem_T_12, _rem_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 357:11] node _bitMask_T = dshl(UInt<1>(0h1), cycleNum) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 359:23] node bitMask = shr(_bitMask_T, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 359:34] node _trialTerm_T = eq(io.sqrtOp, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 361:24] node _trialTerm_T_1 = and(inReady, _trialTerm_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 361:21] node _trialTerm_T_2 = shl(io.b.sig, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 361:48] node _trialTerm_T_3 = mux(_trialTerm_T_1, _trialTerm_T_2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 361:12] node _trialTerm_T_4 = and(inReady, evenSqrt_S) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 362:21] node _trialTerm_T_5 = mux(_trialTerm_T_4, UInt<54>(0h20000000000000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 362:12] node _trialTerm_T_6 = or(_trialTerm_T_3, _trialTerm_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 361:74] node _trialTerm_T_7 = and(inReady, oddSqrt_S) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 363:21] node _trialTerm_T_8 = mux(_trialTerm_T_7, UInt<55>(0h50000000000000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 363:12] node _trialTerm_T_9 = or(_trialTerm_T_6, _trialTerm_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 362:74] node _trialTerm_T_10 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 364:13] node _trialTerm_T_11 = mux(_trialTerm_T_10, fractB_Z, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 364:12] node _trialTerm_T_12 = or(_trialTerm_T_9, _trialTerm_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 363:74] node _trialTerm_T_13 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 365:13] node _trialTerm_T_14 = eq(sqrtOp_Z, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 365:26] node _trialTerm_T_15 = and(_trialTerm_T_13, _trialTerm_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 365:23] node _trialTerm_T_16 = shl(UInt<1>(0h1), 53) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 365:42] node _trialTerm_T_17 = mux(_trialTerm_T_15, _trialTerm_T_16, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 365:12] node _trialTerm_T_18 = or(_trialTerm_T_12, _trialTerm_T_17) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 364:74] node _trialTerm_T_19 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 366:13] node _trialTerm_T_20 = and(_trialTerm_T_19, sqrtOp_Z) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 366:23] node _trialTerm_T_21 = shl(sigX_Z, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 366:44] node _trialTerm_T_22 = mux(_trialTerm_T_20, _trialTerm_T_21, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 366:12] node trialTerm = or(_trialTerm_T_18, _trialTerm_T_22) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 365:74] node _trialRem_T = cvt(rem) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 367:24] node _trialRem_T_1 = cvt(trialTerm) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 367:42] node trialRem = sub(_trialRem_T, _trialRem_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 367:29] node newBit = leq(asSInt(UInt<1>(0h0)), trialRem) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 368:23] node _nextRem_Z_T = asUInt(trialRem) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 370:42] node _nextRem_Z_T_1 = mux(newBit, _nextRem_Z_T, rem) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 370:24] node nextRem_Z = bits(_nextRem_Z_T_1, 54, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 370:54] node rem2 = shl(nextRem_Z, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 371:25] node _trialTerm2_newBit0_T = shr(fractB_Z, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 372:52] node _trialTerm2_newBit0_T_1 = shl(sigX_Z, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 372:64] node _trialTerm2_newBit0_T_2 = or(_trialTerm2_newBit0_T, _trialTerm2_newBit0_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 372:56] node _trialTerm2_newBit0_T_3 = shl(UInt<1>(0h1), 53) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 372:85] node _trialTerm2_newBit0_T_4 = or(fractB_Z, _trialTerm2_newBit0_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 372:78] node trialTerm2_newBit0 = mux(sqrtOp_Z, _trialTerm2_newBit0_T_2, _trialTerm2_newBit0_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 372:33] node _trialTerm2_newBit1_T = shl(fractB_Z, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 373:73] node _trialTerm2_newBit1_T_1 = mux(sqrtOp_Z, _trialTerm2_newBit1_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 373:54] node trialTerm2_newBit1 = or(trialTerm2_newBit0, _trialTerm2_newBit1_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 373:49] node _trialRem2_T = shl(trialRem, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 376:22] node _trialRem2_T_1 = cvt(trialTerm2_newBit1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 376:48] node _trialRem2_T_2 = sub(_trialRem2_T, _trialRem2_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 376:27] node _trialRem2_T_3 = tail(_trialRem2_T_2, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 376:27] node _trialRem2_T_4 = asSInt(_trialRem2_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 376:27] node _trialRem2_T_5 = shl(rem_Z, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 377:19] node _trialRem2_T_6 = bits(_trialRem2_T_5, 55, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 377:23] node _trialRem2_T_7 = cvt(_trialRem2_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 377:39] node _trialRem2_T_8 = cvt(trialTerm2_newBit0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 377:65] node _trialRem2_T_9 = sub(_trialRem2_T_7, _trialRem2_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 377:44] node _trialRem2_T_10 = tail(_trialRem2_T_9, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 377:44] node _trialRem2_T_11 = asSInt(_trialRem2_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 377:44] node trialRem2 = mux(newBit, _trialRem2_T_4, _trialRem2_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 375:12] node newBit2 = leq(asSInt(UInt<1>(0h0)), trialRem2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 378:24] node _nextNotZeroRem_Z_T = or(inReady, newBit) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 379:40] node _nextNotZeroRem_Z_T_1 = neq(trialRem, asSInt(UInt<1>(0h0))) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 379:60] node nextNotZeroRem_Z = mux(_nextNotZeroRem_Z_T, _nextNotZeroRem_Z_T_1, notZeroRem_Z) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 379:31] node _nextNotZeroRem_Z_2_T = and(processTwoBits, newBit) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 381:24] node _nextNotZeroRem_Z_2_T_1 = shl(trialRem, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 381:53] node _nextNotZeroRem_Z_2_T_2 = cvt(trialTerm2_newBit1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 381:79] node _nextNotZeroRem_Z_2_T_3 = sub(_nextNotZeroRem_Z_2_T_1, _nextNotZeroRem_Z_2_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 381:58] node _nextNotZeroRem_Z_2_T_4 = tail(_nextNotZeroRem_Z_2_T_3, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 381:58] node _nextNotZeroRem_Z_2_T_5 = asSInt(_nextNotZeroRem_Z_2_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 381:58] node _nextNotZeroRem_Z_2_T_6 = lt(asSInt(UInt<1>(0h0)), _nextNotZeroRem_Z_2_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 381:42] node _nextNotZeroRem_Z_2_T_7 = and(_nextNotZeroRem_Z_2_T, _nextNotZeroRem_Z_2_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 381:34] node _nextNotZeroRem_Z_2_T_8 = eq(newBit, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:27] node _nextNotZeroRem_Z_2_T_9 = and(processTwoBits, _nextNotZeroRem_Z_2_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:24] node _nextNotZeroRem_Z_2_T_10 = shl(rem_Z, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:51] node _nextNotZeroRem_Z_2_T_11 = bits(_nextNotZeroRem_Z_2_T_10, 55, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:55] node _nextNotZeroRem_Z_2_T_12 = cvt(_nextNotZeroRem_Z_2_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:71] node _nextNotZeroRem_Z_2_T_13 = cvt(trialTerm2_newBit0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:97] node _nextNotZeroRem_Z_2_T_14 = sub(_nextNotZeroRem_Z_2_T_12, _nextNotZeroRem_Z_2_T_13) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:76] node _nextNotZeroRem_Z_2_T_15 = tail(_nextNotZeroRem_Z_2_T_14, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:76] node _nextNotZeroRem_Z_2_T_16 = asSInt(_nextNotZeroRem_Z_2_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:76] node _nextNotZeroRem_Z_2_T_17 = lt(asSInt(UInt<1>(0h0)), _nextNotZeroRem_Z_2_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:43] node _nextNotZeroRem_Z_2_T_18 = and(_nextNotZeroRem_Z_2_T_9, _nextNotZeroRem_Z_2_T_17) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:35] node _nextNotZeroRem_Z_2_T_19 = or(_nextNotZeroRem_Z_2_T_7, _nextNotZeroRem_Z_2_T_18) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 381:85] node _nextNotZeroRem_Z_2_T_20 = and(processTwoBits, newBit2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 383:26] node _nextNotZeroRem_Z_2_T_21 = eq(_nextNotZeroRem_Z_2_T_20, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 383:9] node _nextNotZeroRem_Z_2_T_22 = and(_nextNotZeroRem_Z_2_T_21, nextNotZeroRem_Z) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 383:38] node nextNotZeroRem_Z_2 = or(_nextNotZeroRem_Z_2_T_19, _nextNotZeroRem_Z_2_T_22) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 382:103] node _nextRem_Z_2_T = and(processTwoBits, newBit2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 385:28] node _nextRem_Z_2_T_1 = asUInt(trialRem2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 385:51] node _nextRem_Z_2_T_2 = bits(_nextRem_Z_2_T_1, 54, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 385:57] node _nextRem_Z_2_T_3 = mux(_nextRem_Z_2_T, _nextRem_Z_2_T_2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 385:12] node _nextRem_Z_2_T_4 = eq(newBit2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 386:31] node _nextRem_Z_2_T_5 = and(processTwoBits, _nextRem_Z_2_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 386:28] node _nextRem_Z_2_T_6 = bits(rem2, 54, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 386:45] node _nextRem_Z_2_T_7 = mux(_nextRem_Z_2_T_5, _nextRem_Z_2_T_6, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 386:12] node _nextRem_Z_2_T_8 = or(_nextRem_Z_2_T_3, _nextRem_Z_2_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 385:81] node _nextRem_Z_2_T_9 = eq(processTwoBits, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 387:13] node _nextRem_Z_2_T_10 = mux(_nextRem_Z_2_T_9, nextRem_Z, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 387:12] node nextRem_Z_2 = or(_nextRem_Z_2_T_8, _nextRem_Z_2_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 386:83] node _T_5 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 389:23] node _T_6 = or(entering, _T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 389:20] when _T_6 : @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 389:34] connect notZeroRem_Z, nextNotZeroRem_Z_2 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 390:22] connect rem_Z, nextRem_Z_2 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 391:15] node _sigX_Z_T = eq(io.sqrtOp, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 393:28] node _sigX_Z_T_1 = and(inReady, _sigX_Z_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 393:25] node _sigX_Z_T_2 = shl(newBit, 54) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 393:50] node _sigX_Z_T_3 = mux(_sigX_Z_T_1, _sigX_Z_T_2, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 393:16] node _sigX_Z_T_4 = and(inReady, io.sqrtOp) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 394:25] node _sigX_Z_T_5 = mux(_sigX_Z_T_4, UInt<54>(0h20000000000000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 394:16] node _sigX_Z_T_6 = or(_sigX_Z_T_3, _sigX_Z_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 393:74] node _sigX_Z_T_7 = and(inReady, oddSqrt_S) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 395:25] node _sigX_Z_T_8 = shl(newBit, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 395:50] node _sigX_Z_T_9 = mux(_sigX_Z_T_7, _sigX_Z_T_8, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 395:16] node _sigX_Z_T_10 = or(_sigX_Z_T_6, _sigX_Z_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 394:74] node _sigX_Z_T_11 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 396:17] node _sigX_Z_T_12 = mux(_sigX_Z_T_11, sigX_Z, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 396:16] node _sigX_Z_T_13 = or(_sigX_Z_T_10, _sigX_Z_T_12) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 395:74] node _sigX_Z_T_14 = eq(inReady, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 397:17] node _sigX_Z_T_15 = and(_sigX_Z_T_14, newBit) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 397:27] node _sigX_Z_T_16 = mux(_sigX_Z_T_15, bitMask, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 397:16] node _sigX_Z_T_17 = or(_sigX_Z_T_13, _sigX_Z_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 396:74] node _sigX_Z_T_18 = and(processTwoBits, newBit2) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 398:32] node _sigX_Z_T_19 = shr(bitMask, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 398:51] node _sigX_Z_T_20 = mux(_sigX_Z_T_18, _sigX_Z_T_19, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 398:16] node _sigX_Z_T_21 = or(_sigX_Z_T_17, _sigX_Z_T_20) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 397:74] connect sigX_Z, _sigX_Z_T_21 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 392:16] node _io_rawOutValid_div_T = eq(sqrtOp_Z, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 403:43] node _io_rawOutValid_div_T_1 = and(rawOutValid, _io_rawOutValid_div_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 403:40] connect io.rawOutValid_div, _io_rawOutValid_div_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 403:25] node _io_rawOutValid_sqrt_T = and(rawOutValid, sqrtOp_Z) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 404:40] connect io.rawOutValid_sqrt, _io_rawOutValid_sqrt_T @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 404:25] connect io.roundingModeOut, roundingMode_Z @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 405:25] node _io_invalidExc_T = and(majorExc_Z, isNaN_Z) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 406:36] connect io.invalidExc, _io_invalidExc_T @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 406:22] node _io_infiniteExc_T = eq(isNaN_Z, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 407:39] node _io_infiniteExc_T_1 = and(majorExc_Z, _io_infiniteExc_T) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 407:36] connect io.infiniteExc, _io_infiniteExc_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 407:22] connect io.rawOut.isNaN, isNaN_Z @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 408:22] connect io.rawOut.isInf, isInf_Z @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 409:22] connect io.rawOut.isZero, isZero_Z @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 410:22] connect io.rawOut.sign, sign_Z @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 411:22] connect io.rawOut.sExp, sExp_Z @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 412:22] node _io_rawOut_sig_T = shl(sigX_Z, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 413:31] node _io_rawOut_sig_T_1 = or(_io_rawOut_sig_T, notZeroRem_Z) @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 413:35] connect io.rawOut.sig, _io_rawOut_sig_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 413:22] module DivSqrtRecFNToRaw_small_1 : @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 421:5] input clock : Clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 421:5] input reset : Reset @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 421:5] output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}} @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 424:16] inst divSqrtRawFN of DivSqrtRawFN_small_1 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 444:15] connect divSqrtRawFN.clock, clock connect divSqrtRawFN.reset, reset connect io.inReady, divSqrtRawFN.io.inReady @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 446:16] connect divSqrtRawFN.io.inValid, io.inValid @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 447:34] connect divSqrtRawFN.io.sqrtOp, io.sqrtOp @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 448:34] node divSqrtRawFN_io_a_exp = bits(io.a, 63, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _divSqrtRawFN_io_a_isZero_T = bits(divSqrtRawFN_io_a_exp, 11, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node divSqrtRawFN_io_a_isZero = eq(_divSqrtRawFN_io_a_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _divSqrtRawFN_io_a_isSpecial_T = bits(divSqrtRawFN_io_a_exp, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node divSqrtRawFN_io_a_isSpecial = eq(_divSqrtRawFN_io_a_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire divSqrtRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _divSqrtRawFN_io_a_out_isNaN_T = bits(divSqrtRawFN_io_a_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _divSqrtRawFN_io_a_out_isNaN_T_1 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect divSqrtRawFN_io_a_out.isNaN, _divSqrtRawFN_io_a_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _divSqrtRawFN_io_a_out_isInf_T = bits(divSqrtRawFN_io_a_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _divSqrtRawFN_io_a_out_isInf_T_1 = eq(_divSqrtRawFN_io_a_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _divSqrtRawFN_io_a_out_isInf_T_2 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect divSqrtRawFN_io_a_out.isInf, _divSqrtRawFN_io_a_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect divSqrtRawFN_io_a_out.isZero, divSqrtRawFN_io_a_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _divSqrtRawFN_io_a_out_sign_T = bits(io.a, 64, 64) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect divSqrtRawFN_io_a_out.sign, _divSqrtRawFN_io_a_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _divSqrtRawFN_io_a_out_sExp_T = cvt(divSqrtRawFN_io_a_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect divSqrtRawFN_io_a_out.sExp, _divSqrtRawFN_io_a_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _divSqrtRawFN_io_a_out_sig_T = eq(divSqrtRawFN_io_a_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _divSqrtRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_a_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _divSqrtRawFN_io_a_out_sig_T_2 = bits(io.a, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _divSqrtRawFN_io_a_out_sig_T_3 = cat(_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect divSqrtRawFN_io_a_out.sig, _divSqrtRawFN_io_a_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] connect divSqrtRawFN.io.a.sig, divSqrtRawFN_io_a_out.sig @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 449:34] connect divSqrtRawFN.io.a.sExp, divSqrtRawFN_io_a_out.sExp @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 449:34] connect divSqrtRawFN.io.a.sign, divSqrtRawFN_io_a_out.sign @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 449:34] connect divSqrtRawFN.io.a.isZero, divSqrtRawFN_io_a_out.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 449:34] connect divSqrtRawFN.io.a.isInf, divSqrtRawFN_io_a_out.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 449:34] connect divSqrtRawFN.io.a.isNaN, divSqrtRawFN_io_a_out.isNaN @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 449:34] node divSqrtRawFN_io_b_exp = bits(io.b, 63, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _divSqrtRawFN_io_b_isZero_T = bits(divSqrtRawFN_io_b_exp, 11, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node divSqrtRawFN_io_b_isZero = eq(_divSqrtRawFN_io_b_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _divSqrtRawFN_io_b_isSpecial_T = bits(divSqrtRawFN_io_b_exp, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node divSqrtRawFN_io_b_isSpecial = eq(_divSqrtRawFN_io_b_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire divSqrtRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _divSqrtRawFN_io_b_out_isNaN_T = bits(divSqrtRawFN_io_b_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _divSqrtRawFN_io_b_out_isNaN_T_1 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect divSqrtRawFN_io_b_out.isNaN, _divSqrtRawFN_io_b_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _divSqrtRawFN_io_b_out_isInf_T = bits(divSqrtRawFN_io_b_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _divSqrtRawFN_io_b_out_isInf_T_1 = eq(_divSqrtRawFN_io_b_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _divSqrtRawFN_io_b_out_isInf_T_2 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect divSqrtRawFN_io_b_out.isInf, _divSqrtRawFN_io_b_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect divSqrtRawFN_io_b_out.isZero, divSqrtRawFN_io_b_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _divSqrtRawFN_io_b_out_sign_T = bits(io.b, 64, 64) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect divSqrtRawFN_io_b_out.sign, _divSqrtRawFN_io_b_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _divSqrtRawFN_io_b_out_sExp_T = cvt(divSqrtRawFN_io_b_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect divSqrtRawFN_io_b_out.sExp, _divSqrtRawFN_io_b_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _divSqrtRawFN_io_b_out_sig_T = eq(divSqrtRawFN_io_b_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _divSqrtRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_b_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _divSqrtRawFN_io_b_out_sig_T_2 = bits(io.b, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _divSqrtRawFN_io_b_out_sig_T_3 = cat(_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect divSqrtRawFN_io_b_out.sig, _divSqrtRawFN_io_b_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] connect divSqrtRawFN.io.b.sig, divSqrtRawFN_io_b_out.sig @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 450:34] connect divSqrtRawFN.io.b.sExp, divSqrtRawFN_io_b_out.sExp @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 450:34] connect divSqrtRawFN.io.b.sign, divSqrtRawFN_io_b_out.sign @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 450:34] connect divSqrtRawFN.io.b.isZero, divSqrtRawFN_io_b_out.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 450:34] connect divSqrtRawFN.io.b.isInf, divSqrtRawFN_io_b_out.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 450:34] connect divSqrtRawFN.io.b.isNaN, divSqrtRawFN_io_b_out.isNaN @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 450:34] connect divSqrtRawFN.io.roundingMode, io.roundingMode @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 451:34] connect io.rawOutValid_div, divSqrtRawFN.io.rawOutValid_div @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 453:25] connect io.rawOutValid_sqrt, divSqrtRawFN.io.rawOutValid_sqrt @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 454:25] connect io.roundingModeOut, divSqrtRawFN.io.roundingModeOut @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 455:25] connect io.invalidExc, divSqrtRawFN.io.invalidExc @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 456:25] connect io.infiniteExc, divSqrtRawFN.io.infiniteExc @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 457:25] connect io.rawOut, divSqrtRawFN.io.rawOut @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 458:25] module RoundAnyRawFNToRecFN_6 : @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 48:5] output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 57:16] node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 89:53] node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 90:53] node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 91:53] node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 92:53] node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 93:53] node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 94:53] node _roundMagUp_T = and(roundingMode_min, io.in.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:27] node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:66] node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:63] node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 97:42] node adjustedSig = shl(io.in.sig, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 113:22] node doShiftSigDown1 = bits(adjustedSig, 55, 55) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 119:57] wire common_expOut : UInt<12> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 121:31] wire common_fractOut : UInt<52> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 122:31] wire common_overflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 123:37] wire common_totalUnderflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 124:37] wire common_underflow : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 125:37] wire common_inexact : UInt<1> @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 126:37] node _roundMask_T = bits(io.in.sExp, 11, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 155:37] node _roundMask_T_1 = not(_roundMask_T) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 52:21] node roundMask_msb = bits(_roundMask_T_1, 11, 11) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs = bits(_roundMask_T_1, 10, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_1 = bits(roundMask_lsbs, 10, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_1 = bits(roundMask_lsbs, 9, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_2 = bits(roundMask_lsbs_1, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 8, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_3 = bits(roundMask_lsbs_2, 8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_3 = bits(roundMask_lsbs_2, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_4 = bits(roundMask_lsbs_3, 7, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_4 = bits(roundMask_lsbs_3, 6, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_5 = bits(roundMask_lsbs_4, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_5 = bits(roundMask_lsbs_4, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 76:56] node _roundMask_T_2 = bits(roundMask_shift, 63, 13) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 78:22] node _roundMask_T_3 = bits(_roundMask_T_2, 31, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_4 = shl(UInt<16>(0hffff), 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_5 = xor(UInt<32>(0hffffffff), _roundMask_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_6 = shr(_roundMask_T_3, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_8 = bits(_roundMask_T_3, 15, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_9 = shl(_roundMask_T_8, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_10 = not(_roundMask_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_13 = bits(_roundMask_T_5, 23, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_14 = shl(_roundMask_T_13, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_16 = shr(_roundMask_T_12, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_18 = bits(_roundMask_T_12, 23, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_19 = shl(_roundMask_T_18, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_20 = not(_roundMask_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_23 = bits(_roundMask_T_15, 27, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_24 = shl(_roundMask_T_23, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_26 = shr(_roundMask_T_22, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_28 = bits(_roundMask_T_22, 27, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_29 = shl(_roundMask_T_28, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_30 = not(_roundMask_T_25) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_33 = bits(_roundMask_T_25, 29, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_34 = shl(_roundMask_T_33, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_36 = shr(_roundMask_T_32, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_38 = bits(_roundMask_T_32, 29, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_39 = shl(_roundMask_T_38, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_40 = not(_roundMask_T_35) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_43 = bits(_roundMask_T_35, 30, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_44 = shl(_roundMask_T_43, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_45 = xor(_roundMask_T_35, _roundMask_T_44) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_46 = shr(_roundMask_T_42, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_47 = and(_roundMask_T_46, _roundMask_T_45) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_48 = bits(_roundMask_T_42, 30, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_49 = shl(_roundMask_T_48, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_50 = not(_roundMask_T_45) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_51 = and(_roundMask_T_49, _roundMask_T_50) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_52 = or(_roundMask_T_47, _roundMask_T_51) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_53 = bits(_roundMask_T_2, 50, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_54 = bits(_roundMask_T_53, 15, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_55 = shl(UInt<8>(0hff), 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_56 = xor(UInt<16>(0hffff), _roundMask_T_55) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_57 = shr(_roundMask_T_54, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_58 = and(_roundMask_T_57, _roundMask_T_56) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_59 = bits(_roundMask_T_54, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_60 = shl(_roundMask_T_59, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_61 = not(_roundMask_T_56) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_62 = and(_roundMask_T_60, _roundMask_T_61) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_63 = or(_roundMask_T_58, _roundMask_T_62) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_64 = bits(_roundMask_T_56, 11, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_65 = shl(_roundMask_T_64, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_66 = xor(_roundMask_T_56, _roundMask_T_65) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_67 = shr(_roundMask_T_63, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_68 = and(_roundMask_T_67, _roundMask_T_66) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_69 = bits(_roundMask_T_63, 11, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_70 = shl(_roundMask_T_69, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_71 = not(_roundMask_T_66) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_72 = and(_roundMask_T_70, _roundMask_T_71) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_73 = or(_roundMask_T_68, _roundMask_T_72) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_74 = bits(_roundMask_T_66, 13, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_75 = shl(_roundMask_T_74, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_76 = xor(_roundMask_T_66, _roundMask_T_75) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_77 = shr(_roundMask_T_73, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_78 = and(_roundMask_T_77, _roundMask_T_76) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_79 = bits(_roundMask_T_73, 13, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_80 = shl(_roundMask_T_79, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_81 = not(_roundMask_T_76) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_82 = and(_roundMask_T_80, _roundMask_T_81) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_83 = or(_roundMask_T_78, _roundMask_T_82) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_84 = bits(_roundMask_T_76, 14, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_85 = shl(_roundMask_T_84, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_86 = xor(_roundMask_T_76, _roundMask_T_85) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_87 = shr(_roundMask_T_83, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_88 = and(_roundMask_T_87, _roundMask_T_86) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_89 = bits(_roundMask_T_83, 14, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_90 = shl(_roundMask_T_89, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_91 = not(_roundMask_T_86) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_92 = and(_roundMask_T_90, _roundMask_T_91) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_93 = or(_roundMask_T_88, _roundMask_T_92) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_94 = bits(_roundMask_T_53, 18, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_95 = bits(_roundMask_T_94, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_96 = bits(_roundMask_T_95, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_97 = bits(_roundMask_T_95, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_98 = cat(_roundMask_T_96, _roundMask_T_97) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_99 = bits(_roundMask_T_94, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_100 = cat(_roundMask_T_98, _roundMask_T_99) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_101 = cat(_roundMask_T_93, _roundMask_T_100) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_102 = cat(_roundMask_T_52, _roundMask_T_101) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_103 = not(_roundMask_T_102) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:32] node _roundMask_T_104 = mux(roundMask_msb_5, UInt<1>(0h0), _roundMask_T_103) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:21] node _roundMask_T_105 = not(_roundMask_T_104) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:17] node _roundMask_T_106 = not(_roundMask_T_105) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:32] node _roundMask_T_107 = mux(roundMask_msb_4, UInt<1>(0h0), _roundMask_T_106) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:21] node _roundMask_T_108 = not(_roundMask_T_107) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:17] node _roundMask_T_109 = not(_roundMask_T_108) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:32] node _roundMask_T_110 = mux(roundMask_msb_3, UInt<1>(0h0), _roundMask_T_109) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:21] node _roundMask_T_111 = not(_roundMask_T_110) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:17] node _roundMask_T_112 = not(_roundMask_T_111) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:32] node _roundMask_T_113 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_112) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:21] node _roundMask_T_114 = not(_roundMask_T_113) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 73:17] node _roundMask_T_115 = cat(_roundMask_T_114, UInt<3>(0h7)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 68:58] node roundMask_msb_6 = bits(roundMask_lsbs_1, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_6 = bits(roundMask_lsbs_1, 8, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_7 = bits(roundMask_lsbs_6, 8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_7 = bits(roundMask_lsbs_6, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_8 = bits(roundMask_lsbs_7, 7, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_8 = bits(roundMask_lsbs_7, 6, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_msb_9 = bits(roundMask_lsbs_8, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 58:25] node roundMask_lsbs_9 = bits(roundMask_lsbs_8, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 59:26] node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_9) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 76:56] node _roundMask_T_116 = bits(roundMask_shift_1, 2, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 78:22] node _roundMask_T_117 = bits(_roundMask_T_116, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_118 = bits(_roundMask_T_117, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_119 = bits(_roundMask_T_117, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_120 = cat(_roundMask_T_118, _roundMask_T_119) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_121 = bits(_roundMask_T_116, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_122 = cat(_roundMask_T_120, _roundMask_T_121) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 77:20] node _roundMask_T_123 = mux(roundMask_msb_9, _roundMask_T_122, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 62:24] node _roundMask_T_124 = mux(roundMask_msb_8, _roundMask_T_123, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 62:24] node _roundMask_T_125 = mux(roundMask_msb_7, _roundMask_T_124, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 62:24] node _roundMask_T_126 = mux(roundMask_msb_6, _roundMask_T_125, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 62:24] node _roundMask_T_127 = mux(roundMask_msb_1, _roundMask_T_115, _roundMask_T_126) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 67:24] node _roundMask_T_128 = mux(roundMask_msb, _roundMask_T_127, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 62:24] node _roundMask_T_129 = or(_roundMask_T_128, doShiftSigDown1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 158:23] node roundMask = cat(_roundMask_T_129, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 158:42] node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 161:41] node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 161:53] node _roundPosMask_T = not(shiftedRoundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 162:28] node roundPosMask = and(_roundPosMask_T, roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 162:46] node _roundPosBit_T = and(adjustedSig, roundPosMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 163:40] node roundPosBit = orr(_roundPosBit_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 163:56] node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 164:42] node anyRoundExtra = orr(_anyRoundExtra_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 164:62] node anyRound = or(roundPosBit, anyRoundExtra) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 165:36] node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 168:38] node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 168:67] node _roundIncr_T_2 = and(roundMagUp, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 170:29] node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 169:31] node _roundedSig_T = or(adjustedSig, roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:32] node _roundedSig_T_1 = shr(_roundedSig_T, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:44] node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:49] node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:49] node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 175:30] node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:64] node _roundedSig_T_6 = shr(roundMask, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 176:35] node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<55>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:25] node _roundedSig_T_8 = not(_roundedSig_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 174:21] node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 173:57] node _roundedSig_T_10 = not(roundMask) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:32] node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:30] node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:43] node _roundedSig_T_13 = and(roundingMode_odd, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:42] node _roundedSig_T_14 = shr(roundPosMask, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:67] node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 180:24] node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 179:47] node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 172:16] node _sRoundedExp_T = shr(roundedSig, 53) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:54] node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:76] node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 184:40] node _common_expOut_T = bits(sRoundedExp, 11, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 186:37] connect common_expOut, _common_expOut_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 186:23] node _common_fractOut_T = bits(roundedSig, 52, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 189:27] node _common_fractOut_T_1 = bits(roundedSig, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 190:27] node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 188:16] connect common_fractOut, _common_fractOut_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 187:25] node _common_overflow_T = shr(sRoundedExp, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 195:30] node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 195:50] connect common_overflow, _common_overflow_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 192:25] node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<11>(0h3ce))) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 199:31] connect common_totalUnderflow, _common_totalUnderflow_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 196:31] node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:45] node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:61] node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 202:16] node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:44] node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:30] node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:63] node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:70] node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 204:49] node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 206:38] node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 206:67] node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 208:29] node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 207:46] node _roundCarry_T = bits(roundedSig, 54, 54) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 211:27] node _roundCarry_T_1 = bits(roundedSig, 53, 53) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 212:27] node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 210:16] node _common_underflow_T = shr(io.in.sExp, 11) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:49] node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:64] node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:32] node _common_underflow_T_3 = bits(roundMask, 3, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:57] node _common_underflow_T_4 = bits(roundMask, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:71] node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:30] node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 219:72] node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 221:49] node _common_underflow_T_8 = bits(roundMask, 4, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 223:49] node _common_underflow_T_9 = bits(roundMask, 3, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 224:49] node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 222:39] node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 222:34] node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 221:77] node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 225:38] node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 226:45] node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 226:60] node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 221:27] node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 220:76] node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 216:40] connect common_underflow, _common_underflow_T_18 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 214:26] node _common_inexact_T = or(common_totalUnderflow, anyRound) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 229:49] connect common_inexact, _common_inexact_T @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 229:24] node isNaNOut = or(io.invalidExc, io.in.isNaN) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 234:34] node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 235:49] node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:22] node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:36] node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:33] node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:64] node commonCase = and(_commonCase_T_2, _commonCase_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 236:61] node overflow = and(commonCase, common_overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 237:32] node underflow = and(commonCase, common_underflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 238:32] node _inexact_T = and(commonCase, common_inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 239:43] node inexact = or(overflow, _inexact_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 239:28] node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 242:32] node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 242:60] node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:20] node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:60] node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 244:45] node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 245:42] node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 245:39] node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 247:45] node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 247:32] node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 249:22] node _expOut_T = or(io.in.isZero, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:32] node _expOut_T_1 = mux(_expOut_T, UInt<12>(0he00), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:18] node _expOut_T_2 = not(_expOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 252:14] node _expOut_T_3 = and(common_expOut, _expOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 251:24] node _expOut_T_4 = not(UInt<12>(0h3ce)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 257:19] node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 256:18] node _expOut_T_6 = not(_expOut_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 256:14] node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 255:17] node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<12>(0h400), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 260:18] node _expOut_T_9 = not(_expOut_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 260:14] node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 259:17] node _expOut_T_11 = mux(notNaN_isInfOut, UInt<12>(0h200), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 264:18] node _expOut_T_12 = not(_expOut_T_11) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 264:14] node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 263:17] node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<12>(0h3ce), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 268:16] node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 267:18] node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<12>(0hbff), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 272:16] node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 271:15] node _expOut_T_18 = mux(notNaN_isInfOut, UInt<12>(0hc00), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 276:16] node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 275:15] node _expOut_T_20 = mux(isNaNOut, UInt<12>(0he00), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 277:16] node expOut = or(_expOut_T_19, _expOut_T_20) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 276:73] node _fractOut_T = or(isNaNOut, io.in.isZero) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:22] node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:38] node _fractOut_T_2 = mux(isNaNOut, UInt<52>(0h8000000000000), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 280:16] node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 279:12] node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<52>(0hfffffffffffff), UInt<52>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 283:13] node fractOut = or(_fractOut_T_3, _fractOut_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 282:11] node _io_out_T = cat(signOut, expOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:23] node _io_out_T_1 = cat(_io_out_T, fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:33] connect io.out, _io_out_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 285:12] node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:23] node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:41] node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:53] node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 287:66] connect io.exceptionFlags, _io_exceptionFlags_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 286:23] module RoundRawFNToRecFN_3 : @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 294:5] output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 297:16] inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_6 @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 308:15] connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 311:44] connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 312:44] connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 313:44] connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 314:44] connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 315:44] connect io.out, roundAnyRawFNToRecFN.io.out @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 316:23] connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags @[dependencies/hardfloat/hardfloat/src/main/scala/RoundAnyRawFNToRecFN.scala 317:23] module DivSqrtRecFN_small_1 : @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 466:5] input clock : Clock @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 466:5] input reset : Reset @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 466:5] output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 469:16] inst divSqrtRecFNToRaw of DivSqrtRecFNToRaw_small_1 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 490:15] connect divSqrtRecFNToRaw.clock, clock connect divSqrtRecFNToRaw.reset, reset connect io.inReady, divSqrtRecFNToRaw.io.inReady @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 492:16] connect divSqrtRecFNToRaw.io.inValid, io.inValid @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 493:39] connect divSqrtRecFNToRaw.io.sqrtOp, io.sqrtOp @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 494:39] connect divSqrtRecFNToRaw.io.a, io.a @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 495:39] connect divSqrtRecFNToRaw.io.b, io.b @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 496:39] connect divSqrtRecFNToRaw.io.roundingMode, io.roundingMode @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 497:39] connect io.outValid_div, divSqrtRecFNToRaw.io.rawOutValid_div @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 501:22] connect io.outValid_sqrt, divSqrtRecFNToRaw.io.rawOutValid_sqrt @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 502:22] inst roundRawFNToRecFN of RoundRawFNToRecFN_3 @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 505:15] connect roundRawFNToRecFN.io.invalidExc, divSqrtRecFNToRaw.io.invalidExc @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 506:39] connect roundRawFNToRecFN.io.infiniteExc, divSqrtRecFNToRaw.io.infiniteExc @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 507:39] connect roundRawFNToRecFN.io.in.sig, divSqrtRecFNToRaw.io.rawOut.sig @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 508:39] connect roundRawFNToRecFN.io.in.sExp, divSqrtRecFNToRaw.io.rawOut.sExp @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 508:39] connect roundRawFNToRecFN.io.in.sign, divSqrtRecFNToRaw.io.rawOut.sign @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 508:39] connect roundRawFNToRecFN.io.in.isZero, divSqrtRecFNToRaw.io.rawOut.isZero @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 508:39] connect roundRawFNToRecFN.io.in.isInf, divSqrtRecFNToRaw.io.rawOut.isInf @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 508:39] connect roundRawFNToRecFN.io.in.isNaN, divSqrtRecFNToRaw.io.rawOut.isNaN @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 508:39] connect roundRawFNToRecFN.io.roundingMode, divSqrtRecFNToRaw.io.roundingModeOut @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 509:39] connect roundRawFNToRecFN.io.detectTininess, io.detectTininess @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 510:41] connect io.out, roundRawFNToRecFN.io.out @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 511:23] connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags @[dependencies/hardfloat/hardfloat/src/main/scala/DivSqrtRecFN_small.scala 512:23] module FPU : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 735:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 735:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 735:7] output io : { flip hartid : UInt<1>, flip time : UInt<64>, flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, flip v_sew : UInt<3>, store_data : UInt<64>, toint_data : UInt<64>, flip ll_resp_val : UInt<1>, flip ll_resp_type : UInt<3>, flip ll_resp_tag : UInt<5>, flip ll_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip keep_clock_enabled : UInt<1>, flip cp_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 736:14] reg clock_en_reg : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 744:25] node clock_en = or(clock_en_reg, io.cp_req.valid) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 745:31] inst fp_decoder of FPUDecoder @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 750:26] connect fp_decoder.clock, clock connect fp_decoder.reset, reset connect fp_decoder.io.inst, io.inst @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 751:22] wire id_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 752:25] connect id_ctrl, fp_decoder.io.sigs @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 752:25] regreset ex_reg_valid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 768:29] connect ex_reg_valid, io.valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 768:29] reg ex_reg_inst : UInt<32>, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 769:30] when io.valid : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 769:30] connect ex_reg_inst, io.inst @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 769:30] reg ex_reg_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 770:30] when io.valid : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 770:30] connect ex_reg_ctrl, id_ctrl @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 770:30] reg ex_ra_0 : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 771:31] reg ex_ra_1 : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 771:31] reg ex_ra_2 : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 771:31] reg load_wb : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 774:24] connect load_wb, io.ll_resp_val @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 774:24] node _load_wb_typeTag_T = bits(io.ll_resp_type, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 775:50] node _load_wb_typeTag_T_1 = sub(_load_wb_typeTag_T, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 775:56] node _load_wb_typeTag_T_2 = tail(_load_wb_typeTag_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 775:56] reg load_wb_typeTag : UInt<2>, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 775:34] when io.ll_resp_val : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 775:34] connect load_wb_typeTag, _load_wb_typeTag_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 775:34] reg load_wb_data : UInt<64>, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 776:31] when io.ll_resp_val : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 776:31] connect load_wb_data, io.ll_resp_data @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 776:31] reg load_wb_tag : UInt<5>, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 777:30] when io.ll_resp_val : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 777:30] connect load_wb_tag, io.ll_resp_tag @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 777:30] node req_valid = or(ex_reg_valid, io.cp_req.valid) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 781:32] node ex_cp_valid = and(io.cp_req.ready, io.cp_req.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] regreset mem_cp_valid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 783:29] connect mem_cp_valid, ex_cp_valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 783:29] regreset wb_cp_valid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 784:28] connect wb_cp_valid, mem_cp_valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 784:28] regreset mem_reg_valid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 785:30] node _killm_T = or(io.killm, io.nack_mem) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 786:25] node _killm_T_1 = eq(mem_cp_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 786:44] node killm = and(_killm_T, _killm_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 786:41] node _killx_T = and(mem_reg_valid, killm) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 790:41] node killx = or(io.killx, _killx_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 790:24] node _mem_reg_valid_T = eq(killx, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 791:36] node _mem_reg_valid_T_1 = and(ex_reg_valid, _mem_reg_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 791:33] node _mem_reg_valid_T_2 = or(_mem_reg_valid_T_1, ex_cp_valid) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 791:43] connect mem_reg_valid, _mem_reg_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 791:17] reg mem_reg_inst : UInt<32>, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 792:31] when ex_reg_valid : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 792:31] connect mem_reg_inst, ex_reg_inst @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 792:31] node _wb_reg_valid_T = eq(killm, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 793:48] node _wb_reg_valid_T_1 = or(_wb_reg_valid_T, mem_cp_valid) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 793:55] node _wb_reg_valid_T_2 = and(mem_reg_valid, _wb_reg_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 793:44] regreset wb_reg_valid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 793:29] connect wb_reg_valid, _wb_reg_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 793:29] wire cp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 795:21] connect cp_ctrl.vec, io.cp_req.bits.vec @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 796:11] connect cp_ctrl.wflags, io.cp_req.bits.wflags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 796:11] connect cp_ctrl.sqrt, io.cp_req.bits.sqrt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 796:11] connect cp_ctrl.div, io.cp_req.bits.div @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 796:11] connect cp_ctrl.fma, io.cp_req.bits.fma @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 796:11] connect cp_ctrl.fastpipe, io.cp_req.bits.fastpipe @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 796:11] connect cp_ctrl.toint, io.cp_req.bits.toint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 796:11] connect cp_ctrl.fromint, io.cp_req.bits.fromint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 796:11] connect cp_ctrl.typeTagOut, io.cp_req.bits.typeTagOut @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 796:11] connect cp_ctrl.typeTagIn, io.cp_req.bits.typeTagIn @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 796:11] connect cp_ctrl.swap23, io.cp_req.bits.swap23 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 796:11] connect cp_ctrl.swap12, io.cp_req.bits.swap12 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 796:11] connect cp_ctrl.ren3, io.cp_req.bits.ren3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 796:11] connect cp_ctrl.ren2, io.cp_req.bits.ren2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 796:11] connect cp_ctrl.ren1, io.cp_req.bits.ren1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 796:11] connect cp_ctrl.wen, io.cp_req.bits.wen @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 796:11] connect cp_ctrl.ldst, io.cp_req.bits.ldst @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 796:11] connect io.cp_resp.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 797:20] connect io.cp_resp.bits.data, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 798:24] invalidate io.cp_resp.bits.exc @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 799:23] node ex_ctrl = mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 801:20] reg mem_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 802:27] when req_valid : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 802:27] connect mem_ctrl, ex_ctrl @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 802:27] reg wb_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 803:26] when mem_reg_valid : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 803:26] connect wb_ctrl, mem_ctrl @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 803:26] wire frfWriteBundle_0 : { clock : Clock, reset : UInt<1>, excpt : UInt<1>, priv_mode : UInt<3>, hartid : UInt<64>, timer : UInt<32>, valid : UInt<1>, pc : UInt<64>, wrdst : UInt<5>, wrdata : UInt<64>, wrenx : UInt<1>, wrenf : UInt<1>, rd0src : UInt<5>, rd0val : UInt<64>, rd1src : UInt<5>, rd1val : UInt<64>, inst : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_0.inst @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_0.rd1val @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_0.rd1src @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_0.rd0val @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_0.rd0src @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_0.wrenf @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_0.wrenx @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_0.wrdata @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_0.wrdst @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_0.pc @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_0.valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_0.timer @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_0.hartid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_0.priv_mode @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_0.excpt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_0.reset @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_0.clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] wire frfWriteBundle_1 : { clock : Clock, reset : UInt<1>, excpt : UInt<1>, priv_mode : UInt<3>, hartid : UInt<64>, timer : UInt<32>, valid : UInt<1>, pc : UInt<64>, wrdst : UInt<5>, wrdata : UInt<64>, wrenx : UInt<1>, wrenf : UInt<1>, rd0src : UInt<5>, rd0val : UInt<64>, rd1src : UInt<5>, rd1val : UInt<64>, inst : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_1.inst @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_1.rd1val @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_1.rd1src @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_1.rd0val @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_1.rd0src @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_1.wrenf @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_1.wrenx @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_1.wrdata @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_1.wrdst @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_1.pc @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_1.valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_1.timer @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_1.hartid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_1.priv_mode @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_1.excpt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_1.reset @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] invalidate frfWriteBundle_1.clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 806:44] connect frfWriteBundle_0.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 808:13] connect frfWriteBundle_0.reset, reset @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 809:13] connect frfWriteBundle_0.hartid, io.hartid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 810:14] node _frfWriteBundle_0_timer_T = bits(io.time, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 811:23] connect frfWriteBundle_0.timer, _frfWriteBundle_0_timer_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 811:13] connect frfWriteBundle_0.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 812:13] connect frfWriteBundle_0.wrenx, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 813:13] connect frfWriteBundle_0.wrenf, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 814:13] connect frfWriteBundle_0.excpt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 815:13] connect frfWriteBundle_1.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 808:13] connect frfWriteBundle_1.reset, reset @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 809:13] connect frfWriteBundle_1.hartid, io.hartid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 810:14] node _frfWriteBundle_1_timer_T = bits(io.time, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 811:23] connect frfWriteBundle_1.timer, _frfWriteBundle_1_timer_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 811:13] connect frfWriteBundle_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 812:13] connect frfWriteBundle_1.wrenx, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 813:13] connect frfWriteBundle_1.wrenf, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 814:13] connect frfWriteBundle_1.excpt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 815:13] cmem regfile : UInt<65> [32] @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 819:20] when load_wb : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 820:18] node _wdata_truncIdx_T = or(load_wb_typeTag, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:21] node wdata_truncIdx = bits(_wdata_truncIdx_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:47] node _wdata_T = eq(wdata_truncIdx, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _wdata_T_1 = mux(_wdata_T, UInt<1>(0h0), UInt<64>(0hffffffff00000000)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _wdata_T_2 = or(_wdata_T_1, load_wb_data) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 431:23] node wdata_rawIn_sign = bits(_wdata_T_2, 63, 63) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 44:18] node wdata_rawIn_expIn = bits(_wdata_T_2, 62, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 45:19] node wdata_rawIn_fractIn = bits(_wdata_T_2, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 46:21] node wdata_rawIn_isZeroExpIn = eq(wdata_rawIn_expIn, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 48:30] node wdata_rawIn_isZeroFractIn = eq(wdata_rawIn_fractIn, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 49:34] node _wdata_rawIn_normDist_T = bits(wdata_rawIn_fractIn, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_1 = bits(wdata_rawIn_fractIn, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_2 = bits(wdata_rawIn_fractIn, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_3 = bits(wdata_rawIn_fractIn, 3, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_4 = bits(wdata_rawIn_fractIn, 4, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_5 = bits(wdata_rawIn_fractIn, 5, 5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_6 = bits(wdata_rawIn_fractIn, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_7 = bits(wdata_rawIn_fractIn, 7, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_8 = bits(wdata_rawIn_fractIn, 8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_9 = bits(wdata_rawIn_fractIn, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_10 = bits(wdata_rawIn_fractIn, 10, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_11 = bits(wdata_rawIn_fractIn, 11, 11) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_12 = bits(wdata_rawIn_fractIn, 12, 12) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_13 = bits(wdata_rawIn_fractIn, 13, 13) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_14 = bits(wdata_rawIn_fractIn, 14, 14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_15 = bits(wdata_rawIn_fractIn, 15, 15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_16 = bits(wdata_rawIn_fractIn, 16, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_17 = bits(wdata_rawIn_fractIn, 17, 17) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_18 = bits(wdata_rawIn_fractIn, 18, 18) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_19 = bits(wdata_rawIn_fractIn, 19, 19) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_20 = bits(wdata_rawIn_fractIn, 20, 20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_21 = bits(wdata_rawIn_fractIn, 21, 21) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_22 = bits(wdata_rawIn_fractIn, 22, 22) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_23 = bits(wdata_rawIn_fractIn, 23, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_24 = bits(wdata_rawIn_fractIn, 24, 24) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_25 = bits(wdata_rawIn_fractIn, 25, 25) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_26 = bits(wdata_rawIn_fractIn, 26, 26) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_27 = bits(wdata_rawIn_fractIn, 27, 27) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_28 = bits(wdata_rawIn_fractIn, 28, 28) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_29 = bits(wdata_rawIn_fractIn, 29, 29) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_30 = bits(wdata_rawIn_fractIn, 30, 30) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_31 = bits(wdata_rawIn_fractIn, 31, 31) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_32 = bits(wdata_rawIn_fractIn, 32, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_33 = bits(wdata_rawIn_fractIn, 33, 33) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_34 = bits(wdata_rawIn_fractIn, 34, 34) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_35 = bits(wdata_rawIn_fractIn, 35, 35) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_36 = bits(wdata_rawIn_fractIn, 36, 36) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_37 = bits(wdata_rawIn_fractIn, 37, 37) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_38 = bits(wdata_rawIn_fractIn, 38, 38) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_39 = bits(wdata_rawIn_fractIn, 39, 39) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_40 = bits(wdata_rawIn_fractIn, 40, 40) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_41 = bits(wdata_rawIn_fractIn, 41, 41) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_42 = bits(wdata_rawIn_fractIn, 42, 42) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_43 = bits(wdata_rawIn_fractIn, 43, 43) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_44 = bits(wdata_rawIn_fractIn, 44, 44) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_45 = bits(wdata_rawIn_fractIn, 45, 45) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_46 = bits(wdata_rawIn_fractIn, 46, 46) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_47 = bits(wdata_rawIn_fractIn, 47, 47) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_48 = bits(wdata_rawIn_fractIn, 48, 48) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_49 = bits(wdata_rawIn_fractIn, 49, 49) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_50 = bits(wdata_rawIn_fractIn, 50, 50) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_51 = bits(wdata_rawIn_fractIn, 51, 51) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_52 = mux(_wdata_rawIn_normDist_T_1, UInt<6>(0h32), UInt<6>(0h33)) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_53 = mux(_wdata_rawIn_normDist_T_2, UInt<6>(0h31), _wdata_rawIn_normDist_T_52) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_54 = mux(_wdata_rawIn_normDist_T_3, UInt<6>(0h30), _wdata_rawIn_normDist_T_53) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_55 = mux(_wdata_rawIn_normDist_T_4, UInt<6>(0h2f), _wdata_rawIn_normDist_T_54) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_56 = mux(_wdata_rawIn_normDist_T_5, UInt<6>(0h2e), _wdata_rawIn_normDist_T_55) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_57 = mux(_wdata_rawIn_normDist_T_6, UInt<6>(0h2d), _wdata_rawIn_normDist_T_56) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_58 = mux(_wdata_rawIn_normDist_T_7, UInt<6>(0h2c), _wdata_rawIn_normDist_T_57) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_59 = mux(_wdata_rawIn_normDist_T_8, UInt<6>(0h2b), _wdata_rawIn_normDist_T_58) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_60 = mux(_wdata_rawIn_normDist_T_9, UInt<6>(0h2a), _wdata_rawIn_normDist_T_59) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_61 = mux(_wdata_rawIn_normDist_T_10, UInt<6>(0h29), _wdata_rawIn_normDist_T_60) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_62 = mux(_wdata_rawIn_normDist_T_11, UInt<6>(0h28), _wdata_rawIn_normDist_T_61) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_63 = mux(_wdata_rawIn_normDist_T_12, UInt<6>(0h27), _wdata_rawIn_normDist_T_62) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_64 = mux(_wdata_rawIn_normDist_T_13, UInt<6>(0h26), _wdata_rawIn_normDist_T_63) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_65 = mux(_wdata_rawIn_normDist_T_14, UInt<6>(0h25), _wdata_rawIn_normDist_T_64) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_66 = mux(_wdata_rawIn_normDist_T_15, UInt<6>(0h24), _wdata_rawIn_normDist_T_65) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_67 = mux(_wdata_rawIn_normDist_T_16, UInt<6>(0h23), _wdata_rawIn_normDist_T_66) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_68 = mux(_wdata_rawIn_normDist_T_17, UInt<6>(0h22), _wdata_rawIn_normDist_T_67) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_69 = mux(_wdata_rawIn_normDist_T_18, UInt<6>(0h21), _wdata_rawIn_normDist_T_68) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_70 = mux(_wdata_rawIn_normDist_T_19, UInt<6>(0h20), _wdata_rawIn_normDist_T_69) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_71 = mux(_wdata_rawIn_normDist_T_20, UInt<5>(0h1f), _wdata_rawIn_normDist_T_70) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_72 = mux(_wdata_rawIn_normDist_T_21, UInt<5>(0h1e), _wdata_rawIn_normDist_T_71) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_73 = mux(_wdata_rawIn_normDist_T_22, UInt<5>(0h1d), _wdata_rawIn_normDist_T_72) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_74 = mux(_wdata_rawIn_normDist_T_23, UInt<5>(0h1c), _wdata_rawIn_normDist_T_73) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_75 = mux(_wdata_rawIn_normDist_T_24, UInt<5>(0h1b), _wdata_rawIn_normDist_T_74) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_76 = mux(_wdata_rawIn_normDist_T_25, UInt<5>(0h1a), _wdata_rawIn_normDist_T_75) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_77 = mux(_wdata_rawIn_normDist_T_26, UInt<5>(0h19), _wdata_rawIn_normDist_T_76) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_78 = mux(_wdata_rawIn_normDist_T_27, UInt<5>(0h18), _wdata_rawIn_normDist_T_77) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_79 = mux(_wdata_rawIn_normDist_T_28, UInt<5>(0h17), _wdata_rawIn_normDist_T_78) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_80 = mux(_wdata_rawIn_normDist_T_29, UInt<5>(0h16), _wdata_rawIn_normDist_T_79) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_81 = mux(_wdata_rawIn_normDist_T_30, UInt<5>(0h15), _wdata_rawIn_normDist_T_80) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_82 = mux(_wdata_rawIn_normDist_T_31, UInt<5>(0h14), _wdata_rawIn_normDist_T_81) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_83 = mux(_wdata_rawIn_normDist_T_32, UInt<5>(0h13), _wdata_rawIn_normDist_T_82) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_84 = mux(_wdata_rawIn_normDist_T_33, UInt<5>(0h12), _wdata_rawIn_normDist_T_83) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_85 = mux(_wdata_rawIn_normDist_T_34, UInt<5>(0h11), _wdata_rawIn_normDist_T_84) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_86 = mux(_wdata_rawIn_normDist_T_35, UInt<5>(0h10), _wdata_rawIn_normDist_T_85) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_87 = mux(_wdata_rawIn_normDist_T_36, UInt<4>(0hf), _wdata_rawIn_normDist_T_86) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_88 = mux(_wdata_rawIn_normDist_T_37, UInt<4>(0he), _wdata_rawIn_normDist_T_87) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_89 = mux(_wdata_rawIn_normDist_T_38, UInt<4>(0hd), _wdata_rawIn_normDist_T_88) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_90 = mux(_wdata_rawIn_normDist_T_39, UInt<4>(0hc), _wdata_rawIn_normDist_T_89) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_91 = mux(_wdata_rawIn_normDist_T_40, UInt<4>(0hb), _wdata_rawIn_normDist_T_90) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_92 = mux(_wdata_rawIn_normDist_T_41, UInt<4>(0ha), _wdata_rawIn_normDist_T_91) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_93 = mux(_wdata_rawIn_normDist_T_42, UInt<4>(0h9), _wdata_rawIn_normDist_T_92) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_94 = mux(_wdata_rawIn_normDist_T_43, UInt<4>(0h8), _wdata_rawIn_normDist_T_93) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_95 = mux(_wdata_rawIn_normDist_T_44, UInt<3>(0h7), _wdata_rawIn_normDist_T_94) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_96 = mux(_wdata_rawIn_normDist_T_45, UInt<3>(0h6), _wdata_rawIn_normDist_T_95) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_97 = mux(_wdata_rawIn_normDist_T_46, UInt<3>(0h5), _wdata_rawIn_normDist_T_96) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_98 = mux(_wdata_rawIn_normDist_T_47, UInt<3>(0h4), _wdata_rawIn_normDist_T_97) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_99 = mux(_wdata_rawIn_normDist_T_48, UInt<2>(0h3), _wdata_rawIn_normDist_T_98) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_100 = mux(_wdata_rawIn_normDist_T_49, UInt<2>(0h2), _wdata_rawIn_normDist_T_99) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_101 = mux(_wdata_rawIn_normDist_T_50, UInt<1>(0h1), _wdata_rawIn_normDist_T_100) @[src/main/scala/chisel3/util/Mux.scala 50:70] node wdata_rawIn_normDist = mux(_wdata_rawIn_normDist_T_51, UInt<1>(0h0), _wdata_rawIn_normDist_T_101) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_subnormFract_T = dshl(wdata_rawIn_fractIn, wdata_rawIn_normDist) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 52:33] node _wdata_rawIn_subnormFract_T_1 = bits(_wdata_rawIn_subnormFract_T, 50, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 52:46] node wdata_rawIn_subnormFract = shl(_wdata_rawIn_subnormFract_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 52:64] node _wdata_rawIn_adjustedExp_T = xor(wdata_rawIn_normDist, UInt<12>(0hfff)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 55:18] node _wdata_rawIn_adjustedExp_T_1 = mux(wdata_rawIn_isZeroExpIn, _wdata_rawIn_adjustedExp_T, wdata_rawIn_expIn) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 54:10] node _wdata_rawIn_adjustedExp_T_2 = mux(wdata_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 58:14] node _wdata_rawIn_adjustedExp_T_3 = or(UInt<11>(0h400), _wdata_rawIn_adjustedExp_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 58:9] node _wdata_rawIn_adjustedExp_T_4 = add(_wdata_rawIn_adjustedExp_T_1, _wdata_rawIn_adjustedExp_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 57:9] node wdata_rawIn_adjustedExp = tail(_wdata_rawIn_adjustedExp_T_4, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 57:9] node wdata_rawIn_isZero = and(wdata_rawIn_isZeroExpIn, wdata_rawIn_isZeroFractIn) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 60:30] node _wdata_rawIn_isSpecial_T = bits(wdata_rawIn_adjustedExp, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 61:32] node wdata_rawIn_isSpecial = eq(_wdata_rawIn_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 61:57] wire wdata_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 63:19] node _wdata_rawIn_out_isNaN_T = eq(wdata_rawIn_isZeroFractIn, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 64:31] node _wdata_rawIn_out_isNaN_T_1 = and(wdata_rawIn_isSpecial, _wdata_rawIn_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 64:28] connect wdata_rawIn.isNaN, _wdata_rawIn_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 64:15] node _wdata_rawIn_out_isInf_T = and(wdata_rawIn_isSpecial, wdata_rawIn_isZeroFractIn) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 65:28] connect wdata_rawIn.isInf, _wdata_rawIn_out_isInf_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 65:15] connect wdata_rawIn.isZero, wdata_rawIn_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 66:16] connect wdata_rawIn.sign, wdata_rawIn_sign @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 67:14] node _wdata_rawIn_out_sExp_T = bits(wdata_rawIn_adjustedExp, 11, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 68:28] node _wdata_rawIn_out_sExp_T_1 = cvt(_wdata_rawIn_out_sExp_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 68:42] connect wdata_rawIn.sExp, _wdata_rawIn_out_sExp_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 68:14] node _wdata_rawIn_out_sig_T = eq(wdata_rawIn_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 70:19] node _wdata_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _wdata_rawIn_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 70:16] node _wdata_rawIn_out_sig_T_2 = mux(wdata_rawIn_isZeroExpIn, wdata_rawIn_subnormFract, wdata_rawIn_fractIn) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 70:33] node _wdata_rawIn_out_sig_T_3 = cat(_wdata_rawIn_out_sig_T_1, _wdata_rawIn_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 70:27] connect wdata_rawIn.sig, _wdata_rawIn_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 69:13] node _wdata_T_3 = bits(wdata_rawIn.sExp, 11, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 48:50] node _wdata_T_4 = mux(wdata_rawIn.isZero, UInt<3>(0h0), _wdata_T_3) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 48:15] node _wdata_T_5 = mux(wdata_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 49:20] node _wdata_T_6 = or(_wdata_T_4, _wdata_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 48:76] node _wdata_T_7 = cat(wdata_rawIn.sign, _wdata_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 47:20] node _wdata_T_8 = bits(wdata_rawIn.sExp, 8, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 50:23] node _wdata_T_9 = cat(_wdata_T_7, _wdata_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 49:45] node _wdata_T_10 = bits(wdata_rawIn.sig, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 51:22] node _wdata_T_11 = cat(_wdata_T_9, _wdata_T_10) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 50:41] node wdata_rawIn_sign_1 = bits(_wdata_T_2, 31, 31) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 44:18] node wdata_rawIn_expIn_1 = bits(_wdata_T_2, 30, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 45:19] node wdata_rawIn_fractIn_1 = bits(_wdata_T_2, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 46:21] node wdata_rawIn_isZeroExpIn_1 = eq(wdata_rawIn_expIn_1, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 48:30] node wdata_rawIn_isZeroFractIn_1 = eq(wdata_rawIn_fractIn_1, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 49:34] node _wdata_rawIn_normDist_T_102 = bits(wdata_rawIn_fractIn_1, 0, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_103 = bits(wdata_rawIn_fractIn_1, 1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_104 = bits(wdata_rawIn_fractIn_1, 2, 2) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_105 = bits(wdata_rawIn_fractIn_1, 3, 3) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_106 = bits(wdata_rawIn_fractIn_1, 4, 4) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_107 = bits(wdata_rawIn_fractIn_1, 5, 5) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_108 = bits(wdata_rawIn_fractIn_1, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_109 = bits(wdata_rawIn_fractIn_1, 7, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_110 = bits(wdata_rawIn_fractIn_1, 8, 8) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_111 = bits(wdata_rawIn_fractIn_1, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_112 = bits(wdata_rawIn_fractIn_1, 10, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_113 = bits(wdata_rawIn_fractIn_1, 11, 11) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_114 = bits(wdata_rawIn_fractIn_1, 12, 12) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_115 = bits(wdata_rawIn_fractIn_1, 13, 13) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_116 = bits(wdata_rawIn_fractIn_1, 14, 14) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_117 = bits(wdata_rawIn_fractIn_1, 15, 15) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_118 = bits(wdata_rawIn_fractIn_1, 16, 16) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_119 = bits(wdata_rawIn_fractIn_1, 17, 17) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_120 = bits(wdata_rawIn_fractIn_1, 18, 18) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_121 = bits(wdata_rawIn_fractIn_1, 19, 19) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_122 = bits(wdata_rawIn_fractIn_1, 20, 20) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_123 = bits(wdata_rawIn_fractIn_1, 21, 21) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_124 = bits(wdata_rawIn_fractIn_1, 22, 22) @[dependencies/hardfloat/hardfloat/src/main/scala/primitives.scala 91:52] node _wdata_rawIn_normDist_T_125 = mux(_wdata_rawIn_normDist_T_103, UInt<5>(0h15), UInt<5>(0h16)) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_126 = mux(_wdata_rawIn_normDist_T_104, UInt<5>(0h14), _wdata_rawIn_normDist_T_125) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_127 = mux(_wdata_rawIn_normDist_T_105, UInt<5>(0h13), _wdata_rawIn_normDist_T_126) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_128 = mux(_wdata_rawIn_normDist_T_106, UInt<5>(0h12), _wdata_rawIn_normDist_T_127) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_129 = mux(_wdata_rawIn_normDist_T_107, UInt<5>(0h11), _wdata_rawIn_normDist_T_128) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_130 = mux(_wdata_rawIn_normDist_T_108, UInt<5>(0h10), _wdata_rawIn_normDist_T_129) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_131 = mux(_wdata_rawIn_normDist_T_109, UInt<4>(0hf), _wdata_rawIn_normDist_T_130) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_132 = mux(_wdata_rawIn_normDist_T_110, UInt<4>(0he), _wdata_rawIn_normDist_T_131) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_133 = mux(_wdata_rawIn_normDist_T_111, UInt<4>(0hd), _wdata_rawIn_normDist_T_132) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_134 = mux(_wdata_rawIn_normDist_T_112, UInt<4>(0hc), _wdata_rawIn_normDist_T_133) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_135 = mux(_wdata_rawIn_normDist_T_113, UInt<4>(0hb), _wdata_rawIn_normDist_T_134) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_136 = mux(_wdata_rawIn_normDist_T_114, UInt<4>(0ha), _wdata_rawIn_normDist_T_135) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_137 = mux(_wdata_rawIn_normDist_T_115, UInt<4>(0h9), _wdata_rawIn_normDist_T_136) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_138 = mux(_wdata_rawIn_normDist_T_116, UInt<4>(0h8), _wdata_rawIn_normDist_T_137) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_139 = mux(_wdata_rawIn_normDist_T_117, UInt<3>(0h7), _wdata_rawIn_normDist_T_138) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_140 = mux(_wdata_rawIn_normDist_T_118, UInt<3>(0h6), _wdata_rawIn_normDist_T_139) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_141 = mux(_wdata_rawIn_normDist_T_119, UInt<3>(0h5), _wdata_rawIn_normDist_T_140) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_142 = mux(_wdata_rawIn_normDist_T_120, UInt<3>(0h4), _wdata_rawIn_normDist_T_141) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_143 = mux(_wdata_rawIn_normDist_T_121, UInt<2>(0h3), _wdata_rawIn_normDist_T_142) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_144 = mux(_wdata_rawIn_normDist_T_122, UInt<2>(0h2), _wdata_rawIn_normDist_T_143) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_normDist_T_145 = mux(_wdata_rawIn_normDist_T_123, UInt<1>(0h1), _wdata_rawIn_normDist_T_144) @[src/main/scala/chisel3/util/Mux.scala 50:70] node wdata_rawIn_normDist_1 = mux(_wdata_rawIn_normDist_T_124, UInt<1>(0h0), _wdata_rawIn_normDist_T_145) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _wdata_rawIn_subnormFract_T_2 = dshl(wdata_rawIn_fractIn_1, wdata_rawIn_normDist_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 52:33] node _wdata_rawIn_subnormFract_T_3 = bits(_wdata_rawIn_subnormFract_T_2, 21, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 52:46] node wdata_rawIn_subnormFract_1 = shl(_wdata_rawIn_subnormFract_T_3, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 52:64] node _wdata_rawIn_adjustedExp_T_5 = xor(wdata_rawIn_normDist_1, UInt<9>(0h1ff)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 55:18] node _wdata_rawIn_adjustedExp_T_6 = mux(wdata_rawIn_isZeroExpIn_1, _wdata_rawIn_adjustedExp_T_5, wdata_rawIn_expIn_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 54:10] node _wdata_rawIn_adjustedExp_T_7 = mux(wdata_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 58:14] node _wdata_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _wdata_rawIn_adjustedExp_T_7) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 58:9] node _wdata_rawIn_adjustedExp_T_9 = add(_wdata_rawIn_adjustedExp_T_6, _wdata_rawIn_adjustedExp_T_8) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 57:9] node wdata_rawIn_adjustedExp_1 = tail(_wdata_rawIn_adjustedExp_T_9, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 57:9] node wdata_rawIn_isZero_1 = and(wdata_rawIn_isZeroExpIn_1, wdata_rawIn_isZeroFractIn_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 60:30] node _wdata_rawIn_isSpecial_T_1 = bits(wdata_rawIn_adjustedExp_1, 8, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 61:32] node wdata_rawIn_isSpecial_1 = eq(_wdata_rawIn_isSpecial_T_1, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 61:57] wire wdata_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 63:19] node _wdata_rawIn_out_isNaN_T_2 = eq(wdata_rawIn_isZeroFractIn_1, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 64:31] node _wdata_rawIn_out_isNaN_T_3 = and(wdata_rawIn_isSpecial_1, _wdata_rawIn_out_isNaN_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 64:28] connect wdata_rawIn_1.isNaN, _wdata_rawIn_out_isNaN_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 64:15] node _wdata_rawIn_out_isInf_T_1 = and(wdata_rawIn_isSpecial_1, wdata_rawIn_isZeroFractIn_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 65:28] connect wdata_rawIn_1.isInf, _wdata_rawIn_out_isInf_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 65:15] connect wdata_rawIn_1.isZero, wdata_rawIn_isZero_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 66:16] connect wdata_rawIn_1.sign, wdata_rawIn_sign_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 67:14] node _wdata_rawIn_out_sExp_T_2 = bits(wdata_rawIn_adjustedExp_1, 8, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 68:28] node _wdata_rawIn_out_sExp_T_3 = cvt(_wdata_rawIn_out_sExp_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 68:42] connect wdata_rawIn_1.sExp, _wdata_rawIn_out_sExp_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 68:14] node _wdata_rawIn_out_sig_T_4 = eq(wdata_rawIn_isZero_1, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 70:19] node _wdata_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _wdata_rawIn_out_sig_T_4) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 70:16] node _wdata_rawIn_out_sig_T_6 = mux(wdata_rawIn_isZeroExpIn_1, wdata_rawIn_subnormFract_1, wdata_rawIn_fractIn_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 70:33] node _wdata_rawIn_out_sig_T_7 = cat(_wdata_rawIn_out_sig_T_5, _wdata_rawIn_out_sig_T_6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 70:27] connect wdata_rawIn_1.sig, _wdata_rawIn_out_sig_T_7 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromFN.scala 69:13] node _wdata_T_12 = bits(wdata_rawIn_1.sExp, 8, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 48:50] node _wdata_T_13 = mux(wdata_rawIn_1.isZero, UInt<3>(0h0), _wdata_T_12) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 48:15] node _wdata_T_14 = mux(wdata_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 49:20] node _wdata_T_15 = or(_wdata_T_13, _wdata_T_14) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 48:76] node _wdata_T_16 = cat(wdata_rawIn_1.sign, _wdata_T_15) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 47:20] node _wdata_T_17 = bits(wdata_rawIn_1.sExp, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 50:23] node _wdata_T_18 = cat(_wdata_T_16, _wdata_T_17) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 49:45] node _wdata_T_19 = bits(wdata_rawIn_1.sig, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 51:22] node _wdata_T_20 = cat(_wdata_T_18, _wdata_T_19) @[dependencies/hardfloat/hardfloat/src/main/scala/recFNFromFN.scala 50:41] node _wdata_swizzledNaN_T = bits(_wdata_T_11, 64, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 337:8] node _wdata_swizzledNaN_T_1 = bits(_wdata_T_11, 51, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 338:8] node _wdata_swizzledNaN_T_2 = andr(_wdata_swizzledNaN_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 338:42] node _wdata_swizzledNaN_T_3 = bits(_wdata_T_11, 59, 53) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 339:8] node _wdata_swizzledNaN_T_4 = bits(_wdata_T_20, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 340:8] node _wdata_swizzledNaN_T_5 = bits(_wdata_T_11, 51, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 341:8] node _wdata_swizzledNaN_T_6 = bits(_wdata_T_20, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 342:8] node _wdata_swizzledNaN_T_7 = bits(_wdata_T_20, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 343:8] node wdata_swizzledNaN_lo_hi = cat(_wdata_swizzledNaN_T_5, _wdata_swizzledNaN_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 336:26] node wdata_swizzledNaN_lo = cat(wdata_swizzledNaN_lo_hi, _wdata_swizzledNaN_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 336:26] node wdata_swizzledNaN_hi_lo = cat(_wdata_swizzledNaN_T_3, _wdata_swizzledNaN_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 336:26] node wdata_swizzledNaN_hi_hi = cat(_wdata_swizzledNaN_T, _wdata_swizzledNaN_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 336:26] node wdata_swizzledNaN_hi = cat(wdata_swizzledNaN_hi_hi, wdata_swizzledNaN_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 336:26] node wdata_swizzledNaN = cat(wdata_swizzledNaN_hi, wdata_swizzledNaN_lo) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 336:26] node _wdata_T_21 = bits(_wdata_T_11, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node _wdata_T_22 = andr(_wdata_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node wdata = mux(_wdata_T_22, wdata_swizzledNaN, _wdata_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 344:8] infer mport MPORT = regfile[load_wb_tag], clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 822:12] connect MPORT, wdata @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 822:26] node _unswizzled_T = bits(wdata, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 381:10] node _unswizzled_T_1 = bits(wdata, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 382:10] node _unswizzled_T_2 = bits(wdata, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 383:10] node unswizzled_hi = cat(_unswizzled_T, _unswizzled_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 380:27] node unswizzled = cat(unswizzled_hi, _unswizzled_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 380:27] node _prevOK_T = bits(wdata, 64, 60) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:49] node _prevOK_T_1 = andr(_prevOK_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:84] node _prevOK_T_2 = eq(_prevOK_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 384:20] node prevOK = or(_prevOK_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 384:33] node _curOK_T = bits(wdata, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node _curOK_T_1 = andr(_curOK_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node _curOK_T_2 = eq(_curOK_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 385:19] node _curOK_T_3 = bits(wdata, 60, 60) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 385:35] node _curOK_T_4 = bits(wdata, 51, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 385:60] node _curOK_T_5 = andr(_curOK_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 385:96] node _curOK_T_6 = eq(_curOK_T_3, _curOK_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 385:55] node curOK = or(_curOK_T_2, _curOK_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 385:31] node _T = and(prevOK, curOK) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 386:14] node _T_1 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 823:11] node _T_2 = eq(_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 823:11] when _T_2 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 823:11] node _T_3 = eq(_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 823:11] when _T_3 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 823:11] printf(clock, UInt<1>(0h1), "Assertion failed\n at FPU.scala:823 assert(consistent(wdata))\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 823:11] assert(clock, _T, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 823:11] connect frfWriteBundle_0.wrdst, load_wb_tag @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 828:29] connect frfWriteBundle_0.wrenf, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 829:29] node frfWriteBundle_0_wrdata_unrecoded_rawIn_exp = bits(wdata, 63, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn_exp, 11, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero = eq(_frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn_exp, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial = eq(_frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire frfWriteBundle_0_wrdata_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T_1 = and(frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect frfWriteBundle_0_wrdata_unrecoded_rawIn.isNaN, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_1 = eq(_frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_2 = and(frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect frfWriteBundle_0_wrdata_unrecoded_rawIn.isInf, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect frfWriteBundle_0_wrdata_unrecoded_rawIn.isZero, frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sign_T = bits(wdata, 64, 64) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect frfWriteBundle_0_wrdata_unrecoded_rawIn.sign, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sExp_T = cvt(frfWriteBundle_0_wrdata_unrecoded_rawIn_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect frfWriteBundle_0_wrdata_unrecoded_rawIn.sExp, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T = eq(frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_2 = bits(wdata, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_3 = cat(_frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect frfWriteBundle_0_wrdata_unrecoded_rawIn.sig, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node frfWriteBundle_0_wrdata_unrecoded_isSubnormal = lt(frfWriteBundle_0_wrdata_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 51:38] node _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn.sExp, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:47] node _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node frfWriteBundle_0_wrdata_unrecoded_denormShiftDist = tail(_frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node _frfWriteBundle_0_wrdata_unrecoded_denormFract_T = shr(frfWriteBundle_0_wrdata_unrecoded_rawIn.sig, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:38] node _frfWriteBundle_0_wrdata_unrecoded_denormFract_T_1 = dshr(_frfWriteBundle_0_wrdata_unrecoded_denormFract_T, frfWriteBundle_0_wrdata_unrecoded_denormShiftDist) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:42] node frfWriteBundle_0_wrdata_unrecoded_denormFract = bits(_frfWriteBundle_0_wrdata_unrecoded_denormFract_T_1, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:60] node _frfWriteBundle_0_wrdata_unrecoded_expOut_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn.sExp, 10, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:27] node _frfWriteBundle_0_wrdata_unrecoded_expOut_T_1 = sub(_frfWriteBundle_0_wrdata_unrecoded_expOut_T, UInt<11>(0h401)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _frfWriteBundle_0_wrdata_unrecoded_expOut_T_2 = tail(_frfWriteBundle_0_wrdata_unrecoded_expOut_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _frfWriteBundle_0_wrdata_unrecoded_expOut_T_3 = mux(frfWriteBundle_0_wrdata_unrecoded_isSubnormal, UInt<1>(0h0), _frfWriteBundle_0_wrdata_unrecoded_expOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 56:16] node _frfWriteBundle_0_wrdata_unrecoded_expOut_T_4 = or(frfWriteBundle_0_wrdata_unrecoded_rawIn.isNaN, frfWriteBundle_0_wrdata_unrecoded_rawIn.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:44] node _frfWriteBundle_0_wrdata_unrecoded_expOut_T_5 = mux(_frfWriteBundle_0_wrdata_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:21] node frfWriteBundle_0_wrdata_unrecoded_expOut = or(_frfWriteBundle_0_wrdata_unrecoded_expOut_T_3, _frfWriteBundle_0_wrdata_unrecoded_expOut_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:15] node _frfWriteBundle_0_wrdata_unrecoded_fractOut_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn.sig, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:48] node _frfWriteBundle_0_wrdata_unrecoded_fractOut_T_1 = mux(frfWriteBundle_0_wrdata_unrecoded_rawIn.isInf, UInt<1>(0h0), _frfWriteBundle_0_wrdata_unrecoded_fractOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:20] node frfWriteBundle_0_wrdata_unrecoded_fractOut = mux(frfWriteBundle_0_wrdata_unrecoded_isSubnormal, frfWriteBundle_0_wrdata_unrecoded_denormFract, _frfWriteBundle_0_wrdata_unrecoded_fractOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 62:16] node frfWriteBundle_0_wrdata_unrecoded_hi = cat(frfWriteBundle_0_wrdata_unrecoded_rawIn.sign, frfWriteBundle_0_wrdata_unrecoded_expOut) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node frfWriteBundle_0_wrdata_unrecoded = cat(frfWriteBundle_0_wrdata_unrecoded_hi, frfWriteBundle_0_wrdata_unrecoded_fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node _frfWriteBundle_0_wrdata_prevRecoded_T = bits(wdata, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 442:10] node _frfWriteBundle_0_wrdata_prevRecoded_T_1 = bits(wdata, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 443:10] node _frfWriteBundle_0_wrdata_prevRecoded_T_2 = bits(wdata, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 444:10] node frfWriteBundle_0_wrdata_prevRecoded_hi = cat(_frfWriteBundle_0_wrdata_prevRecoded_T, _frfWriteBundle_0_wrdata_prevRecoded_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 441:28] node frfWriteBundle_0_wrdata_prevRecoded = cat(frfWriteBundle_0_wrdata_prevRecoded_hi, _frfWriteBundle_0_wrdata_prevRecoded_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 441:28] node frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_exp = bits(frfWriteBundle_0_wrdata_prevRecoded, 31, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_isZero_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_exp, 8, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_isZero = eq(_frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_isSpecial_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_exp, 8, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_isSpecial = eq(_frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire frfWriteBundle_0_wrdata_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_isNaN_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_exp, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_isNaN_T_1 = and(frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_isSpecial, _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect frfWriteBundle_0_wrdata_prevUnrecoded_rawIn.isNaN, _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_isInf_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_exp, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_isInf_T_2 = and(frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_isSpecial, _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect frfWriteBundle_0_wrdata_prevUnrecoded_rawIn.isInf, _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect frfWriteBundle_0_wrdata_prevUnrecoded_rawIn.isZero, frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_sign_T = bits(frfWriteBundle_0_wrdata_prevRecoded, 32, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect frfWriteBundle_0_wrdata_prevUnrecoded_rawIn.sign, _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_sExp_T = cvt(frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect frfWriteBundle_0_wrdata_prevUnrecoded_rawIn.sExp, _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_sig_T = eq(frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_sig_T_2 = bits(frfWriteBundle_0_wrdata_prevRecoded, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_sig_T_3 = cat(_frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect frfWriteBundle_0_wrdata_prevUnrecoded_rawIn.sig, _frfWriteBundle_0_wrdata_prevUnrecoded_rawIn_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node frfWriteBundle_0_wrdata_prevUnrecoded_isSubnormal = lt(frfWriteBundle_0_wrdata_prevUnrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 51:38] node _frfWriteBundle_0_wrdata_prevUnrecoded_denormShiftDist_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_rawIn.sExp, 4, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:47] node _frfWriteBundle_0_wrdata_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _frfWriteBundle_0_wrdata_prevUnrecoded_denormShiftDist_T) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node frfWriteBundle_0_wrdata_prevUnrecoded_denormShiftDist = tail(_frfWriteBundle_0_wrdata_prevUnrecoded_denormShiftDist_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node _frfWriteBundle_0_wrdata_prevUnrecoded_denormFract_T = shr(frfWriteBundle_0_wrdata_prevUnrecoded_rawIn.sig, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:38] node _frfWriteBundle_0_wrdata_prevUnrecoded_denormFract_T_1 = dshr(_frfWriteBundle_0_wrdata_prevUnrecoded_denormFract_T, frfWriteBundle_0_wrdata_prevUnrecoded_denormShiftDist) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:42] node frfWriteBundle_0_wrdata_prevUnrecoded_denormFract = bits(_frfWriteBundle_0_wrdata_prevUnrecoded_denormFract_T_1, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:60] node _frfWriteBundle_0_wrdata_prevUnrecoded_expOut_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_rawIn.sExp, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:27] node _frfWriteBundle_0_wrdata_prevUnrecoded_expOut_T_1 = sub(_frfWriteBundle_0_wrdata_prevUnrecoded_expOut_T, UInt<8>(0h81)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _frfWriteBundle_0_wrdata_prevUnrecoded_expOut_T_2 = tail(_frfWriteBundle_0_wrdata_prevUnrecoded_expOut_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _frfWriteBundle_0_wrdata_prevUnrecoded_expOut_T_3 = mux(frfWriteBundle_0_wrdata_prevUnrecoded_isSubnormal, UInt<1>(0h0), _frfWriteBundle_0_wrdata_prevUnrecoded_expOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 56:16] node _frfWriteBundle_0_wrdata_prevUnrecoded_expOut_T_4 = or(frfWriteBundle_0_wrdata_prevUnrecoded_rawIn.isNaN, frfWriteBundle_0_wrdata_prevUnrecoded_rawIn.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:44] node _frfWriteBundle_0_wrdata_prevUnrecoded_expOut_T_5 = mux(_frfWriteBundle_0_wrdata_prevUnrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:21] node frfWriteBundle_0_wrdata_prevUnrecoded_expOut = or(_frfWriteBundle_0_wrdata_prevUnrecoded_expOut_T_3, _frfWriteBundle_0_wrdata_prevUnrecoded_expOut_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:15] node _frfWriteBundle_0_wrdata_prevUnrecoded_fractOut_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_rawIn.sig, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:48] node _frfWriteBundle_0_wrdata_prevUnrecoded_fractOut_T_1 = mux(frfWriteBundle_0_wrdata_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _frfWriteBundle_0_wrdata_prevUnrecoded_fractOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:20] node frfWriteBundle_0_wrdata_prevUnrecoded_fractOut = mux(frfWriteBundle_0_wrdata_prevUnrecoded_isSubnormal, frfWriteBundle_0_wrdata_prevUnrecoded_denormFract, _frfWriteBundle_0_wrdata_prevUnrecoded_fractOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 62:16] node frfWriteBundle_0_wrdata_prevUnrecoded_hi = cat(frfWriteBundle_0_wrdata_prevUnrecoded_rawIn.sign, frfWriteBundle_0_wrdata_prevUnrecoded_expOut) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node frfWriteBundle_0_wrdata_prevUnrecoded = cat(frfWriteBundle_0_wrdata_prevUnrecoded_hi, frfWriteBundle_0_wrdata_prevUnrecoded_fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node _frfWriteBundle_0_wrdata_T = shr(frfWriteBundle_0_wrdata_unrecoded, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:21] node _frfWriteBundle_0_wrdata_T_1 = bits(wdata, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node _frfWriteBundle_0_wrdata_T_2 = andr(_frfWriteBundle_0_wrdata_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node _frfWriteBundle_0_wrdata_T_3 = bits(frfWriteBundle_0_wrdata_unrecoded, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:81] node _frfWriteBundle_0_wrdata_T_4 = mux(_frfWriteBundle_0_wrdata_T_2, frfWriteBundle_0_wrdata_prevUnrecoded, _frfWriteBundle_0_wrdata_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:44] node _frfWriteBundle_0_wrdata_T_5 = cat(_frfWriteBundle_0_wrdata_T, _frfWriteBundle_0_wrdata_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:10] connect frfWriteBundle_0.wrdata, _frfWriteBundle_0_wrdata_T_5 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 830:30] node _ex_rs_T = or(ex_ra_0, UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 833:37] node _ex_rs_T_1 = bits(_ex_rs_T, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 833:37] infer mport ex_rs_0 = regfile[_ex_rs_T_1], clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 833:37] node _ex_rs_T_2 = or(ex_ra_1, UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 833:37] node _ex_rs_T_3 = bits(_ex_rs_T_2, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 833:37] infer mport ex_rs_1 = regfile[_ex_rs_T_3], clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 833:37] node _ex_rs_T_4 = or(ex_ra_2, UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 833:37] node _ex_rs_T_5 = bits(_ex_rs_T_4, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 833:37] infer mport ex_rs_2 = regfile[_ex_rs_T_5], clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 833:37] when io.valid : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 834:19] when id_ctrl.ren1 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 835:25] node _T_4 = eq(id_ctrl.swap12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 836:13] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 836:30] node _ex_ra_0_T = bits(io.inst, 19, 15) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 836:51] connect ex_ra_0, _ex_ra_0_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 836:41] when id_ctrl.swap12 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 837:29] node _ex_ra_1_T = bits(io.inst, 19, 15) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 837:50] connect ex_ra_1, _ex_ra_1_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 837:40] when id_ctrl.ren2 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 839:25] when id_ctrl.swap12 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 840:29] node _ex_ra_0_T_1 = bits(io.inst, 24, 20) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 840:50] connect ex_ra_0, _ex_ra_0_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 840:40] when id_ctrl.swap23 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 841:29] node _ex_ra_2_T = bits(io.inst, 24, 20) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 841:50] connect ex_ra_2, _ex_ra_2_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 841:40] node _T_5 = eq(id_ctrl.swap12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 842:13] node _T_6 = eq(id_ctrl.swap23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 842:32] node _T_7 = and(_T_5, _T_6) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 842:29] when _T_7 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 842:49] node _ex_ra_1_T_1 = bits(io.inst, 24, 20) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 842:70] connect ex_ra_1, _ex_ra_1_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 842:60] when id_ctrl.ren3 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 844:25] node _ex_ra_2_T_1 = bits(io.inst, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 844:46] connect ex_ra_2, _ex_ra_2_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 844:36] node _ex_rm_T = bits(ex_reg_inst, 14, 12) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 846:30] node _ex_rm_T_1 = eq(_ex_rm_T, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 846:38] node _ex_rm_T_2 = bits(ex_reg_inst, 14, 12) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 846:70] node ex_rm = mux(_ex_rm_T_1, io.fcsr_rm, _ex_rm_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 846:18] inst sfma of FPUFMAPipe_l3_f32 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 873:20] connect sfma.clock, clock connect sfma.reset, reset node _sfma_io_in_valid_T = and(req_valid, ex_ctrl.fma) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 874:33] node _sfma_io_in_valid_T_1 = eq(ex_ctrl.typeTagOut, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 874:70] node _sfma_io_in_valid_T_2 = and(_sfma_io_in_valid_T, _sfma_io_in_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 874:48] connect sfma.io.in.valid, _sfma_io_in_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 874:20] wire sfma_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 849:19] connect sfma_io_in_bits_req.vec, ex_ctrl.vec @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect sfma_io_in_bits_req.wflags, ex_ctrl.wflags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect sfma_io_in_bits_req.sqrt, ex_ctrl.sqrt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect sfma_io_in_bits_req.div, ex_ctrl.div @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect sfma_io_in_bits_req.fma, ex_ctrl.fma @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect sfma_io_in_bits_req.fastpipe, ex_ctrl.fastpipe @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect sfma_io_in_bits_req.toint, ex_ctrl.toint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect sfma_io_in_bits_req.fromint, ex_ctrl.fromint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect sfma_io_in_bits_req.typeTagOut, ex_ctrl.typeTagOut @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect sfma_io_in_bits_req.typeTagIn, ex_ctrl.typeTagIn @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect sfma_io_in_bits_req.swap23, ex_ctrl.swap23 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect sfma_io_in_bits_req.swap12, ex_ctrl.swap12 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect sfma_io_in_bits_req.ren3, ex_ctrl.ren3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect sfma_io_in_bits_req.ren2, ex_ctrl.ren2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect sfma_io_in_bits_req.ren1, ex_ctrl.ren1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect sfma_io_in_bits_req.wen, ex_ctrl.wen @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect sfma_io_in_bits_req.ldst, ex_ctrl.ldst @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect sfma_io_in_bits_req.rm, ex_rm @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 852:12] node _sfma_io_in_bits_req_in1_prev_unswizzled_T = bits(ex_rs_0, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 357:14] node _sfma_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(ex_rs_0, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 358:14] node _sfma_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(ex_rs_0, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 359:14] node sfma_io_in_bits_req_in1_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in1_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_unswizzled_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 356:31] node sfma_io_in_bits_req_in1_floats_0 = cat(sfma_io_in_bits_req_in1_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_unswizzled_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 356:31] node _sfma_io_in_bits_req_in1_prev_isbox_T = bits(ex_rs_0, 64, 60) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:49] node sfma_io_in_bits_req_in1_prev_isbox = andr(_sfma_io_in_bits_req_in1_prev_isbox_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:84] node sfma_io_in_bits_req_in1_oks_0 = and(sfma_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 362:32] node sfma_io_in_bits_req_in1_sign = bits(ex_rs_0, 64, 64) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 274:17] node sfma_io_in_bits_req_in1_fractIn = bits(ex_rs_0, 51, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 275:20] node sfma_io_in_bits_req_in1_expIn = bits(ex_rs_0, 63, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 276:18] node _sfma_io_in_bits_req_in1_fractOut_T = shl(sfma_io_in_bits_req_in1_fractIn, 24) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:28] node sfma_io_in_bits_req_in1_fractOut = shr(_sfma_io_in_bits_req_in1_fractOut_T, 53) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:38] node sfma_io_in_bits_req_in1_expOut_expCode = bits(sfma_io_in_bits_req_in1_expIn, 11, 9) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 279:26] node _sfma_io_in_bits_req_in1_expOut_commonCase_T = add(sfma_io_in_bits_req_in1_expIn, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _sfma_io_in_bits_req_in1_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in1_expOut_commonCase_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _sfma_io_in_bits_req_in1_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in1_expOut_commonCase_T_1, UInt<12>(0h800)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node sfma_io_in_bits_req_in1_expOut_commonCase = tail(_sfma_io_in_bits_req_in1_expOut_commonCase_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node _sfma_io_in_bits_req_in1_expOut_T = eq(sfma_io_in_bits_req_in1_expOut_expCode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:19] node _sfma_io_in_bits_req_in1_expOut_T_1 = geq(sfma_io_in_bits_req_in1_expOut_expCode, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:38] node _sfma_io_in_bits_req_in1_expOut_T_2 = or(_sfma_io_in_bits_req_in1_expOut_T, _sfma_io_in_bits_req_in1_expOut_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:27] node _sfma_io_in_bits_req_in1_expOut_T_3 = bits(sfma_io_in_bits_req_in1_expOut_commonCase, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:69] node _sfma_io_in_bits_req_in1_expOut_T_4 = cat(sfma_io_in_bits_req_in1_expOut_expCode, _sfma_io_in_bits_req_in1_expOut_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:49] node _sfma_io_in_bits_req_in1_expOut_T_5 = bits(sfma_io_in_bits_req_in1_expOut_commonCase, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:97] node sfma_io_in_bits_req_in1_expOut = mux(_sfma_io_in_bits_req_in1_expOut_T_2, _sfma_io_in_bits_req_in1_expOut_T_4, _sfma_io_in_bits_req_in1_expOut_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:10] node sfma_io_in_bits_req_in1_hi = cat(sfma_io_in_bits_req_in1_sign, sfma_io_in_bits_req_in1_expOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node sfma_io_in_bits_req_in1_floats_1 = cat(sfma_io_in_bits_req_in1_hi, sfma_io_in_bits_req_in1_fractOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node _sfma_io_in_bits_req_in1_T = mux(sfma_io_in_bits_req_in1_oks_0, UInt<1>(0h0), UInt<33>(0he0400000)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 372:31] node _sfma_io_in_bits_req_in1_T_1 = or(sfma_io_in_bits_req_in1_floats_0, _sfma_io_in_bits_req_in1_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 372:26] connect sfma_io_in_bits_req.in1, _sfma_io_in_bits_req_in1_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 853:13] node _sfma_io_in_bits_req_in2_prev_unswizzled_T = bits(ex_rs_1, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 357:14] node _sfma_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(ex_rs_1, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 358:14] node _sfma_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(ex_rs_1, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 359:14] node sfma_io_in_bits_req_in2_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in2_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_unswizzled_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 356:31] node sfma_io_in_bits_req_in2_floats_0 = cat(sfma_io_in_bits_req_in2_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_unswizzled_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 356:31] node _sfma_io_in_bits_req_in2_prev_isbox_T = bits(ex_rs_1, 64, 60) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:49] node sfma_io_in_bits_req_in2_prev_isbox = andr(_sfma_io_in_bits_req_in2_prev_isbox_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:84] node sfma_io_in_bits_req_in2_oks_0 = and(sfma_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 362:32] node sfma_io_in_bits_req_in2_sign = bits(ex_rs_1, 64, 64) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 274:17] node sfma_io_in_bits_req_in2_fractIn = bits(ex_rs_1, 51, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 275:20] node sfma_io_in_bits_req_in2_expIn = bits(ex_rs_1, 63, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 276:18] node _sfma_io_in_bits_req_in2_fractOut_T = shl(sfma_io_in_bits_req_in2_fractIn, 24) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:28] node sfma_io_in_bits_req_in2_fractOut = shr(_sfma_io_in_bits_req_in2_fractOut_T, 53) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:38] node sfma_io_in_bits_req_in2_expOut_expCode = bits(sfma_io_in_bits_req_in2_expIn, 11, 9) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 279:26] node _sfma_io_in_bits_req_in2_expOut_commonCase_T = add(sfma_io_in_bits_req_in2_expIn, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _sfma_io_in_bits_req_in2_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in2_expOut_commonCase_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _sfma_io_in_bits_req_in2_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in2_expOut_commonCase_T_1, UInt<12>(0h800)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node sfma_io_in_bits_req_in2_expOut_commonCase = tail(_sfma_io_in_bits_req_in2_expOut_commonCase_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node _sfma_io_in_bits_req_in2_expOut_T = eq(sfma_io_in_bits_req_in2_expOut_expCode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:19] node _sfma_io_in_bits_req_in2_expOut_T_1 = geq(sfma_io_in_bits_req_in2_expOut_expCode, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:38] node _sfma_io_in_bits_req_in2_expOut_T_2 = or(_sfma_io_in_bits_req_in2_expOut_T, _sfma_io_in_bits_req_in2_expOut_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:27] node _sfma_io_in_bits_req_in2_expOut_T_3 = bits(sfma_io_in_bits_req_in2_expOut_commonCase, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:69] node _sfma_io_in_bits_req_in2_expOut_T_4 = cat(sfma_io_in_bits_req_in2_expOut_expCode, _sfma_io_in_bits_req_in2_expOut_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:49] node _sfma_io_in_bits_req_in2_expOut_T_5 = bits(sfma_io_in_bits_req_in2_expOut_commonCase, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:97] node sfma_io_in_bits_req_in2_expOut = mux(_sfma_io_in_bits_req_in2_expOut_T_2, _sfma_io_in_bits_req_in2_expOut_T_4, _sfma_io_in_bits_req_in2_expOut_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:10] node sfma_io_in_bits_req_in2_hi = cat(sfma_io_in_bits_req_in2_sign, sfma_io_in_bits_req_in2_expOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node sfma_io_in_bits_req_in2_floats_1 = cat(sfma_io_in_bits_req_in2_hi, sfma_io_in_bits_req_in2_fractOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node _sfma_io_in_bits_req_in2_T = mux(sfma_io_in_bits_req_in2_oks_0, UInt<1>(0h0), UInt<33>(0he0400000)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 372:31] node _sfma_io_in_bits_req_in2_T_1 = or(sfma_io_in_bits_req_in2_floats_0, _sfma_io_in_bits_req_in2_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 372:26] connect sfma_io_in_bits_req.in2, _sfma_io_in_bits_req_in2_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 854:13] node _sfma_io_in_bits_req_in3_prev_unswizzled_T = bits(ex_rs_2, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 357:14] node _sfma_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(ex_rs_2, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 358:14] node _sfma_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(ex_rs_2, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 359:14] node sfma_io_in_bits_req_in3_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in3_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_unswizzled_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 356:31] node sfma_io_in_bits_req_in3_floats_0 = cat(sfma_io_in_bits_req_in3_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_unswizzled_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 356:31] node _sfma_io_in_bits_req_in3_prev_isbox_T = bits(ex_rs_2, 64, 60) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:49] node sfma_io_in_bits_req_in3_prev_isbox = andr(_sfma_io_in_bits_req_in3_prev_isbox_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:84] node sfma_io_in_bits_req_in3_oks_0 = and(sfma_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 362:32] node sfma_io_in_bits_req_in3_sign = bits(ex_rs_2, 64, 64) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 274:17] node sfma_io_in_bits_req_in3_fractIn = bits(ex_rs_2, 51, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 275:20] node sfma_io_in_bits_req_in3_expIn = bits(ex_rs_2, 63, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 276:18] node _sfma_io_in_bits_req_in3_fractOut_T = shl(sfma_io_in_bits_req_in3_fractIn, 24) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:28] node sfma_io_in_bits_req_in3_fractOut = shr(_sfma_io_in_bits_req_in3_fractOut_T, 53) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:38] node sfma_io_in_bits_req_in3_expOut_expCode = bits(sfma_io_in_bits_req_in3_expIn, 11, 9) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 279:26] node _sfma_io_in_bits_req_in3_expOut_commonCase_T = add(sfma_io_in_bits_req_in3_expIn, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _sfma_io_in_bits_req_in3_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in3_expOut_commonCase_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _sfma_io_in_bits_req_in3_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in3_expOut_commonCase_T_1, UInt<12>(0h800)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node sfma_io_in_bits_req_in3_expOut_commonCase = tail(_sfma_io_in_bits_req_in3_expOut_commonCase_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node _sfma_io_in_bits_req_in3_expOut_T = eq(sfma_io_in_bits_req_in3_expOut_expCode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:19] node _sfma_io_in_bits_req_in3_expOut_T_1 = geq(sfma_io_in_bits_req_in3_expOut_expCode, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:38] node _sfma_io_in_bits_req_in3_expOut_T_2 = or(_sfma_io_in_bits_req_in3_expOut_T, _sfma_io_in_bits_req_in3_expOut_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:27] node _sfma_io_in_bits_req_in3_expOut_T_3 = bits(sfma_io_in_bits_req_in3_expOut_commonCase, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:69] node _sfma_io_in_bits_req_in3_expOut_T_4 = cat(sfma_io_in_bits_req_in3_expOut_expCode, _sfma_io_in_bits_req_in3_expOut_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:49] node _sfma_io_in_bits_req_in3_expOut_T_5 = bits(sfma_io_in_bits_req_in3_expOut_commonCase, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:97] node sfma_io_in_bits_req_in3_expOut = mux(_sfma_io_in_bits_req_in3_expOut_T_2, _sfma_io_in_bits_req_in3_expOut_T_4, _sfma_io_in_bits_req_in3_expOut_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:10] node sfma_io_in_bits_req_in3_hi = cat(sfma_io_in_bits_req_in3_sign, sfma_io_in_bits_req_in3_expOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node sfma_io_in_bits_req_in3_floats_1 = cat(sfma_io_in_bits_req_in3_hi, sfma_io_in_bits_req_in3_fractOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node _sfma_io_in_bits_req_in3_T = mux(sfma_io_in_bits_req_in3_oks_0, UInt<1>(0h0), UInt<33>(0he0400000)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 372:31] node _sfma_io_in_bits_req_in3_T_1 = or(sfma_io_in_bits_req_in3_floats_0, _sfma_io_in_bits_req_in3_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 372:26] connect sfma_io_in_bits_req.in3, _sfma_io_in_bits_req_in3_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 855:13] node _sfma_io_in_bits_req_typ_T = bits(ex_reg_inst, 21, 20) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 856:27] connect sfma_io_in_bits_req.typ, _sfma_io_in_bits_req_typ_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 856:13] node _sfma_io_in_bits_req_fmt_T = bits(ex_reg_inst, 26, 25) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 857:27] connect sfma_io_in_bits_req.fmt, _sfma_io_in_bits_req_fmt_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 857:13] node _sfma_io_in_bits_req_fmaCmd_T = bits(ex_reg_inst, 3, 2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 858:30] node _sfma_io_in_bits_req_fmaCmd_T_1 = eq(ex_ctrl.ren3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 858:39] node _sfma_io_in_bits_req_fmaCmd_T_2 = bits(ex_reg_inst, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 858:67] node _sfma_io_in_bits_req_fmaCmd_T_3 = and(_sfma_io_in_bits_req_fmaCmd_T_1, _sfma_io_in_bits_req_fmaCmd_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 858:53] node _sfma_io_in_bits_req_fmaCmd_T_4 = or(_sfma_io_in_bits_req_fmaCmd_T, _sfma_io_in_bits_req_fmaCmd_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 858:36] connect sfma_io_in_bits_req.fmaCmd, _sfma_io_in_bits_req_fmaCmd_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 858:16] when ex_cp_valid : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 859:24] connect sfma_io_in_bits_req, io.cp_req.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 860:11] when io.cp_req.bits.swap12 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 861:36] connect sfma_io_in_bits_req.in1, io.cp_req.bits.in2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 862:17] connect sfma_io_in_bits_req.in2, io.cp_req.bits.in1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 863:17] when io.cp_req.bits.swap23 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 865:36] connect sfma_io_in_bits_req.in2, io.cp_req.bits.in3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 866:17] connect sfma_io_in_bits_req.in3, io.cp_req.bits.in2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 867:17] connect sfma.io.in.bits.in3, sfma_io_in_bits_req.in3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.in2, sfma_io_in_bits_req.in2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.in1, sfma_io_in_bits_req.in1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.fmt, sfma_io_in_bits_req.fmt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.typ, sfma_io_in_bits_req.typ @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.fmaCmd, sfma_io_in_bits_req.fmaCmd @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.rm, sfma_io_in_bits_req.rm @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.vec, sfma_io_in_bits_req.vec @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.wflags, sfma_io_in_bits_req.wflags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.sqrt, sfma_io_in_bits_req.sqrt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.div, sfma_io_in_bits_req.div @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.fma, sfma_io_in_bits_req.fma @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.fastpipe, sfma_io_in_bits_req.fastpipe @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.toint, sfma_io_in_bits_req.toint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.fromint, sfma_io_in_bits_req.fromint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.typeTagOut, sfma_io_in_bits_req.typeTagOut @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.typeTagIn, sfma_io_in_bits_req.typeTagIn @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.swap23, sfma_io_in_bits_req.swap23 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.swap12, sfma_io_in_bits_req.swap12 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.ren3, sfma_io_in_bits_req.ren3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.ren2, sfma_io_in_bits_req.ren2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.ren1, sfma_io_in_bits_req.ren1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.wen, sfma_io_in_bits_req.wen @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] connect sfma.io.in.bits.ldst, sfma_io_in_bits_req.ldst @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 875:19] inst fpiu of FPToInt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 877:20] connect fpiu.clock, clock connect fpiu.reset, reset node _fpiu_io_in_valid_T = or(ex_ctrl.toint, ex_ctrl.div) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 878:51] node _fpiu_io_in_valid_T_1 = or(_fpiu_io_in_valid_T, ex_ctrl.sqrt) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 878:66] node _fpiu_io_in_valid_T_2 = and(ex_ctrl.fastpipe, ex_ctrl.wflags) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 878:103] node _fpiu_io_in_valid_T_3 = or(_fpiu_io_in_valid_T_1, _fpiu_io_in_valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 878:82] node _fpiu_io_in_valid_T_4 = and(req_valid, _fpiu_io_in_valid_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 878:33] connect fpiu.io.in.valid, _fpiu_io_in_valid_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 878:20] wire fpiu_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 849:19] connect fpiu_io_in_bits_req.vec, ex_ctrl.vec @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect fpiu_io_in_bits_req.wflags, ex_ctrl.wflags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect fpiu_io_in_bits_req.sqrt, ex_ctrl.sqrt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect fpiu_io_in_bits_req.div, ex_ctrl.div @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect fpiu_io_in_bits_req.fma, ex_ctrl.fma @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect fpiu_io_in_bits_req.fastpipe, ex_ctrl.fastpipe @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect fpiu_io_in_bits_req.toint, ex_ctrl.toint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect fpiu_io_in_bits_req.fromint, ex_ctrl.fromint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect fpiu_io_in_bits_req.typeTagOut, ex_ctrl.typeTagOut @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect fpiu_io_in_bits_req.typeTagIn, ex_ctrl.typeTagIn @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect fpiu_io_in_bits_req.swap23, ex_ctrl.swap23 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect fpiu_io_in_bits_req.swap12, ex_ctrl.swap12 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect fpiu_io_in_bits_req.ren3, ex_ctrl.ren3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect fpiu_io_in_bits_req.ren2, ex_ctrl.ren2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect fpiu_io_in_bits_req.ren1, ex_ctrl.ren1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect fpiu_io_in_bits_req.wen, ex_ctrl.wen @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect fpiu_io_in_bits_req.ldst, ex_ctrl.ldst @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect fpiu_io_in_bits_req.rm, ex_rm @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 852:12] node _fpiu_io_in_bits_req_in1_prev_unswizzled_T = bits(ex_rs_0, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 357:14] node _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(ex_rs_0, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 358:14] node _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(ex_rs_0, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 359:14] node fpiu_io_in_bits_req_in1_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in1_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 356:31] node fpiu_io_in_bits_req_in1_prev_unswizzled = cat(fpiu_io_in_bits_req_in1_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 356:31] node fpiu_io_in_bits_req_in1_prev_prev_sign = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 274:17] node fpiu_io_in_bits_req_in1_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 22, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 275:20] node fpiu_io_in_bits_req_in1_prev_prev_expIn = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 31, 23) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 276:18] node _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in1_prev_prev_fractIn, 53) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:28] node fpiu_io_in_bits_req_in1_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in1_prev_prev_fractOut_T, 24) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:38] node fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in1_prev_prev_expIn, 8, 6) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 279:26] node _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in1_prev_prev_expIn, UInt<12>(0h800)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:19] node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:38] node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in1_prev_prev_expOut_T, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:27] node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:69] node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:49] node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:97] node fpiu_io_in_bits_req_in1_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:10] node fpiu_io_in_bits_req_in1_prev_prev_hi = cat(fpiu_io_in_bits_req_in1_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_expOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node fpiu_io_in_bits_req_in1_floats_0 = cat(fpiu_io_in_bits_req_in1_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_fractOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node _fpiu_io_in_bits_req_in1_prev_isbox_T = bits(ex_rs_0, 64, 60) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:49] node fpiu_io_in_bits_req_in1_prev_isbox = andr(_fpiu_io_in_bits_req_in1_prev_isbox_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:84] node fpiu_io_in_bits_req_in1_oks_0 = and(fpiu_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 362:32] node _fpiu_io_in_bits_req_in1_truncIdx_T = or(ex_ctrl.typeTagIn, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:21] node fpiu_io_in_bits_req_in1_truncIdx = bits(_fpiu_io_in_bits_req_in1_truncIdx_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:47] node _fpiu_io_in_bits_req_in1_T = eq(fpiu_io_in_bits_req_in1_truncIdx, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _fpiu_io_in_bits_req_in1_T_1 = mux(_fpiu_io_in_bits_req_in1_T, UInt<1>(0h1), fpiu_io_in_bits_req_in1_oks_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _fpiu_io_in_bits_req_in1_truncIdx_T_1 = or(ex_ctrl.typeTagIn, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:21] node fpiu_io_in_bits_req_in1_truncIdx_1 = bits(_fpiu_io_in_bits_req_in1_truncIdx_T_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:47] node _fpiu_io_in_bits_req_in1_T_2 = eq(fpiu_io_in_bits_req_in1_truncIdx_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _fpiu_io_in_bits_req_in1_T_3 = mux(_fpiu_io_in_bits_req_in1_T_2, ex_rs_0, fpiu_io_in_bits_req_in1_floats_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _fpiu_io_in_bits_req_in1_T_4 = mux(_fpiu_io_in_bits_req_in1_T_1, _fpiu_io_in_bits_req_in1_T_3, UInt<65>(0he008000000000000)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 369:10] connect fpiu_io_in_bits_req.in1, _fpiu_io_in_bits_req_in1_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 853:13] node _fpiu_io_in_bits_req_in2_prev_unswizzled_T = bits(ex_rs_1, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 357:14] node _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(ex_rs_1, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 358:14] node _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(ex_rs_1, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 359:14] node fpiu_io_in_bits_req_in2_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in2_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 356:31] node fpiu_io_in_bits_req_in2_prev_unswizzled = cat(fpiu_io_in_bits_req_in2_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 356:31] node fpiu_io_in_bits_req_in2_prev_prev_sign = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 274:17] node fpiu_io_in_bits_req_in2_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 22, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 275:20] node fpiu_io_in_bits_req_in2_prev_prev_expIn = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 31, 23) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 276:18] node _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in2_prev_prev_fractIn, 53) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:28] node fpiu_io_in_bits_req_in2_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in2_prev_prev_fractOut_T, 24) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:38] node fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in2_prev_prev_expIn, 8, 6) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 279:26] node _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in2_prev_prev_expIn, UInt<12>(0h800)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:19] node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:38] node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in2_prev_prev_expOut_T, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:27] node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:69] node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:49] node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:97] node fpiu_io_in_bits_req_in2_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:10] node fpiu_io_in_bits_req_in2_prev_prev_hi = cat(fpiu_io_in_bits_req_in2_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_expOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node fpiu_io_in_bits_req_in2_floats_0 = cat(fpiu_io_in_bits_req_in2_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_fractOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node _fpiu_io_in_bits_req_in2_prev_isbox_T = bits(ex_rs_1, 64, 60) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:49] node fpiu_io_in_bits_req_in2_prev_isbox = andr(_fpiu_io_in_bits_req_in2_prev_isbox_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:84] node fpiu_io_in_bits_req_in2_oks_0 = and(fpiu_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 362:32] node _fpiu_io_in_bits_req_in2_truncIdx_T = or(ex_ctrl.typeTagIn, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:21] node fpiu_io_in_bits_req_in2_truncIdx = bits(_fpiu_io_in_bits_req_in2_truncIdx_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:47] node _fpiu_io_in_bits_req_in2_T = eq(fpiu_io_in_bits_req_in2_truncIdx, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _fpiu_io_in_bits_req_in2_T_1 = mux(_fpiu_io_in_bits_req_in2_T, UInt<1>(0h1), fpiu_io_in_bits_req_in2_oks_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _fpiu_io_in_bits_req_in2_truncIdx_T_1 = or(ex_ctrl.typeTagIn, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:21] node fpiu_io_in_bits_req_in2_truncIdx_1 = bits(_fpiu_io_in_bits_req_in2_truncIdx_T_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:47] node _fpiu_io_in_bits_req_in2_T_2 = eq(fpiu_io_in_bits_req_in2_truncIdx_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _fpiu_io_in_bits_req_in2_T_3 = mux(_fpiu_io_in_bits_req_in2_T_2, ex_rs_1, fpiu_io_in_bits_req_in2_floats_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _fpiu_io_in_bits_req_in2_T_4 = mux(_fpiu_io_in_bits_req_in2_T_1, _fpiu_io_in_bits_req_in2_T_3, UInt<65>(0he008000000000000)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 369:10] connect fpiu_io_in_bits_req.in2, _fpiu_io_in_bits_req_in2_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 854:13] node _fpiu_io_in_bits_req_in3_prev_unswizzled_T = bits(ex_rs_2, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 357:14] node _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(ex_rs_2, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 358:14] node _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(ex_rs_2, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 359:14] node fpiu_io_in_bits_req_in3_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in3_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 356:31] node fpiu_io_in_bits_req_in3_prev_unswizzled = cat(fpiu_io_in_bits_req_in3_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 356:31] node fpiu_io_in_bits_req_in3_prev_prev_sign = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 274:17] node fpiu_io_in_bits_req_in3_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 22, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 275:20] node fpiu_io_in_bits_req_in3_prev_prev_expIn = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 31, 23) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 276:18] node _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in3_prev_prev_fractIn, 53) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:28] node fpiu_io_in_bits_req_in3_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in3_prev_prev_fractOut_T, 24) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:38] node fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in3_prev_prev_expIn, 8, 6) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 279:26] node _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in3_prev_prev_expIn, UInt<12>(0h800)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:19] node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:38] node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in3_prev_prev_expOut_T, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:27] node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:69] node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:49] node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:97] node fpiu_io_in_bits_req_in3_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:10] node fpiu_io_in_bits_req_in3_prev_prev_hi = cat(fpiu_io_in_bits_req_in3_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_expOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node fpiu_io_in_bits_req_in3_floats_0 = cat(fpiu_io_in_bits_req_in3_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_fractOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node _fpiu_io_in_bits_req_in3_prev_isbox_T = bits(ex_rs_2, 64, 60) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:49] node fpiu_io_in_bits_req_in3_prev_isbox = andr(_fpiu_io_in_bits_req_in3_prev_isbox_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:84] node fpiu_io_in_bits_req_in3_oks_0 = and(fpiu_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 362:32] node _fpiu_io_in_bits_req_in3_truncIdx_T = or(ex_ctrl.typeTagIn, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:21] node fpiu_io_in_bits_req_in3_truncIdx = bits(_fpiu_io_in_bits_req_in3_truncIdx_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:47] node _fpiu_io_in_bits_req_in3_T = eq(fpiu_io_in_bits_req_in3_truncIdx, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _fpiu_io_in_bits_req_in3_T_1 = mux(_fpiu_io_in_bits_req_in3_T, UInt<1>(0h1), fpiu_io_in_bits_req_in3_oks_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _fpiu_io_in_bits_req_in3_truncIdx_T_1 = or(ex_ctrl.typeTagIn, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:21] node fpiu_io_in_bits_req_in3_truncIdx_1 = bits(_fpiu_io_in_bits_req_in3_truncIdx_T_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:47] node _fpiu_io_in_bits_req_in3_T_2 = eq(fpiu_io_in_bits_req_in3_truncIdx_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _fpiu_io_in_bits_req_in3_T_3 = mux(_fpiu_io_in_bits_req_in3_T_2, ex_rs_2, fpiu_io_in_bits_req_in3_floats_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _fpiu_io_in_bits_req_in3_T_4 = mux(_fpiu_io_in_bits_req_in3_T_1, _fpiu_io_in_bits_req_in3_T_3, UInt<65>(0he008000000000000)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 369:10] connect fpiu_io_in_bits_req.in3, _fpiu_io_in_bits_req_in3_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 855:13] node _fpiu_io_in_bits_req_typ_T = bits(ex_reg_inst, 21, 20) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 856:27] connect fpiu_io_in_bits_req.typ, _fpiu_io_in_bits_req_typ_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 856:13] node _fpiu_io_in_bits_req_fmt_T = bits(ex_reg_inst, 26, 25) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 857:27] connect fpiu_io_in_bits_req.fmt, _fpiu_io_in_bits_req_fmt_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 857:13] node _fpiu_io_in_bits_req_fmaCmd_T = bits(ex_reg_inst, 3, 2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 858:30] node _fpiu_io_in_bits_req_fmaCmd_T_1 = eq(ex_ctrl.ren3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 858:39] node _fpiu_io_in_bits_req_fmaCmd_T_2 = bits(ex_reg_inst, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 858:67] node _fpiu_io_in_bits_req_fmaCmd_T_3 = and(_fpiu_io_in_bits_req_fmaCmd_T_1, _fpiu_io_in_bits_req_fmaCmd_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 858:53] node _fpiu_io_in_bits_req_fmaCmd_T_4 = or(_fpiu_io_in_bits_req_fmaCmd_T, _fpiu_io_in_bits_req_fmaCmd_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 858:36] connect fpiu_io_in_bits_req.fmaCmd, _fpiu_io_in_bits_req_fmaCmd_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 858:16] when ex_cp_valid : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 859:24] connect fpiu_io_in_bits_req, io.cp_req.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 860:11] when io.cp_req.bits.swap12 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 861:36] connect fpiu_io_in_bits_req.in1, io.cp_req.bits.in2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 862:17] connect fpiu_io_in_bits_req.in2, io.cp_req.bits.in1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 863:17] when io.cp_req.bits.swap23 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 865:36] connect fpiu_io_in_bits_req.in2, io.cp_req.bits.in3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 866:17] connect fpiu_io_in_bits_req.in3, io.cp_req.bits.in2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 867:17] connect fpiu.io.in.bits.in3, fpiu_io_in_bits_req.in3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.in2, fpiu_io_in_bits_req.in2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.in1, fpiu_io_in_bits_req.in1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.fmt, fpiu_io_in_bits_req.fmt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.typ, fpiu_io_in_bits_req.typ @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.fmaCmd, fpiu_io_in_bits_req.fmaCmd @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.rm, fpiu_io_in_bits_req.rm @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.vec, fpiu_io_in_bits_req.vec @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.wflags, fpiu_io_in_bits_req.wflags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.sqrt, fpiu_io_in_bits_req.sqrt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.div, fpiu_io_in_bits_req.div @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.fma, fpiu_io_in_bits_req.fma @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.fastpipe, fpiu_io_in_bits_req.fastpipe @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.toint, fpiu_io_in_bits_req.toint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.fromint, fpiu_io_in_bits_req.fromint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.typeTagOut, fpiu_io_in_bits_req.typeTagOut @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.typeTagIn, fpiu_io_in_bits_req.typeTagIn @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.swap23, fpiu_io_in_bits_req.swap23 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.swap12, fpiu_io_in_bits_req.swap12 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.ren3, fpiu_io_in_bits_req.ren3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.ren2, fpiu_io_in_bits_req.ren2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.ren1, fpiu_io_in_bits_req.ren1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.wen, fpiu_io_in_bits_req.wen @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect fpiu.io.in.bits.ldst, fpiu_io_in_bits_req.ldst @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 879:19] connect io.store_data, fpiu.io.out.bits.store @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 880:17] connect io.toint_data, fpiu.io.out.bits.toint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 881:17] node _T_8 = and(fpiu.io.out.valid, mem_cp_valid) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 882:26] node _T_9 = and(_T_8, mem_ctrl.toint) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 882:42] when _T_9 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 882:60] connect io.cp_resp.bits.data, fpiu.io.out.bits.toint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 883:26] connect io.cp_resp.valid, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 884:22] inst ifpu of IntToFP @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 887:20] connect ifpu.clock, clock connect ifpu.reset, reset node _ifpu_io_in_valid_T = and(req_valid, ex_ctrl.fromint) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 888:33] connect ifpu.io.in.valid, _ifpu_io_in_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 888:20] connect ifpu.io.in.bits.in1, fpiu.io.in.bits.in1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.typ, fpiu.io.in.bits.typ @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.rm, fpiu.io.in.bits.rm @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.vec, fpiu.io.in.bits.vec @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.wflags, fpiu.io.in.bits.wflags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.sqrt, fpiu.io.in.bits.sqrt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.div, fpiu.io.in.bits.div @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.fma, fpiu.io.in.bits.fma @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.fastpipe, fpiu.io.in.bits.fastpipe @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.toint, fpiu.io.in.bits.toint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.fromint, fpiu.io.in.bits.fromint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.typeTagOut, fpiu.io.in.bits.typeTagOut @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.typeTagIn, fpiu.io.in.bits.typeTagIn @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.swap23, fpiu.io.in.bits.swap23 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.swap12, fpiu.io.in.bits.swap12 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.ren3, fpiu.io.in.bits.ren3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.ren2, fpiu.io.in.bits.ren2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.ren1, fpiu.io.in.bits.ren1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.wen, fpiu.io.in.bits.wen @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] connect ifpu.io.in.bits.ldst, fpiu.io.in.bits.ldst @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 889:19] node _ifpu_io_in_bits_in1_T = mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 890:29] connect ifpu.io.in.bits.in1, _ifpu_io_in_bits_in1_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 890:23] inst fpmu of FPToFP @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 892:20] connect fpmu.clock, clock connect fpmu.reset, reset node _fpmu_io_in_valid_T = and(req_valid, ex_ctrl.fastpipe) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 893:33] connect fpmu.io.in.valid, _fpmu_io_in_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 893:20] connect fpmu.io.in.bits.in3, fpiu.io.in.bits.in3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.in2, fpiu.io.in.bits.in2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.in1, fpiu.io.in.bits.in1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.fmt, fpiu.io.in.bits.fmt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.typ, fpiu.io.in.bits.typ @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.fmaCmd, fpiu.io.in.bits.fmaCmd @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.rm, fpiu.io.in.bits.rm @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.vec, fpiu.io.in.bits.vec @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.wflags, fpiu.io.in.bits.wflags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.sqrt, fpiu.io.in.bits.sqrt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.div, fpiu.io.in.bits.div @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.fma, fpiu.io.in.bits.fma @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.fastpipe, fpiu.io.in.bits.fastpipe @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.toint, fpiu.io.in.bits.toint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.fromint, fpiu.io.in.bits.fromint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.typeTagOut, fpiu.io.in.bits.typeTagOut @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.typeTagIn, fpiu.io.in.bits.typeTagIn @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.swap23, fpiu.io.in.bits.swap23 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.swap12, fpiu.io.in.bits.swap12 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.ren3, fpiu.io.in.bits.ren3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.ren2, fpiu.io.in.bits.ren2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.ren1, fpiu.io.in.bits.ren1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.wen, fpiu.io.in.bits.wen @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.in.bits.ldst, fpiu.io.in.bits.ldst @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 894:19] connect fpmu.io.lt, fpiu.io.out.bits.lt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 895:14] wire divSqrt_wen : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 897:32] connect divSqrt_wen, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 897:32] wire divSqrt_inFlight : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 898:37] connect divSqrt_inFlight, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 898:37] reg divSqrt_waddr : UInt<5>, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 899:26] reg divSqrt_cp : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 900:23] wire divSqrt_typeTag : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 901:29] wire divSqrt_wdata : UInt<65> @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 902:27] wire divSqrt_flags : UInt<5> @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 903:27] invalidate divSqrt_typeTag @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 904:19] invalidate divSqrt_wdata @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 905:17] invalidate divSqrt_flags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 906:17] inst dfma of FPUFMAPipe_l4_f64 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 914:28] connect dfma.clock, clock connect dfma.reset, reset node _dfma_io_in_valid_T = and(req_valid, ex_ctrl.fma) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 915:41] node _dfma_io_in_valid_T_1 = eq(ex_ctrl.typeTagOut, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 915:78] node _dfma_io_in_valid_T_2 = and(_dfma_io_in_valid_T, _dfma_io_in_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 915:56] connect dfma.io.in.valid, _dfma_io_in_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 915:28] wire dfma_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 849:19] connect dfma_io_in_bits_req.vec, ex_ctrl.vec @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect dfma_io_in_bits_req.wflags, ex_ctrl.wflags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect dfma_io_in_bits_req.sqrt, ex_ctrl.sqrt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect dfma_io_in_bits_req.div, ex_ctrl.div @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect dfma_io_in_bits_req.fma, ex_ctrl.fma @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect dfma_io_in_bits_req.fastpipe, ex_ctrl.fastpipe @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect dfma_io_in_bits_req.toint, ex_ctrl.toint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect dfma_io_in_bits_req.fromint, ex_ctrl.fromint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect dfma_io_in_bits_req.typeTagOut, ex_ctrl.typeTagOut @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect dfma_io_in_bits_req.typeTagIn, ex_ctrl.typeTagIn @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect dfma_io_in_bits_req.swap23, ex_ctrl.swap23 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect dfma_io_in_bits_req.swap12, ex_ctrl.swap12 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect dfma_io_in_bits_req.ren3, ex_ctrl.ren3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect dfma_io_in_bits_req.ren2, ex_ctrl.ren2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect dfma_io_in_bits_req.ren1, ex_ctrl.ren1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect dfma_io_in_bits_req.wen, ex_ctrl.wen @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect dfma_io_in_bits_req.ldst, ex_ctrl.ldst @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 851:57] connect dfma_io_in_bits_req.rm, ex_rm @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 852:12] node _dfma_io_in_bits_req_in1_prev_unswizzled_T = bits(ex_rs_0, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 357:14] node _dfma_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(ex_rs_0, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 358:14] node _dfma_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(ex_rs_0, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 359:14] node dfma_io_in_bits_req_in1_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in1_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_unswizzled_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 356:31] node dfma_io_in_bits_req_in1_prev_unswizzled = cat(dfma_io_in_bits_req_in1_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_unswizzled_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 356:31] node dfma_io_in_bits_req_in1_prev_prev_sign = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 274:17] node dfma_io_in_bits_req_in1_prev_prev_fractIn = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 22, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 275:20] node dfma_io_in_bits_req_in1_prev_prev_expIn = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 31, 23) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 276:18] node _dfma_io_in_bits_req_in1_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in1_prev_prev_fractIn, 53) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:28] node dfma_io_in_bits_req_in1_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in1_prev_prev_fractOut_T, 24) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:38] node dfma_io_in_bits_req_in1_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in1_prev_prev_expIn, 8, 6) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 279:26] node _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in1_prev_prev_expIn, UInt<12>(0h800)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node _dfma_io_in_bits_req_in1_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:19] node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:38] node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in1_prev_prev_expOut_T, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:27] node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:69] node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:49] node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:97] node dfma_io_in_bits_req_in1_prev_prev_expOut = mux(_dfma_io_in_bits_req_in1_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:10] node dfma_io_in_bits_req_in1_prev_prev_hi = cat(dfma_io_in_bits_req_in1_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_expOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node dfma_io_in_bits_req_in1_floats_0 = cat(dfma_io_in_bits_req_in1_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_fractOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node _dfma_io_in_bits_req_in1_prev_isbox_T = bits(ex_rs_0, 64, 60) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:49] node dfma_io_in_bits_req_in1_prev_isbox = andr(_dfma_io_in_bits_req_in1_prev_isbox_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:84] node dfma_io_in_bits_req_in1_oks_0 = and(dfma_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 362:32] node _dfma_io_in_bits_req_in1_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 372:31] node _dfma_io_in_bits_req_in1_T_1 = or(ex_rs_0, _dfma_io_in_bits_req_in1_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 372:26] connect dfma_io_in_bits_req.in1, _dfma_io_in_bits_req_in1_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 853:13] node _dfma_io_in_bits_req_in2_prev_unswizzled_T = bits(ex_rs_1, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 357:14] node _dfma_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(ex_rs_1, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 358:14] node _dfma_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(ex_rs_1, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 359:14] node dfma_io_in_bits_req_in2_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in2_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_unswizzled_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 356:31] node dfma_io_in_bits_req_in2_prev_unswizzled = cat(dfma_io_in_bits_req_in2_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_unswizzled_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 356:31] node dfma_io_in_bits_req_in2_prev_prev_sign = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 274:17] node dfma_io_in_bits_req_in2_prev_prev_fractIn = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 22, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 275:20] node dfma_io_in_bits_req_in2_prev_prev_expIn = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 31, 23) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 276:18] node _dfma_io_in_bits_req_in2_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in2_prev_prev_fractIn, 53) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:28] node dfma_io_in_bits_req_in2_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in2_prev_prev_fractOut_T, 24) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:38] node dfma_io_in_bits_req_in2_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in2_prev_prev_expIn, 8, 6) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 279:26] node _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in2_prev_prev_expIn, UInt<12>(0h800)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node _dfma_io_in_bits_req_in2_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:19] node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:38] node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in2_prev_prev_expOut_T, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:27] node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:69] node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:49] node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:97] node dfma_io_in_bits_req_in2_prev_prev_expOut = mux(_dfma_io_in_bits_req_in2_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:10] node dfma_io_in_bits_req_in2_prev_prev_hi = cat(dfma_io_in_bits_req_in2_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_expOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node dfma_io_in_bits_req_in2_floats_0 = cat(dfma_io_in_bits_req_in2_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_fractOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node _dfma_io_in_bits_req_in2_prev_isbox_T = bits(ex_rs_1, 64, 60) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:49] node dfma_io_in_bits_req_in2_prev_isbox = andr(_dfma_io_in_bits_req_in2_prev_isbox_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:84] node dfma_io_in_bits_req_in2_oks_0 = and(dfma_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 362:32] node _dfma_io_in_bits_req_in2_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 372:31] node _dfma_io_in_bits_req_in2_T_1 = or(ex_rs_1, _dfma_io_in_bits_req_in2_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 372:26] connect dfma_io_in_bits_req.in2, _dfma_io_in_bits_req_in2_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 854:13] node _dfma_io_in_bits_req_in3_prev_unswizzled_T = bits(ex_rs_2, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 357:14] node _dfma_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(ex_rs_2, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 358:14] node _dfma_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(ex_rs_2, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 359:14] node dfma_io_in_bits_req_in3_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in3_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_unswizzled_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 356:31] node dfma_io_in_bits_req_in3_prev_unswizzled = cat(dfma_io_in_bits_req_in3_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_unswizzled_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 356:31] node dfma_io_in_bits_req_in3_prev_prev_sign = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 274:17] node dfma_io_in_bits_req_in3_prev_prev_fractIn = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 22, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 275:20] node dfma_io_in_bits_req_in3_prev_prev_expIn = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 31, 23) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 276:18] node _dfma_io_in_bits_req_in3_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in3_prev_prev_fractIn, 53) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:28] node dfma_io_in_bits_req_in3_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in3_prev_prev_fractOut_T, 24) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:38] node dfma_io_in_bits_req_in3_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in3_prev_prev_expIn, 8, 6) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 279:26] node _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in3_prev_prev_expIn, UInt<12>(0h800)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node _dfma_io_in_bits_req_in3_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:19] node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:38] node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in3_prev_prev_expOut_T, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:27] node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:69] node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:49] node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:97] node dfma_io_in_bits_req_in3_prev_prev_expOut = mux(_dfma_io_in_bits_req_in3_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:10] node dfma_io_in_bits_req_in3_prev_prev_hi = cat(dfma_io_in_bits_req_in3_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_expOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node dfma_io_in_bits_req_in3_floats_0 = cat(dfma_io_in_bits_req_in3_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_fractOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node _dfma_io_in_bits_req_in3_prev_isbox_T = bits(ex_rs_2, 64, 60) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:49] node dfma_io_in_bits_req_in3_prev_isbox = andr(_dfma_io_in_bits_req_in3_prev_isbox_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:84] node dfma_io_in_bits_req_in3_oks_0 = and(dfma_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 362:32] node _dfma_io_in_bits_req_in3_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 372:31] node _dfma_io_in_bits_req_in3_T_1 = or(ex_rs_2, _dfma_io_in_bits_req_in3_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 372:26] connect dfma_io_in_bits_req.in3, _dfma_io_in_bits_req_in3_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 855:13] node _dfma_io_in_bits_req_typ_T = bits(ex_reg_inst, 21, 20) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 856:27] connect dfma_io_in_bits_req.typ, _dfma_io_in_bits_req_typ_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 856:13] node _dfma_io_in_bits_req_fmt_T = bits(ex_reg_inst, 26, 25) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 857:27] connect dfma_io_in_bits_req.fmt, _dfma_io_in_bits_req_fmt_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 857:13] node _dfma_io_in_bits_req_fmaCmd_T = bits(ex_reg_inst, 3, 2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 858:30] node _dfma_io_in_bits_req_fmaCmd_T_1 = eq(ex_ctrl.ren3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 858:39] node _dfma_io_in_bits_req_fmaCmd_T_2 = bits(ex_reg_inst, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 858:67] node _dfma_io_in_bits_req_fmaCmd_T_3 = and(_dfma_io_in_bits_req_fmaCmd_T_1, _dfma_io_in_bits_req_fmaCmd_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 858:53] node _dfma_io_in_bits_req_fmaCmd_T_4 = or(_dfma_io_in_bits_req_fmaCmd_T, _dfma_io_in_bits_req_fmaCmd_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 858:36] connect dfma_io_in_bits_req.fmaCmd, _dfma_io_in_bits_req_fmaCmd_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 858:16] when ex_cp_valid : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 859:24] connect dfma_io_in_bits_req, io.cp_req.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 860:11] when io.cp_req.bits.swap12 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 861:36] connect dfma_io_in_bits_req.in1, io.cp_req.bits.in2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 862:17] connect dfma_io_in_bits_req.in2, io.cp_req.bits.in1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 863:17] when io.cp_req.bits.swap23 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 865:36] connect dfma_io_in_bits_req.in2, io.cp_req.bits.in3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 866:17] connect dfma_io_in_bits_req.in3, io.cp_req.bits.in2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 867:17] connect dfma.io.in.bits.in3, dfma_io_in_bits_req.in3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.in2, dfma_io_in_bits_req.in2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.in1, dfma_io_in_bits_req.in1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.fmt, dfma_io_in_bits_req.fmt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.typ, dfma_io_in_bits_req.typ @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.fmaCmd, dfma_io_in_bits_req.fmaCmd @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.rm, dfma_io_in_bits_req.rm @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.vec, dfma_io_in_bits_req.vec @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.wflags, dfma_io_in_bits_req.wflags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.sqrt, dfma_io_in_bits_req.sqrt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.div, dfma_io_in_bits_req.div @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.fma, dfma_io_in_bits_req.fma @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.fastpipe, dfma_io_in_bits_req.fastpipe @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.toint, dfma_io_in_bits_req.toint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.fromint, dfma_io_in_bits_req.fromint @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.typeTagOut, dfma_io_in_bits_req.typeTagOut @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.typeTagIn, dfma_io_in_bits_req.typeTagIn @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.swap23, dfma_io_in_bits_req.swap23 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.swap12, dfma_io_in_bits_req.swap12 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.ren3, dfma_io_in_bits_req.ren3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.ren2, dfma_io_in_bits_req.ren2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.ren1, dfma_io_in_bits_req.ren1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.wen, dfma_io_in_bits_req.wen @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] connect dfma.io.in.bits.ldst, dfma_io_in_bits_req.ldst @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 916:27] node _memLatencyMask_T = mux(mem_ctrl.fastpipe, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:23] node _memLatencyMask_T_1 = mux(mem_ctrl.fromint, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:23] node _memLatencyMask_T_2 = eq(mem_ctrl.typeTagOut, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 912:72] node _memLatencyMask_T_3 = and(mem_ctrl.fma, _memLatencyMask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 912:56] node _memLatencyMask_T_4 = mux(_memLatencyMask_T_3, UInt<2>(0h2), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:23] node _memLatencyMask_T_5 = eq(mem_ctrl.typeTagOut, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 917:78] node _memLatencyMask_T_6 = and(mem_ctrl.fma, _memLatencyMask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 917:62] node _memLatencyMask_T_7 = mux(_memLatencyMask_T_6, UInt<3>(0h4), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:23] node _memLatencyMask_T_8 = or(_memLatencyMask_T, _memLatencyMask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:72] node _memLatencyMask_T_9 = or(_memLatencyMask_T_8, _memLatencyMask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:72] node memLatencyMask = or(_memLatencyMask_T_9, _memLatencyMask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:72] regreset wen : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 940:20] reg wbInfo : { rd : UInt<5>, typeTag : UInt<1>, cp : UInt<1>, pipeid : UInt<2>}[3], clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 941:19] node _mem_wen_T = or(mem_ctrl.fma, mem_ctrl.fastpipe) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 942:48] node _mem_wen_T_1 = or(_mem_wen_T, mem_ctrl.fromint) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 942:69] node mem_wen = and(mem_reg_valid, _mem_wen_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 942:31] node _write_port_busy_T = mux(ex_ctrl.fastpipe, UInt<2>(0h2), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:23] node _write_port_busy_T_1 = mux(ex_ctrl.fromint, UInt<2>(0h2), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:23] node _write_port_busy_T_2 = eq(ex_ctrl.typeTagOut, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 912:72] node _write_port_busy_T_3 = and(ex_ctrl.fma, _write_port_busy_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 912:56] node _write_port_busy_T_4 = mux(_write_port_busy_T_3, UInt<3>(0h4), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:23] node _write_port_busy_T_5 = eq(ex_ctrl.typeTagOut, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 917:78] node _write_port_busy_T_6 = and(ex_ctrl.fma, _write_port_busy_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 917:62] node _write_port_busy_T_7 = mux(_write_port_busy_T_6, UInt<4>(0h8), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:23] node _write_port_busy_T_8 = or(_write_port_busy_T, _write_port_busy_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:72] node _write_port_busy_T_9 = or(_write_port_busy_T_8, _write_port_busy_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:72] node _write_port_busy_T_10 = or(_write_port_busy_T_9, _write_port_busy_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:72] node _write_port_busy_T_11 = and(memLatencyMask, _write_port_busy_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 943:62] node _write_port_busy_T_12 = orr(_write_port_busy_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 943:89] node _write_port_busy_T_13 = and(mem_wen, _write_port_busy_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 943:43] node _write_port_busy_T_14 = mux(ex_ctrl.fastpipe, UInt<3>(0h4), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:23] node _write_port_busy_T_15 = mux(ex_ctrl.fromint, UInt<3>(0h4), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:23] node _write_port_busy_T_16 = eq(ex_ctrl.typeTagOut, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 912:72] node _write_port_busy_T_17 = and(ex_ctrl.fma, _write_port_busy_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 912:56] node _write_port_busy_T_18 = mux(_write_port_busy_T_17, UInt<4>(0h8), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:23] node _write_port_busy_T_19 = eq(ex_ctrl.typeTagOut, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 917:78] node _write_port_busy_T_20 = and(ex_ctrl.fma, _write_port_busy_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 917:62] node _write_port_busy_T_21 = mux(_write_port_busy_T_20, UInt<5>(0h10), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:23] node _write_port_busy_T_22 = or(_write_port_busy_T_14, _write_port_busy_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:72] node _write_port_busy_T_23 = or(_write_port_busy_T_22, _write_port_busy_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:72] node _write_port_busy_T_24 = or(_write_port_busy_T_23, _write_port_busy_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 927:72] node _write_port_busy_T_25 = and(wen, _write_port_busy_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 943:101] node _write_port_busy_T_26 = orr(_write_port_busy_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 943:128] node _write_port_busy_T_27 = or(_write_port_busy_T_13, _write_port_busy_T_26) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 943:93] reg write_port_busy : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 943:34] when req_valid : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 943:34] connect write_port_busy, _write_port_busy_T_27 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 943:34] node _T_10 = and(mem_reg_valid, write_port_busy) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 944:24] node _T_11 = bits(wen, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 947:14] when _T_11 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 947:21] connect wbInfo[0], wbInfo[1] @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 947:33] node _T_12 = bits(wen, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 947:14] when _T_12 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 947:21] connect wbInfo[1], wbInfo[2] @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 947:33] node _wen_T = shr(wen, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 949:14] connect wen, _wen_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 949:7] when mem_wen : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 950:18] node _T_13 = eq(killm, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 951:11] when _T_13 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 951:19] node _wen_T_1 = shr(wen, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 952:18] node _wen_T_2 = or(_wen_T_1, memLatencyMask) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 952:23] connect wen, _wen_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 952:11] node _T_14 = eq(write_port_busy, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 955:13] node _T_15 = bits(memLatencyMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 955:47] node _T_16 = and(_T_14, _T_15) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 955:30] when _T_16 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 955:52] connect wbInfo[0].cp, mem_cp_valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 956:22] connect wbInfo[0].typeTag, mem_ctrl.typeTagOut @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 957:27] node _wbInfo_0_pipeid_T = mux(mem_ctrl.fastpipe, UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:63] node _wbInfo_0_pipeid_T_1 = mux(mem_ctrl.fromint, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:63] node _wbInfo_0_pipeid_T_2 = eq(mem_ctrl.typeTagOut, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 912:72] node _wbInfo_0_pipeid_T_3 = and(mem_ctrl.fma, _wbInfo_0_pipeid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 912:56] node _wbInfo_0_pipeid_T_4 = mux(_wbInfo_0_pipeid_T_3, UInt<2>(0h2), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:63] node _wbInfo_0_pipeid_T_5 = eq(mem_ctrl.typeTagOut, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 917:78] node _wbInfo_0_pipeid_T_6 = and(mem_ctrl.fma, _wbInfo_0_pipeid_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 917:62] node _wbInfo_0_pipeid_T_7 = mux(_wbInfo_0_pipeid_T_6, UInt<2>(0h3), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:63] node _wbInfo_0_pipeid_T_8 = or(_wbInfo_0_pipeid_T, _wbInfo_0_pipeid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:100] node _wbInfo_0_pipeid_T_9 = or(_wbInfo_0_pipeid_T_8, _wbInfo_0_pipeid_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:100] node _wbInfo_0_pipeid_T_10 = or(_wbInfo_0_pipeid_T_9, _wbInfo_0_pipeid_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:100] connect wbInfo[0].pipeid, _wbInfo_0_pipeid_T_10 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 958:26] node _wbInfo_0_rd_T = bits(mem_reg_inst, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 959:37] connect wbInfo[0].rd, _wbInfo_0_rd_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 959:22] node _T_17 = eq(write_port_busy, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 955:13] node _T_18 = bits(memLatencyMask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 955:47] node _T_19 = and(_T_17, _T_18) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 955:30] when _T_19 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 955:52] connect wbInfo[1].cp, mem_cp_valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 956:22] connect wbInfo[1].typeTag, mem_ctrl.typeTagOut @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 957:27] node _wbInfo_1_pipeid_T = mux(mem_ctrl.fastpipe, UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:63] node _wbInfo_1_pipeid_T_1 = mux(mem_ctrl.fromint, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:63] node _wbInfo_1_pipeid_T_2 = eq(mem_ctrl.typeTagOut, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 912:72] node _wbInfo_1_pipeid_T_3 = and(mem_ctrl.fma, _wbInfo_1_pipeid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 912:56] node _wbInfo_1_pipeid_T_4 = mux(_wbInfo_1_pipeid_T_3, UInt<2>(0h2), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:63] node _wbInfo_1_pipeid_T_5 = eq(mem_ctrl.typeTagOut, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 917:78] node _wbInfo_1_pipeid_T_6 = and(mem_ctrl.fma, _wbInfo_1_pipeid_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 917:62] node _wbInfo_1_pipeid_T_7 = mux(_wbInfo_1_pipeid_T_6, UInt<2>(0h3), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:63] node _wbInfo_1_pipeid_T_8 = or(_wbInfo_1_pipeid_T, _wbInfo_1_pipeid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:100] node _wbInfo_1_pipeid_T_9 = or(_wbInfo_1_pipeid_T_8, _wbInfo_1_pipeid_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:100] node _wbInfo_1_pipeid_T_10 = or(_wbInfo_1_pipeid_T_9, _wbInfo_1_pipeid_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:100] connect wbInfo[1].pipeid, _wbInfo_1_pipeid_T_10 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 958:26] node _wbInfo_1_rd_T = bits(mem_reg_inst, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 959:37] connect wbInfo[1].rd, _wbInfo_1_rd_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 959:22] node _T_20 = eq(write_port_busy, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 955:13] node _T_21 = bits(memLatencyMask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 955:47] node _T_22 = and(_T_20, _T_21) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 955:30] when _T_22 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 955:52] connect wbInfo[2].cp, mem_cp_valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 956:22] connect wbInfo[2].typeTag, mem_ctrl.typeTagOut @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 957:27] node _wbInfo_2_pipeid_T = mux(mem_ctrl.fastpipe, UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:63] node _wbInfo_2_pipeid_T_1 = mux(mem_ctrl.fromint, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:63] node _wbInfo_2_pipeid_T_2 = eq(mem_ctrl.typeTagOut, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 912:72] node _wbInfo_2_pipeid_T_3 = and(mem_ctrl.fma, _wbInfo_2_pipeid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 912:56] node _wbInfo_2_pipeid_T_4 = mux(_wbInfo_2_pipeid_T_3, UInt<2>(0h2), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:63] node _wbInfo_2_pipeid_T_5 = eq(mem_ctrl.typeTagOut, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 917:78] node _wbInfo_2_pipeid_T_6 = and(mem_ctrl.fma, _wbInfo_2_pipeid_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 917:62] node _wbInfo_2_pipeid_T_7 = mux(_wbInfo_2_pipeid_T_6, UInt<2>(0h3), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:63] node _wbInfo_2_pipeid_T_8 = or(_wbInfo_2_pipeid_T, _wbInfo_2_pipeid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:100] node _wbInfo_2_pipeid_T_9 = or(_wbInfo_2_pipeid_T_8, _wbInfo_2_pipeid_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:100] node _wbInfo_2_pipeid_T_10 = or(_wbInfo_2_pipeid_T_9, _wbInfo_2_pipeid_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 929:100] connect wbInfo[2].pipeid, _wbInfo_2_pipeid_T_10 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 958:26] node _wbInfo_2_rd_T = bits(mem_reg_inst, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 959:37] connect wbInfo[2].rd, _wbInfo_2_rd_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 959:22] node waddr = mux(divSqrt_wen, divSqrt_waddr, wbInfo[0].rd) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 964:18] node wb_cp = mux(divSqrt_wen, divSqrt_cp, wbInfo[0].cp) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 965:18] node wtypeTag = mux(divSqrt_wen, divSqrt_typeTag, wbInfo[0].typeTag) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 966:21] node _wdata_T_23 = eq(wbInfo[0].pipeid, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _wdata_T_24 = mux(_wdata_T_23, ifpu.io.out.bits.data, fpmu.io.out.bits.data) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _wdata_T_25 = eq(wbInfo[0].pipeid, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _wdata_T_26 = mux(_wdata_T_25, sfma.io.out.bits.data, _wdata_T_24) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _wdata_T_27 = eq(wbInfo[0].pipeid, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _wdata_T_28 = mux(_wdata_T_27, dfma.io.out.bits.data, _wdata_T_26) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _wdata_T_29 = mux(divSqrt_wen, divSqrt_wdata, _wdata_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 967:22] node _wdata_opts_bigger_swizzledNaN_T = andr(UInt<20>(0hfffff)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 338:42] node _wdata_opts_bigger_swizzledNaN_T_1 = bits(_wdata_T_29, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 340:8] node _wdata_opts_bigger_swizzledNaN_T_2 = bits(_wdata_T_29, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 342:8] node _wdata_opts_bigger_swizzledNaN_T_3 = bits(_wdata_T_29, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 343:8] node wdata_opts_bigger_swizzledNaN_lo_hi = cat(UInt<20>(0hfffff), _wdata_opts_bigger_swizzledNaN_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 336:26] node wdata_opts_bigger_swizzledNaN_lo = cat(wdata_opts_bigger_swizzledNaN_lo_hi, _wdata_opts_bigger_swizzledNaN_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 336:26] node wdata_opts_bigger_swizzledNaN_hi_lo = cat(UInt<7>(0h7f), _wdata_opts_bigger_swizzledNaN_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 336:26] node wdata_opts_bigger_swizzledNaN_hi_hi = cat(UInt<4>(0hf), _wdata_opts_bigger_swizzledNaN_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 336:26] node wdata_opts_bigger_swizzledNaN_hi = cat(wdata_opts_bigger_swizzledNaN_hi_hi, wdata_opts_bigger_swizzledNaN_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 336:26] node wdata_opts_bigger_swizzledNaN = cat(wdata_opts_bigger_swizzledNaN_hi, wdata_opts_bigger_swizzledNaN_lo) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 336:26] node _wdata_opts_bigger_T = andr(UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node wdata_opts_bigger = mux(_wdata_opts_bigger_T, wdata_opts_bigger_swizzledNaN, UInt<65>(0h1ffffffffffffffff)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 344:8] node wdata_opts_0 = or(wdata_opts_bigger, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 398:14] node _wdata_T_30 = eq(wtypeTag, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node wdata_1 = mux(_wdata_T_30, _wdata_T_29, wdata_opts_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _wexc_T = eq(wbInfo[0].pipeid, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _wexc_T_1 = mux(_wexc_T, ifpu.io.out.bits.exc, fpmu.io.out.bits.exc) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _wexc_T_2 = eq(wbInfo[0].pipeid, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _wexc_T_3 = mux(_wexc_T_2, sfma.io.out.bits.exc, _wexc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _wexc_T_4 = eq(wbInfo[0].pipeid, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node wexc = mux(_wexc_T_4, dfma.io.out.bits.exc, _wexc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _T_23 = eq(wbInfo[0].cp, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 969:10] node _T_24 = bits(wen, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 969:30] node _T_25 = and(_T_23, _T_24) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 969:24] node _T_26 = or(_T_25, divSqrt_wen) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 969:35] when _T_26 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 969:51] node _unswizzled_T_3 = bits(wdata_1, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 381:10] node _unswizzled_T_4 = bits(wdata_1, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 382:10] node _unswizzled_T_5 = bits(wdata_1, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 383:10] node unswizzled_hi_1 = cat(_unswizzled_T_3, _unswizzled_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 380:27] node unswizzled_1 = cat(unswizzled_hi_1, _unswizzled_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 380:27] node _prevOK_T_3 = bits(wdata_1, 64, 60) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:49] node _prevOK_T_4 = andr(_prevOK_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 332:84] node _prevOK_T_5 = eq(_prevOK_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 384:20] node prevOK_1 = or(_prevOK_T_5, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 384:33] node _curOK_T_7 = bits(wdata_1, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node _curOK_T_8 = andr(_curOK_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node _curOK_T_9 = eq(_curOK_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 385:19] node _curOK_T_10 = bits(wdata_1, 60, 60) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 385:35] node _curOK_T_11 = bits(wdata_1, 51, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 385:60] node _curOK_T_12 = andr(_curOK_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 385:96] node _curOK_T_13 = eq(_curOK_T_10, _curOK_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 385:55] node curOK_1 = or(_curOK_T_9, _curOK_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 385:31] node _T_27 = and(prevOK_1, curOK_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 386:14] node _T_28 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 970:11] node _T_29 = eq(_T_28, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 970:11] when _T_29 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 970:11] node _T_30 = eq(_T_27, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 970:11] when _T_30 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 970:11] printf(clock, UInt<1>(0h1), "Assertion failed\n at FPU.scala:970 assert(consistent(wdata))\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 970:11] assert(clock, _T_27, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 970:11] infer mport MPORT_1 = regfile[waddr], clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 971:12] connect MPORT_1, wdata_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 971:20] connect frfWriteBundle_1.wrdst, waddr @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 975:29] connect frfWriteBundle_1.wrenf, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 976:29] node frfWriteBundle_1_wrdata_unrecoded_rawIn_exp = bits(wdata_1, 63, 52) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _frfWriteBundle_1_wrdata_unrecoded_rawIn_isZero_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn_exp, 11, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node frfWriteBundle_1_wrdata_unrecoded_rawIn_isZero = eq(_frfWriteBundle_1_wrdata_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _frfWriteBundle_1_wrdata_unrecoded_rawIn_isSpecial_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn_exp, 11, 10) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node frfWriteBundle_1_wrdata_unrecoded_rawIn_isSpecial = eq(_frfWriteBundle_1_wrdata_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire frfWriteBundle_1_wrdata_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isNaN_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isNaN_T_1 = and(frfWriteBundle_1_wrdata_unrecoded_rawIn_isSpecial, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect frfWriteBundle_1_wrdata_unrecoded_rawIn.isNaN, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isInf_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn_exp, 9, 9) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isInf_T_1 = eq(_frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isInf_T_2 = and(frfWriteBundle_1_wrdata_unrecoded_rawIn_isSpecial, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect frfWriteBundle_1_wrdata_unrecoded_rawIn.isInf, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect frfWriteBundle_1_wrdata_unrecoded_rawIn.isZero, frfWriteBundle_1_wrdata_unrecoded_rawIn_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sign_T = bits(wdata_1, 64, 64) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect frfWriteBundle_1_wrdata_unrecoded_rawIn.sign, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sExp_T = cvt(frfWriteBundle_1_wrdata_unrecoded_rawIn_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect frfWriteBundle_1_wrdata_unrecoded_rawIn.sExp, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T = eq(frfWriteBundle_1_wrdata_unrecoded_rawIn_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T_2 = bits(wdata_1, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T_3 = cat(_frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T_1, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect frfWriteBundle_1_wrdata_unrecoded_rawIn.sig, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node frfWriteBundle_1_wrdata_unrecoded_isSubnormal = lt(frfWriteBundle_1_wrdata_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 51:38] node _frfWriteBundle_1_wrdata_unrecoded_denormShiftDist_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn.sExp, 5, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:47] node _frfWriteBundle_1_wrdata_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _frfWriteBundle_1_wrdata_unrecoded_denormShiftDist_T) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node frfWriteBundle_1_wrdata_unrecoded_denormShiftDist = tail(_frfWriteBundle_1_wrdata_unrecoded_denormShiftDist_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node _frfWriteBundle_1_wrdata_unrecoded_denormFract_T = shr(frfWriteBundle_1_wrdata_unrecoded_rawIn.sig, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:38] node _frfWriteBundle_1_wrdata_unrecoded_denormFract_T_1 = dshr(_frfWriteBundle_1_wrdata_unrecoded_denormFract_T, frfWriteBundle_1_wrdata_unrecoded_denormShiftDist) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:42] node frfWriteBundle_1_wrdata_unrecoded_denormFract = bits(_frfWriteBundle_1_wrdata_unrecoded_denormFract_T_1, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:60] node _frfWriteBundle_1_wrdata_unrecoded_expOut_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn.sExp, 10, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:27] node _frfWriteBundle_1_wrdata_unrecoded_expOut_T_1 = sub(_frfWriteBundle_1_wrdata_unrecoded_expOut_T, UInt<11>(0h401)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _frfWriteBundle_1_wrdata_unrecoded_expOut_T_2 = tail(_frfWriteBundle_1_wrdata_unrecoded_expOut_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _frfWriteBundle_1_wrdata_unrecoded_expOut_T_3 = mux(frfWriteBundle_1_wrdata_unrecoded_isSubnormal, UInt<1>(0h0), _frfWriteBundle_1_wrdata_unrecoded_expOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 56:16] node _frfWriteBundle_1_wrdata_unrecoded_expOut_T_4 = or(frfWriteBundle_1_wrdata_unrecoded_rawIn.isNaN, frfWriteBundle_1_wrdata_unrecoded_rawIn.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:44] node _frfWriteBundle_1_wrdata_unrecoded_expOut_T_5 = mux(_frfWriteBundle_1_wrdata_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:21] node frfWriteBundle_1_wrdata_unrecoded_expOut = or(_frfWriteBundle_1_wrdata_unrecoded_expOut_T_3, _frfWriteBundle_1_wrdata_unrecoded_expOut_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:15] node _frfWriteBundle_1_wrdata_unrecoded_fractOut_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn.sig, 51, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:48] node _frfWriteBundle_1_wrdata_unrecoded_fractOut_T_1 = mux(frfWriteBundle_1_wrdata_unrecoded_rawIn.isInf, UInt<1>(0h0), _frfWriteBundle_1_wrdata_unrecoded_fractOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:20] node frfWriteBundle_1_wrdata_unrecoded_fractOut = mux(frfWriteBundle_1_wrdata_unrecoded_isSubnormal, frfWriteBundle_1_wrdata_unrecoded_denormFract, _frfWriteBundle_1_wrdata_unrecoded_fractOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 62:16] node frfWriteBundle_1_wrdata_unrecoded_hi = cat(frfWriteBundle_1_wrdata_unrecoded_rawIn.sign, frfWriteBundle_1_wrdata_unrecoded_expOut) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node frfWriteBundle_1_wrdata_unrecoded = cat(frfWriteBundle_1_wrdata_unrecoded_hi, frfWriteBundle_1_wrdata_unrecoded_fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node _frfWriteBundle_1_wrdata_prevRecoded_T = bits(wdata_1, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 442:10] node _frfWriteBundle_1_wrdata_prevRecoded_T_1 = bits(wdata_1, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 443:10] node _frfWriteBundle_1_wrdata_prevRecoded_T_2 = bits(wdata_1, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 444:10] node frfWriteBundle_1_wrdata_prevRecoded_hi = cat(_frfWriteBundle_1_wrdata_prevRecoded_T, _frfWriteBundle_1_wrdata_prevRecoded_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 441:28] node frfWriteBundle_1_wrdata_prevRecoded = cat(frfWriteBundle_1_wrdata_prevRecoded_hi, _frfWriteBundle_1_wrdata_prevRecoded_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 441:28] node frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_exp = bits(frfWriteBundle_1_wrdata_prevRecoded, 31, 23) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 51:21] node _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_isZero_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_exp, 8, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:28] node frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_isZero = eq(_frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 52:53] node _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_isSpecial_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_exp, 8, 7) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:28] node frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_isSpecial = eq(_frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 53:53] wire frfWriteBundle_1_wrdata_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 55:23] node _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_isNaN_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_exp, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:41] node _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_isNaN_T_1 = and(frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_isSpecial, _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_isNaN_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:33] connect frfWriteBundle_1_wrdata_prevUnrecoded_rawIn.isNaN, _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_isNaN_T_1 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 56:20] node _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_isInf_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_exp, 6, 6) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:41] node _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:36] node _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_isInf_T_2 = and(frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_isSpecial, _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_isInf_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:33] connect frfWriteBundle_1_wrdata_prevUnrecoded_rawIn.isInf, _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_isInf_T_2 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 57:20] connect frfWriteBundle_1_wrdata_prevUnrecoded_rawIn.isZero, frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_isZero @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 58:20] node _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_sign_T = bits(frfWriteBundle_1_wrdata_prevRecoded, 32, 32) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:25] connect frfWriteBundle_1_wrdata_prevUnrecoded_rawIn.sign, _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_sign_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 59:20] node _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_sExp_T = cvt(frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_exp) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:27] connect frfWriteBundle_1_wrdata_prevUnrecoded_rawIn.sExp, _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_sExp_T @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 60:20] node _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_sig_T = eq(frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:35] node _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_sig_T) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:32] node _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_sig_T_2 = bits(frfWriteBundle_1_wrdata_prevRecoded, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:49] node _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_sig_T_3 = cat(_frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_sig_T_1, _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_sig_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:44] connect frfWriteBundle_1_wrdata_prevUnrecoded_rawIn.sig, _frfWriteBundle_1_wrdata_prevUnrecoded_rawIn_out_sig_T_3 @[dependencies/hardfloat/hardfloat/src/main/scala/rawFloatFromRecFN.scala 61:20] node frfWriteBundle_1_wrdata_prevUnrecoded_isSubnormal = lt(frfWriteBundle_1_wrdata_prevUnrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 51:38] node _frfWriteBundle_1_wrdata_prevUnrecoded_denormShiftDist_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_rawIn.sExp, 4, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:47] node _frfWriteBundle_1_wrdata_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _frfWriteBundle_1_wrdata_prevUnrecoded_denormShiftDist_T) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node frfWriteBundle_1_wrdata_prevUnrecoded_denormShiftDist = tail(_frfWriteBundle_1_wrdata_prevUnrecoded_denormShiftDist_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 52:35] node _frfWriteBundle_1_wrdata_prevUnrecoded_denormFract_T = shr(frfWriteBundle_1_wrdata_prevUnrecoded_rawIn.sig, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:38] node _frfWriteBundle_1_wrdata_prevUnrecoded_denormFract_T_1 = dshr(_frfWriteBundle_1_wrdata_prevUnrecoded_denormFract_T, frfWriteBundle_1_wrdata_prevUnrecoded_denormShiftDist) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:42] node frfWriteBundle_1_wrdata_prevUnrecoded_denormFract = bits(_frfWriteBundle_1_wrdata_prevUnrecoded_denormFract_T_1, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 53:60] node _frfWriteBundle_1_wrdata_prevUnrecoded_expOut_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_rawIn.sExp, 7, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:27] node _frfWriteBundle_1_wrdata_prevUnrecoded_expOut_T_1 = sub(_frfWriteBundle_1_wrdata_prevUnrecoded_expOut_T, UInt<8>(0h81)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _frfWriteBundle_1_wrdata_prevUnrecoded_expOut_T_2 = tail(_frfWriteBundle_1_wrdata_prevUnrecoded_expOut_T_1, 1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 58:45] node _frfWriteBundle_1_wrdata_prevUnrecoded_expOut_T_3 = mux(frfWriteBundle_1_wrdata_prevUnrecoded_isSubnormal, UInt<1>(0h0), _frfWriteBundle_1_wrdata_prevUnrecoded_expOut_T_2) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 56:16] node _frfWriteBundle_1_wrdata_prevUnrecoded_expOut_T_4 = or(frfWriteBundle_1_wrdata_prevUnrecoded_rawIn.isNaN, frfWriteBundle_1_wrdata_prevUnrecoded_rawIn.isInf) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:44] node _frfWriteBundle_1_wrdata_prevUnrecoded_expOut_T_5 = mux(_frfWriteBundle_1_wrdata_prevUnrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:21] node frfWriteBundle_1_wrdata_prevUnrecoded_expOut = or(_frfWriteBundle_1_wrdata_prevUnrecoded_expOut_T_3, _frfWriteBundle_1_wrdata_prevUnrecoded_expOut_T_5) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 60:15] node _frfWriteBundle_1_wrdata_prevUnrecoded_fractOut_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_rawIn.sig, 22, 0) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:48] node _frfWriteBundle_1_wrdata_prevUnrecoded_fractOut_T_1 = mux(frfWriteBundle_1_wrdata_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _frfWriteBundle_1_wrdata_prevUnrecoded_fractOut_T) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 64:20] node frfWriteBundle_1_wrdata_prevUnrecoded_fractOut = mux(frfWriteBundle_1_wrdata_prevUnrecoded_isSubnormal, frfWriteBundle_1_wrdata_prevUnrecoded_denormFract, _frfWriteBundle_1_wrdata_prevUnrecoded_fractOut_T_1) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 62:16] node frfWriteBundle_1_wrdata_prevUnrecoded_hi = cat(frfWriteBundle_1_wrdata_prevUnrecoded_rawIn.sign, frfWriteBundle_1_wrdata_prevUnrecoded_expOut) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node frfWriteBundle_1_wrdata_prevUnrecoded = cat(frfWriteBundle_1_wrdata_prevUnrecoded_hi, frfWriteBundle_1_wrdata_prevUnrecoded_fractOut) @[dependencies/hardfloat/hardfloat/src/main/scala/fNFromRecFN.scala 66:12] node _frfWriteBundle_1_wrdata_T = shr(frfWriteBundle_1_wrdata_unrecoded, 32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:21] node _frfWriteBundle_1_wrdata_T_1 = bits(wdata_1, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node _frfWriteBundle_1_wrdata_T_2 = andr(_frfWriteBundle_1_wrdata_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node _frfWriteBundle_1_wrdata_T_3 = bits(frfWriteBundle_1_wrdata_unrecoded, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:81] node _frfWriteBundle_1_wrdata_T_4 = mux(_frfWriteBundle_1_wrdata_T_2, frfWriteBundle_1_wrdata_prevUnrecoded, _frfWriteBundle_1_wrdata_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:44] node _frfWriteBundle_1_wrdata_T_5 = cat(_frfWriteBundle_1_wrdata_T, _frfWriteBundle_1_wrdata_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 446:10] connect frfWriteBundle_1.wrdata, _frfWriteBundle_1_wrdata_T_5 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 977:30] node _T_31 = bits(wen, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 983:22] node _T_32 = or(_T_31, divSqrt_wen) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 983:26] node _T_33 = and(wb_cp, _T_32) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 983:15] when _T_33 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 983:43] connect io.cp_resp.bits.data, wdata_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 984:26] connect io.cp_resp.valid, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 985:22] node _T_34 = eq(io.cp_req.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 988:10] node _T_35 = or(_T_34, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 988:27] node _T_36 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 988:9] node _T_37 = eq(_T_36, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 988:9] when _T_37 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 988:9] node _T_38 = eq(_T_35, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 988:9] when _T_38 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 988:9] printf(clock, UInt<1>(0h1), "Assertion failed: FPU only supports coprocessor if FMA pipes have uniform latency List(2, 2, 3, 4)\n at FPU.scala:988 assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,\n") : printf_2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 988:9] assert(clock, _T_35, UInt<1>(0h1), "") : assert_2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 988:9] node _io_cp_req_ready_T = neq(wen, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 992:45] node _io_cp_req_ready_T_1 = and(cp_ctrl.toint, _io_cp_req_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 992:38] node _io_cp_req_ready_T_2 = eq(_io_cp_req_ready_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 992:22] node _io_cp_req_ready_T_3 = eq(divSqrt_inFlight, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 992:57] node _io_cp_req_ready_T_4 = and(_io_cp_req_ready_T_2, _io_cp_req_ready_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 992:54] connect io.cp_req.ready, _io_cp_req_ready_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 992:19] node wb_toint_valid = and(wb_reg_valid, wb_ctrl.toint) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 994:37] reg wb_toint_exc : UInt<5>, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 995:31] when mem_ctrl.toint : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 995:31] connect wb_toint_exc, fpiu.io.out.bits.exc @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 995:31] node _io_fcsr_flags_valid_T = or(wb_toint_valid, divSqrt_wen) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 996:41] node _io_fcsr_flags_valid_T_1 = bits(wen, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 996:62] node _io_fcsr_flags_valid_T_2 = or(_io_fcsr_flags_valid_T, _io_fcsr_flags_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 996:56] connect io.fcsr_flags.valid, _io_fcsr_flags_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 996:23] node _io_fcsr_flags_bits_T = mux(wb_toint_valid, wb_toint_exc, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 998:8] node _io_fcsr_flags_bits_T_1 = mux(divSqrt_wen, divSqrt_flags, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 999:8] node _io_fcsr_flags_bits_T_2 = or(_io_fcsr_flags_bits_T, _io_fcsr_flags_bits_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 998:44] node _io_fcsr_flags_bits_T_3 = bits(wen, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1000:12] node _io_fcsr_flags_bits_T_4 = mux(_io_fcsr_flags_bits_T_3, wexc, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1000:8] node _io_fcsr_flags_bits_T_5 = or(_io_fcsr_flags_bits_T_2, _io_fcsr_flags_bits_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 999:42] connect io.fcsr_flags.bits, _io_fcsr_flags_bits_T_5 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 997:22] node _divSqrt_write_port_busy_T = or(mem_ctrl.div, mem_ctrl.sqrt) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1002:47] node _divSqrt_write_port_busy_T_1 = orr(wen) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1002:72] node divSqrt_write_port_busy = and(_divSqrt_write_port_busy_T, _divSqrt_write_port_busy_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1002:65] node _io_fcsr_rdy_T = and(ex_reg_valid, ex_ctrl.wflags) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1003:33] node _io_fcsr_rdy_T_1 = and(mem_reg_valid, mem_ctrl.wflags) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1003:68] node _io_fcsr_rdy_T_2 = or(_io_fcsr_rdy_T, _io_fcsr_rdy_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1003:51] node _io_fcsr_rdy_T_3 = and(wb_reg_valid, wb_ctrl.toint) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1003:103] node _io_fcsr_rdy_T_4 = or(_io_fcsr_rdy_T_2, _io_fcsr_rdy_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1003:87] node _io_fcsr_rdy_T_5 = orr(wen) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1003:127] node _io_fcsr_rdy_T_6 = or(_io_fcsr_rdy_T_4, _io_fcsr_rdy_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1003:120] node _io_fcsr_rdy_T_7 = or(_io_fcsr_rdy_T_6, divSqrt_inFlight) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1003:131] node _io_fcsr_rdy_T_8 = eq(_io_fcsr_rdy_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1003:18] connect io.fcsr_rdy, _io_fcsr_rdy_T_8 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1003:15] node _io_nack_mem_T = or(write_port_busy, divSqrt_write_port_busy) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1004:35] node _io_nack_mem_T_1 = or(_io_nack_mem_T, divSqrt_inFlight) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1004:62] node _io_nack_mem_T_2 = or(_io_nack_mem_T_1, mem_cp_valid) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1004:82] connect io.nack_mem, _io_nack_mem_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1004:15] connect io.dec, id_ctrl @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1005:10] node _io_sboard_set_T = eq(wb_cp_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1007:36] node _io_sboard_set_T_1 = and(wb_reg_valid, _io_sboard_set_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1007:33] node _io_sboard_set_T_2 = eq(mem_ctrl.typeTagOut, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 917:78] node _io_sboard_set_T_3 = and(mem_ctrl.fma, _io_sboard_set_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 917:62] node _io_sboard_set_T_4 = or(UInt<1>(0h0), _io_sboard_set_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1006:119] node _io_sboard_set_T_5 = or(_io_sboard_set_T_4, mem_ctrl.div) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1007:95] node _io_sboard_set_T_6 = or(_io_sboard_set_T_5, mem_ctrl.sqrt) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1007:111] node _io_sboard_set_T_7 = or(_io_sboard_set_T_6, mem_ctrl.vec) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1007:128] reg io_sboard_set_REG : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1007:59] connect io_sboard_set_REG, _io_sboard_set_T_7 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1007:59] node _io_sboard_set_T_8 = and(_io_sboard_set_T_1, io_sboard_set_REG) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1007:49] connect io.sboard_set, _io_sboard_set_T_8 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1007:17] node _io_sboard_clr_T = eq(wb_cp_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1008:20] node _io_sboard_clr_T_1 = bits(wen, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1008:56] node _io_sboard_clr_T_2 = eq(wbInfo[0].pipeid, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1008:99] node _io_sboard_clr_T_3 = or(UInt<1>(0h0), _io_sboard_clr_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1006:119] node _io_sboard_clr_T_4 = and(_io_sboard_clr_T_1, _io_sboard_clr_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1008:60] node _io_sboard_clr_T_5 = or(divSqrt_wen, _io_sboard_clr_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1008:49] node _io_sboard_clr_T_6 = and(_io_sboard_clr_T, _io_sboard_clr_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1008:33] connect io.sboard_clr, _io_sboard_clr_T_6 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1008:17] connect io.sboard_clra, waddr @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1009:18] node _T_39 = and(io.sboard_clr, load_wb) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1010:24] node _io_illegal_rm_T = bits(io.inst, 14, 12) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1012:27] node _io_illegal_rm_T_1 = eq(_io_illegal_rm_T, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_illegal_rm_T_2 = eq(_io_illegal_rm_T, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_illegal_rm_T_3 = or(_io_illegal_rm_T_1, _io_illegal_rm_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_illegal_rm_T_4 = bits(io.inst, 14, 12) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1012:63] node _io_illegal_rm_T_5 = eq(_io_illegal_rm_T_4, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1012:71] node _io_illegal_rm_T_6 = geq(io.fcsr_rm, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1012:93] node _io_illegal_rm_T_7 = and(_io_illegal_rm_T_5, _io_illegal_rm_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1012:79] node _io_illegal_rm_T_8 = or(_io_illegal_rm_T_3, _io_illegal_rm_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1012:53] connect io.illegal_rm, _io_illegal_rm_T_8 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1012:17] node _divSqrt_inValid_T = or(mem_ctrl.div, mem_ctrl.sqrt) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1015:58] node _divSqrt_inValid_T_1 = and(mem_reg_valid, _divSqrt_inValid_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1015:41] node _divSqrt_inValid_T_2 = eq(divSqrt_inFlight, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1015:79] node divSqrt_inValid = and(_divSqrt_inValid_T_1, _divSqrt_inValid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1015:76] node _divSqrt_killed_T = and(divSqrt_inValid, killm) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1016:50] regreset divSqrt_killed : UInt<1>, clock, reset, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1016:33] connect divSqrt_killed, _divSqrt_killed_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1016:33] when divSqrt_inValid : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1017:28] node _divSqrt_waddr_T = bits(mem_reg_inst, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1018:36] connect divSqrt_waddr, _divSqrt_waddr_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1018:21] connect divSqrt_cp, mem_cp_valid @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1019:18] node _T_40 = and(divSqrt_inFlight, divSqrt_killed) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1022:29] node _T_41 = and(divSqrt_inFlight, mem_reg_valid) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1023:29] node _T_42 = or(mem_ctrl.div, mem_ctrl.sqrt) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1023:63] node _T_43 = and(_T_41, _T_42) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1023:46] node _T_44 = and(mem_reg_valid, divSqrt_write_port_busy) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1024:26] inst divSqrt of DivSqrtRecFN_small @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1028:55] connect divSqrt.clock, clock connect divSqrt.reset, divSqrt_killed node _divSqrt_io_inValid_T = eq(mem_ctrl.typeTagOut, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1029:52] node _divSqrt_io_inValid_T_1 = and(divSqrt_inValid, _divSqrt_io_inValid_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1029:45] connect divSqrt.io.inValid, _divSqrt_io_inValid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1029:26] connect divSqrt.io.sqrtOp, mem_ctrl.sqrt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1030:25] node divSqrt_io_a_sign = bits(fpiu.io.out.bits.in.in1, 64, 64) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 274:17] node divSqrt_io_a_fractIn = bits(fpiu.io.out.bits.in.in1, 51, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 275:20] node divSqrt_io_a_expIn = bits(fpiu.io.out.bits.in.in1, 63, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 276:18] node _divSqrt_io_a_fractOut_T = shl(divSqrt_io_a_fractIn, 24) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:28] node divSqrt_io_a_fractOut = shr(_divSqrt_io_a_fractOut_T, 53) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:38] node divSqrt_io_a_expOut_expCode = bits(divSqrt_io_a_expIn, 11, 9) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 279:26] node _divSqrt_io_a_expOut_commonCase_T = add(divSqrt_io_a_expIn, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _divSqrt_io_a_expOut_commonCase_T_1 = tail(_divSqrt_io_a_expOut_commonCase_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _divSqrt_io_a_expOut_commonCase_T_2 = sub(_divSqrt_io_a_expOut_commonCase_T_1, UInt<12>(0h800)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node divSqrt_io_a_expOut_commonCase = tail(_divSqrt_io_a_expOut_commonCase_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node _divSqrt_io_a_expOut_T = eq(divSqrt_io_a_expOut_expCode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:19] node _divSqrt_io_a_expOut_T_1 = geq(divSqrt_io_a_expOut_expCode, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:38] node _divSqrt_io_a_expOut_T_2 = or(_divSqrt_io_a_expOut_T, _divSqrt_io_a_expOut_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:27] node _divSqrt_io_a_expOut_T_3 = bits(divSqrt_io_a_expOut_commonCase, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:69] node _divSqrt_io_a_expOut_T_4 = cat(divSqrt_io_a_expOut_expCode, _divSqrt_io_a_expOut_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:49] node _divSqrt_io_a_expOut_T_5 = bits(divSqrt_io_a_expOut_commonCase, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:97] node divSqrt_io_a_expOut = mux(_divSqrt_io_a_expOut_T_2, _divSqrt_io_a_expOut_T_4, _divSqrt_io_a_expOut_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:10] node divSqrt_io_a_hi = cat(divSqrt_io_a_sign, divSqrt_io_a_expOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node _divSqrt_io_a_T = cat(divSqrt_io_a_hi, divSqrt_io_a_fractOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] connect divSqrt.io.a, _divSqrt_io_a_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1031:20] node divSqrt_io_b_sign = bits(fpiu.io.out.bits.in.in2, 64, 64) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 274:17] node divSqrt_io_b_fractIn = bits(fpiu.io.out.bits.in.in2, 51, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 275:20] node divSqrt_io_b_expIn = bits(fpiu.io.out.bits.in.in2, 63, 52) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 276:18] node _divSqrt_io_b_fractOut_T = shl(divSqrt_io_b_fractIn, 24) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:28] node divSqrt_io_b_fractOut = shr(_divSqrt_io_b_fractOut_T, 53) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 277:38] node divSqrt_io_b_expOut_expCode = bits(divSqrt_io_b_expIn, 11, 9) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 279:26] node _divSqrt_io_b_expOut_commonCase_T = add(divSqrt_io_b_expIn, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _divSqrt_io_b_expOut_commonCase_T_1 = tail(_divSqrt_io_b_expOut_commonCase_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:31] node _divSqrt_io_b_expOut_commonCase_T_2 = sub(_divSqrt_io_b_expOut_commonCase_T_1, UInt<12>(0h800)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node divSqrt_io_b_expOut_commonCase = tail(_divSqrt_io_b_expOut_commonCase_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 280:50] node _divSqrt_io_b_expOut_T = eq(divSqrt_io_b_expOut_expCode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:19] node _divSqrt_io_b_expOut_T_1 = geq(divSqrt_io_b_expOut_expCode, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:38] node _divSqrt_io_b_expOut_T_2 = or(_divSqrt_io_b_expOut_T, _divSqrt_io_b_expOut_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:27] node _divSqrt_io_b_expOut_T_3 = bits(divSqrt_io_b_expOut_commonCase, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:69] node _divSqrt_io_b_expOut_T_4 = cat(divSqrt_io_b_expOut_expCode, _divSqrt_io_b_expOut_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:49] node _divSqrt_io_b_expOut_T_5 = bits(divSqrt_io_b_expOut_commonCase, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:97] node divSqrt_io_b_expOut = mux(_divSqrt_io_b_expOut_T_2, _divSqrt_io_b_expOut_T_4, _divSqrt_io_b_expOut_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 281:10] node divSqrt_io_b_hi = cat(divSqrt_io_b_sign, divSqrt_io_b_expOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] node _divSqrt_io_b_T = cat(divSqrt_io_b_hi, divSqrt_io_b_fractOut) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 283:8] connect divSqrt.io.b, _divSqrt_io_b_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1032:20] connect divSqrt.io.roundingMode, fpiu.io.out.bits.in.rm @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1033:31] connect divSqrt.io.detectTininess, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1034:33] node _T_45 = eq(divSqrt.io.inReady, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1036:13] when _T_45 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1036:34] connect divSqrt_inFlight, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1036:53] node _T_46 = or(divSqrt.io.outValid_div, divSqrt.io.outValid_sqrt) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1038:37] when _T_46 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1038:66] node _divSqrt_wen_T = eq(divSqrt_killed, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1039:24] connect divSqrt_wen, _divSqrt_wen_T @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1039:21] connect divSqrt_wdata, divSqrt.io.out @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1040:23] connect divSqrt_flags, divSqrt.io.exceptionFlags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1041:23] connect divSqrt_typeTag, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1042:25] inst divSqrt_1 of DivSqrtRecFN_small_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1028:55] connect divSqrt_1.clock, clock connect divSqrt_1.reset, divSqrt_killed node _divSqrt_io_inValid_T_2 = eq(mem_ctrl.typeTagOut, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1029:52] node _divSqrt_io_inValid_T_3 = and(divSqrt_inValid, _divSqrt_io_inValid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1029:45] connect divSqrt_1.io.inValid, _divSqrt_io_inValid_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1029:26] connect divSqrt_1.io.sqrtOp, mem_ctrl.sqrt @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1030:25] connect divSqrt_1.io.a, fpiu.io.out.bits.in.in1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1031:20] connect divSqrt_1.io.b, fpiu.io.out.bits.in.in2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1032:20] connect divSqrt_1.io.roundingMode, fpiu.io.out.bits.in.rm @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1033:31] connect divSqrt_1.io.detectTininess, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1034:33] node _T_47 = eq(divSqrt_1.io.inReady, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1036:13] when _T_47 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1036:34] connect divSqrt_inFlight, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1036:53] node _T_48 = or(divSqrt_1.io.outValid_div, divSqrt_1.io.outValid_sqrt) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1038:37] when _T_48 : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1038:66] node _divSqrt_wen_T_1 = eq(divSqrt_killed, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1039:24] connect divSqrt_wen, _divSqrt_wen_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1039:21] node _divSqrt_wdata_maskedNaN_T = not(UInt<65>(0h1010000000000000)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 413:27] node divSqrt_wdata_maskedNaN = and(divSqrt_1.io.out, _divSqrt_wdata_maskedNaN_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 413:25] node _divSqrt_wdata_T = bits(divSqrt_1.io.out, 63, 61) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:25] node _divSqrt_wdata_T_1 = andr(_divSqrt_wdata_T) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 249:56] node _divSqrt_wdata_T_2 = mux(_divSqrt_wdata_T_1, divSqrt_wdata_maskedNaN, divSqrt_1.io.out) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 414:10] connect divSqrt_wdata, _divSqrt_wdata_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1040:23] connect divSqrt_flags, divSqrt_1.io.exceptionFlags @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1041:23] connect divSqrt_typeTag, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1042:25] when divSqrt_killed : @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1046:27] connect divSqrt_inFlight, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1046:46] node _clock_en_reg_T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1052:19] node _clock_en_reg_T_1 = or(_clock_en_reg_T, io.keep_clock_enabled) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1052:37] node _clock_en_reg_T_2 = or(_clock_en_reg_T_1, io.valid) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1053:27] node _clock_en_reg_T_3 = or(_clock_en_reg_T_2, req_valid) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1054:14] node _clock_en_reg_T_4 = or(_clock_en_reg_T_3, mem_reg_valid) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1055:15] node _clock_en_reg_T_5 = or(_clock_en_reg_T_4, mem_cp_valid) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1056:19] node _clock_en_reg_T_6 = or(_clock_en_reg_T_5, wb_reg_valid) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1056:35] node _clock_en_reg_T_7 = or(_clock_en_reg_T_6, wb_cp_valid) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1057:18] node _clock_en_reg_T_8 = orr(wen) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1058:9] node _clock_en_reg_T_9 = or(_clock_en_reg_T_7, _clock_en_reg_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1057:33] node _clock_en_reg_T_10 = or(_clock_en_reg_T_9, divSqrt_inFlight) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1058:13] node _clock_en_reg_T_11 = or(_clock_en_reg_T_10, io.ll_resp_val) @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1058:33] connect clock_en_reg, _clock_en_reg_T_11 @[hardware/upstream/rocket-chip/src/main/scala/tile/FPU.scala 1052:16] module HellaCacheArbiter : @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 10:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 10:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 10:7] output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<34>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<34>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 12:14] reg s1_id : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 20:20] reg s2_id : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 21:24] connect s2_id, s1_id @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 21:24] node _io_mem_keep_clock_enabled_T = or(io.requestor[0].keep_clock_enabled, io.requestor[1].keep_clock_enabled) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 23:81] connect io.mem.keep_clock_enabled, _io_mem_keep_clock_enabled_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 23:31] node _io_mem_req_valid_T = or(io.requestor[0].req.valid, io.requestor[1].req.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 25:63] connect io.mem.req.valid, _io_mem_req_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 25:22] connect io.requestor[0].req.ready, io.mem.req.ready @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 26:31] node _io_requestor_1_req_ready_T = eq(io.requestor[0].req.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 28:67] node _io_requestor_1_req_ready_T_1 = and(io.requestor[0].req.ready, _io_requestor_1_req_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 28:64] connect io.requestor[1].req.ready, _io_requestor_1_req_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 28:33] connect io.mem.req.bits, io.requestor[1].req.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 33:25] node _io_mem_req_bits_tag_T = cat(io.requestor[1].req.bits.tag, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 34:35] connect io.mem.req.bits.tag, _io_mem_req_bits_tag_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 34:29] connect s1_id, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 35:15] connect io.mem.s1_kill, io.requestor[1].s1_kill @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 38:24] connect io.mem.s1_data, io.requestor[1].s1_data @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 39:24] connect io.mem.s2_kill, io.requestor[1].s2_kill @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 42:24] when io.requestor[0].req.valid : @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 50:26] connect io.mem.req.bits, io.requestor[0].req.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 33:25] node _io_mem_req_bits_tag_T_1 = cat(io.requestor[0].req.bits.tag, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 34:35] connect io.mem.req.bits.tag, _io_mem_req_bits_tag_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 34:29] connect s1_id, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 35:15] node _T = eq(s1_id, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 51:21] when _T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 51:30] connect io.mem.s1_kill, io.requestor[0].s1_kill @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 38:24] connect io.mem.s1_data, io.requestor[0].s1_data @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 39:24] node _T_1 = eq(s2_id, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 52:21] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 52:30] connect io.mem.s2_kill, io.requestor[0].s2_kill @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 42:24] node _tag_hit_T = bits(io.mem.resp.bits.tag, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 60:41] node tag_hit = eq(_tag_hit_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 60:57] node _io_requestor_0_resp_valid_T = and(io.mem.resp.valid, tag_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 61:39] connect io.requestor[0].resp.valid, _io_requestor_0_resp_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 61:18] connect io.requestor[0].s2_xcpt, io.mem.s2_xcpt @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 62:31] connect io.requestor[0].s2_gpa, io.mem.s2_gpa @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 63:30] connect io.requestor[0].s2_gpa_is_pte, io.mem.s2_gpa_is_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 64:37] connect io.requestor[0].ordered, io.mem.ordered @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 65:31] connect io.requestor[0].store_pending, io.mem.store_pending @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 66:37] connect io.requestor[0].perf, io.mem.perf @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 67:28] node _io_requestor_0_s2_nack_T = eq(s2_id, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 68:58] node _io_requestor_0_s2_nack_T_1 = and(io.mem.s2_nack, _io_requestor_0_s2_nack_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 68:49] connect io.requestor[0].s2_nack, _io_requestor_0_s2_nack_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 68:31] connect io.requestor[0].s2_nack_cause_raw, io.mem.s2_nack_cause_raw @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 69:41] connect io.requestor[0].s2_uncached, io.mem.s2_uncached @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 70:35] connect io.requestor[0].s2_paddr, io.mem.s2_paddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 71:32] connect io.requestor[0].clock_enabled, io.mem.clock_enabled @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 72:37] connect io.requestor[0].resp.bits, io.mem.resp.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 73:17] node _io_requestor_0_resp_bits_tag_T = shr(io.mem.resp.bits.tag, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 74:45] connect io.requestor[0].resp.bits.tag, _io_requestor_0_resp_bits_tag_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 74:21] connect io.requestor[0].replay_next, io.mem.replay_next @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 76:35] node _tag_hit_T_1 = bits(io.mem.resp.bits.tag, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 60:41] node tag_hit_1 = eq(_tag_hit_T_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 60:57] node _io_requestor_1_resp_valid_T = and(io.mem.resp.valid, tag_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 61:39] connect io.requestor[1].resp.valid, _io_requestor_1_resp_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 61:18] connect io.requestor[1].s2_xcpt, io.mem.s2_xcpt @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 62:31] connect io.requestor[1].s2_gpa, io.mem.s2_gpa @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 63:30] connect io.requestor[1].s2_gpa_is_pte, io.mem.s2_gpa_is_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 64:37] connect io.requestor[1].ordered, io.mem.ordered @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 65:31] connect io.requestor[1].store_pending, io.mem.store_pending @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 66:37] connect io.requestor[1].perf, io.mem.perf @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 67:28] node _io_requestor_1_s2_nack_T = eq(s2_id, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 68:58] node _io_requestor_1_s2_nack_T_1 = and(io.mem.s2_nack, _io_requestor_1_s2_nack_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 68:49] connect io.requestor[1].s2_nack, _io_requestor_1_s2_nack_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 68:31] connect io.requestor[1].s2_nack_cause_raw, io.mem.s2_nack_cause_raw @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 69:41] connect io.requestor[1].s2_uncached, io.mem.s2_uncached @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 70:35] connect io.requestor[1].s2_paddr, io.mem.s2_paddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 71:32] connect io.requestor[1].clock_enabled, io.mem.clock_enabled @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 72:37] connect io.requestor[1].resp.bits, io.mem.resp.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 73:17] node _io_requestor_1_resp_bits_tag_T = shr(io.mem.resp.bits.tag, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 74:45] connect io.requestor[1].resp.bits.tag, _io_requestor_1_resp_bits_tag_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 74:21] connect io.requestor[1].replay_next, io.mem.replay_next @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala 76:35] module Arbiter2_Valid_PTWReq : @[src/main/scala/chisel3/util/Arbiter.scala 133:7] input clock : Clock @[src/main/scala/chisel3/util/Arbiter.scala 133:7] input reset : Reset @[src/main/scala/chisel3/util/Arbiter.scala 133:7] output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<21>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}[2], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<21>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, chosen : UInt<1>} @[src/main/scala/chisel3/util/Arbiter.scala 140:14] connect io.chosen, UInt<1>(0h1) @[src/main/scala/chisel3/util/Arbiter.scala 142:13] connect io.out.bits, io.in[1].bits @[src/main/scala/chisel3/util/Arbiter.scala 143:15] when io.in[0].valid : @[src/main/scala/chisel3/util/Arbiter.scala 145:26] connect io.chosen, UInt<1>(0h0) @[src/main/scala/chisel3/util/Arbiter.scala 146:17] connect io.out.bits, io.in[0].bits @[src/main/scala/chisel3/util/Arbiter.scala 147:19] node grant_1 = eq(io.in[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Arbiter.scala 45:78] node _io_in_0_ready_T = and(UInt<1>(0h1), io.out.ready) @[src/main/scala/chisel3/util/Arbiter.scala 153:19] connect io.in[0].ready, _io_in_0_ready_T @[src/main/scala/chisel3/util/Arbiter.scala 153:14] node _io_in_1_ready_T = and(grant_1, io.out.ready) @[src/main/scala/chisel3/util/Arbiter.scala 153:19] connect io.in[1].ready, _io_in_1_ready_T @[src/main/scala/chisel3/util/Arbiter.scala 153:14] node _io_out_valid_T = eq(grant_1, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Arbiter.scala 154:19] node _io_out_valid_T_1 = or(_io_out_valid_T, io.in[1].valid) @[src/main/scala/chisel3/util/Arbiter.scala 154:31] connect io.out.valid, _io_out_valid_T_1 @[src/main/scala/chisel3/util/Arbiter.scala 154:16] module OptimizationBarrier_UInt : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : UInt, y : UInt} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module OptimizationBarrier_PTE : @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:30] output io : { flip x : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, y : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 269:18] connect io.y, io.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 273:12] module PTW : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 219:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 219:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 219:7] output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<21>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<33>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<34>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, dpath : { flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<33>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], perf : { l2miss : UInt<1>, l2hit : UInt<1>, pte_miss : UInt<1>, pte_hit : UInt<1>}, flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}, clock_enabled : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 220:14] regreset state : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 233:22] wire l2_refill_wire : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 234:28] inst arb of Arbiter2_Valid_PTWReq @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 236:19] connect arb.clock, clock connect arb.reset, reset connect arb.io.in[0], io.requestor[0].req @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 238:13] connect arb.io.in[1], io.requestor[1].req @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 238:13] node _arb_io_out_ready_T = eq(state, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 240:30] node _arb_io_out_ready_T_1 = eq(l2_refill_wire, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 240:46] node _arb_io_out_ready_T_2 = and(_arb_io_out_ready_T, _arb_io_out_ready_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 240:43] connect arb.io.out.ready, _arb_io_out_ready_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 240:20] wire _resp_valid_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 242:35] connect _resp_valid_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 242:35] connect _resp_valid_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 242:35] reg resp_valid : UInt<1>[2], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 242:27] connect resp_valid, _resp_valid_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 242:27] node _clock_en_T = neq(state, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 244:24] node _clock_en_T_1 = or(_clock_en_T, l2_refill_wire) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 244:36] node _clock_en_T_2 = or(_clock_en_T_1, arb.io.out.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 244:54] node _clock_en_T_3 = or(_clock_en_T_2, io.dpath.sfence.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 244:74] node _clock_en_T_4 = bits(io.dpath.customCSRs.csrs[0].value, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tile/CustomCSRs.scala 43:61] node clock_en = or(_clock_en_T_3, _clock_en_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 244:99] node _io_dpath_clock_enabled_T = and(UInt<1>(0h0), clock_en) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 245:39] connect io.dpath.clock_enabled, _io_dpath_clock_enabled_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 245:26] reg invalidated : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 251:24] reg count : UInt<2>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 259:18] reg resp_ae_ptw : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 260:24] reg resp_ae_final : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 261:26] reg resp_pf : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 262:20] reg resp_gf : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 263:20] reg resp_hr : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 264:20] reg resp_hw : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 265:20] reg resp_hx : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 266:20] reg resp_fragmented_superpage : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 267:38] reg r_req : { addr : UInt<21>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 270:18] reg r_req_dest : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 272:23] reg r_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 275:18] reg r_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 276:20] reg aux_count : UInt<2>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 278:22] reg aux_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 280:20] reg gpa_pgoff : UInt<12>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 281:22] reg stage2 : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 282:19] reg stage2_final : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 283:25] node satp = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 285:17] node _r_hgatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 286:42] node _r_hgatp_initial_count_T_1 = tail(_r_hgatp_initial_count_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 286:42] node _r_hgatp_initial_count_T_2 = sub(_r_hgatp_initial_count_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 286:58] node r_hgatp_initial_count = tail(_r_hgatp_initial_count_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 286:58] node do_both_stages = and(r_req.vstage1, r_req.stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 288:38] node _max_count_T = lt(count, aux_count) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 289:25] node max_count = mux(_max_count_T, aux_count, count) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 289:25] node _vpn_T = and(r_req.vstage1, stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 290:31] node vpn = mux(_vpn_T, aux_pte.ppn, r_req.addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 290:16] reg mem_resp_valid : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 292:31] connect mem_resp_valid, io.mem.resp.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 292:31] reg mem_resp_data : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 293:30] connect mem_resp_data, io.mem.resp.bits.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 293:30] wire tmp : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] wire _tmp_WIRE : UInt<64> @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] connect _tmp_WIRE, mem_resp_data @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] node _tmp_T = bits(_tmp_WIRE, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] connect tmp.v, _tmp_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] node _tmp_T_1 = bits(_tmp_WIRE, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] connect tmp.r, _tmp_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] node _tmp_T_2 = bits(_tmp_WIRE, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] connect tmp.w, _tmp_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] node _tmp_T_3 = bits(_tmp_WIRE, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] connect tmp.x, _tmp_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] node _tmp_T_4 = bits(_tmp_WIRE, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] connect tmp.u, _tmp_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] node _tmp_T_5 = bits(_tmp_WIRE, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] connect tmp.g, _tmp_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] node _tmp_T_6 = bits(_tmp_WIRE, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] connect tmp.a, _tmp_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] node _tmp_T_7 = bits(_tmp_WIRE, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] connect tmp.d, _tmp_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] node _tmp_T_8 = bits(_tmp_WIRE, 9, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] connect tmp.reserved_for_software, _tmp_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] node _tmp_T_9 = bits(_tmp_WIRE, 53, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] connect tmp.ppn, _tmp_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] node _tmp_T_10 = bits(_tmp_WIRE, 63, 54) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] connect tmp.reserved_for_future, _tmp_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 304:37] wire pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 305:26] connect pte, tmp @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 305:26] node _res_ppn_T = eq(stage2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 306:38] node _res_ppn_T_1 = and(do_both_stages, _res_ppn_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 306:35] node _res_ppn_T_2 = bits(tmp.ppn, 20, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 306:54] node _res_ppn_T_3 = bits(tmp.ppn, 19, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 306:99] node _res_ppn_T_4 = mux(_res_ppn_T_1, _res_ppn_T_2, _res_ppn_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 306:19] connect pte.ppn, _res_ppn_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 306:13] node _T = or(tmp.r, tmp.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 307:17] node _T_1 = or(_T, tmp.x) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 307:26] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 307:36] node _T_2 = leq(count, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 310:21] node _T_3 = bits(tmp.ppn, 17, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 310:38] node _T_4 = neq(_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 310:97] node _T_5 = and(_T_2, _T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 310:28] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 310:106] connect pte.v, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 310:114] node _T_6 = leq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 310:21] node _T_7 = bits(tmp.ppn, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 310:38] node _T_8 = neq(_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 310:97] node _T_9 = and(_T_6, _T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 310:28] when _T_9 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 310:106] connect pte.v, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 310:114] node _T_10 = eq(stage2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 313:26] node _T_11 = and(do_both_stages, _T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 313:23] node _T_12 = eq(_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 313:6] node _T_13 = shr(tmp.ppn, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 313:48] node _T_14 = neq(_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 313:60] node invalid_paddr = and(_T_12, _T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 313:35] node _T_15 = eq(stage2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 314:24] node _T_16 = and(do_both_stages, _T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 314:21] node _count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 806:28] node _count_T_1 = tail(_count_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 806:28] node _count_T_2 = sub(_count_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 806:44] node count_1 = tail(_count_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 806:44] node idxs_0 = shr(tmp.ppn, 29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 807:58] wire _WIRE : UInt<15>[1] @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 44:40] connect _WIRE[0], idxs_0 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 44:40] node _T_17 = or(count_1, UInt<0>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 25:40] node _T_18 = neq(_WIRE[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 808:25] node invalid_gpa = and(_T_16, _T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 314:32] node _traverse_T = eq(pte.r, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:36] node _traverse_T_1 = and(pte.v, _traverse_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:33] node _traverse_T_2 = eq(pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:42] node _traverse_T_3 = and(_traverse_T_1, _traverse_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:39] node _traverse_T_4 = eq(pte.x, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:48] node _traverse_T_5 = and(_traverse_T_3, _traverse_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:45] node _traverse_T_6 = eq(pte.d, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:54] node _traverse_T_7 = and(_traverse_T_5, _traverse_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:51] node _traverse_T_8 = eq(pte.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:60] node _traverse_T_9 = and(_traverse_T_7, _traverse_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:57] node _traverse_T_10 = eq(pte.u, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:66] node _traverse_T_11 = and(_traverse_T_9, _traverse_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:63] node _traverse_T_12 = eq(pte.reserved_for_future, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:92] node _traverse_T_13 = and(_traverse_T_11, _traverse_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:69] node _traverse_T_14 = eq(invalid_paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 317:33] node _traverse_T_15 = and(_traverse_T_13, _traverse_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 317:30] node _traverse_T_16 = eq(invalid_gpa, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 317:51] node _traverse_T_17 = and(_traverse_T_15, _traverse_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 317:48] node _traverse_T_18 = lt(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 317:73] node traverse = and(_traverse_T_17, _traverse_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 317:64] regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 168:70] regreset valid : UInt<8>, clock, reset, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 352:24] reg tags : UInt<32>[8], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 353:19] reg data : UInt<20>[8], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 355:19] node _can_hit_T = lt(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 358:18] node _can_hit_T_1 = eq(r_req.stage2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 358:65] node _can_hit_T_2 = mux(r_req.vstage1, stage2, _can_hit_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 358:41] node can_hit = and(_can_hit_T, _can_hit_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 358:35] node _tag_T = cat(UInt<31>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 139:15] node tag = cat(r_req.vstage1, _tag_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 364:15] node _hits_T = eq(tags[0], tag) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 366:27] node _hits_T_1 = eq(tags[1], tag) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 366:27] node _hits_T_2 = eq(tags[2], tag) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 366:27] node _hits_T_3 = eq(tags[3], tag) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 366:27] node _hits_T_4 = eq(tags[4], tag) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 366:27] node _hits_T_5 = eq(tags[5], tag) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 366:27] node _hits_T_6 = eq(tags[6], tag) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 366:27] node _hits_T_7 = eq(tags[7], tag) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 366:27] node hits_lo_lo = cat(_hits_T_1, _hits_T) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hits_lo_hi = cat(_hits_T_3, _hits_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hits_lo = cat(hits_lo_hi, hits_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hits_hi_lo = cat(_hits_T_5, _hits_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hits_hi_hi = cat(_hits_T_7, _hits_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hits_hi = cat(hits_hi_hi, hits_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hits_T_8 = cat(hits_hi, hits_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hits = and(_hits_T_8, valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 366:43] node _hit_T = orr(hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 367:20] node pte_cache_hit = and(_hit_T, can_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 367:24] node _T_19 = and(mem_resp_valid, traverse) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 369:26] node _T_20 = and(_T_19, can_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 369:38] node _T_21 = orr(hits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 369:61] node _T_22 = eq(_T_21, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 369:55] node _T_23 = and(_T_20, _T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 369:52] node _T_24 = eq(invalidated, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 369:68] node _T_25 = and(_T_23, _T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 369:65] when _T_25 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 369:82] node _r_T = andr(valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 370:25] node r_left_subtree_older = bits(state_reg, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 243:38] node r_left_subtree_state = bits(state_reg, 5, 3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node r_right_subtree_state = bits(state_reg, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 245:38] node r_left_subtree_older_1 = bits(r_left_subtree_state, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 243:38] node r_left_subtree_state_1 = bits(r_left_subtree_state, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node r_right_subtree_state_1 = bits(r_left_subtree_state, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 245:38] node _r_T_1 = bits(r_left_subtree_state_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 262:12] node _r_T_2 = bits(r_right_subtree_state_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 262:12] node _r_T_3 = mux(r_left_subtree_older_1, _r_T_1, _r_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 250:16] node _r_T_4 = cat(r_left_subtree_older_1, _r_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 249:12] node r_left_subtree_older_2 = bits(r_right_subtree_state, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 243:38] node r_left_subtree_state_2 = bits(r_right_subtree_state, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node r_right_subtree_state_2 = bits(r_right_subtree_state, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 245:38] node _r_T_5 = bits(r_left_subtree_state_2, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 262:12] node _r_T_6 = bits(r_right_subtree_state_2, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 262:12] node _r_T_7 = mux(r_left_subtree_older_2, _r_T_5, _r_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 250:16] node _r_T_8 = cat(r_left_subtree_older_2, _r_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 249:12] node _r_T_9 = mux(r_left_subtree_older, _r_T_4, _r_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 250:16] node _r_T_10 = cat(r_left_subtree_older, _r_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 249:12] node _r_T_11 = not(valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 370:57] node _r_T_12 = bits(_r_T_11, 0, 0) @[src/main/scala/chisel3/util/OneHot.scala 48:45] node _r_T_13 = bits(_r_T_11, 1, 1) @[src/main/scala/chisel3/util/OneHot.scala 48:45] node _r_T_14 = bits(_r_T_11, 2, 2) @[src/main/scala/chisel3/util/OneHot.scala 48:45] node _r_T_15 = bits(_r_T_11, 3, 3) @[src/main/scala/chisel3/util/OneHot.scala 48:45] node _r_T_16 = bits(_r_T_11, 4, 4) @[src/main/scala/chisel3/util/OneHot.scala 48:45] node _r_T_17 = bits(_r_T_11, 5, 5) @[src/main/scala/chisel3/util/OneHot.scala 48:45] node _r_T_18 = bits(_r_T_11, 6, 6) @[src/main/scala/chisel3/util/OneHot.scala 48:45] node _r_T_19 = bits(_r_T_11, 7, 7) @[src/main/scala/chisel3/util/OneHot.scala 48:45] node _r_T_20 = mux(_r_T_18, UInt<3>(0h6), UInt<3>(0h7)) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _r_T_21 = mux(_r_T_17, UInt<3>(0h5), _r_T_20) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _r_T_22 = mux(_r_T_16, UInt<3>(0h4), _r_T_21) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _r_T_23 = mux(_r_T_15, UInt<2>(0h3), _r_T_22) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _r_T_24 = mux(_r_T_14, UInt<2>(0h2), _r_T_23) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _r_T_25 = mux(_r_T_13, UInt<1>(0h1), _r_T_24) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _r_T_26 = mux(_r_T_12, UInt<1>(0h0), _r_T_25) @[src/main/scala/chisel3/util/Mux.scala 50:70] node r = mux(_r_T, _r_T_10, _r_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 370:18] node _valid_T = dshl(UInt<1>(0h1), r) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node _valid_T_1 = or(valid, _valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 371:22] connect valid, _valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 371:13] connect tags[r], tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 372:15] connect data[r], pte.ppn @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 373:15] node state_reg_touch_way_sized = bits(r, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:43] node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:33] node state_reg_left_subtree_state = bits(state_reg, 5, 3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node state_reg_right_subtree_state = bits(state_reg, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 198:38] node _state_reg_T = bits(state_reg_touch_way_sized, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_set_left_older_T_1 = bits(_state_reg_T, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:43] node state_reg_set_left_older_1 = eq(_state_reg_set_left_older_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:33] node state_reg_left_subtree_state_1 = bits(state_reg_left_subtree_state, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node state_reg_right_subtree_state_1 = bits(state_reg_left_subtree_state, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 198:38] node _state_reg_T_1 = bits(_state_reg_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_T_2 = bits(_state_reg_T_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_3 = eq(_state_reg_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_4 = mux(state_reg_set_left_older_1, state_reg_left_subtree_state_1, _state_reg_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 203:16] node _state_reg_T_5 = bits(_state_reg_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 207:62] node _state_reg_T_6 = bits(_state_reg_T_5, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_7 = eq(_state_reg_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_8 = mux(state_reg_set_left_older_1, _state_reg_T_7, state_reg_right_subtree_state_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 206:16] node state_reg_hi = cat(state_reg_set_left_older_1, _state_reg_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_9 = cat(state_reg_hi, _state_reg_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_10 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 203:16] node _state_reg_T_11 = bits(state_reg_touch_way_sized, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 207:62] node _state_reg_set_left_older_T_2 = bits(_state_reg_T_11, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:43] node state_reg_set_left_older_2 = eq(_state_reg_set_left_older_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:33] node state_reg_left_subtree_state_2 = bits(state_reg_right_subtree_state, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node state_reg_right_subtree_state_2 = bits(state_reg_right_subtree_state, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 198:38] node _state_reg_T_12 = bits(_state_reg_T_11, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_T_13 = bits(_state_reg_T_12, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_14 = eq(_state_reg_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_15 = mux(state_reg_set_left_older_2, state_reg_left_subtree_state_2, _state_reg_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 203:16] node _state_reg_T_16 = bits(_state_reg_T_11, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 207:62] node _state_reg_T_17 = bits(_state_reg_T_16, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_18 = eq(_state_reg_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_19 = mux(state_reg_set_left_older_2, _state_reg_T_18, state_reg_right_subtree_state_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 206:16] node state_reg_hi_1 = cat(state_reg_set_left_older_2, _state_reg_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_20 = cat(state_reg_hi_1, _state_reg_T_19) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_21 = mux(state_reg_set_left_older, _state_reg_T_20, state_reg_right_subtree_state) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 206:16] node state_reg_hi_2 = cat(state_reg_set_left_older, _state_reg_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_22 = cat(state_reg_hi_2, _state_reg_T_21) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] connect state_reg, _state_reg_T_22 @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 172:15] node _T_26 = eq(state, UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 377:24] node _T_27 = and(pte_cache_hit, _T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 377:15] when _T_27 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 377:35] node hi = bits(hits, 7, 4) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node lo = bits(hits, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _T_28 = orr(hi) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _T_29 = or(hi, lo) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node hi_1 = bits(_T_29, 3, 2) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node lo_1 = bits(_T_29, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _T_30 = orr(hi_1) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _T_31 = or(hi_1, lo_1) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node _T_32 = bits(_T_31, 1, 1) @[src/main/scala/chisel3/util/CircuitMath.scala 28:8] node _T_33 = cat(_T_30, _T_32) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node _T_34 = cat(_T_28, _T_33) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node state_reg_touch_way_sized_1 = bits(_T_34, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_set_left_older_T_3 = bits(state_reg_touch_way_sized_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:43] node state_reg_set_left_older_3 = eq(_state_reg_set_left_older_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:33] node state_reg_left_subtree_state_3 = bits(state_reg, 5, 3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node state_reg_right_subtree_state_3 = bits(state_reg, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 198:38] node _state_reg_T_23 = bits(state_reg_touch_way_sized_1, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_set_left_older_T_4 = bits(_state_reg_T_23, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:43] node state_reg_set_left_older_4 = eq(_state_reg_set_left_older_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:33] node state_reg_left_subtree_state_4 = bits(state_reg_left_subtree_state_3, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node state_reg_right_subtree_state_4 = bits(state_reg_left_subtree_state_3, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 198:38] node _state_reg_T_24 = bits(_state_reg_T_23, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_T_25 = bits(_state_reg_T_24, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_26 = eq(_state_reg_T_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_27 = mux(state_reg_set_left_older_4, state_reg_left_subtree_state_4, _state_reg_T_26) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 203:16] node _state_reg_T_28 = bits(_state_reg_T_23, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 207:62] node _state_reg_T_29 = bits(_state_reg_T_28, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_30 = eq(_state_reg_T_29, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_31 = mux(state_reg_set_left_older_4, _state_reg_T_30, state_reg_right_subtree_state_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 206:16] node state_reg_hi_3 = cat(state_reg_set_left_older_4, _state_reg_T_27) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_32 = cat(state_reg_hi_3, _state_reg_T_31) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_33 = mux(state_reg_set_left_older_3, state_reg_left_subtree_state_3, _state_reg_T_32) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 203:16] node _state_reg_T_34 = bits(state_reg_touch_way_sized_1, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 207:62] node _state_reg_set_left_older_T_5 = bits(_state_reg_T_34, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:43] node state_reg_set_left_older_5 = eq(_state_reg_set_left_older_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:33] node state_reg_left_subtree_state_5 = bits(state_reg_right_subtree_state_3, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node state_reg_right_subtree_state_5 = bits(state_reg_right_subtree_state_3, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 198:38] node _state_reg_T_35 = bits(_state_reg_T_34, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_T_36 = bits(_state_reg_T_35, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_37 = eq(_state_reg_T_36, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_38 = mux(state_reg_set_left_older_5, state_reg_left_subtree_state_5, _state_reg_T_37) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 203:16] node _state_reg_T_39 = bits(_state_reg_T_34, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 207:62] node _state_reg_T_40 = bits(_state_reg_T_39, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_41 = eq(_state_reg_T_40, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_42 = mux(state_reg_set_left_older_5, _state_reg_T_41, state_reg_right_subtree_state_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 206:16] node state_reg_hi_4 = cat(state_reg_set_left_older_5, _state_reg_T_38) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_43 = cat(state_reg_hi_4, _state_reg_T_42) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_44 = mux(state_reg_set_left_older_3, _state_reg_T_43, state_reg_right_subtree_state_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 206:16] node state_reg_hi_5 = cat(state_reg_set_left_older_3, _state_reg_T_33) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_45 = cat(state_reg_hi_5, _state_reg_T_44) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] connect state_reg, _state_reg_T_45 @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 172:15] node _T_35 = eq(io.dpath.sfence.bits.rs1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 378:37] node _T_36 = and(UInt<1>(0h0), io.dpath.sfence.bits.hg) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 378:84] node _T_37 = or(_T_35, _T_36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 378:63] node _T_38 = and(io.dpath.sfence.valid, _T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 378:33] when _T_38 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 378:113] connect valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 378:121] node _T_39 = eq(state, UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 382:27] node _T_40 = and(pte_cache_hit, _T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 382:18] node _T_41 = eq(count, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 382:47] node _T_42 = and(_T_40, _T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 382:37] node _T_43 = eq(state, UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 382:27] node _T_44 = and(pte_cache_hit, _T_43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 382:18] node _T_45 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 382:47] node _T_46 = and(_T_44, _T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 382:37] node _T_47 = bits(hits, 0, 0) @[src/main/scala/chisel3/util/Mux.scala 32:36] node _T_48 = bits(hits, 1, 1) @[src/main/scala/chisel3/util/Mux.scala 32:36] node _T_49 = bits(hits, 2, 2) @[src/main/scala/chisel3/util/Mux.scala 32:36] node _T_50 = bits(hits, 3, 3) @[src/main/scala/chisel3/util/Mux.scala 32:36] node _T_51 = bits(hits, 4, 4) @[src/main/scala/chisel3/util/Mux.scala 32:36] node _T_52 = bits(hits, 5, 5) @[src/main/scala/chisel3/util/Mux.scala 32:36] node _T_53 = bits(hits, 6, 6) @[src/main/scala/chisel3/util/Mux.scala 32:36] node _T_54 = bits(hits, 7, 7) @[src/main/scala/chisel3/util/Mux.scala 32:36] node _T_55 = mux(_T_47, data[0], UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_56 = mux(_T_48, data[1], UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_57 = mux(_T_49, data[2], UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_58 = mux(_T_50, data[3], UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_59 = mux(_T_51, data[4], UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_60 = mux(_T_52, data[5], UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_61 = mux(_T_53, data[6], UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_62 = mux(_T_54, data[7], UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_63 = or(_T_55, _T_56) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_64 = or(_T_63, _T_57) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_65 = or(_T_64, _T_58) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_66 = or(_T_65, _T_59) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_67 = or(_T_66, _T_60) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_68 = or(_T_67, _T_61) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_69 = or(_T_68, _T_62) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire pte_cache_data : UInt<20> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect pte_cache_data, _T_69 @[src/main/scala/chisel3/util/Mux.scala 30:73] regreset state_reg_1 : UInt<7>, clock, reset, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 168:70] regreset valid_1 : UInt<8>, clock, reset, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 352:24] reg tags_1 : UInt<32>[8], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 353:19] reg data_1 : UInt<20>[8], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 355:19] node _can_hit_T_3 = eq(count, r_hgatp_initial_count) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 357:21] node _can_hit_T_4 = lt(aux_count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 357:60] node _can_hit_T_5 = and(_can_hit_T_3, _can_hit_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 357:47] node _can_hit_T_6 = and(_can_hit_T_5, r_req.vstage1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 357:77] node _can_hit_T_7 = and(_can_hit_T_6, stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 357:94] node _can_hit_T_8 = eq(stage2_final, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 357:107] node can_hit_1 = and(_can_hit_T_7, _can_hit_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 357:104] node _can_refill_T = eq(stage2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 360:33] node _can_refill_T_1 = and(do_both_stages, _can_refill_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 360:30] node _can_refill_T_2 = eq(stage2_final, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 360:44] node can_refill = and(_can_refill_T_1, _can_refill_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 360:41] node _tag_T_1 = cat(UInt<32>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 139:15] node tag_1 = cat(UInt<1>(0h1), _tag_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 363:18] node _hits_T_9 = eq(tags_1[0], tag_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 366:27] node _hits_T_10 = eq(tags_1[1], tag_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 366:27] node _hits_T_11 = eq(tags_1[2], tag_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 366:27] node _hits_T_12 = eq(tags_1[3], tag_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 366:27] node _hits_T_13 = eq(tags_1[4], tag_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 366:27] node _hits_T_14 = eq(tags_1[5], tag_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 366:27] node _hits_T_15 = eq(tags_1[6], tag_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 366:27] node _hits_T_16 = eq(tags_1[7], tag_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 366:27] node hits_lo_lo_1 = cat(_hits_T_10, _hits_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hits_lo_hi_1 = cat(_hits_T_12, _hits_T_11) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hits_lo_1 = cat(hits_lo_hi_1, hits_lo_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hits_hi_lo_1 = cat(_hits_T_14, _hits_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hits_hi_hi_1 = cat(_hits_T_16, _hits_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hits_hi_1 = cat(hits_hi_hi_1, hits_hi_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _hits_T_17 = cat(hits_hi_1, hits_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hits_1 = and(_hits_T_17, valid_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 366:43] node _hit_T_1 = orr(hits_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 367:20] node stage2_pte_cache_hit = and(_hit_T_1, can_hit_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 367:24] node _T_70 = and(mem_resp_valid, traverse) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 369:26] node _T_71 = and(_T_70, can_refill) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 369:38] node _T_72 = orr(hits_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 369:61] node _T_73 = eq(_T_72, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 369:55] node _T_74 = and(_T_71, _T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 369:52] node _T_75 = eq(invalidated, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 369:68] node _T_76 = and(_T_74, _T_75) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 369:65] when _T_76 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 369:82] node _r_T_27 = andr(valid_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 370:25] node r_left_subtree_older_3 = bits(state_reg_1, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 243:38] node r_left_subtree_state_3 = bits(state_reg_1, 5, 3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node r_right_subtree_state_3 = bits(state_reg_1, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 245:38] node r_left_subtree_older_4 = bits(r_left_subtree_state_3, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 243:38] node r_left_subtree_state_4 = bits(r_left_subtree_state_3, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node r_right_subtree_state_4 = bits(r_left_subtree_state_3, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 245:38] node _r_T_28 = bits(r_left_subtree_state_4, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 262:12] node _r_T_29 = bits(r_right_subtree_state_4, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 262:12] node _r_T_30 = mux(r_left_subtree_older_4, _r_T_28, _r_T_29) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 250:16] node _r_T_31 = cat(r_left_subtree_older_4, _r_T_30) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 249:12] node r_left_subtree_older_5 = bits(r_right_subtree_state_3, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 243:38] node r_left_subtree_state_5 = bits(r_right_subtree_state_3, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node r_right_subtree_state_5 = bits(r_right_subtree_state_3, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 245:38] node _r_T_32 = bits(r_left_subtree_state_5, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 262:12] node _r_T_33 = bits(r_right_subtree_state_5, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 262:12] node _r_T_34 = mux(r_left_subtree_older_5, _r_T_32, _r_T_33) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 250:16] node _r_T_35 = cat(r_left_subtree_older_5, _r_T_34) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 249:12] node _r_T_36 = mux(r_left_subtree_older_3, _r_T_31, _r_T_35) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 250:16] node _r_T_37 = cat(r_left_subtree_older_3, _r_T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 249:12] node _r_T_38 = not(valid_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 370:57] node _r_T_39 = bits(_r_T_38, 0, 0) @[src/main/scala/chisel3/util/OneHot.scala 48:45] node _r_T_40 = bits(_r_T_38, 1, 1) @[src/main/scala/chisel3/util/OneHot.scala 48:45] node _r_T_41 = bits(_r_T_38, 2, 2) @[src/main/scala/chisel3/util/OneHot.scala 48:45] node _r_T_42 = bits(_r_T_38, 3, 3) @[src/main/scala/chisel3/util/OneHot.scala 48:45] node _r_T_43 = bits(_r_T_38, 4, 4) @[src/main/scala/chisel3/util/OneHot.scala 48:45] node _r_T_44 = bits(_r_T_38, 5, 5) @[src/main/scala/chisel3/util/OneHot.scala 48:45] node _r_T_45 = bits(_r_T_38, 6, 6) @[src/main/scala/chisel3/util/OneHot.scala 48:45] node _r_T_46 = bits(_r_T_38, 7, 7) @[src/main/scala/chisel3/util/OneHot.scala 48:45] node _r_T_47 = mux(_r_T_45, UInt<3>(0h6), UInt<3>(0h7)) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _r_T_48 = mux(_r_T_44, UInt<3>(0h5), _r_T_47) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _r_T_49 = mux(_r_T_43, UInt<3>(0h4), _r_T_48) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _r_T_50 = mux(_r_T_42, UInt<2>(0h3), _r_T_49) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _r_T_51 = mux(_r_T_41, UInt<2>(0h2), _r_T_50) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _r_T_52 = mux(_r_T_40, UInt<1>(0h1), _r_T_51) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _r_T_53 = mux(_r_T_39, UInt<1>(0h0), _r_T_52) @[src/main/scala/chisel3/util/Mux.scala 50:70] node r_1 = mux(_r_T_27, _r_T_37, _r_T_53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 370:18] node _valid_T_2 = dshl(UInt<1>(0h1), r_1) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node _valid_T_3 = or(valid_1, _valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 371:22] connect valid_1, _valid_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 371:13] connect tags_1[r_1], tag_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 372:15] connect data_1[r_1], pte.ppn @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 373:15] node state_reg_touch_way_sized_2 = bits(r_1, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_set_left_older_T_6 = bits(state_reg_touch_way_sized_2, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:43] node state_reg_set_left_older_6 = eq(_state_reg_set_left_older_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:33] node state_reg_left_subtree_state_6 = bits(state_reg_1, 5, 3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node state_reg_right_subtree_state_6 = bits(state_reg_1, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 198:38] node _state_reg_T_46 = bits(state_reg_touch_way_sized_2, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_set_left_older_T_7 = bits(_state_reg_T_46, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:43] node state_reg_set_left_older_7 = eq(_state_reg_set_left_older_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:33] node state_reg_left_subtree_state_7 = bits(state_reg_left_subtree_state_6, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node state_reg_right_subtree_state_7 = bits(state_reg_left_subtree_state_6, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 198:38] node _state_reg_T_47 = bits(_state_reg_T_46, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_T_48 = bits(_state_reg_T_47, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_49 = eq(_state_reg_T_48, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_50 = mux(state_reg_set_left_older_7, state_reg_left_subtree_state_7, _state_reg_T_49) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 203:16] node _state_reg_T_51 = bits(_state_reg_T_46, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 207:62] node _state_reg_T_52 = bits(_state_reg_T_51, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_53 = eq(_state_reg_T_52, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_54 = mux(state_reg_set_left_older_7, _state_reg_T_53, state_reg_right_subtree_state_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 206:16] node state_reg_hi_6 = cat(state_reg_set_left_older_7, _state_reg_T_50) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_55 = cat(state_reg_hi_6, _state_reg_T_54) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_56 = mux(state_reg_set_left_older_6, state_reg_left_subtree_state_6, _state_reg_T_55) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 203:16] node _state_reg_T_57 = bits(state_reg_touch_way_sized_2, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 207:62] node _state_reg_set_left_older_T_8 = bits(_state_reg_T_57, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:43] node state_reg_set_left_older_8 = eq(_state_reg_set_left_older_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:33] node state_reg_left_subtree_state_8 = bits(state_reg_right_subtree_state_6, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node state_reg_right_subtree_state_8 = bits(state_reg_right_subtree_state_6, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 198:38] node _state_reg_T_58 = bits(_state_reg_T_57, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_T_59 = bits(_state_reg_T_58, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_60 = eq(_state_reg_T_59, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_61 = mux(state_reg_set_left_older_8, state_reg_left_subtree_state_8, _state_reg_T_60) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 203:16] node _state_reg_T_62 = bits(_state_reg_T_57, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 207:62] node _state_reg_T_63 = bits(_state_reg_T_62, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_64 = eq(_state_reg_T_63, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_65 = mux(state_reg_set_left_older_8, _state_reg_T_64, state_reg_right_subtree_state_8) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 206:16] node state_reg_hi_7 = cat(state_reg_set_left_older_8, _state_reg_T_61) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_66 = cat(state_reg_hi_7, _state_reg_T_65) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_67 = mux(state_reg_set_left_older_6, _state_reg_T_66, state_reg_right_subtree_state_6) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 206:16] node state_reg_hi_8 = cat(state_reg_set_left_older_6, _state_reg_T_56) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_68 = cat(state_reg_hi_8, _state_reg_T_67) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] connect state_reg_1, _state_reg_T_68 @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 172:15] node _T_77 = eq(state, UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 377:24] node _T_78 = and(stage2_pte_cache_hit, _T_77) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 377:15] when _T_78 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 377:35] node hi_2 = bits(hits_1, 7, 4) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node lo_2 = bits(hits_1, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _T_79 = orr(hi_2) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _T_80 = or(hi_2, lo_2) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node hi_3 = bits(_T_80, 3, 2) @[src/main/scala/chisel3/util/OneHot.scala 30:18] node lo_3 = bits(_T_80, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 31:18] node _T_81 = orr(hi_3) @[src/main/scala/chisel3/util/OneHot.scala 32:14] node _T_82 = or(hi_3, lo_3) @[src/main/scala/chisel3/util/OneHot.scala 32:28] node _T_83 = bits(_T_82, 1, 1) @[src/main/scala/chisel3/util/CircuitMath.scala 28:8] node _T_84 = cat(_T_81, _T_83) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node _T_85 = cat(_T_79, _T_84) @[src/main/scala/chisel3/util/OneHot.scala 32:10] node state_reg_touch_way_sized_3 = bits(_T_85, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_set_left_older_T_9 = bits(state_reg_touch_way_sized_3, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:43] node state_reg_set_left_older_9 = eq(_state_reg_set_left_older_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:33] node state_reg_left_subtree_state_9 = bits(state_reg_1, 5, 3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node state_reg_right_subtree_state_9 = bits(state_reg_1, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 198:38] node _state_reg_T_69 = bits(state_reg_touch_way_sized_3, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_set_left_older_T_10 = bits(_state_reg_T_69, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:43] node state_reg_set_left_older_10 = eq(_state_reg_set_left_older_T_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:33] node state_reg_left_subtree_state_10 = bits(state_reg_left_subtree_state_9, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node state_reg_right_subtree_state_10 = bits(state_reg_left_subtree_state_9, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 198:38] node _state_reg_T_70 = bits(_state_reg_T_69, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_T_71 = bits(_state_reg_T_70, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_72 = eq(_state_reg_T_71, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_73 = mux(state_reg_set_left_older_10, state_reg_left_subtree_state_10, _state_reg_T_72) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 203:16] node _state_reg_T_74 = bits(_state_reg_T_69, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 207:62] node _state_reg_T_75 = bits(_state_reg_T_74, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_76 = eq(_state_reg_T_75, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_77 = mux(state_reg_set_left_older_10, _state_reg_T_76, state_reg_right_subtree_state_10) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 206:16] node state_reg_hi_9 = cat(state_reg_set_left_older_10, _state_reg_T_73) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_78 = cat(state_reg_hi_9, _state_reg_T_77) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_79 = mux(state_reg_set_left_older_9, state_reg_left_subtree_state_9, _state_reg_T_78) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 203:16] node _state_reg_T_80 = bits(state_reg_touch_way_sized_3, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 207:62] node _state_reg_set_left_older_T_11 = bits(_state_reg_T_80, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:43] node state_reg_set_left_older_11 = eq(_state_reg_set_left_older_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 196:33] node state_reg_left_subtree_state_11 = bits(state_reg_right_subtree_state_9, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node state_reg_right_subtree_state_11 = bits(state_reg_right_subtree_state_9, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 198:38] node _state_reg_T_81 = bits(_state_reg_T_80, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _state_reg_T_82 = bits(_state_reg_T_81, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_83 = eq(_state_reg_T_82, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_84 = mux(state_reg_set_left_older_11, state_reg_left_subtree_state_11, _state_reg_T_83) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 203:16] node _state_reg_T_85 = bits(_state_reg_T_80, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 207:62] node _state_reg_T_86 = bits(_state_reg_T_85, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:17] node _state_reg_T_87 = eq(_state_reg_T_86, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 218:7] node _state_reg_T_88 = mux(state_reg_set_left_older_11, _state_reg_T_87, state_reg_right_subtree_state_11) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 206:16] node state_reg_hi_10 = cat(state_reg_set_left_older_11, _state_reg_T_84) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_89 = cat(state_reg_hi_10, _state_reg_T_88) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_90 = mux(state_reg_set_left_older_9, _state_reg_T_89, state_reg_right_subtree_state_9) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 206:16] node state_reg_hi_11 = cat(state_reg_set_left_older_9, _state_reg_T_79) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] node _state_reg_T_91 = cat(state_reg_hi_11, _state_reg_T_90) @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 202:12] connect state_reg_1, _state_reg_T_91 @[hardware/upstream/rocket-chip/src/main/scala/util/Replacement.scala 172:15] node _T_86 = eq(io.dpath.sfence.bits.rs1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 378:37] node _T_87 = and(UInt<1>(0h0), io.dpath.sfence.bits.hg) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 378:84] node _T_88 = or(_T_86, _T_87) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 378:63] node _T_89 = and(io.dpath.sfence.valid, _T_88) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 378:33] when _T_89 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 378:113] connect valid_1, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 378:121] node _T_90 = eq(state, UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 382:27] node _T_91 = and(stage2_pte_cache_hit, _T_90) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 382:18] node _T_92 = eq(aux_count, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 382:47] node _T_93 = and(_T_91, _T_92) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 382:37] node _T_94 = eq(state, UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 382:27] node _T_95 = and(stage2_pte_cache_hit, _T_94) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 382:18] node _T_96 = eq(aux_count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 382:47] node _T_97 = and(_T_95, _T_96) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 382:37] node _T_98 = bits(hits_1, 0, 0) @[src/main/scala/chisel3/util/Mux.scala 32:36] node _T_99 = bits(hits_1, 1, 1) @[src/main/scala/chisel3/util/Mux.scala 32:36] node _T_100 = bits(hits_1, 2, 2) @[src/main/scala/chisel3/util/Mux.scala 32:36] node _T_101 = bits(hits_1, 3, 3) @[src/main/scala/chisel3/util/Mux.scala 32:36] node _T_102 = bits(hits_1, 4, 4) @[src/main/scala/chisel3/util/Mux.scala 32:36] node _T_103 = bits(hits_1, 5, 5) @[src/main/scala/chisel3/util/Mux.scala 32:36] node _T_104 = bits(hits_1, 6, 6) @[src/main/scala/chisel3/util/Mux.scala 32:36] node _T_105 = bits(hits_1, 7, 7) @[src/main/scala/chisel3/util/Mux.scala 32:36] node _T_106 = mux(_T_98, data_1[0], UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_107 = mux(_T_99, data_1[1], UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_108 = mux(_T_100, data_1[2], UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_109 = mux(_T_101, data_1[3], UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_110 = mux(_T_102, data_1[4], UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_111 = mux(_T_103, data_1[5], UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_112 = mux(_T_104, data_1[6], UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_113 = mux(_T_105, data_1[7], UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_114 = or(_T_106, _T_107) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_115 = or(_T_114, _T_108) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_116 = or(_T_115, _T_109) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_117 = or(_T_116, _T_110) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_118 = or(_T_117, _T_111) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_119 = or(_T_118, _T_112) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _T_120 = or(_T_119, _T_113) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire stage2_pte_cache_data : UInt<20> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect stage2_pte_cache_data, _T_120 @[src/main/scala/chisel3/util/Mux.scala 30:73] reg pte_hit : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 392:24] connect pte_hit, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 392:24] connect io.dpath.perf.pte_miss, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 393:26] node _io_dpath_perf_pte_hit_T = eq(state, UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 394:46] node _io_dpath_perf_pte_hit_T_1 = and(pte_hit, _io_dpath_perf_pte_hit_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 394:36] node _io_dpath_perf_pte_hit_T_2 = eq(io.dpath.perf.l2hit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 394:60] node _io_dpath_perf_pte_hit_T_3 = and(_io_dpath_perf_pte_hit_T_1, _io_dpath_perf_pte_hit_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 394:57] connect io.dpath.perf.pte_hit, _io_dpath_perf_pte_hit_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 394:25] node _T_121 = or(io.dpath.perf.pte_miss, io.dpath.perf.pte_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 395:59] node _T_122 = and(io.dpath.perf.l2hit, _T_121) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 395:32] node _T_123 = eq(_T_122, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 395:10] node _T_124 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 395:9] node _T_125 = eq(_T_124, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 395:9] when _T_125 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 395:9] node _T_126 = eq(_T_123, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 395:9] when _T_126 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 395:9] printf(clock, UInt<1>(0h1), "Assertion failed: PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event\n at PTW.scala:395 assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)),\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 395:9] assert(clock, _T_123, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 395:9] reg l2_refill : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 398:26] connect l2_refill, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 398:26] connect l2_refill_wire, l2_refill @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 399:18] connect io.dpath.perf.l2miss, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 400:24] connect io.dpath.perf.l2hit, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 401:23] wire _WIRE_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 403:126] connect _WIRE_1.v, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 403:126] connect _WIRE_1.r, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 403:126] connect _WIRE_1.w, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 403:126] connect _WIRE_1.x, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 403:126] connect _WIRE_1.u, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 403:126] connect _WIRE_1.g, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 403:126] connect _WIRE_1.a, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 403:126] connect _WIRE_1.d, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 403:126] connect _WIRE_1.reserved_for_software, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 403:126] connect _WIRE_1.ppn, UInt<44>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 403:126] connect _WIRE_1.reserved_for_future, UInt<10>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 403:126] wire l2_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 403:113] connect l2_pte, _WIRE_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 403:113] node _invalidated_T = neq(state, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 511:65] node _invalidated_T_1 = and(invalidated, _invalidated_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 511:56] node _invalidated_T_2 = or(io.dpath.sfence.valid, _invalidated_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 511:40] connect invalidated, _invalidated_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 511:15] connect io.mem.keep_clock_enabled, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 513:29] node _io_mem_req_valid_T = eq(state, UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 515:29] node _io_mem_req_valid_T_1 = eq(state, UInt<3>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 515:48] node _io_mem_req_valid_T_2 = or(_io_mem_req_valid_T, _io_mem_req_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 515:39] connect io.mem.req.valid, _io_mem_req_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 515:20] connect io.mem.req.bits.phys, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 516:24] connect io.mem.req.bits.cmd, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 517:24] connect io.mem.req.bits.size, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 518:24] connect io.mem.req.bits.signed, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 519:26] connect io.mem.req.bits.addr, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 520:24] connect io.mem.req.bits.dprv, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 522:24] node _io_mem_req_bits_dv_T = eq(stage2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 523:43] node _io_mem_req_bits_dv_T_1 = and(do_both_stages, _io_mem_req_bits_dv_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 523:40] connect io.mem.req.bits.dv, _io_mem_req_bits_dv_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 523:22] invalidate io.mem.req.bits.tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 524:23] connect io.mem.req.bits.no_resp, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 525:27] invalidate io.mem.req.bits.no_alloc @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 526:28] invalidate io.mem.req.bits.no_xcpt @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 527:27] invalidate io.mem.req.bits.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 528:24] invalidate io.mem.req.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 529:24] node _io_mem_s1_kill_T = neq(state, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 531:38] node _io_mem_s1_kill_T_1 = or(UInt<1>(0h0), _io_mem_s1_kill_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 531:28] node _io_mem_s1_kill_T_2 = or(_io_mem_s1_kill_T_1, resp_gf) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 531:51] connect io.mem.s1_kill, _io_mem_s1_kill_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 531:18] invalidate io.mem.s1_data.mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 532:18] invalidate io.mem.s1_data.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 532:18] connect io.mem.s2_kill, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 533:18] node _pmaPgLevelHomogeneous_T = shl(r_pte.ppn, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 544:96] node _pmaPgLevelHomogeneous_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _pmaPgLevelHomogeneous_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _pmaPgLevelHomogeneous_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _pmaPgLevelHomogeneous_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _pmaPgLevelHomogeneous_T_5 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _pmaPgLevelHomogeneous_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _pmaPgLevelHomogeneous_T_7 = shl(r_pte.ppn, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 544:96] node _pmaPgLevelHomogeneous_T_8 = xor(_pmaPgLevelHomogeneous_T_7, UInt<28>(0hc000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pmaPgLevelHomogeneous_T_9 = cvt(_pmaPgLevelHomogeneous_T_8) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pmaPgLevelHomogeneous_T_10 = and(_pmaPgLevelHomogeneous_T_9, asSInt(UInt<27>(0h4000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_11 = asSInt(_pmaPgLevelHomogeneous_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_12 = eq(_pmaPgLevelHomogeneous_T_11, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node pmaPgLevelHomogeneous_1 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _pmaPgLevelHomogeneous_T_13 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _pmaPgLevelHomogeneous_T_14 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _pmaPgLevelHomogeneous_T_15 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _pmaPgLevelHomogeneous_T_16 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _pmaPgLevelHomogeneous_T_17 = shl(r_pte.ppn, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 544:96] node _pmaPgLevelHomogeneous_T_18 = xor(_pmaPgLevelHomogeneous_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pmaPgLevelHomogeneous_T_19 = cvt(_pmaPgLevelHomogeneous_T_18) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pmaPgLevelHomogeneous_T_20 = and(_pmaPgLevelHomogeneous_T_19, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_21 = asSInt(_pmaPgLevelHomogeneous_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_22 = eq(_pmaPgLevelHomogeneous_T_21, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pmaPgLevelHomogeneous_T_23 = xor(_pmaPgLevelHomogeneous_T_17, UInt<14>(0h3000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pmaPgLevelHomogeneous_T_24 = cvt(_pmaPgLevelHomogeneous_T_23) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pmaPgLevelHomogeneous_T_25 = and(_pmaPgLevelHomogeneous_T_24, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_26 = asSInt(_pmaPgLevelHomogeneous_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_27 = eq(_pmaPgLevelHomogeneous_T_26, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pmaPgLevelHomogeneous_T_28 = xor(_pmaPgLevelHomogeneous_T_17, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pmaPgLevelHomogeneous_T_29 = cvt(_pmaPgLevelHomogeneous_T_28) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pmaPgLevelHomogeneous_T_30 = and(_pmaPgLevelHomogeneous_T_29, asSInt(UInt<17>(0h10000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_31 = asSInt(_pmaPgLevelHomogeneous_T_30) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_32 = eq(_pmaPgLevelHomogeneous_T_31, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pmaPgLevelHomogeneous_T_33 = xor(_pmaPgLevelHomogeneous_T_17, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pmaPgLevelHomogeneous_T_34 = cvt(_pmaPgLevelHomogeneous_T_33) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pmaPgLevelHomogeneous_T_35 = and(_pmaPgLevelHomogeneous_T_34, asSInt(UInt<17>(0h10000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_36 = asSInt(_pmaPgLevelHomogeneous_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_37 = eq(_pmaPgLevelHomogeneous_T_36, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pmaPgLevelHomogeneous_T_38 = xor(_pmaPgLevelHomogeneous_T_17, UInt<28>(0hc000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pmaPgLevelHomogeneous_T_39 = cvt(_pmaPgLevelHomogeneous_T_38) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pmaPgLevelHomogeneous_T_40 = and(_pmaPgLevelHomogeneous_T_39, asSInt(UInt<27>(0h4000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_41 = asSInt(_pmaPgLevelHomogeneous_T_40) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_42 = eq(_pmaPgLevelHomogeneous_T_41, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pmaPgLevelHomogeneous_T_43 = xor(_pmaPgLevelHomogeneous_T_17, UInt<29>(0h10013000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pmaPgLevelHomogeneous_T_44 = cvt(_pmaPgLevelHomogeneous_T_43) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pmaPgLevelHomogeneous_T_45 = and(_pmaPgLevelHomogeneous_T_44, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_46 = asSInt(_pmaPgLevelHomogeneous_T_45) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_47 = eq(_pmaPgLevelHomogeneous_T_46, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pmaPgLevelHomogeneous_T_48 = xor(_pmaPgLevelHomogeneous_T_17, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pmaPgLevelHomogeneous_T_49 = cvt(_pmaPgLevelHomogeneous_T_48) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pmaPgLevelHomogeneous_T_50 = and(_pmaPgLevelHomogeneous_T_49, asSInt(UInt<14>(0h2000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_51 = asSInt(_pmaPgLevelHomogeneous_T_50) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_52 = eq(_pmaPgLevelHomogeneous_T_51, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pmaPgLevelHomogeneous_T_53 = xor(_pmaPgLevelHomogeneous_T_17, UInt<29>(0h10020000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pmaPgLevelHomogeneous_T_54 = cvt(_pmaPgLevelHomogeneous_T_53) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pmaPgLevelHomogeneous_T_55 = and(_pmaPgLevelHomogeneous_T_54, asSInt(UInt<16>(0h8000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_56 = asSInt(_pmaPgLevelHomogeneous_T_55) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_57 = eq(_pmaPgLevelHomogeneous_T_56, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pmaPgLevelHomogeneous_T_58 = xor(_pmaPgLevelHomogeneous_T_17, UInt<29>(0h10028000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pmaPgLevelHomogeneous_T_59 = cvt(_pmaPgLevelHomogeneous_T_58) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pmaPgLevelHomogeneous_T_60 = and(_pmaPgLevelHomogeneous_T_59, asSInt(UInt<14>(0h2000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_61 = asSInt(_pmaPgLevelHomogeneous_T_60) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_62 = eq(_pmaPgLevelHomogeneous_T_61, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pmaPgLevelHomogeneous_T_63 = xor(_pmaPgLevelHomogeneous_T_17, UInt<29>(0h1002a000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pmaPgLevelHomogeneous_T_64 = cvt(_pmaPgLevelHomogeneous_T_63) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pmaPgLevelHomogeneous_T_65 = and(_pmaPgLevelHomogeneous_T_64, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_66 = asSInt(_pmaPgLevelHomogeneous_T_65) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_67 = eq(_pmaPgLevelHomogeneous_T_66, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pmaPgLevelHomogeneous_T_68 = xor(_pmaPgLevelHomogeneous_T_17, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pmaPgLevelHomogeneous_T_69 = cvt(_pmaPgLevelHomogeneous_T_68) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pmaPgLevelHomogeneous_T_70 = and(_pmaPgLevelHomogeneous_T_69, asSInt(UInt<21>(0h100000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_71 = asSInt(_pmaPgLevelHomogeneous_T_70) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_72 = eq(_pmaPgLevelHomogeneous_T_71, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pmaPgLevelHomogeneous_T_73 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _pmaPgLevelHomogeneous_T_74 = or(_pmaPgLevelHomogeneous_T_73, _pmaPgLevelHomogeneous_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _pmaPgLevelHomogeneous_T_75 = or(_pmaPgLevelHomogeneous_T_74, _pmaPgLevelHomogeneous_T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _pmaPgLevelHomogeneous_T_76 = or(_pmaPgLevelHomogeneous_T_75, _pmaPgLevelHomogeneous_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _pmaPgLevelHomogeneous_T_77 = or(_pmaPgLevelHomogeneous_T_76, _pmaPgLevelHomogeneous_T_42) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _pmaPgLevelHomogeneous_T_78 = or(_pmaPgLevelHomogeneous_T_77, _pmaPgLevelHomogeneous_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _pmaPgLevelHomogeneous_T_79 = or(_pmaPgLevelHomogeneous_T_78, _pmaPgLevelHomogeneous_T_52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _pmaPgLevelHomogeneous_T_80 = or(_pmaPgLevelHomogeneous_T_79, _pmaPgLevelHomogeneous_T_57) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _pmaPgLevelHomogeneous_T_81 = or(_pmaPgLevelHomogeneous_T_80, _pmaPgLevelHomogeneous_T_62) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _pmaPgLevelHomogeneous_T_82 = or(_pmaPgLevelHomogeneous_T_81, _pmaPgLevelHomogeneous_T_67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node pmaPgLevelHomogeneous_2 = or(_pmaPgLevelHomogeneous_T_82, _pmaPgLevelHomogeneous_T_72) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 101:65] node _pmaPgLevelHomogeneous_T_83 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _pmaPgLevelHomogeneous_T_84 = xor(_pmaPgLevelHomogeneous_T_17, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pmaPgLevelHomogeneous_T_85 = cvt(_pmaPgLevelHomogeneous_T_84) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pmaPgLevelHomogeneous_T_86 = and(_pmaPgLevelHomogeneous_T_85, asSInt(UInt<33>(0h98010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_87 = asSInt(_pmaPgLevelHomogeneous_T_86) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_88 = eq(_pmaPgLevelHomogeneous_T_87, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pmaPgLevelHomogeneous_T_89 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_88) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:66] node _pmaPgLevelHomogeneous_T_90 = eq(_pmaPgLevelHomogeneous_T_89, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _pmaPgLevelHomogeneous_T_91 = xor(_pmaPgLevelHomogeneous_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pmaPgLevelHomogeneous_T_92 = cvt(_pmaPgLevelHomogeneous_T_91) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pmaPgLevelHomogeneous_T_93 = and(_pmaPgLevelHomogeneous_T_92, asSInt(UInt<30>(0h1a000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_94 = asSInt(_pmaPgLevelHomogeneous_T_93) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_95 = eq(_pmaPgLevelHomogeneous_T_94, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pmaPgLevelHomogeneous_T_96 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_95) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 85:66] node _pmaPgLevelHomogeneous_T_97 = xor(_pmaPgLevelHomogeneous_T_17, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pmaPgLevelHomogeneous_T_98 = cvt(_pmaPgLevelHomogeneous_T_97) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pmaPgLevelHomogeneous_T_99 = and(_pmaPgLevelHomogeneous_T_98, asSInt(UInt<33>(0h98010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_100 = asSInt(_pmaPgLevelHomogeneous_T_99) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_101 = eq(_pmaPgLevelHomogeneous_T_100, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pmaPgLevelHomogeneous_T_102 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_101) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:66] node _pmaPgLevelHomogeneous_T_103 = eq(_pmaPgLevelHomogeneous_T_102, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _pmaPgLevelHomogeneous_T_104 = xor(_pmaPgLevelHomogeneous_T_17, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pmaPgLevelHomogeneous_T_105 = cvt(_pmaPgLevelHomogeneous_T_104) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pmaPgLevelHomogeneous_T_106 = and(_pmaPgLevelHomogeneous_T_105, asSInt(UInt<33>(0h98010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_107 = asSInt(_pmaPgLevelHomogeneous_T_106) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pmaPgLevelHomogeneous_T_108 = eq(_pmaPgLevelHomogeneous_T_107, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pmaPgLevelHomogeneous_T_109 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_108) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:66] node _pmaPgLevelHomogeneous_T_110 = eq(_pmaPgLevelHomogeneous_T_109, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/TLBPermissions.scala 87:22] node _pmaHomogeneous_T = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmaHomogeneous_T_1 = mux(_pmaHomogeneous_T, pmaPgLevelHomogeneous_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmaHomogeneous_T_2 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmaHomogeneous_T_3 = mux(_pmaHomogeneous_T_2, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmaHomogeneous_T_4 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node pmaHomogeneous = mux(_pmaHomogeneous_T_4, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T = shl(r_pte.ppn, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 548:80] wire _pmpHomogeneous_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 137:40] connect _pmpHomogeneous_WIRE.mask, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 137:40] connect _pmpHomogeneous_WIRE.addr, UInt<30>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 137:40] connect _pmpHomogeneous_WIRE.cfg.r, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 137:40] connect _pmpHomogeneous_WIRE.cfg.w, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 137:40] connect _pmpHomogeneous_WIRE.cfg.x, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 137:40] connect _pmpHomogeneous_WIRE.cfg.a, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 137:40] connect _pmpHomogeneous_WIRE.cfg.res, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 137:40] connect _pmpHomogeneous_WIRE.cfg.l, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 137:40] node _pmpHomogeneous_T_1 = bits(io.dpath.pmp[0].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _pmpHomogeneous_maskHomogeneous_T = bits(io.dpath.pmp[0].mask, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_1 = bits(io.dpath.pmp[0].mask, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_2 = bits(io.dpath.pmp[0].mask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_3 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_maskHomogeneous_T_4 = mux(_pmpHomogeneous_maskHomogeneous_T_3, _pmpHomogeneous_maskHomogeneous_T_1, _pmpHomogeneous_maskHomogeneous_T) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_maskHomogeneous_T_5 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_maskHomogeneous_T_6 = mux(_pmpHomogeneous_maskHomogeneous_T_5, _pmpHomogeneous_maskHomogeneous_T_2, _pmpHomogeneous_maskHomogeneous_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_maskHomogeneous_T_7 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node pmpHomogeneous_maskHomogeneous = mux(_pmpHomogeneous_maskHomogeneous_T_7, _pmpHomogeneous_maskHomogeneous_T_2, _pmpHomogeneous_maskHomogeneous_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_2 = shl(io.dpath.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_3 = not(_pmpHomogeneous_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_4 = or(_pmpHomogeneous_T_3, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_5 = not(_pmpHomogeneous_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_6 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_7 = shr(_pmpHomogeneous_T_6, 30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_8 = neq(_pmpHomogeneous_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_9 = shl(io.dpath.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_10 = not(_pmpHomogeneous_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_11 = or(_pmpHomogeneous_T_10, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_12 = not(_pmpHomogeneous_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_13 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_14 = shr(_pmpHomogeneous_T_13, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_15 = neq(_pmpHomogeneous_T_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_16 = shl(io.dpath.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_17 = not(_pmpHomogeneous_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_18 = or(_pmpHomogeneous_T_17, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_19 = not(_pmpHomogeneous_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_20 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_21 = shr(_pmpHomogeneous_T_20, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_22 = neq(_pmpHomogeneous_T_21, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_23 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_24 = mux(_pmpHomogeneous_T_23, _pmpHomogeneous_T_15, _pmpHomogeneous_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_25 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_26 = mux(_pmpHomogeneous_T_25, _pmpHomogeneous_T_22, _pmpHomogeneous_T_24) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_27 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_28 = mux(_pmpHomogeneous_T_27, _pmpHomogeneous_T_22, _pmpHomogeneous_T_26) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_29 = or(pmpHomogeneous_maskHomogeneous, _pmpHomogeneous_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:21] node _pmpHomogeneous_T_30 = bits(io.dpath.pmp[0].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _pmpHomogeneous_T_31 = eq(_pmpHomogeneous_T_30, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:45] node _pmpHomogeneous_beginsAfterLower_T = shl(_pmpHomogeneous_WIRE.addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_beginsAfterLower_T_1 = not(_pmpHomogeneous_beginsAfterLower_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_beginsAfterLower_T_2 = or(_pmpHomogeneous_beginsAfterLower_T_1, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_beginsAfterLower_T_3 = not(_pmpHomogeneous_beginsAfterLower_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_beginsAfterLower_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 106:32] node pmpHomogeneous_beginsAfterLower = eq(_pmpHomogeneous_beginsAfterLower_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 106:28] node _pmpHomogeneous_beginsAfterUpper_T = shl(io.dpath.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_beginsAfterUpper_T_1 = not(_pmpHomogeneous_beginsAfterUpper_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_beginsAfterUpper_T_2 = or(_pmpHomogeneous_beginsAfterUpper_T_1, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_beginsAfterUpper_T_3 = not(_pmpHomogeneous_beginsAfterUpper_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_beginsAfterUpper_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 107:32] node pmpHomogeneous_beginsAfterUpper = eq(_pmpHomogeneous_beginsAfterUpper_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 107:28] node _pmpHomogeneous_pgMask_T = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_pgMask_T_1 = mux(_pmpHomogeneous_pgMask_T, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_pgMask_T_2 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_pgMask_T_3 = mux(_pmpHomogeneous_pgMask_T_2, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_pgMask_T_4 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node pmpHomogeneous_pgMask = mux(_pmpHomogeneous_pgMask_T_4, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_endsBeforeLower_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:30] node _pmpHomogeneous_endsBeforeLower_T_1 = shl(_pmpHomogeneous_WIRE.addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_endsBeforeLower_T_2 = not(_pmpHomogeneous_endsBeforeLower_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_endsBeforeLower_T_3 = or(_pmpHomogeneous_endsBeforeLower_T_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_endsBeforeLower_T_4 = not(_pmpHomogeneous_endsBeforeLower_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_endsBeforeLower_T_5 = and(_pmpHomogeneous_endsBeforeLower_T_4, pmpHomogeneous_pgMask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:58] node pmpHomogeneous_endsBeforeLower = lt(_pmpHomogeneous_endsBeforeLower_T, _pmpHomogeneous_endsBeforeLower_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:40] node _pmpHomogeneous_endsBeforeUpper_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:30] node _pmpHomogeneous_endsBeforeUpper_T_1 = shl(io.dpath.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_endsBeforeUpper_T_2 = not(_pmpHomogeneous_endsBeforeUpper_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_endsBeforeUpper_T_3 = or(_pmpHomogeneous_endsBeforeUpper_T_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_endsBeforeUpper_T_4 = not(_pmpHomogeneous_endsBeforeUpper_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_endsBeforeUpper_T_5 = and(_pmpHomogeneous_endsBeforeUpper_T_4, pmpHomogeneous_pgMask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:53] node pmpHomogeneous_endsBeforeUpper = lt(_pmpHomogeneous_endsBeforeUpper_T, _pmpHomogeneous_endsBeforeUpper_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:40] node _pmpHomogeneous_T_32 = or(pmpHomogeneous_endsBeforeLower, pmpHomogeneous_beginsAfterUpper) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:21] node _pmpHomogeneous_T_33 = and(pmpHomogeneous_beginsAfterLower, pmpHomogeneous_endsBeforeUpper) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:62] node _pmpHomogeneous_T_34 = or(_pmpHomogeneous_T_32, _pmpHomogeneous_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:41] node _pmpHomogeneous_T_35 = or(_pmpHomogeneous_T_31, _pmpHomogeneous_T_34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:58] node _pmpHomogeneous_T_36 = mux(_pmpHomogeneous_T_1, _pmpHomogeneous_T_29, _pmpHomogeneous_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:8] node _pmpHomogeneous_T_37 = and(UInt<1>(0h1), _pmpHomogeneous_T_36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 138:10] node _pmpHomogeneous_T_38 = bits(io.dpath.pmp[1].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _pmpHomogeneous_maskHomogeneous_T_8 = bits(io.dpath.pmp[1].mask, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_9 = bits(io.dpath.pmp[1].mask, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_10 = bits(io.dpath.pmp[1].mask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_11 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_maskHomogeneous_T_12 = mux(_pmpHomogeneous_maskHomogeneous_T_11, _pmpHomogeneous_maskHomogeneous_T_9, _pmpHomogeneous_maskHomogeneous_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_maskHomogeneous_T_13 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_maskHomogeneous_T_14 = mux(_pmpHomogeneous_maskHomogeneous_T_13, _pmpHomogeneous_maskHomogeneous_T_10, _pmpHomogeneous_maskHomogeneous_T_12) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_maskHomogeneous_T_15 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node pmpHomogeneous_maskHomogeneous_1 = mux(_pmpHomogeneous_maskHomogeneous_T_15, _pmpHomogeneous_maskHomogeneous_T_10, _pmpHomogeneous_maskHomogeneous_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_39 = shl(io.dpath.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_40 = not(_pmpHomogeneous_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_41 = or(_pmpHomogeneous_T_40, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_42 = not(_pmpHomogeneous_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_43 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_42) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_44 = shr(_pmpHomogeneous_T_43, 30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_45 = neq(_pmpHomogeneous_T_44, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_46 = shl(io.dpath.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_47 = not(_pmpHomogeneous_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_48 = or(_pmpHomogeneous_T_47, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_49 = not(_pmpHomogeneous_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_50 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_51 = shr(_pmpHomogeneous_T_50, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_52 = neq(_pmpHomogeneous_T_51, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_53 = shl(io.dpath.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_54 = not(_pmpHomogeneous_T_53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_55 = or(_pmpHomogeneous_T_54, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_56 = not(_pmpHomogeneous_T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_57 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_58 = shr(_pmpHomogeneous_T_57, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_59 = neq(_pmpHomogeneous_T_58, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_60 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_61 = mux(_pmpHomogeneous_T_60, _pmpHomogeneous_T_52, _pmpHomogeneous_T_45) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_62 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_63 = mux(_pmpHomogeneous_T_62, _pmpHomogeneous_T_59, _pmpHomogeneous_T_61) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_64 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_65 = mux(_pmpHomogeneous_T_64, _pmpHomogeneous_T_59, _pmpHomogeneous_T_63) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_66 = or(pmpHomogeneous_maskHomogeneous_1, _pmpHomogeneous_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:21] node _pmpHomogeneous_T_67 = bits(io.dpath.pmp[1].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _pmpHomogeneous_T_68 = eq(_pmpHomogeneous_T_67, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:45] node _pmpHomogeneous_beginsAfterLower_T_5 = shl(io.dpath.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_beginsAfterLower_T_6 = not(_pmpHomogeneous_beginsAfterLower_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_beginsAfterLower_T_7 = or(_pmpHomogeneous_beginsAfterLower_T_6, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_beginsAfterLower_T_8 = not(_pmpHomogeneous_beginsAfterLower_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_beginsAfterLower_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 106:32] node pmpHomogeneous_beginsAfterLower_1 = eq(_pmpHomogeneous_beginsAfterLower_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 106:28] node _pmpHomogeneous_beginsAfterUpper_T_5 = shl(io.dpath.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_beginsAfterUpper_T_6 = not(_pmpHomogeneous_beginsAfterUpper_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_beginsAfterUpper_T_7 = or(_pmpHomogeneous_beginsAfterUpper_T_6, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_beginsAfterUpper_T_8 = not(_pmpHomogeneous_beginsAfterUpper_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_beginsAfterUpper_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 107:32] node pmpHomogeneous_beginsAfterUpper_1 = eq(_pmpHomogeneous_beginsAfterUpper_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 107:28] node _pmpHomogeneous_pgMask_T_5 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_pgMask_T_6 = mux(_pmpHomogeneous_pgMask_T_5, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_pgMask_T_7 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_pgMask_T_8 = mux(_pmpHomogeneous_pgMask_T_7, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_pgMask_T_9 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node pmpHomogeneous_pgMask_1 = mux(_pmpHomogeneous_pgMask_T_9, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_endsBeforeLower_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:30] node _pmpHomogeneous_endsBeforeLower_T_7 = shl(io.dpath.pmp[0].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_endsBeforeLower_T_8 = not(_pmpHomogeneous_endsBeforeLower_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_endsBeforeLower_T_9 = or(_pmpHomogeneous_endsBeforeLower_T_8, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_endsBeforeLower_T_10 = not(_pmpHomogeneous_endsBeforeLower_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_endsBeforeLower_T_11 = and(_pmpHomogeneous_endsBeforeLower_T_10, pmpHomogeneous_pgMask_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:58] node pmpHomogeneous_endsBeforeLower_1 = lt(_pmpHomogeneous_endsBeforeLower_T_6, _pmpHomogeneous_endsBeforeLower_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:40] node _pmpHomogeneous_endsBeforeUpper_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:30] node _pmpHomogeneous_endsBeforeUpper_T_7 = shl(io.dpath.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_endsBeforeUpper_T_8 = not(_pmpHomogeneous_endsBeforeUpper_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_endsBeforeUpper_T_9 = or(_pmpHomogeneous_endsBeforeUpper_T_8, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_endsBeforeUpper_T_10 = not(_pmpHomogeneous_endsBeforeUpper_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_endsBeforeUpper_T_11 = and(_pmpHomogeneous_endsBeforeUpper_T_10, pmpHomogeneous_pgMask_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:53] node pmpHomogeneous_endsBeforeUpper_1 = lt(_pmpHomogeneous_endsBeforeUpper_T_6, _pmpHomogeneous_endsBeforeUpper_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:40] node _pmpHomogeneous_T_69 = or(pmpHomogeneous_endsBeforeLower_1, pmpHomogeneous_beginsAfterUpper_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:21] node _pmpHomogeneous_T_70 = and(pmpHomogeneous_beginsAfterLower_1, pmpHomogeneous_endsBeforeUpper_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:62] node _pmpHomogeneous_T_71 = or(_pmpHomogeneous_T_69, _pmpHomogeneous_T_70) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:41] node _pmpHomogeneous_T_72 = or(_pmpHomogeneous_T_68, _pmpHomogeneous_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:58] node _pmpHomogeneous_T_73 = mux(_pmpHomogeneous_T_38, _pmpHomogeneous_T_66, _pmpHomogeneous_T_72) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:8] node _pmpHomogeneous_T_74 = and(_pmpHomogeneous_T_37, _pmpHomogeneous_T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 138:10] node _pmpHomogeneous_T_75 = bits(io.dpath.pmp[2].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _pmpHomogeneous_maskHomogeneous_T_16 = bits(io.dpath.pmp[2].mask, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_17 = bits(io.dpath.pmp[2].mask, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_18 = bits(io.dpath.pmp[2].mask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_19 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_maskHomogeneous_T_20 = mux(_pmpHomogeneous_maskHomogeneous_T_19, _pmpHomogeneous_maskHomogeneous_T_17, _pmpHomogeneous_maskHomogeneous_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_maskHomogeneous_T_21 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_maskHomogeneous_T_22 = mux(_pmpHomogeneous_maskHomogeneous_T_21, _pmpHomogeneous_maskHomogeneous_T_18, _pmpHomogeneous_maskHomogeneous_T_20) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_maskHomogeneous_T_23 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node pmpHomogeneous_maskHomogeneous_2 = mux(_pmpHomogeneous_maskHomogeneous_T_23, _pmpHomogeneous_maskHomogeneous_T_18, _pmpHomogeneous_maskHomogeneous_T_22) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_76 = shl(io.dpath.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_77 = not(_pmpHomogeneous_T_76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_78 = or(_pmpHomogeneous_T_77, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_79 = not(_pmpHomogeneous_T_78) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_80 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_79) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_81 = shr(_pmpHomogeneous_T_80, 30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_82 = neq(_pmpHomogeneous_T_81, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_83 = shl(io.dpath.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_84 = not(_pmpHomogeneous_T_83) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_85 = or(_pmpHomogeneous_T_84, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_86 = not(_pmpHomogeneous_T_85) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_87 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_86) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_88 = shr(_pmpHomogeneous_T_87, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_89 = neq(_pmpHomogeneous_T_88, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_90 = shl(io.dpath.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_91 = not(_pmpHomogeneous_T_90) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_92 = or(_pmpHomogeneous_T_91, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_93 = not(_pmpHomogeneous_T_92) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_94 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_93) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_95 = shr(_pmpHomogeneous_T_94, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_96 = neq(_pmpHomogeneous_T_95, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_97 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_98 = mux(_pmpHomogeneous_T_97, _pmpHomogeneous_T_89, _pmpHomogeneous_T_82) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_99 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_100 = mux(_pmpHomogeneous_T_99, _pmpHomogeneous_T_96, _pmpHomogeneous_T_98) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_101 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_102 = mux(_pmpHomogeneous_T_101, _pmpHomogeneous_T_96, _pmpHomogeneous_T_100) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_103 = or(pmpHomogeneous_maskHomogeneous_2, _pmpHomogeneous_T_102) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:21] node _pmpHomogeneous_T_104 = bits(io.dpath.pmp[2].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _pmpHomogeneous_T_105 = eq(_pmpHomogeneous_T_104, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:45] node _pmpHomogeneous_beginsAfterLower_T_10 = shl(io.dpath.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_beginsAfterLower_T_11 = not(_pmpHomogeneous_beginsAfterLower_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_beginsAfterLower_T_12 = or(_pmpHomogeneous_beginsAfterLower_T_11, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_beginsAfterLower_T_13 = not(_pmpHomogeneous_beginsAfterLower_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_beginsAfterLower_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 106:32] node pmpHomogeneous_beginsAfterLower_2 = eq(_pmpHomogeneous_beginsAfterLower_T_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 106:28] node _pmpHomogeneous_beginsAfterUpper_T_10 = shl(io.dpath.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_beginsAfterUpper_T_11 = not(_pmpHomogeneous_beginsAfterUpper_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_beginsAfterUpper_T_12 = or(_pmpHomogeneous_beginsAfterUpper_T_11, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_beginsAfterUpper_T_13 = not(_pmpHomogeneous_beginsAfterUpper_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_beginsAfterUpper_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 107:32] node pmpHomogeneous_beginsAfterUpper_2 = eq(_pmpHomogeneous_beginsAfterUpper_T_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 107:28] node _pmpHomogeneous_pgMask_T_10 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_pgMask_T_11 = mux(_pmpHomogeneous_pgMask_T_10, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_pgMask_T_12 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_pgMask_T_13 = mux(_pmpHomogeneous_pgMask_T_12, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_pgMask_T_14 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node pmpHomogeneous_pgMask_2 = mux(_pmpHomogeneous_pgMask_T_14, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_endsBeforeLower_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:30] node _pmpHomogeneous_endsBeforeLower_T_13 = shl(io.dpath.pmp[1].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_endsBeforeLower_T_14 = not(_pmpHomogeneous_endsBeforeLower_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_endsBeforeLower_T_15 = or(_pmpHomogeneous_endsBeforeLower_T_14, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_endsBeforeLower_T_16 = not(_pmpHomogeneous_endsBeforeLower_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_endsBeforeLower_T_17 = and(_pmpHomogeneous_endsBeforeLower_T_16, pmpHomogeneous_pgMask_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:58] node pmpHomogeneous_endsBeforeLower_2 = lt(_pmpHomogeneous_endsBeforeLower_T_12, _pmpHomogeneous_endsBeforeLower_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:40] node _pmpHomogeneous_endsBeforeUpper_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:30] node _pmpHomogeneous_endsBeforeUpper_T_13 = shl(io.dpath.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_endsBeforeUpper_T_14 = not(_pmpHomogeneous_endsBeforeUpper_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_endsBeforeUpper_T_15 = or(_pmpHomogeneous_endsBeforeUpper_T_14, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_endsBeforeUpper_T_16 = not(_pmpHomogeneous_endsBeforeUpper_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_endsBeforeUpper_T_17 = and(_pmpHomogeneous_endsBeforeUpper_T_16, pmpHomogeneous_pgMask_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:53] node pmpHomogeneous_endsBeforeUpper_2 = lt(_pmpHomogeneous_endsBeforeUpper_T_12, _pmpHomogeneous_endsBeforeUpper_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:40] node _pmpHomogeneous_T_106 = or(pmpHomogeneous_endsBeforeLower_2, pmpHomogeneous_beginsAfterUpper_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:21] node _pmpHomogeneous_T_107 = and(pmpHomogeneous_beginsAfterLower_2, pmpHomogeneous_endsBeforeUpper_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:62] node _pmpHomogeneous_T_108 = or(_pmpHomogeneous_T_106, _pmpHomogeneous_T_107) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:41] node _pmpHomogeneous_T_109 = or(_pmpHomogeneous_T_105, _pmpHomogeneous_T_108) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:58] node _pmpHomogeneous_T_110 = mux(_pmpHomogeneous_T_75, _pmpHomogeneous_T_103, _pmpHomogeneous_T_109) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:8] node _pmpHomogeneous_T_111 = and(_pmpHomogeneous_T_74, _pmpHomogeneous_T_110) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 138:10] node _pmpHomogeneous_T_112 = bits(io.dpath.pmp[3].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _pmpHomogeneous_maskHomogeneous_T_24 = bits(io.dpath.pmp[3].mask, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_25 = bits(io.dpath.pmp[3].mask, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_26 = bits(io.dpath.pmp[3].mask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_27 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_maskHomogeneous_T_28 = mux(_pmpHomogeneous_maskHomogeneous_T_27, _pmpHomogeneous_maskHomogeneous_T_25, _pmpHomogeneous_maskHomogeneous_T_24) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_maskHomogeneous_T_29 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_maskHomogeneous_T_30 = mux(_pmpHomogeneous_maskHomogeneous_T_29, _pmpHomogeneous_maskHomogeneous_T_26, _pmpHomogeneous_maskHomogeneous_T_28) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_maskHomogeneous_T_31 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node pmpHomogeneous_maskHomogeneous_3 = mux(_pmpHomogeneous_maskHomogeneous_T_31, _pmpHomogeneous_maskHomogeneous_T_26, _pmpHomogeneous_maskHomogeneous_T_30) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_113 = shl(io.dpath.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_114 = not(_pmpHomogeneous_T_113) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_115 = or(_pmpHomogeneous_T_114, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_116 = not(_pmpHomogeneous_T_115) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_117 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_116) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_118 = shr(_pmpHomogeneous_T_117, 30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_119 = neq(_pmpHomogeneous_T_118, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_120 = shl(io.dpath.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_121 = not(_pmpHomogeneous_T_120) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_122 = or(_pmpHomogeneous_T_121, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_123 = not(_pmpHomogeneous_T_122) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_124 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_123) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_125 = shr(_pmpHomogeneous_T_124, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_126 = neq(_pmpHomogeneous_T_125, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_127 = shl(io.dpath.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_128 = not(_pmpHomogeneous_T_127) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_129 = or(_pmpHomogeneous_T_128, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_130 = not(_pmpHomogeneous_T_129) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_131 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_130) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_132 = shr(_pmpHomogeneous_T_131, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_133 = neq(_pmpHomogeneous_T_132, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_134 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_135 = mux(_pmpHomogeneous_T_134, _pmpHomogeneous_T_126, _pmpHomogeneous_T_119) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_136 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_137 = mux(_pmpHomogeneous_T_136, _pmpHomogeneous_T_133, _pmpHomogeneous_T_135) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_138 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_139 = mux(_pmpHomogeneous_T_138, _pmpHomogeneous_T_133, _pmpHomogeneous_T_137) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_140 = or(pmpHomogeneous_maskHomogeneous_3, _pmpHomogeneous_T_139) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:21] node _pmpHomogeneous_T_141 = bits(io.dpath.pmp[3].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _pmpHomogeneous_T_142 = eq(_pmpHomogeneous_T_141, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:45] node _pmpHomogeneous_beginsAfterLower_T_15 = shl(io.dpath.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_beginsAfterLower_T_16 = not(_pmpHomogeneous_beginsAfterLower_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_beginsAfterLower_T_17 = or(_pmpHomogeneous_beginsAfterLower_T_16, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_beginsAfterLower_T_18 = not(_pmpHomogeneous_beginsAfterLower_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_beginsAfterLower_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 106:32] node pmpHomogeneous_beginsAfterLower_3 = eq(_pmpHomogeneous_beginsAfterLower_T_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 106:28] node _pmpHomogeneous_beginsAfterUpper_T_15 = shl(io.dpath.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_beginsAfterUpper_T_16 = not(_pmpHomogeneous_beginsAfterUpper_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_beginsAfterUpper_T_17 = or(_pmpHomogeneous_beginsAfterUpper_T_16, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_beginsAfterUpper_T_18 = not(_pmpHomogeneous_beginsAfterUpper_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_beginsAfterUpper_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 107:32] node pmpHomogeneous_beginsAfterUpper_3 = eq(_pmpHomogeneous_beginsAfterUpper_T_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 107:28] node _pmpHomogeneous_pgMask_T_15 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_pgMask_T_16 = mux(_pmpHomogeneous_pgMask_T_15, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_pgMask_T_17 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_pgMask_T_18 = mux(_pmpHomogeneous_pgMask_T_17, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_pgMask_T_19 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node pmpHomogeneous_pgMask_3 = mux(_pmpHomogeneous_pgMask_T_19, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_endsBeforeLower_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:30] node _pmpHomogeneous_endsBeforeLower_T_19 = shl(io.dpath.pmp[2].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_endsBeforeLower_T_20 = not(_pmpHomogeneous_endsBeforeLower_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_endsBeforeLower_T_21 = or(_pmpHomogeneous_endsBeforeLower_T_20, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_endsBeforeLower_T_22 = not(_pmpHomogeneous_endsBeforeLower_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_endsBeforeLower_T_23 = and(_pmpHomogeneous_endsBeforeLower_T_22, pmpHomogeneous_pgMask_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:58] node pmpHomogeneous_endsBeforeLower_3 = lt(_pmpHomogeneous_endsBeforeLower_T_18, _pmpHomogeneous_endsBeforeLower_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:40] node _pmpHomogeneous_endsBeforeUpper_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:30] node _pmpHomogeneous_endsBeforeUpper_T_19 = shl(io.dpath.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_endsBeforeUpper_T_20 = not(_pmpHomogeneous_endsBeforeUpper_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_endsBeforeUpper_T_21 = or(_pmpHomogeneous_endsBeforeUpper_T_20, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_endsBeforeUpper_T_22 = not(_pmpHomogeneous_endsBeforeUpper_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_endsBeforeUpper_T_23 = and(_pmpHomogeneous_endsBeforeUpper_T_22, pmpHomogeneous_pgMask_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:53] node pmpHomogeneous_endsBeforeUpper_3 = lt(_pmpHomogeneous_endsBeforeUpper_T_18, _pmpHomogeneous_endsBeforeUpper_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:40] node _pmpHomogeneous_T_143 = or(pmpHomogeneous_endsBeforeLower_3, pmpHomogeneous_beginsAfterUpper_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:21] node _pmpHomogeneous_T_144 = and(pmpHomogeneous_beginsAfterLower_3, pmpHomogeneous_endsBeforeUpper_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:62] node _pmpHomogeneous_T_145 = or(_pmpHomogeneous_T_143, _pmpHomogeneous_T_144) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:41] node _pmpHomogeneous_T_146 = or(_pmpHomogeneous_T_142, _pmpHomogeneous_T_145) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:58] node _pmpHomogeneous_T_147 = mux(_pmpHomogeneous_T_112, _pmpHomogeneous_T_140, _pmpHomogeneous_T_146) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:8] node _pmpHomogeneous_T_148 = and(_pmpHomogeneous_T_111, _pmpHomogeneous_T_147) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 138:10] node _pmpHomogeneous_T_149 = bits(io.dpath.pmp[4].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _pmpHomogeneous_maskHomogeneous_T_32 = bits(io.dpath.pmp[4].mask, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_33 = bits(io.dpath.pmp[4].mask, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_34 = bits(io.dpath.pmp[4].mask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_35 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_maskHomogeneous_T_36 = mux(_pmpHomogeneous_maskHomogeneous_T_35, _pmpHomogeneous_maskHomogeneous_T_33, _pmpHomogeneous_maskHomogeneous_T_32) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_maskHomogeneous_T_37 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_maskHomogeneous_T_38 = mux(_pmpHomogeneous_maskHomogeneous_T_37, _pmpHomogeneous_maskHomogeneous_T_34, _pmpHomogeneous_maskHomogeneous_T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_maskHomogeneous_T_39 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node pmpHomogeneous_maskHomogeneous_4 = mux(_pmpHomogeneous_maskHomogeneous_T_39, _pmpHomogeneous_maskHomogeneous_T_34, _pmpHomogeneous_maskHomogeneous_T_38) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_150 = shl(io.dpath.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_151 = not(_pmpHomogeneous_T_150) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_152 = or(_pmpHomogeneous_T_151, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_153 = not(_pmpHomogeneous_T_152) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_154 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_153) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_155 = shr(_pmpHomogeneous_T_154, 30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_156 = neq(_pmpHomogeneous_T_155, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_157 = shl(io.dpath.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_158 = not(_pmpHomogeneous_T_157) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_159 = or(_pmpHomogeneous_T_158, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_160 = not(_pmpHomogeneous_T_159) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_161 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_160) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_162 = shr(_pmpHomogeneous_T_161, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_163 = neq(_pmpHomogeneous_T_162, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_164 = shl(io.dpath.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_165 = not(_pmpHomogeneous_T_164) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_166 = or(_pmpHomogeneous_T_165, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_167 = not(_pmpHomogeneous_T_166) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_168 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_167) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_169 = shr(_pmpHomogeneous_T_168, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_170 = neq(_pmpHomogeneous_T_169, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_171 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_172 = mux(_pmpHomogeneous_T_171, _pmpHomogeneous_T_163, _pmpHomogeneous_T_156) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_173 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_174 = mux(_pmpHomogeneous_T_173, _pmpHomogeneous_T_170, _pmpHomogeneous_T_172) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_175 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_176 = mux(_pmpHomogeneous_T_175, _pmpHomogeneous_T_170, _pmpHomogeneous_T_174) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_177 = or(pmpHomogeneous_maskHomogeneous_4, _pmpHomogeneous_T_176) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:21] node _pmpHomogeneous_T_178 = bits(io.dpath.pmp[4].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _pmpHomogeneous_T_179 = eq(_pmpHomogeneous_T_178, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:45] node _pmpHomogeneous_beginsAfterLower_T_20 = shl(io.dpath.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_beginsAfterLower_T_21 = not(_pmpHomogeneous_beginsAfterLower_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_beginsAfterLower_T_22 = or(_pmpHomogeneous_beginsAfterLower_T_21, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_beginsAfterLower_T_23 = not(_pmpHomogeneous_beginsAfterLower_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_beginsAfterLower_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 106:32] node pmpHomogeneous_beginsAfterLower_4 = eq(_pmpHomogeneous_beginsAfterLower_T_24, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 106:28] node _pmpHomogeneous_beginsAfterUpper_T_20 = shl(io.dpath.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_beginsAfterUpper_T_21 = not(_pmpHomogeneous_beginsAfterUpper_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_beginsAfterUpper_T_22 = or(_pmpHomogeneous_beginsAfterUpper_T_21, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_beginsAfterUpper_T_23 = not(_pmpHomogeneous_beginsAfterUpper_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_beginsAfterUpper_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 107:32] node pmpHomogeneous_beginsAfterUpper_4 = eq(_pmpHomogeneous_beginsAfterUpper_T_24, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 107:28] node _pmpHomogeneous_pgMask_T_20 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_pgMask_T_21 = mux(_pmpHomogeneous_pgMask_T_20, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_pgMask_T_22 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_pgMask_T_23 = mux(_pmpHomogeneous_pgMask_T_22, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_21) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_pgMask_T_24 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node pmpHomogeneous_pgMask_4 = mux(_pmpHomogeneous_pgMask_T_24, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_23) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_endsBeforeLower_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:30] node _pmpHomogeneous_endsBeforeLower_T_25 = shl(io.dpath.pmp[3].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_endsBeforeLower_T_26 = not(_pmpHomogeneous_endsBeforeLower_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_endsBeforeLower_T_27 = or(_pmpHomogeneous_endsBeforeLower_T_26, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_endsBeforeLower_T_28 = not(_pmpHomogeneous_endsBeforeLower_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_endsBeforeLower_T_29 = and(_pmpHomogeneous_endsBeforeLower_T_28, pmpHomogeneous_pgMask_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:58] node pmpHomogeneous_endsBeforeLower_4 = lt(_pmpHomogeneous_endsBeforeLower_T_24, _pmpHomogeneous_endsBeforeLower_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:40] node _pmpHomogeneous_endsBeforeUpper_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:30] node _pmpHomogeneous_endsBeforeUpper_T_25 = shl(io.dpath.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_endsBeforeUpper_T_26 = not(_pmpHomogeneous_endsBeforeUpper_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_endsBeforeUpper_T_27 = or(_pmpHomogeneous_endsBeforeUpper_T_26, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_endsBeforeUpper_T_28 = not(_pmpHomogeneous_endsBeforeUpper_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_endsBeforeUpper_T_29 = and(_pmpHomogeneous_endsBeforeUpper_T_28, pmpHomogeneous_pgMask_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:53] node pmpHomogeneous_endsBeforeUpper_4 = lt(_pmpHomogeneous_endsBeforeUpper_T_24, _pmpHomogeneous_endsBeforeUpper_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:40] node _pmpHomogeneous_T_180 = or(pmpHomogeneous_endsBeforeLower_4, pmpHomogeneous_beginsAfterUpper_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:21] node _pmpHomogeneous_T_181 = and(pmpHomogeneous_beginsAfterLower_4, pmpHomogeneous_endsBeforeUpper_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:62] node _pmpHomogeneous_T_182 = or(_pmpHomogeneous_T_180, _pmpHomogeneous_T_181) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:41] node _pmpHomogeneous_T_183 = or(_pmpHomogeneous_T_179, _pmpHomogeneous_T_182) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:58] node _pmpHomogeneous_T_184 = mux(_pmpHomogeneous_T_149, _pmpHomogeneous_T_177, _pmpHomogeneous_T_183) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:8] node _pmpHomogeneous_T_185 = and(_pmpHomogeneous_T_148, _pmpHomogeneous_T_184) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 138:10] node _pmpHomogeneous_T_186 = bits(io.dpath.pmp[5].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _pmpHomogeneous_maskHomogeneous_T_40 = bits(io.dpath.pmp[5].mask, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_41 = bits(io.dpath.pmp[5].mask, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_42 = bits(io.dpath.pmp[5].mask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_43 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_maskHomogeneous_T_44 = mux(_pmpHomogeneous_maskHomogeneous_T_43, _pmpHomogeneous_maskHomogeneous_T_41, _pmpHomogeneous_maskHomogeneous_T_40) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_maskHomogeneous_T_45 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_maskHomogeneous_T_46 = mux(_pmpHomogeneous_maskHomogeneous_T_45, _pmpHomogeneous_maskHomogeneous_T_42, _pmpHomogeneous_maskHomogeneous_T_44) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_maskHomogeneous_T_47 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node pmpHomogeneous_maskHomogeneous_5 = mux(_pmpHomogeneous_maskHomogeneous_T_47, _pmpHomogeneous_maskHomogeneous_T_42, _pmpHomogeneous_maskHomogeneous_T_46) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_187 = shl(io.dpath.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_188 = not(_pmpHomogeneous_T_187) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_189 = or(_pmpHomogeneous_T_188, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_190 = not(_pmpHomogeneous_T_189) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_191 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_190) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_192 = shr(_pmpHomogeneous_T_191, 30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_193 = neq(_pmpHomogeneous_T_192, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_194 = shl(io.dpath.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_195 = not(_pmpHomogeneous_T_194) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_196 = or(_pmpHomogeneous_T_195, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_197 = not(_pmpHomogeneous_T_196) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_198 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_197) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_199 = shr(_pmpHomogeneous_T_198, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_200 = neq(_pmpHomogeneous_T_199, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_201 = shl(io.dpath.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_202 = not(_pmpHomogeneous_T_201) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_203 = or(_pmpHomogeneous_T_202, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_204 = not(_pmpHomogeneous_T_203) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_205 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_204) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_206 = shr(_pmpHomogeneous_T_205, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_207 = neq(_pmpHomogeneous_T_206, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_208 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_209 = mux(_pmpHomogeneous_T_208, _pmpHomogeneous_T_200, _pmpHomogeneous_T_193) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_210 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_211 = mux(_pmpHomogeneous_T_210, _pmpHomogeneous_T_207, _pmpHomogeneous_T_209) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_212 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_213 = mux(_pmpHomogeneous_T_212, _pmpHomogeneous_T_207, _pmpHomogeneous_T_211) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_214 = or(pmpHomogeneous_maskHomogeneous_5, _pmpHomogeneous_T_213) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:21] node _pmpHomogeneous_T_215 = bits(io.dpath.pmp[5].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _pmpHomogeneous_T_216 = eq(_pmpHomogeneous_T_215, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:45] node _pmpHomogeneous_beginsAfterLower_T_25 = shl(io.dpath.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_beginsAfterLower_T_26 = not(_pmpHomogeneous_beginsAfterLower_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_beginsAfterLower_T_27 = or(_pmpHomogeneous_beginsAfterLower_T_26, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_beginsAfterLower_T_28 = not(_pmpHomogeneous_beginsAfterLower_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_beginsAfterLower_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 106:32] node pmpHomogeneous_beginsAfterLower_5 = eq(_pmpHomogeneous_beginsAfterLower_T_29, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 106:28] node _pmpHomogeneous_beginsAfterUpper_T_25 = shl(io.dpath.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_beginsAfterUpper_T_26 = not(_pmpHomogeneous_beginsAfterUpper_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_beginsAfterUpper_T_27 = or(_pmpHomogeneous_beginsAfterUpper_T_26, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_beginsAfterUpper_T_28 = not(_pmpHomogeneous_beginsAfterUpper_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_beginsAfterUpper_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 107:32] node pmpHomogeneous_beginsAfterUpper_5 = eq(_pmpHomogeneous_beginsAfterUpper_T_29, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 107:28] node _pmpHomogeneous_pgMask_T_25 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_pgMask_T_26 = mux(_pmpHomogeneous_pgMask_T_25, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_pgMask_T_27 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_pgMask_T_28 = mux(_pmpHomogeneous_pgMask_T_27, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_26) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_pgMask_T_29 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node pmpHomogeneous_pgMask_5 = mux(_pmpHomogeneous_pgMask_T_29, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_28) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_endsBeforeLower_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:30] node _pmpHomogeneous_endsBeforeLower_T_31 = shl(io.dpath.pmp[4].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_endsBeforeLower_T_32 = not(_pmpHomogeneous_endsBeforeLower_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_endsBeforeLower_T_33 = or(_pmpHomogeneous_endsBeforeLower_T_32, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_endsBeforeLower_T_34 = not(_pmpHomogeneous_endsBeforeLower_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_endsBeforeLower_T_35 = and(_pmpHomogeneous_endsBeforeLower_T_34, pmpHomogeneous_pgMask_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:58] node pmpHomogeneous_endsBeforeLower_5 = lt(_pmpHomogeneous_endsBeforeLower_T_30, _pmpHomogeneous_endsBeforeLower_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:40] node _pmpHomogeneous_endsBeforeUpper_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:30] node _pmpHomogeneous_endsBeforeUpper_T_31 = shl(io.dpath.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_endsBeforeUpper_T_32 = not(_pmpHomogeneous_endsBeforeUpper_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_endsBeforeUpper_T_33 = or(_pmpHomogeneous_endsBeforeUpper_T_32, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_endsBeforeUpper_T_34 = not(_pmpHomogeneous_endsBeforeUpper_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_endsBeforeUpper_T_35 = and(_pmpHomogeneous_endsBeforeUpper_T_34, pmpHomogeneous_pgMask_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:53] node pmpHomogeneous_endsBeforeUpper_5 = lt(_pmpHomogeneous_endsBeforeUpper_T_30, _pmpHomogeneous_endsBeforeUpper_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:40] node _pmpHomogeneous_T_217 = or(pmpHomogeneous_endsBeforeLower_5, pmpHomogeneous_beginsAfterUpper_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:21] node _pmpHomogeneous_T_218 = and(pmpHomogeneous_beginsAfterLower_5, pmpHomogeneous_endsBeforeUpper_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:62] node _pmpHomogeneous_T_219 = or(_pmpHomogeneous_T_217, _pmpHomogeneous_T_218) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:41] node _pmpHomogeneous_T_220 = or(_pmpHomogeneous_T_216, _pmpHomogeneous_T_219) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:58] node _pmpHomogeneous_T_221 = mux(_pmpHomogeneous_T_186, _pmpHomogeneous_T_214, _pmpHomogeneous_T_220) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:8] node _pmpHomogeneous_T_222 = and(_pmpHomogeneous_T_185, _pmpHomogeneous_T_221) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 138:10] node _pmpHomogeneous_T_223 = bits(io.dpath.pmp[6].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _pmpHomogeneous_maskHomogeneous_T_48 = bits(io.dpath.pmp[6].mask, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_49 = bits(io.dpath.pmp[6].mask, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_50 = bits(io.dpath.pmp[6].mask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_51 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_maskHomogeneous_T_52 = mux(_pmpHomogeneous_maskHomogeneous_T_51, _pmpHomogeneous_maskHomogeneous_T_49, _pmpHomogeneous_maskHomogeneous_T_48) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_maskHomogeneous_T_53 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_maskHomogeneous_T_54 = mux(_pmpHomogeneous_maskHomogeneous_T_53, _pmpHomogeneous_maskHomogeneous_T_50, _pmpHomogeneous_maskHomogeneous_T_52) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_maskHomogeneous_T_55 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node pmpHomogeneous_maskHomogeneous_6 = mux(_pmpHomogeneous_maskHomogeneous_T_55, _pmpHomogeneous_maskHomogeneous_T_50, _pmpHomogeneous_maskHomogeneous_T_54) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_224 = shl(io.dpath.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_225 = not(_pmpHomogeneous_T_224) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_226 = or(_pmpHomogeneous_T_225, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_227 = not(_pmpHomogeneous_T_226) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_228 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_227) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_229 = shr(_pmpHomogeneous_T_228, 30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_230 = neq(_pmpHomogeneous_T_229, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_231 = shl(io.dpath.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_232 = not(_pmpHomogeneous_T_231) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_233 = or(_pmpHomogeneous_T_232, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_234 = not(_pmpHomogeneous_T_233) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_235 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_234) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_236 = shr(_pmpHomogeneous_T_235, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_237 = neq(_pmpHomogeneous_T_236, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_238 = shl(io.dpath.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_239 = not(_pmpHomogeneous_T_238) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_240 = or(_pmpHomogeneous_T_239, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_241 = not(_pmpHomogeneous_T_240) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_242 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_241) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_243 = shr(_pmpHomogeneous_T_242, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_244 = neq(_pmpHomogeneous_T_243, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_245 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_246 = mux(_pmpHomogeneous_T_245, _pmpHomogeneous_T_237, _pmpHomogeneous_T_230) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_247 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_248 = mux(_pmpHomogeneous_T_247, _pmpHomogeneous_T_244, _pmpHomogeneous_T_246) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_249 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_250 = mux(_pmpHomogeneous_T_249, _pmpHomogeneous_T_244, _pmpHomogeneous_T_248) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_251 = or(pmpHomogeneous_maskHomogeneous_6, _pmpHomogeneous_T_250) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:21] node _pmpHomogeneous_T_252 = bits(io.dpath.pmp[6].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _pmpHomogeneous_T_253 = eq(_pmpHomogeneous_T_252, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:45] node _pmpHomogeneous_beginsAfterLower_T_30 = shl(io.dpath.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_beginsAfterLower_T_31 = not(_pmpHomogeneous_beginsAfterLower_T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_beginsAfterLower_T_32 = or(_pmpHomogeneous_beginsAfterLower_T_31, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_beginsAfterLower_T_33 = not(_pmpHomogeneous_beginsAfterLower_T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_beginsAfterLower_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 106:32] node pmpHomogeneous_beginsAfterLower_6 = eq(_pmpHomogeneous_beginsAfterLower_T_34, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 106:28] node _pmpHomogeneous_beginsAfterUpper_T_30 = shl(io.dpath.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_beginsAfterUpper_T_31 = not(_pmpHomogeneous_beginsAfterUpper_T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_beginsAfterUpper_T_32 = or(_pmpHomogeneous_beginsAfterUpper_T_31, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_beginsAfterUpper_T_33 = not(_pmpHomogeneous_beginsAfterUpper_T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_beginsAfterUpper_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 107:32] node pmpHomogeneous_beginsAfterUpper_6 = eq(_pmpHomogeneous_beginsAfterUpper_T_34, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 107:28] node _pmpHomogeneous_pgMask_T_30 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_pgMask_T_31 = mux(_pmpHomogeneous_pgMask_T_30, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_pgMask_T_32 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_pgMask_T_33 = mux(_pmpHomogeneous_pgMask_T_32, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_31) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_pgMask_T_34 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node pmpHomogeneous_pgMask_6 = mux(_pmpHomogeneous_pgMask_T_34, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_33) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_endsBeforeLower_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:30] node _pmpHomogeneous_endsBeforeLower_T_37 = shl(io.dpath.pmp[5].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_endsBeforeLower_T_38 = not(_pmpHomogeneous_endsBeforeLower_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_endsBeforeLower_T_39 = or(_pmpHomogeneous_endsBeforeLower_T_38, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_endsBeforeLower_T_40 = not(_pmpHomogeneous_endsBeforeLower_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_endsBeforeLower_T_41 = and(_pmpHomogeneous_endsBeforeLower_T_40, pmpHomogeneous_pgMask_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:58] node pmpHomogeneous_endsBeforeLower_6 = lt(_pmpHomogeneous_endsBeforeLower_T_36, _pmpHomogeneous_endsBeforeLower_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:40] node _pmpHomogeneous_endsBeforeUpper_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:30] node _pmpHomogeneous_endsBeforeUpper_T_37 = shl(io.dpath.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_endsBeforeUpper_T_38 = not(_pmpHomogeneous_endsBeforeUpper_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_endsBeforeUpper_T_39 = or(_pmpHomogeneous_endsBeforeUpper_T_38, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_endsBeforeUpper_T_40 = not(_pmpHomogeneous_endsBeforeUpper_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_endsBeforeUpper_T_41 = and(_pmpHomogeneous_endsBeforeUpper_T_40, pmpHomogeneous_pgMask_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:53] node pmpHomogeneous_endsBeforeUpper_6 = lt(_pmpHomogeneous_endsBeforeUpper_T_36, _pmpHomogeneous_endsBeforeUpper_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:40] node _pmpHomogeneous_T_254 = or(pmpHomogeneous_endsBeforeLower_6, pmpHomogeneous_beginsAfterUpper_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:21] node _pmpHomogeneous_T_255 = and(pmpHomogeneous_beginsAfterLower_6, pmpHomogeneous_endsBeforeUpper_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:62] node _pmpHomogeneous_T_256 = or(_pmpHomogeneous_T_254, _pmpHomogeneous_T_255) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:41] node _pmpHomogeneous_T_257 = or(_pmpHomogeneous_T_253, _pmpHomogeneous_T_256) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:58] node _pmpHomogeneous_T_258 = mux(_pmpHomogeneous_T_223, _pmpHomogeneous_T_251, _pmpHomogeneous_T_257) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:8] node _pmpHomogeneous_T_259 = and(_pmpHomogeneous_T_222, _pmpHomogeneous_T_258) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 138:10] node _pmpHomogeneous_T_260 = bits(io.dpath.pmp[7].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _pmpHomogeneous_maskHomogeneous_T_56 = bits(io.dpath.pmp[7].mask, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_57 = bits(io.dpath.pmp[7].mask, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_58 = bits(io.dpath.pmp[7].mask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 97:93] node _pmpHomogeneous_maskHomogeneous_T_59 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_maskHomogeneous_T_60 = mux(_pmpHomogeneous_maskHomogeneous_T_59, _pmpHomogeneous_maskHomogeneous_T_57, _pmpHomogeneous_maskHomogeneous_T_56) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_maskHomogeneous_T_61 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_maskHomogeneous_T_62 = mux(_pmpHomogeneous_maskHomogeneous_T_61, _pmpHomogeneous_maskHomogeneous_T_58, _pmpHomogeneous_maskHomogeneous_T_60) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_maskHomogeneous_T_63 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node pmpHomogeneous_maskHomogeneous_7 = mux(_pmpHomogeneous_maskHomogeneous_T_63, _pmpHomogeneous_maskHomogeneous_T_58, _pmpHomogeneous_maskHomogeneous_T_62) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_261 = shl(io.dpath.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_262 = not(_pmpHomogeneous_T_261) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_263 = or(_pmpHomogeneous_T_262, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_264 = not(_pmpHomogeneous_T_263) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_265 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_264) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_266 = shr(_pmpHomogeneous_T_265, 30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_267 = neq(_pmpHomogeneous_T_266, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_268 = shl(io.dpath.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_269 = not(_pmpHomogeneous_T_268) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_270 = or(_pmpHomogeneous_T_269, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_271 = not(_pmpHomogeneous_T_270) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_272 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_271) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_273 = shr(_pmpHomogeneous_T_272, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_274 = neq(_pmpHomogeneous_T_273, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_275 = shl(io.dpath.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_T_276 = not(_pmpHomogeneous_T_275) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_T_277 = or(_pmpHomogeneous_T_276, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_T_278 = not(_pmpHomogeneous_T_277) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_T_279 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_278) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:53] node _pmpHomogeneous_T_280 = shr(_pmpHomogeneous_T_279, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:66] node _pmpHomogeneous_T_281 = neq(_pmpHomogeneous_T_280, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:78] node _pmpHomogeneous_T_282 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_283 = mux(_pmpHomogeneous_T_282, _pmpHomogeneous_T_274, _pmpHomogeneous_T_267) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_284 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_285 = mux(_pmpHomogeneous_T_284, _pmpHomogeneous_T_281, _pmpHomogeneous_T_283) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_286 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_T_287 = mux(_pmpHomogeneous_T_286, _pmpHomogeneous_T_281, _pmpHomogeneous_T_285) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_T_288 = or(pmpHomogeneous_maskHomogeneous_7, _pmpHomogeneous_T_287) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 98:21] node _pmpHomogeneous_T_289 = bits(io.dpath.pmp[7].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _pmpHomogeneous_T_290 = eq(_pmpHomogeneous_T_289, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:45] node _pmpHomogeneous_beginsAfterLower_T_35 = shl(io.dpath.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_beginsAfterLower_T_36 = not(_pmpHomogeneous_beginsAfterLower_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_beginsAfterLower_T_37 = or(_pmpHomogeneous_beginsAfterLower_T_36, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_beginsAfterLower_T_38 = not(_pmpHomogeneous_beginsAfterLower_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_beginsAfterLower_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 106:32] node pmpHomogeneous_beginsAfterLower_7 = eq(_pmpHomogeneous_beginsAfterLower_T_39, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 106:28] node _pmpHomogeneous_beginsAfterUpper_T_35 = shl(io.dpath.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_beginsAfterUpper_T_36 = not(_pmpHomogeneous_beginsAfterUpper_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_beginsAfterUpper_T_37 = or(_pmpHomogeneous_beginsAfterUpper_T_36, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_beginsAfterUpper_T_38 = not(_pmpHomogeneous_beginsAfterUpper_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_beginsAfterUpper_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 107:32] node pmpHomogeneous_beginsAfterUpper_7 = eq(_pmpHomogeneous_beginsAfterUpper_T_39, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 107:28] node _pmpHomogeneous_pgMask_T_35 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_pgMask_T_36 = mux(_pmpHomogeneous_pgMask_T_35, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_pgMask_T_37 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _pmpHomogeneous_pgMask_T_38 = mux(_pmpHomogeneous_pgMask_T_37, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_pgMask_T_39 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node pmpHomogeneous_pgMask_7 = mux(_pmpHomogeneous_pgMask_T_39, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_38) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _pmpHomogeneous_endsBeforeLower_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:30] node _pmpHomogeneous_endsBeforeLower_T_43 = shl(io.dpath.pmp[6].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_endsBeforeLower_T_44 = not(_pmpHomogeneous_endsBeforeLower_T_43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_endsBeforeLower_T_45 = or(_pmpHomogeneous_endsBeforeLower_T_44, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_endsBeforeLower_T_46 = not(_pmpHomogeneous_endsBeforeLower_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_endsBeforeLower_T_47 = and(_pmpHomogeneous_endsBeforeLower_T_46, pmpHomogeneous_pgMask_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:58] node pmpHomogeneous_endsBeforeLower_7 = lt(_pmpHomogeneous_endsBeforeLower_T_42, _pmpHomogeneous_endsBeforeLower_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 110:40] node _pmpHomogeneous_endsBeforeUpper_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:30] node _pmpHomogeneous_endsBeforeUpper_T_43 = shl(io.dpath.pmp[7].addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:36] node _pmpHomogeneous_endsBeforeUpper_T_44 = not(_pmpHomogeneous_endsBeforeUpper_T_43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:29] node _pmpHomogeneous_endsBeforeUpper_T_45 = or(_pmpHomogeneous_endsBeforeUpper_T_44, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:48] node _pmpHomogeneous_endsBeforeUpper_T_46 = not(_pmpHomogeneous_endsBeforeUpper_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 60:27] node _pmpHomogeneous_endsBeforeUpper_T_47 = and(_pmpHomogeneous_endsBeforeUpper_T_46, pmpHomogeneous_pgMask_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:53] node pmpHomogeneous_endsBeforeUpper_7 = lt(_pmpHomogeneous_endsBeforeUpper_T_42, _pmpHomogeneous_endsBeforeUpper_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 111:40] node _pmpHomogeneous_T_291 = or(pmpHomogeneous_endsBeforeLower_7, pmpHomogeneous_beginsAfterUpper_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:21] node _pmpHomogeneous_T_292 = and(pmpHomogeneous_beginsAfterLower_7, pmpHomogeneous_endsBeforeUpper_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:62] node _pmpHomogeneous_T_293 = or(_pmpHomogeneous_T_291, _pmpHomogeneous_T_292) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 113:41] node _pmpHomogeneous_T_294 = or(_pmpHomogeneous_T_290, _pmpHomogeneous_T_293) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:58] node _pmpHomogeneous_T_295 = mux(_pmpHomogeneous_T_260, _pmpHomogeneous_T_288, _pmpHomogeneous_T_294) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 118:8] node pmpHomogeneous = and(_pmpHomogeneous_T_259, _pmpHomogeneous_T_295) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 138:10] node homogeneous = and(pmaHomogeneous, pmpHomogeneous) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 549:36] connect io.requestor[0].resp.valid, resp_valid[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 552:32] connect io.requestor[0].resp.bits.ae_ptw, resp_ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 553:38] connect io.requestor[0].resp.bits.ae_final, resp_ae_final @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 554:40] connect io.requestor[0].resp.bits.pf, resp_pf @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 555:34] connect io.requestor[0].resp.bits.gf, resp_gf @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 556:34] connect io.requestor[0].resp.bits.hr, resp_hr @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 557:34] connect io.requestor[0].resp.bits.hw, resp_hw @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 558:34] connect io.requestor[0].resp.bits.hx, resp_hx @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 559:34] connect io.requestor[0].resp.bits.pte, r_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 560:35] connect io.requestor[0].resp.bits.level, max_count @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 561:37] node _io_requestor_0_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 562:58] connect io.requestor[0].resp.bits.homogeneous, _io_requestor_0_resp_bits_homogeneous_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 562:43] node _io_requestor_0_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 563:81] connect io.requestor[0].resp.bits.fragmented_superpage, _io_requestor_0_resp_bits_fragmented_superpage_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 563:52] connect io.requestor[0].resp.bits.gpa.valid, r_req.need_gpa @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 564:41] node _io_requestor_0_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 571:17] node _io_requestor_0_resp_bits_gpa_bits_T_1 = eq(aux_count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 571:44] node _io_requestor_0_resp_bits_gpa_bits_T_2 = or(_io_requestor_0_resp_bits_gpa_bits_T, _io_requestor_0_resp_bits_gpa_bits_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 571:31] node _io_requestor_0_resp_bits_gpa_bits_T_3 = shr(aux_pte.ppn, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 343:49] node _io_requestor_0_resp_bits_gpa_bits_T_4 = bits(r_req.addr, 17, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 343:79] node _io_requestor_0_resp_bits_gpa_bits_T_5 = cat(_io_requestor_0_resp_bits_gpa_bits_T_3, _io_requestor_0_resp_bits_gpa_bits_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 343:44] node _io_requestor_0_resp_bits_gpa_bits_T_6 = shr(aux_pte.ppn, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 343:49] node _io_requestor_0_resp_bits_gpa_bits_T_7 = bits(r_req.addr, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 343:79] node _io_requestor_0_resp_bits_gpa_bits_T_8 = cat(_io_requestor_0_resp_bits_gpa_bits_T_6, _io_requestor_0_resp_bits_gpa_bits_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 343:44] node _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:21] node io_requestor_0_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_0_resp_bits_gpa_bits_truncIdx_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:47] node _io_requestor_0_resp_bits_gpa_bits_T_9 = eq(io_requestor_0_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_requestor_0_resp_bits_gpa_bits_T_10 = mux(_io_requestor_0_resp_bits_gpa_bits_T_9, _io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_requestor_0_resp_bits_gpa_bits_T_11 = mux(_io_requestor_0_resp_bits_gpa_bits_T_2, aux_pte.ppn, _io_requestor_0_resp_bits_gpa_bits_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 571:16] node _io_requestor_0_resp_bits_gpa_bits_T_12 = mux(stage2, _io_requestor_0_resp_bits_gpa_bits_T_11, r_pte.ppn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 569:14] node _io_requestor_0_resp_bits_gpa_bits_T_13 = cat(_io_requestor_0_resp_bits_gpa_bits_T_12, gpa_pgoff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 568:12] node _io_requestor_0_resp_bits_gpa_bits_T_14 = mux(r_req.vstage1, _io_requestor_0_resp_bits_gpa_bits_T_13, r_req.addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 566:10] connect io.requestor[0].resp.bits.gpa.bits, _io_requestor_0_resp_bits_gpa_bits_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 565:40] node _io_requestor_0_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 578:45] connect io.requestor[0].resp.bits.gpa_is_pte, _io_requestor_0_resp_bits_gpa_is_pte_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 578:42] connect io.requestor[0].ptbr, io.dpath.ptbr @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 579:26] connect io.requestor[0].hgatp, io.dpath.hgatp @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 580:27] connect io.requestor[0].vsatp, io.dpath.vsatp @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 581:27] connect io.requestor[0].customCSRs, io.dpath.customCSRs @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 582:32] connect io.requestor[0].status, io.dpath.status @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 583:28] connect io.requestor[0].hstatus, io.dpath.hstatus @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 584:29] connect io.requestor[0].gstatus, io.dpath.gstatus @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 585:29] connect io.requestor[0].pmp, io.dpath.pmp @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 586:25] connect io.requestor[1].resp.valid, resp_valid[1] @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 552:32] connect io.requestor[1].resp.bits.ae_ptw, resp_ae_ptw @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 553:38] connect io.requestor[1].resp.bits.ae_final, resp_ae_final @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 554:40] connect io.requestor[1].resp.bits.pf, resp_pf @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 555:34] connect io.requestor[1].resp.bits.gf, resp_gf @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 556:34] connect io.requestor[1].resp.bits.hr, resp_hr @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 557:34] connect io.requestor[1].resp.bits.hw, resp_hw @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 558:34] connect io.requestor[1].resp.bits.hx, resp_hx @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 559:34] connect io.requestor[1].resp.bits.pte, r_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 560:35] connect io.requestor[1].resp.bits.level, max_count @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 561:37] node _io_requestor_1_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 562:58] connect io.requestor[1].resp.bits.homogeneous, _io_requestor_1_resp_bits_homogeneous_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 562:43] node _io_requestor_1_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 563:81] connect io.requestor[1].resp.bits.fragmented_superpage, _io_requestor_1_resp_bits_fragmented_superpage_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 563:52] connect io.requestor[1].resp.bits.gpa.valid, r_req.need_gpa @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 564:41] node _io_requestor_1_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 571:17] node _io_requestor_1_resp_bits_gpa_bits_T_1 = eq(aux_count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 571:44] node _io_requestor_1_resp_bits_gpa_bits_T_2 = or(_io_requestor_1_resp_bits_gpa_bits_T, _io_requestor_1_resp_bits_gpa_bits_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 571:31] node _io_requestor_1_resp_bits_gpa_bits_T_3 = shr(aux_pte.ppn, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 343:49] node _io_requestor_1_resp_bits_gpa_bits_T_4 = bits(r_req.addr, 17, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 343:79] node _io_requestor_1_resp_bits_gpa_bits_T_5 = cat(_io_requestor_1_resp_bits_gpa_bits_T_3, _io_requestor_1_resp_bits_gpa_bits_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 343:44] node _io_requestor_1_resp_bits_gpa_bits_T_6 = shr(aux_pte.ppn, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 343:49] node _io_requestor_1_resp_bits_gpa_bits_T_7 = bits(r_req.addr, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 343:79] node _io_requestor_1_resp_bits_gpa_bits_T_8 = cat(_io_requestor_1_resp_bits_gpa_bits_T_6, _io_requestor_1_resp_bits_gpa_bits_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 343:44] node _io_requestor_1_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:21] node io_requestor_1_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_1_resp_bits_gpa_bits_truncIdx_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:47] node _io_requestor_1_resp_bits_gpa_bits_T_9 = eq(io_requestor_1_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_requestor_1_resp_bits_gpa_bits_T_10 = mux(_io_requestor_1_resp_bits_gpa_bits_T_9, _io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_requestor_1_resp_bits_gpa_bits_T_11 = mux(_io_requestor_1_resp_bits_gpa_bits_T_2, aux_pte.ppn, _io_requestor_1_resp_bits_gpa_bits_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 571:16] node _io_requestor_1_resp_bits_gpa_bits_T_12 = mux(stage2, _io_requestor_1_resp_bits_gpa_bits_T_11, r_pte.ppn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 569:14] node _io_requestor_1_resp_bits_gpa_bits_T_13 = cat(_io_requestor_1_resp_bits_gpa_bits_T_12, gpa_pgoff) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 568:12] node _io_requestor_1_resp_bits_gpa_bits_T_14 = mux(r_req.vstage1, _io_requestor_1_resp_bits_gpa_bits_T_13, r_req.addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 566:10] connect io.requestor[1].resp.bits.gpa.bits, _io_requestor_1_resp_bits_gpa_bits_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 565:40] node _io_requestor_1_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 578:45] connect io.requestor[1].resp.bits.gpa_is_pte, _io_requestor_1_resp_bits_gpa_is_pte_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 578:42] connect io.requestor[1].ptbr, io.dpath.ptbr @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 579:26] connect io.requestor[1].hgatp, io.dpath.hgatp @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 580:27] connect io.requestor[1].vsatp, io.dpath.vsatp @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 581:27] connect io.requestor[1].customCSRs, io.dpath.customCSRs @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 582:32] connect io.requestor[1].status, io.dpath.status @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 583:28] connect io.requestor[1].hstatus, io.dpath.hstatus @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 584:29] connect io.requestor[1].gstatus, io.dpath.gstatus @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 585:29] connect io.requestor[1].pmp, io.dpath.pmp @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 586:25] wire next_state : UInt @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 590:31] connect next_state, state @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 590:31] inst state_barrier of OptimizationBarrier_UInt @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect state_barrier.clock, clock connect state_barrier.reset, reset connect state_barrier.io.x, next_state @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect state, state_barrier.io.y @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 591:9] wire do_switch : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 592:30] connect do_switch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 592:30] node _T_127 = eq(UInt<3>(0h0), state) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 594:18] when _T_127 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 594:18] node _T_128 = and(arb.io.out.ready, arb.io.out.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_128 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 596:30] node _satp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 597:45] node _satp_initial_count_T_1 = tail(_satp_initial_count_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 597:45] node _satp_initial_count_T_2 = sub(_satp_initial_count_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 597:61] node satp_initial_count = tail(_satp_initial_count_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 597:61] node _vsatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 598:46] node _vsatp_initial_count_T_1 = tail(_vsatp_initial_count_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 598:46] node _vsatp_initial_count_T_2 = sub(_vsatp_initial_count_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 598:62] node vsatp_initial_count = tail(_vsatp_initial_count_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 598:62] node _hgatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 599:46] node _hgatp_initial_count_T_1 = tail(_hgatp_initial_count_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 599:46] node _hgatp_initial_count_T_2 = sub(_hgatp_initial_count_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 599:62] node hgatp_initial_count = tail(_hgatp_initial_count_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 599:62] node aux_ppn = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 600:38] connect r_req, arb.io.out.bits.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 602:15] connect r_req_dest, arb.io.chosen @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 603:20] node _next_state_T = mux(arb.io.out.bits.valid, UInt<3>(0h1), UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 604:26] connect next_state, _next_state_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 604:20] connect stage2, arb.io.out.bits.bits.stage2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 605:22] node _stage2_final_T = eq(arb.io.out.bits.bits.vstage1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 606:56] node _stage2_final_T_1 = and(arb.io.out.bits.bits.stage2, _stage2_final_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 606:53] connect stage2_final, _stage2_final_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 606:22] node _count_T_3 = mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 607:27] connect count, _count_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 607:21] node _aux_count_T = mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 608:27] connect aux_count, _aux_count_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 608:21] connect aux_pte.ppn, aux_ppn @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 609:21] connect aux_pte.reserved_for_future, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 610:37] connect resp_ae_ptw, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 611:21] connect resp_ae_final, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 612:23] connect resp_pf, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 613:17] node _resp_gf_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 806:28] node _resp_gf_count_T_1 = tail(_resp_gf_count_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 806:28] node _resp_gf_count_T_2 = sub(_resp_gf_count_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 806:44] node resp_gf_count = tail(_resp_gf_count_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 806:44] node resp_gf_idxs_0 = shr(aux_ppn, 29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 807:58] wire _resp_gf_WIRE : UInt<23>[1] @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 44:40] connect _resp_gf_WIRE[0], resp_gf_idxs_0 @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 44:40] node _resp_gf_T = or(resp_gf_count, UInt<0>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 25:40] node _resp_gf_T_1 = neq(_resp_gf_WIRE[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 808:25] node _resp_gf_T_2 = and(_resp_gf_T_1, arb.io.out.bits.bits.stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 614:71] connect resp_gf, _resp_gf_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 614:17] connect resp_hr, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 615:17] connect resp_hw, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 616:17] connect resp_hx, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 617:17] connect resp_fragmented_superpage, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 618:35] connect r_hgatp, io.dpath.hgatp @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 619:17] node _T_129 = eq(arb.io.out.bits.bits.need_gpa, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 621:16] node _T_130 = or(_T_129, arb.io.out.bits.bits.stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 621:47] node _T_131 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 621:15] node _T_132 = eq(_T_131, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 621:15] when _T_132 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 621:15] node _T_133 = eq(_T_130, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 621:15] when _T_133 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 621:15] printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:621 assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2)\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 621:15] assert(clock, _T_130, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 621:15] else : node _T_134 = eq(UInt<3>(0h1), state) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 594:18] when _T_134 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 594:18] node _T_135 = eq(count, r_hgatp_initial_count) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 625:28] node _T_136 = and(stage2, _T_135) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 625:19] when _T_136 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 625:55] node _gpa_pgoff_T = eq(aux_count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 626:36] node _gpa_pgoff_T_1 = shl(r_req.addr, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 626:67] node _gpa_pgoff_T_2 = mux(_gpa_pgoff_T, _gpa_pgoff_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 626:25] connect gpa_pgoff, _gpa_pgoff_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 626:19] when stage2_pte_cache_hit : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 629:35] node _aux_count_T_1 = add(aux_count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 630:32] node _aux_count_T_2 = tail(_aux_count_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 630:32] connect aux_count, _aux_count_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 630:19] connect aux_pte.ppn, stage2_pte_cache_data @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 631:21] connect aux_pte.reserved_for_future, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 632:37] connect pte_hit, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 633:17] else : when pte_cache_hit : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 634:34] node _count_T_4 = add(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 635:24] node _count_T_5 = tail(_count_T_4, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 635:24] connect count, _count_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 635:15] connect pte_hit, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 636:17] else : node _next_state_T_1 = mux(io.mem.req.ready, UInt<3>(0h2), UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 638:26] connect next_state, _next_state_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 638:20] when resp_gf : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 640:21] connect next_state, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 641:20] node _T_137 = or(r_req_dest, UInt<1>(0h0)) node _T_138 = bits(_T_137, 0, 0) connect resp_valid[_T_138], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 642:32] else : node _T_139 = eq(UInt<3>(0h2), state) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 594:18] when _T_139 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 594:18] node _next_state_T_2 = mux(UInt<1>(0h0), UInt<3>(0h1), UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 647:24] connect next_state, _next_state_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 647:18] else : node _T_140 = eq(UInt<3>(0h4), state) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 594:18] when _T_140 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 594:18] connect next_state, UInt<3>(0h5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 650:18] node _io_dpath_perf_pte_miss_T = lt(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 651:39] connect io.dpath.perf.pte_miss, _io_dpath_perf_pte_miss_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 651:30] when io.mem.s2_xcpt.ae.ld : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 652:35] connect resp_ae_ptw, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 653:21] connect next_state, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 654:20] node _T_141 = or(r_req_dest, UInt<1>(0h0)) node _T_142 = bits(_T_141, 0, 0) connect resp_valid[_T_142], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 655:32] else : node _T_143 = eq(UInt<3>(0h7), state) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 594:18] when _T_143 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 594:18] connect next_state, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 659:18] node _T_144 = or(r_req_dest, UInt<1>(0h0)) node _T_145 = bits(_T_144, 0, 0) connect resp_valid[_T_145], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 660:30] node _T_146 = eq(homogeneous, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 661:13] when _T_146 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 661:27] connect count, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 662:15] connect resp_fragmented_superpage, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 663:35] when do_both_stages : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 665:29] connect resp_fragmented_superpage, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 666:35] node _merged_pte_superpage_mask_T = mux(stage2_final, max_count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 673:45] node _merged_pte_superpage_mask_T_1 = eq(_merged_pte_superpage_mask_T, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _merged_pte_superpage_mask_T_2 = mux(_merged_pte_superpage_mask_T_1, UInt<44>(0hffffffffe00), UInt<44>(0hffffffc0000)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _merged_pte_superpage_mask_T_3 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _merged_pte_superpage_mask_T_4 = mux(_merged_pte_superpage_mask_T_3, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _merged_pte_superpage_mask_T_5 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node merged_pte_superpage_mask = mux(_merged_pte_superpage_mask_T_5, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _merged_pte_stage1_ppns_T = bits(pte.ppn, 43, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 674:64] node _merged_pte_stage1_ppns_T_1 = bits(aux_pte.ppn, 17, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 674:125] node merged_pte_stage1_ppns_0 = cat(_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 674:56] node _merged_pte_stage1_ppns_T_2 = bits(pte.ppn, 43, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 674:64] node _merged_pte_stage1_ppns_T_3 = bits(aux_pte.ppn, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 674:125] node merged_pte_stage1_ppns_1 = cat(_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 674:56] node _merged_pte_stage1_ppn_T = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _merged_pte_stage1_ppn_T_1 = mux(_merged_pte_stage1_ppn_T, merged_pte_stage1_ppns_1, merged_pte_stage1_ppns_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _merged_pte_stage1_ppn_T_2 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _merged_pte_stage1_ppn_T_3 = mux(_merged_pte_stage1_ppn_T_2, pte.ppn, _merged_pte_stage1_ppn_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _merged_pte_stage1_ppn_T_4 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node merged_pte_stage1_ppn = mux(_merged_pte_stage1_ppn_T_4, pte.ppn, _merged_pte_stage1_ppn_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _merged_pte_T = and(merged_pte_stage1_ppn, merged_pte_superpage_mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 676:24] wire merged_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 791:26] connect merged_pte, aux_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 791:26] connect merged_pte.ppn, _merged_pte_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 792:13] node _r_pte_T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 681:19] node _r_pte_T_1 = and(UInt<1>(0h0), _r_pte_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 681:16] node _r_pte_T_2 = eq(resp_gf, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 681:32] node _r_pte_T_3 = and(_r_pte_T_1, _r_pte_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 681:29] node _r_pte_T_4 = eq(state, UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 683:15] node _r_pte_T_5 = and(_r_pte_T_4, stage2_pte_cache_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 683:25] node _r_pte_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 797:28] node _r_pte_count_T_1 = tail(_r_pte_count_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 797:28] node _r_pte_count_T_2 = sub(_r_pte_count_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 797:44] node r_pte_count = tail(_r_pte_count_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 797:44] node r_pte_idxs_0 = shr(stage2_pte_cache_data, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 798:58] wire r_pte_lsbs : UInt<2> @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 799:27] connect r_pte_lsbs, r_pte_idxs_0 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 799:27] wire r_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 800:26] connect r_pte_pte, l2_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 800:26] node _r_pte_pte_ppn_T = shr(r_hgatp.ppn, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 801:30] node _r_pte_pte_ppn_T_1 = cat(_r_pte_pte_ppn_T, r_pte_lsbs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 801:19] connect r_pte_pte.ppn, _r_pte_pte_ppn_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 801:13] node _r_pte_T_6 = eq(state, UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 685:15] node _r_pte_T_7 = and(_r_pte_T_6, pte_cache_hit) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 685:25] wire r_pte_pte_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 791:26] connect r_pte_pte_1, l2_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 791:26] connect r_pte_pte_1.ppn, pte_cache_data @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 792:13] node _r_pte_count_T_3 = sub(UInt<2>(0h3), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 797:28] node _r_pte_count_T_4 = tail(_r_pte_count_T_3, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 797:28] node _r_pte_count_T_5 = sub(_r_pte_count_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 797:44] node r_pte_count_1 = tail(_r_pte_count_T_5, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 797:44] node r_pte_idxs_0_1 = shr(pte.ppn, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 798:58] wire r_pte_lsbs_1 : UInt<2> @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 799:27] connect r_pte_lsbs_1, r_pte_idxs_0_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 799:27] wire r_pte_pte_2 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 800:26] connect r_pte_pte_2, r_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 800:26] node _r_pte_pte_ppn_T_2 = shr(r_hgatp.ppn, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 801:30] node _r_pte_pte_ppn_T_3 = cat(_r_pte_pte_ppn_T_2, r_pte_lsbs_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 801:19] connect r_pte_pte_2.ppn, _r_pte_pte_ppn_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 801:13] node _r_pte_T_8 = eq(traverse, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 689:29] node _r_pte_T_9 = and(_r_pte_T_8, r_req.vstage1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 689:39] node _r_pte_T_10 = and(_r_pte_T_9, stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 689:56] node _r_pte_T_11 = mux(_r_pte_T_10, merged_pte, pte) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 689:28] node _r_pte_T_12 = eq(state, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 691:15] node _r_pte_T_13 = eq(homogeneous, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 691:43] node _r_pte_T_14 = and(_r_pte_T_12, _r_pte_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 691:40] node _r_pte_T_15 = neq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 691:65] node _r_pte_T_16 = and(_r_pte_T_14, _r_pte_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 691:56] node _r_pte_T_17 = shr(r_pte.ppn, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 343:49] node _r_pte_T_18 = bits(r_req.addr, 17, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 343:79] node _r_pte_T_19 = cat(_r_pte_T_17, _r_pte_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 343:44] node _r_pte_T_20 = shr(r_pte.ppn, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 343:49] node _r_pte_T_21 = bits(r_req.addr, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 343:79] node _r_pte_T_22 = cat(_r_pte_T_20, _r_pte_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 343:44] node _r_pte_truncIdx_T = or(count, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:21] node r_pte_truncIdx = bits(_r_pte_truncIdx_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 39:47] node _r_pte_T_23 = eq(r_pte_truncIdx, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _r_pte_T_24 = mux(_r_pte_T_23, _r_pte_T_22, _r_pte_T_19) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] wire r_pte_pte_3 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 791:26] connect r_pte_pte_3, r_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 791:26] connect r_pte_pte_3.ppn, _r_pte_T_24 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 792:13] node _r_pte_T_25 = and(arb.io.out.ready, arb.io.out.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _r_pte_count_T_6 = sub(UInt<2>(0h3), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 797:28] node _r_pte_count_T_7 = tail(_r_pte_count_T_6, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 797:28] node _r_pte_count_T_8 = sub(_r_pte_count_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 797:44] node r_pte_count_2 = tail(_r_pte_count_T_8, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 797:44] node r_pte_idxs_0_2 = shr(io.dpath.vsatp.ppn, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 798:58] wire r_pte_lsbs_2 : UInt<2> @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 799:27] connect r_pte_lsbs_2, r_pte_idxs_0_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 799:27] wire r_pte_pte_4 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 800:26] connect r_pte_pte_4, r_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 800:26] node _r_pte_pte_ppn_T_4 = shr(io.dpath.hgatp.ppn, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 801:30] node _r_pte_pte_ppn_T_5 = cat(_r_pte_pte_ppn_T_4, r_pte_lsbs_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 801:19] connect r_pte_pte_4.ppn, _r_pte_pte_ppn_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 801:13] wire r_pte_pte_5 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 791:26] connect r_pte_pte_5, r_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 791:26] connect r_pte_pte_5.ppn, satp.ppn @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 792:13] node _r_pte_T_26 = mux(arb.io.out.bits.bits.stage2, r_pte_pte_4, r_pte_pte_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 693:29] node _r_pte_T_27 = mux(_r_pte_T_25, _r_pte_T_26, r_pte) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 693:8] node _r_pte_T_28 = mux(_r_pte_T_16, r_pte_pte_3, _r_pte_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 691:8] node _r_pte_T_29 = mux(mem_resp_valid, _r_pte_T_11, _r_pte_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 689:8] node _r_pte_T_30 = mux(do_switch, r_pte_pte_2, _r_pte_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 687:8] node _r_pte_T_31 = mux(_r_pte_T_7, r_pte_pte_1, _r_pte_T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 685:8] node _r_pte_T_32 = mux(_r_pte_T_5, r_pte_pte, _r_pte_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 683:8] node _r_pte_T_33 = mux(_r_pte_T_3, l2_pte, _r_pte_T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 681:8] inst r_pte_barrier of OptimizationBarrier_PTE @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 268:25] connect r_pte_barrier.clock, clock connect r_pte_barrier.reset, reset connect r_pte_barrier.io.x.v, _r_pte_T_33.v @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect r_pte_barrier.io.x.r, _r_pte_T_33.r @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect r_pte_barrier.io.x.w, _r_pte_T_33.w @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect r_pte_barrier.io.x.x, _r_pte_T_33.x @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect r_pte_barrier.io.x.u, _r_pte_T_33.u @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect r_pte_barrier.io.x.g, _r_pte_T_33.g @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect r_pte_barrier.io.x.a, _r_pte_T_33.a @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect r_pte_barrier.io.x.d, _r_pte_T_33.d @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect r_pte_barrier.io.x.reserved_for_software, _r_pte_T_33.reserved_for_software @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect r_pte_barrier.io.x.ppn, _r_pte_T_33.ppn @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect r_pte_barrier.io.x.reserved_for_future, _r_pte_T_33.reserved_for_future @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 276:18] connect r_pte, r_pte_barrier.io.y @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 679:9] node _T_147 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 696:19] node _T_148 = and(UInt<1>(0h0), _T_147) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 696:16] node _T_149 = eq(resp_gf, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 696:32] node _T_150 = and(_T_148, _T_149) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 696:29] when _T_150 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 696:42] node _T_151 = eq(state, UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 697:18] node _T_152 = eq(state, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 697:37] node _T_153 = or(_T_151, _T_152) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 697:28] node _T_154 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 697:11] node _T_155 = eq(_T_154, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 697:11] when _T_155 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 697:11] node _T_156 = eq(_T_153, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 697:11] when _T_156 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 697:11] printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:697 assert(state === s_req || state === s_wait1)\n") : printf_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 697:11] assert(clock, _T_153, UInt<1>(0h1), "") : assert_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 697:11] connect next_state, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 698:16] node _T_157 = or(r_req_dest, UInt<1>(0h0)) node _T_158 = bits(_T_157, 0, 0) connect resp_valid[_T_158], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 699:28] connect count, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 700:11] when mem_resp_valid : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 702:25] node _T_159 = eq(state, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 703:18] node _T_160 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 703:11] node _T_161 = eq(_T_160, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 703:11] when _T_161 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 703:11] node _T_162 = eq(_T_159, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 703:11] when _T_162 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 703:11] printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:703 assert(state === s_wait3)\n") : printf_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 703:11] assert(clock, _T_159, UInt<1>(0h1), "") : assert_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 703:11] connect next_state, UInt<3>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 704:16] node _T_163 = eq(stage2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 705:29] node _T_164 = and(do_both_stages, _T_163) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 705:26] when _T_164 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 705:38] node gpa_pgoff_vpn_idxs_0 = shr(vpn, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 707:56] node gpa_pgoff_vpn_idxs_1 = shr(vpn, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 707:56] node gpa_pgoff_vpn_idxs_2 = shr(vpn, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 707:56] node _gpa_pgoff_vpn_idx_T = add(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 708:39] node _gpa_pgoff_vpn_idx_T_1 = tail(_gpa_pgoff_vpn_idx_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 708:39] node _gpa_pgoff_vpn_idx_T_2 = eq(_gpa_pgoff_vpn_idx_T_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _gpa_pgoff_vpn_idx_T_3 = mux(_gpa_pgoff_vpn_idx_T_2, gpa_pgoff_vpn_idxs_1, gpa_pgoff_vpn_idxs_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _gpa_pgoff_vpn_idx_T_4 = eq(_gpa_pgoff_vpn_idx_T_1, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _gpa_pgoff_vpn_idx_T_5 = mux(_gpa_pgoff_vpn_idx_T_4, gpa_pgoff_vpn_idxs_2, _gpa_pgoff_vpn_idx_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _gpa_pgoff_vpn_idx_T_6 = eq(_gpa_pgoff_vpn_idx_T_1, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node gpa_pgoff_vpn_idx = mux(_gpa_pgoff_vpn_idx_T_6, gpa_pgoff_vpn_idxs_2, _gpa_pgoff_vpn_idx_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _gpa_pgoff_T_3 = shl(gpa_pgoff_vpn_idx, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 709:17] connect gpa_pgoff, _gpa_pgoff_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 706:17] when traverse : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 713:21] node _T_165 = eq(stage2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 714:31] node _T_166 = and(do_both_stages, _T_165) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 714:28] when _T_166 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 714:40] connect do_switch, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 714:52] node _count_T_6 = add(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 715:22] node _count_T_7 = tail(_count_T_6, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 715:22] connect count, _count_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 715:13] else : node _gf_T = eq(stage2_final, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 717:27] node _gf_T_1 = and(stage2, _gf_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 717:24] node _gf_T_2 = eq(pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:47] node _gf_T_3 = and(pte.x, _gf_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:44] node _gf_T_4 = or(pte.r, _gf_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:38] node _gf_T_5 = and(pte.v, _gf_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:32] node _gf_T_6 = and(_gf_T_5, pte.a) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:52] node _gf_T_7 = and(_gf_T_6, pte.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 149:35] node _gf_T_8 = and(_gf_T_7, pte.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 143:33] node _gf_T_9 = eq(_gf_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 717:44] node _gf_T_10 = and(_gf_T_1, _gf_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 717:41] node _gf_T_11 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 718:20] node _gf_T_12 = eq(pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:47] node _gf_T_13 = and(pte.x, _gf_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:44] node _gf_T_14 = or(pte.r, _gf_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:38] node _gf_T_15 = and(pte.v, _gf_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:32] node _gf_T_16 = and(_gf_T_15, pte.a) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:52] node _gf_T_17 = mux(_gf_T_11, _gf_T_16, pte.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 718:13] node _gf_T_18 = eq(pte.reserved_for_future, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 718:88] node _gf_T_19 = and(_gf_T_17, _gf_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 718:61] node _gf_T_20 = and(_gf_T_19, invalid_gpa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 718:96] node gf = or(_gf_T_10, _gf_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 717:55] node _ae_T = and(pte.v, invalid_paddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 719:22] node _ae_T_1 = neq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 719:67] node _ae_T_2 = eq(pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:47] node _ae_T_3 = and(pte.x, _ae_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:44] node _ae_T_4 = or(pte.r, _ae_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:38] node _ae_T_5 = and(pte.v, _ae_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:32] node _ae_T_6 = and(_ae_T_5, pte.a) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:52] node _ae_T_7 = or(_ae_T_1, _ae_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 719:89] node _ae_T_8 = and(invalid_gpa, _ae_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 719:56] node _ae_T_9 = eq(_ae_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 719:42] node ae = and(_ae_T, _ae_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 719:39] node _pf_T = neq(pte.reserved_for_future, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 720:49] node pf = and(pte.v, _pf_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 720:22] node _success_T = eq(ae, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 721:30] node _success_T_1 = and(pte.v, _success_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 721:27] node _success_T_2 = eq(pf, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 721:37] node _success_T_3 = and(_success_T_1, _success_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 721:34] node _success_T_4 = eq(gf, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 721:44] node success = and(_success_T_3, _success_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 721:41] node _T_167 = eq(stage2_final, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 723:31] node _T_168 = and(do_both_stages, _T_167) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 723:28] node _T_169 = and(_T_168, success) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 723:45] when _T_169 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 723:57] when stage2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 724:23] connect stage2, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 725:18] connect count, aux_count @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 726:17] else : connect stage2_final, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 728:24] connect do_switch, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 729:21] else : node _l2_refill_T = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 733:39] node _l2_refill_T_1 = and(success, _l2_refill_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 733:30] node _l2_refill_T_2 = eq(r_req.need_gpa, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 733:61] node _l2_refill_T_3 = and(_l2_refill_T_1, _l2_refill_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 733:58] node _l2_refill_T_4 = eq(r_req.vstage1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 734:12] node _l2_refill_T_5 = eq(r_req.stage2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 734:30] node _l2_refill_T_6 = and(_l2_refill_T_4, _l2_refill_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 734:27] node _l2_refill_T_7 = eq(aux_count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 735:40] node _l2_refill_T_8 = and(do_both_stages, _l2_refill_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 735:27] node _l2_refill_T_9 = eq(pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:47] node _l2_refill_T_10 = and(pte.x, _l2_refill_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:44] node _l2_refill_T_11 = or(pte.r, _l2_refill_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:38] node _l2_refill_T_12 = and(pte.v, _l2_refill_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:32] node _l2_refill_T_13 = and(_l2_refill_T_12, pte.a) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:52] node _l2_refill_T_14 = and(_l2_refill_T_13, pte.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 151:35] node _l2_refill_T_15 = and(_l2_refill_T_14, pte.d) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 151:40] node _l2_refill_T_16 = and(_l2_refill_T_15, pte.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 145:33] node _l2_refill_T_17 = eq(pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:47] node _l2_refill_T_18 = and(pte.x, _l2_refill_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:44] node _l2_refill_T_19 = or(pte.r, _l2_refill_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:38] node _l2_refill_T_20 = and(pte.v, _l2_refill_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:32] node _l2_refill_T_21 = and(_l2_refill_T_20, pte.a) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:52] node _l2_refill_T_22 = and(_l2_refill_T_21, pte.x) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 153:35] node _l2_refill_T_23 = and(_l2_refill_T_22, pte.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 147:33] node _l2_refill_T_24 = and(_l2_refill_T_16, _l2_refill_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 155:41] node _l2_refill_T_25 = and(_l2_refill_T_8, _l2_refill_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 735:59] node _l2_refill_T_26 = or(_l2_refill_T_6, _l2_refill_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 734:44] node _l2_refill_T_27 = and(_l2_refill_T_3, _l2_refill_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 733:77] connect l2_refill, _l2_refill_T_27 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 733:19] connect count, max_count @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 736:15] node _T_170 = and(success, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 738:23] node _T_171 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 738:59] node _T_172 = eq(do_both_stages, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 738:82] node _T_173 = eq(aux_count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 738:111] node _T_174 = or(_T_172, _T_173) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 738:98] node _T_175 = and(_T_171, _T_174) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 738:78] node _T_176 = eq(_T_175, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 738:51] node _T_177 = and(_T_170, _T_176) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 738:48] when _T_177 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 738:133] connect next_state, UInt<3>(0h7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 739:22] else : connect next_state, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 741:22] node _T_178 = or(r_req_dest, UInt<1>(0h0)) node _T_179 = bits(_T_178, 0, 0) connect resp_valid[_T_179], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 742:34] node _resp_ae_ptw_T = lt(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 745:38] node _resp_ae_ptw_T_1 = eq(pte.r, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:36] node _resp_ae_ptw_T_2 = and(pte.v, _resp_ae_ptw_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:33] node _resp_ae_ptw_T_3 = eq(pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:42] node _resp_ae_ptw_T_4 = and(_resp_ae_ptw_T_2, _resp_ae_ptw_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:39] node _resp_ae_ptw_T_5 = eq(pte.x, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:48] node _resp_ae_ptw_T_6 = and(_resp_ae_ptw_T_4, _resp_ae_ptw_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:45] node _resp_ae_ptw_T_7 = eq(pte.d, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:54] node _resp_ae_ptw_T_8 = and(_resp_ae_ptw_T_6, _resp_ae_ptw_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:51] node _resp_ae_ptw_T_9 = eq(pte.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:60] node _resp_ae_ptw_T_10 = and(_resp_ae_ptw_T_8, _resp_ae_ptw_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:57] node _resp_ae_ptw_T_11 = eq(pte.u, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:66] node _resp_ae_ptw_T_12 = and(_resp_ae_ptw_T_10, _resp_ae_ptw_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:63] node _resp_ae_ptw_T_13 = eq(pte.reserved_for_future, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:92] node _resp_ae_ptw_T_14 = and(_resp_ae_ptw_T_12, _resp_ae_ptw_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:69] node _resp_ae_ptw_T_15 = and(_resp_ae_ptw_T, _resp_ae_ptw_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 745:55] node _resp_ae_ptw_T_16 = eq(stage2_final, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 745:93] node _resp_ae_ptw_T_17 = and(do_both_stages, _resp_ae_ptw_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 745:90] node _resp_ae_ptw_T_18 = or(_resp_ae_ptw_T_15, _resp_ae_ptw_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 745:71] node _resp_ae_ptw_T_19 = and(ae, _resp_ae_ptw_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 745:27] connect resp_ae_ptw, _resp_ae_ptw_T_19 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 745:21] node _resp_ae_final_T = eq(pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:47] node _resp_ae_final_T_1 = and(pte.x, _resp_ae_final_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:44] node _resp_ae_final_T_2 = or(pte.r, _resp_ae_final_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:38] node _resp_ae_final_T_3 = and(pte.v, _resp_ae_final_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:32] node _resp_ae_final_T_4 = and(_resp_ae_final_T_3, pte.a) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:52] node _resp_ae_final_T_5 = and(ae, _resp_ae_final_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 746:29] node _resp_ae_final_T_6 = eq(stage2_final, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 746:66] node _resp_ae_final_T_7 = and(do_both_stages, _resp_ae_final_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 746:63] node _resp_ae_final_T_8 = eq(_resp_ae_final_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 746:46] node _resp_ae_final_T_9 = and(_resp_ae_final_T_5, _resp_ae_final_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 746:43] connect resp_ae_final, _resp_ae_final_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 746:23] node _resp_pf_T = eq(stage2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 747:26] node _resp_pf_T_1 = and(pf, _resp_pf_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 747:23] connect resp_pf, _resp_pf_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 747:17] node _resp_gf_T_3 = and(pf, stage2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 748:30] node _resp_gf_T_4 = or(gf, _resp_gf_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 748:23] connect resp_gf, _resp_gf_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 748:17] node _resp_hr_T = eq(stage2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 749:20] node _resp_hr_T_1 = eq(pf, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 749:32] node _resp_hr_T_2 = eq(gf, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 749:39] node _resp_hr_T_3 = and(_resp_hr_T_1, _resp_hr_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 749:36] node _resp_hr_T_4 = eq(pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:47] node _resp_hr_T_5 = and(pte.x, _resp_hr_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:44] node _resp_hr_T_6 = or(pte.r, _resp_hr_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:38] node _resp_hr_T_7 = and(pte.v, _resp_hr_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:32] node _resp_hr_T_8 = and(_resp_hr_T_7, pte.a) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:52] node _resp_hr_T_9 = and(_resp_hr_T_8, pte.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 149:35] node _resp_hr_T_10 = and(_resp_hr_T_9, pte.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 143:33] node _resp_hr_T_11 = and(_resp_hr_T_3, _resp_hr_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 749:43] node _resp_hr_T_12 = or(_resp_hr_T, _resp_hr_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 749:28] connect resp_hr, _resp_hr_T_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 749:17] node _resp_hw_T = eq(stage2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 750:20] node _resp_hw_T_1 = eq(pf, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 750:32] node _resp_hw_T_2 = eq(gf, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 750:39] node _resp_hw_T_3 = and(_resp_hw_T_1, _resp_hw_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 750:36] node _resp_hw_T_4 = eq(pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:47] node _resp_hw_T_5 = and(pte.x, _resp_hw_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:44] node _resp_hw_T_6 = or(pte.r, _resp_hw_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:38] node _resp_hw_T_7 = and(pte.v, _resp_hw_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:32] node _resp_hw_T_8 = and(_resp_hw_T_7, pte.a) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:52] node _resp_hw_T_9 = and(_resp_hw_T_8, pte.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 151:35] node _resp_hw_T_10 = and(_resp_hw_T_9, pte.d) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 151:40] node _resp_hw_T_11 = and(_resp_hw_T_10, pte.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 145:33] node _resp_hw_T_12 = and(_resp_hw_T_3, _resp_hw_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 750:43] node _resp_hw_T_13 = or(_resp_hw_T, _resp_hw_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 750:28] connect resp_hw, _resp_hw_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 750:17] node _resp_hx_T = eq(stage2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 751:20] node _resp_hx_T_1 = eq(pf, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 751:32] node _resp_hx_T_2 = eq(gf, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 751:39] node _resp_hx_T_3 = and(_resp_hx_T_1, _resp_hx_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 751:36] node _resp_hx_T_4 = eq(pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:47] node _resp_hx_T_5 = and(pte.x, _resp_hx_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:44] node _resp_hx_T_6 = or(pte.r, _resp_hx_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:38] node _resp_hx_T_7 = and(pte.v, _resp_hx_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:32] node _resp_hx_T_8 = and(_resp_hx_T_7, pte.a) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 141:52] node _resp_hx_T_9 = and(_resp_hx_T_8, pte.x) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 153:35] node _resp_hx_T_10 = and(_resp_hx_T_9, pte.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 147:33] node _resp_hx_T_11 = and(_resp_hx_T_3, _resp_hx_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 751:43] node _resp_hx_T_12 = or(_resp_hx_T, _resp_hx_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 751:28] connect resp_hx, _resp_hx_T_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 751:17] when io.mem.s2_nack : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 755:25] node _T_180 = eq(state, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 756:18] node _T_181 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 756:11] node _T_182 = eq(_T_181, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 756:11] when _T_182 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 756:11] node _T_183 = eq(_T_180, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 756:11] when _T_183 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 756:11] printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:756 assert(state === s_wait2)\n") : printf_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 756:11] assert(clock, _T_180, UInt<1>(0h1), "") : assert_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 756:11] connect next_state, UInt<3>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 757:16] when do_switch : @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 760:20] node _aux_count_T_3 = add(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 761:38] node _aux_count_T_4 = tail(_aux_count_T_3, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 761:38] node _aux_count_T_5 = mux(traverse, _aux_count_T_4, count) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 761:21] connect aux_count, _aux_count_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 761:15] connect count, r_hgatp_initial_count @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 762:11] node _aux_pte_s1_ppns_T = bits(pte.ppn, 43, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 764:62] node _aux_pte_s1_ppns_T_1 = bits(r_req.addr, 17, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 764:122] node aux_pte_s1_ppns_0 = cat(_aux_pte_s1_ppns_T, _aux_pte_s1_ppns_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 764:54] node _aux_pte_s1_ppns_T_2 = bits(pte.ppn, 43, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 764:62] node _aux_pte_s1_ppns_T_3 = bits(r_req.addr, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 764:122] node aux_pte_s1_ppns_1 = cat(_aux_pte_s1_ppns_T_2, _aux_pte_s1_ppns_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 764:54] node _aux_pte_T = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _aux_pte_T_1 = mux(_aux_pte_T, aux_pte_s1_ppns_1, aux_pte_s1_ppns_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _aux_pte_T_2 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _aux_pte_T_3 = mux(_aux_pte_T_2, pte.ppn, _aux_pte_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _aux_pte_T_4 = eq(count, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _aux_pte_T_5 = mux(_aux_pte_T_4, pte.ppn, _aux_pte_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] wire aux_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 791:26] connect aux_pte_pte, pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 791:26] connect aux_pte_pte.ppn, _aux_pte_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 792:13] node _aux_pte_T_6 = mux(traverse, pte, aux_pte_pte) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 763:19] connect aux_pte, _aux_pte_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 763:13] connect stage2, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 767:12] node _leaf_T = eq(traverse, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 771:34] node _leaf_T_1 = and(mem_resp_valid, _leaf_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 771:31] node _leaf_T_2 = eq(count, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 771:53] node leaf = and(_leaf_T_1, _leaf_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 771:44] node _T_184 = and(leaf, pte.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:17] node _T_185 = eq(invalid_paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:29] node _T_186 = and(_T_184, _T_185) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:26] node _T_187 = eq(invalid_gpa, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:47] node _T_188 = and(_T_186, _T_187) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:44] node _T_189 = eq(pte.reserved_for_future, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:87] node _T_190 = and(_T_188, _T_189) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:60] node _T_191 = and(leaf, pte.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 773:17] node _T_192 = and(_T_191, invalid_paddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 773:26] node _T_193 = and(leaf, pte.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 774:17] node _T_194 = and(_T_193, invalid_gpa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 774:26] node _T_195 = and(leaf, pte.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 775:17] node _T_196 = neq(pte.reserved_for_future, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 775:53] node _T_197 = and(_T_195, _T_196) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 775:26] node _T_198 = bits(mem_resp_data, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 776:34] node _T_199 = eq(_T_198, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 776:20] node _T_200 = and(leaf, _T_199) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 776:17] node _T_201 = eq(pte.v, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 778:22] node _T_202 = and(leaf, _T_201) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 778:19] node _T_203 = bits(mem_resp_data, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 778:45] node _T_204 = and(_T_202, _T_203) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 778:29] node _leaf_T_3 = eq(traverse, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 771:34] node _leaf_T_4 = and(mem_resp_valid, _leaf_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 771:31] node _leaf_T_5 = eq(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 771:53] node leaf_1 = and(_leaf_T_4, _leaf_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 771:44] node _T_205 = and(leaf_1, pte.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:17] node _T_206 = eq(invalid_paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:29] node _T_207 = and(_T_205, _T_206) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:26] node _T_208 = eq(invalid_gpa, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:47] node _T_209 = and(_T_207, _T_208) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:44] node _T_210 = eq(pte.reserved_for_future, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:87] node _T_211 = and(_T_209, _T_210) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:60] node _T_212 = and(leaf_1, pte.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 773:17] node _T_213 = and(_T_212, invalid_paddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 773:26] node _T_214 = and(leaf_1, pte.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 774:17] node _T_215 = and(_T_214, invalid_gpa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 774:26] node _T_216 = and(leaf_1, pte.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 775:17] node _T_217 = neq(pte.reserved_for_future, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 775:53] node _T_218 = and(_T_216, _T_217) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 775:26] node _T_219 = bits(mem_resp_data, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 776:34] node _T_220 = eq(_T_219, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 776:20] node _T_221 = and(leaf_1, _T_220) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 776:17] node _T_222 = eq(pte.v, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 778:22] node _T_223 = and(leaf_1, _T_222) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 778:19] node _T_224 = bits(mem_resp_data, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 778:45] node _T_225 = and(_T_223, _T_224) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 778:29] node _leaf_T_6 = eq(traverse, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 771:34] node _leaf_T_7 = and(mem_resp_valid, _leaf_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 771:31] node _leaf_T_8 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 771:53] node leaf_2 = and(_leaf_T_7, _leaf_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 771:44] node _T_226 = and(leaf_2, pte.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:17] node _T_227 = eq(invalid_paddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:29] node _T_228 = and(_T_226, _T_227) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:26] node _T_229 = eq(invalid_gpa, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:47] node _T_230 = and(_T_228, _T_229) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:44] node _T_231 = eq(pte.reserved_for_future, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:87] node _T_232 = and(_T_230, _T_231) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 772:60] node _T_233 = and(leaf_2, pte.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 773:17] node _T_234 = and(_T_233, invalid_paddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 773:26] node _T_235 = and(leaf_2, pte.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 774:17] node _T_236 = and(_T_235, invalid_gpa) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 774:26] node _T_237 = and(leaf_2, pte.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 775:17] node _T_238 = neq(pte.reserved_for_future, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 775:53] node _T_239 = and(_T_237, _T_238) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 775:26] node _T_240 = bits(mem_resp_data, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 776:34] node _T_241 = eq(_T_240, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 776:20] node _T_242 = and(leaf_2, _T_241) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 776:17] node _T_243 = eq(count, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 780:34] node _T_244 = and(mem_resp_valid, _T_243) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 780:25] node _T_245 = eq(pte.r, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:36] node _T_246 = and(pte.v, _T_245) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:33] node _T_247 = eq(pte.w, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:42] node _T_248 = and(_T_246, _T_247) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:39] node _T_249 = eq(pte.x, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:48] node _T_250 = and(_T_248, _T_249) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:45] node _T_251 = eq(pte.d, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:54] node _T_252 = and(_T_250, _T_251) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:51] node _T_253 = eq(pte.a, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:60] node _T_254 = and(_T_252, _T_253) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:57] node _T_255 = eq(pte.u, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:66] node _T_256 = and(_T_254, _T_255) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:63] node _T_257 = eq(pte.reserved_for_future, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:92] node _T_258 = and(_T_256, _T_257) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 139:69] node _T_259 = and(_T_244, _T_258) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 780:53] node _T_260 = eq(state, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 782:16] node _T_261 = and(_T_260, io.mem.s2_xcpt.ae.ld) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 782:28] module RVCExpander : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 190:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 190:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 190:7] output io : { flip in : UInt<32>, out : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, rvc : UInt<1>, ill : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 191:14] node _io_rvc_T = bits(io.in, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 199:20] node _io_rvc_T_1 = neq(_io_rvc_T, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 199:26] connect io.rvc, _io_rvc_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 199:12] node _io_out_s_opc_T = bits(io.in, 12, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 53:22] node _io_out_s_opc_T_1 = orr(_io_out_s_opc_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 53:29] node io_out_s_opc = mux(_io_out_s_opc_T_1, UInt<7>(0h13), UInt<7>(0h1f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 53:20] node _io_out_s_T = bits(io.in, 10, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 34:26] node _io_out_s_T_1 = bits(io.in, 12, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 34:35] node _io_out_s_T_2 = bits(io.in, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 34:45] node _io_out_s_T_3 = bits(io.in, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 34:51] node io_out_s_lo = cat(_io_out_s_T_3, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 34:24] node io_out_s_hi_hi = cat(_io_out_s_T, _io_out_s_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 34:24] node io_out_s_hi = cat(io_out_s_hi_hi, _io_out_s_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 34:24] node _io_out_s_T_4 = cat(io_out_s_hi, io_out_s_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 34:24] node _io_out_s_T_5 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_6 = cat(UInt<2>(0h1), _io_out_s_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node io_out_s_lo_1 = cat(_io_out_s_T_6, io_out_s_opc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 54:15] node io_out_s_hi_hi_1 = cat(_io_out_s_T_4, UInt<5>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 54:15] node io_out_s_hi_1 = cat(io_out_s_hi_hi_1, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 54:15] node _io_out_s_T_7 = cat(io_out_s_hi_1, io_out_s_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 54:15] node _io_out_s_T_8 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_9 = cat(UInt<2>(0h1), _io_out_s_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_10 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_11 = cat(UInt<2>(0h1), _io_out_s_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_12 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_0 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_0.bits, _io_out_s_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_0.rd, _io_out_s_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_0.rs1, UInt<5>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_0.rs2, _io_out_s_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_0.rs3, _io_out_s_T_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_13 = bits(io.in, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:20] node _io_out_s_T_14 = bits(io.in, 12, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:28] node io_out_s_hi_2 = cat(_io_out_s_T_13, _io_out_s_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:18] node _io_out_s_T_15 = cat(io_out_s_hi_2, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:18] node _io_out_s_T_16 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_17 = cat(UInt<2>(0h1), _io_out_s_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_18 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_19 = cat(UInt<2>(0h1), _io_out_s_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node io_out_s_lo_2 = cat(_io_out_s_T_19, UInt<7>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 58:23] node io_out_s_hi_hi_2 = cat(_io_out_s_T_15, _io_out_s_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 58:23] node io_out_s_hi_3 = cat(io_out_s_hi_hi_2, UInt<3>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 58:23] node _io_out_s_T_20 = cat(io_out_s_hi_3, io_out_s_lo_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 58:23] node _io_out_s_T_21 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_22 = cat(UInt<2>(0h1), _io_out_s_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_23 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_24 = cat(UInt<2>(0h1), _io_out_s_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_25 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_26 = cat(UInt<2>(0h1), _io_out_s_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_27 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_1 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_1.bits, _io_out_s_T_20 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_1.rd, _io_out_s_T_22 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_1.rs1, _io_out_s_T_24 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_1.rs2, _io_out_s_T_26 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_1.rs3, _io_out_s_T_27 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_28 = bits(io.in, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:20] node _io_out_s_T_29 = bits(io.in, 12, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:26] node _io_out_s_T_30 = bits(io.in, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:36] node io_out_s_lo_3 = cat(_io_out_s_T_30, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:18] node io_out_s_hi_4 = cat(_io_out_s_T_28, _io_out_s_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:18] node _io_out_s_T_31 = cat(io_out_s_hi_4, io_out_s_lo_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:18] node _io_out_s_T_32 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_33 = cat(UInt<2>(0h1), _io_out_s_T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_34 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_35 = cat(UInt<2>(0h1), _io_out_s_T_34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node io_out_s_lo_4 = cat(_io_out_s_T_35, UInt<7>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 57:22] node io_out_s_hi_hi_3 = cat(_io_out_s_T_31, _io_out_s_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 57:22] node io_out_s_hi_5 = cat(io_out_s_hi_hi_3, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 57:22] node _io_out_s_T_36 = cat(io_out_s_hi_5, io_out_s_lo_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 57:22] node _io_out_s_T_37 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_38 = cat(UInt<2>(0h1), _io_out_s_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_39 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_40 = cat(UInt<2>(0h1), _io_out_s_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_41 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_42 = cat(UInt<2>(0h1), _io_out_s_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_43 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_2 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_2.bits, _io_out_s_T_36 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_2.rd, _io_out_s_T_38 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_2.rs1, _io_out_s_T_40 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_2.rs2, _io_out_s_T_42 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_2.rs3, _io_out_s_T_43 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_44 = bits(io.in, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:20] node _io_out_s_T_45 = bits(io.in, 12, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:28] node io_out_s_hi_6 = cat(_io_out_s_T_44, _io_out_s_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:18] node _io_out_s_T_46 = cat(io_out_s_hi_6, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:18] node _io_out_s_T_47 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_48 = cat(UInt<2>(0h1), _io_out_s_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_49 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_50 = cat(UInt<2>(0h1), _io_out_s_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node io_out_s_lo_5 = cat(_io_out_s_T_50, UInt<7>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 56:22] node io_out_s_hi_hi_4 = cat(_io_out_s_T_46, _io_out_s_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 56:22] node io_out_s_hi_7 = cat(io_out_s_hi_hi_4, UInt<3>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 56:22] node _io_out_s_T_51 = cat(io_out_s_hi_7, io_out_s_lo_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 56:22] node _io_out_s_T_52 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_53 = cat(UInt<2>(0h1), _io_out_s_T_52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_54 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_55 = cat(UInt<2>(0h1), _io_out_s_T_54) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_56 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_57 = cat(UInt<2>(0h1), _io_out_s_T_56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_58 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_3 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_3.bits, _io_out_s_T_51 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_3.rd, _io_out_s_T_53 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_3.rs1, _io_out_s_T_55 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_3.rs2, _io_out_s_T_57 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_3.rs3, _io_out_s_T_58 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_59 = bits(io.in, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:20] node _io_out_s_T_60 = bits(io.in, 12, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:26] node _io_out_s_T_61 = bits(io.in, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:36] node io_out_s_lo_6 = cat(_io_out_s_T_61, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:18] node io_out_s_hi_8 = cat(_io_out_s_T_59, _io_out_s_T_60) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:18] node _io_out_s_T_62 = cat(io_out_s_hi_8, io_out_s_lo_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:18] node _io_out_s_T_63 = shr(_io_out_s_T_62, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 63:32] node _io_out_s_T_64 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_65 = cat(UInt<2>(0h1), _io_out_s_T_64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_66 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_67 = cat(UInt<2>(0h1), _io_out_s_T_66) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_68 = bits(io.in, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:20] node _io_out_s_T_69 = bits(io.in, 12, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:26] node _io_out_s_T_70 = bits(io.in, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:36] node io_out_s_lo_7 = cat(_io_out_s_T_70, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:18] node io_out_s_hi_9 = cat(_io_out_s_T_68, _io_out_s_T_69) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:18] node _io_out_s_T_71 = cat(io_out_s_hi_9, io_out_s_lo_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:18] node _io_out_s_T_72 = bits(_io_out_s_T_71, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 63:65] node io_out_s_lo_hi = cat(UInt<3>(0h2), _io_out_s_T_72) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 63:25] node io_out_s_lo_8 = cat(io_out_s_lo_hi, UInt<7>(0h3f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 63:25] node io_out_s_hi_hi_5 = cat(_io_out_s_T_63, _io_out_s_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 63:25] node io_out_s_hi_10 = cat(io_out_s_hi_hi_5, _io_out_s_T_67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 63:25] node _io_out_s_T_73 = cat(io_out_s_hi_10, io_out_s_lo_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 63:25] node _io_out_s_T_74 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_75 = cat(UInt<2>(0h1), _io_out_s_T_74) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_76 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_77 = cat(UInt<2>(0h1), _io_out_s_T_76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_78 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_79 = cat(UInt<2>(0h1), _io_out_s_T_78) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_80 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_4 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_4.bits, _io_out_s_T_73 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_4.rd, _io_out_s_T_75 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_4.rs1, _io_out_s_T_77 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_4.rs2, _io_out_s_T_79 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_4.rs3, _io_out_s_T_80 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_81 = bits(io.in, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:20] node _io_out_s_T_82 = bits(io.in, 12, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:28] node io_out_s_hi_11 = cat(_io_out_s_T_81, _io_out_s_T_82) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:18] node _io_out_s_T_83 = cat(io_out_s_hi_11, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:18] node _io_out_s_T_84 = shr(_io_out_s_T_83, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 66:30] node _io_out_s_T_85 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_86 = cat(UInt<2>(0h1), _io_out_s_T_85) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_87 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_88 = cat(UInt<2>(0h1), _io_out_s_T_87) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_89 = bits(io.in, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:20] node _io_out_s_T_90 = bits(io.in, 12, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:28] node io_out_s_hi_12 = cat(_io_out_s_T_89, _io_out_s_T_90) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:18] node _io_out_s_T_91 = cat(io_out_s_hi_12, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:18] node _io_out_s_T_92 = bits(_io_out_s_T_91, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 66:63] node io_out_s_lo_hi_1 = cat(UInt<3>(0h3), _io_out_s_T_92) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 66:23] node io_out_s_lo_9 = cat(io_out_s_lo_hi_1, UInt<7>(0h27)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 66:23] node io_out_s_hi_hi_6 = cat(_io_out_s_T_84, _io_out_s_T_86) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 66:23] node io_out_s_hi_13 = cat(io_out_s_hi_hi_6, _io_out_s_T_88) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 66:23] node _io_out_s_T_93 = cat(io_out_s_hi_13, io_out_s_lo_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 66:23] node _io_out_s_T_94 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_95 = cat(UInt<2>(0h1), _io_out_s_T_94) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_96 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_97 = cat(UInt<2>(0h1), _io_out_s_T_96) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_98 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_99 = cat(UInt<2>(0h1), _io_out_s_T_98) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_100 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_5 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_5.bits, _io_out_s_T_93 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_5.rd, _io_out_s_T_95 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_5.rs1, _io_out_s_T_97 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_5.rs2, _io_out_s_T_99 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_5.rs3, _io_out_s_T_100 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_101 = bits(io.in, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:20] node _io_out_s_T_102 = bits(io.in, 12, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:26] node _io_out_s_T_103 = bits(io.in, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:36] node io_out_s_lo_10 = cat(_io_out_s_T_103, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:18] node io_out_s_hi_14 = cat(_io_out_s_T_101, _io_out_s_T_102) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:18] node _io_out_s_T_104 = cat(io_out_s_hi_14, io_out_s_lo_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:18] node _io_out_s_T_105 = shr(_io_out_s_T_104, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 65:29] node _io_out_s_T_106 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_107 = cat(UInt<2>(0h1), _io_out_s_T_106) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_108 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_109 = cat(UInt<2>(0h1), _io_out_s_T_108) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_110 = bits(io.in, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:20] node _io_out_s_T_111 = bits(io.in, 12, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:26] node _io_out_s_T_112 = bits(io.in, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:36] node io_out_s_lo_11 = cat(_io_out_s_T_112, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:18] node io_out_s_hi_15 = cat(_io_out_s_T_110, _io_out_s_T_111) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:18] node _io_out_s_T_113 = cat(io_out_s_hi_15, io_out_s_lo_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 35:18] node _io_out_s_T_114 = bits(_io_out_s_T_113, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 65:62] node io_out_s_lo_hi_2 = cat(UInt<3>(0h2), _io_out_s_T_114) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 65:22] node io_out_s_lo_12 = cat(io_out_s_lo_hi_2, UInt<7>(0h23)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 65:22] node io_out_s_hi_hi_7 = cat(_io_out_s_T_105, _io_out_s_T_107) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 65:22] node io_out_s_hi_16 = cat(io_out_s_hi_hi_7, _io_out_s_T_109) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 65:22] node _io_out_s_T_115 = cat(io_out_s_hi_16, io_out_s_lo_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 65:22] node _io_out_s_T_116 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_117 = cat(UInt<2>(0h1), _io_out_s_T_116) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_118 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_119 = cat(UInt<2>(0h1), _io_out_s_T_118) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_120 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_121 = cat(UInt<2>(0h1), _io_out_s_T_120) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_122 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_6 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_6.bits, _io_out_s_T_115 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_6.rd, _io_out_s_T_117 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_6.rs1, _io_out_s_T_119 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_6.rs2, _io_out_s_T_121 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_6.rs3, _io_out_s_T_122 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_123 = bits(io.in, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:20] node _io_out_s_T_124 = bits(io.in, 12, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:28] node io_out_s_hi_17 = cat(_io_out_s_T_123, _io_out_s_T_124) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:18] node _io_out_s_T_125 = cat(io_out_s_hi_17, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:18] node _io_out_s_T_126 = shr(_io_out_s_T_125, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 64:29] node _io_out_s_T_127 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_128 = cat(UInt<2>(0h1), _io_out_s_T_127) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_129 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_130 = cat(UInt<2>(0h1), _io_out_s_T_129) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_131 = bits(io.in, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:20] node _io_out_s_T_132 = bits(io.in, 12, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:28] node io_out_s_hi_18 = cat(_io_out_s_T_131, _io_out_s_T_132) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:18] node _io_out_s_T_133 = cat(io_out_s_hi_18, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 36:18] node _io_out_s_T_134 = bits(_io_out_s_T_133, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 64:62] node io_out_s_lo_hi_3 = cat(UInt<3>(0h3), _io_out_s_T_134) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 64:22] node io_out_s_lo_13 = cat(io_out_s_lo_hi_3, UInt<7>(0h23)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 64:22] node io_out_s_hi_hi_8 = cat(_io_out_s_T_126, _io_out_s_T_128) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 64:22] node io_out_s_hi_19 = cat(io_out_s_hi_hi_8, _io_out_s_T_130) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 64:22] node _io_out_s_T_135 = cat(io_out_s_hi_19, io_out_s_lo_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 64:22] node _io_out_s_T_136 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_137 = cat(UInt<2>(0h1), _io_out_s_T_136) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_138 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_139 = cat(UInt<2>(0h1), _io_out_s_T_138) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_140 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_141 = cat(UInt<2>(0h1), _io_out_s_T_140) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_142 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_7 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_7.bits, _io_out_s_T_135 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_7.rd, _io_out_s_T_137 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_7.rs1, _io_out_s_T_139 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_7.rs2, _io_out_s_T_141 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_7.rs3, _io_out_s_T_142 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_143 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:30] node _io_out_s_T_144 = mux(_io_out_s_T_143, UInt<7>(0h7f), UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:25] node _io_out_s_T_145 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:38] node _io_out_s_T_146 = cat(_io_out_s_T_144, _io_out_s_T_145) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:20] node _io_out_s_T_147 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_148 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node io_out_s_lo_14 = cat(_io_out_s_T_148, UInt<7>(0h13)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 75:24] node io_out_s_hi_hi_9 = cat(_io_out_s_T_146, _io_out_s_T_147) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 75:24] node io_out_s_hi_20 = cat(io_out_s_hi_hi_9, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 75:24] node _io_out_s_T_149 = cat(io_out_s_hi_20, io_out_s_lo_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 75:24] node _io_out_s_T_150 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_151 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_152 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_153 = cat(UInt<2>(0h1), _io_out_s_T_152) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_154 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_8 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_8.bits, _io_out_s_T_149 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_8.rd, _io_out_s_T_150 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_8.rs1, _io_out_s_T_151 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_8.rs2, _io_out_s_T_153 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_8.rs3, _io_out_s_T_154 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_opc_T_2 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_opc_T_3 = orr(_io_out_s_opc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 77:24] node io_out_s_opc_1 = mux(_io_out_s_opc_T_3, UInt<7>(0h1b), UInt<7>(0h1f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 77:20] node _io_out_s_T_155 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:30] node _io_out_s_T_156 = mux(_io_out_s_T_155, UInt<7>(0h7f), UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:25] node _io_out_s_T_157 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:38] node _io_out_s_T_158 = cat(_io_out_s_T_156, _io_out_s_T_157) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:20] node _io_out_s_T_159 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_160 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node io_out_s_lo_15 = cat(_io_out_s_T_160, io_out_s_opc_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 78:15] node io_out_s_hi_hi_10 = cat(_io_out_s_T_158, _io_out_s_T_159) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 78:15] node io_out_s_hi_21 = cat(io_out_s_hi_hi_10, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 78:15] node _io_out_s_T_161 = cat(io_out_s_hi_21, io_out_s_lo_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 78:15] node _io_out_s_T_162 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_163 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_164 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_165 = cat(UInt<2>(0h1), _io_out_s_T_164) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_166 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_9 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_9.bits, _io_out_s_T_161 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_9.rd, _io_out_s_T_162 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_9.rs1, _io_out_s_T_163 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_9.rs2, _io_out_s_T_165 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_9.rs3, _io_out_s_T_166 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_167 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:30] node _io_out_s_T_168 = mux(_io_out_s_T_167, UInt<7>(0h7f), UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:25] node _io_out_s_T_169 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:38] node _io_out_s_T_170 = cat(_io_out_s_T_168, _io_out_s_T_169) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:20] node _io_out_s_T_171 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node io_out_s_lo_16 = cat(_io_out_s_T_171, UInt<7>(0h13)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 84:22] node io_out_s_hi_hi_11 = cat(_io_out_s_T_170, UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 84:22] node io_out_s_hi_22 = cat(io_out_s_hi_hi_11, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 84:22] node _io_out_s_T_172 = cat(io_out_s_hi_22, io_out_s_lo_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 84:22] node _io_out_s_T_173 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_174 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_175 = cat(UInt<2>(0h1), _io_out_s_T_174) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_176 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_10 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_10.bits, _io_out_s_T_172 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_10.rd, _io_out_s_T_173 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_10.rs1, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_10.rs2, _io_out_s_T_175 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_10.rs3, _io_out_s_T_176 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_opc_T_4 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:30] node _io_out_s_opc_T_5 = mux(_io_out_s_opc_T_4, UInt<7>(0h7f), UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:25] node _io_out_s_opc_T_6 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:38] node _io_out_s_opc_T_7 = cat(_io_out_s_opc_T_5, _io_out_s_opc_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:20] node _io_out_s_opc_T_8 = orr(_io_out_s_opc_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 90:29] node io_out_s_opc_2 = mux(_io_out_s_opc_T_8, UInt<7>(0h37), UInt<7>(0h3f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 90:20] node _io_out_s_me_T = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 41:30] node _io_out_s_me_T_1 = mux(_io_out_s_me_T, UInt<15>(0h7fff), UInt<15>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 41:24] node _io_out_s_me_T_2 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 41:38] node io_out_s_me_hi = cat(_io_out_s_me_T_1, _io_out_s_me_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 41:19] node _io_out_s_me_T_3 = cat(io_out_s_me_hi, UInt<12>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 41:19] node _io_out_s_me_T_4 = bits(_io_out_s_me_T_3, 31, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 91:31] node _io_out_s_me_T_5 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node io_out_s_me_hi_1 = cat(_io_out_s_me_T_4, _io_out_s_me_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 91:24] node _io_out_s_me_T_6 = cat(io_out_s_me_hi_1, io_out_s_opc_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 91:24] node _io_out_s_me_T_7 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_me_T_8 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_me_T_9 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_me_T_10 = cat(UInt<2>(0h1), _io_out_s_me_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_me_T_11 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_me : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_me.bits, _io_out_s_me_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_me.rd, _io_out_s_me_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_me.rs1, _io_out_s_me_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_me.rs2, _io_out_s_me_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_me.rs3, _io_out_s_me_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_177 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_178 = eq(_io_out_s_T_177, UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 92:14] node _io_out_s_T_179 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_180 = eq(_io_out_s_T_179, UInt<5>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 92:27] node _io_out_s_T_181 = or(_io_out_s_T_178, _io_out_s_T_180) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 92:21] node _io_out_s_opc_T_9 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:30] node _io_out_s_opc_T_10 = mux(_io_out_s_opc_T_9, UInt<7>(0h7f), UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:25] node _io_out_s_opc_T_11 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:38] node _io_out_s_opc_T_12 = cat(_io_out_s_opc_T_10, _io_out_s_opc_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:20] node _io_out_s_opc_T_13 = orr(_io_out_s_opc_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 86:29] node io_out_s_opc_3 = mux(_io_out_s_opc_T_13, UInt<7>(0h13), UInt<7>(0h1f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 86:20] node _io_out_s_T_182 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 42:34] node _io_out_s_T_183 = mux(_io_out_s_T_182, UInt<3>(0h7), UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 42:29] node _io_out_s_T_184 = bits(io.in, 4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 42:42] node _io_out_s_T_185 = bits(io.in, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 42:50] node _io_out_s_T_186 = bits(io.in, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 42:56] node _io_out_s_T_187 = bits(io.in, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 42:62] node io_out_s_lo_hi_4 = cat(_io_out_s_T_186, _io_out_s_T_187) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 42:24] node io_out_s_lo_17 = cat(io_out_s_lo_hi_4, UInt<4>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 42:24] node io_out_s_hi_hi_12 = cat(_io_out_s_T_183, _io_out_s_T_184) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 42:24] node io_out_s_hi_23 = cat(io_out_s_hi_hi_12, _io_out_s_T_185) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 42:24] node _io_out_s_T_188 = cat(io_out_s_hi_23, io_out_s_lo_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 42:24] node _io_out_s_T_189 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_190 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node io_out_s_lo_18 = cat(_io_out_s_T_190, io_out_s_opc_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 87:15] node io_out_s_hi_hi_13 = cat(_io_out_s_T_188, _io_out_s_T_189) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 87:15] node io_out_s_hi_24 = cat(io_out_s_hi_hi_13, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 87:15] node _io_out_s_T_191 = cat(io_out_s_hi_24, io_out_s_lo_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 87:15] node _io_out_s_T_192 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_193 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_194 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_195 = cat(UInt<2>(0h1), _io_out_s_T_194) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_196 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_res : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_res.bits, _io_out_s_T_191 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_res.rd, _io_out_s_T_192 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_res.rs1, _io_out_s_T_193 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_res.rs2, _io_out_s_T_195 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_res.rs3, _io_out_s_T_196 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node io_out_s_11 = mux(_io_out_s_T_181, io_out_s_res, io_out_s_me) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 92:10] node _io_out_s_T_197 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 46:20] node _io_out_s_T_198 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 46:27] node _io_out_s_T_199 = cat(_io_out_s_T_197, _io_out_s_T_198) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 46:18] node _io_out_s_T_200 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_201 = cat(UInt<2>(0h1), _io_out_s_T_200) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_202 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_203 = cat(UInt<2>(0h1), _io_out_s_T_202) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node io_out_s_lo_19 = cat(_io_out_s_T_203, UInt<7>(0h13)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 98:21] node io_out_s_hi_hi_14 = cat(_io_out_s_T_199, _io_out_s_T_201) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 98:21] node io_out_s_hi_25 = cat(io_out_s_hi_hi_14, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 98:21] node _io_out_s_T_204 = cat(io_out_s_hi_25, io_out_s_lo_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 98:21] node _io_out_s_T_205 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 46:20] node _io_out_s_T_206 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 46:27] node _io_out_s_T_207 = cat(_io_out_s_T_205, _io_out_s_T_206) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 46:18] node _io_out_s_T_208 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_209 = cat(UInt<2>(0h1), _io_out_s_T_208) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_210 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_211 = cat(UInt<2>(0h1), _io_out_s_T_210) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node io_out_s_lo_20 = cat(_io_out_s_T_211, UInt<7>(0h13)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 98:21] node io_out_s_hi_hi_15 = cat(_io_out_s_T_207, _io_out_s_T_209) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 98:21] node io_out_s_hi_26 = cat(io_out_s_hi_hi_15, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 98:21] node _io_out_s_T_212 = cat(io_out_s_hi_26, io_out_s_lo_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 98:21] node _io_out_s_T_213 = or(_io_out_s_T_212, UInt<31>(0h40000000)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 99:23] node _io_out_s_T_214 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:30] node _io_out_s_T_215 = mux(_io_out_s_T_214, UInt<7>(0h7f), UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:25] node _io_out_s_T_216 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:38] node _io_out_s_T_217 = cat(_io_out_s_T_215, _io_out_s_T_216) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 43:20] node _io_out_s_T_218 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_219 = cat(UInt<2>(0h1), _io_out_s_T_218) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_220 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_221 = cat(UInt<2>(0h1), _io_out_s_T_220) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node io_out_s_lo_21 = cat(_io_out_s_T_221, UInt<7>(0h13)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 100:21] node io_out_s_hi_hi_16 = cat(_io_out_s_T_217, _io_out_s_T_219) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 100:21] node io_out_s_hi_27 = cat(io_out_s_hi_hi_16, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 100:21] node _io_out_s_T_222 = cat(io_out_s_hi_27, io_out_s_lo_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 100:21] node _io_out_s_funct_T = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 102:70] node _io_out_s_funct_T_1 = bits(io.in, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 102:77] node _io_out_s_funct_T_2 = cat(_io_out_s_funct_T, _io_out_s_funct_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 102:68] node _io_out_s_funct_T_3 = eq(_io_out_s_funct_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_s_funct_T_4 = mux(_io_out_s_funct_T_3, UInt<3>(0h4), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_s_funct_T_5 = eq(_io_out_s_funct_T_2, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_s_funct_T_6 = mux(_io_out_s_funct_T_5, UInt<3>(0h6), _io_out_s_funct_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_s_funct_T_7 = eq(_io_out_s_funct_T_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_s_funct_T_8 = mux(_io_out_s_funct_T_7, UInt<3>(0h7), _io_out_s_funct_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_s_funct_T_9 = eq(_io_out_s_funct_T_2, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_s_funct_T_10 = mux(_io_out_s_funct_T_9, UInt<1>(0h0), _io_out_s_funct_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_s_funct_T_11 = eq(_io_out_s_funct_T_2, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_s_funct_T_12 = mux(_io_out_s_funct_T_11, UInt<1>(0h0), _io_out_s_funct_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_s_funct_T_13 = eq(_io_out_s_funct_T_2, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_s_funct_T_14 = mux(_io_out_s_funct_T_13, UInt<2>(0h2), _io_out_s_funct_T_12) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_s_funct_T_15 = eq(_io_out_s_funct_T_2, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node io_out_s_funct = mux(_io_out_s_funct_T_15, UInt<2>(0h3), _io_out_s_funct_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_s_sub_T = bits(io.in, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 103:24] node _io_out_s_sub_T_1 = eq(_io_out_s_sub_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 103:30] node io_out_s_sub = mux(_io_out_s_sub_T_1, UInt<31>(0h40000000), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 103:22] node _io_out_s_opc_T_14 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 104:24] node io_out_s_opc_4 = mux(_io_out_s_opc_T_14, UInt<7>(0h3b), UInt<7>(0h33)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 104:22] node _io_out_s_T_223 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_224 = cat(UInt<2>(0h1), _io_out_s_T_223) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_225 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_226 = cat(UInt<2>(0h1), _io_out_s_T_225) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_227 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_228 = cat(UInt<2>(0h1), _io_out_s_T_227) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node io_out_s_lo_22 = cat(_io_out_s_T_228, io_out_s_opc_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 105:12] node io_out_s_hi_hi_17 = cat(_io_out_s_T_224, _io_out_s_T_226) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 105:12] node io_out_s_hi_28 = cat(io_out_s_hi_hi_17, io_out_s_funct) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 105:12] node _io_out_s_T_229 = cat(io_out_s_hi_28, io_out_s_lo_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 105:12] node _io_out_s_T_230 = or(_io_out_s_T_229, io_out_s_sub) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 105:43] node _io_out_s_T_231 = bits(io.in, 11, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 107:42] node _io_out_s_T_232 = eq(_io_out_s_T_231, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_s_T_233 = mux(_io_out_s_T_232, _io_out_s_T_213, _io_out_s_T_204) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_s_T_234 = eq(_io_out_s_T_231, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_s_T_235 = mux(_io_out_s_T_234, _io_out_s_T_222, _io_out_s_T_233) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_s_T_236 = eq(_io_out_s_T_231, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_s_T_237 = mux(_io_out_s_T_236, _io_out_s_T_230, _io_out_s_T_235) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_s_T_238 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_239 = cat(UInt<2>(0h1), _io_out_s_T_238) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_240 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_241 = cat(UInt<2>(0h1), _io_out_s_T_240) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_242 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_243 = cat(UInt<2>(0h1), _io_out_s_T_242) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_244 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_12 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_12.bits, _io_out_s_T_237 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_12.rd, _io_out_s_T_239 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_12.rs1, _io_out_s_T_241 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_12.rs2, _io_out_s_T_243 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_12.rs3, _io_out_s_T_244 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_245 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:28] node _io_out_s_T_246 = mux(_io_out_s_T_245, UInt<10>(0h3ff), UInt<10>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:22] node _io_out_s_T_247 = bits(io.in, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:36] node _io_out_s_T_248 = bits(io.in, 10, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:42] node _io_out_s_T_249 = bits(io.in, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:51] node _io_out_s_T_250 = bits(io.in, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:57] node _io_out_s_T_251 = bits(io.in, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:63] node _io_out_s_T_252 = bits(io.in, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:69] node _io_out_s_T_253 = bits(io.in, 5, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:76] node io_out_s_lo_lo = cat(_io_out_s_T_253, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_lo_hi_5 = cat(_io_out_s_T_251, _io_out_s_T_252) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_lo_23 = cat(io_out_s_lo_hi_5, io_out_s_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_hi_lo = cat(_io_out_s_T_249, _io_out_s_T_250) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_hi_hi_hi = cat(_io_out_s_T_246, _io_out_s_T_247) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_hi_hi_18 = cat(io_out_s_hi_hi_hi, _io_out_s_T_248) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_hi_29 = cat(io_out_s_hi_hi_18, io_out_s_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node _io_out_s_T_254 = cat(io_out_s_hi_29, io_out_s_lo_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node _io_out_s_T_255 = bits(_io_out_s_T_254, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 94:26] node _io_out_s_T_256 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:28] node _io_out_s_T_257 = mux(_io_out_s_T_256, UInt<10>(0h3ff), UInt<10>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:22] node _io_out_s_T_258 = bits(io.in, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:36] node _io_out_s_T_259 = bits(io.in, 10, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:42] node _io_out_s_T_260 = bits(io.in, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:51] node _io_out_s_T_261 = bits(io.in, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:57] node _io_out_s_T_262 = bits(io.in, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:63] node _io_out_s_T_263 = bits(io.in, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:69] node _io_out_s_T_264 = bits(io.in, 5, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:76] node io_out_s_lo_lo_1 = cat(_io_out_s_T_264, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_lo_hi_6 = cat(_io_out_s_T_262, _io_out_s_T_263) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_lo_24 = cat(io_out_s_lo_hi_6, io_out_s_lo_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_hi_lo_1 = cat(_io_out_s_T_260, _io_out_s_T_261) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_hi_hi_hi_1 = cat(_io_out_s_T_257, _io_out_s_T_258) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_hi_hi_19 = cat(io_out_s_hi_hi_hi_1, _io_out_s_T_259) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_hi_30 = cat(io_out_s_hi_hi_19, io_out_s_hi_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node _io_out_s_T_265 = cat(io_out_s_hi_30, io_out_s_lo_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node _io_out_s_T_266 = bits(_io_out_s_T_265, 10, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 94:36] node _io_out_s_T_267 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:28] node _io_out_s_T_268 = mux(_io_out_s_T_267, UInt<10>(0h3ff), UInt<10>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:22] node _io_out_s_T_269 = bits(io.in, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:36] node _io_out_s_T_270 = bits(io.in, 10, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:42] node _io_out_s_T_271 = bits(io.in, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:51] node _io_out_s_T_272 = bits(io.in, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:57] node _io_out_s_T_273 = bits(io.in, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:63] node _io_out_s_T_274 = bits(io.in, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:69] node _io_out_s_T_275 = bits(io.in, 5, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:76] node io_out_s_lo_lo_2 = cat(_io_out_s_T_275, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_lo_hi_7 = cat(_io_out_s_T_273, _io_out_s_T_274) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_lo_25 = cat(io_out_s_lo_hi_7, io_out_s_lo_lo_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_hi_lo_2 = cat(_io_out_s_T_271, _io_out_s_T_272) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_hi_hi_hi_2 = cat(_io_out_s_T_268, _io_out_s_T_269) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_hi_hi_20 = cat(io_out_s_hi_hi_hi_2, _io_out_s_T_270) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_hi_31 = cat(io_out_s_hi_hi_20, io_out_s_hi_lo_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node _io_out_s_T_276 = cat(io_out_s_hi_31, io_out_s_lo_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node _io_out_s_T_277 = bits(_io_out_s_T_276, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 94:48] node _io_out_s_T_278 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:28] node _io_out_s_T_279 = mux(_io_out_s_T_278, UInt<10>(0h3ff), UInt<10>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:22] node _io_out_s_T_280 = bits(io.in, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:36] node _io_out_s_T_281 = bits(io.in, 10, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:42] node _io_out_s_T_282 = bits(io.in, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:51] node _io_out_s_T_283 = bits(io.in, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:57] node _io_out_s_T_284 = bits(io.in, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:63] node _io_out_s_T_285 = bits(io.in, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:69] node _io_out_s_T_286 = bits(io.in, 5, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:76] node io_out_s_lo_lo_3 = cat(_io_out_s_T_286, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_lo_hi_8 = cat(_io_out_s_T_284, _io_out_s_T_285) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_lo_26 = cat(io_out_s_lo_hi_8, io_out_s_lo_lo_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_hi_lo_3 = cat(_io_out_s_T_282, _io_out_s_T_283) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_hi_hi_hi_3 = cat(_io_out_s_T_279, _io_out_s_T_280) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_hi_hi_21 = cat(io_out_s_hi_hi_hi_3, _io_out_s_T_281) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node io_out_s_hi_32 = cat(io_out_s_hi_hi_21, io_out_s_hi_lo_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node _io_out_s_T_287 = cat(io_out_s_hi_32, io_out_s_lo_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 44:17] node _io_out_s_T_288 = bits(_io_out_s_T_287, 19, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 94:58] node io_out_s_lo_hi_9 = cat(_io_out_s_T_288, UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 94:21] node io_out_s_lo_27 = cat(io_out_s_lo_hi_9, UInt<7>(0h6f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 94:21] node io_out_s_hi_hi_22 = cat(_io_out_s_T_255, _io_out_s_T_266) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 94:21] node io_out_s_hi_33 = cat(io_out_s_hi_hi_22, _io_out_s_T_277) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 94:21] node _io_out_s_T_289 = cat(io_out_s_hi_33, io_out_s_lo_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 94:21] node _io_out_s_T_290 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_291 = cat(UInt<2>(0h1), _io_out_s_T_290) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_292 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:29] node _io_out_s_T_293 = cat(UInt<2>(0h1), _io_out_s_T_292) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 31:17] node _io_out_s_T_294 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_13 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_13.bits, _io_out_s_T_289 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_13.rd, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_13.rs1, _io_out_s_T_291 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_13.rs2, _io_out_s_T_293 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_13.rs3, _io_out_s_T_294 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_295 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:27] node _io_out_s_T_296 = mux(_io_out_s_T_295, UInt<5>(0h1f), UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:22] node _io_out_s_T_297 = bits(io.in, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:35] node _io_out_s_T_298 = bits(io.in, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:43] node _io_out_s_T_299 = bits(io.in, 11, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:49] node _io_out_s_T_300 = bits(io.in, 4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:59] node io_out_s_lo_hi_10 = cat(_io_out_s_T_299, _io_out_s_T_300) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_lo_28 = cat(io_out_s_lo_hi_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_hi_hi_23 = cat(_io_out_s_T_296, _io_out_s_T_297) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_hi_34 = cat(io_out_s_hi_hi_23, _io_out_s_T_298) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node _io_out_s_T_301 = cat(io_out_s_hi_34, io_out_s_lo_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node _io_out_s_T_302 = bits(_io_out_s_T_301, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 95:29] node _io_out_s_T_303 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:27] node _io_out_s_T_304 = mux(_io_out_s_T_303, UInt<5>(0h1f), UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:22] node _io_out_s_T_305 = bits(io.in, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:35] node _io_out_s_T_306 = bits(io.in, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:43] node _io_out_s_T_307 = bits(io.in, 11, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:49] node _io_out_s_T_308 = bits(io.in, 4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:59] node io_out_s_lo_hi_11 = cat(_io_out_s_T_307, _io_out_s_T_308) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_lo_29 = cat(io_out_s_lo_hi_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_hi_hi_24 = cat(_io_out_s_T_304, _io_out_s_T_305) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_hi_35 = cat(io_out_s_hi_hi_24, _io_out_s_T_306) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node _io_out_s_T_309 = cat(io_out_s_hi_35, io_out_s_lo_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node _io_out_s_T_310 = bits(_io_out_s_T_309, 10, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 95:39] node _io_out_s_T_311 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_312 = cat(UInt<2>(0h1), _io_out_s_T_311) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_313 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:27] node _io_out_s_T_314 = mux(_io_out_s_T_313, UInt<5>(0h1f), UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:22] node _io_out_s_T_315 = bits(io.in, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:35] node _io_out_s_T_316 = bits(io.in, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:43] node _io_out_s_T_317 = bits(io.in, 11, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:49] node _io_out_s_T_318 = bits(io.in, 4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:59] node io_out_s_lo_hi_12 = cat(_io_out_s_T_317, _io_out_s_T_318) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_lo_30 = cat(io_out_s_lo_hi_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_hi_hi_25 = cat(_io_out_s_T_314, _io_out_s_T_315) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_hi_36 = cat(io_out_s_hi_hi_25, _io_out_s_T_316) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node _io_out_s_T_319 = cat(io_out_s_hi_36, io_out_s_lo_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node _io_out_s_T_320 = bits(_io_out_s_T_319, 4, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 95:71] node _io_out_s_T_321 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:27] node _io_out_s_T_322 = mux(_io_out_s_T_321, UInt<5>(0h1f), UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:22] node _io_out_s_T_323 = bits(io.in, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:35] node _io_out_s_T_324 = bits(io.in, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:43] node _io_out_s_T_325 = bits(io.in, 11, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:49] node _io_out_s_T_326 = bits(io.in, 4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:59] node io_out_s_lo_hi_13 = cat(_io_out_s_T_325, _io_out_s_T_326) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_lo_31 = cat(io_out_s_lo_hi_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_hi_hi_26 = cat(_io_out_s_T_322, _io_out_s_T_323) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_hi_37 = cat(io_out_s_hi_hi_26, _io_out_s_T_324) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node _io_out_s_T_327 = cat(io_out_s_hi_37, io_out_s_lo_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node _io_out_s_T_328 = bits(_io_out_s_T_327, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 95:82] node io_out_s_lo_lo_4 = cat(_io_out_s_T_328, UInt<7>(0h63)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 95:24] node io_out_s_lo_hi_14 = cat(UInt<3>(0h0), _io_out_s_T_320) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 95:24] node io_out_s_lo_32 = cat(io_out_s_lo_hi_14, io_out_s_lo_lo_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 95:24] node io_out_s_hi_lo_4 = cat(UInt<5>(0h0), _io_out_s_T_312) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 95:24] node io_out_s_hi_hi_27 = cat(_io_out_s_T_302, _io_out_s_T_310) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 95:24] node io_out_s_hi_38 = cat(io_out_s_hi_hi_27, io_out_s_hi_lo_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 95:24] node _io_out_s_T_329 = cat(io_out_s_hi_38, io_out_s_lo_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 95:24] node _io_out_s_T_330 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_331 = cat(UInt<2>(0h1), _io_out_s_T_330) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_332 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_333 = cat(UInt<2>(0h1), _io_out_s_T_332) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_334 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_14 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_14.bits, _io_out_s_T_329 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_14.rd, _io_out_s_T_331 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_14.rs1, _io_out_s_T_333 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_14.rs2, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_14.rs3, _io_out_s_T_334 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_335 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:27] node _io_out_s_T_336 = mux(_io_out_s_T_335, UInt<5>(0h1f), UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:22] node _io_out_s_T_337 = bits(io.in, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:35] node _io_out_s_T_338 = bits(io.in, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:43] node _io_out_s_T_339 = bits(io.in, 11, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:49] node _io_out_s_T_340 = bits(io.in, 4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:59] node io_out_s_lo_hi_15 = cat(_io_out_s_T_339, _io_out_s_T_340) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_lo_33 = cat(io_out_s_lo_hi_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_hi_hi_28 = cat(_io_out_s_T_336, _io_out_s_T_337) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_hi_39 = cat(io_out_s_hi_hi_28, _io_out_s_T_338) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node _io_out_s_T_341 = cat(io_out_s_hi_39, io_out_s_lo_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node _io_out_s_T_342 = bits(_io_out_s_T_341, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 96:29] node _io_out_s_T_343 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:27] node _io_out_s_T_344 = mux(_io_out_s_T_343, UInt<5>(0h1f), UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:22] node _io_out_s_T_345 = bits(io.in, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:35] node _io_out_s_T_346 = bits(io.in, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:43] node _io_out_s_T_347 = bits(io.in, 11, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:49] node _io_out_s_T_348 = bits(io.in, 4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:59] node io_out_s_lo_hi_16 = cat(_io_out_s_T_347, _io_out_s_T_348) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_lo_34 = cat(io_out_s_lo_hi_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_hi_hi_29 = cat(_io_out_s_T_344, _io_out_s_T_345) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_hi_40 = cat(io_out_s_hi_hi_29, _io_out_s_T_346) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node _io_out_s_T_349 = cat(io_out_s_hi_40, io_out_s_lo_34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node _io_out_s_T_350 = bits(_io_out_s_T_349, 10, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 96:39] node _io_out_s_T_351 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_352 = cat(UInt<2>(0h1), _io_out_s_T_351) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_353 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:27] node _io_out_s_T_354 = mux(_io_out_s_T_353, UInt<5>(0h1f), UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:22] node _io_out_s_T_355 = bits(io.in, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:35] node _io_out_s_T_356 = bits(io.in, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:43] node _io_out_s_T_357 = bits(io.in, 11, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:49] node _io_out_s_T_358 = bits(io.in, 4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:59] node io_out_s_lo_hi_17 = cat(_io_out_s_T_357, _io_out_s_T_358) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_lo_35 = cat(io_out_s_lo_hi_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_hi_hi_30 = cat(_io_out_s_T_354, _io_out_s_T_355) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_hi_41 = cat(io_out_s_hi_hi_30, _io_out_s_T_356) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node _io_out_s_T_359 = cat(io_out_s_hi_41, io_out_s_lo_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node _io_out_s_T_360 = bits(_io_out_s_T_359, 4, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 96:71] node _io_out_s_T_361 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:27] node _io_out_s_T_362 = mux(_io_out_s_T_361, UInt<5>(0h1f), UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:22] node _io_out_s_T_363 = bits(io.in, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:35] node _io_out_s_T_364 = bits(io.in, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:43] node _io_out_s_T_365 = bits(io.in, 11, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:49] node _io_out_s_T_366 = bits(io.in, 4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:59] node io_out_s_lo_hi_18 = cat(_io_out_s_T_365, _io_out_s_T_366) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_lo_36 = cat(io_out_s_lo_hi_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_hi_hi_31 = cat(_io_out_s_T_362, _io_out_s_T_363) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node io_out_s_hi_42 = cat(io_out_s_hi_hi_31, _io_out_s_T_364) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node _io_out_s_T_367 = cat(io_out_s_hi_42, io_out_s_lo_36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 45:17] node _io_out_s_T_368 = bits(_io_out_s_T_367, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 96:82] node io_out_s_lo_lo_5 = cat(_io_out_s_T_368, UInt<7>(0h63)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 96:24] node io_out_s_lo_hi_19 = cat(UInt<3>(0h1), _io_out_s_T_360) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 96:24] node io_out_s_lo_37 = cat(io_out_s_lo_hi_19, io_out_s_lo_lo_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 96:24] node io_out_s_hi_lo_5 = cat(UInt<5>(0h0), _io_out_s_T_352) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 96:24] node io_out_s_hi_hi_32 = cat(_io_out_s_T_342, _io_out_s_T_350) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 96:24] node io_out_s_hi_43 = cat(io_out_s_hi_hi_32, io_out_s_hi_lo_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 96:24] node _io_out_s_T_369 = cat(io_out_s_hi_43, io_out_s_lo_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 96:24] node _io_out_s_T_370 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:29] node _io_out_s_T_371 = cat(UInt<2>(0h1), _io_out_s_T_370) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 30:17] node _io_out_s_T_372 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_15 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_15.bits, _io_out_s_T_369 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_15.rd, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_15.rs1, _io_out_s_T_371 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_15.rs2, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_15.rs3, _io_out_s_T_372 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_load_opc_T = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_load_opc_T_1 = orr(_io_out_s_load_opc_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 113:27] node io_out_s_load_opc = mux(_io_out_s_load_opc_T_1, UInt<7>(0h3), UInt<7>(0h1f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 113:23] node _io_out_s_T_373 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 46:20] node _io_out_s_T_374 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 46:27] node _io_out_s_T_375 = cat(_io_out_s_T_373, _io_out_s_T_374) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 46:18] node _io_out_s_T_376 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_377 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node io_out_s_lo_38 = cat(_io_out_s_T_377, UInt<7>(0h13)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 114:24] node io_out_s_hi_hi_33 = cat(_io_out_s_T_375, _io_out_s_T_376) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 114:24] node io_out_s_hi_44 = cat(io_out_s_hi_hi_33, UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 114:24] node _io_out_s_T_378 = cat(io_out_s_hi_44, io_out_s_lo_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 114:24] node _io_out_s_T_379 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_380 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_381 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_T_382 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_16 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_16.bits, _io_out_s_T_378 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_16.rd, _io_out_s_T_379 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_16.rs1, _io_out_s_T_380 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_16.rs2, _io_out_s_T_381 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_16.rs3, _io_out_s_T_382 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_383 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 38:22] node _io_out_s_T_384 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 38:30] node _io_out_s_T_385 = bits(io.in, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 38:37] node io_out_s_lo_39 = cat(_io_out_s_T_385, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 38:20] node io_out_s_hi_45 = cat(_io_out_s_T_383, _io_out_s_T_384) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 38:20] node _io_out_s_T_386 = cat(io_out_s_hi_45, io_out_s_lo_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 38:20] node _io_out_s_T_387 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node io_out_s_lo_40 = cat(_io_out_s_T_387, UInt<7>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 117:25] node io_out_s_hi_hi_34 = cat(_io_out_s_T_386, UInt<5>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 117:25] node io_out_s_hi_46 = cat(io_out_s_hi_hi_34, UInt<3>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 117:25] node _io_out_s_T_388 = cat(io_out_s_hi_46, io_out_s_lo_40) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 117:25] node _io_out_s_T_389 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_390 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_T_391 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_17 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_17.bits, _io_out_s_T_388 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_17.rd, _io_out_s_T_389 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_17.rs1, UInt<5>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_17.rs2, _io_out_s_T_390 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_17.rs3, _io_out_s_T_391 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_392 = bits(io.in, 3, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 37:22] node _io_out_s_T_393 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 37:30] node _io_out_s_T_394 = bits(io.in, 6, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 37:37] node io_out_s_lo_41 = cat(_io_out_s_T_394, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 37:20] node io_out_s_hi_47 = cat(_io_out_s_T_392, _io_out_s_T_393) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 37:20] node _io_out_s_T_395 = cat(io_out_s_hi_47, io_out_s_lo_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 37:20] node _io_out_s_T_396 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node io_out_s_lo_42 = cat(_io_out_s_T_396, io_out_s_load_opc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 116:24] node io_out_s_hi_hi_35 = cat(_io_out_s_T_395, UInt<5>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 116:24] node io_out_s_hi_48 = cat(io_out_s_hi_hi_35, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 116:24] node _io_out_s_T_397 = cat(io_out_s_hi_48, io_out_s_lo_42) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 116:24] node _io_out_s_T_398 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_399 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_T_400 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_18 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_18.bits, _io_out_s_T_397 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_18.rd, _io_out_s_T_398 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_18.rs1, UInt<5>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_18.rs2, _io_out_s_T_399 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_18.rs3, _io_out_s_T_400 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_401 = bits(io.in, 4, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 38:22] node _io_out_s_T_402 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 38:30] node _io_out_s_T_403 = bits(io.in, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 38:37] node io_out_s_lo_43 = cat(_io_out_s_T_403, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 38:20] node io_out_s_hi_49 = cat(_io_out_s_T_401, _io_out_s_T_402) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 38:20] node _io_out_s_T_404 = cat(io_out_s_hi_49, io_out_s_lo_43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 38:20] node _io_out_s_T_405 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node io_out_s_lo_44 = cat(_io_out_s_T_405, io_out_s_load_opc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 115:24] node io_out_s_hi_hi_36 = cat(_io_out_s_T_404, UInt<5>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 115:24] node io_out_s_hi_50 = cat(io_out_s_hi_hi_36, UInt<3>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 115:24] node _io_out_s_T_406 = cat(io_out_s_hi_50, io_out_s_lo_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 115:24] node _io_out_s_T_407 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_408 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_T_409 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_19 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_19.bits, _io_out_s_T_406 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_19.rd, _io_out_s_T_407 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_19.rs1, UInt<5>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_19.rs2, _io_out_s_T_408 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_19.rs3, _io_out_s_T_409 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_mv_T = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_mv_T_1 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node io_out_s_mv_lo = cat(_io_out_s_mv_T_1, UInt<7>(0h33)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 132:22] node io_out_s_mv_hi_hi = cat(_io_out_s_mv_T, UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 132:22] node io_out_s_mv_hi = cat(io_out_s_mv_hi_hi, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 132:22] node _io_out_s_mv_T_2 = cat(io_out_s_mv_hi, io_out_s_mv_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 132:22] node _io_out_s_mv_T_3 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_mv_T_4 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_mv_T_5 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_mv : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_mv.bits, _io_out_s_mv_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_mv.rd, _io_out_s_mv_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_mv.rs1, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_mv.rs2, _io_out_s_mv_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_mv.rs3, _io_out_s_mv_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_add_T = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_add_T_1 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_add_T_2 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node io_out_s_add_lo = cat(_io_out_s_add_T_2, UInt<7>(0h33)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 134:25] node io_out_s_add_hi_hi = cat(_io_out_s_add_T, _io_out_s_add_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 134:25] node io_out_s_add_hi = cat(io_out_s_add_hi_hi, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 134:25] node _io_out_s_add_T_3 = cat(io_out_s_add_hi, io_out_s_add_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 134:25] node _io_out_s_add_T_4 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_add_T_5 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_add_T_6 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_add_T_7 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_add : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_add.bits, _io_out_s_add_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_add.rd, _io_out_s_add_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_add.rs1, _io_out_s_add_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_add.rs2, _io_out_s_add_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_add.rs3, _io_out_s_add_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_jr_T = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_jr_T_1 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node io_out_s_jr_lo = cat(UInt<5>(0h0), UInt<7>(0h67)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 135:19] node io_out_s_jr_hi_hi = cat(_io_out_s_jr_T, _io_out_s_jr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 135:19] node io_out_s_jr_hi = cat(io_out_s_jr_hi_hi, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 135:19] node io_out_s_jr = cat(io_out_s_jr_hi, io_out_s_jr_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 135:19] node _io_out_s_reserved_T = shr(io_out_s_jr, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 136:29] node io_out_s_reserved = cat(_io_out_s_reserved_T, UInt<7>(0h1f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 136:25] node _io_out_s_jr_reserved_T = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_jr_reserved_T_1 = orr(_io_out_s_jr_reserved_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 137:37] node _io_out_s_jr_reserved_T_2 = mux(_io_out_s_jr_reserved_T_1, io_out_s_jr, io_out_s_reserved) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 137:33] node _io_out_s_jr_reserved_T_3 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_jr_reserved_T_4 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_jr_reserved_T_5 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_jr_reserved : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_jr_reserved.bits, _io_out_s_jr_reserved_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_jr_reserved.rd, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_jr_reserved.rs1, _io_out_s_jr_reserved_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_jr_reserved.rs2, _io_out_s_jr_reserved_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_jr_reserved.rs3, _io_out_s_jr_reserved_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_jr_mv_T = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_jr_mv_T_1 = orr(_io_out_s_jr_mv_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 138:27] node io_out_s_jr_mv = mux(_io_out_s_jr_mv_T_1, io_out_s_mv, io_out_s_jr_reserved) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 138:22] node _io_out_s_jalr_T = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_jalr_T_1 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node io_out_s_jalr_lo = cat(UInt<5>(0h1), UInt<7>(0h67)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 139:21] node io_out_s_jalr_hi_hi = cat(_io_out_s_jalr_T, _io_out_s_jalr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 139:21] node io_out_s_jalr_hi = cat(io_out_s_jalr_hi_hi, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 139:21] node io_out_s_jalr = cat(io_out_s_jalr_hi, io_out_s_jalr_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 139:21] node _io_out_s_ebreak_T = shr(io_out_s_jr, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 140:27] node _io_out_s_ebreak_T_1 = cat(_io_out_s_ebreak_T, UInt<7>(0h73)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 140:23] node io_out_s_ebreak = or(_io_out_s_ebreak_T_1, UInt<21>(0h100000)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 140:46] node _io_out_s_jalr_ebreak_T = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_jalr_ebreak_T_1 = orr(_io_out_s_jalr_ebreak_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 141:37] node _io_out_s_jalr_ebreak_T_2 = mux(_io_out_s_jalr_ebreak_T_1, io_out_s_jalr, io_out_s_ebreak) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 141:33] node _io_out_s_jalr_ebreak_T_3 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_jalr_ebreak_T_4 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_jalr_ebreak_T_5 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_jalr_ebreak : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_jalr_ebreak.bits, _io_out_s_jalr_ebreak_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_jalr_ebreak.rd, UInt<5>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_jalr_ebreak.rs1, _io_out_s_jalr_ebreak_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_jalr_ebreak.rs2, _io_out_s_jalr_ebreak_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_jalr_ebreak.rs3, _io_out_s_jalr_ebreak_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_jalr_add_T = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_jalr_add_T_1 = orr(_io_out_s_jalr_add_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 142:30] node io_out_s_jalr_add = mux(_io_out_s_jalr_add_T_1, io_out_s_add, io_out_s_jalr_ebreak) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 142:25] node _io_out_s_T_410 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 143:12] node io_out_s_20 = mux(_io_out_s_T_410, io_out_s_jalr_add, io_out_s_jr_mv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 143:10] node _io_out_s_T_411 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 40:22] node _io_out_s_T_412 = bits(io.in, 12, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 40:30] node io_out_s_hi_51 = cat(_io_out_s_T_411, _io_out_s_T_412) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 40:20] node _io_out_s_T_413 = cat(io_out_s_hi_51, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 40:20] node _io_out_s_T_414 = shr(_io_out_s_T_413, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 124:34] node _io_out_s_T_415 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_T_416 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 40:22] node _io_out_s_T_417 = bits(io.in, 12, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 40:30] node io_out_s_hi_52 = cat(_io_out_s_T_416, _io_out_s_T_417) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 40:20] node _io_out_s_T_418 = cat(io_out_s_hi_52, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 40:20] node _io_out_s_T_419 = bits(_io_out_s_T_418, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 124:66] node io_out_s_lo_hi_20 = cat(UInt<3>(0h3), _io_out_s_T_419) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 124:25] node io_out_s_lo_45 = cat(io_out_s_lo_hi_20, UInt<7>(0h27)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 124:25] node io_out_s_hi_hi_37 = cat(_io_out_s_T_414, _io_out_s_T_415) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 124:25] node io_out_s_hi_53 = cat(io_out_s_hi_hi_37, UInt<5>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 124:25] node _io_out_s_T_420 = cat(io_out_s_hi_53, io_out_s_lo_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 124:25] node _io_out_s_T_421 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_422 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_T_423 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_21 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_21.bits, _io_out_s_T_420 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_21.rd, _io_out_s_T_421 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_21.rs1, UInt<5>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_21.rs2, _io_out_s_T_422 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_21.rs3, _io_out_s_T_423 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_424 = bits(io.in, 8, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 39:22] node _io_out_s_T_425 = bits(io.in, 12, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 39:30] node io_out_s_hi_54 = cat(_io_out_s_T_424, _io_out_s_T_425) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 39:20] node _io_out_s_T_426 = cat(io_out_s_hi_54, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 39:20] node _io_out_s_T_427 = shr(_io_out_s_T_426, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 123:33] node _io_out_s_T_428 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_T_429 = bits(io.in, 8, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 39:22] node _io_out_s_T_430 = bits(io.in, 12, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 39:30] node io_out_s_hi_55 = cat(_io_out_s_T_429, _io_out_s_T_430) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 39:20] node _io_out_s_T_431 = cat(io_out_s_hi_55, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 39:20] node _io_out_s_T_432 = bits(_io_out_s_T_431, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 123:65] node io_out_s_lo_hi_21 = cat(UInt<3>(0h2), _io_out_s_T_432) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 123:24] node io_out_s_lo_46 = cat(io_out_s_lo_hi_21, UInt<7>(0h23)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 123:24] node io_out_s_hi_hi_38 = cat(_io_out_s_T_427, _io_out_s_T_428) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 123:24] node io_out_s_hi_56 = cat(io_out_s_hi_hi_38, UInt<5>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 123:24] node _io_out_s_T_433 = cat(io_out_s_hi_56, io_out_s_lo_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 123:24] node _io_out_s_T_434 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_435 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_T_436 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_22 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_22.bits, _io_out_s_T_433 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_22.rd, _io_out_s_T_434 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_22.rs1, UInt<5>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_22.rs2, _io_out_s_T_435 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_22.rs3, _io_out_s_T_436 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_437 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 40:22] node _io_out_s_T_438 = bits(io.in, 12, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 40:30] node io_out_s_hi_57 = cat(_io_out_s_T_437, _io_out_s_T_438) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 40:20] node _io_out_s_T_439 = cat(io_out_s_hi_57, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 40:20] node _io_out_s_T_440 = shr(_io_out_s_T_439, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 122:33] node _io_out_s_T_441 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_T_442 = bits(io.in, 9, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 40:22] node _io_out_s_T_443 = bits(io.in, 12, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 40:30] node io_out_s_hi_58 = cat(_io_out_s_T_442, _io_out_s_T_443) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 40:20] node _io_out_s_T_444 = cat(io_out_s_hi_58, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 40:20] node _io_out_s_T_445 = bits(_io_out_s_T_444, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 122:65] node io_out_s_lo_hi_22 = cat(UInt<3>(0h3), _io_out_s_T_445) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 122:24] node io_out_s_lo_47 = cat(io_out_s_lo_hi_22, UInt<7>(0h23)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 122:24] node io_out_s_hi_hi_39 = cat(_io_out_s_T_440, _io_out_s_T_441) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 122:24] node io_out_s_hi_59 = cat(io_out_s_hi_hi_39, UInt<5>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 122:24] node _io_out_s_T_446 = cat(io_out_s_hi_59, io_out_s_lo_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 122:24] node _io_out_s_T_447 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node _io_out_s_T_448 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 32:14] node _io_out_s_T_449 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_23 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_23.bits, _io_out_s_T_446 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_23.rd, _io_out_s_T_447 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_23.rs1, UInt<5>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_23.rs2, _io_out_s_T_448 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_23.rs3, _io_out_s_T_449 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_450 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:36] node _io_out_s_T_451 = bits(io.in, 19, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:57] node _io_out_s_T_452 = bits(io.in, 24, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:79] node _io_out_s_T_453 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_24 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_24.bits, io.in @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_24.rd, _io_out_s_T_450 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_24.rs1, _io_out_s_T_451 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_24.rs2, _io_out_s_T_452 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_24.rs3, _io_out_s_T_453 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_454 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:36] node _io_out_s_T_455 = bits(io.in, 19, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:57] node _io_out_s_T_456 = bits(io.in, 24, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:79] node _io_out_s_T_457 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_25 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_25.bits, io.in @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_25.rd, _io_out_s_T_454 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_25.rs1, _io_out_s_T_455 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_25.rs2, _io_out_s_T_456 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_25.rs3, _io_out_s_T_457 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_458 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:36] node _io_out_s_T_459 = bits(io.in, 19, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:57] node _io_out_s_T_460 = bits(io.in, 24, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:79] node _io_out_s_T_461 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_26 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_26.bits, io.in @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_26.rd, _io_out_s_T_458 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_26.rs1, _io_out_s_T_459 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_26.rs2, _io_out_s_T_460 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_26.rs3, _io_out_s_T_461 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_462 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:36] node _io_out_s_T_463 = bits(io.in, 19, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:57] node _io_out_s_T_464 = bits(io.in, 24, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:79] node _io_out_s_T_465 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_27 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_27.bits, io.in @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_27.rd, _io_out_s_T_462 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_27.rs1, _io_out_s_T_463 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_27.rs2, _io_out_s_T_464 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_27.rs3, _io_out_s_T_465 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_466 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:36] node _io_out_s_T_467 = bits(io.in, 19, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:57] node _io_out_s_T_468 = bits(io.in, 24, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:79] node _io_out_s_T_469 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_28 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_28.bits, io.in @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_28.rd, _io_out_s_T_466 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_28.rs1, _io_out_s_T_467 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_28.rs2, _io_out_s_T_468 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_28.rs3, _io_out_s_T_469 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_470 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:36] node _io_out_s_T_471 = bits(io.in, 19, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:57] node _io_out_s_T_472 = bits(io.in, 24, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:79] node _io_out_s_T_473 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_29 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_29.bits, io.in @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_29.rd, _io_out_s_T_470 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_29.rs1, _io_out_s_T_471 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_29.rs2, _io_out_s_T_472 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_29.rs3, _io_out_s_T_473 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_474 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:36] node _io_out_s_T_475 = bits(io.in, 19, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:57] node _io_out_s_T_476 = bits(io.in, 24, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:79] node _io_out_s_T_477 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_30 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_30.bits, io.in @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_30.rd, _io_out_s_T_474 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_30.rs1, _io_out_s_T_475 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_30.rs2, _io_out_s_T_476 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_30.rs3, _io_out_s_T_477 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_s_T_478 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:36] node _io_out_s_T_479 = bits(io.in, 19, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:57] node _io_out_s_T_480 = bits(io.in, 24, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:79] node _io_out_s_T_481 = bits(io.in, 31, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 20:101] wire io_out_s_31 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 21:19] connect io_out_s_31.bits, io.in @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 22:14] connect io_out_s_31.rd, _io_out_s_T_478 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 23:12] connect io_out_s_31.rs1, _io_out_s_T_479 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 24:13] connect io_out_s_31.rs2, _io_out_s_T_480 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 25:13] connect io_out_s_31.rs3, _io_out_s_T_481 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 26:13] node _io_out_T = bits(io.in, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 154:12] node _io_out_T_1 = bits(io.in, 15, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 154:20] node _io_out_T_2 = cat(_io_out_T, _io_out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 154:10] node _io_out_T_3 = eq(_io_out_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_4 = mux(_io_out_T_3, io_out_s_1, io_out_s_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_5 = eq(_io_out_T_2, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_6 = mux(_io_out_T_5, io_out_s_2, _io_out_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_7 = eq(_io_out_T_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_8 = mux(_io_out_T_7, io_out_s_3, _io_out_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_9 = eq(_io_out_T_2, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_10 = mux(_io_out_T_9, io_out_s_4, _io_out_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_11 = eq(_io_out_T_2, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_12 = mux(_io_out_T_11, io_out_s_5, _io_out_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_13 = eq(_io_out_T_2, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_14 = mux(_io_out_T_13, io_out_s_6, _io_out_T_12) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_15 = eq(_io_out_T_2, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_16 = mux(_io_out_T_15, io_out_s_7, _io_out_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_17 = eq(_io_out_T_2, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_18 = mux(_io_out_T_17, io_out_s_8, _io_out_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_19 = eq(_io_out_T_2, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_20 = mux(_io_out_T_19, io_out_s_9, _io_out_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_21 = eq(_io_out_T_2, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_22 = mux(_io_out_T_21, io_out_s_10, _io_out_T_20) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_23 = eq(_io_out_T_2, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_24 = mux(_io_out_T_23, io_out_s_11, _io_out_T_22) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_25 = eq(_io_out_T_2, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_26 = mux(_io_out_T_25, io_out_s_12, _io_out_T_24) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_27 = eq(_io_out_T_2, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_28 = mux(_io_out_T_27, io_out_s_13, _io_out_T_26) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_29 = eq(_io_out_T_2, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_30 = mux(_io_out_T_29, io_out_s_14, _io_out_T_28) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_31 = eq(_io_out_T_2, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_32 = mux(_io_out_T_31, io_out_s_15, _io_out_T_30) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_33 = eq(_io_out_T_2, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_34 = mux(_io_out_T_33, io_out_s_16, _io_out_T_32) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_35 = eq(_io_out_T_2, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_36 = mux(_io_out_T_35, io_out_s_17, _io_out_T_34) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_37 = eq(_io_out_T_2, UInt<5>(0h12)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_38 = mux(_io_out_T_37, io_out_s_18, _io_out_T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_39 = eq(_io_out_T_2, UInt<5>(0h13)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_40 = mux(_io_out_T_39, io_out_s_19, _io_out_T_38) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_41 = eq(_io_out_T_2, UInt<5>(0h14)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_42 = mux(_io_out_T_41, io_out_s_20, _io_out_T_40) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_43 = eq(_io_out_T_2, UInt<5>(0h15)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_44 = mux(_io_out_T_43, io_out_s_21, _io_out_T_42) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_45 = eq(_io_out_T_2, UInt<5>(0h16)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_46 = mux(_io_out_T_45, io_out_s_22, _io_out_T_44) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_47 = eq(_io_out_T_2, UInt<5>(0h17)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_48 = mux(_io_out_T_47, io_out_s_23, _io_out_T_46) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_49 = eq(_io_out_T_2, UInt<5>(0h18)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_50 = mux(_io_out_T_49, io_out_s_24, _io_out_T_48) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_51 = eq(_io_out_T_2, UInt<5>(0h19)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_52 = mux(_io_out_T_51, io_out_s_25, _io_out_T_50) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_53 = eq(_io_out_T_2, UInt<5>(0h1a)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_54 = mux(_io_out_T_53, io_out_s_26, _io_out_T_52) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_55 = eq(_io_out_T_2, UInt<5>(0h1b)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_56 = mux(_io_out_T_55, io_out_s_27, _io_out_T_54) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_57 = eq(_io_out_T_2, UInt<5>(0h1c)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_58 = mux(_io_out_T_57, io_out_s_28, _io_out_T_56) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_59 = eq(_io_out_T_2, UInt<5>(0h1d)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_60 = mux(_io_out_T_59, io_out_s_29, _io_out_T_58) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_61 = eq(_io_out_T_2, UInt<5>(0h1e)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_62 = mux(_io_out_T_61, io_out_s_30, _io_out_T_60) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_out_T_63 = eq(_io_out_T_2, UInt<5>(0h1f)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_out_T_64 = mux(_io_out_T_63, io_out_s_31, _io_out_T_62) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] connect io.out, _io_out_T_64 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 201:12] node _io_ill_s_T = bits(io.in, 12, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 158:19] node _io_ill_s_T_1 = orr(_io_ill_s_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 158:27] node io_ill_s_0 = eq(_io_ill_s_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 158:16] node _io_ill_s_T_2 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node io_ill_s_9 = eq(_io_ill_s_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 167:47] node _io_ill_s_T_3 = bits(io.in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 168:19] node _io_ill_s_T_4 = bits(io.in, 6, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 168:27] node _io_ill_s_T_5 = orr(_io_ill_s_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 168:34] node _io_ill_s_T_6 = or(_io_ill_s_T_3, _io_ill_s_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 168:24] node io_ill_s_11 = eq(_io_ill_s_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 168:16] node _io_ill_s_T_7 = bits(io.in, 12, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 169:22] node _io_ill_s_T_8 = andr(_io_ill_s_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 169:31] node _io_ill_s_T_9 = bits(io.in, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 169:69] node _io_ill_s_T_10 = eq(_io_ill_s_T_9, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 169:73] node io_ill_s_12 = and(_io_ill_s_T_8, _io_ill_s_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 169:36] node _io_ill_s_T_11 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node io_ill_s_18 = eq(_io_ill_s_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 175:18] node _io_ill_s_T_12 = bits(io.in, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 33:13] node io_ill_s_19 = eq(_io_ill_s_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 175:18] node _io_ill_s_T_13 = bits(io.in, 12, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 177:21] node _io_ill_s_T_14 = orr(_io_ill_s_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 177:29] node io_ill_s_20 = eq(_io_ill_s_T_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 177:18] node _io_ill_T = bits(io.in, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 186:12] node _io_ill_T_1 = bits(io.in, 15, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 186:20] node _io_ill_T_2 = cat(_io_ill_T, _io_ill_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 186:10] node _io_ill_T_3 = eq(_io_ill_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_4 = mux(_io_ill_T_3, UInt<1>(0h0), io_ill_s_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_5 = eq(_io_ill_T_2, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_6 = mux(_io_ill_T_5, UInt<1>(0h0), _io_ill_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_7 = eq(_io_ill_T_2, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_8 = mux(_io_ill_T_7, UInt<1>(0h0), _io_ill_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_9 = eq(_io_ill_T_2, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_10 = mux(_io_ill_T_9, UInt<1>(0h1), _io_ill_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_11 = eq(_io_ill_T_2, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_12 = mux(_io_ill_T_11, UInt<1>(0h0), _io_ill_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_13 = eq(_io_ill_T_2, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_14 = mux(_io_ill_T_13, UInt<1>(0h0), _io_ill_T_12) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_15 = eq(_io_ill_T_2, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_16 = mux(_io_ill_T_15, UInt<1>(0h0), _io_ill_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_17 = eq(_io_ill_T_2, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_18 = mux(_io_ill_T_17, UInt<1>(0h0), _io_ill_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_19 = eq(_io_ill_T_2, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_20 = mux(_io_ill_T_19, io_ill_s_9, _io_ill_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_21 = eq(_io_ill_T_2, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_22 = mux(_io_ill_T_21, UInt<1>(0h0), _io_ill_T_20) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_23 = eq(_io_ill_T_2, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_24 = mux(_io_ill_T_23, io_ill_s_11, _io_ill_T_22) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_25 = eq(_io_ill_T_2, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_26 = mux(_io_ill_T_25, io_ill_s_12, _io_ill_T_24) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_27 = eq(_io_ill_T_2, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_28 = mux(_io_ill_T_27, UInt<1>(0h0), _io_ill_T_26) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_29 = eq(_io_ill_T_2, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_30 = mux(_io_ill_T_29, UInt<1>(0h0), _io_ill_T_28) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_31 = eq(_io_ill_T_2, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_32 = mux(_io_ill_T_31, UInt<1>(0h0), _io_ill_T_30) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_33 = eq(_io_ill_T_2, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_34 = mux(_io_ill_T_33, UInt<1>(0h0), _io_ill_T_32) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_35 = eq(_io_ill_T_2, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_36 = mux(_io_ill_T_35, UInt<1>(0h0), _io_ill_T_34) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_37 = eq(_io_ill_T_2, UInt<5>(0h12)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_38 = mux(_io_ill_T_37, io_ill_s_18, _io_ill_T_36) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_39 = eq(_io_ill_T_2, UInt<5>(0h13)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_40 = mux(_io_ill_T_39, io_ill_s_19, _io_ill_T_38) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_41 = eq(_io_ill_T_2, UInt<5>(0h14)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_42 = mux(_io_ill_T_41, io_ill_s_20, _io_ill_T_40) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_43 = eq(_io_ill_T_2, UInt<5>(0h15)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_44 = mux(_io_ill_T_43, UInt<1>(0h0), _io_ill_T_42) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_45 = eq(_io_ill_T_2, UInt<5>(0h16)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_46 = mux(_io_ill_T_45, UInt<1>(0h0), _io_ill_T_44) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_47 = eq(_io_ill_T_2, UInt<5>(0h17)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_48 = mux(_io_ill_T_47, UInt<1>(0h0), _io_ill_T_46) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_49 = eq(_io_ill_T_2, UInt<5>(0h18)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_50 = mux(_io_ill_T_49, UInt<1>(0h0), _io_ill_T_48) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_51 = eq(_io_ill_T_2, UInt<5>(0h19)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_52 = mux(_io_ill_T_51, UInt<1>(0h0), _io_ill_T_50) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_53 = eq(_io_ill_T_2, UInt<5>(0h1a)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_54 = mux(_io_ill_T_53, UInt<1>(0h0), _io_ill_T_52) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_55 = eq(_io_ill_T_2, UInt<5>(0h1b)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_56 = mux(_io_ill_T_55, UInt<1>(0h0), _io_ill_T_54) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_57 = eq(_io_ill_T_2, UInt<5>(0h1c)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_58 = mux(_io_ill_T_57, UInt<1>(0h0), _io_ill_T_56) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_59 = eq(_io_ill_T_2, UInt<5>(0h1d)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_60 = mux(_io_ill_T_59, UInt<1>(0h0), _io_ill_T_58) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_61 = eq(_io_ill_T_2, UInt<5>(0h1e)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_62 = mux(_io_ill_T_61, UInt<1>(0h0), _io_ill_T_60) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _io_ill_T_63 = eq(_io_ill_T_2, UInt<5>(0h1f)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_ill_T_64 = mux(_io_ill_T_63, UInt<1>(0h0), _io_ill_T_62) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] connect io.ill, _io_ill_T_64 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RVC.scala 202:12] module IBuf : @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 21:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 21:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 21:7] output io : { flip imem : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<1>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<34>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, flip kill : UInt<1>, pc : UInt<34>, btb_resp : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<1>, bht : { history : UInt<8>, value : UInt<1>}}, inst : { flip ready : UInt<1>, valid : UInt<1>, bits : { xcpt0 : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, xcpt1 : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>, rvc : UInt<1>, inst : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, raw : UInt<32>}}[1]} @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 22:14] regreset nBufValid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 34:47] reg buf : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<1>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<34>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 35:16] reg ibufBTBResp : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<1>, bht : { history : UInt<8>, value : UInt<1>}}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 36:24] node pcWordBits = bits(io.imem.bits.pc, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] wire nReady : UInt<2> @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 40:27] connect nReady, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 40:27] node _nIC_T = add(io.imem.bits.btb.bridx, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 41:64] node _nIC_T_1 = mux(io.imem.bits.btb.taken, _nIC_T, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 41:16] node _nIC_T_2 = sub(_nIC_T_1, pcWordBits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 41:86] node nIC = tail(_nIC_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 41:86] node _nICReady_T = sub(nReady, nBufValid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 42:25] node nICReady = tail(_nICReady_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 42:25] node _nValid_T = mux(io.imem.valid, nIC, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 43:19] node _nValid_T_1 = add(_nValid_T, nBufValid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 43:45] node nValid = tail(_nValid_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 43:45] node _io_imem_ready_T = geq(nReady, nBufValid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 44:47] node _io_imem_ready_T_1 = and(io.inst[0].ready, _io_imem_ready_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 44:37] node _io_imem_ready_T_2 = geq(nICReady, nIC) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 44:73] node _io_imem_ready_T_3 = sub(nIC, nICReady) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 44:94] node _io_imem_ready_T_4 = tail(_io_imem_ready_T_3, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 44:94] node _io_imem_ready_T_5 = geq(UInt<1>(0h1), _io_imem_ready_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 44:87] node _io_imem_ready_T_6 = or(_io_imem_ready_T_2, _io_imem_ready_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 44:80] node _io_imem_ready_T_7 = and(_io_imem_ready_T_1, _io_imem_ready_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 44:60] connect io.imem.ready, _io_imem_ready_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 44:17] when io.inst[0].ready : @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 47:29] node _nBufValid_T = geq(nReady, nBufValid) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 219:33] node _nBufValid_T_1 = eq(nBufValid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 219:43] node _nBufValid_T_2 = or(_nBufValid_T, _nBufValid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 219:38] node _nBufValid_T_3 = sub(nBufValid, nReady) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 48:61] node _nBufValid_T_4 = tail(_nBufValid_T_3, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 48:61] node _nBufValid_T_5 = mux(_nBufValid_T_2, UInt<1>(0h0), _nBufValid_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 48:23] connect nBufValid, _nBufValid_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 48:17] node _T = geq(nReady, nBufValid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 54:37] node _T_1 = and(io.imem.valid, _T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 54:27] node _T_2 = lt(nICReady, nIC) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 54:62] node _T_3 = and(_T_1, _T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 54:50] node _T_4 = sub(nIC, nICReady) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 54:82] node _T_5 = tail(_T_4, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 54:82] node _T_6 = geq(UInt<1>(0h1), _T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 54:75] node _T_7 = and(_T_3, _T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 54:68] when _T_7 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 54:94] node _shamt_T = add(pcWordBits, nICReady) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 55:32] node shamt = tail(_shamt_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 55:32] node _nBufValid_T_6 = sub(nIC, nICReady) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 56:26] node _nBufValid_T_7 = tail(_nBufValid_T_6, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 56:26] connect nBufValid, _nBufValid_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 56:19] connect buf, io.imem.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 57:13] node _buf_data_data_T = shr(io.imem.bits.data, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 127:58] node _buf_data_data_T_1 = cat(_buf_data_data_T, _buf_data_data_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 127:24] node buf_data_data = cat(_buf_data_data_T_1, io.imem.bits.data) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 127:19] node _buf_data_T = shl(shamt, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 128:19] node _buf_data_T_1 = dshr(buf_data_data, _buf_data_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 128:10] node _buf_data_T_2 = bits(_buf_data_T_1, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 58:61] connect buf.data, _buf_data_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 58:18] node _buf_pc_T = not(UInt<34>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 59:37] node _buf_pc_T_1 = and(io.imem.bits.pc, _buf_pc_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 59:35] node _buf_pc_T_2 = shl(nICReady, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 59:80] node _buf_pc_T_3 = add(io.imem.bits.pc, _buf_pc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 59:68] node _buf_pc_T_4 = tail(_buf_pc_T_3, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 59:68] node _buf_pc_T_5 = and(_buf_pc_T_4, UInt<34>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 59:109] node _buf_pc_T_6 = or(_buf_pc_T_1, _buf_pc_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 59:49] connect buf.pc, _buf_pc_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 59:16] connect ibufBTBResp, io.imem.bits.btb @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 60:21] when io.kill : @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 63:20] connect nBufValid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 64:17] node _icShiftAmt_T = add(UInt<2>(0h2), nBufValid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 68:34] node _icShiftAmt_T_1 = tail(_icShiftAmt_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 68:34] node _icShiftAmt_T_2 = sub(_icShiftAmt_T_1, pcWordBits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 68:46] node _icShiftAmt_T_3 = tail(_icShiftAmt_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 68:46] node icShiftAmt = bits(_icShiftAmt_T_3, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 68:59] node _icData_T = bits(io.imem.bits.data, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 69:87] node _icData_T_1 = cat(_icData_T, _icData_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 69:57] node _icData_T_2 = cat(io.imem.bits.data, _icData_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 69:33] node _icData_data_T = shr(_icData_T_2, 48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 120:58] node _icData_data_T_1 = cat(_icData_data_T, _icData_data_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 120:24] node _icData_data_T_2 = cat(_icData_data_T_1, _icData_data_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 120:24] node icData_data = cat(_icData_data_T_2, _icData_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 120:19] node _icData_T_3 = shl(icShiftAmt, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 121:19] node _icData_T_4 = dshl(icData_data, _icData_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 121:10] node icData = bits(_icData_T_4, 95, 64) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _icMask_T = not(UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 71:17] node _icMask_T_1 = shl(nBufValid, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 71:65] node _icMask_T_2 = dshl(_icMask_T, _icMask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 71:51] node icMask = bits(_icMask_T_2, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 71:92] node _inst_T = and(icData, icMask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 72:21] node _inst_T_1 = not(icMask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 72:43] node _inst_T_2 = and(buf.data, _inst_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 72:41] node inst = or(_inst_T, _inst_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 72:30] node _valid_T = dshl(UInt<1>(0h1), nValid) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node _valid_T_1 = sub(_valid_T, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 74:33] node _valid_T_2 = tail(_valid_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 74:33] node valid = bits(_valid_T_2, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 74:39] node _bufMask_T = dshl(UInt<1>(0h1), nBufValid) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node _bufMask_T_1 = sub(_bufMask_T, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 75:37] node bufMask = tail(_bufMask_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 75:37] node _xcpt_T = bits(bufMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 76:61] node xcpt_0 = mux(_xcpt_T, buf.xcpt, io.imem.bits.xcpt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 76:53] node _xcpt_T_1 = bits(bufMask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 76:61] node xcpt_1 = mux(_xcpt_T_1, buf.xcpt, io.imem.bits.xcpt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 76:53] node buf_replay = mux(buf.replay, bufMask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 77:23] node _ic_replay_T = not(bufMask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 78:65] node _ic_replay_T_1 = and(valid, _ic_replay_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 78:63] node _ic_replay_T_2 = mux(io.imem.bits.replay, _ic_replay_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 78:35] node ic_replay = or(buf_replay, _ic_replay_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 78:30] node _T_8 = eq(io.imem.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 79:10] node _T_9 = eq(io.imem.bits.btb.taken, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 79:28] node _T_10 = or(_T_8, _T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 79:25] node _T_11 = geq(io.imem.bits.btb.bridx, pcWordBits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 79:78] node _T_12 = or(_T_10, _T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 79:52] node _T_13 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 79:9] node _T_14 = eq(_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 79:9] when _T_14 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 79:9] node _T_15 = eq(_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 79:9] when _T_15 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 79:9] printf(clock, UInt<1>(0h1), "Assertion failed\n at IBuf.scala:79 assert(!io.imem.valid || !io.imem.bits.btb.taken || io.imem.bits.btb.bridx >= pcWordBits)\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 79:9] assert(clock, _T_12, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 79:9] connect io.btb_resp, io.imem.bits.btb @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 81:15] node _io_pc_T = gt(nBufValid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 82:26] node _io_pc_T_1 = mux(_io_pc_T, buf.pc, io.imem.bits.pc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 82:15] connect io.pc, _io_pc_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 82:9] inst exp of RVCExpander @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 86:21] connect exp.clock, clock connect exp.reset, reset connect exp.io.in, inst @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 87:15] connect io.inst[0].bits.inst, exp.io.out @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 88:26] connect io.inst[0].bits.raw, inst @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 89:25] node _replay_T = dshr(ic_replay, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 92:29] node _replay_T_1 = bits(_replay_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 92:29] node _replay_T_2 = eq(exp.io.rvc, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 92:37] node _replay_T_3 = add(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 92:63] node _replay_T_4 = tail(_replay_T_3, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 92:63] node _replay_T_5 = dshr(ic_replay, _replay_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 92:61] node _replay_T_6 = bits(_replay_T_5, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 92:61] node _replay_T_7 = and(_replay_T_2, _replay_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 92:49] node replay = or(_replay_T_1, _replay_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 92:33] node _full_insn_T = add(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 93:44] node _full_insn_T_1 = tail(_full_insn_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 93:44] node _full_insn_T_2 = dshr(valid, _full_insn_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 93:42] node _full_insn_T_3 = bits(_full_insn_T_2, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 93:42] node _full_insn_T_4 = or(exp.io.rvc, _full_insn_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 93:34] node _full_insn_T_5 = dshr(buf_replay, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 93:63] node _full_insn_T_6 = bits(_full_insn_T_5, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 93:63] node full_insn = or(_full_insn_T_4, _full_insn_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 93:50] node _io_inst_0_valid_T = dshr(valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 94:32] node _io_inst_0_valid_T_1 = bits(_io_inst_0_valid_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 94:32] node _io_inst_0_valid_T_2 = and(_io_inst_0_valid_T_1, full_insn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 94:36] connect io.inst[0].valid, _io_inst_0_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 94:24] node _io_inst_0_bits_xcpt0_T = eq(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_inst_0_bits_xcpt0_T_1 = mux(_io_inst_0_bits_xcpt0_T, xcpt_1, xcpt_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] connect io.inst[0].bits.xcpt0, _io_inst_0_bits_xcpt0_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 95:29] node _io_inst_0_bits_xcpt1_T = add(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 96:59] node _io_inst_0_bits_xcpt1_T_1 = tail(_io_inst_0_bits_xcpt1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 96:59] node _io_inst_0_bits_xcpt1_T_2 = eq(_io_inst_0_bits_xcpt1_T_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _io_inst_0_bits_xcpt1_T_3 = mux(_io_inst_0_bits_xcpt1_T_2, xcpt_1, xcpt_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node io_inst_0_bits_xcpt1_hi = cat(_io_inst_0_bits_xcpt1_T_3.pf.inst, _io_inst_0_bits_xcpt1_T_3.gf.inst) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 96:65] node _io_inst_0_bits_xcpt1_T_4 = cat(io_inst_0_bits_xcpt1_hi, _io_inst_0_bits_xcpt1_T_3.ae.inst) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 96:65] node _io_inst_0_bits_xcpt1_T_5 = mux(exp.io.rvc, UInt<1>(0h0), _io_inst_0_bits_xcpt1_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 96:35] wire _io_inst_0_bits_xcpt1_WIRE : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 96:81] wire _io_inst_0_bits_xcpt1_WIRE_1 : UInt<3> @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 96:81] connect _io_inst_0_bits_xcpt1_WIRE_1, _io_inst_0_bits_xcpt1_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 96:81] node _io_inst_0_bits_xcpt1_T_6 = bits(_io_inst_0_bits_xcpt1_WIRE_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 96:81] connect _io_inst_0_bits_xcpt1_WIRE.ae.inst, _io_inst_0_bits_xcpt1_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 96:81] node _io_inst_0_bits_xcpt1_T_7 = bits(_io_inst_0_bits_xcpt1_WIRE_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 96:81] connect _io_inst_0_bits_xcpt1_WIRE.gf.inst, _io_inst_0_bits_xcpt1_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 96:81] node _io_inst_0_bits_xcpt1_T_8 = bits(_io_inst_0_bits_xcpt1_WIRE_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 96:81] connect _io_inst_0_bits_xcpt1_WIRE.pf.inst, _io_inst_0_bits_xcpt1_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 96:81] connect io.inst[0].bits.xcpt1, _io_inst_0_bits_xcpt1_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 96:29] connect io.inst[0].bits.replay, replay @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 97:30] connect io.inst[0].bits.rvc, exp.io.rvc @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 98:27] node _T_16 = dshr(bufMask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 100:21] node _T_17 = bits(_T_16, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 100:21] node _T_18 = and(_T_17, exp.io.rvc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 100:25] node _T_19 = add(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 100:52] node _T_20 = tail(_T_19, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 100:52] node _T_21 = dshr(bufMask, _T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 100:50] node _T_22 = bits(_T_21, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 100:50] node _T_23 = or(_T_18, _T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 100:40] when _T_23 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 100:59] connect io.btb_resp, ibufBTBResp @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 100:73] node _T_24 = or(UInt<1>(0h1), io.inst[0].ready) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 102:38] node _T_25 = and(full_insn, _T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 102:23] when _T_25 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 102:60] node _nReady_T = add(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 102:89] node _nReady_T_1 = tail(_nReady_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 102:89] node _nReady_T_2 = add(UInt<1>(0h0), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 102:96] node _nReady_T_3 = tail(_nReady_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 102:96] node _nReady_T_4 = mux(exp.io.rvc, _nReady_T_1, _nReady_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 102:75] connect nReady, _nReady_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 102:69] node _T_26 = add(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 104:36] node _T_27 = tail(_T_26, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 104:36] node _T_28 = add(UInt<1>(0h0), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 104:43] node _T_29 = tail(_T_28, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 104:43] node _T_30 = mux(exp.io.rvc, _T_27, _T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 104:22] node _T_31 = shr(inst, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 104:74] node _T_32 = shr(inst, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 104:89] node _T_33 = mux(exp.io.rvc, _T_31, _T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/IBuf.scala 104:53] module CSRFile : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 378:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 378:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 378:7] output io : { flip ungated_clock : Clock, flip interrupts : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt<1>, rw : { flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, decode : { flip inst : UInt<32>, fp_illegal : UInt<1>, vector_illegal : UInt<1>, fp_csr : UInt<1>, vector_csr : UInt<1>, rocc_illegal : UInt<1>, read_illegal : UInt<1>, write_illegal : UInt<1>, write_flush : UInt<1>, system_illegal : UInt<1>, virtual_access_illegal : UInt<1>, virtual_system_illegal : UInt<1>}[1], csr_stall : UInt<1>, rw_stall : UInt<1>, eret : UInt<1>, trap_return : UInt<1>, singleStep : UInt<1>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, evec : UInt<34>, flip exception : UInt<1>, flip retire : UInt<1>, flip cause : UInt<64>, flip pc : UInt<34>, flip tval : UInt<34>, flip htval : UInt<40>, flip mhtinst_read_pseudo : UInt<1>, flip gva : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, flip rocc_interrupt : UInt<1>, interrupt : UInt<1>, interrupt_cause : UInt<64>, bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<33>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[1], pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], counters : { eventSel : UInt<64>, flip inc : UInt<1>}[0], csrw_counter : UInt<32>, inhibit_cycle : UInt<1>, flip inst : UInt<32>[1], trace : { valid : UInt<1>, iaddr : UInt<34>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<34>}[1], mcontext : UInt<0>, scontext : UInt<0>, fiom : UInt<1>, customCSRs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4], roccCSRs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 385:14] connect io.rw_stall, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 390:15] wire _reset_mstatus_WIRE : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.uie, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.sie, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.hie, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.mie, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.upie, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.spie, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.ube, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.mpie, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.spp, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.vs, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.mpp, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.fs, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.xs, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.mprv, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.sum, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.mxr, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.tvm, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.tw, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.tsr, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.zero1, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.sd_rv32, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.uxl, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.sxl, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.sbe, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.mbe, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.gva, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.mpv, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.zero2, UInt<23>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.sd, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.v, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.prv, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.dv, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.dprv, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.isa, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.wfi, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.cease, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] connect _reset_mstatus_WIRE.debug, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:47] wire reset_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:34] connect reset_mstatus, _reset_mstatus_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 392:34] connect reset_mstatus.mpp, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 393:21] connect reset_mstatus.prv, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 394:21] connect reset_mstatus.xs, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 395:20] regreset reg_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock, reset, reset_mstatus @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 396:28] wire new_prv : UInt @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 398:28] connect new_prv, reg_mstatus.prv @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 398:28] connect reg_mstatus.prv, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 399:19] wire _reset_dcsr_WIRE : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 401:44] connect _reset_dcsr_WIRE.prv, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 401:44] connect _reset_dcsr_WIRE.step, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 401:44] connect _reset_dcsr_WIRE.zero1, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 401:44] connect _reset_dcsr_WIRE.v, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 401:44] connect _reset_dcsr_WIRE.cause, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 401:44] connect _reset_dcsr_WIRE.stoptime, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 401:44] connect _reset_dcsr_WIRE.stopcycle, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 401:44] connect _reset_dcsr_WIRE.zero2, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 401:44] connect _reset_dcsr_WIRE.ebreaku, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 401:44] connect _reset_dcsr_WIRE.ebreaks, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 401:44] connect _reset_dcsr_WIRE.ebreakh, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 401:44] connect _reset_dcsr_WIRE.ebreakm, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 401:44] connect _reset_dcsr_WIRE.zero3, UInt<12>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 401:44] connect _reset_dcsr_WIRE.zero4, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 401:44] connect _reset_dcsr_WIRE.xdebugver, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 401:44] wire reset_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 401:31] connect reset_dcsr, _reset_dcsr_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 401:31] connect reset_dcsr.xdebugver, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 402:24] connect reset_dcsr.prv, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 403:18] regreset reg_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>}, clock, reset, reset_dcsr @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 404:25] wire sup : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 407:19] connect sup.usip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 408:14] connect sup.ssip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 409:14] connect sup.vssip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 410:15] connect sup.msip, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 411:14] connect sup.utip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 412:14] connect sup.stip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 413:14] connect sup.vstip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 414:15] connect sup.mtip, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 415:14] connect sup.ueip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 416:14] connect sup.seip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 417:14] connect sup.vseip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 418:15] connect sup.meip, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 419:14] connect sup.sgeip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 420:15] connect sup.rocc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 421:14] connect sup.debug, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 422:15] connect sup.zero1, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 423:15] wire del : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 427:26] connect del, sup @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 427:26] connect del.msip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 428:14] connect del.mtip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 429:14] connect del.meip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 430:14] node lo_lo_lo = cat(sup.ssip, sup.usip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:10] node lo_lo_hi = cat(sup.msip, sup.vssip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:10] node lo_lo = cat(lo_lo_hi, lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:10] node lo_hi_lo = cat(sup.stip, sup.utip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:10] node lo_hi_hi = cat(sup.mtip, sup.vstip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:10] node lo_hi = cat(lo_hi_hi, lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:10] node lo = cat(lo_hi, lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:10] node hi_lo_lo = cat(sup.seip, sup.ueip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:10] node hi_lo_hi = cat(sup.meip, sup.vseip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:10] node hi_lo = cat(hi_lo_hi, hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:10] node hi_hi_lo = cat(sup.rocc, sup.sgeip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:10] node hi_hi_hi_hi = cat(UInt<0>(0h0), sup.zero1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:10] node hi_hi_hi = cat(hi_hi_hi_hi, sup.debug) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:10] node hi_hi = cat(hi_hi_hi, hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:10] node hi = cat(hi_hi, hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:10] node _T = cat(hi, lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:10] node supported_interrupts = or(_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:17] node lo_lo_lo_1 = cat(del.ssip, del.usip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:50] node lo_lo_hi_1 = cat(del.msip, del.vssip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:50] node lo_lo_1 = cat(lo_lo_hi_1, lo_lo_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:50] node lo_hi_lo_1 = cat(del.stip, del.utip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:50] node lo_hi_hi_1 = cat(del.mtip, del.vstip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:50] node lo_hi_1 = cat(lo_hi_hi_1, lo_hi_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:50] node lo_1 = cat(lo_hi_1, lo_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:50] node hi_lo_lo_1 = cat(del.seip, del.ueip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:50] node hi_lo_hi_1 = cat(del.meip, del.vseip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:50] node hi_lo_1 = cat(hi_lo_hi_1, hi_lo_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:50] node hi_hi_lo_1 = cat(del.rocc, del.sgeip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:50] node hi_hi_hi_hi_1 = cat(UInt<0>(0h0), del.zero1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:50] node hi_hi_hi_1 = cat(hi_hi_hi_hi_1, del.debug) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:50] node hi_hi_1 = cat(hi_hi_hi_1, hi_hi_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:50] node hi_1 = cat(hi_hi_1, hi_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:50] node delegable_interrupts = cat(hi_1, lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 432:50] wire _always_WIRE : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:42] connect _always_WIRE.usip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:42] connect _always_WIRE.ssip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:42] connect _always_WIRE.vssip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:42] connect _always_WIRE.msip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:42] connect _always_WIRE.utip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:42] connect _always_WIRE.stip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:42] connect _always_WIRE.vstip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:42] connect _always_WIRE.mtip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:42] connect _always_WIRE.ueip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:42] connect _always_WIRE.seip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:42] connect _always_WIRE.vseip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:42] connect _always_WIRE.meip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:42] connect _always_WIRE.sgeip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:42] connect _always_WIRE.rocc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:42] connect _always_WIRE.debug, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:42] connect _always_WIRE.zero1, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:42] wire always : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:29] connect always, _always_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 472:29] connect always.vssip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 473:18] connect always.vstip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 474:18] connect always.vseip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 475:18] wire deleg : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 477:28] connect deleg, always @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 477:28] node lo_lo_lo_2 = cat(deleg.ssip, deleg.usip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:12] node lo_lo_hi_2 = cat(deleg.msip, deleg.vssip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:12] node lo_lo_2 = cat(lo_lo_hi_2, lo_lo_lo_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:12] node lo_hi_lo_2 = cat(deleg.stip, deleg.utip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:12] node lo_hi_hi_2 = cat(deleg.mtip, deleg.vstip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:12] node lo_hi_2 = cat(lo_hi_hi_2, lo_hi_lo_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:12] node lo_2 = cat(lo_hi_2, lo_lo_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:12] node hi_lo_lo_2 = cat(deleg.seip, deleg.ueip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:12] node hi_lo_hi_2 = cat(deleg.meip, deleg.vseip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:12] node hi_lo_2 = cat(hi_lo_hi_2, hi_lo_lo_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:12] node hi_hi_lo_2 = cat(deleg.rocc, deleg.sgeip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:12] node hi_hi_hi_hi_2 = cat(UInt<0>(0h0), deleg.zero1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:12] node hi_hi_hi_2 = cat(hi_hi_hi_hi_2, deleg.debug) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:12] node hi_hi_2 = cat(hi_hi_hi_2, hi_hi_lo_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:12] node hi_2 = cat(hi_hi_2, hi_lo_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:12] node hs_delegable_interrupts = cat(hi_2, lo_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:12] node lo_lo_lo_3 = cat(always.ssip, always.usip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:27] node lo_lo_hi_3 = cat(always.msip, always.vssip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:27] node lo_lo_3 = cat(lo_lo_hi_3, lo_lo_lo_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:27] node lo_hi_lo_3 = cat(always.stip, always.utip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:27] node lo_hi_hi_3 = cat(always.mtip, always.vstip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:27] node lo_hi_3 = cat(lo_hi_hi_3, lo_hi_lo_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:27] node lo_3 = cat(lo_hi_3, lo_lo_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:27] node hi_lo_lo_3 = cat(always.seip, always.ueip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:27] node hi_lo_hi_3 = cat(always.meip, always.vseip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:27] node hi_lo_3 = cat(hi_lo_hi_3, hi_lo_lo_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:27] node hi_hi_lo_3 = cat(always.rocc, always.sgeip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:27] node hi_hi_hi_hi_3 = cat(UInt<0>(0h0), always.zero1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:27] node hi_hi_hi_3 = cat(hi_hi_hi_hi_3, always.debug) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:27] node hi_hi_3 = cat(hi_hi_hi_3, hi_hi_lo_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:27] node hi_3 = cat(hi_hi_3, hi_lo_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:27] node mideleg_always_hs = cat(hi_3, lo_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 480:27] regreset reg_debug : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 483:26] reg reg_dpc : UInt<34>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 484:20] reg reg_dscratch0 : UInt<64>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 485:26] reg reg_singleStepped : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 487:30] reg reg_tselect : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 492:24] reg reg_bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<33>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[2], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 493:19] reg reg_pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>}[8], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 494:20] reg reg_mie : UInt<64>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 496:20] reg reg_mideleg : UInt<64>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 498:18] node _T_1 = and(reg_mideleg, delegable_interrupts) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 499:38] node _T_2 = or(_T_1, mideleg_always_hs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 499:61] node read_mideleg = mux(UInt<1>(0h0), _T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 499:14] reg reg_medeleg : UInt<64>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 502:18] node _T_3 = and(reg_medeleg, UInt<16>(0hb15d)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 503:38] node read_medeleg = mux(UInt<1>(0h0), _T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 503:14] reg reg_mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 505:20] reg reg_mepc : UInt<34>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 506:21] regreset reg_mcause : UInt<64>, clock, reset, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 507:27] reg reg_mtval : UInt<34>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 508:22] reg reg_mtval2 : UInt<40>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 509:23] reg reg_mscratch : UInt<64>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 510:25] regreset reg_mtvec : UInt<32>, clock, reset, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 513:31] wire _reset_mnstatus_WIRE : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 517:48] connect _reset_mnstatus_WIRE.zero1, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 517:48] connect _reset_mnstatus_WIRE.mie, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 517:48] connect _reset_mnstatus_WIRE.zero2, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 517:48] connect _reset_mnstatus_WIRE.mpv, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 517:48] connect _reset_mnstatus_WIRE.zero3, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 517:48] connect _reset_mnstatus_WIRE.mpp, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 517:48] wire reset_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 517:35] connect reset_mnstatus, _reset_mnstatus_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 517:35] connect reset_mnstatus.mpp, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 518:22] reg reg_mnscratch : UInt<64>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 519:26] reg reg_mnepc : UInt<34>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 520:22] regreset reg_mncause : UInt<64>, clock, reset, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 521:28] regreset reg_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>}, clock, reset, reset_mnstatus @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 522:29] regreset reg_rnmie : UInt<1>, clock, reset, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 523:26] wire _reg_menvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 526:41] connect _reg_menvcfg_WIRE.fiom, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 526:41] connect _reg_menvcfg_WIRE.zero3, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 526:41] connect _reg_menvcfg_WIRE.cbie, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 526:41] connect _reg_menvcfg_WIRE.cbcfe, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 526:41] connect _reg_menvcfg_WIRE.cbze, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 526:41] connect _reg_menvcfg_WIRE.zero54, UInt<54>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 526:41] connect _reg_menvcfg_WIRE.pbmte, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 526:41] connect _reg_menvcfg_WIRE.stce, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 526:41] regreset reg_menvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_menvcfg_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 526:28] wire _reg_senvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 527:41] connect _reg_senvcfg_WIRE.fiom, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 527:41] connect _reg_senvcfg_WIRE.zero3, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 527:41] connect _reg_senvcfg_WIRE.cbie, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 527:41] connect _reg_senvcfg_WIRE.cbcfe, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 527:41] connect _reg_senvcfg_WIRE.cbze, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 527:41] connect _reg_senvcfg_WIRE.zero54, UInt<54>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 527:41] connect _reg_senvcfg_WIRE.pbmte, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 527:41] connect _reg_senvcfg_WIRE.stce, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 527:41] regreset reg_senvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_senvcfg_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 527:28] wire _reg_henvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 528:41] connect _reg_henvcfg_WIRE.fiom, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 528:41] connect _reg_henvcfg_WIRE.zero3, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 528:41] connect _reg_henvcfg_WIRE.cbie, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 528:41] connect _reg_henvcfg_WIRE.cbcfe, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 528:41] connect _reg_henvcfg_WIRE.cbze, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 528:41] connect _reg_henvcfg_WIRE.zero54, UInt<54>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 528:41] connect _reg_henvcfg_WIRE.pbmte, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 528:41] connect _reg_henvcfg_WIRE.stce, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 528:41] regreset reg_henvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_henvcfg_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 528:28] reg reg_mcounteren : UInt<32>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 532:18] node _T_4 = and(reg_mcounteren, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 533:32] node read_mcounteren = mux(UInt<1>(0h0), _T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 533:14] reg reg_scounteren : UInt<32>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 536:18] node _T_5 = and(reg_scounteren, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 537:38] node read_scounteren = mux(UInt<1>(0h0), _T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 537:14] reg reg_hideleg : UInt<64>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 541:18] node _T_6 = and(reg_hideleg, hs_delegable_interrupts) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 542:38] node read_hideleg = mux(UInt<1>(0h0), _T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 542:14] reg reg_hedeleg : UInt<64>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 545:18] node _T_7 = and(reg_hedeleg, UInt<16>(0hb1ff)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 546:38] node read_hedeleg = mux(UInt<1>(0h0), _T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 546:14] reg reg_hcounteren : UInt<32>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 550:18] node _T_8 = and(reg_hcounteren, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 551:38] node read_hcounteren = mux(UInt<1>(0h0), _T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 551:14] wire _reg_hstatus_WIRE : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 553:41] connect _reg_hstatus_WIRE.zero1, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 553:41] connect _reg_hstatus_WIRE.vsbe, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 553:41] connect _reg_hstatus_WIRE.gva, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 553:41] connect _reg_hstatus_WIRE.spv, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 553:41] connect _reg_hstatus_WIRE.spvp, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 553:41] connect _reg_hstatus_WIRE.hu, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 553:41] connect _reg_hstatus_WIRE.zero2, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 553:41] connect _reg_hstatus_WIRE.vgein, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 553:41] connect _reg_hstatus_WIRE.zero3, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 553:41] connect _reg_hstatus_WIRE.vtvm, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 553:41] connect _reg_hstatus_WIRE.vtw, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 553:41] connect _reg_hstatus_WIRE.vtsr, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 553:41] connect _reg_hstatus_WIRE.zero5, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 553:41] connect _reg_hstatus_WIRE.vsxl, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 553:41] connect _reg_hstatus_WIRE.zero6, UInt<30>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 553:41] regreset reg_hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, clock, reset, _reg_hstatus_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 553:28] reg reg_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 554:22] reg reg_htval : UInt<40>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 555:22] node read_hvip_lo_lo_lo = cat(reg_mip.ssip, reg_mip.usip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 556:27] node read_hvip_lo_lo_hi = cat(reg_mip.msip, reg_mip.vssip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 556:27] node read_hvip_lo_lo = cat(read_hvip_lo_lo_hi, read_hvip_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 556:27] node read_hvip_lo_hi_lo = cat(reg_mip.stip, reg_mip.utip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 556:27] node read_hvip_lo_hi_hi = cat(reg_mip.mtip, reg_mip.vstip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 556:27] node read_hvip_lo_hi = cat(read_hvip_lo_hi_hi, read_hvip_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 556:27] node read_hvip_lo = cat(read_hvip_lo_hi, read_hvip_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 556:27] node read_hvip_hi_lo_lo = cat(reg_mip.seip, reg_mip.ueip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 556:27] node read_hvip_hi_lo_hi = cat(reg_mip.meip, reg_mip.vseip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 556:27] node read_hvip_hi_lo = cat(read_hvip_hi_lo_hi, read_hvip_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 556:27] node read_hvip_hi_hi_lo = cat(reg_mip.rocc, reg_mip.sgeip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 556:27] node read_hvip_hi_hi_hi_hi = cat(UInt<0>(0h0), reg_mip.zero1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 556:27] node read_hvip_hi_hi_hi = cat(read_hvip_hi_hi_hi_hi, reg_mip.debug) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 556:27] node read_hvip_hi_hi = cat(read_hvip_hi_hi_hi, read_hvip_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 556:27] node read_hvip_hi = cat(read_hvip_hi_hi, read_hvip_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 556:27] node _read_hvip_T = cat(read_hvip_hi, read_hvip_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 556:27] node read_hvip = and(_read_hvip_T, hs_delegable_interrupts) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 556:34] node read_hie = and(reg_mie, hs_delegable_interrupts) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 557:26] reg reg_vstvec : UInt<34>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 560:18] node _T_9 = bits(reg_vstvec, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1668:41] node _T_10 = mux(_T_9, UInt<8>(0hfe), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1668:39] node _T_11 = and(reg_vstvec, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 175:46] node _T_12 = or(_T_10, _T_11) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 175:41] node _T_13 = not(_T_12) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 175:37] node _T_14 = and(reg_vstvec, _T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 175:35] node _T_15 = bits(_T_14, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:38] node _T_16 = mux(_T_15, UInt<30>(0h3fffffff), UInt<30>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:20] node read_vstvec = cat(_T_16, _T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:15] reg reg_vsstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 563:25] reg reg_vsscratch : UInt<64>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 564:26] reg reg_vsepc : UInt<34>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 565:22] reg reg_vscause : UInt<64>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 566:24] reg reg_vstval : UInt<34>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 567:23] reg reg_vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 568:22] reg reg_sepc : UInt<34>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 570:21] reg reg_scause : UInt<64>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 571:23] reg reg_stval : UInt<34>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 572:22] reg reg_sscratch : UInt<64>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 573:25] reg reg_stvec : UInt<33>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 574:22] reg reg_satp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 575:21] regreset reg_wfi : UInt<1>, io.ungated_clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 576:54] reg reg_fflags : UInt<5>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 578:23] reg reg_frm : UInt<3>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 579:20] reg reg_mtinst_read_pseudo : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 585:35] reg reg_htinst_read_pseudo : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 586:35] node hi_4 = cat(reg_mtinst_read_pseudo, reg_mtinst_read_pseudo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 589:103] node read_mtinst = cat(hi_4, UInt<12>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 589:103] node hi_5 = cat(reg_htinst_read_pseudo, reg_htinst_read_pseudo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 589:103] node read_htinst = cat(hi_5, UInt<12>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 589:103] regreset reg_mcountinhibit : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 591:34] node _io_inhibit_cycle_T = bits(reg_mcountinhibit, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 592:40] connect io.inhibit_cycle, _io_inhibit_cycle_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 592:20] node x3 = bits(reg_mcountinhibit, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 593:75] regreset small : UInt<6>, clock, reset, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 45:41] node nextSmall = add(small, io.retire) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 46:33] node _T_17 = eq(x3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 47:9] when _T_17 : @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 47:19] connect small, nextSmall @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 47:27] regreset large : UInt<58>, clock, reset, UInt<58>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 50:31] node _large_T = bits(nextSmall, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 51:20] node _large_T_1 = eq(x3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 51:36] node _large_T_2 = and(_large_T, _large_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 51:33] when _large_T_2 : @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 51:46] node _large_r_T = add(large, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 51:55] node _large_r_T_1 = tail(_large_r_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 51:55] connect large, _large_r_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 51:50] node value = cat(large, small) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 55:30] node x10 = eq(io.csr_stall, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 595:56] node x11 = bits(reg_mcountinhibit, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 595:98] regreset small_1 : UInt<6>, io.ungated_clock, reset, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 45:41] node nextSmall_1 = add(small_1, x10) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 46:33] node _T_18 = eq(x11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 47:9] when _T_18 : @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 47:19] connect small_1, nextSmall_1 @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 47:27] regreset large_1 : UInt<58>, io.ungated_clock, reset, UInt<58>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 50:31] node _large_T_3 = bits(nextSmall_1, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 51:20] node _large_T_4 = eq(x11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 51:36] node _large_T_5 = and(_large_T_3, _large_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 51:33] when _large_T_5 : @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 51:46] node _large_r_T_2 = add(large_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 51:55] node _large_r_T_3 = tail(_large_r_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 51:55] connect large_1, _large_r_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 51:50] node value_1 = cat(large_1, small_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 55:30] wire mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 601:24] connect mip, reg_mip @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 601:24] connect mip.mtip, io.interrupts.mtip @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 603:12] connect mip.msip, io.interrupts.msip @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 604:12] connect mip.meip, io.interrupts.meip @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 605:12] connect mip.rocc, io.rocc_interrupt @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 610:12] node read_mip_lo_lo_lo = cat(mip.ssip, mip.usip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 611:22] node read_mip_lo_lo_hi = cat(mip.msip, mip.vssip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 611:22] node read_mip_lo_lo = cat(read_mip_lo_lo_hi, read_mip_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 611:22] node read_mip_lo_hi_lo = cat(mip.stip, mip.utip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 611:22] node read_mip_lo_hi_hi = cat(mip.mtip, mip.vstip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 611:22] node read_mip_lo_hi = cat(read_mip_lo_hi_hi, read_mip_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 611:22] node read_mip_lo = cat(read_mip_lo_hi, read_mip_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 611:22] node read_mip_hi_lo_lo = cat(mip.seip, mip.ueip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 611:22] node read_mip_hi_lo_hi = cat(mip.meip, mip.vseip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 611:22] node read_mip_hi_lo = cat(read_mip_hi_lo_hi, read_mip_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 611:22] node read_mip_hi_hi_lo = cat(mip.rocc, mip.sgeip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 611:22] node read_mip_hi_hi_hi_hi = cat(UInt<0>(0h0), mip.zero1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 611:22] node read_mip_hi_hi_hi = cat(read_mip_hi_hi_hi_hi, mip.debug) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 611:22] node read_mip_hi_hi = cat(read_mip_hi_hi_hi, read_mip_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 611:22] node read_mip_hi = cat(read_mip_hi_hi, read_mip_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 611:22] node _read_mip_T = cat(read_mip_hi, read_mip_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 611:22] node read_mip = and(_read_mip_T, supported_interrupts) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 611:29] node read_hip = and(read_mip, hs_delegable_interrupts) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 612:27] node _pending_interrupts_T = and(read_mip, reg_mie) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 615:56] node pending_interrupts = or(UInt<1>(0h0), _pending_interrupts_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 615:44] node d_interrupts = shl(io.interrupts.debug, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 616:42] node _m_interrupts_T = leq(reg_mstatus.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 621:51] node _m_interrupts_T_1 = or(_m_interrupts_T, reg_mstatus.mie) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 621:62] node _m_interrupts_T_2 = and(reg_rnmie, _m_interrupts_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 621:31] node _m_interrupts_T_3 = not(pending_interrupts) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 621:85] node _m_interrupts_T_4 = or(_m_interrupts_T_3, read_mideleg) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 621:105] node _m_interrupts_T_5 = not(_m_interrupts_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 621:83] node m_interrupts = mux(_m_interrupts_T_2, _m_interrupts_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 621:25] node _s_interrupts_T = lt(reg_mstatus.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 622:68] node _s_interrupts_T_1 = or(reg_mstatus.v, _s_interrupts_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 622:49] node _s_interrupts_T_2 = eq(reg_mstatus.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 622:98] node _s_interrupts_T_3 = and(_s_interrupts_T_2, reg_mstatus.sie) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 622:110] node _s_interrupts_T_4 = or(_s_interrupts_T_1, _s_interrupts_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 622:78] node _s_interrupts_T_5 = and(reg_rnmie, _s_interrupts_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 622:31] node _s_interrupts_T_6 = and(pending_interrupts, read_mideleg) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 622:151] node _s_interrupts_T_7 = not(read_hideleg) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 622:168] node _s_interrupts_T_8 = and(_s_interrupts_T_6, _s_interrupts_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 622:166] node s_interrupts = mux(_s_interrupts_T_5, _s_interrupts_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 622:25] node _vs_interrupts_T = lt(reg_mstatus.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 623:70] node _vs_interrupts_T_1 = eq(reg_mstatus.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 623:99] node _vs_interrupts_T_2 = and(_vs_interrupts_T_1, reg_vsstatus.sie) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 623:111] node _vs_interrupts_T_3 = or(_vs_interrupts_T, _vs_interrupts_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 623:80] node _vs_interrupts_T_4 = and(reg_mstatus.v, _vs_interrupts_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 623:50] node _vs_interrupts_T_5 = and(reg_rnmie, _vs_interrupts_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 623:32] node _vs_interrupts_T_6 = and(pending_interrupts, read_hideleg) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 623:153] node vs_interrupts = mux(_vs_interrupts_T_5, _vs_interrupts_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 623:26] node _any_T = bits(d_interrupts, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_1 = bits(d_interrupts, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_2 = bits(d_interrupts, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_3 = bits(d_interrupts, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_4 = bits(d_interrupts, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_5 = bits(d_interrupts, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_6 = bits(d_interrupts, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_7 = bits(d_interrupts, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_8 = bits(d_interrupts, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_9 = bits(d_interrupts, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_10 = bits(d_interrupts, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_11 = bits(d_interrupts, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_12 = bits(d_interrupts, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_13 = bits(d_interrupts, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_14 = bits(d_interrupts, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_15 = bits(m_interrupts, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_16 = bits(m_interrupts, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_17 = bits(m_interrupts, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_18 = bits(m_interrupts, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_19 = bits(m_interrupts, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_20 = bits(m_interrupts, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_21 = bits(m_interrupts, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_22 = bits(m_interrupts, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_23 = bits(m_interrupts, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_24 = bits(m_interrupts, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_25 = bits(m_interrupts, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_26 = bits(m_interrupts, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_27 = bits(m_interrupts, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_28 = bits(m_interrupts, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_29 = bits(m_interrupts, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_30 = bits(m_interrupts, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_31 = bits(s_interrupts, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_32 = bits(s_interrupts, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_33 = bits(s_interrupts, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_34 = bits(s_interrupts, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_35 = bits(s_interrupts, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_36 = bits(s_interrupts, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_37 = bits(s_interrupts, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_38 = bits(s_interrupts, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_39 = bits(s_interrupts, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_40 = bits(s_interrupts, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_41 = bits(s_interrupts, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_42 = bits(s_interrupts, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_43 = bits(s_interrupts, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_44 = bits(s_interrupts, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_45 = bits(s_interrupts, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_46 = bits(s_interrupts, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_47 = bits(vs_interrupts, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_48 = bits(vs_interrupts, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_49 = bits(vs_interrupts, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_50 = bits(vs_interrupts, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_51 = bits(vs_interrupts, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_52 = bits(vs_interrupts, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_53 = bits(vs_interrupts, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_54 = bits(vs_interrupts, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_55 = bits(vs_interrupts, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_56 = bits(vs_interrupts, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_57 = bits(vs_interrupts, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_58 = bits(vs_interrupts, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_59 = bits(vs_interrupts, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_60 = bits(vs_interrupts, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_61 = bits(vs_interrupts, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_62 = bits(vs_interrupts, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:76] node _any_T_63 = or(_any_T, _any_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_64 = or(_any_T_63, _any_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_65 = or(_any_T_64, _any_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_66 = or(_any_T_65, _any_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_67 = or(_any_T_66, _any_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_68 = or(_any_T_67, _any_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_69 = or(_any_T_68, _any_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_70 = or(_any_T_69, _any_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_71 = or(_any_T_70, _any_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_72 = or(_any_T_71, _any_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_73 = or(_any_T_72, _any_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_74 = or(_any_T_73, _any_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_75 = or(_any_T_74, _any_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_76 = or(_any_T_75, _any_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_77 = or(_any_T_76, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_78 = or(_any_T_77, _any_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_79 = or(_any_T_78, _any_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_80 = or(_any_T_79, _any_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_81 = or(_any_T_80, _any_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_82 = or(_any_T_81, _any_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_83 = or(_any_T_82, _any_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_84 = or(_any_T_83, _any_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_85 = or(_any_T_84, _any_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_86 = or(_any_T_85, _any_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_87 = or(_any_T_86, _any_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_88 = or(_any_T_87, _any_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_89 = or(_any_T_88, _any_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_90 = or(_any_T_89, _any_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_91 = or(_any_T_90, _any_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_92 = or(_any_T_91, _any_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_93 = or(_any_T_92, _any_T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_94 = or(_any_T_93, _any_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_95 = or(_any_T_94, _any_T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_96 = or(_any_T_95, _any_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_97 = or(_any_T_96, _any_T_34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_98 = or(_any_T_97, _any_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_99 = or(_any_T_98, _any_T_36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_100 = or(_any_T_99, _any_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_101 = or(_any_T_100, _any_T_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_102 = or(_any_T_101, _any_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_103 = or(_any_T_102, _any_T_40) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_104 = or(_any_T_103, _any_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_105 = or(_any_T_104, _any_T_42) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_106 = or(_any_T_105, _any_T_43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_107 = or(_any_T_106, _any_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_108 = or(_any_T_107, _any_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_109 = or(_any_T_108, _any_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_110 = or(_any_T_109, _any_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_111 = or(_any_T_110, _any_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_112 = or(_any_T_111, _any_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_113 = or(_any_T_112, _any_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_114 = or(_any_T_113, _any_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_115 = or(_any_T_114, _any_T_52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_116 = or(_any_T_115, _any_T_53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_117 = or(_any_T_116, _any_T_54) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_118 = or(_any_T_117, _any_T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_119 = or(_any_T_118, _any_T_56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_120 = or(_any_T_119, _any_T_57) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_121 = or(_any_T_120, _any_T_58) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_122 = or(_any_T_121, _any_T_59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_123 = or(_any_T_122, _any_T_60) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _any_T_124 = or(_any_T_123, _any_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node anyInterrupt = or(_any_T_124, _any_T_62) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1639:90] node _which_T = bits(d_interrupts, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_1 = bits(d_interrupts, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_2 = bits(d_interrupts, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_3 = bits(d_interrupts, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_4 = bits(d_interrupts, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_5 = bits(d_interrupts, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_6 = bits(d_interrupts, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_7 = bits(d_interrupts, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_8 = bits(d_interrupts, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_9 = bits(d_interrupts, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_10 = bits(d_interrupts, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_11 = bits(d_interrupts, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_12 = bits(d_interrupts, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_13 = bits(d_interrupts, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_14 = bits(d_interrupts, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_15 = bits(m_interrupts, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_16 = bits(m_interrupts, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_17 = bits(m_interrupts, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_18 = bits(m_interrupts, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_19 = bits(m_interrupts, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_20 = bits(m_interrupts, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_21 = bits(m_interrupts, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_22 = bits(m_interrupts, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_23 = bits(m_interrupts, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_24 = bits(m_interrupts, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_25 = bits(m_interrupts, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_26 = bits(m_interrupts, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_27 = bits(m_interrupts, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_28 = bits(m_interrupts, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_29 = bits(m_interrupts, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_30 = bits(m_interrupts, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_31 = bits(s_interrupts, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_32 = bits(s_interrupts, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_33 = bits(s_interrupts, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_34 = bits(s_interrupts, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_35 = bits(s_interrupts, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_36 = bits(s_interrupts, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_37 = bits(s_interrupts, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_38 = bits(s_interrupts, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_39 = bits(s_interrupts, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_40 = bits(s_interrupts, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_41 = bits(s_interrupts, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_42 = bits(s_interrupts, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_43 = bits(s_interrupts, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_44 = bits(s_interrupts, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_45 = bits(s_interrupts, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_46 = bits(s_interrupts, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_47 = bits(vs_interrupts, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_48 = bits(vs_interrupts, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_49 = bits(vs_interrupts, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_50 = bits(vs_interrupts, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_51 = bits(vs_interrupts, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_52 = bits(vs_interrupts, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_53 = bits(vs_interrupts, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_54 = bits(vs_interrupts, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_55 = bits(vs_interrupts, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_56 = bits(vs_interrupts, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_57 = bits(vs_interrupts, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_58 = bits(vs_interrupts, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_59 = bits(vs_interrupts, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_60 = bits(vs_interrupts, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_61 = bits(vs_interrupts, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_62 = bits(vs_interrupts, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1640:91] node _which_T_63 = mux(_which_T_61, UInt<1>(0h0), UInt<3>(0h4)) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_64 = mux(_which_T_60, UInt<4>(0h8), _which_T_63) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_65 = mux(_which_T_59, UInt<3>(0h6), _which_T_64) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_66 = mux(_which_T_58, UInt<2>(0h2), _which_T_65) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_67 = mux(_which_T_57, UInt<4>(0ha), _which_T_66) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_68 = mux(_which_T_56, UInt<3>(0h5), _which_T_67) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_69 = mux(_which_T_55, UInt<1>(0h1), _which_T_68) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_70 = mux(_which_T_54, UInt<4>(0h9), _which_T_69) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_71 = mux(_which_T_53, UInt<3>(0h7), _which_T_70) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_72 = mux(_which_T_52, UInt<2>(0h3), _which_T_71) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_73 = mux(_which_T_51, UInt<4>(0hb), _which_T_72) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_74 = mux(_which_T_50, UInt<4>(0hc), _which_T_73) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_75 = mux(_which_T_49, UInt<4>(0hd), _which_T_74) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_76 = mux(_which_T_48, UInt<4>(0he), _which_T_75) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_77 = mux(_which_T_47, UInt<4>(0hf), _which_T_76) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_78 = mux(_which_T_46, UInt<3>(0h4), _which_T_77) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_79 = mux(_which_T_45, UInt<1>(0h0), _which_T_78) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_80 = mux(_which_T_44, UInt<4>(0h8), _which_T_79) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_81 = mux(_which_T_43, UInt<3>(0h6), _which_T_80) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_82 = mux(_which_T_42, UInt<2>(0h2), _which_T_81) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_83 = mux(_which_T_41, UInt<4>(0ha), _which_T_82) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_84 = mux(_which_T_40, UInt<3>(0h5), _which_T_83) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_85 = mux(_which_T_39, UInt<1>(0h1), _which_T_84) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_86 = mux(_which_T_38, UInt<4>(0h9), _which_T_85) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_87 = mux(_which_T_37, UInt<3>(0h7), _which_T_86) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_88 = mux(_which_T_36, UInt<2>(0h3), _which_T_87) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_89 = mux(_which_T_35, UInt<4>(0hb), _which_T_88) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_90 = mux(_which_T_34, UInt<4>(0hc), _which_T_89) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_91 = mux(_which_T_33, UInt<4>(0hd), _which_T_90) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_92 = mux(_which_T_32, UInt<4>(0he), _which_T_91) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_93 = mux(_which_T_31, UInt<4>(0hf), _which_T_92) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_94 = mux(_which_T_30, UInt<3>(0h4), _which_T_93) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_95 = mux(_which_T_29, UInt<1>(0h0), _which_T_94) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_96 = mux(_which_T_28, UInt<4>(0h8), _which_T_95) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_97 = mux(_which_T_27, UInt<3>(0h6), _which_T_96) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_98 = mux(_which_T_26, UInt<2>(0h2), _which_T_97) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_99 = mux(_which_T_25, UInt<4>(0ha), _which_T_98) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_100 = mux(_which_T_24, UInt<3>(0h5), _which_T_99) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_101 = mux(_which_T_23, UInt<1>(0h1), _which_T_100) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_102 = mux(_which_T_22, UInt<4>(0h9), _which_T_101) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_103 = mux(_which_T_21, UInt<3>(0h7), _which_T_102) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_104 = mux(_which_T_20, UInt<2>(0h3), _which_T_103) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_105 = mux(_which_T_19, UInt<4>(0hb), _which_T_104) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_106 = mux(_which_T_18, UInt<4>(0hc), _which_T_105) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_107 = mux(_which_T_17, UInt<4>(0hd), _which_T_106) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_108 = mux(_which_T_16, UInt<4>(0he), _which_T_107) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_109 = mux(_which_T_15, UInt<4>(0hf), _which_T_108) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_110 = mux(UInt<1>(0h0), UInt<1>(0h0), _which_T_109) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_111 = mux(_which_T_14, UInt<3>(0h4), _which_T_110) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_112 = mux(_which_T_13, UInt<1>(0h0), _which_T_111) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_113 = mux(_which_T_12, UInt<4>(0h8), _which_T_112) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_114 = mux(_which_T_11, UInt<3>(0h6), _which_T_113) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_115 = mux(_which_T_10, UInt<2>(0h2), _which_T_114) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_116 = mux(_which_T_9, UInt<4>(0ha), _which_T_115) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_117 = mux(_which_T_8, UInt<3>(0h5), _which_T_116) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_118 = mux(_which_T_7, UInt<1>(0h1), _which_T_117) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_119 = mux(_which_T_6, UInt<4>(0h9), _which_T_118) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_120 = mux(_which_T_5, UInt<3>(0h7), _which_T_119) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_121 = mux(_which_T_4, UInt<2>(0h3), _which_T_120) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_122 = mux(_which_T_3, UInt<4>(0hb), _which_T_121) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_123 = mux(_which_T_2, UInt<4>(0hc), _which_T_122) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _which_T_124 = mux(_which_T_1, UInt<4>(0hd), _which_T_123) @[src/main/scala/chisel3/util/Mux.scala 50:70] node whichInterrupt = mux(_which_T, UInt<4>(0he), _which_T_124) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _interruptCause_T = shl(UInt<1>(0h0), 62) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 626:50] node _interruptCause_T_1 = add(UInt<64>(0h8000000000000000), _interruptCause_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 626:39] node _interruptCause_T_2 = tail(_interruptCause_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 626:39] node _interruptCause_T_3 = add(_interruptCause_T_2, whichInterrupt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 626:63] node interruptCause = tail(_interruptCause_T_3, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 626:63] node _io_interrupt_T = eq(io.singleStep, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 627:36] node _io_interrupt_T_1 = and(anyInterrupt, _io_interrupt_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 627:33] node _io_interrupt_T_2 = or(_io_interrupt_T_1, reg_singleStepped) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 627:51] node _io_interrupt_T_3 = or(reg_debug, io.status.cease) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 627:88] node _io_interrupt_T_4 = eq(_io_interrupt_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 627:76] node _io_interrupt_T_5 = and(_io_interrupt_T_2, _io_interrupt_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 627:73] connect io.interrupt, _io_interrupt_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 627:16] connect io.interrupt_cause, interruptCause @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 628:22] connect io.bp[0], reg_bp[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 629:9] connect io.mcontext, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 630:15] connect io.scontext, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 631:15] node _io_fiom_T = lt(reg_mstatus.prv, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 632:31] node _io_fiom_T_1 = and(_io_fiom_T, reg_menvcfg.fiom) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 632:41] node _io_fiom_T_2 = lt(reg_mstatus.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 632:82] node _io_fiom_T_3 = and(_io_fiom_T_2, reg_senvcfg.fiom) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 632:92] node _io_fiom_T_4 = or(_io_fiom_T_1, _io_fiom_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 632:62] node _io_fiom_T_5 = and(reg_mstatus.v, reg_henvcfg.fiom) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 632:131] node _io_fiom_T_6 = or(_io_fiom_T_4, _io_fiom_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 632:113] connect io.fiom, _io_fiom_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 632:11] wire pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 24:19] connect pmp.cfg, reg_pmp[0].cfg @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 25:13] connect pmp.addr, reg_pmp[0].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 26:14] node _pmp_mask_base_T = bits(pmp.cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:31] node _pmp_mask_base_T_1 = cat(pmp.addr, _pmp_mask_base_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:19] node _pmp_mask_base_T_2 = shr(UInt<2>(0h3), 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:62] node pmp_mask_base = or(_pmp_mask_base_T_1, _pmp_mask_base_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:36] node _pmp_mask_T = add(pmp_mask_base, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:23] node _pmp_mask_T_1 = tail(_pmp_mask_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:23] node _pmp_mask_T_2 = not(_pmp_mask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:16] node _pmp_mask_T_3 = and(pmp_mask_base, _pmp_mask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:14] node _pmp_mask_T_4 = cat(_pmp_mask_T_3, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:8] connect pmp.mask, _pmp_mask_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 27:14] wire pmp_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 24:19] connect pmp_1.cfg, reg_pmp[1].cfg @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 25:13] connect pmp_1.addr, reg_pmp[1].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 26:14] node _pmp_mask_base_T_3 = bits(pmp_1.cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:31] node _pmp_mask_base_T_4 = cat(pmp_1.addr, _pmp_mask_base_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:19] node _pmp_mask_base_T_5 = shr(UInt<2>(0h3), 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:62] node pmp_mask_base_1 = or(_pmp_mask_base_T_4, _pmp_mask_base_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:36] node _pmp_mask_T_5 = add(pmp_mask_base_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:23] node _pmp_mask_T_6 = tail(_pmp_mask_T_5, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:23] node _pmp_mask_T_7 = not(_pmp_mask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:16] node _pmp_mask_T_8 = and(pmp_mask_base_1, _pmp_mask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:14] node _pmp_mask_T_9 = cat(_pmp_mask_T_8, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:8] connect pmp_1.mask, _pmp_mask_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 27:14] wire pmp_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 24:19] connect pmp_2.cfg, reg_pmp[2].cfg @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 25:13] connect pmp_2.addr, reg_pmp[2].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 26:14] node _pmp_mask_base_T_6 = bits(pmp_2.cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:31] node _pmp_mask_base_T_7 = cat(pmp_2.addr, _pmp_mask_base_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:19] node _pmp_mask_base_T_8 = shr(UInt<2>(0h3), 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:62] node pmp_mask_base_2 = or(_pmp_mask_base_T_7, _pmp_mask_base_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:36] node _pmp_mask_T_10 = add(pmp_mask_base_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:23] node _pmp_mask_T_11 = tail(_pmp_mask_T_10, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:23] node _pmp_mask_T_12 = not(_pmp_mask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:16] node _pmp_mask_T_13 = and(pmp_mask_base_2, _pmp_mask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:14] node _pmp_mask_T_14 = cat(_pmp_mask_T_13, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:8] connect pmp_2.mask, _pmp_mask_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 27:14] wire pmp_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 24:19] connect pmp_3.cfg, reg_pmp[3].cfg @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 25:13] connect pmp_3.addr, reg_pmp[3].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 26:14] node _pmp_mask_base_T_9 = bits(pmp_3.cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:31] node _pmp_mask_base_T_10 = cat(pmp_3.addr, _pmp_mask_base_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:19] node _pmp_mask_base_T_11 = shr(UInt<2>(0h3), 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:62] node pmp_mask_base_3 = or(_pmp_mask_base_T_10, _pmp_mask_base_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:36] node _pmp_mask_T_15 = add(pmp_mask_base_3, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:23] node _pmp_mask_T_16 = tail(_pmp_mask_T_15, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:23] node _pmp_mask_T_17 = not(_pmp_mask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:16] node _pmp_mask_T_18 = and(pmp_mask_base_3, _pmp_mask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:14] node _pmp_mask_T_19 = cat(_pmp_mask_T_18, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:8] connect pmp_3.mask, _pmp_mask_T_19 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 27:14] wire pmp_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 24:19] connect pmp_4.cfg, reg_pmp[4].cfg @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 25:13] connect pmp_4.addr, reg_pmp[4].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 26:14] node _pmp_mask_base_T_12 = bits(pmp_4.cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:31] node _pmp_mask_base_T_13 = cat(pmp_4.addr, _pmp_mask_base_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:19] node _pmp_mask_base_T_14 = shr(UInt<2>(0h3), 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:62] node pmp_mask_base_4 = or(_pmp_mask_base_T_13, _pmp_mask_base_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:36] node _pmp_mask_T_20 = add(pmp_mask_base_4, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:23] node _pmp_mask_T_21 = tail(_pmp_mask_T_20, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:23] node _pmp_mask_T_22 = not(_pmp_mask_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:16] node _pmp_mask_T_23 = and(pmp_mask_base_4, _pmp_mask_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:14] node _pmp_mask_T_24 = cat(_pmp_mask_T_23, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:8] connect pmp_4.mask, _pmp_mask_T_24 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 27:14] wire pmp_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 24:19] connect pmp_5.cfg, reg_pmp[5].cfg @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 25:13] connect pmp_5.addr, reg_pmp[5].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 26:14] node _pmp_mask_base_T_15 = bits(pmp_5.cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:31] node _pmp_mask_base_T_16 = cat(pmp_5.addr, _pmp_mask_base_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:19] node _pmp_mask_base_T_17 = shr(UInt<2>(0h3), 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:62] node pmp_mask_base_5 = or(_pmp_mask_base_T_16, _pmp_mask_base_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:36] node _pmp_mask_T_25 = add(pmp_mask_base_5, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:23] node _pmp_mask_T_26 = tail(_pmp_mask_T_25, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:23] node _pmp_mask_T_27 = not(_pmp_mask_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:16] node _pmp_mask_T_28 = and(pmp_mask_base_5, _pmp_mask_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:14] node _pmp_mask_T_29 = cat(_pmp_mask_T_28, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:8] connect pmp_5.mask, _pmp_mask_T_29 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 27:14] wire pmp_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 24:19] connect pmp_6.cfg, reg_pmp[6].cfg @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 25:13] connect pmp_6.addr, reg_pmp[6].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 26:14] node _pmp_mask_base_T_18 = bits(pmp_6.cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:31] node _pmp_mask_base_T_19 = cat(pmp_6.addr, _pmp_mask_base_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:19] node _pmp_mask_base_T_20 = shr(UInt<2>(0h3), 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:62] node pmp_mask_base_6 = or(_pmp_mask_base_T_19, _pmp_mask_base_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:36] node _pmp_mask_T_30 = add(pmp_mask_base_6, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:23] node _pmp_mask_T_31 = tail(_pmp_mask_T_30, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:23] node _pmp_mask_T_32 = not(_pmp_mask_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:16] node _pmp_mask_T_33 = and(pmp_mask_base_6, _pmp_mask_T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:14] node _pmp_mask_T_34 = cat(_pmp_mask_T_33, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:8] connect pmp_6.mask, _pmp_mask_T_34 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 27:14] wire pmp_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 24:19] connect pmp_7.cfg, reg_pmp[7].cfg @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 25:13] connect pmp_7.addr, reg_pmp[7].addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 26:14] node _pmp_mask_base_T_21 = bits(pmp_7.cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:31] node _pmp_mask_base_T_22 = cat(pmp_7.addr, _pmp_mask_base_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:19] node _pmp_mask_base_T_23 = shr(UInt<2>(0h3), 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:62] node pmp_mask_base_7 = or(_pmp_mask_base_T_22, _pmp_mask_base_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 57:36] node _pmp_mask_T_35 = add(pmp_mask_base_7, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:23] node _pmp_mask_T_36 = tail(_pmp_mask_T_35, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:23] node _pmp_mask_T_37 = not(_pmp_mask_T_36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:16] node _pmp_mask_T_38 = and(pmp_mask_base_7, _pmp_mask_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:14] node _pmp_mask_T_39 = cat(_pmp_mask_T_38, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 58:8] connect pmp_7.mask, _pmp_mask_T_39 @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 27:14] connect io.pmp[0], pmp @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 633:10] connect io.pmp[1], pmp_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 633:10] connect io.pmp[2], pmp_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 633:10] connect io.pmp[3], pmp_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 633:10] connect io.pmp[4], pmp_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 633:10] connect io.pmp[5], pmp_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 633:10] connect io.pmp[6], pmp_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 633:10] connect io.pmp[7], pmp_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 633:10] regreset reg_misa : UInt, clock, reset, UInt<64>(0h800000000080112d) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 649:25] node read_mstatus_lo_lo_lo_lo = cat(io.status.sie, io.status.uie) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_lo_lo_lo_hi = cat(io.status.mie, io.status.hie) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_lo_lo_lo = cat(read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_lo_lo_hi_lo = cat(io.status.spie, io.status.upie) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_lo_lo_hi_hi_hi = cat(io.status.spp, io.status.mpie) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_lo_lo_hi_hi = cat(read_mstatus_lo_lo_hi_hi_hi, io.status.ube) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_lo_lo_hi = cat(read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_lo_lo = cat(read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_lo_hi_lo_lo = cat(io.status.mpp, io.status.vs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_lo_hi_lo_hi = cat(io.status.xs, io.status.fs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_lo_hi_lo = cat(read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_lo_hi_hi_lo = cat(io.status.sum, io.status.mprv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_lo_hi_hi_hi_hi = cat(io.status.tw, io.status.tvm) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_lo_hi_hi_hi = cat(read_mstatus_lo_hi_hi_hi_hi, io.status.mxr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_lo_hi_hi = cat(read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_lo_hi = cat(read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_lo = cat(read_mstatus_lo_hi, read_mstatus_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_hi_lo_lo_lo = cat(io.status.zero1, io.status.tsr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_hi_lo_lo_hi = cat(io.status.uxl, io.status.sd_rv32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_hi_lo_lo = cat(read_mstatus_hi_lo_lo_hi, read_mstatus_hi_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_hi_lo_hi_lo = cat(io.status.sbe, io.status.sxl) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_hi_lo_hi_hi_hi = cat(io.status.mpv, io.status.gva) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_hi_lo_hi_hi = cat(read_mstatus_hi_lo_hi_hi_hi, io.status.mbe) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_hi_lo_hi = cat(read_mstatus_hi_lo_hi_hi, read_mstatus_hi_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_hi_lo = cat(read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_hi_hi_lo_lo = cat(io.status.sd, io.status.zero2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_hi_hi_lo_hi_hi = cat(io.status.dv, io.status.prv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_hi_hi_lo_hi = cat(read_mstatus_hi_hi_lo_hi_hi, io.status.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_hi_hi_lo = cat(read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_hi_hi_hi_lo = cat(io.status.isa, io.status.dprv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_hi_hi_hi_hi_hi = cat(io.status.debug, io.status.cease) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_hi_hi_hi_hi = cat(read_mstatus_hi_hi_hi_hi_hi, io.status.wfi) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_hi_hi_hi = cat(read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_hi_hi = cat(read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus_hi = cat(read_mstatus_hi_hi, read_mstatus_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node _read_mstatus_T = cat(read_mstatus_hi, read_mstatus_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 650:32] node read_mstatus = bits(_read_mstatus_T, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _read_mtvec_T = bits(reg_mtvec, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1668:41] node _read_mtvec_T_1 = mux(_read_mtvec_T, UInt<8>(0hfe), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1668:39] node _read_mtvec_T_2 = and(reg_mtvec, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 175:46] node _read_mtvec_T_3 = or(_read_mtvec_T_1, _read_mtvec_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 175:41] node _read_mtvec_T_4 = not(_read_mtvec_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 175:37] node _read_mtvec_T_5 = and(reg_mtvec, _read_mtvec_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 175:35] node read_mtvec = cat(UInt<32>(0h0), _read_mtvec_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 139:15] node _read_stvec_T = bits(reg_stvec, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1668:41] node _read_stvec_T_1 = mux(_read_stvec_T, UInt<8>(0hfe), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1668:39] node _read_stvec_T_2 = and(reg_stvec, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 175:46] node _read_stvec_T_3 = or(_read_stvec_T_1, _read_stvec_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 175:41] node _read_stvec_T_4 = not(_read_stvec_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 175:37] node _read_stvec_T_5 = and(reg_stvec, _read_stvec_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 175:35] node _read_stvec_T_6 = bits(_read_stvec_T_5, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:38] node _read_stvec_T_7 = mux(_read_stvec_T_6, UInt<31>(0h7fffffff), UInt<31>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:20] node read_stvec = cat(_read_stvec_T_7, _read_stvec_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:15] node read_mapping_lo_lo_hi = cat(reg_bp[reg_tselect].control.x, reg_bp[reg_tselect].control.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 656:48] node read_mapping_lo_lo = cat(read_mapping_lo_lo_hi, reg_bp[reg_tselect].control.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 656:48] node read_mapping_lo_hi_lo = cat(reg_bp[reg_tselect].control.s, reg_bp[reg_tselect].control.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 656:48] node read_mapping_lo_hi_hi = cat(reg_bp[reg_tselect].control.m, reg_bp[reg_tselect].control.h) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 656:48] node read_mapping_lo_hi = cat(read_mapping_lo_hi_hi, read_mapping_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 656:48] node read_mapping_lo = cat(read_mapping_lo_hi, read_mapping_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 656:48] node read_mapping_hi_lo_lo = cat(reg_bp[reg_tselect].control.zero, reg_bp[reg_tselect].control.tmatch) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 656:48] node read_mapping_hi_lo_hi = cat(reg_bp[reg_tselect].control.action, reg_bp[reg_tselect].control.chain) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 656:48] node read_mapping_hi_lo = cat(read_mapping_hi_lo_hi, read_mapping_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 656:48] node read_mapping_hi_hi_lo = cat(reg_bp[reg_tselect].control.maskmax, reg_bp[reg_tselect].control.reserved) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 656:48] node read_mapping_hi_hi_hi = cat(reg_bp[reg_tselect].control.ttype, reg_bp[reg_tselect].control.dmode) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 656:48] node read_mapping_hi_hi = cat(read_mapping_hi_hi_hi, read_mapping_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 656:48] node read_mapping_hi = cat(read_mapping_hi_hi, read_mapping_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 656:48] node read_mapping_1_2 = cat(read_mapping_hi, read_mapping_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 656:48] node _read_mapping_T = bits(reg_bp[reg_tselect].address, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:38] node _read_mapping_T_1 = mux(_read_mapping_T, UInt<31>(0h7fffffff), UInt<31>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:20] node read_mapping_2_2 = cat(_read_mapping_T_1, reg_bp[reg_tselect].address) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:15] node read_mapping_lo_hi_1 = cat(reg_bp[reg_tselect].textra.svalue, reg_bp[reg_tselect].textra.pad1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 658:47] node read_mapping_lo_1 = cat(read_mapping_lo_hi_1, reg_bp[reg_tselect].textra.sselect) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 658:47] node read_mapping_hi_hi_1 = cat(reg_bp[reg_tselect].textra.mvalue, reg_bp[reg_tselect].textra.mselect) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 658:47] node read_mapping_hi_1 = cat(read_mapping_hi_hi_1, reg_bp[reg_tselect].textra.pad2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 658:47] node read_mapping_3_2 = cat(read_mapping_hi_1, read_mapping_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 658:47] node _read_mapping_T_2 = not(reg_mepc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:28] node _read_mapping_T_3 = bits(reg_misa, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:45] node _read_mapping_T_4 = mux(_read_mapping_T_3, UInt<1>(0h1), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:36] node _read_mapping_T_5 = or(_read_mapping_T_2, _read_mapping_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:31] node _read_mapping_T_6 = not(_read_mapping_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:26] node _read_mapping_T_7 = bits(_read_mapping_T_6, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:38] node _read_mapping_T_8 = mux(_read_mapping_T_7, UInt<30>(0h3fffffff), UInt<30>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:20] node read_mapping_10_2 = cat(_read_mapping_T_8, _read_mapping_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:15] node _read_mapping_T_9 = bits(reg_mtval, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:38] node _read_mapping_T_10 = mux(_read_mapping_T_9, UInt<30>(0h3fffffff), UInt<30>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:20] node read_mapping_11_2 = cat(_read_mapping_T_10, reg_mtval) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:15] node debug_csrs_lo_lo_hi = cat(reg_dcsr.zero1, reg_dcsr.step) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 671:27] node debug_csrs_lo_lo = cat(debug_csrs_lo_lo_hi, reg_dcsr.prv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 671:27] node debug_csrs_lo_hi_lo = cat(reg_dcsr.cause, reg_dcsr.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 671:27] node debug_csrs_lo_hi_hi = cat(reg_dcsr.stopcycle, reg_dcsr.stoptime) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 671:27] node debug_csrs_lo_hi = cat(debug_csrs_lo_hi_hi, debug_csrs_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 671:27] node debug_csrs_lo = cat(debug_csrs_lo_hi, debug_csrs_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 671:27] node debug_csrs_hi_lo_lo = cat(reg_dcsr.ebreaku, reg_dcsr.zero2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 671:27] node debug_csrs_hi_lo_hi = cat(reg_dcsr.ebreakh, reg_dcsr.ebreaks) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 671:27] node debug_csrs_hi_lo = cat(debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 671:27] node debug_csrs_hi_hi_lo = cat(reg_dcsr.zero3, reg_dcsr.ebreakm) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 671:27] node debug_csrs_hi_hi_hi = cat(reg_dcsr.xdebugver, reg_dcsr.zero4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 671:27] node debug_csrs_hi_hi = cat(debug_csrs_hi_hi_hi, debug_csrs_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 671:27] node debug_csrs_hi = cat(debug_csrs_hi_hi, debug_csrs_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 671:27] node debug_csrs_0_2 = cat(debug_csrs_hi, debug_csrs_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 671:27] node _debug_csrs_T = not(reg_dpc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:28] node _debug_csrs_T_1 = bits(reg_misa, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:45] node _debug_csrs_T_2 = mux(_debug_csrs_T_1, UInt<1>(0h1), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:36] node _debug_csrs_T_3 = or(_debug_csrs_T, _debug_csrs_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:31] node _debug_csrs_T_4 = not(_debug_csrs_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:26] node _debug_csrs_T_5 = bits(_debug_csrs_T_4, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:38] node _debug_csrs_T_6 = mux(_debug_csrs_T_5, UInt<30>(0h3fffffff), UInt<30>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:20] node debug_csrs_1_2 = cat(_debug_csrs_T_6, _debug_csrs_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:15] wire _read_mnstatus_WIRE : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 676:44] connect _read_mnstatus_WIRE.zero1, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 676:44] connect _read_mnstatus_WIRE.mie, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 676:44] connect _read_mnstatus_WIRE.zero2, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 676:44] connect _read_mnstatus_WIRE.mpv, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 676:44] connect _read_mnstatus_WIRE.zero3, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 676:44] connect _read_mnstatus_WIRE.mpp, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 676:44] wire read_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 676:31] connect read_mnstatus, _read_mnstatus_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 676:31] connect read_mnstatus.mpp, reg_mnstatus.mpp @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 677:21] connect read_mnstatus.mpv, reg_mnstatus.mpv @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 678:21] connect read_mnstatus.mie, reg_rnmie @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 679:21] node read_fcsr = cat(reg_frm, reg_fflags) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 690:22] node read_vcsr = cat(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 696:22] wire _sie_mask_sgeip_mask_WIRE : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:43] connect _sie_mask_sgeip_mask_WIRE.usip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:43] connect _sie_mask_sgeip_mask_WIRE.ssip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:43] connect _sie_mask_sgeip_mask_WIRE.vssip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:43] connect _sie_mask_sgeip_mask_WIRE.msip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:43] connect _sie_mask_sgeip_mask_WIRE.utip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:43] connect _sie_mask_sgeip_mask_WIRE.stip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:43] connect _sie_mask_sgeip_mask_WIRE.vstip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:43] connect _sie_mask_sgeip_mask_WIRE.mtip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:43] connect _sie_mask_sgeip_mask_WIRE.ueip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:43] connect _sie_mask_sgeip_mask_WIRE.seip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:43] connect _sie_mask_sgeip_mask_WIRE.vseip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:43] connect _sie_mask_sgeip_mask_WIRE.meip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:43] connect _sie_mask_sgeip_mask_WIRE.sgeip, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:43] connect _sie_mask_sgeip_mask_WIRE.rocc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:43] connect _sie_mask_sgeip_mask_WIRE.debug, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:43] connect _sie_mask_sgeip_mask_WIRE.zero1, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:43] wire sie_mask_sgeip_mask : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:30] connect sie_mask_sgeip_mask, _sie_mask_sgeip_mask_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 749:30] connect sie_mask_sgeip_mask.sgeip, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 750:22] node sie_mask_lo_lo_lo = cat(sie_mask_sgeip_mask.ssip, sie_mask_sgeip_mask.usip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:59] node sie_mask_lo_lo_hi = cat(sie_mask_sgeip_mask.msip, sie_mask_sgeip_mask.vssip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:59] node sie_mask_lo_lo = cat(sie_mask_lo_lo_hi, sie_mask_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:59] node sie_mask_lo_hi_lo = cat(sie_mask_sgeip_mask.stip, sie_mask_sgeip_mask.utip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:59] node sie_mask_lo_hi_hi = cat(sie_mask_sgeip_mask.mtip, sie_mask_sgeip_mask.vstip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:59] node sie_mask_lo_hi = cat(sie_mask_lo_hi_hi, sie_mask_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:59] node sie_mask_lo = cat(sie_mask_lo_hi, sie_mask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:59] node sie_mask_hi_lo_lo = cat(sie_mask_sgeip_mask.seip, sie_mask_sgeip_mask.ueip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:59] node sie_mask_hi_lo_hi = cat(sie_mask_sgeip_mask.meip, sie_mask_sgeip_mask.vseip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:59] node sie_mask_hi_lo = cat(sie_mask_hi_lo_hi, sie_mask_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:59] node sie_mask_hi_hi_lo = cat(sie_mask_sgeip_mask.rocc, sie_mask_sgeip_mask.sgeip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:59] node sie_mask_hi_hi_hi_hi = cat(UInt<0>(0h0), sie_mask_sgeip_mask.zero1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:59] node sie_mask_hi_hi_hi = cat(sie_mask_hi_hi_hi_hi, sie_mask_sgeip_mask.debug) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:59] node sie_mask_hi_hi = cat(sie_mask_hi_hi_hi, sie_mask_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:59] node sie_mask_hi = cat(sie_mask_hi_hi, sie_mask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:59] node _sie_mask_T = cat(sie_mask_hi, sie_mask_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:59] node _sie_mask_T_1 = or(hs_delegable_interrupts, _sie_mask_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:46] node _sie_mask_T_2 = not(_sie_mask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:20] node sie_mask = and(read_mideleg, _sie_mask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 751:18] wire read_pmp_15 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 788:59] connect read_pmp_15.mask, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 788:59] connect read_pmp_15.addr, UInt<30>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 788:59] connect read_pmp_15.cfg.r, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 788:59] connect read_pmp_15.cfg.w, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 788:59] connect read_pmp_15.cfg.x, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 788:59] connect read_pmp_15.cfg.a, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 788:59] connect read_pmp_15.cfg.res, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 788:59] connect read_pmp_15.cfg.l, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 788:59] node lo_hi_4 = cat(reg_pmp[0].cfg.x, reg_pmp[0].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_4 = cat(lo_hi_4, reg_pmp[0].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_hi_4 = cat(reg_pmp[0].cfg.l, reg_pmp[0].cfg.res) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_6 = cat(hi_hi_4, reg_pmp[0].cfg.a) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node _T_19 = cat(hi_6, lo_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_hi_5 = cat(reg_pmp[1].cfg.x, reg_pmp[1].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_5 = cat(lo_hi_5, reg_pmp[1].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_hi_5 = cat(reg_pmp[1].cfg.l, reg_pmp[1].cfg.res) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_7 = cat(hi_hi_5, reg_pmp[1].cfg.a) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node _T_20 = cat(hi_7, lo_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_hi_6 = cat(reg_pmp[2].cfg.x, reg_pmp[2].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_6 = cat(lo_hi_6, reg_pmp[2].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_hi_6 = cat(reg_pmp[2].cfg.l, reg_pmp[2].cfg.res) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_8 = cat(hi_hi_6, reg_pmp[2].cfg.a) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node _T_21 = cat(hi_8, lo_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_hi_7 = cat(reg_pmp[3].cfg.x, reg_pmp[3].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_7 = cat(lo_hi_7, reg_pmp[3].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_hi_7 = cat(reg_pmp[3].cfg.l, reg_pmp[3].cfg.res) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_9 = cat(hi_hi_7, reg_pmp[3].cfg.a) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node _T_22 = cat(hi_9, lo_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_hi_8 = cat(reg_pmp[4].cfg.x, reg_pmp[4].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_8 = cat(lo_hi_8, reg_pmp[4].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_hi_8 = cat(reg_pmp[4].cfg.l, reg_pmp[4].cfg.res) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_10 = cat(hi_hi_8, reg_pmp[4].cfg.a) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node _T_23 = cat(hi_10, lo_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_hi_9 = cat(reg_pmp[5].cfg.x, reg_pmp[5].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_9 = cat(lo_hi_9, reg_pmp[5].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_hi_9 = cat(reg_pmp[5].cfg.l, reg_pmp[5].cfg.res) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_11 = cat(hi_hi_9, reg_pmp[5].cfg.a) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node _T_24 = cat(hi_11, lo_9) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_hi_10 = cat(reg_pmp[6].cfg.x, reg_pmp[6].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_10 = cat(lo_hi_10, reg_pmp[6].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_hi_10 = cat(reg_pmp[6].cfg.l, reg_pmp[6].cfg.res) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_12 = cat(hi_hi_10, reg_pmp[6].cfg.a) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node _T_25 = cat(hi_12, lo_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_hi_11 = cat(reg_pmp[7].cfg.x, reg_pmp[7].cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_11 = cat(lo_hi_11, reg_pmp[7].cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_hi_11 = cat(reg_pmp[7].cfg.l, reg_pmp[7].cfg.res) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_13 = cat(hi_hi_11, reg_pmp[7].cfg.a) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node _T_26 = cat(hi_13, lo_11) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_lo_4 = cat(_T_20, _T_19) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node lo_hi_12 = cat(_T_22, _T_21) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node lo_12 = cat(lo_hi_12, lo_lo_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hi_lo_4 = cat(_T_24, _T_23) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hi_hi_12 = cat(_T_26, _T_25) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hi_14 = cat(hi_hi_12, hi_lo_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _T_27 = cat(hi_14, lo_12) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node lo_hi_13 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_13 = cat(lo_hi_13, read_pmp_15.cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_hi_13 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_15 = cat(hi_hi_13, read_pmp_15.cfg.a) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node _T_28 = cat(hi_15, lo_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_hi_14 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_14 = cat(lo_hi_14, read_pmp_15.cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_hi_14 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_16 = cat(hi_hi_14, read_pmp_15.cfg.a) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node _T_29 = cat(hi_16, lo_14) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_hi_15 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_15 = cat(lo_hi_15, read_pmp_15.cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_hi_15 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_17 = cat(hi_hi_15, read_pmp_15.cfg.a) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node _T_30 = cat(hi_17, lo_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_hi_16 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_16 = cat(lo_hi_16, read_pmp_15.cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_hi_16 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_18 = cat(hi_hi_16, read_pmp_15.cfg.a) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node _T_31 = cat(hi_18, lo_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_hi_17 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_17 = cat(lo_hi_17, read_pmp_15.cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_hi_17 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_19 = cat(hi_hi_17, read_pmp_15.cfg.a) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node _T_32 = cat(hi_19, lo_17) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_hi_18 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_18 = cat(lo_hi_18, read_pmp_15.cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_hi_18 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_20 = cat(hi_hi_18, read_pmp_15.cfg.a) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node _T_33 = cat(hi_20, lo_18) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_hi_19 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_19 = cat(lo_hi_19, read_pmp_15.cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_hi_19 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_21 = cat(hi_hi_19, read_pmp_15.cfg.a) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node _T_34 = cat(hi_21, lo_19) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_hi_20 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_20 = cat(lo_hi_20, read_pmp_15.cfg.r) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_hi_20 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node hi_22 = cat(hi_hi_20, read_pmp_15.cfg.a) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node _T_35 = cat(hi_22, lo_20) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:36] node lo_lo_5 = cat(_T_29, _T_28) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node lo_hi_21 = cat(_T_31, _T_30) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node lo_21 = cat(lo_hi_21, lo_lo_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hi_lo_5 = cat(_T_33, _T_32) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hi_hi_21 = cat(_T_35, _T_34) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node hi_23 = cat(hi_hi_21, hi_lo_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _T_36 = cat(hi_23, lo_21) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] regreset reg_custom_0 : UInt<64>, clock, reset, UInt<64>(0h8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 799:43] node _reg_custom_read_T = neq(io.rw.cmd, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 800:26] node _reg_custom_read_T_1 = eq(io.rw.addr, UInt<11>(0h7c1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 800:50] node reg_custom_read = and(_reg_custom_read_T, _reg_custom_read_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 800:36] connect io.customCSRs[0].ren, reg_custom_read @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 801:16] node _reg_custom_T = and(reg_custom_read, io.customCSRs[0].stall) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 802:16] when _reg_custom_T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 802:33] connect io.rw_stall, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 802:47] regreset reg_custom_1 : UInt<64>, clock, reset, UInt<64>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 799:43] node _reg_custom_read_T_2 = neq(io.rw.cmd, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 800:26] node _reg_custom_read_T_3 = eq(io.rw.addr, UInt<12>(0hf12)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 800:50] node reg_custom_read_1 = and(_reg_custom_read_T_2, _reg_custom_read_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 800:36] connect io.customCSRs[1].ren, reg_custom_read_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 801:16] node _reg_custom_T_1 = and(reg_custom_read_1, io.customCSRs[1].stall) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 802:16] when _reg_custom_T_1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 802:33] connect io.rw_stall, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 802:47] regreset reg_custom_2 : UInt<64>, clock, reset, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 799:43] node _reg_custom_read_T_4 = neq(io.rw.cmd, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 800:26] node _reg_custom_read_T_5 = eq(io.rw.addr, UInt<12>(0hf11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 800:50] node reg_custom_read_2 = and(_reg_custom_read_T_4, _reg_custom_read_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 800:36] connect io.customCSRs[2].ren, reg_custom_read_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 801:16] node _reg_custom_T_2 = and(reg_custom_read_2, io.customCSRs[2].stall) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 802:16] when _reg_custom_T_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 802:33] connect io.rw_stall, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 802:47] regreset reg_custom_3 : UInt<64>, clock, reset, UInt<64>(0h20181004) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 799:43] node _reg_custom_read_T_6 = neq(io.rw.cmd, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 800:26] node _reg_custom_read_T_7 = eq(io.rw.addr, UInt<12>(0hf13)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 800:50] node reg_custom_read_3 = and(_reg_custom_read_T_6, _reg_custom_read_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 800:36] connect io.customCSRs[3].ren, reg_custom_read_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 801:16] node _reg_custom_T_3 = and(reg_custom_read_3, io.customCSRs[3].stall) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 802:16] when _reg_custom_T_3 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 802:33] connect io.rw_stall, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 802:47] node decoded_addr_addr = cat(io.status.v, io.rw.addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 852:19] wire decoded_addr_decoded_decoded_plaInput : UInt<12> @[src/main/scala/chisel3/util/pla.scala 77:22] node decoded_addr_decoded_decoded_invInputs = not(decoded_addr_decoded_decoded_plaInput) @[src/main/scala/chisel3/util/pla.scala 78:21] wire decoded_addr_decoded_decoded : UInt<135> @[src/main/scala/chisel3/util/pla.scala 81:23] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_1) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_2) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_3) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_4) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_5) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_6) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_7) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_8) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_9) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_10) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_11) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_12) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_13) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_14) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_15) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_16) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_17) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_18) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_19) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_20) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_21) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_22) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_23) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_24) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_25) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_26) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_27) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_28) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_29) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_30) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_31) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_32) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_33) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_34) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_35) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_36) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_37) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_38) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_39) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_40) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_41) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_42) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_43) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_44) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_45) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_46) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_47) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_48) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_49) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_50) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_51) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_52) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_53) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_54) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_55) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_56) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_57) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_58) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_59) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_60) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_61) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_62) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_63) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_64) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_65) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_66) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_67) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_68) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_69) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_70) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_71) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_72) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_73) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_74) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_75) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_76) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_77) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_78) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_79) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_80) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_81) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_82) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_83) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_84) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_85) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_86) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_87) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_88) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_89) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_90) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_91) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_92) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_93) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_94) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_95) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_96) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_97) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_98) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_99) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_100) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_101) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_102) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_103) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_104) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_105) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_106) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_107) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_108) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_109) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_110) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_111) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_112) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_113) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_114) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_115) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_116) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_117) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_118) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_119) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_120) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_121) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_122) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_123) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_124) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_125) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_126) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_127) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_128) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_129) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_130) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_131) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_132) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_133) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_134) @[src/main/scala/chisel3/util/pla.scala 98:70] node _decoded_addr_decoded_decoded_orMatrixOutputs_T = orr(decoded_addr_decoded_decoded_andMatrixOutputs_67_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_12_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_89_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_33_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_11_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_134_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_101_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_86_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_130_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_36_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_65_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_122_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_81_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_99_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_88_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_75_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_51_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_80_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_18_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_39_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_9_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_42_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_60_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_46_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_43_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_98_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_111_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_129_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_70_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_48_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_27_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_63_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_84_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_34_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_37_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_53_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_56_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_45_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_85_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_28_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_14_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_76_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_31_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_40_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_13_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_58_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_104_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_116_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_82_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_110_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_128_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_22_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_87_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_15_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_127_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_91_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_24_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_118_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_62_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_3_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_78_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_133_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_90_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_16_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_96_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_115_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_114_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_100_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_64_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_74_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_19_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_4_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_54_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_57_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_103_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_7_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_17_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_8_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_77_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_32_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_117_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_124_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_120_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_52_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_106_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_47_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_55_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_105_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_66_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_26_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_10_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_30_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_38_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_126_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_112_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_125_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_41_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_25_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_69_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_6_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_21_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_132_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_97_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_5_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_109_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_93_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_95_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_0_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_49_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_20_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_83_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_121_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_71_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_68_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_29_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_35_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_119_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_123_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_23_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_44_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_2_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_73_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_72_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_108_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_94_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_59_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_79_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_107_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_61_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_102_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_92_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_50_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_113_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_131_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_1_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_7, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_9, _decoded_addr_decoded_decoded_orMatrixOutputs_T_8) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_11, _decoded_addr_decoded_decoded_orMatrixOutputs_T_10) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_13, _decoded_addr_decoded_decoded_orMatrixOutputs_T_12) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_15, _decoded_addr_decoded_decoded_orMatrixOutputs_T_14) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_17, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_19, _decoded_addr_decoded_decoded_orMatrixOutputs_T_18) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_21, _decoded_addr_decoded_decoded_orMatrixOutputs_T_20) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_25, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_27, _decoded_addr_decoded_decoded_orMatrixOutputs_T_26) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_29, _decoded_addr_decoded_decoded_orMatrixOutputs_T_28) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_32, _decoded_addr_decoded_decoded_orMatrixOutputs_T_31) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_34, _decoded_addr_decoded_decoded_orMatrixOutputs_T_33) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_36, _decoded_addr_decoded_decoded_orMatrixOutputs_T_35) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_40, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_42, _decoded_addr_decoded_decoded_orMatrixOutputs_T_41) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_44, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_46, _decoded_addr_decoded_decoded_orMatrixOutputs_T_45) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_49, _decoded_addr_decoded_decoded_orMatrixOutputs_T_48) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_47) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_51, _decoded_addr_decoded_decoded_orMatrixOutputs_T_50) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_53, _decoded_addr_decoded_decoded_orMatrixOutputs_T_52) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_55, _decoded_addr_decoded_decoded_orMatrixOutputs_T_54) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_59, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_61, _decoded_addr_decoded_decoded_orMatrixOutputs_T_60) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_63, _decoded_addr_decoded_decoded_orMatrixOutputs_T_62) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_66, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_64) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_68, _decoded_addr_decoded_decoded_orMatrixOutputs_T_67) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_70, _decoded_addr_decoded_decoded_orMatrixOutputs_T_69) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_72, _decoded_addr_decoded_decoded_orMatrixOutputs_T_71) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_74, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_76, _decoded_addr_decoded_decoded_orMatrixOutputs_T_75) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_78, _decoded_addr_decoded_decoded_orMatrixOutputs_T_77) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_80, _decoded_addr_decoded_decoded_orMatrixOutputs_T_79) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_83, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_81) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_85, _decoded_addr_decoded_decoded_orMatrixOutputs_T_84) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_87, _decoded_addr_decoded_decoded_orMatrixOutputs_T_86) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_89, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_91, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_93, _decoded_addr_decoded_decoded_orMatrixOutputs_T_92) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_95, _decoded_addr_decoded_decoded_orMatrixOutputs_T_94) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_97, _decoded_addr_decoded_decoded_orMatrixOutputs_T_96) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_100, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_98) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_102, _decoded_addr_decoded_decoded_orMatrixOutputs_T_101) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_104, _decoded_addr_decoded_decoded_orMatrixOutputs_T_103) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_110, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_112, _decoded_addr_decoded_decoded_orMatrixOutputs_T_111) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_114, _decoded_addr_decoded_decoded_orMatrixOutputs_T_113) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_117, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_115) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_119, _decoded_addr_decoded_decoded_orMatrixOutputs_T_118) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_121, _decoded_addr_decoded_decoded_orMatrixOutputs_T_120) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_123, _decoded_addr_decoded_decoded_orMatrixOutputs_T_122) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_125, _decoded_addr_decoded_decoded_orMatrixOutputs_T_124) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_129, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_131, _decoded_addr_decoded_decoded_orMatrixOutputs_T_130) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_134, _decoded_addr_decoded_decoded_orMatrixOutputs_T_133) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_132) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_addr_decoded_decoded_orMatrixOutputs = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node _decoded_addr_decoded_decoded_invMatrixOutputs_T = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 15, 15) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 16, 16) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 17, 17) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 18, 18) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 19, 19) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 32, 32) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 33, 33) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 34, 34) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 35, 35) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 36, 36) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 37, 37) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 38, 38) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 39, 39) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 40, 40) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 41, 41) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 42, 42) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 43, 43) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 44, 44) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 45, 45) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 46, 46) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 47, 47) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 48, 48) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 49, 49) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 50, 50) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 51, 51) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 52, 52) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 53, 53) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 54, 54) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 55, 55) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 56, 56) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 57, 57) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 58, 58) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 59, 59) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 60, 60) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 61, 61) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 62, 62) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 63, 63) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 64, 64) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 65, 65) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 66, 66) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 67, 67) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 68, 68) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 69, 69) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 70, 70) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 71, 71) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 72, 72) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 73, 73) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 74, 74) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 75, 75) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 76, 76) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 77, 77) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 78, 78) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 79, 79) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 80, 80) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 81, 81) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 82, 82) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 83, 83) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 84, 84) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 85, 85) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 86, 86) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 87, 87) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 88, 88) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 89, 89) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 90, 90) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 91, 91) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 92, 92) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 93, 93) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 94, 94) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 95, 95) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 96, 96) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 97, 97) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 98, 98) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 99, 99) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 100, 100) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 101, 101) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 102, 102) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 103, 103) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 104, 104) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 105, 105) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 106, 106) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 107, 107) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 108, 108) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 109, 109) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 110, 110) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 111, 111) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 112, 112) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 113, 113) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 114, 114) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 115, 115) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 116, 116) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 117, 117) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 118, 118) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 119, 119) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 120, 120) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 121, 121) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 122, 122) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 123, 123) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 124, 124) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 125, 125) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 126, 126) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 127, 127) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 128, 128) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 129, 129) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 130, 130) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 131, 131) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 132, 132) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 133, 133) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 134, 134) @[src/main/scala/chisel3/util/pla.scala 124:31] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_7, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_9, _decoded_addr_decoded_decoded_invMatrixOutputs_T_8) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_11, _decoded_addr_decoded_decoded_invMatrixOutputs_T_10) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_13, _decoded_addr_decoded_decoded_invMatrixOutputs_T_12) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_15, _decoded_addr_decoded_decoded_invMatrixOutputs_T_14) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_17, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_19, _decoded_addr_decoded_decoded_invMatrixOutputs_T_18) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_21, _decoded_addr_decoded_decoded_invMatrixOutputs_T_20) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_25, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_27, _decoded_addr_decoded_decoded_invMatrixOutputs_T_26) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_29, _decoded_addr_decoded_decoded_invMatrixOutputs_T_28) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_32, _decoded_addr_decoded_decoded_invMatrixOutputs_T_31) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_34, _decoded_addr_decoded_decoded_invMatrixOutputs_T_33) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_36, _decoded_addr_decoded_decoded_invMatrixOutputs_T_35) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_40, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_42, _decoded_addr_decoded_decoded_invMatrixOutputs_T_41) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_44, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_46, _decoded_addr_decoded_decoded_invMatrixOutputs_T_45) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_49, _decoded_addr_decoded_decoded_invMatrixOutputs_T_48) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_47) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_51, _decoded_addr_decoded_decoded_invMatrixOutputs_T_50) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_53, _decoded_addr_decoded_decoded_invMatrixOutputs_T_52) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_55, _decoded_addr_decoded_decoded_invMatrixOutputs_T_54) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_59, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_61, _decoded_addr_decoded_decoded_invMatrixOutputs_T_60) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_63, _decoded_addr_decoded_decoded_invMatrixOutputs_T_62) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_66, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_64) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_68, _decoded_addr_decoded_decoded_invMatrixOutputs_T_67) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_70, _decoded_addr_decoded_decoded_invMatrixOutputs_T_69) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_72, _decoded_addr_decoded_decoded_invMatrixOutputs_T_71) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_74, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_76, _decoded_addr_decoded_decoded_invMatrixOutputs_T_75) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_78, _decoded_addr_decoded_decoded_invMatrixOutputs_T_77) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_80, _decoded_addr_decoded_decoded_invMatrixOutputs_T_79) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_83, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_81) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_85, _decoded_addr_decoded_decoded_invMatrixOutputs_T_84) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_87, _decoded_addr_decoded_decoded_invMatrixOutputs_T_86) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_89, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_91, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_93, _decoded_addr_decoded_decoded_invMatrixOutputs_T_92) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_95, _decoded_addr_decoded_decoded_invMatrixOutputs_T_94) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_97, _decoded_addr_decoded_decoded_invMatrixOutputs_T_96) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_100, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_98) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_102, _decoded_addr_decoded_decoded_invMatrixOutputs_T_101) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_104, _decoded_addr_decoded_decoded_invMatrixOutputs_T_103) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_110, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_112, _decoded_addr_decoded_decoded_invMatrixOutputs_T_111) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_114, _decoded_addr_decoded_decoded_invMatrixOutputs_T_113) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_117, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_115) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_119, _decoded_addr_decoded_decoded_invMatrixOutputs_T_118) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_121, _decoded_addr_decoded_decoded_invMatrixOutputs_T_120) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_123, _decoded_addr_decoded_decoded_invMatrixOutputs_T_122) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_125, _decoded_addr_decoded_decoded_invMatrixOutputs_T_124) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_129, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_131, _decoded_addr_decoded_decoded_invMatrixOutputs_T_130) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_134, _decoded_addr_decoded_decoded_invMatrixOutputs_T_133) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_132) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_addr_decoded_decoded_invMatrixOutputs = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] connect decoded_addr_decoded_decoded, decoded_addr_decoded_decoded_invMatrixOutputs @[src/main/scala/chisel3/util/pla.scala 129:13] connect decoded_addr_decoded_decoded_plaInput, decoded_addr_addr @[src/main/scala/chisel3/util/experimental/decode/decoder.scala 35:16] node decoded_addr_decoded_0 = bits(decoded_addr_decoded_decoded, 134, 134) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_1 = bits(decoded_addr_decoded_decoded, 133, 133) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_2 = bits(decoded_addr_decoded_decoded, 132, 132) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_3 = bits(decoded_addr_decoded_decoded, 131, 131) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_4 = bits(decoded_addr_decoded_decoded, 130, 130) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_5 = bits(decoded_addr_decoded_decoded, 129, 129) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_6 = bits(decoded_addr_decoded_decoded, 128, 128) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_7 = bits(decoded_addr_decoded_decoded, 127, 127) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_8 = bits(decoded_addr_decoded_decoded, 126, 126) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_9 = bits(decoded_addr_decoded_decoded, 125, 125) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_10 = bits(decoded_addr_decoded_decoded, 124, 124) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_11 = bits(decoded_addr_decoded_decoded, 123, 123) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_12 = bits(decoded_addr_decoded_decoded, 122, 122) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_13 = bits(decoded_addr_decoded_decoded, 121, 121) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_14 = bits(decoded_addr_decoded_decoded, 120, 120) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_15 = bits(decoded_addr_decoded_decoded, 119, 119) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_16 = bits(decoded_addr_decoded_decoded, 118, 118) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_17 = bits(decoded_addr_decoded_decoded, 117, 117) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_18 = bits(decoded_addr_decoded_decoded, 116, 116) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_19 = bits(decoded_addr_decoded_decoded, 115, 115) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_20 = bits(decoded_addr_decoded_decoded, 114, 114) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_21 = bits(decoded_addr_decoded_decoded, 113, 113) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_22 = bits(decoded_addr_decoded_decoded, 112, 112) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_23 = bits(decoded_addr_decoded_decoded, 111, 111) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_24 = bits(decoded_addr_decoded_decoded, 110, 110) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_25 = bits(decoded_addr_decoded_decoded, 109, 109) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_26 = bits(decoded_addr_decoded_decoded, 108, 108) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_27 = bits(decoded_addr_decoded_decoded, 107, 107) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_28 = bits(decoded_addr_decoded_decoded, 106, 106) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_29 = bits(decoded_addr_decoded_decoded, 105, 105) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_30 = bits(decoded_addr_decoded_decoded, 104, 104) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_31 = bits(decoded_addr_decoded_decoded, 103, 103) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_32 = bits(decoded_addr_decoded_decoded, 102, 102) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_33 = bits(decoded_addr_decoded_decoded, 101, 101) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_34 = bits(decoded_addr_decoded_decoded, 100, 100) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_35 = bits(decoded_addr_decoded_decoded, 99, 99) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_36 = bits(decoded_addr_decoded_decoded, 98, 98) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_37 = bits(decoded_addr_decoded_decoded, 97, 97) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_38 = bits(decoded_addr_decoded_decoded, 96, 96) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_39 = bits(decoded_addr_decoded_decoded, 95, 95) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_40 = bits(decoded_addr_decoded_decoded, 94, 94) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_41 = bits(decoded_addr_decoded_decoded, 93, 93) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_42 = bits(decoded_addr_decoded_decoded, 92, 92) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_43 = bits(decoded_addr_decoded_decoded, 91, 91) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_44 = bits(decoded_addr_decoded_decoded, 90, 90) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_45 = bits(decoded_addr_decoded_decoded, 89, 89) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_46 = bits(decoded_addr_decoded_decoded, 88, 88) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_47 = bits(decoded_addr_decoded_decoded, 87, 87) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_48 = bits(decoded_addr_decoded_decoded, 86, 86) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_49 = bits(decoded_addr_decoded_decoded, 85, 85) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_50 = bits(decoded_addr_decoded_decoded, 84, 84) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_51 = bits(decoded_addr_decoded_decoded, 83, 83) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_52 = bits(decoded_addr_decoded_decoded, 82, 82) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_53 = bits(decoded_addr_decoded_decoded, 81, 81) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_54 = bits(decoded_addr_decoded_decoded, 80, 80) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_55 = bits(decoded_addr_decoded_decoded, 79, 79) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_56 = bits(decoded_addr_decoded_decoded, 78, 78) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_57 = bits(decoded_addr_decoded_decoded, 77, 77) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_58 = bits(decoded_addr_decoded_decoded, 76, 76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_59 = bits(decoded_addr_decoded_decoded, 75, 75) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_60 = bits(decoded_addr_decoded_decoded, 74, 74) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_61 = bits(decoded_addr_decoded_decoded, 73, 73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_62 = bits(decoded_addr_decoded_decoded, 72, 72) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_63 = bits(decoded_addr_decoded_decoded, 71, 71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_64 = bits(decoded_addr_decoded_decoded, 70, 70) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_65 = bits(decoded_addr_decoded_decoded, 69, 69) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_66 = bits(decoded_addr_decoded_decoded, 68, 68) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_67 = bits(decoded_addr_decoded_decoded, 67, 67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_68 = bits(decoded_addr_decoded_decoded, 66, 66) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_69 = bits(decoded_addr_decoded_decoded, 65, 65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_70 = bits(decoded_addr_decoded_decoded, 64, 64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_71 = bits(decoded_addr_decoded_decoded, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_72 = bits(decoded_addr_decoded_decoded, 62, 62) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_73 = bits(decoded_addr_decoded_decoded, 61, 61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_74 = bits(decoded_addr_decoded_decoded, 60, 60) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_75 = bits(decoded_addr_decoded_decoded, 59, 59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_76 = bits(decoded_addr_decoded_decoded, 58, 58) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_77 = bits(decoded_addr_decoded_decoded, 57, 57) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_78 = bits(decoded_addr_decoded_decoded, 56, 56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_79 = bits(decoded_addr_decoded_decoded, 55, 55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_80 = bits(decoded_addr_decoded_decoded, 54, 54) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_81 = bits(decoded_addr_decoded_decoded, 53, 53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_82 = bits(decoded_addr_decoded_decoded, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_83 = bits(decoded_addr_decoded_decoded, 51, 51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_84 = bits(decoded_addr_decoded_decoded, 50, 50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_85 = bits(decoded_addr_decoded_decoded, 49, 49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_86 = bits(decoded_addr_decoded_decoded, 48, 48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_87 = bits(decoded_addr_decoded_decoded, 47, 47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_88 = bits(decoded_addr_decoded_decoded, 46, 46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_89 = bits(decoded_addr_decoded_decoded, 45, 45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_90 = bits(decoded_addr_decoded_decoded, 44, 44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_91 = bits(decoded_addr_decoded_decoded, 43, 43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_92 = bits(decoded_addr_decoded_decoded, 42, 42) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_93 = bits(decoded_addr_decoded_decoded, 41, 41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_94 = bits(decoded_addr_decoded_decoded, 40, 40) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_95 = bits(decoded_addr_decoded_decoded, 39, 39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_96 = bits(decoded_addr_decoded_decoded, 38, 38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_97 = bits(decoded_addr_decoded_decoded, 37, 37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_98 = bits(decoded_addr_decoded_decoded, 36, 36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_99 = bits(decoded_addr_decoded_decoded, 35, 35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_100 = bits(decoded_addr_decoded_decoded, 34, 34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_101 = bits(decoded_addr_decoded_decoded, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_102 = bits(decoded_addr_decoded_decoded, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_103 = bits(decoded_addr_decoded_decoded, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_104 = bits(decoded_addr_decoded_decoded, 30, 30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_105 = bits(decoded_addr_decoded_decoded, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_106 = bits(decoded_addr_decoded_decoded, 28, 28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_107 = bits(decoded_addr_decoded_decoded, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_108 = bits(decoded_addr_decoded_decoded, 26, 26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_109 = bits(decoded_addr_decoded_decoded, 25, 25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_110 = bits(decoded_addr_decoded_decoded, 24, 24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_111 = bits(decoded_addr_decoded_decoded, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_112 = bits(decoded_addr_decoded_decoded, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_113 = bits(decoded_addr_decoded_decoded, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_114 = bits(decoded_addr_decoded_decoded, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_115 = bits(decoded_addr_decoded_decoded, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_116 = bits(decoded_addr_decoded_decoded, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_117 = bits(decoded_addr_decoded_decoded, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_118 = bits(decoded_addr_decoded_decoded, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_119 = bits(decoded_addr_decoded_decoded, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_120 = bits(decoded_addr_decoded_decoded, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_121 = bits(decoded_addr_decoded_decoded, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_122 = bits(decoded_addr_decoded_decoded, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_123 = bits(decoded_addr_decoded_decoded, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_124 = bits(decoded_addr_decoded_decoded, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_125 = bits(decoded_addr_decoded_decoded, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_126 = bits(decoded_addr_decoded_decoded, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_127 = bits(decoded_addr_decoded_decoded, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_128 = bits(decoded_addr_decoded_decoded, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_129 = bits(decoded_addr_decoded_decoded, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_130 = bits(decoded_addr_decoded_decoded, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_131 = bits(decoded_addr_decoded_decoded, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_132 = bits(decoded_addr_decoded_decoded, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_133 = bits(decoded_addr_decoded_decoded, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_decoded_134 = bits(decoded_addr_decoded_decoded, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node decoded_addr_85_2 = bits(decoded_addr_decoded_0, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_46_2 = bits(decoded_addr_decoded_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_9_2 = bits(decoded_addr_decoded_2, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_106_2 = bits(decoded_addr_decoded_3, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_82_2 = bits(decoded_addr_decoded_4, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_88_2 = bits(decoded_addr_decoded_5, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_61_2 = bits(decoded_addr_decoded_6, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_96_2 = bits(decoded_addr_decoded_7, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_65_2 = bits(decoded_addr_decoded_8, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_116_2 = bits(decoded_addr_decoded_9, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_119_2 = bits(decoded_addr_decoded_10, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_123_2 = bits(decoded_addr_decoded_11, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_24_2 = bits(decoded_addr_decoded_12, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_118_2 = bits(decoded_addr_decoded_13, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_40_2 = bits(decoded_addr_decoded_14, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_78_2 = bits(decoded_addr_decoded_15, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_48_2 = bits(decoded_addr_decoded_16, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_30_2 = bits(decoded_addr_decoded_17, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_58_2 = bits(decoded_addr_decoded_18, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_87_2 = bits(decoded_addr_decoded_19, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_117_2 = bits(decoded_addr_decoded_20, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_91_2 = bits(decoded_addr_decoded_21, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_109_2 = bits(decoded_addr_decoded_22, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_131_2 = bits(decoded_addr_decoded_23, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_15_2 = bits(decoded_addr_decoded_24, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_23_2 = bits(decoded_addr_decoded_25, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_72_2 = bits(decoded_addr_decoded_26, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_43_2 = bits(decoded_addr_decoded_27, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_130_2 = bits(decoded_addr_decoded_28, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_59_2 = bits(decoded_addr_decoded_29, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_99_2 = bits(decoded_addr_decoded_30, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_71_2 = bits(decoded_addr_decoded_31, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_26_2 = bits(decoded_addr_decoded_32, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_0_2 = bits(decoded_addr_decoded_33, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_50_2 = bits(decoded_addr_decoded_34, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_124_2 = bits(decoded_addr_decoded_35, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_113_2 = bits(decoded_addr_decoded_36, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_63_2 = bits(decoded_addr_decoded_37, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_104_2 = bits(decoded_addr_decoded_38, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_79_2 = bits(decoded_addr_decoded_39, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_101_2 = bits(decoded_addr_decoded_40, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_1_2 = bits(decoded_addr_decoded_41, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_14_2 = bits(decoded_addr_decoded_42, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_67_2 = bits(decoded_addr_decoded_43, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_33_2 = bits(decoded_addr_decoded_44, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_42_2 = bits(decoded_addr_decoded_45, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_97_2 = bits(decoded_addr_decoded_46, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_80_2 = bits(decoded_addr_decoded_47, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_70_2 = bits(decoded_addr_decoded_48, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_57_2 = bits(decoded_addr_decoded_49, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_93_2 = bits(decoded_addr_decoded_50, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_110_2 = bits(decoded_addr_decoded_51, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_21_2 = bits(decoded_addr_decoded_52, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_111_2 = bits(decoded_addr_decoded_53, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_22_2 = bits(decoded_addr_decoded_54, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_115_2 = bits(decoded_addr_decoded_55, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_6_2 = bits(decoded_addr_decoded_56, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_52_2 = bits(decoded_addr_decoded_57, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_66_2 = bits(decoded_addr_decoded_58, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_38_2 = bits(decoded_addr_decoded_59, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_100_2 = bits(decoded_addr_decoded_60, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_51_2 = bits(decoded_addr_decoded_61, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_81_2 = bits(decoded_addr_decoded_62, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_133_2 = bits(decoded_addr_decoded_63, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_13_2 = bits(decoded_addr_decoded_64, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_19_2 = bits(decoded_addr_decoded_65, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_28_2 = bits(decoded_addr_decoded_66, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_17_2 = bits(decoded_addr_decoded_67, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_120_2 = bits(decoded_addr_decoded_68, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_134_2 = bits(decoded_addr_decoded_69, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_41_2 = bits(decoded_addr_decoded_70, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_64_2 = bits(decoded_addr_decoded_71, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_90_2 = bits(decoded_addr_decoded_72, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_73_2 = bits(decoded_addr_decoded_73, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_37_2 = bits(decoded_addr_decoded_74, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_54_2 = bits(decoded_addr_decoded_75, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_108_2 = bits(decoded_addr_decoded_76, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_25_2 = bits(decoded_addr_decoded_77, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_5_2 = bits(decoded_addr_decoded_78, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_27_2 = bits(decoded_addr_decoded_79, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_129_2 = bits(decoded_addr_decoded_80, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_105_2 = bits(decoded_addr_decoded_81, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_53_2 = bits(decoded_addr_decoded_82, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_95_2 = bits(decoded_addr_decoded_83, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_77_2 = bits(decoded_addr_decoded_84, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_102_2 = bits(decoded_addr_decoded_85, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_62_2 = bits(decoded_addr_decoded_86, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_44_2 = bits(decoded_addr_decoded_87, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_132_2 = bits(decoded_addr_decoded_88, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_35_2 = bits(decoded_addr_decoded_89, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_47_2 = bits(decoded_addr_decoded_90, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_31_2 = bits(decoded_addr_decoded_91, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_68_2 = bits(decoded_addr_decoded_92, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_84_2 = bits(decoded_addr_decoded_93, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_4_2 = bits(decoded_addr_decoded_94, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_89_2 = bits(decoded_addr_decoded_95, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_107_2 = bits(decoded_addr_decoded_96, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_20_2 = bits(decoded_addr_decoded_97, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_125_2 = bits(decoded_addr_decoded_98, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_10_2 = bits(decoded_addr_decoded_99, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_121_2 = bits(decoded_addr_decoded_100, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_11_2 = bits(decoded_addr_decoded_101, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_55_2 = bits(decoded_addr_decoded_102, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_75_2 = bits(decoded_addr_decoded_103, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_39_2 = bits(decoded_addr_decoded_104, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_94_2 = bits(decoded_addr_decoded_105, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_49_2 = bits(decoded_addr_decoded_106, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_76_2 = bits(decoded_addr_decoded_107, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_128_2 = bits(decoded_addr_decoded_108, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_12_2 = bits(decoded_addr_decoded_109, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_2_2 = bits(decoded_addr_decoded_110, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_56_2 = bits(decoded_addr_decoded_111, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_127_2 = bits(decoded_addr_decoded_112, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_8_2 = bits(decoded_addr_decoded_113, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_92_2 = bits(decoded_addr_decoded_114, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_7_2 = bits(decoded_addr_decoded_115, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_112_2 = bits(decoded_addr_decoded_116, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_74_2 = bits(decoded_addr_decoded_117, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_45_2 = bits(decoded_addr_decoded_118, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_18_2 = bits(decoded_addr_decoded_119, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_122_2 = bits(decoded_addr_decoded_120, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_103_2 = bits(decoded_addr_decoded_121, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_36_2 = bits(decoded_addr_decoded_122, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_60_2 = bits(decoded_addr_decoded_123, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_98_2 = bits(decoded_addr_decoded_124, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_126_2 = bits(decoded_addr_decoded_125, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_29_2 = bits(decoded_addr_decoded_126, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_34_2 = bits(decoded_addr_decoded_127, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_69_2 = bits(decoded_addr_decoded_128, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_86_2 = bits(decoded_addr_decoded_129, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_16_2 = bits(decoded_addr_decoded_130, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_3_2 = bits(decoded_addr_decoded_131, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_32_2 = bits(decoded_addr_decoded_132, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_114_2 = bits(decoded_addr_decoded_133, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node decoded_addr_83_2 = bits(decoded_addr_decoded_134, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 856:93] node _wdata_T = bits(io.rw.cmd, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:13] node _wdata_T_1 = mux(_wdata_T, io.rw.rdata, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:9] node _wdata_T_2 = or(_wdata_T_1, io.rw.wdata) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:30] node _wdata_T_3 = bits(io.rw.cmd, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:49] node _wdata_T_4 = andr(_wdata_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:55] node _wdata_T_5 = mux(_wdata_T_4, io.rw.wdata, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:45] node _wdata_T_6 = not(_wdata_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:41] node wdata = and(_wdata_T_2, _wdata_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:39] node system_insn = eq(io.rw.cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 877:31] node _insn_T = shl(io.rw.addr, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 893:44] node insn = or(UInt<7>(0h73), _insn_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 893:30] wire decoded_plaInput : UInt<32> @[src/main/scala/chisel3/util/pla.scala 77:22] node decoded_invInputs = not(decoded_plaInput) @[src/main/scala/chisel3/util/pla.scala 78:21] wire decoded : UInt<9> @[src/main/scala/chisel3/util/pla.scala 81:23] node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_plaInput, 20, 20) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_2_2, decoded_andMatrixOutputs_andMatrixInput_3_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_2) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_3) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput, 22, 22) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_4) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_5) @[src/main/scala/chisel3/util/pla.scala 98:70] node _decoded_orMatrixOutputs_T = orr(decoded_andMatrixOutputs_3_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_orMatrixOutputs_T_1 = orr(decoded_andMatrixOutputs_4_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_orMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_2_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_orMatrixOutputs_T_4 = orr(decoded_andMatrixOutputs_1_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_orMatrixOutputs_T_5 = orr(decoded_andMatrixOutputs_5_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node decoded_orMatrixOutputs_lo_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_orMatrixOutputs_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_orMatrixOutputs_hi_lo = cat(_decoded_orMatrixOutputs_T_1, _decoded_orMatrixOutputs_T) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_orMatrixOutputs_hi_hi_hi = cat(_decoded_orMatrixOutputs_T_5, _decoded_orMatrixOutputs_T_4) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_orMatrixOutputs_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_3) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 124:31] node decoded_invMatrixOutputs_lo_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_invMatrixOutputs_lo_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_invMatrixOutputs_hi_lo = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_invMatrixOutputs_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] connect decoded, decoded_invMatrixOutputs @[src/main/scala/chisel3/util/pla.scala 129:13] connect decoded_plaInput, insn @[src/main/scala/chisel3/util/experimental/decode/decoder.scala 35:16] node _T_37 = bits(decoded, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_38 = bits(decoded, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_39 = bits(decoded, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_40 = bits(decoded, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_41 = bits(decoded, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_42 = bits(decoded, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_43 = bits(decoded, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_44 = bits(decoded, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_45 = bits(decoded, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_46 = bits(_T_37, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 894:88] node insn_call = and(system_insn, _T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 894:83] node _T_47 = bits(_T_38, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 894:88] node insn_break = and(system_insn, _T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 894:83] node _T_48 = bits(_T_39, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 894:88] node insn_ret = and(system_insn, _T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 894:83] node _T_49 = bits(_T_40, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 894:88] node insn_cease = and(system_insn, _T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 894:83] node _T_50 = bits(_T_41, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 894:88] node insn_wfi = and(system_insn, _T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 894:83] node _T_51 = bits(_T_42, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 894:88] node _T_52 = and(system_insn, _T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 894:83] node _T_53 = bits(_T_43, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 894:88] node _T_54 = and(system_insn, _T_53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 894:83] node _T_55 = bits(_T_44, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 894:88] node _T_56 = and(system_insn, _T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 894:83] node _T_57 = bits(_T_45, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 894:88] node _T_58 = and(system_insn, _T_57) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 894:83] node addr = bits(io.decode[0].inst, 31, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 898:27] wire decoded_plaInput_1 : UInt<32> @[src/main/scala/chisel3/util/pla.scala 77:22] node decoded_invInputs_1 = not(decoded_plaInput_1) @[src/main/scala/chisel3/util/pla.scala 78:21] wire decoded_1 : UInt<9> @[src/main/scala/chisel3/util/pla.scala 81:23] node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_invInputs_1, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs_1, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_invInputs_1, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs_1, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_invInputs_1, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_invInputs_1, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_invInputs_1, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_invInputs_1, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs_1, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs_1, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_invInputs_1, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs_1, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_11_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_andMatrixOutputs_andMatrixInput_7_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_8_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_5_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_2_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_5_2_1 = andr(_decoded_andMatrixOutputs_T_6) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_plaInput_1, 20, 20) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs_1, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_invInputs_1, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs_1, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs_1, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs_1, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_invInputs_1, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_invInputs_1, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_invInputs_1, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs_1, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs_1, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs_1, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_andMatrixOutputs_andMatrixInput_10_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_andMatrixOutputs_andMatrixInput_7_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_8_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_7) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_plaInput_1, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs_1, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_invInputs_1, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs_1, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_2_7, decoded_andMatrixOutputs_andMatrixInput_3_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_3_2_1 = andr(_decoded_andMatrixOutputs_T_8) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_invInputs_1, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs_1, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_invInputs_1, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_invInputs_1, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs_1, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_1, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_plaInput_1, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_plaInput_1, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_invInputs_1, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs_1, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_8_6, decoded_andMatrixOutputs_andMatrixInput_9_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_5_6, decoded_andMatrixOutputs_andMatrixInput_6_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_7_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_9) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_plaInput_1, 22, 22) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs_1, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_invInputs_1, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs_1, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs_1, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs_1, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_plaInput_1, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_plaInput_1, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_invInputs_1, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs_1, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_8_7, decoded_andMatrixOutputs_andMatrixInput_9_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_andMatrixOutputs_andMatrixInput_6_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_7_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_4_2_1 = andr(_decoded_andMatrixOutputs_T_10) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_plaInput_1, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_invInputs_1, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_11) @[src/main/scala/chisel3/util/pla.scala 98:70] node _decoded_orMatrixOutputs_T_6 = orr(decoded_andMatrixOutputs_3_2_1) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_orMatrixOutputs_T_7 = orr(decoded_andMatrixOutputs_4_2_1) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_orMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_0_2_1, decoded_andMatrixOutputs_2_2_1) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoded_orMatrixOutputs_T_9 = orr(_decoded_orMatrixOutputs_T_8) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_orMatrixOutputs_T_10 = orr(decoded_andMatrixOutputs_1_2_1) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_orMatrixOutputs_T_11 = orr(decoded_andMatrixOutputs_5_2_1) @[src/main/scala/chisel3/util/pla.scala 114:36] node decoded_orMatrixOutputs_lo_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_orMatrixOutputs_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_orMatrixOutputs_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_orMatrixOutputs_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_orMatrixOutputs_hi_lo_1 = cat(_decoded_orMatrixOutputs_T_7, _decoded_orMatrixOutputs_T_6) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_11, _decoded_orMatrixOutputs_T_10) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_9) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_orMatrixOutputs_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) @[src/main/scala/chisel3/util/pla.scala 102:36] node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs_1, 0, 0) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs_1, 1, 1) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs_1, 2, 2) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_1, 3, 3) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_1, 4, 4) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_1, 5, 5) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_1, 6, 6) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_1, 7, 7) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_1, 8, 8) @[src/main/scala/chisel3/util/pla.scala 124:31] node decoded_invMatrixOutputs_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_invMatrixOutputs_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_invMatrixOutputs_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) @[src/main/scala/chisel3/util/pla.scala 120:37] connect decoded_1, decoded_invMatrixOutputs_1 @[src/main/scala/chisel3/util/pla.scala 129:13] connect decoded_plaInput_1, io.decode[0].inst @[src/main/scala/chisel3/util/experimental/decode/decoder.scala 35:16] node _T_59 = bits(decoded_1, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_60 = bits(decoded_1, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_61 = bits(decoded_1, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_62 = bits(decoded_1, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_63 = bits(decoded_1, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_64 = bits(decoded_1, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_65 = bits(decoded_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_66 = bits(decoded_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_67 = bits(decoded_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_68 = bits(_T_59, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 904:82] node is_break = bits(_T_60, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 904:82] node is_ret = bits(_T_61, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 904:82] node _T_69 = bits(_T_62, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 904:82] node is_wfi = bits(_T_63, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 904:82] node is_sfence = bits(_T_64, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 904:82] node is_hfence_vvma = bits(_T_65, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 904:82] node is_hfence_gvma = bits(_T_66, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 904:82] node is_hlsv = bits(_T_67, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 904:82] node _is_counter_T = geq(addr, UInt<12>(0hc00)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 214:47] node _is_counter_T_1 = lt(addr, UInt<12>(0hc20)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 214:60] node _is_counter_T_2 = and(_is_counter_T, _is_counter_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 214:55] node _is_counter_T_3 = geq(addr, UInt<12>(0hc80)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 214:47] node _is_counter_T_4 = lt(addr, UInt<12>(0hca0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 214:60] node _is_counter_T_5 = and(_is_counter_T_3, _is_counter_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 214:55] node is_counter = or(_is_counter_T_2, _is_counter_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 905:81] node _allow_wfi_T = gt(reg_mstatus.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 907:61] node _allow_wfi_T_1 = or(UInt<1>(0h1), _allow_wfi_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 907:42] node _allow_wfi_T_2 = eq(reg_mstatus.tw, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 907:74] node _allow_wfi_T_3 = eq(reg_mstatus.v, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 907:94] node _allow_wfi_T_4 = eq(reg_hstatus.vtw, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 907:112] node _allow_wfi_T_5 = or(_allow_wfi_T_3, _allow_wfi_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 907:109] node _allow_wfi_T_6 = and(_allow_wfi_T_2, _allow_wfi_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 907:90] node allow_wfi = or(_allow_wfi_T_1, _allow_wfi_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 907:71] node _allow_sfence_vma_T = gt(reg_mstatus.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 908:60] node _allow_sfence_vma_T_1 = or(UInt<1>(0h1), _allow_sfence_vma_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 908:41] node _allow_sfence_vma_T_2 = mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 908:77] node _allow_sfence_vma_T_3 = eq(_allow_sfence_vma_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 908:73] node allow_sfence_vma = or(_allow_sfence_vma_T_1, _allow_sfence_vma_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 908:70] node _allow_hfence_vvma_T = eq(reg_mstatus.v, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 909:53] node _allow_hfence_vvma_T_1 = geq(reg_mstatus.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 909:88] node _allow_hfence_vvma_T_2 = and(_allow_hfence_vvma_T, _allow_hfence_vvma_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 909:68] node allow_hfence_vvma = or(UInt<1>(0h1), _allow_hfence_vvma_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 909:50] node _allow_hlsv_T = eq(reg_mstatus.v, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 910:46] node _allow_hlsv_T_1 = geq(reg_mstatus.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 910:81] node _allow_hlsv_T_2 = or(_allow_hlsv_T_1, reg_hstatus.hu) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 910:92] node _allow_hlsv_T_3 = and(_allow_hlsv_T, _allow_hlsv_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 910:61] node allow_hlsv = or(UInt<1>(0h1), _allow_hlsv_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 910:43] node _allow_sret_T = gt(reg_mstatus.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 911:62] node _allow_sret_T_1 = or(UInt<1>(0h1), _allow_sret_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 911:43] node _allow_sret_T_2 = mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 911:79] node _allow_sret_T_3 = eq(_allow_sret_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 911:75] node allow_sret = or(_allow_sret_T_1, _allow_sret_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 911:72] node counter_addr = bits(addr, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 912:28] node _allow_counter_T = gt(reg_mstatus.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 913:42] node _allow_counter_T_1 = dshr(read_mcounteren, counter_addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 913:70] node _allow_counter_T_2 = bits(_allow_counter_T_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 913:70] node _allow_counter_T_3 = or(_allow_counter_T, _allow_counter_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 913:52] node _allow_counter_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 914:8] node _allow_counter_T_5 = geq(reg_mstatus.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 914:46] node _allow_counter_T_6 = or(_allow_counter_T_4, _allow_counter_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 914:27] node _allow_counter_T_7 = dshr(read_scounteren, counter_addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 914:75] node _allow_counter_T_8 = bits(_allow_counter_T_7, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 914:75] node _allow_counter_T_9 = or(_allow_counter_T_6, _allow_counter_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 914:57] node _allow_counter_T_10 = and(_allow_counter_T_3, _allow_counter_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 913:86] node _allow_counter_T_11 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 915:8] node _allow_counter_T_12 = eq(reg_mstatus.v, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 915:30] node _allow_counter_T_13 = or(_allow_counter_T_11, _allow_counter_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 915:27] node _allow_counter_T_14 = dshr(read_hcounteren, counter_addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 915:63] node _allow_counter_T_15 = bits(_allow_counter_T_14, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 915:63] node _allow_counter_T_16 = or(_allow_counter_T_13, _allow_counter_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 915:45] node allow_counter = and(_allow_counter_T_10, _allow_counter_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 914:91] node _io_decode_0_fp_illegal_T = eq(io.status.fs, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 916:39] node _io_decode_0_fp_illegal_T_1 = eq(reg_vsstatus.fs, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 916:83] node _io_decode_0_fp_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_fp_illegal_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 916:64] node _io_decode_0_fp_illegal_T_3 = or(_io_decode_0_fp_illegal_T, _io_decode_0_fp_illegal_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 916:47] node _io_decode_0_fp_illegal_T_4 = bits(reg_misa, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 916:103] node _io_decode_0_fp_illegal_T_5 = eq(_io_decode_0_fp_illegal_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 916:94] node _io_decode_0_fp_illegal_T_6 = or(_io_decode_0_fp_illegal_T_3, _io_decode_0_fp_illegal_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 916:91] connect io.decode[0].fp_illegal, _io_decode_0_fp_illegal_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 916:23] node _io_decode_0_vector_illegal_T = eq(io.status.vs, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 917:43] node _io_decode_0_vector_illegal_T_1 = eq(reg_vsstatus.vs, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 917:87] node _io_decode_0_vector_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_vector_illegal_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 917:68] node _io_decode_0_vector_illegal_T_3 = or(_io_decode_0_vector_illegal_T, _io_decode_0_vector_illegal_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 917:51] node _io_decode_0_vector_illegal_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 917:98] node _io_decode_0_vector_illegal_T_5 = or(_io_decode_0_vector_illegal_T_3, _io_decode_0_vector_illegal_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 917:95] connect io.decode[0].vector_illegal, _io_decode_0_vector_illegal_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 917:27] wire io_decode_0_fp_csr_plaInput : UInt<12> @[src/main/scala/chisel3/util/pla.scala 77:22] node io_decode_0_fp_csr_invInputs = not(io_decode_0_fp_csr_plaInput) @[src/main/scala/chisel3/util/pla.scala 78:21] wire io_decode_0_fp_csr_plaOutput : UInt<1> @[src/main/scala/chisel3/util/pla.scala 81:23] node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_0_fp_csr_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_0_fp_csr_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_0_fp_csr_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node io_decode_0_fp_csr_andMatrixOutputs_hi = cat(io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node _io_decode_0_fp_csr_andMatrixOutputs_T = cat(io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node io_decode_0_fp_csr_andMatrixOutputs_0_2 = andr(_io_decode_0_fp_csr_andMatrixOutputs_T) @[src/main/scala/chisel3/util/pla.scala 98:70] node io_decode_0_fp_csr_orMatrixOutputs = orr(io_decode_0_fp_csr_andMatrixOutputs_0_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node io_decode_0_fp_csr_invMatrixOutputs = bits(io_decode_0_fp_csr_orMatrixOutputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 124:31] connect io_decode_0_fp_csr_plaOutput, io_decode_0_fp_csr_invMatrixOutputs @[src/main/scala/chisel3/util/pla.scala 129:13] connect io_decode_0_fp_csr_plaInput, addr @[src/main/scala/chisel3/util/experimental/decode/decoder.scala 35:16] node _io_decode_0_fp_csr_T = bits(io_decode_0_fp_csr_plaOutput, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 55:116] connect io.decode[0].fp_csr, _io_decode_0_fp_csr_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 918:19] wire io_decode_0_vector_csr_plaInput : UInt<12> @[src/main/scala/chisel3/util/pla.scala 77:22] node io_decode_0_vector_csr_invInputs = not(io_decode_0_vector_csr_plaInput) @[src/main/scala/chisel3/util/pla.scala 78:21] wire io_decode_0_vector_csr_plaOutput : UInt<1> @[src/main/scala/chisel3/util/pla.scala 81:23] connect io_decode_0_vector_csr_plaOutput, UInt<1>(0h0) @[src/main/scala/chisel3/util/pla.scala 129:13] connect io_decode_0_vector_csr_plaInput, addr @[src/main/scala/chisel3/util/experimental/decode/decoder.scala 35:16] node _io_decode_0_vector_csr_T = bits(io_decode_0_vector_csr_plaOutput, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 55:116] connect io.decode[0].vector_csr, _io_decode_0_vector_csr_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 919:23] node _io_decode_0_rocc_illegal_T = eq(io.status.xs, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 920:41] node _io_decode_0_rocc_illegal_T_1 = eq(reg_vsstatus.xs, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 920:85] node _io_decode_0_rocc_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_rocc_illegal_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 920:66] node _io_decode_0_rocc_illegal_T_3 = or(_io_decode_0_rocc_illegal_T, _io_decode_0_rocc_illegal_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 920:49] node _io_decode_0_rocc_illegal_T_4 = bits(reg_misa, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 920:105] node _io_decode_0_rocc_illegal_T_5 = eq(_io_decode_0_rocc_illegal_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 920:96] node _io_decode_0_rocc_illegal_T_6 = or(_io_decode_0_rocc_illegal_T_3, _io_decode_0_rocc_illegal_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 920:93] connect io.decode[0].rocc_illegal, _io_decode_0_rocc_illegal_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 920:25] node _csr_addr_legal_T = bits(addr, 9, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 190:36] node _csr_addr_legal_T_1 = geq(reg_mstatus.prv, _csr_addr_legal_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 921:42] node _csr_addr_legal_T_2 = eq(reg_mstatus.v, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 922:28] node _csr_addr_legal_T_3 = and(UInt<1>(0h0), _csr_addr_legal_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 922:25] node _csr_addr_legal_T_4 = eq(reg_mstatus.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 922:62] node _csr_addr_legal_T_5 = and(_csr_addr_legal_T_3, _csr_addr_legal_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 922:43] node _csr_addr_legal_T_6 = bits(addr, 9, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 190:36] node _csr_addr_legal_T_7 = eq(_csr_addr_legal_T_6, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 922:92] node _csr_addr_legal_T_8 = and(_csr_addr_legal_T_5, _csr_addr_legal_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 922:74] node csr_addr_legal = or(_csr_addr_legal_T_1, _csr_addr_legal_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 921:60] node _csr_exists_T = eq(addr, UInt<11>(0h7a0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_1 = eq(addr, UInt<11>(0h7a1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_2 = eq(addr, UInt<11>(0h7a2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_3 = eq(addr, UInt<11>(0h7a3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_4 = eq(addr, UInt<10>(0h301)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_5 = eq(addr, UInt<10>(0h300)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_6 = eq(addr, UInt<10>(0h305)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_7 = eq(addr, UInt<10>(0h344)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_8 = eq(addr, UInt<10>(0h304)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_9 = eq(addr, UInt<10>(0h340)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_10 = eq(addr, UInt<10>(0h341)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_11 = eq(addr, UInt<10>(0h343)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_12 = eq(addr, UInt<10>(0h342)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_13 = eq(addr, UInt<12>(0hf14)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_14 = eq(addr, UInt<11>(0h7b0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_15 = eq(addr, UInt<11>(0h7b1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_16 = eq(addr, UInt<11>(0h7b2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_17 = eq(addr, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_18 = eq(addr, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_19 = eq(addr, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_20 = eq(addr, UInt<10>(0h320)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_21 = eq(addr, UInt<12>(0hb00)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_22 = eq(addr, UInt<12>(0hb02)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_23 = eq(addr, UInt<10>(0h323)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_24 = eq(addr, UInt<12>(0hb03)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_25 = eq(addr, UInt<12>(0hc03)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_26 = eq(addr, UInt<10>(0h324)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_27 = eq(addr, UInt<12>(0hb04)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_28 = eq(addr, UInt<12>(0hc04)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_29 = eq(addr, UInt<10>(0h325)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_30 = eq(addr, UInt<12>(0hb05)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_31 = eq(addr, UInt<12>(0hc05)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_32 = eq(addr, UInt<10>(0h326)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_33 = eq(addr, UInt<12>(0hb06)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_34 = eq(addr, UInt<12>(0hc06)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_35 = eq(addr, UInt<10>(0h327)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_36 = eq(addr, UInt<12>(0hb07)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_37 = eq(addr, UInt<12>(0hc07)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_38 = eq(addr, UInt<10>(0h328)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_39 = eq(addr, UInt<12>(0hb08)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_40 = eq(addr, UInt<12>(0hc08)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_41 = eq(addr, UInt<10>(0h329)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_42 = eq(addr, UInt<12>(0hb09)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_43 = eq(addr, UInt<12>(0hc09)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_44 = eq(addr, UInt<10>(0h32a)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_45 = eq(addr, UInt<12>(0hb0a)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_46 = eq(addr, UInt<12>(0hc0a)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_47 = eq(addr, UInt<10>(0h32b)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_48 = eq(addr, UInt<12>(0hb0b)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_49 = eq(addr, UInt<12>(0hc0b)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_50 = eq(addr, UInt<10>(0h32c)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_51 = eq(addr, UInt<12>(0hb0c)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_52 = eq(addr, UInt<12>(0hc0c)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_53 = eq(addr, UInt<10>(0h32d)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_54 = eq(addr, UInt<12>(0hb0d)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_55 = eq(addr, UInt<12>(0hc0d)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_56 = eq(addr, UInt<10>(0h32e)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_57 = eq(addr, UInt<12>(0hb0e)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_58 = eq(addr, UInt<12>(0hc0e)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_59 = eq(addr, UInt<10>(0h32f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_60 = eq(addr, UInt<12>(0hb0f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_61 = eq(addr, UInt<12>(0hc0f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_62 = eq(addr, UInt<10>(0h330)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_63 = eq(addr, UInt<12>(0hb10)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_64 = eq(addr, UInt<12>(0hc10)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_65 = eq(addr, UInt<10>(0h331)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_66 = eq(addr, UInt<12>(0hb11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_67 = eq(addr, UInt<12>(0hc11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_68 = eq(addr, UInt<10>(0h332)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_69 = eq(addr, UInt<12>(0hb12)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_70 = eq(addr, UInt<12>(0hc12)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_71 = eq(addr, UInt<10>(0h333)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_72 = eq(addr, UInt<12>(0hb13)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_73 = eq(addr, UInt<12>(0hc13)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_74 = eq(addr, UInt<10>(0h334)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_75 = eq(addr, UInt<12>(0hb14)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_76 = eq(addr, UInt<12>(0hc14)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_77 = eq(addr, UInt<10>(0h335)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_78 = eq(addr, UInt<12>(0hb15)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_79 = eq(addr, UInt<12>(0hc15)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_80 = eq(addr, UInt<10>(0h336)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_81 = eq(addr, UInt<12>(0hb16)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_82 = eq(addr, UInt<12>(0hc16)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_83 = eq(addr, UInt<10>(0h337)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_84 = eq(addr, UInt<12>(0hb17)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_85 = eq(addr, UInt<12>(0hc17)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_86 = eq(addr, UInt<10>(0h338)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_87 = eq(addr, UInt<12>(0hb18)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_88 = eq(addr, UInt<12>(0hc18)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_89 = eq(addr, UInt<10>(0h339)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_90 = eq(addr, UInt<12>(0hb19)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_91 = eq(addr, UInt<12>(0hc19)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_92 = eq(addr, UInt<10>(0h33a)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_93 = eq(addr, UInt<12>(0hb1a)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_94 = eq(addr, UInt<12>(0hc1a)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_95 = eq(addr, UInt<10>(0h33b)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_96 = eq(addr, UInt<12>(0hb1b)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_97 = eq(addr, UInt<12>(0hc1b)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_98 = eq(addr, UInt<10>(0h33c)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_99 = eq(addr, UInt<12>(0hb1c)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_100 = eq(addr, UInt<12>(0hc1c)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_101 = eq(addr, UInt<10>(0h33d)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_102 = eq(addr, UInt<12>(0hb1d)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_103 = eq(addr, UInt<12>(0hc1d)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_104 = eq(addr, UInt<10>(0h33e)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_105 = eq(addr, UInt<12>(0hb1e)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_106 = eq(addr, UInt<12>(0hc1e)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_107 = eq(addr, UInt<10>(0h33f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_108 = eq(addr, UInt<12>(0hb1f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_109 = eq(addr, UInt<12>(0hc1f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_110 = eq(addr, UInt<12>(0hc00)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_111 = eq(addr, UInt<12>(0hc02)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_112 = eq(addr, UInt<10>(0h3a0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_113 = eq(addr, UInt<10>(0h3a2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_114 = eq(addr, UInt<10>(0h3b0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_115 = eq(addr, UInt<10>(0h3b1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_116 = eq(addr, UInt<10>(0h3b2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_117 = eq(addr, UInt<10>(0h3b3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_118 = eq(addr, UInt<10>(0h3b4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_119 = eq(addr, UInt<10>(0h3b5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_120 = eq(addr, UInt<10>(0h3b6)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_121 = eq(addr, UInt<10>(0h3b7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_122 = eq(addr, UInt<10>(0h3b8)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_123 = eq(addr, UInt<10>(0h3b9)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_124 = eq(addr, UInt<10>(0h3ba)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_125 = eq(addr, UInt<10>(0h3bb)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_126 = eq(addr, UInt<10>(0h3bc)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_127 = eq(addr, UInt<10>(0h3bd)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_128 = eq(addr, UInt<10>(0h3be)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_129 = eq(addr, UInt<10>(0h3bf)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_130 = eq(addr, UInt<11>(0h7c1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_131 = eq(addr, UInt<12>(0hf12)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_132 = eq(addr, UInt<12>(0hf11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_133 = eq(addr, UInt<12>(0hf13)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_134 = eq(addr, UInt<12>(0hf15)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:93] node _csr_exists_T_135 = or(_csr_exists_T, _csr_exists_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_136 = or(_csr_exists_T_135, _csr_exists_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_137 = or(_csr_exists_T_136, _csr_exists_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_138 = or(_csr_exists_T_137, _csr_exists_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_139 = or(_csr_exists_T_138, _csr_exists_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_140 = or(_csr_exists_T_139, _csr_exists_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_141 = or(_csr_exists_T_140, _csr_exists_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_142 = or(_csr_exists_T_141, _csr_exists_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_143 = or(_csr_exists_T_142, _csr_exists_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_144 = or(_csr_exists_T_143, _csr_exists_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_145 = or(_csr_exists_T_144, _csr_exists_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_146 = or(_csr_exists_T_145, _csr_exists_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_147 = or(_csr_exists_T_146, _csr_exists_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_148 = or(_csr_exists_T_147, _csr_exists_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_149 = or(_csr_exists_T_148, _csr_exists_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_150 = or(_csr_exists_T_149, _csr_exists_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_151 = or(_csr_exists_T_150, _csr_exists_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_152 = or(_csr_exists_T_151, _csr_exists_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_153 = or(_csr_exists_T_152, _csr_exists_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_154 = or(_csr_exists_T_153, _csr_exists_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_155 = or(_csr_exists_T_154, _csr_exists_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_156 = or(_csr_exists_T_155, _csr_exists_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_157 = or(_csr_exists_T_156, _csr_exists_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_158 = or(_csr_exists_T_157, _csr_exists_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_159 = or(_csr_exists_T_158, _csr_exists_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_160 = or(_csr_exists_T_159, _csr_exists_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_161 = or(_csr_exists_T_160, _csr_exists_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_162 = or(_csr_exists_T_161, _csr_exists_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_163 = or(_csr_exists_T_162, _csr_exists_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_164 = or(_csr_exists_T_163, _csr_exists_T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_165 = or(_csr_exists_T_164, _csr_exists_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_166 = or(_csr_exists_T_165, _csr_exists_T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_167 = or(_csr_exists_T_166, _csr_exists_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_168 = or(_csr_exists_T_167, _csr_exists_T_34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_169 = or(_csr_exists_T_168, _csr_exists_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_170 = or(_csr_exists_T_169, _csr_exists_T_36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_171 = or(_csr_exists_T_170, _csr_exists_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_172 = or(_csr_exists_T_171, _csr_exists_T_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_173 = or(_csr_exists_T_172, _csr_exists_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_174 = or(_csr_exists_T_173, _csr_exists_T_40) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_175 = or(_csr_exists_T_174, _csr_exists_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_176 = or(_csr_exists_T_175, _csr_exists_T_42) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_177 = or(_csr_exists_T_176, _csr_exists_T_43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_178 = or(_csr_exists_T_177, _csr_exists_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_179 = or(_csr_exists_T_178, _csr_exists_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_180 = or(_csr_exists_T_179, _csr_exists_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_181 = or(_csr_exists_T_180, _csr_exists_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_182 = or(_csr_exists_T_181, _csr_exists_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_183 = or(_csr_exists_T_182, _csr_exists_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_184 = or(_csr_exists_T_183, _csr_exists_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_185 = or(_csr_exists_T_184, _csr_exists_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_186 = or(_csr_exists_T_185, _csr_exists_T_52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_187 = or(_csr_exists_T_186, _csr_exists_T_53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_188 = or(_csr_exists_T_187, _csr_exists_T_54) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_189 = or(_csr_exists_T_188, _csr_exists_T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_190 = or(_csr_exists_T_189, _csr_exists_T_56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_191 = or(_csr_exists_T_190, _csr_exists_T_57) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_192 = or(_csr_exists_T_191, _csr_exists_T_58) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_193 = or(_csr_exists_T_192, _csr_exists_T_59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_194 = or(_csr_exists_T_193, _csr_exists_T_60) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_195 = or(_csr_exists_T_194, _csr_exists_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_196 = or(_csr_exists_T_195, _csr_exists_T_62) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_197 = or(_csr_exists_T_196, _csr_exists_T_63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_198 = or(_csr_exists_T_197, _csr_exists_T_64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_199 = or(_csr_exists_T_198, _csr_exists_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_200 = or(_csr_exists_T_199, _csr_exists_T_66) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_201 = or(_csr_exists_T_200, _csr_exists_T_67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_202 = or(_csr_exists_T_201, _csr_exists_T_68) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_203 = or(_csr_exists_T_202, _csr_exists_T_69) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_204 = or(_csr_exists_T_203, _csr_exists_T_70) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_205 = or(_csr_exists_T_204, _csr_exists_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_206 = or(_csr_exists_T_205, _csr_exists_T_72) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_207 = or(_csr_exists_T_206, _csr_exists_T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_208 = or(_csr_exists_T_207, _csr_exists_T_74) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_209 = or(_csr_exists_T_208, _csr_exists_T_75) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_210 = or(_csr_exists_T_209, _csr_exists_T_76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_211 = or(_csr_exists_T_210, _csr_exists_T_77) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_212 = or(_csr_exists_T_211, _csr_exists_T_78) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_213 = or(_csr_exists_T_212, _csr_exists_T_79) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_214 = or(_csr_exists_T_213, _csr_exists_T_80) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_215 = or(_csr_exists_T_214, _csr_exists_T_81) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_216 = or(_csr_exists_T_215, _csr_exists_T_82) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_217 = or(_csr_exists_T_216, _csr_exists_T_83) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_218 = or(_csr_exists_T_217, _csr_exists_T_84) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_219 = or(_csr_exists_T_218, _csr_exists_T_85) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_220 = or(_csr_exists_T_219, _csr_exists_T_86) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_221 = or(_csr_exists_T_220, _csr_exists_T_87) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_222 = or(_csr_exists_T_221, _csr_exists_T_88) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_223 = or(_csr_exists_T_222, _csr_exists_T_89) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_224 = or(_csr_exists_T_223, _csr_exists_T_90) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_225 = or(_csr_exists_T_224, _csr_exists_T_91) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_226 = or(_csr_exists_T_225, _csr_exists_T_92) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_227 = or(_csr_exists_T_226, _csr_exists_T_93) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_228 = or(_csr_exists_T_227, _csr_exists_T_94) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_229 = or(_csr_exists_T_228, _csr_exists_T_95) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_230 = or(_csr_exists_T_229, _csr_exists_T_96) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_231 = or(_csr_exists_T_230, _csr_exists_T_97) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_232 = or(_csr_exists_T_231, _csr_exists_T_98) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_233 = or(_csr_exists_T_232, _csr_exists_T_99) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_234 = or(_csr_exists_T_233, _csr_exists_T_100) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_235 = or(_csr_exists_T_234, _csr_exists_T_101) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_236 = or(_csr_exists_T_235, _csr_exists_T_102) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_237 = or(_csr_exists_T_236, _csr_exists_T_103) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_238 = or(_csr_exists_T_237, _csr_exists_T_104) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_239 = or(_csr_exists_T_238, _csr_exists_T_105) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_240 = or(_csr_exists_T_239, _csr_exists_T_106) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_241 = or(_csr_exists_T_240, _csr_exists_T_107) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_242 = or(_csr_exists_T_241, _csr_exists_T_108) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_243 = or(_csr_exists_T_242, _csr_exists_T_109) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_244 = or(_csr_exists_T_243, _csr_exists_T_110) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_245 = or(_csr_exists_T_244, _csr_exists_T_111) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_246 = or(_csr_exists_T_245, _csr_exists_T_112) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_247 = or(_csr_exists_T_246, _csr_exists_T_113) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_248 = or(_csr_exists_T_247, _csr_exists_T_114) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_249 = or(_csr_exists_T_248, _csr_exists_T_115) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_250 = or(_csr_exists_T_249, _csr_exists_T_116) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_251 = or(_csr_exists_T_250, _csr_exists_T_117) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_252 = or(_csr_exists_T_251, _csr_exists_T_118) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_253 = or(_csr_exists_T_252, _csr_exists_T_119) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_254 = or(_csr_exists_T_253, _csr_exists_T_120) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_255 = or(_csr_exists_T_254, _csr_exists_T_121) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_256 = or(_csr_exists_T_255, _csr_exists_T_122) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_257 = or(_csr_exists_T_256, _csr_exists_T_123) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_258 = or(_csr_exists_T_257, _csr_exists_T_124) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_259 = or(_csr_exists_T_258, _csr_exists_T_125) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_260 = or(_csr_exists_T_259, _csr_exists_T_126) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_261 = or(_csr_exists_T_260, _csr_exists_T_127) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_262 = or(_csr_exists_T_261, _csr_exists_T_128) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_263 = or(_csr_exists_T_262, _csr_exists_T_129) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_264 = or(_csr_exists_T_263, _csr_exists_T_130) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_265 = or(_csr_exists_T_264, _csr_exists_T_131) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_266 = or(_csr_exists_T_265, _csr_exists_T_132) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _csr_exists_T_267 = or(_csr_exists_T_266, _csr_exists_T_133) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node csr_exists = or(_csr_exists_T_267, _csr_exists_T_134) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 900:111] node _io_decode_0_read_illegal_T = eq(csr_addr_legal, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 924:28] node _io_decode_0_read_illegal_T_1 = eq(csr_exists, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 925:7] node _io_decode_0_read_illegal_T_2 = or(_io_decode_0_read_illegal_T, _io_decode_0_read_illegal_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 924:44] node _io_decode_0_read_illegal_T_3 = eq(addr, UInt<9>(0h180)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 926:14] node _io_decode_0_read_illegal_T_4 = eq(addr, UInt<11>(0h680)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 926:38] node _io_decode_0_read_illegal_T_5 = or(_io_decode_0_read_illegal_T_3, _io_decode_0_read_illegal_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 926:30] node _io_decode_0_read_illegal_T_6 = eq(allow_sfence_vma, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 926:59] node _io_decode_0_read_illegal_T_7 = and(_io_decode_0_read_illegal_T_5, _io_decode_0_read_illegal_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 926:56] node _io_decode_0_read_illegal_T_8 = or(_io_decode_0_read_illegal_T_2, _io_decode_0_read_illegal_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 925:19] node _io_decode_0_read_illegal_T_9 = eq(allow_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 927:21] node _io_decode_0_read_illegal_T_10 = and(is_counter, _io_decode_0_read_illegal_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 927:18] node _io_decode_0_read_illegal_T_11 = or(_io_decode_0_read_illegal_T_8, _io_decode_0_read_illegal_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 926:78] wire io_decode_0_read_illegal_plaInput : UInt<12> @[src/main/scala/chisel3/util/pla.scala 77:22] node io_decode_0_read_illegal_invInputs = not(io_decode_0_read_illegal_plaInput) @[src/main/scala/chisel3/util/pla.scala 78:21] wire io_decode_0_read_illegal_plaOutput : UInt<1> @[src/main/scala/chisel3/util/pla.scala 81:23] node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_0_read_illegal_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_0_read_illegal_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_0_read_illegal_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_0_read_illegal_plaInput, 7, 7) @[src/main/scala/chisel3/util/pla.scala 90:45] node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = bits(io_decode_0_read_illegal_plaInput, 8, 8) @[src/main/scala/chisel3/util/pla.scala 90:45] node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = bits(io_decode_0_read_illegal_plaInput, 9, 9) @[src/main/scala/chisel3/util/pla.scala 90:45] node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = bits(io_decode_0_read_illegal_plaInput, 10, 10) @[src/main/scala/chisel3/util/pla.scala 90:45] node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = bits(io_decode_0_read_illegal_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node io_decode_0_read_illegal_andMatrixOutputs_lo_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node io_decode_0_read_illegal_andMatrixOutputs_lo_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node io_decode_0_read_illegal_andMatrixOutputs_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node io_decode_0_read_illegal_andMatrixOutputs_hi_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node io_decode_0_read_illegal_andMatrixOutputs_hi_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node io_decode_0_read_illegal_andMatrixOutputs_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node _io_decode_0_read_illegal_andMatrixOutputs_T = cat(io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node io_decode_0_read_illegal_andMatrixOutputs_0_2 = andr(_io_decode_0_read_illegal_andMatrixOutputs_T) @[src/main/scala/chisel3/util/pla.scala 98:70] node io_decode_0_read_illegal_orMatrixOutputs = orr(io_decode_0_read_illegal_andMatrixOutputs_0_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node io_decode_0_read_illegal_invMatrixOutputs = bits(io_decode_0_read_illegal_orMatrixOutputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 124:31] connect io_decode_0_read_illegal_plaOutput, io_decode_0_read_illegal_invMatrixOutputs @[src/main/scala/chisel3/util/pla.scala 129:13] connect io_decode_0_read_illegal_plaInput, addr @[src/main/scala/chisel3/util/experimental/decode/decoder.scala 35:16] node _io_decode_0_read_illegal_T_12 = bits(io_decode_0_read_illegal_plaOutput, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 55:116] node _io_decode_0_read_illegal_T_13 = eq(reg_debug, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 928:45] node _io_decode_0_read_illegal_T_14 = and(_io_decode_0_read_illegal_T_12, _io_decode_0_read_illegal_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 928:42] node _io_decode_0_read_illegal_T_15 = or(_io_decode_0_read_illegal_T_11, _io_decode_0_read_illegal_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 927:36] wire io_decode_0_read_illegal_plaInput_1 : UInt<12> @[src/main/scala/chisel3/util/pla.scala 77:22] node io_decode_0_read_illegal_invInputs_1 = not(io_decode_0_read_illegal_plaInput_1) @[src/main/scala/chisel3/util/pla.scala 78:21] wire io_decode_0_read_illegal_plaOutput_1 : UInt<1> @[src/main/scala/chisel3/util/pla.scala 81:23] connect io_decode_0_read_illegal_plaOutput_1, UInt<1>(0h0) @[src/main/scala/chisel3/util/pla.scala 129:13] connect io_decode_0_read_illegal_plaInput_1, addr @[src/main/scala/chisel3/util/experimental/decode/decoder.scala 35:16] node _io_decode_0_read_illegal_T_16 = bits(io_decode_0_read_illegal_plaOutput_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 55:116] node _io_decode_0_read_illegal_T_17 = and(_io_decode_0_read_illegal_T_16, io.decode[0].vector_illegal) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 929:43] node _io_decode_0_read_illegal_T_18 = or(_io_decode_0_read_illegal_T_15, _io_decode_0_read_illegal_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 928:56] node _io_decode_0_read_illegal_T_19 = and(io.decode[0].fp_csr, io.decode[0].fp_illegal) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 930:21] node _io_decode_0_read_illegal_T_20 = or(_io_decode_0_read_illegal_T_18, _io_decode_0_read_illegal_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 929:68] connect io.decode[0].read_illegal, _io_decode_0_read_illegal_T_20 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 924:25] node _io_decode_0_write_illegal_T = bits(addr, 11, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 931:33] node _io_decode_0_write_illegal_T_1 = andr(_io_decode_0_write_illegal_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 931:41] connect io.decode[0].write_illegal, _io_decode_0_write_illegal_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 931:26] node _io_decode_0_write_flush_addr_m_T = shl(UInt<2>(0h3), 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 933:36] node io_decode_0_write_flush_addr_m = or(addr, _io_decode_0_write_flush_addr_m_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 933:25] node _io_decode_0_write_flush_T = geq(io_decode_0_write_flush_addr_m, UInt<10>(0h340)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 934:16] node _io_decode_0_write_flush_T_1 = leq(io_decode_0_write_flush_addr_m, UInt<10>(0h343)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 934:45] node _io_decode_0_write_flush_T_2 = and(_io_decode_0_write_flush_T, _io_decode_0_write_flush_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 934:35] node _io_decode_0_write_flush_T_3 = eq(_io_decode_0_write_flush_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 934:7] connect io.decode[0].write_flush, _io_decode_0_write_flush_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 932:24] node _io_decode_0_system_illegal_T = eq(csr_addr_legal, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 936:30] node _io_decode_0_system_illegal_T_1 = eq(is_hlsv, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 936:49] node _io_decode_0_system_illegal_T_2 = and(_io_decode_0_system_illegal_T, _io_decode_0_system_illegal_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 936:46] node _io_decode_0_system_illegal_T_3 = eq(allow_wfi, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 937:17] node _io_decode_0_system_illegal_T_4 = and(is_wfi, _io_decode_0_system_illegal_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 937:14] node _io_decode_0_system_illegal_T_5 = or(_io_decode_0_system_illegal_T_2, _io_decode_0_system_illegal_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 936:58] node _io_decode_0_system_illegal_T_6 = eq(allow_sret, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 938:17] node _io_decode_0_system_illegal_T_7 = and(is_ret, _io_decode_0_system_illegal_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 938:14] node _io_decode_0_system_illegal_T_8 = or(_io_decode_0_system_illegal_T_5, _io_decode_0_system_illegal_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 937:28] node _io_decode_0_system_illegal_T_9 = bits(addr, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 939:21] node _io_decode_0_system_illegal_T_10 = and(is_ret, _io_decode_0_system_illegal_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 939:14] node _io_decode_0_system_illegal_T_11 = bits(addr, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 939:33] node _io_decode_0_system_illegal_T_12 = and(_io_decode_0_system_illegal_T_10, _io_decode_0_system_illegal_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 939:26] node _io_decode_0_system_illegal_T_13 = eq(reg_debug, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 939:40] node _io_decode_0_system_illegal_T_14 = and(_io_decode_0_system_illegal_T_12, _io_decode_0_system_illegal_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 939:37] node _io_decode_0_system_illegal_T_15 = or(_io_decode_0_system_illegal_T_8, _io_decode_0_system_illegal_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 938:29] node _io_decode_0_system_illegal_T_16 = or(is_sfence, is_hfence_gvma) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 940:18] node _io_decode_0_system_illegal_T_17 = eq(allow_sfence_vma, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 940:40] node _io_decode_0_system_illegal_T_18 = and(_io_decode_0_system_illegal_T_16, _io_decode_0_system_illegal_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 940:37] node _io_decode_0_system_illegal_T_19 = or(_io_decode_0_system_illegal_T_15, _io_decode_0_system_illegal_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 939:51] node _io_decode_0_system_illegal_T_20 = eq(allow_hfence_vvma, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 941:25] node _io_decode_0_system_illegal_T_21 = and(is_hfence_vvma, _io_decode_0_system_illegal_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 941:22] node _io_decode_0_system_illegal_T_22 = or(_io_decode_0_system_illegal_T_19, _io_decode_0_system_illegal_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 940:58] node _io_decode_0_system_illegal_T_23 = eq(allow_hlsv, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 942:18] node _io_decode_0_system_illegal_T_24 = and(is_hlsv, _io_decode_0_system_illegal_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 942:15] node _io_decode_0_system_illegal_T_25 = or(_io_decode_0_system_illegal_T_22, _io_decode_0_system_illegal_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 941:44] connect io.decode[0].system_illegal, _io_decode_0_system_illegal_T_25 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 936:27] node _io_decode_0_virtual_access_illegal_T = and(reg_mstatus.v, csr_exists) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 944:52] node _io_decode_0_virtual_access_illegal_T_1 = bits(addr, 9, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 190:36] node _io_decode_0_virtual_access_illegal_T_2 = eq(_io_decode_0_virtual_access_illegal_T_1, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 945:22] node _io_decode_0_virtual_access_illegal_T_3 = dshr(read_mcounteren, counter_addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 946:36] node _io_decode_0_virtual_access_illegal_T_4 = bits(_io_decode_0_virtual_access_illegal_T_3, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 946:36] node _io_decode_0_virtual_access_illegal_T_5 = and(is_counter, _io_decode_0_virtual_access_illegal_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 946:18] node _io_decode_0_virtual_access_illegal_T_6 = dshr(read_hcounteren, counter_addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 946:71] node _io_decode_0_virtual_access_illegal_T_7 = bits(_io_decode_0_virtual_access_illegal_T_6, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 946:71] node _io_decode_0_virtual_access_illegal_T_8 = eq(_io_decode_0_virtual_access_illegal_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 946:55] node _io_decode_0_virtual_access_illegal_T_9 = bits(reg_mstatus.prv, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 946:105] node _io_decode_0_virtual_access_illegal_T_10 = eq(_io_decode_0_virtual_access_illegal_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 946:89] node _io_decode_0_virtual_access_illegal_T_11 = dshr(read_scounteren, counter_addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 946:128] node _io_decode_0_virtual_access_illegal_T_12 = bits(_io_decode_0_virtual_access_illegal_T_11, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 946:128] node _io_decode_0_virtual_access_illegal_T_13 = eq(_io_decode_0_virtual_access_illegal_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 946:112] node _io_decode_0_virtual_access_illegal_T_14 = and(_io_decode_0_virtual_access_illegal_T_10, _io_decode_0_virtual_access_illegal_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 946:109] node _io_decode_0_virtual_access_illegal_T_15 = or(_io_decode_0_virtual_access_illegal_T_8, _io_decode_0_virtual_access_illegal_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 946:86] node _io_decode_0_virtual_access_illegal_T_16 = and(_io_decode_0_virtual_access_illegal_T_5, _io_decode_0_virtual_access_illegal_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 946:51] node _io_decode_0_virtual_access_illegal_T_17 = or(_io_decode_0_virtual_access_illegal_T_2, _io_decode_0_virtual_access_illegal_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 945:34] node _io_decode_0_virtual_access_illegal_T_18 = bits(addr, 9, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 190:36] node _io_decode_0_virtual_access_illegal_T_19 = eq(_io_decode_0_virtual_access_illegal_T_18, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 947:22] node _io_decode_0_virtual_access_illegal_T_20 = bits(reg_mstatus.prv, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 947:53] node _io_decode_0_virtual_access_illegal_T_21 = eq(_io_decode_0_virtual_access_illegal_T_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 947:37] node _io_decode_0_virtual_access_illegal_T_22 = and(_io_decode_0_virtual_access_illegal_T_19, _io_decode_0_virtual_access_illegal_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 947:34] node _io_decode_0_virtual_access_illegal_T_23 = or(_io_decode_0_virtual_access_illegal_T_17, _io_decode_0_virtual_access_illegal_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 946:144] node _io_decode_0_virtual_access_illegal_T_24 = eq(addr, UInt<9>(0h180)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 948:12] node _io_decode_0_virtual_access_illegal_T_25 = bits(reg_mstatus.prv, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 948:46] node _io_decode_0_virtual_access_illegal_T_26 = and(_io_decode_0_virtual_access_illegal_T_24, _io_decode_0_virtual_access_illegal_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 948:28] node _io_decode_0_virtual_access_illegal_T_27 = and(_io_decode_0_virtual_access_illegal_T_26, reg_hstatus.vtvm) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 948:50] node _io_decode_0_virtual_access_illegal_T_28 = or(_io_decode_0_virtual_access_illegal_T_23, _io_decode_0_virtual_access_illegal_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 947:57] node _io_decode_0_virtual_access_illegal_T_29 = and(_io_decode_0_virtual_access_illegal_T, _io_decode_0_virtual_access_illegal_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 944:66] connect io.decode[0].virtual_access_illegal, _io_decode_0_virtual_access_illegal_T_29 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 944:35] node _io_decode_0_virtual_system_illegal_T = or(is_hfence_vvma, is_hfence_gvma) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 951:22] node _io_decode_0_virtual_system_illegal_T_1 = or(_io_decode_0_virtual_system_illegal_T, is_hlsv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 952:22] node _io_decode_0_virtual_system_illegal_T_2 = bits(reg_mstatus.prv, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 954:34] node _io_decode_0_virtual_system_illegal_T_3 = eq(_io_decode_0_virtual_system_illegal_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 954:18] node _io_decode_0_virtual_system_illegal_T_4 = eq(reg_mstatus.tw, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 954:41] node _io_decode_0_virtual_system_illegal_T_5 = and(_io_decode_0_virtual_system_illegal_T_4, reg_hstatus.vtw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 954:57] node _io_decode_0_virtual_system_illegal_T_6 = or(_io_decode_0_virtual_system_illegal_T_3, _io_decode_0_virtual_system_illegal_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 954:38] node _io_decode_0_virtual_system_illegal_T_7 = and(is_wfi, _io_decode_0_virtual_system_illegal_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 954:14] node _io_decode_0_virtual_system_illegal_T_8 = or(_io_decode_0_virtual_system_illegal_T_1, _io_decode_0_virtual_system_illegal_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 953:15] node _io_decode_0_virtual_system_illegal_T_9 = bits(addr, 9, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 190:36] node _io_decode_0_virtual_system_illegal_T_10 = eq(_io_decode_0_virtual_system_illegal_T_9, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 955:32] node _io_decode_0_virtual_system_illegal_T_11 = and(is_ret, _io_decode_0_virtual_system_illegal_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 955:14] node _io_decode_0_virtual_system_illegal_T_12 = bits(reg_mstatus.prv, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 955:64] node _io_decode_0_virtual_system_illegal_T_13 = eq(_io_decode_0_virtual_system_illegal_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 955:48] node _io_decode_0_virtual_system_illegal_T_14 = or(_io_decode_0_virtual_system_illegal_T_13, reg_hstatus.vtsr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 955:68] node _io_decode_0_virtual_system_illegal_T_15 = and(_io_decode_0_virtual_system_illegal_T_11, _io_decode_0_virtual_system_illegal_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 955:44] node _io_decode_0_virtual_system_illegal_T_16 = or(_io_decode_0_virtual_system_illegal_T_8, _io_decode_0_virtual_system_illegal_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 954:77] node _io_decode_0_virtual_system_illegal_T_17 = bits(reg_mstatus.prv, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 956:37] node _io_decode_0_virtual_system_illegal_T_18 = eq(_io_decode_0_virtual_system_illegal_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 956:21] node _io_decode_0_virtual_system_illegal_T_19 = or(_io_decode_0_virtual_system_illegal_T_18, reg_hstatus.vtvm) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 956:41] node _io_decode_0_virtual_system_illegal_T_20 = and(is_sfence, _io_decode_0_virtual_system_illegal_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 956:17] node _io_decode_0_virtual_system_illegal_T_21 = or(_io_decode_0_virtual_system_illegal_T_16, _io_decode_0_virtual_system_illegal_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 955:89] node _io_decode_0_virtual_system_illegal_T_22 = and(reg_mstatus.v, _io_decode_0_virtual_system_illegal_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 950:52] connect io.decode[0].virtual_system_illegal, _io_decode_0_virtual_system_illegal_T_22 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 950:35] node _cause_T = bits(reg_mstatus.prv, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 960:61] node _cause_T_1 = and(_cause_T, reg_mstatus.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 960:65] node _cause_T_2 = mux(_cause_T_1, UInt<2>(0h2), reg_mstatus.prv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 960:45] node _cause_T_3 = add(UInt<4>(0h8), _cause_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 960:40] node _cause_T_4 = tail(_cause_T_3, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 960:40] node _cause_T_5 = mux(insn_break, UInt<2>(0h3), io.cause) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 961:14] node cause = mux(insn_call, _cause_T_4, _cause_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 960:8] node cause_lsbs = bits(cause, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 962:25] node cause_deleg_lsbs = bits(cause, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 963:31] node _causeIsDebugInt_T = bits(cause, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 964:30] node _causeIsDebugInt_T_1 = eq(cause_lsbs, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 964:53] node causeIsDebugInt = and(_causeIsDebugInt_T, _causeIsDebugInt_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 964:39] node _causeIsDebugTrigger_T = bits(cause, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 965:35] node _causeIsDebugTrigger_T_1 = eq(_causeIsDebugTrigger_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 965:29] node _causeIsDebugTrigger_T_2 = eq(cause_lsbs, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 965:58] node causeIsDebugTrigger = and(_causeIsDebugTrigger_T_1, _causeIsDebugTrigger_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 965:44] node _causeIsDebugBreak_T = bits(cause, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 966:33] node _causeIsDebugBreak_T_1 = eq(_causeIsDebugBreak_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 966:27] node _causeIsDebugBreak_T_2 = and(_causeIsDebugBreak_T_1, insn_break) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 966:42] node causeIsDebugBreak_lo = cat(reg_dcsr.ebreaks, reg_dcsr.ebreaku) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 966:62] node causeIsDebugBreak_hi = cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 966:62] node _causeIsDebugBreak_T_3 = cat(causeIsDebugBreak_hi, causeIsDebugBreak_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 966:62] node _causeIsDebugBreak_T_4 = dshr(_causeIsDebugBreak_T_3, reg_mstatus.prv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 966:134] node _causeIsDebugBreak_T_5 = bits(_causeIsDebugBreak_T_4, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 966:134] node causeIsDebugBreak = and(_causeIsDebugBreak_T_2, _causeIsDebugBreak_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 966:56] node _trapToDebug_T = or(reg_singleStepped, causeIsDebugInt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 967:56] node _trapToDebug_T_1 = or(_trapToDebug_T, causeIsDebugTrigger) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 967:75] node _trapToDebug_T_2 = or(_trapToDebug_T_1, causeIsDebugBreak) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 967:98] node _trapToDebug_T_3 = or(_trapToDebug_T_2, reg_debug) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 967:119] node trapToDebug = and(UInt<1>(0h1), _trapToDebug_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 967:34] node _debugTVec_T = mux(insn_break, UInt<12>(0h800), UInt<12>(0h808)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 970:37] node debugTVec = mux(reg_debug, _debugTVec_T, UInt<12>(0h800)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 970:22] node _delegate_T = leq(reg_mstatus.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 971:55] node _delegate_T_1 = and(UInt<1>(0h0), _delegate_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 971:36] node _delegate_T_2 = bits(cause, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 971:78] node _delegate_T_3 = dshr(read_mideleg, cause_deleg_lsbs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 971:100] node _delegate_T_4 = bits(_delegate_T_3, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 971:100] node _delegate_T_5 = dshr(read_medeleg, cause_deleg_lsbs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 971:132] node _delegate_T_6 = bits(_delegate_T_5, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 971:132] node _delegate_T_7 = mux(_delegate_T_2, _delegate_T_4, _delegate_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 971:72] node delegate = and(_delegate_T_1, _delegate_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 971:66] node _delegateVS_T = and(reg_mstatus.v, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 972:34] node _delegateVS_T_1 = bits(cause, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 972:58] node _delegateVS_T_2 = dshr(read_hideleg, cause_deleg_lsbs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 972:80] node _delegateVS_T_3 = bits(_delegateVS_T_2, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 972:80] node _delegateVS_T_4 = dshr(read_hedeleg, cause_deleg_lsbs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 972:112] node _delegateVS_T_5 = bits(_delegateVS_T_4, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 972:112] node _delegateVS_T_6 = mux(_delegateVS_T_1, _delegateVS_T_3, _delegateVS_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 972:52] node delegateVS = and(_delegateVS_T, _delegateVS_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 972:46] node _notDebugTVec_base_T = mux(delegateVS, read_vstvec, read_stvec) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 979:33] node notDebugTVec_base = mux(delegate, _notDebugTVec_base_T, read_mtvec) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 979:19] node _notDebugTVec_interruptOffset_T = bits(cause, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 980:32] node notDebugTVec_interruptOffset = shl(_notDebugTVec_interruptOffset_T, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 980:59] node _notDebugTVec_interruptVec_T = shr(notDebugTVec_base, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 981:33] node notDebugTVec_interruptVec = cat(_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 981:27] node _notDebugTVec_doVector_T = bits(notDebugTVec_base, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 982:24] node _notDebugTVec_doVector_T_1 = bits(cause, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 982:36] node _notDebugTVec_doVector_T_2 = and(_notDebugTVec_doVector_T, _notDebugTVec_doVector_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 982:28] node _notDebugTVec_doVector_T_3 = shr(cause_lsbs, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 982:70] node _notDebugTVec_doVector_T_4 = eq(_notDebugTVec_doVector_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 982:94] node notDebugTVec_doVector = and(_notDebugTVec_doVector_T_2, _notDebugTVec_doVector_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 982:55] node _notDebugTVec_T = shr(notDebugTVec_base, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 983:38] node _notDebugTVec_T_1 = shl(_notDebugTVec_T, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 983:56] node notDebugTVec = mux(notDebugTVec_doVector, notDebugTVec_interruptVec, _notDebugTVec_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 983:8] node _causeIsRnmiInt_T = bits(cause, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 986:29] node _causeIsRnmiInt_T_1 = bits(cause, 62, 62) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 986:46] node _causeIsRnmiInt_T_2 = and(_causeIsRnmiInt_T, _causeIsRnmiInt_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 986:38] node _causeIsRnmiInt_T_3 = eq(cause_lsbs, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 986:70] node _causeIsRnmiInt_T_4 = eq(cause_lsbs, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 986:107] node _causeIsRnmiInt_T_5 = or(_causeIsRnmiInt_T_3, _causeIsRnmiInt_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 986:93] node causeIsRnmiInt = and(_causeIsRnmiInt_T_2, _causeIsRnmiInt_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 986:55] node _causeIsRnmiBEU_T = bits(cause, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 987:29] node _causeIsRnmiBEU_T_1 = bits(cause, 62, 62) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 987:46] node _causeIsRnmiBEU_T_2 = and(_causeIsRnmiBEU_T, _causeIsRnmiBEU_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 987:38] node _causeIsRnmiBEU_T_3 = eq(cause_lsbs, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 987:69] node causeIsRnmiBEU = and(_causeIsRnmiBEU_T_2, _causeIsRnmiBEU_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 987:55] node trapToNmiInt = and(UInt<1>(0h0), causeIsRnmiInt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 991:33] node _trapToNmiXcpt_T = eq(reg_rnmie, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 992:37] node trapToNmiXcpt = and(UInt<1>(0h0), _trapToNmiXcpt_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 992:34] node trapToNmi = or(trapToNmiInt, trapToNmiXcpt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 993:32] node _nmiTVec_T = mux(causeIsRnmiInt, UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 994:21] node _nmiTVec_T_1 = shr(_nmiTVec_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 994:58] node nmiTVec = shl(_nmiTVec_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 994:62] node _tvec_T = mux(trapToNmi, nmiTVec, notDebugTVec) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 996:45] node tvec = mux(trapToDebug, debugTVec, _tvec_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 996:17] connect io.evec, tvec @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 997:11] connect io.ptbr, reg_satp @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 998:11] connect io.hgatp, reg_hgatp @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 999:12] connect io.vsatp, reg_vsatp @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1000:12] node _io_eret_T = or(insn_call, insn_break) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1001:24] node _io_eret_T_1 = or(_io_eret_T, insn_ret) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1001:38] connect io.eret, _io_eret_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1001:11] connect io.trap_return, insn_ret @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1002:18] node _io_singleStep_T = eq(reg_debug, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1003:37] node _io_singleStep_T_1 = and(reg_dcsr.step, _io_singleStep_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1003:34] connect io.singleStep, _io_singleStep_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1003:17] connect io.status, reg_mstatus @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1004:13] node _io_status_sd_T = andr(io.status.fs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1005:32] node _io_status_sd_T_1 = andr(io.status.xs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1005:53] node _io_status_sd_T_2 = or(_io_status_sd_T, _io_status_sd_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1005:37] node _io_status_sd_T_3 = andr(io.status.vs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1005:74] node _io_status_sd_T_4 = or(_io_status_sd_T_2, _io_status_sd_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1005:58] connect io.status.sd, _io_status_sd_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1005:16] connect io.status.debug, reg_debug @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1006:19] connect io.status.isa, reg_misa @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1007:17] connect io.status.uxl, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1008:17] connect io.status.sxl, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1009:17] node _io_status_dprv_T = eq(reg_debug, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1010:45] node _io_status_dprv_T_1 = and(reg_mstatus.mprv, _io_status_dprv_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1010:42] node _io_status_dprv_T_2 = mux(_io_status_dprv_T_1, reg_mstatus.mpp, reg_mstatus.prv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1010:24] connect io.status.dprv, _io_status_dprv_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1010:18] node _io_status_dv_T = eq(reg_debug, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1011:60] node _io_status_dv_T_1 = and(reg_mstatus.mprv, _io_status_dv_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1011:57] node _io_status_dv_T_2 = mux(_io_status_dv_T_1, reg_mstatus.mpv, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1011:39] node _io_status_dv_T_3 = or(reg_mstatus.v, _io_status_dv_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1011:33] connect io.status.dv, _io_status_dv_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1011:16] node _io_status_sd_rv32_T = and(UInt<1>(0h0), io.status.sd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1012:39] connect io.status.sd_rv32, _io_status_sd_rv32_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1012:21] connect io.status.mpv, reg_mstatus.mpv @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1013:17] connect io.status.gva, reg_mstatus.gva @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1014:17] connect io.hstatus, reg_hstatus @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1015:14] connect io.hstatus.vsxl, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1016:19] connect io.gstatus, reg_vsstatus @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1017:14] node _io_gstatus_sd_T = andr(io.gstatus.fs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1018:34] node _io_gstatus_sd_T_1 = andr(io.gstatus.xs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1018:56] node _io_gstatus_sd_T_2 = or(_io_gstatus_sd_T, _io_gstatus_sd_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1018:39] node _io_gstatus_sd_T_3 = andr(io.gstatus.vs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1018:78] node _io_gstatus_sd_T_4 = or(_io_gstatus_sd_T_2, _io_gstatus_sd_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1018:61] connect io.gstatus.sd, _io_gstatus_sd_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1018:17] connect io.gstatus.uxl, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1019:18] node _io_gstatus_sd_rv32_T = and(UInt<1>(0h0), io.gstatus.sd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1020:40] connect io.gstatus.sd_rv32, _io_gstatus_sd_rv32_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1020:22] node _exception_T = or(insn_call, insn_break) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1022:29] node exception = or(_exception_T, io.exception) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1022:43] node _T_70 = add(insn_ret, insn_call) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1023:18] node _T_71 = bits(_T_70, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1023:18] node _T_72 = add(insn_break, io.exception) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1023:18] node _T_73 = bits(_T_72, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1023:18] node _T_74 = add(_T_71, _T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1023:18] node _T_75 = bits(_T_74, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1023:18] node _T_76 = leq(_T_75, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1023:79] node _T_77 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1023:9] node _T_78 = eq(_T_77, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1023:9] when _T_78 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1023:9] node _T_79 = eq(_T_76, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1023:9] when _T_79 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1023:9] printf(clock, UInt<1>(0h1), "Assertion failed: these conditions must be mutually exclusive\n at CSR.scala:1023 assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, \"these conditions must be mutually exclusive\")\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1023:9] assert(clock, _T_76, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1023:9] node _T_80 = eq(io.singleStep, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1025:21] node _T_81 = and(insn_wfi, _T_80) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1025:18] node _T_82 = eq(reg_debug, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1025:39] node _T_83 = and(_T_81, _T_82) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1025:36] when _T_83 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1025:51] connect reg_wfi, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1025:61] node _T_84 = orr(pending_interrupts) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1026:28] node _T_85 = or(_T_84, io.interrupts.debug) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1026:32] node _T_86 = or(_T_85, exception) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1026:55] when _T_86 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1026:69] connect reg_wfi, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1026:79] node _T_87 = bits(io.retire, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1029:18] node _T_88 = or(_T_87, exception) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1029:22] when _T_88 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1029:36] connect reg_singleStepped, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1029:56] node _T_89 = eq(io.singleStep, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1030:9] when _T_89 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1030:25] connect reg_singleStepped, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1030:45] node _T_90 = eq(io.singleStep, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1031:10] node _T_91 = leq(io.retire, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1031:38] node _T_92 = or(_T_90, _T_91) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1031:25] node _T_93 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1031:9] node _T_94 = eq(_T_93, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1031:9] when _T_94 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1031:9] node _T_95 = eq(_T_92, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1031:9] when _T_95 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1031:9] printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1031 assert(!io.singleStep || io.retire <= 1.U)\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1031:9] assert(clock, _T_92, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1031:9] node _T_96 = eq(reg_singleStepped, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1032:10] node _T_97 = eq(io.retire, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1032:42] node _T_98 = or(_T_96, _T_97) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1032:29] node _T_99 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1032:9] node _T_100 = eq(_T_99, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1032:9] when _T_100 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1032:9] node _T_101 = eq(_T_98, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1032:9] when _T_101 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1032:9] printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1032 assert(!reg_singleStepped || io.retire === 0.U)\n") : printf_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1032:9] assert(clock, _T_98, UInt<1>(0h1), "") : assert_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1032:9] node _epc_T = not(io.pc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1666:28] node _epc_T_1 = or(_epc_T, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1666:31] node epc = not(_epc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1666:26] node tval = mux(insn_break, epc, io.tval) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1035:17] when exception : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1037:20] when trapToDebug : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1038:24] node _T_102 = eq(reg_debug, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1039:13] when _T_102 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1039:25] connect reg_mstatus.v, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1040:23] connect reg_debug, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1041:19] connect reg_dpc, epc @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1042:17] node _reg_dcsr_cause_T = mux(causeIsDebugTrigger, UInt<2>(0h2), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1043:90] node _reg_dcsr_cause_T_1 = mux(causeIsDebugInt, UInt<2>(0h3), _reg_dcsr_cause_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1043:58] node _reg_dcsr_cause_T_2 = mux(reg_singleStepped, UInt<3>(0h4), _reg_dcsr_cause_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1043:30] connect reg_dcsr.cause, _reg_dcsr_cause_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1043:24] connect reg_dcsr.prv, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1044:22] connect reg_dcsr.v, reg_mstatus.v @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1045:20] connect new_prv, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1046:17] else : when trapToNmiInt : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1048:31] when reg_rnmie : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1049:24] connect reg_mstatus.v, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1050:23] connect reg_mnstatus.mpv, reg_mstatus.v @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1051:26] connect reg_rnmie, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1052:19] connect reg_mnepc, epc @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1053:19] node _reg_mncause_T = mux(causeIsRnmiBEU, UInt<2>(0h3), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1054:55] node _reg_mncause_T_1 = or(UInt<64>(0h8000000000000000), _reg_mncause_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1054:50] connect reg_mncause, _reg_mncause_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1054:21] connect reg_mnstatus.mpp, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1055:26] connect new_prv, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1056:17] else : node _T_103 = and(delegateVS, reg_rnmie) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1058:28] when _T_103 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1058:37] connect reg_mstatus.v, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1059:21] connect reg_vsstatus.spp, reg_mstatus.prv @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1060:24] connect reg_vsepc, epc @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1061:17] node _reg_vscause_T = bits(cause, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1062:31] node _reg_vscause_T_1 = bits(cause, 63, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1062:50] node _reg_vscause_T_2 = cat(_reg_vscause_T_1, UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1062:44] node _reg_vscause_T_3 = mux(_reg_vscause_T, _reg_vscause_T_2, cause) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1062:25] connect reg_vscause, _reg_vscause_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1062:19] connect reg_vstval, tval @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1063:18] connect reg_vsstatus.spie, reg_vsstatus.sie @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1064:25] connect reg_vsstatus.sie, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1065:24] connect new_prv, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1066:15] else : node _T_104 = and(delegate, reg_rnmie) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1067:26] when _T_104 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1067:35] connect reg_mstatus.v, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1068:21] node _reg_hstatus_spvp_T = bits(reg_mstatus.prv, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1069:61] node _reg_hstatus_spvp_T_1 = mux(reg_mstatus.v, _reg_hstatus_spvp_T, reg_hstatus.spvp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1069:30] connect reg_hstatus.spvp, _reg_hstatus_spvp_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1069:24] connect reg_hstatus.gva, io.gva @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1070:23] connect reg_hstatus.spv, reg_mstatus.v @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1071:23] connect reg_sepc, epc @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1072:16] connect reg_scause, cause @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1073:18] connect reg_stval, tval @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1074:17] connect reg_htval, io.htval @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1075:17] connect reg_htinst_read_pseudo, io.mhtinst_read_pseudo @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1076:30] connect reg_mstatus.spie, reg_mstatus.sie @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1077:24] connect reg_mstatus.spp, reg_mstatus.prv @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1078:23] connect reg_mstatus.sie, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1079:23] connect new_prv, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1080:15] else : connect reg_mstatus.v, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1082:21] connect reg_mstatus.mpv, reg_mstatus.v @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1083:23] connect reg_mstatus.gva, io.gva @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1084:23] connect reg_mepc, epc @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1085:16] connect reg_mcause, cause @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1086:18] connect reg_mtval, tval @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1087:17] connect reg_mtval2, io.htval @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1088:18] connect reg_mtinst_read_pseudo, io.mhtinst_read_pseudo @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1089:30] connect reg_mstatus.mpie, reg_mstatus.mie @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1090:24] connect reg_mstatus.mpp, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1091:23] connect reg_mstatus.mie, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1092:23] connect new_prv, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1093:15] node _en_T = and(supported_interrupts, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:49] node _en_T_1 = neq(_en_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:71] node _en_T_2 = and(exception, _en_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:24] node _en_T_3 = add(UInt<64>(0h8000000000000000), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_4 = tail(_en_T_3, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_5 = eq(cause, _en_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:88] node en = and(_en_T_2, _en_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:79] node _delegable_T = and(delegable_interrupts, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:43] node delegable = neq(_delegable_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:65] node _T_105 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:26] node _T_106 = and(en, _T_105) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:23] node _T_107 = and(en, delegable) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:23] node _T_108 = and(_T_107, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:36] node _en_T_6 = and(supported_interrupts, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:49] node _en_T_7 = neq(_en_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:71] node _en_T_8 = and(exception, _en_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:24] node _en_T_9 = add(UInt<64>(0h8000000000000000), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_10 = tail(_en_T_9, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_11 = eq(cause, _en_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:88] node en_1 = and(_en_T_8, _en_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:79] node _delegable_T_1 = and(delegable_interrupts, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:43] node delegable_1 = neq(_delegable_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:65] node _T_109 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:26] node _T_110 = and(en_1, _T_109) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:23] node _T_111 = and(en_1, delegable_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:23] node _T_112 = and(_T_111, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:36] node _en_T_12 = and(supported_interrupts, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:49] node _en_T_13 = neq(_en_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:71] node _en_T_14 = and(exception, _en_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:24] node _en_T_15 = add(UInt<64>(0h8000000000000000), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_16 = tail(_en_T_15, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_17 = eq(cause, _en_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:88] node en_2 = and(_en_T_14, _en_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:79] node _delegable_T_2 = and(delegable_interrupts, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:43] node delegable_2 = neq(_delegable_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:65] node _T_113 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:26] node _T_114 = and(en_2, _T_113) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:23] node _T_115 = and(en_2, delegable_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:23] node _T_116 = and(_T_115, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:36] node _en_T_18 = and(supported_interrupts, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:49] node _en_T_19 = neq(_en_T_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:71] node _en_T_20 = and(exception, _en_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:24] node _en_T_21 = add(UInt<64>(0h8000000000000000), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_22 = tail(_en_T_21, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_23 = eq(cause, _en_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:88] node en_3 = and(_en_T_20, _en_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:79] node _delegable_T_3 = and(delegable_interrupts, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:43] node delegable_3 = neq(_delegable_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:65] node _T_117 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:26] node _T_118 = and(en_3, _T_117) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:23] node _T_119 = and(en_3, delegable_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:23] node _T_120 = and(_T_119, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:36] node _en_T_24 = and(supported_interrupts, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:49] node _en_T_25 = neq(_en_T_24, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:71] node _en_T_26 = and(exception, _en_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:24] node _en_T_27 = add(UInt<64>(0h8000000000000000), UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_28 = tail(_en_T_27, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_29 = eq(cause, _en_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:88] node en_4 = and(_en_T_26, _en_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:79] node _delegable_T_4 = and(delegable_interrupts, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:43] node delegable_4 = neq(_delegable_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:65] node _T_121 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:26] node _T_122 = and(en_4, _T_121) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:23] node _T_123 = and(en_4, delegable_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:23] node _T_124 = and(_T_123, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:36] node _en_T_30 = and(supported_interrupts, UInt<6>(0h20)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:49] node _en_T_31 = neq(_en_T_30, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:71] node _en_T_32 = and(exception, _en_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:24] node _en_T_33 = add(UInt<64>(0h8000000000000000), UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_34 = tail(_en_T_33, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_35 = eq(cause, _en_T_34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:88] node en_5 = and(_en_T_32, _en_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:79] node _delegable_T_5 = and(delegable_interrupts, UInt<6>(0h20)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:43] node delegable_5 = neq(_delegable_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:65] node _T_125 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:26] node _T_126 = and(en_5, _T_125) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:23] node _T_127 = and(en_5, delegable_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:23] node _T_128 = and(_T_127, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:36] node _en_T_36 = and(supported_interrupts, UInt<7>(0h40)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:49] node _en_T_37 = neq(_en_T_36, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:71] node _en_T_38 = and(exception, _en_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:24] node _en_T_39 = add(UInt<64>(0h8000000000000000), UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_40 = tail(_en_T_39, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_41 = eq(cause, _en_T_40) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:88] node en_6 = and(_en_T_38, _en_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:79] node _delegable_T_6 = and(delegable_interrupts, UInt<7>(0h40)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:43] node delegable_6 = neq(_delegable_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:65] node _T_129 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:26] node _T_130 = and(en_6, _T_129) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:23] node _T_131 = and(en_6, delegable_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:23] node _T_132 = and(_T_131, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:36] node _en_T_42 = and(supported_interrupts, UInt<8>(0h80)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:49] node _en_T_43 = neq(_en_T_42, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:71] node _en_T_44 = and(exception, _en_T_43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:24] node _en_T_45 = add(UInt<64>(0h8000000000000000), UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_46 = tail(_en_T_45, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_47 = eq(cause, _en_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:88] node en_7 = and(_en_T_44, _en_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:79] node _delegable_T_7 = and(delegable_interrupts, UInt<8>(0h80)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:43] node delegable_7 = neq(_delegable_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:65] node _T_133 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:26] node _T_134 = and(en_7, _T_133) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:23] node _T_135 = and(en_7, delegable_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:23] node _T_136 = and(_T_135, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:36] node _en_T_48 = and(supported_interrupts, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:49] node _en_T_49 = neq(_en_T_48, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:71] node _en_T_50 = and(exception, _en_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:24] node _en_T_51 = add(UInt<64>(0h8000000000000000), UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_52 = tail(_en_T_51, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_53 = eq(cause, _en_T_52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:88] node en_8 = and(_en_T_50, _en_T_53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:79] node _delegable_T_8 = and(delegable_interrupts, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:43] node delegable_8 = neq(_delegable_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:65] node _T_137 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:26] node _T_138 = and(en_8, _T_137) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:23] node _T_139 = and(en_8, delegable_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:23] node _T_140 = and(_T_139, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:36] node _en_T_54 = and(supported_interrupts, UInt<10>(0h200)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:49] node _en_T_55 = neq(_en_T_54, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:71] node _en_T_56 = and(exception, _en_T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:24] node _en_T_57 = add(UInt<64>(0h8000000000000000), UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_58 = tail(_en_T_57, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_59 = eq(cause, _en_T_58) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:88] node en_9 = and(_en_T_56, _en_T_59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:79] node _delegable_T_9 = and(delegable_interrupts, UInt<10>(0h200)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:43] node delegable_9 = neq(_delegable_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:65] node _T_141 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:26] node _T_142 = and(en_9, _T_141) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:23] node _T_143 = and(en_9, delegable_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:23] node _T_144 = and(_T_143, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:36] node _en_T_60 = and(supported_interrupts, UInt<11>(0h400)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:49] node _en_T_61 = neq(_en_T_60, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:71] node _en_T_62 = and(exception, _en_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:24] node _en_T_63 = add(UInt<64>(0h8000000000000000), UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_64 = tail(_en_T_63, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_65 = eq(cause, _en_T_64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:88] node en_10 = and(_en_T_62, _en_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:79] node _delegable_T_10 = and(delegable_interrupts, UInt<11>(0h400)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:43] node delegable_10 = neq(_delegable_T_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:65] node _T_145 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:26] node _T_146 = and(en_10, _T_145) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:23] node _T_147 = and(en_10, delegable_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:23] node _T_148 = and(_T_147, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:36] node _en_T_66 = and(supported_interrupts, UInt<12>(0h800)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:49] node _en_T_67 = neq(_en_T_66, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:71] node _en_T_68 = and(exception, _en_T_67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:24] node _en_T_69 = add(UInt<64>(0h8000000000000000), UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_70 = tail(_en_T_69, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_71 = eq(cause, _en_T_70) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:88] node en_11 = and(_en_T_68, _en_T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:79] node _delegable_T_11 = and(delegable_interrupts, UInt<12>(0h800)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:43] node delegable_11 = neq(_delegable_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:65] node _T_149 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:26] node _T_150 = and(en_11, _T_149) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:23] node _T_151 = and(en_11, delegable_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:23] node _T_152 = and(_T_151, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:36] node _en_T_72 = and(supported_interrupts, UInt<13>(0h1000)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:49] node _en_T_73 = neq(_en_T_72, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:71] node _en_T_74 = and(exception, _en_T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:24] node _en_T_75 = add(UInt<64>(0h8000000000000000), UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_76 = tail(_en_T_75, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_77 = eq(cause, _en_T_76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:88] node en_12 = and(_en_T_74, _en_T_77) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:79] node _delegable_T_12 = and(delegable_interrupts, UInt<13>(0h1000)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:43] node delegable_12 = neq(_delegable_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:65] node _T_153 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:26] node _T_154 = and(en_12, _T_153) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:23] node _T_155 = and(en_12, delegable_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:23] node _T_156 = and(_T_155, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:36] node _en_T_78 = and(supported_interrupts, UInt<14>(0h2000)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:49] node _en_T_79 = neq(_en_T_78, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:71] node _en_T_80 = and(exception, _en_T_79) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:24] node _en_T_81 = add(UInt<64>(0h8000000000000000), UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_82 = tail(_en_T_81, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_83 = eq(cause, _en_T_82) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:88] node en_13 = and(_en_T_80, _en_T_83) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:79] node _delegable_T_13 = and(delegable_interrupts, UInt<14>(0h2000)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:43] node delegable_13 = neq(_delegable_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:65] node _T_157 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:26] node _T_158 = and(en_13, _T_157) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:23] node _T_159 = and(en_13, delegable_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:23] node _T_160 = and(_T_159, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:36] node _en_T_84 = and(supported_interrupts, UInt<15>(0h4000)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:49] node _en_T_85 = neq(_en_T_84, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:71] node _en_T_86 = and(exception, _en_T_85) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:24] node _en_T_87 = add(UInt<64>(0h8000000000000000), UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_88 = tail(_en_T_87, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_89 = eq(cause, _en_T_88) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:88] node en_14 = and(_en_T_86, _en_T_89) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:79] node _delegable_T_14 = and(delegable_interrupts, UInt<15>(0h4000)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:43] node delegable_14 = neq(_delegable_T_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:65] node _T_161 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:26] node _T_162 = and(en_14, _T_161) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:23] node _T_163 = and(en_14, delegable_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:23] node _T_164 = and(_T_163, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:36] node _en_T_90 = and(supported_interrupts, UInt<16>(0h8000)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:49] node _en_T_91 = neq(_en_T_90, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:71] node _en_T_92 = and(exception, _en_T_91) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:24] node _en_T_93 = add(UInt<64>(0h8000000000000000), UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_94 = tail(_en_T_93, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:120] node _en_T_95 = eq(cause, _en_T_94) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:88] node en_15 = and(_en_T_92, _en_T_95) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1098:79] node _delegable_T_15 = and(delegable_interrupts, UInt<16>(0h8000)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:43] node delegable_15 = neq(_delegable_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1099:65] node _T_165 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:26] node _T_166 = and(en_15, _T_165) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1100:23] node _T_167 = and(en_15, delegable_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:23] node _T_168 = and(_T_167, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1101:36] node _en_T_96 = eq(cause, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1110:35] node en_16 = and(exception, _en_T_96) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1110:26] node _delegable_T_16 = and(UInt<16>(0hb15d), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1111:45] node delegable_16 = neq(_delegable_T_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1111:67] node _T_169 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1112:28] node _T_170 = and(en_16, _T_169) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1112:25] node _T_171 = and(en_16, delegable_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1113:25] node _T_172 = and(_T_171, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1113:38] node _en_T_97 = eq(cause, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1110:35] node en_17 = and(exception, _en_T_97) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1110:26] node _delegable_T_17 = and(UInt<16>(0hb15d), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1111:45] node delegable_17 = neq(_delegable_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1111:67] node _T_173 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1112:28] node _T_174 = and(en_17, _T_173) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1112:25] node _T_175 = and(en_17, delegable_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1113:25] node _T_176 = and(_T_175, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1113:38] node _en_T_98 = eq(cause, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1110:35] node en_18 = and(exception, _en_T_98) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1110:26] node _delegable_T_18 = and(UInt<16>(0hb15d), UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1111:45] node delegable_18 = neq(_delegable_T_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1111:67] node _T_177 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1112:28] node _T_178 = and(en_18, _T_177) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1112:25] node _T_179 = and(en_18, delegable_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1113:25] node _T_180 = and(_T_179, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1113:38] node _en_T_99 = eq(cause, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1110:35] node en_19 = and(exception, _en_T_99) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1110:26] node _delegable_T_19 = and(UInt<16>(0hb15d), UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1111:45] node delegable_19 = neq(_delegable_T_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1111:67] node _T_181 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1112:28] node _T_182 = and(en_19, _T_181) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1112:25] node _T_183 = and(en_19, delegable_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1113:25] node _T_184 = and(_T_183, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1113:38] node _en_T_100 = eq(cause, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1110:35] node en_20 = and(exception, _en_T_100) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1110:26] node _delegable_T_20 = and(UInt<16>(0hb15d), UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1111:45] node delegable_20 = neq(_delegable_T_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1111:67] node _T_185 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1112:28] node _T_186 = and(en_20, _T_185) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1112:25] node _T_187 = and(en_20, delegable_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1113:25] node _T_188 = and(_T_187, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1113:38] node _en_T_101 = eq(cause, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1110:35] node en_21 = and(exception, _en_T_101) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1110:26] node _delegable_T_21 = and(UInt<16>(0hb15d), UInt<6>(0h20)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1111:45] node delegable_21 = neq(_delegable_T_21, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1111:67] node _T_189 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1112:28] node _T_190 = and(en_21, _T_189) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1112:25] node _T_191 = and(en_21, delegable_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1113:25] node _T_192 = and(_T_191, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1113:38] node _en_T_102 = eq(cause, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1110:35] node en_22 = and(exception, _en_T_102) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1110:26] node _delegable_T_22 = and(UInt<16>(0hb15d), UInt<7>(0h40)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1111:45] node delegable_22 = neq(_delegable_T_22, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1111:67] node _T_193 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1112:28] node _T_194 = and(en_22, _T_193) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1112:25] node _T_195 = and(en_22, delegable_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1113:25] node _T_196 = and(_T_195, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1113:38] node _en_T_103 = eq(cause, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1110:35] node en_23 = and(exception, _en_T_103) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1110:26] node _delegable_T_23 = and(UInt<16>(0hb15d), UInt<8>(0h80)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1111:45] node delegable_23 = neq(_delegable_T_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1111:67] node _T_197 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1112:28] node _T_198 = and(en_23, _T_197) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1112:25] node _T_199 = and(en_23, delegable_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1113:25] node _T_200 = and(_T_199, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1113:38] node _en_T_104 = eq(cause, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1110:35] node en_24 = and(exception, _en_T_104) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1110:26] node _delegable_T_24 = and(UInt<16>(0hb15d), UInt<12>(0h800)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1111:45] node delegable_24 = neq(_delegable_T_24, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1111:67] node _T_201 = eq(delegate, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1112:28] node _T_202 = and(en_24, _T_201) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1112:25] node _T_203 = and(en_24, delegable_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1113:25] node _T_204 = and(_T_203, delegate) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1113:38] when insn_ret : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1117:19] wire ret_prv : UInt @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1118:27] invalidate ret_prv @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1118:27] node _T_205 = bits(io.rw.addr, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1119:43] node _T_206 = eq(_T_205, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1119:32] node _T_207 = and(UInt<1>(0h0), _T_206) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1119:29] when _T_207 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1119:48] node _T_208 = eq(reg_mstatus.v, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1120:13] when _T_208 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1120:29] connect reg_mstatus.sie, reg_mstatus.spie @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1121:25] connect reg_mstatus.spie, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1122:26] connect reg_mstatus.spp, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1123:25] connect ret_prv, reg_mstatus.spp @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1124:17] node _reg_mstatus_v_T = and(UInt<1>(0h0), reg_hstatus.spv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1125:44] connect reg_mstatus.v, _reg_mstatus_v_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1125:23] node _io_evec_T = not(reg_sepc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:28] node _io_evec_T_1 = bits(reg_misa, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:45] node _io_evec_T_2 = mux(_io_evec_T_1, UInt<1>(0h1), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:36] node _io_evec_T_3 = or(_io_evec_T, _io_evec_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:31] node _io_evec_T_4 = not(_io_evec_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:26] connect io.evec, _io_evec_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1126:17] connect reg_hstatus.spv, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1127:25] else : connect reg_vsstatus.sie, reg_vsstatus.spie @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1129:26] connect reg_vsstatus.spie, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1130:27] connect reg_vsstatus.spp, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1131:26] connect ret_prv, reg_vsstatus.spp @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1132:17] connect reg_mstatus.v, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1133:23] node _io_evec_T_5 = not(reg_vsepc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:28] node _io_evec_T_6 = bits(reg_misa, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:45] node _io_evec_T_7 = mux(_io_evec_T_6, UInt<1>(0h1), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:36] node _io_evec_T_8 = or(_io_evec_T_5, _io_evec_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:31] node _io_evec_T_9 = not(_io_evec_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:26] connect io.evec, _io_evec_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1134:17] else : node _T_209 = bits(io.rw.addr, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1136:43] node _T_210 = and(UInt<1>(0h1), _T_209) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1136:30] node _T_211 = bits(io.rw.addr, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1136:61] node _T_212 = and(_T_210, _T_211) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1136:48] when _T_212 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1136:66] connect ret_prv, reg_dcsr.prv @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1137:15] node _reg_mstatus_v_T_1 = and(UInt<1>(0h0), reg_dcsr.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1138:42] node _reg_mstatus_v_T_2 = leq(reg_dcsr.prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1138:72] node _reg_mstatus_v_T_3 = and(_reg_mstatus_v_T_1, _reg_mstatus_v_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1138:56] connect reg_mstatus.v, _reg_mstatus_v_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1138:21] connect reg_debug, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1139:17] node _io_evec_T_10 = not(reg_dpc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:28] node _io_evec_T_11 = bits(reg_misa, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:45] node _io_evec_T_12 = mux(_io_evec_T_11, UInt<1>(0h1), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:36] node _io_evec_T_13 = or(_io_evec_T_10, _io_evec_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:31] node _io_evec_T_14 = not(_io_evec_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:26] connect io.evec, _io_evec_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1140:15] else : node _T_213 = bits(io.rw.addr, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1141:41] node _T_214 = and(UInt<1>(0h0), _T_213) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1141:28] node _T_215 = bits(io.rw.addr, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1141:60] node _T_216 = eq(_T_215, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1141:49] node _T_217 = and(_T_214, _T_216) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1141:46] when _T_217 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1141:65] connect ret_prv, reg_mnstatus.mpp @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1142:15] node _reg_mstatus_v_T_4 = and(UInt<1>(0h0), reg_mnstatus.mpv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1143:42] node _reg_mstatus_v_T_5 = leq(reg_mnstatus.mpp, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1143:82] node _reg_mstatus_v_T_6 = and(_reg_mstatus_v_T_4, _reg_mstatus_v_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1143:62] connect reg_mstatus.v, _reg_mstatus_v_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1143:21] connect reg_rnmie, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1144:17] node _io_evec_T_15 = not(reg_mnepc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:28] node _io_evec_T_16 = bits(reg_misa, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:45] node _io_evec_T_17 = mux(_io_evec_T_16, UInt<1>(0h1), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:36] node _io_evec_T_18 = or(_io_evec_T_15, _io_evec_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:31] node _io_evec_T_19 = not(_io_evec_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:26] connect io.evec, _io_evec_T_19 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1145:15] else : connect reg_mstatus.mie, reg_mstatus.mpie @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1147:23] connect reg_mstatus.mpie, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1148:24] connect reg_mstatus.mpp, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1149:23] connect reg_mstatus.mpv, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1150:23] connect ret_prv, reg_mstatus.mpp @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1151:15] node _reg_mstatus_v_T_7 = and(UInt<1>(0h0), reg_mstatus.mpv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1152:42] node _reg_mstatus_v_T_8 = leq(reg_mstatus.mpp, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1152:80] node _reg_mstatus_v_T_9 = and(_reg_mstatus_v_T_7, _reg_mstatus_v_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1152:61] connect reg_mstatus.v, _reg_mstatus_v_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1152:21] node _io_evec_T_20 = not(reg_mepc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:28] node _io_evec_T_21 = bits(reg_misa, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:45] node _io_evec_T_22 = mux(_io_evec_T_21, UInt<1>(0h1), UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:36] node _io_evec_T_23 = or(_io_evec_T_20, _io_evec_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:31] node _io_evec_T_24 = not(_io_evec_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1667:26] connect io.evec, _io_evec_T_24 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1153:15] connect new_prv, ret_prv @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1156:13] node _T_218 = leq(ret_prv, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1157:34] node _T_219 = and(UInt<1>(0h0), _T_218) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1157:23] when _T_219 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1157:46] connect reg_mstatus.mprv, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1158:24] connect io.time, value_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1162:11] node _io_csr_stall_T = or(reg_wfi, io.status.cease) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1163:27] connect io.csr_stall, _io_csr_stall_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1163:16] regreset io_status_cease_r : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1164:31] when insn_cease : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1164:31] connect io_status_cease_r, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1164:31] connect io.status.cease, io_status_cease_r @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1164:19] connect io.status.wfi, reg_wfi @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1165:17] connect io.customCSRs[0].wen, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1168:12] connect io.customCSRs[0].wdata, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1169:14] connect io.customCSRs[0].value, reg_custom_0 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1170:14] connect io.customCSRs[1].wen, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1168:12] connect io.customCSRs[1].wdata, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1169:14] connect io.customCSRs[1].value, reg_custom_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1170:14] connect io.customCSRs[2].wen, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1168:12] connect io.customCSRs[2].wdata, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1169:14] connect io.customCSRs[2].value, reg_custom_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1170:14] connect io.customCSRs[3].wen, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1168:12] connect io.customCSRs[3].wdata, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1169:14] connect io.customCSRs[3].value, reg_custom_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1170:14] node _io_rw_rdata_T = mux(decoded_addr_85_2, reg_tselect, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_1 = mux(decoded_addr_46_2, read_mapping_1_2, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_2 = mux(decoded_addr_9_2, read_mapping_2_2, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_3 = mux(decoded_addr_106_2, read_mapping_3_2, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_4 = mux(decoded_addr_82_2, reg_misa, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_5 = mux(decoded_addr_88_2, read_mstatus, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_6 = mux(decoded_addr_61_2, read_mtvec, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_7 = mux(decoded_addr_96_2, read_mip, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_8 = mux(decoded_addr_65_2, reg_mie, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_9 = mux(decoded_addr_116_2, reg_mscratch, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_10 = mux(decoded_addr_119_2, read_mapping_10_2, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_11 = mux(decoded_addr_123_2, read_mapping_11_2, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_12 = mux(decoded_addr_24_2, reg_mcause, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_13 = mux(decoded_addr_118_2, io.hartid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_14 = mux(decoded_addr_40_2, debug_csrs_0_2, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_15 = mux(decoded_addr_78_2, debug_csrs_1_2, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_16 = mux(decoded_addr_48_2, reg_dscratch0, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_17 = mux(decoded_addr_30_2, reg_fflags, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_18 = mux(decoded_addr_58_2, reg_frm, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_19 = mux(decoded_addr_87_2, read_fcsr, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_20 = mux(decoded_addr_117_2, reg_mcountinhibit, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_21 = mux(decoded_addr_91_2, value_1, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_22 = mux(decoded_addr_109_2, value, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_23 = mux(decoded_addr_131_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_24 = mux(decoded_addr_15_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_25 = mux(decoded_addr_23_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_26 = mux(decoded_addr_72_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_27 = mux(decoded_addr_43_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_28 = mux(decoded_addr_130_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_29 = mux(decoded_addr_59_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_30 = mux(decoded_addr_99_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_31 = mux(decoded_addr_71_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_32 = mux(decoded_addr_26_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_33 = mux(decoded_addr_0_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_34 = mux(decoded_addr_50_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_35 = mux(decoded_addr_124_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_36 = mux(decoded_addr_113_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_37 = mux(decoded_addr_63_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_38 = mux(decoded_addr_104_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_39 = mux(decoded_addr_79_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_40 = mux(decoded_addr_101_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_41 = mux(decoded_addr_1_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_42 = mux(decoded_addr_14_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_43 = mux(decoded_addr_67_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_44 = mux(decoded_addr_33_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_45 = mux(decoded_addr_42_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_46 = mux(decoded_addr_97_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_47 = mux(decoded_addr_80_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_48 = mux(decoded_addr_70_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_49 = mux(decoded_addr_57_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_50 = mux(decoded_addr_93_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_51 = mux(decoded_addr_110_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_52 = mux(decoded_addr_21_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_53 = mux(decoded_addr_111_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_54 = mux(decoded_addr_22_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_55 = mux(decoded_addr_115_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_56 = mux(decoded_addr_6_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_57 = mux(decoded_addr_52_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_58 = mux(decoded_addr_66_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_59 = mux(decoded_addr_38_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_60 = mux(decoded_addr_100_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_61 = mux(decoded_addr_51_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_62 = mux(decoded_addr_81_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_63 = mux(decoded_addr_133_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_64 = mux(decoded_addr_13_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_65 = mux(decoded_addr_19_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_66 = mux(decoded_addr_28_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_67 = mux(decoded_addr_17_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_68 = mux(decoded_addr_120_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_69 = mux(decoded_addr_134_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_70 = mux(decoded_addr_41_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_71 = mux(decoded_addr_64_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_72 = mux(decoded_addr_90_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_73 = mux(decoded_addr_73_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_74 = mux(decoded_addr_37_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_75 = mux(decoded_addr_54_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_76 = mux(decoded_addr_108_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_77 = mux(decoded_addr_25_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_78 = mux(decoded_addr_5_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_79 = mux(decoded_addr_27_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_80 = mux(decoded_addr_129_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_81 = mux(decoded_addr_105_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_82 = mux(decoded_addr_53_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_83 = mux(decoded_addr_95_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_84 = mux(decoded_addr_77_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_85 = mux(decoded_addr_102_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_86 = mux(decoded_addr_62_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_87 = mux(decoded_addr_44_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_88 = mux(decoded_addr_132_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_89 = mux(decoded_addr_35_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_90 = mux(decoded_addr_47_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_91 = mux(decoded_addr_31_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_92 = mux(decoded_addr_68_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_93 = mux(decoded_addr_84_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_94 = mux(decoded_addr_4_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_95 = mux(decoded_addr_89_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_96 = mux(decoded_addr_107_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_97 = mux(decoded_addr_20_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_98 = mux(decoded_addr_125_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_99 = mux(decoded_addr_10_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_100 = mux(decoded_addr_121_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_101 = mux(decoded_addr_11_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_102 = mux(decoded_addr_55_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_103 = mux(decoded_addr_75_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_104 = mux(decoded_addr_39_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_105 = mux(decoded_addr_94_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_106 = mux(decoded_addr_49_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_107 = mux(decoded_addr_76_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_108 = mux(decoded_addr_128_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_109 = mux(decoded_addr_12_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_110 = mux(decoded_addr_2_2, value_1, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_111 = mux(decoded_addr_56_2, value, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_112 = mux(decoded_addr_127_2, _T_27, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_113 = mux(decoded_addr_8_2, _T_36, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_114 = mux(decoded_addr_92_2, reg_pmp[0].addr, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_115 = mux(decoded_addr_7_2, reg_pmp[1].addr, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_116 = mux(decoded_addr_112_2, reg_pmp[2].addr, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_117 = mux(decoded_addr_74_2, reg_pmp[3].addr, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_118 = mux(decoded_addr_45_2, reg_pmp[4].addr, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_119 = mux(decoded_addr_18_2, reg_pmp[5].addr, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_120 = mux(decoded_addr_122_2, reg_pmp[6].addr, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_121 = mux(decoded_addr_103_2, reg_pmp[7].addr, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_122 = mux(decoded_addr_36_2, read_pmp_15.addr, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_123 = mux(decoded_addr_60_2, read_pmp_15.addr, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_124 = mux(decoded_addr_98_2, read_pmp_15.addr, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_125 = mux(decoded_addr_126_2, read_pmp_15.addr, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_126 = mux(decoded_addr_29_2, read_pmp_15.addr, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_127 = mux(decoded_addr_34_2, read_pmp_15.addr, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_128 = mux(decoded_addr_69_2, read_pmp_15.addr, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_129 = mux(decoded_addr_86_2, read_pmp_15.addr, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_130 = mux(decoded_addr_16_2, reg_custom_0, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_131 = mux(decoded_addr_3_2, reg_custom_1, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_132 = mux(decoded_addr_32_2, reg_custom_2, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_133 = mux(decoded_addr_114_2, reg_custom_3, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_134 = mux(decoded_addr_83_2, UInt<1>(0h0), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_135 = or(_io_rw_rdata_T, _io_rw_rdata_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_136 = or(_io_rw_rdata_T_135, _io_rw_rdata_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_137 = or(_io_rw_rdata_T_136, _io_rw_rdata_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_138 = or(_io_rw_rdata_T_137, _io_rw_rdata_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_139 = or(_io_rw_rdata_T_138, _io_rw_rdata_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_140 = or(_io_rw_rdata_T_139, _io_rw_rdata_T_6) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_141 = or(_io_rw_rdata_T_140, _io_rw_rdata_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_142 = or(_io_rw_rdata_T_141, _io_rw_rdata_T_8) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_143 = or(_io_rw_rdata_T_142, _io_rw_rdata_T_9) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_144 = or(_io_rw_rdata_T_143, _io_rw_rdata_T_10) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_145 = or(_io_rw_rdata_T_144, _io_rw_rdata_T_11) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_146 = or(_io_rw_rdata_T_145, _io_rw_rdata_T_12) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_147 = or(_io_rw_rdata_T_146, _io_rw_rdata_T_13) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_148 = or(_io_rw_rdata_T_147, _io_rw_rdata_T_14) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_149 = or(_io_rw_rdata_T_148, _io_rw_rdata_T_15) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_150 = or(_io_rw_rdata_T_149, _io_rw_rdata_T_16) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_151 = or(_io_rw_rdata_T_150, _io_rw_rdata_T_17) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_152 = or(_io_rw_rdata_T_151, _io_rw_rdata_T_18) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_153 = or(_io_rw_rdata_T_152, _io_rw_rdata_T_19) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_154 = or(_io_rw_rdata_T_153, _io_rw_rdata_T_20) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_155 = or(_io_rw_rdata_T_154, _io_rw_rdata_T_21) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_156 = or(_io_rw_rdata_T_155, _io_rw_rdata_T_22) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_157 = or(_io_rw_rdata_T_156, _io_rw_rdata_T_23) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_158 = or(_io_rw_rdata_T_157, _io_rw_rdata_T_24) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_159 = or(_io_rw_rdata_T_158, _io_rw_rdata_T_25) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_160 = or(_io_rw_rdata_T_159, _io_rw_rdata_T_26) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_161 = or(_io_rw_rdata_T_160, _io_rw_rdata_T_27) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_162 = or(_io_rw_rdata_T_161, _io_rw_rdata_T_28) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_163 = or(_io_rw_rdata_T_162, _io_rw_rdata_T_29) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_164 = or(_io_rw_rdata_T_163, _io_rw_rdata_T_30) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_165 = or(_io_rw_rdata_T_164, _io_rw_rdata_T_31) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_166 = or(_io_rw_rdata_T_165, _io_rw_rdata_T_32) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_167 = or(_io_rw_rdata_T_166, _io_rw_rdata_T_33) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_168 = or(_io_rw_rdata_T_167, _io_rw_rdata_T_34) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_169 = or(_io_rw_rdata_T_168, _io_rw_rdata_T_35) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_170 = or(_io_rw_rdata_T_169, _io_rw_rdata_T_36) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_171 = or(_io_rw_rdata_T_170, _io_rw_rdata_T_37) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_172 = or(_io_rw_rdata_T_171, _io_rw_rdata_T_38) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_173 = or(_io_rw_rdata_T_172, _io_rw_rdata_T_39) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_174 = or(_io_rw_rdata_T_173, _io_rw_rdata_T_40) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_175 = or(_io_rw_rdata_T_174, _io_rw_rdata_T_41) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_176 = or(_io_rw_rdata_T_175, _io_rw_rdata_T_42) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_177 = or(_io_rw_rdata_T_176, _io_rw_rdata_T_43) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_178 = or(_io_rw_rdata_T_177, _io_rw_rdata_T_44) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_179 = or(_io_rw_rdata_T_178, _io_rw_rdata_T_45) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_180 = or(_io_rw_rdata_T_179, _io_rw_rdata_T_46) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_181 = or(_io_rw_rdata_T_180, _io_rw_rdata_T_47) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_182 = or(_io_rw_rdata_T_181, _io_rw_rdata_T_48) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_183 = or(_io_rw_rdata_T_182, _io_rw_rdata_T_49) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_184 = or(_io_rw_rdata_T_183, _io_rw_rdata_T_50) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_185 = or(_io_rw_rdata_T_184, _io_rw_rdata_T_51) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_186 = or(_io_rw_rdata_T_185, _io_rw_rdata_T_52) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_187 = or(_io_rw_rdata_T_186, _io_rw_rdata_T_53) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_188 = or(_io_rw_rdata_T_187, _io_rw_rdata_T_54) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_189 = or(_io_rw_rdata_T_188, _io_rw_rdata_T_55) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_190 = or(_io_rw_rdata_T_189, _io_rw_rdata_T_56) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_191 = or(_io_rw_rdata_T_190, _io_rw_rdata_T_57) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_192 = or(_io_rw_rdata_T_191, _io_rw_rdata_T_58) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_193 = or(_io_rw_rdata_T_192, _io_rw_rdata_T_59) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_194 = or(_io_rw_rdata_T_193, _io_rw_rdata_T_60) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_195 = or(_io_rw_rdata_T_194, _io_rw_rdata_T_61) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_196 = or(_io_rw_rdata_T_195, _io_rw_rdata_T_62) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_197 = or(_io_rw_rdata_T_196, _io_rw_rdata_T_63) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_198 = or(_io_rw_rdata_T_197, _io_rw_rdata_T_64) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_199 = or(_io_rw_rdata_T_198, _io_rw_rdata_T_65) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_200 = or(_io_rw_rdata_T_199, _io_rw_rdata_T_66) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_201 = or(_io_rw_rdata_T_200, _io_rw_rdata_T_67) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_202 = or(_io_rw_rdata_T_201, _io_rw_rdata_T_68) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_203 = or(_io_rw_rdata_T_202, _io_rw_rdata_T_69) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_204 = or(_io_rw_rdata_T_203, _io_rw_rdata_T_70) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_205 = or(_io_rw_rdata_T_204, _io_rw_rdata_T_71) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_206 = or(_io_rw_rdata_T_205, _io_rw_rdata_T_72) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_207 = or(_io_rw_rdata_T_206, _io_rw_rdata_T_73) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_208 = or(_io_rw_rdata_T_207, _io_rw_rdata_T_74) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_209 = or(_io_rw_rdata_T_208, _io_rw_rdata_T_75) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_210 = or(_io_rw_rdata_T_209, _io_rw_rdata_T_76) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_211 = or(_io_rw_rdata_T_210, _io_rw_rdata_T_77) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_212 = or(_io_rw_rdata_T_211, _io_rw_rdata_T_78) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_213 = or(_io_rw_rdata_T_212, _io_rw_rdata_T_79) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_214 = or(_io_rw_rdata_T_213, _io_rw_rdata_T_80) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_215 = or(_io_rw_rdata_T_214, _io_rw_rdata_T_81) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_216 = or(_io_rw_rdata_T_215, _io_rw_rdata_T_82) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_217 = or(_io_rw_rdata_T_216, _io_rw_rdata_T_83) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_218 = or(_io_rw_rdata_T_217, _io_rw_rdata_T_84) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_219 = or(_io_rw_rdata_T_218, _io_rw_rdata_T_85) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_220 = or(_io_rw_rdata_T_219, _io_rw_rdata_T_86) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_221 = or(_io_rw_rdata_T_220, _io_rw_rdata_T_87) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_222 = or(_io_rw_rdata_T_221, _io_rw_rdata_T_88) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_223 = or(_io_rw_rdata_T_222, _io_rw_rdata_T_89) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_224 = or(_io_rw_rdata_T_223, _io_rw_rdata_T_90) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_225 = or(_io_rw_rdata_T_224, _io_rw_rdata_T_91) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_226 = or(_io_rw_rdata_T_225, _io_rw_rdata_T_92) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_227 = or(_io_rw_rdata_T_226, _io_rw_rdata_T_93) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_228 = or(_io_rw_rdata_T_227, _io_rw_rdata_T_94) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_229 = or(_io_rw_rdata_T_228, _io_rw_rdata_T_95) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_230 = or(_io_rw_rdata_T_229, _io_rw_rdata_T_96) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_231 = or(_io_rw_rdata_T_230, _io_rw_rdata_T_97) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_232 = or(_io_rw_rdata_T_231, _io_rw_rdata_T_98) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_233 = or(_io_rw_rdata_T_232, _io_rw_rdata_T_99) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_234 = or(_io_rw_rdata_T_233, _io_rw_rdata_T_100) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_235 = or(_io_rw_rdata_T_234, _io_rw_rdata_T_101) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_236 = or(_io_rw_rdata_T_235, _io_rw_rdata_T_102) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_237 = or(_io_rw_rdata_T_236, _io_rw_rdata_T_103) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_238 = or(_io_rw_rdata_T_237, _io_rw_rdata_T_104) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_239 = or(_io_rw_rdata_T_238, _io_rw_rdata_T_105) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_240 = or(_io_rw_rdata_T_239, _io_rw_rdata_T_106) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_241 = or(_io_rw_rdata_T_240, _io_rw_rdata_T_107) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_242 = or(_io_rw_rdata_T_241, _io_rw_rdata_T_108) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_243 = or(_io_rw_rdata_T_242, _io_rw_rdata_T_109) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_244 = or(_io_rw_rdata_T_243, _io_rw_rdata_T_110) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_245 = or(_io_rw_rdata_T_244, _io_rw_rdata_T_111) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_246 = or(_io_rw_rdata_T_245, _io_rw_rdata_T_112) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_247 = or(_io_rw_rdata_T_246, _io_rw_rdata_T_113) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_248 = or(_io_rw_rdata_T_247, _io_rw_rdata_T_114) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_249 = or(_io_rw_rdata_T_248, _io_rw_rdata_T_115) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_250 = or(_io_rw_rdata_T_249, _io_rw_rdata_T_116) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_251 = or(_io_rw_rdata_T_250, _io_rw_rdata_T_117) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_252 = or(_io_rw_rdata_T_251, _io_rw_rdata_T_118) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_253 = or(_io_rw_rdata_T_252, _io_rw_rdata_T_119) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_254 = or(_io_rw_rdata_T_253, _io_rw_rdata_T_120) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_255 = or(_io_rw_rdata_T_254, _io_rw_rdata_T_121) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_256 = or(_io_rw_rdata_T_255, _io_rw_rdata_T_122) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_257 = or(_io_rw_rdata_T_256, _io_rw_rdata_T_123) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_258 = or(_io_rw_rdata_T_257, _io_rw_rdata_T_124) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_259 = or(_io_rw_rdata_T_258, _io_rw_rdata_T_125) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_260 = or(_io_rw_rdata_T_259, _io_rw_rdata_T_126) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_261 = or(_io_rw_rdata_T_260, _io_rw_rdata_T_127) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_262 = or(_io_rw_rdata_T_261, _io_rw_rdata_T_128) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_263 = or(_io_rw_rdata_T_262, _io_rw_rdata_T_129) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_264 = or(_io_rw_rdata_T_263, _io_rw_rdata_T_130) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_265 = or(_io_rw_rdata_T_264, _io_rw_rdata_T_131) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_266 = or(_io_rw_rdata_T_265, _io_rw_rdata_T_132) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_267 = or(_io_rw_rdata_T_266, _io_rw_rdata_T_133) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _io_rw_rdata_T_268 = or(_io_rw_rdata_T_267, _io_rw_rdata_T_134) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _io_rw_rdata_WIRE : UInt @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _io_rw_rdata_WIRE, _io_rw_rdata_T_268 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect io.rw.rdata, _io_rw_rdata_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1179:15] node _T_220 = andr(UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_221 = eq(_T_220, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_221 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_222 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_223 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_224 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_225 = or(_T_222, _T_223) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_226 = or(_T_225, _T_224) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_227 = eq(io.rw.addr, UInt<11>(0h7a0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_228 = and(_T_226, _T_227) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_229 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_230 = eq(io.rw.addr, UInt<11>(0h7a0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_231 = and(_T_229, _T_230) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_232 = andr(UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_233 = eq(_T_232, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_233 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_234 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_235 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_236 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_237 = or(_T_234, _T_235) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_238 = or(_T_237, _T_236) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_239 = eq(io.rw.addr, UInt<11>(0h7a1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_240 = and(_T_238, _T_239) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_241 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_242 = eq(io.rw.addr, UInt<11>(0h7a1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_243 = and(_T_241, _T_242) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_244 = andr(UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_245 = eq(_T_244, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_245 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_246 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_247 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_248 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_249 = or(_T_246, _T_247) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_250 = or(_T_249, _T_248) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_251 = eq(io.rw.addr, UInt<11>(0h7a2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_252 = and(_T_250, _T_251) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_253 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_254 = eq(io.rw.addr, UInt<11>(0h7a2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_255 = and(_T_253, _T_254) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_256 = andr(UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_257 = eq(_T_256, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_257 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_258 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_259 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_260 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_261 = or(_T_258, _T_259) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_262 = or(_T_261, _T_260) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_263 = eq(io.rw.addr, UInt<11>(0h7a3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_264 = and(_T_262, _T_263) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_265 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_266 = eq(io.rw.addr, UInt<11>(0h7a3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_267 = and(_T_265, _T_266) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_268 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_269 = eq(_T_268, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_269 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_270 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_271 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_272 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_273 = or(_T_270, _T_271) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_274 = or(_T_273, _T_272) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_275 = eq(io.rw.addr, UInt<10>(0h301)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_276 = and(_T_274, _T_275) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_277 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_278 = eq(io.rw.addr, UInt<10>(0h301)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_279 = and(_T_277, _T_278) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_280 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_281 = eq(_T_280, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_281 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_282 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_283 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_284 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_285 = or(_T_282, _T_283) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_286 = or(_T_285, _T_284) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_287 = eq(io.rw.addr, UInt<10>(0h300)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_288 = and(_T_286, _T_287) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_289 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_290 = eq(io.rw.addr, UInt<10>(0h300)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_291 = and(_T_289, _T_290) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_292 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_293 = eq(_T_292, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_293 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_294 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_295 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_296 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_297 = or(_T_294, _T_295) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_298 = or(_T_297, _T_296) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_299 = eq(io.rw.addr, UInt<10>(0h305)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_300 = and(_T_298, _T_299) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_301 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_302 = eq(io.rw.addr, UInt<10>(0h305)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_303 = and(_T_301, _T_302) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_304 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_305 = eq(_T_304, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_305 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_306 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_307 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_308 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_309 = or(_T_306, _T_307) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_310 = or(_T_309, _T_308) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_311 = eq(io.rw.addr, UInt<10>(0h344)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_312 = and(_T_310, _T_311) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_313 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_314 = eq(io.rw.addr, UInt<10>(0h344)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_315 = and(_T_313, _T_314) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_316 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_317 = eq(_T_316, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_317 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_318 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_319 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_320 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_321 = or(_T_318, _T_319) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_322 = or(_T_321, _T_320) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_323 = eq(io.rw.addr, UInt<10>(0h304)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_324 = and(_T_322, _T_323) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_325 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_326 = eq(io.rw.addr, UInt<10>(0h304)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_327 = and(_T_325, _T_326) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_328 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_329 = eq(_T_328, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_329 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_330 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_331 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_332 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_333 = or(_T_330, _T_331) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_334 = or(_T_333, _T_332) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_335 = eq(io.rw.addr, UInt<10>(0h340)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_336 = and(_T_334, _T_335) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_337 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_338 = eq(io.rw.addr, UInt<10>(0h340)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_339 = and(_T_337, _T_338) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_340 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_341 = eq(_T_340, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_341 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_342 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_343 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_344 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_345 = or(_T_342, _T_343) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_346 = or(_T_345, _T_344) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_347 = eq(io.rw.addr, UInt<10>(0h341)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_348 = and(_T_346, _T_347) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_349 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_350 = eq(io.rw.addr, UInt<10>(0h341)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_351 = and(_T_349, _T_350) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_352 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_353 = eq(_T_352, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_353 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_354 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_355 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_356 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_357 = or(_T_354, _T_355) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_358 = or(_T_357, _T_356) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_359 = eq(io.rw.addr, UInt<10>(0h343)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_360 = and(_T_358, _T_359) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_361 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_362 = eq(io.rw.addr, UInt<10>(0h343)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_363 = and(_T_361, _T_362) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_364 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_365 = eq(_T_364, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_365 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_366 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_367 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_368 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_369 = or(_T_366, _T_367) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_370 = or(_T_369, _T_368) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_371 = eq(io.rw.addr, UInt<10>(0h342)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_372 = and(_T_370, _T_371) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_373 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_374 = eq(io.rw.addr, UInt<10>(0h342)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_375 = and(_T_373, _T_374) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_376 = andr(UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_377 = eq(_T_376, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_377 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_378 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_379 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_380 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_381 = or(_T_378, _T_379) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_382 = or(_T_381, _T_380) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_383 = eq(io.rw.addr, UInt<12>(0hf14)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_384 = and(_T_382, _T_383) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_385 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_386 = eq(io.rw.addr, UInt<12>(0hf14)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_387 = and(_T_385, _T_386) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_388 = andr(UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_389 = eq(_T_388, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_389 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_390 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_391 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_392 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_393 = or(_T_390, _T_391) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_394 = or(_T_393, _T_392) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_395 = eq(io.rw.addr, UInt<11>(0h7b0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_396 = and(_T_394, _T_395) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_397 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_398 = eq(io.rw.addr, UInt<11>(0h7b0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_399 = and(_T_397, _T_398) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_400 = andr(UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_401 = eq(_T_400, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_401 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_402 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_403 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_404 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_405 = or(_T_402, _T_403) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_406 = or(_T_405, _T_404) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_407 = eq(io.rw.addr, UInt<11>(0h7b1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_408 = and(_T_406, _T_407) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_409 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_410 = eq(io.rw.addr, UInt<11>(0h7b1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_411 = and(_T_409, _T_410) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_412 = andr(UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_413 = eq(_T_412, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_413 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_414 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_415 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_416 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_417 = or(_T_414, _T_415) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_418 = or(_T_417, _T_416) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_419 = eq(io.rw.addr, UInt<11>(0h7b2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_420 = and(_T_418, _T_419) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_421 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_422 = eq(io.rw.addr, UInt<11>(0h7b2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_423 = and(_T_421, _T_422) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_424 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_425 = eq(_T_424, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_425 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_426 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_427 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_428 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_429 = or(_T_426, _T_427) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_430 = or(_T_429, _T_428) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_431 = eq(io.rw.addr, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_432 = and(_T_430, _T_431) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_433 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_434 = eq(io.rw.addr, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_435 = and(_T_433, _T_434) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_436 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_437 = eq(_T_436, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_437 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_438 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_439 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_440 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_441 = or(_T_438, _T_439) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_442 = or(_T_441, _T_440) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_443 = eq(io.rw.addr, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_444 = and(_T_442, _T_443) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_445 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_446 = eq(io.rw.addr, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_447 = and(_T_445, _T_446) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_448 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_449 = eq(_T_448, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_449 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_450 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_451 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_452 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_453 = or(_T_450, _T_451) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_454 = or(_T_453, _T_452) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_455 = eq(io.rw.addr, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_456 = and(_T_454, _T_455) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_457 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_458 = eq(io.rw.addr, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_459 = and(_T_457, _T_458) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_460 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_461 = eq(_T_460, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_461 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_462 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_463 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_464 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_465 = or(_T_462, _T_463) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_466 = or(_T_465, _T_464) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_467 = eq(io.rw.addr, UInt<10>(0h320)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_468 = and(_T_466, _T_467) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_469 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_470 = eq(io.rw.addr, UInt<10>(0h320)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_471 = and(_T_469, _T_470) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_472 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_473 = eq(_T_472, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_473 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_474 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_475 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_476 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_477 = or(_T_474, _T_475) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_478 = or(_T_477, _T_476) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_479 = eq(io.rw.addr, UInt<12>(0hb00)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_480 = and(_T_478, _T_479) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_481 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_482 = eq(io.rw.addr, UInt<12>(0hb00)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_483 = and(_T_481, _T_482) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_484 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_485 = eq(_T_484, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_485 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_486 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_487 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_488 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_489 = or(_T_486, _T_487) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_490 = or(_T_489, _T_488) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_491 = eq(io.rw.addr, UInt<12>(0hb02)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_492 = and(_T_490, _T_491) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_493 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_494 = eq(io.rw.addr, UInt<12>(0hb02)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_495 = and(_T_493, _T_494) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_496 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_497 = eq(_T_496, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_497 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_498 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_499 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_500 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_501 = or(_T_498, _T_499) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_502 = or(_T_501, _T_500) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_503 = eq(io.rw.addr, UInt<10>(0h323)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_504 = and(_T_502, _T_503) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_505 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_506 = eq(io.rw.addr, UInt<10>(0h323)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_507 = and(_T_505, _T_506) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_508 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_509 = eq(_T_508, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_509 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_510 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_511 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_512 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_513 = or(_T_510, _T_511) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_514 = or(_T_513, _T_512) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_515 = eq(io.rw.addr, UInt<12>(0hb03)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_516 = and(_T_514, _T_515) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_517 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_518 = eq(io.rw.addr, UInt<12>(0hb03)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_519 = and(_T_517, _T_518) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_520 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_521 = eq(_T_520, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_521 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_522 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_523 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_524 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_525 = or(_T_522, _T_523) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_526 = or(_T_525, _T_524) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_527 = eq(io.rw.addr, UInt<10>(0h324)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_528 = and(_T_526, _T_527) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_529 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_530 = eq(io.rw.addr, UInt<10>(0h324)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_531 = and(_T_529, _T_530) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_532 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_533 = eq(_T_532, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_533 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_534 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_535 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_536 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_537 = or(_T_534, _T_535) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_538 = or(_T_537, _T_536) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_539 = eq(io.rw.addr, UInt<12>(0hb04)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_540 = and(_T_538, _T_539) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_541 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_542 = eq(io.rw.addr, UInt<12>(0hb04)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_543 = and(_T_541, _T_542) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_544 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_545 = eq(_T_544, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_545 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_546 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_547 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_548 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_549 = or(_T_546, _T_547) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_550 = or(_T_549, _T_548) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_551 = eq(io.rw.addr, UInt<10>(0h325)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_552 = and(_T_550, _T_551) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_553 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_554 = eq(io.rw.addr, UInt<10>(0h325)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_555 = and(_T_553, _T_554) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_556 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_557 = eq(_T_556, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_557 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_558 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_559 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_560 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_561 = or(_T_558, _T_559) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_562 = or(_T_561, _T_560) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_563 = eq(io.rw.addr, UInt<12>(0hb05)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_564 = and(_T_562, _T_563) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_565 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_566 = eq(io.rw.addr, UInt<12>(0hb05)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_567 = and(_T_565, _T_566) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_568 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_569 = eq(_T_568, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_569 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_570 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_571 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_572 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_573 = or(_T_570, _T_571) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_574 = or(_T_573, _T_572) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_575 = eq(io.rw.addr, UInt<10>(0h326)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_576 = and(_T_574, _T_575) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_577 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_578 = eq(io.rw.addr, UInt<10>(0h326)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_579 = and(_T_577, _T_578) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_580 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_581 = eq(_T_580, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_581 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_582 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_583 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_584 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_585 = or(_T_582, _T_583) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_586 = or(_T_585, _T_584) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_587 = eq(io.rw.addr, UInt<12>(0hb06)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_588 = and(_T_586, _T_587) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_589 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_590 = eq(io.rw.addr, UInt<12>(0hb06)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_591 = and(_T_589, _T_590) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_592 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_593 = eq(_T_592, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_593 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_594 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_595 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_596 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_597 = or(_T_594, _T_595) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_598 = or(_T_597, _T_596) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_599 = eq(io.rw.addr, UInt<10>(0h327)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_600 = and(_T_598, _T_599) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_601 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_602 = eq(io.rw.addr, UInt<10>(0h327)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_603 = and(_T_601, _T_602) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_604 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_605 = eq(_T_604, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_605 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_606 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_607 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_608 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_609 = or(_T_606, _T_607) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_610 = or(_T_609, _T_608) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_611 = eq(io.rw.addr, UInt<12>(0hb07)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_612 = and(_T_610, _T_611) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_613 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_614 = eq(io.rw.addr, UInt<12>(0hb07)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_615 = and(_T_613, _T_614) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_616 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_617 = eq(_T_616, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_617 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_618 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_619 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_620 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_621 = or(_T_618, _T_619) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_622 = or(_T_621, _T_620) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_623 = eq(io.rw.addr, UInt<10>(0h328)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_624 = and(_T_622, _T_623) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_625 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_626 = eq(io.rw.addr, UInt<10>(0h328)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_627 = and(_T_625, _T_626) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_628 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_629 = eq(_T_628, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_629 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_630 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_631 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_632 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_633 = or(_T_630, _T_631) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_634 = or(_T_633, _T_632) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_635 = eq(io.rw.addr, UInt<12>(0hb08)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_636 = and(_T_634, _T_635) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_637 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_638 = eq(io.rw.addr, UInt<12>(0hb08)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_639 = and(_T_637, _T_638) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_640 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_641 = eq(_T_640, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_641 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_642 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_643 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_644 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_645 = or(_T_642, _T_643) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_646 = or(_T_645, _T_644) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_647 = eq(io.rw.addr, UInt<10>(0h329)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_648 = and(_T_646, _T_647) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_649 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_650 = eq(io.rw.addr, UInt<10>(0h329)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_651 = and(_T_649, _T_650) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_652 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_653 = eq(_T_652, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_653 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_654 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_655 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_656 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_657 = or(_T_654, _T_655) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_658 = or(_T_657, _T_656) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_659 = eq(io.rw.addr, UInt<12>(0hb09)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_660 = and(_T_658, _T_659) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_661 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_662 = eq(io.rw.addr, UInt<12>(0hb09)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_663 = and(_T_661, _T_662) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_664 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_665 = eq(_T_664, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_665 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_666 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_667 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_668 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_669 = or(_T_666, _T_667) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_670 = or(_T_669, _T_668) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_671 = eq(io.rw.addr, UInt<10>(0h32a)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_672 = and(_T_670, _T_671) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_673 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_674 = eq(io.rw.addr, UInt<10>(0h32a)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_675 = and(_T_673, _T_674) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_676 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_677 = eq(_T_676, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_677 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_678 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_679 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_680 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_681 = or(_T_678, _T_679) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_682 = or(_T_681, _T_680) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_683 = eq(io.rw.addr, UInt<12>(0hb0a)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_684 = and(_T_682, _T_683) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_685 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_686 = eq(io.rw.addr, UInt<12>(0hb0a)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_687 = and(_T_685, _T_686) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_688 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_689 = eq(_T_688, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_689 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_690 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_691 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_692 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_693 = or(_T_690, _T_691) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_694 = or(_T_693, _T_692) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_695 = eq(io.rw.addr, UInt<10>(0h32b)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_696 = and(_T_694, _T_695) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_697 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_698 = eq(io.rw.addr, UInt<10>(0h32b)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_699 = and(_T_697, _T_698) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_700 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_701 = eq(_T_700, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_701 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_702 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_703 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_704 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_705 = or(_T_702, _T_703) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_706 = or(_T_705, _T_704) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_707 = eq(io.rw.addr, UInt<12>(0hb0b)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_708 = and(_T_706, _T_707) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_709 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_710 = eq(io.rw.addr, UInt<12>(0hb0b)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_711 = and(_T_709, _T_710) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_712 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_713 = eq(_T_712, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_713 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_714 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_715 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_716 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_717 = or(_T_714, _T_715) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_718 = or(_T_717, _T_716) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_719 = eq(io.rw.addr, UInt<10>(0h32c)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_720 = and(_T_718, _T_719) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_721 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_722 = eq(io.rw.addr, UInt<10>(0h32c)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_723 = and(_T_721, _T_722) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_724 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_725 = eq(_T_724, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_725 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_726 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_727 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_728 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_729 = or(_T_726, _T_727) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_730 = or(_T_729, _T_728) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_731 = eq(io.rw.addr, UInt<12>(0hb0c)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_732 = and(_T_730, _T_731) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_733 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_734 = eq(io.rw.addr, UInt<12>(0hb0c)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_735 = and(_T_733, _T_734) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_736 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_737 = eq(_T_736, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_737 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_738 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_739 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_740 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_741 = or(_T_738, _T_739) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_742 = or(_T_741, _T_740) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_743 = eq(io.rw.addr, UInt<10>(0h32d)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_744 = and(_T_742, _T_743) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_745 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_746 = eq(io.rw.addr, UInt<10>(0h32d)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_747 = and(_T_745, _T_746) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_748 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_749 = eq(_T_748, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_749 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_750 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_751 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_752 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_753 = or(_T_750, _T_751) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_754 = or(_T_753, _T_752) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_755 = eq(io.rw.addr, UInt<12>(0hb0d)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_756 = and(_T_754, _T_755) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_757 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_758 = eq(io.rw.addr, UInt<12>(0hb0d)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_759 = and(_T_757, _T_758) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_760 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_761 = eq(_T_760, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_761 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_762 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_763 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_764 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_765 = or(_T_762, _T_763) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_766 = or(_T_765, _T_764) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_767 = eq(io.rw.addr, UInt<10>(0h32e)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_768 = and(_T_766, _T_767) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_769 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_770 = eq(io.rw.addr, UInt<10>(0h32e)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_771 = and(_T_769, _T_770) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_772 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_773 = eq(_T_772, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_773 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_774 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_775 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_776 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_777 = or(_T_774, _T_775) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_778 = or(_T_777, _T_776) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_779 = eq(io.rw.addr, UInt<12>(0hb0e)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_780 = and(_T_778, _T_779) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_781 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_782 = eq(io.rw.addr, UInt<12>(0hb0e)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_783 = and(_T_781, _T_782) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_784 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_785 = eq(_T_784, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_785 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_786 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_787 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_788 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_789 = or(_T_786, _T_787) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_790 = or(_T_789, _T_788) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_791 = eq(io.rw.addr, UInt<10>(0h32f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_792 = and(_T_790, _T_791) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_793 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_794 = eq(io.rw.addr, UInt<10>(0h32f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_795 = and(_T_793, _T_794) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_796 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_797 = eq(_T_796, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_797 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_798 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_799 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_800 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_801 = or(_T_798, _T_799) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_802 = or(_T_801, _T_800) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_803 = eq(io.rw.addr, UInt<12>(0hb0f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_804 = and(_T_802, _T_803) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_805 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_806 = eq(io.rw.addr, UInt<12>(0hb0f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_807 = and(_T_805, _T_806) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_808 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_809 = eq(_T_808, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_809 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_810 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_811 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_812 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_813 = or(_T_810, _T_811) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_814 = or(_T_813, _T_812) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_815 = eq(io.rw.addr, UInt<10>(0h330)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_816 = and(_T_814, _T_815) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_817 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_818 = eq(io.rw.addr, UInt<10>(0h330)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_819 = and(_T_817, _T_818) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_820 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_821 = eq(_T_820, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_821 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_822 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_823 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_824 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_825 = or(_T_822, _T_823) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_826 = or(_T_825, _T_824) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_827 = eq(io.rw.addr, UInt<12>(0hb10)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_828 = and(_T_826, _T_827) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_829 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_830 = eq(io.rw.addr, UInt<12>(0hb10)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_831 = and(_T_829, _T_830) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_832 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_833 = eq(_T_832, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_833 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_834 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_835 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_836 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_837 = or(_T_834, _T_835) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_838 = or(_T_837, _T_836) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_839 = eq(io.rw.addr, UInt<10>(0h331)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_840 = and(_T_838, _T_839) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_841 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_842 = eq(io.rw.addr, UInt<10>(0h331)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_843 = and(_T_841, _T_842) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_844 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_845 = eq(_T_844, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_845 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_846 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_847 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_848 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_849 = or(_T_846, _T_847) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_850 = or(_T_849, _T_848) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_851 = eq(io.rw.addr, UInt<12>(0hb11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_852 = and(_T_850, _T_851) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_853 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_854 = eq(io.rw.addr, UInt<12>(0hb11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_855 = and(_T_853, _T_854) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_856 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_857 = eq(_T_856, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_857 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_858 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_859 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_860 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_861 = or(_T_858, _T_859) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_862 = or(_T_861, _T_860) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_863 = eq(io.rw.addr, UInt<10>(0h332)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_864 = and(_T_862, _T_863) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_865 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_866 = eq(io.rw.addr, UInt<10>(0h332)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_867 = and(_T_865, _T_866) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_868 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_869 = eq(_T_868, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_869 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_870 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_871 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_872 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_873 = or(_T_870, _T_871) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_874 = or(_T_873, _T_872) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_875 = eq(io.rw.addr, UInt<12>(0hb12)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_876 = and(_T_874, _T_875) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_877 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_878 = eq(io.rw.addr, UInt<12>(0hb12)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_879 = and(_T_877, _T_878) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_880 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_881 = eq(_T_880, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_881 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_882 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_883 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_884 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_885 = or(_T_882, _T_883) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_886 = or(_T_885, _T_884) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_887 = eq(io.rw.addr, UInt<10>(0h333)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_888 = and(_T_886, _T_887) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_889 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_890 = eq(io.rw.addr, UInt<10>(0h333)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_891 = and(_T_889, _T_890) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_892 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_893 = eq(_T_892, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_893 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_894 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_895 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_896 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_897 = or(_T_894, _T_895) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_898 = or(_T_897, _T_896) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_899 = eq(io.rw.addr, UInt<12>(0hb13)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_900 = and(_T_898, _T_899) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_901 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_902 = eq(io.rw.addr, UInt<12>(0hb13)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_903 = and(_T_901, _T_902) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_904 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_905 = eq(_T_904, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_905 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_906 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_907 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_908 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_909 = or(_T_906, _T_907) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_910 = or(_T_909, _T_908) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_911 = eq(io.rw.addr, UInt<10>(0h334)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_912 = and(_T_910, _T_911) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_913 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_914 = eq(io.rw.addr, UInt<10>(0h334)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_915 = and(_T_913, _T_914) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_916 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_917 = eq(_T_916, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_917 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_918 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_919 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_920 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_921 = or(_T_918, _T_919) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_922 = or(_T_921, _T_920) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_923 = eq(io.rw.addr, UInt<12>(0hb14)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_924 = and(_T_922, _T_923) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_925 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_926 = eq(io.rw.addr, UInt<12>(0hb14)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_927 = and(_T_925, _T_926) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_928 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_929 = eq(_T_928, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_929 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_930 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_931 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_932 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_933 = or(_T_930, _T_931) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_934 = or(_T_933, _T_932) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_935 = eq(io.rw.addr, UInt<10>(0h335)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_936 = and(_T_934, _T_935) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_937 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_938 = eq(io.rw.addr, UInt<10>(0h335)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_939 = and(_T_937, _T_938) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_940 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_941 = eq(_T_940, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_941 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_942 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_943 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_944 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_945 = or(_T_942, _T_943) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_946 = or(_T_945, _T_944) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_947 = eq(io.rw.addr, UInt<12>(0hb15)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_948 = and(_T_946, _T_947) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_949 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_950 = eq(io.rw.addr, UInt<12>(0hb15)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_951 = and(_T_949, _T_950) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_952 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_953 = eq(_T_952, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_953 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_954 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_955 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_956 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_957 = or(_T_954, _T_955) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_958 = or(_T_957, _T_956) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_959 = eq(io.rw.addr, UInt<10>(0h336)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_960 = and(_T_958, _T_959) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_961 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_962 = eq(io.rw.addr, UInt<10>(0h336)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_963 = and(_T_961, _T_962) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_964 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_965 = eq(_T_964, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_965 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_966 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_967 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_968 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_969 = or(_T_966, _T_967) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_970 = or(_T_969, _T_968) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_971 = eq(io.rw.addr, UInt<12>(0hb16)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_972 = and(_T_970, _T_971) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_973 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_974 = eq(io.rw.addr, UInt<12>(0hb16)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_975 = and(_T_973, _T_974) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_976 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_977 = eq(_T_976, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_977 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_978 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_979 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_980 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_981 = or(_T_978, _T_979) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_982 = or(_T_981, _T_980) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_983 = eq(io.rw.addr, UInt<10>(0h337)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_984 = and(_T_982, _T_983) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_985 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_986 = eq(io.rw.addr, UInt<10>(0h337)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_987 = and(_T_985, _T_986) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_988 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_989 = eq(_T_988, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_989 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_990 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_991 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_992 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_993 = or(_T_990, _T_991) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_994 = or(_T_993, _T_992) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_995 = eq(io.rw.addr, UInt<12>(0hb17)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_996 = and(_T_994, _T_995) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_997 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_998 = eq(io.rw.addr, UInt<12>(0hb17)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_999 = and(_T_997, _T_998) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1000 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1001 = eq(_T_1000, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1001 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1002 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1003 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1004 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1005 = or(_T_1002, _T_1003) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1006 = or(_T_1005, _T_1004) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1007 = eq(io.rw.addr, UInt<10>(0h338)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1008 = and(_T_1006, _T_1007) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1009 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1010 = eq(io.rw.addr, UInt<10>(0h338)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1011 = and(_T_1009, _T_1010) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1012 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1013 = eq(_T_1012, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1013 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1014 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1015 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1016 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1017 = or(_T_1014, _T_1015) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1018 = or(_T_1017, _T_1016) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1019 = eq(io.rw.addr, UInt<12>(0hb18)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1020 = and(_T_1018, _T_1019) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1021 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1022 = eq(io.rw.addr, UInt<12>(0hb18)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1023 = and(_T_1021, _T_1022) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1024 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1025 = eq(_T_1024, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1025 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1026 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1027 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1028 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1029 = or(_T_1026, _T_1027) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1030 = or(_T_1029, _T_1028) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1031 = eq(io.rw.addr, UInt<10>(0h339)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1032 = and(_T_1030, _T_1031) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1033 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1034 = eq(io.rw.addr, UInt<10>(0h339)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1035 = and(_T_1033, _T_1034) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1036 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1037 = eq(_T_1036, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1037 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1038 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1039 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1040 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1041 = or(_T_1038, _T_1039) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1042 = or(_T_1041, _T_1040) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1043 = eq(io.rw.addr, UInt<12>(0hb19)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1044 = and(_T_1042, _T_1043) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1045 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1046 = eq(io.rw.addr, UInt<12>(0hb19)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1047 = and(_T_1045, _T_1046) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1048 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1049 = eq(_T_1048, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1049 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1050 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1051 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1052 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1053 = or(_T_1050, _T_1051) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1054 = or(_T_1053, _T_1052) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1055 = eq(io.rw.addr, UInt<10>(0h33a)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1056 = and(_T_1054, _T_1055) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1057 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1058 = eq(io.rw.addr, UInt<10>(0h33a)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1059 = and(_T_1057, _T_1058) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1060 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1061 = eq(_T_1060, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1061 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1062 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1063 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1064 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1065 = or(_T_1062, _T_1063) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1066 = or(_T_1065, _T_1064) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1067 = eq(io.rw.addr, UInt<12>(0hb1a)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1068 = and(_T_1066, _T_1067) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1069 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1070 = eq(io.rw.addr, UInt<12>(0hb1a)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1071 = and(_T_1069, _T_1070) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1072 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1073 = eq(_T_1072, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1073 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1074 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1075 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1076 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1077 = or(_T_1074, _T_1075) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1078 = or(_T_1077, _T_1076) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1079 = eq(io.rw.addr, UInt<10>(0h33b)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1080 = and(_T_1078, _T_1079) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1081 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1082 = eq(io.rw.addr, UInt<10>(0h33b)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1083 = and(_T_1081, _T_1082) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1084 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1085 = eq(_T_1084, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1085 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1086 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1087 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1088 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1089 = or(_T_1086, _T_1087) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1090 = or(_T_1089, _T_1088) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1091 = eq(io.rw.addr, UInt<12>(0hb1b)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1092 = and(_T_1090, _T_1091) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1093 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1094 = eq(io.rw.addr, UInt<12>(0hb1b)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1095 = and(_T_1093, _T_1094) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1096 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1097 = eq(_T_1096, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1097 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1098 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1099 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1100 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1101 = or(_T_1098, _T_1099) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1102 = or(_T_1101, _T_1100) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1103 = eq(io.rw.addr, UInt<10>(0h33c)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1104 = and(_T_1102, _T_1103) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1105 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1106 = eq(io.rw.addr, UInt<10>(0h33c)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1107 = and(_T_1105, _T_1106) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1108 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1109 = eq(_T_1108, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1109 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1110 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1111 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1112 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1113 = or(_T_1110, _T_1111) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1114 = or(_T_1113, _T_1112) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1115 = eq(io.rw.addr, UInt<12>(0hb1c)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1116 = and(_T_1114, _T_1115) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1117 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1118 = eq(io.rw.addr, UInt<12>(0hb1c)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1119 = and(_T_1117, _T_1118) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1120 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1121 = eq(_T_1120, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1121 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1122 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1123 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1124 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1125 = or(_T_1122, _T_1123) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1126 = or(_T_1125, _T_1124) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1127 = eq(io.rw.addr, UInt<10>(0h33d)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1128 = and(_T_1126, _T_1127) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1129 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1130 = eq(io.rw.addr, UInt<10>(0h33d)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1131 = and(_T_1129, _T_1130) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1132 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1133 = eq(_T_1132, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1133 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1134 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1135 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1136 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1137 = or(_T_1134, _T_1135) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1138 = or(_T_1137, _T_1136) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1139 = eq(io.rw.addr, UInt<12>(0hb1d)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1140 = and(_T_1138, _T_1139) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1141 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1142 = eq(io.rw.addr, UInt<12>(0hb1d)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1143 = and(_T_1141, _T_1142) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1144 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1145 = eq(_T_1144, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1145 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1146 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1147 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1148 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1149 = or(_T_1146, _T_1147) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1150 = or(_T_1149, _T_1148) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1151 = eq(io.rw.addr, UInt<10>(0h33e)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1152 = and(_T_1150, _T_1151) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1153 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1154 = eq(io.rw.addr, UInt<10>(0h33e)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1155 = and(_T_1153, _T_1154) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1156 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1157 = eq(_T_1156, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1157 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1158 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1159 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1160 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1161 = or(_T_1158, _T_1159) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1162 = or(_T_1161, _T_1160) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1163 = eq(io.rw.addr, UInt<12>(0hb1e)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1164 = and(_T_1162, _T_1163) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1165 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1166 = eq(io.rw.addr, UInt<12>(0hb1e)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1167 = and(_T_1165, _T_1166) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1168 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1169 = eq(_T_1168, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1169 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1170 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1171 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1172 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1173 = or(_T_1170, _T_1171) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1174 = or(_T_1173, _T_1172) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1175 = eq(io.rw.addr, UInt<10>(0h33f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1176 = and(_T_1174, _T_1175) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1177 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1178 = eq(io.rw.addr, UInt<10>(0h33f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1179 = and(_T_1177, _T_1178) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1180 = andr(UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1181 = eq(_T_1180, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1181 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1182 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1183 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1184 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1185 = or(_T_1182, _T_1183) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1186 = or(_T_1185, _T_1184) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1187 = eq(io.rw.addr, UInt<12>(0hb1f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1188 = and(_T_1186, _T_1187) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1189 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1190 = eq(io.rw.addr, UInt<12>(0hb1f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1191 = and(_T_1189, _T_1190) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1192 = andr(UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1193 = eq(_T_1192, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1193 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1194 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1195 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1196 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1197 = or(_T_1194, _T_1195) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1198 = or(_T_1197, _T_1196) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1199 = eq(io.rw.addr, UInt<12>(0hc00)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1200 = and(_T_1198, _T_1199) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1201 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1202 = eq(io.rw.addr, UInt<12>(0hc00)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1203 = and(_T_1201, _T_1202) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1204 = andr(UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1205 = eq(_T_1204, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1205 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1206 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1207 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1208 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1209 = or(_T_1206, _T_1207) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1210 = or(_T_1209, _T_1208) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1211 = eq(io.rw.addr, UInt<12>(0hc02)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1212 = and(_T_1210, _T_1211) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1213 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1214 = eq(io.rw.addr, UInt<12>(0hc02)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1215 = and(_T_1213, _T_1214) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1216 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1217 = eq(_T_1216, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1217 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1218 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1219 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1220 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1221 = or(_T_1218, _T_1219) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1222 = or(_T_1221, _T_1220) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1223 = eq(io.rw.addr, UInt<10>(0h3a0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1224 = and(_T_1222, _T_1223) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1225 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1226 = eq(io.rw.addr, UInt<10>(0h3a0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1227 = and(_T_1225, _T_1226) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1228 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1229 = eq(_T_1228, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1229 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1230 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1231 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1232 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1233 = or(_T_1230, _T_1231) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1234 = or(_T_1233, _T_1232) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1235 = eq(io.rw.addr, UInt<10>(0h3a2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1236 = and(_T_1234, _T_1235) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1237 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1238 = eq(io.rw.addr, UInt<10>(0h3a2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1239 = and(_T_1237, _T_1238) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1240 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1241 = eq(_T_1240, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1241 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1242 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1243 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1244 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1245 = or(_T_1242, _T_1243) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1246 = or(_T_1245, _T_1244) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1247 = eq(io.rw.addr, UInt<10>(0h3b0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1248 = and(_T_1246, _T_1247) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1249 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1250 = eq(io.rw.addr, UInt<10>(0h3b0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1251 = and(_T_1249, _T_1250) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1252 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1253 = eq(_T_1252, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1253 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1254 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1255 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1256 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1257 = or(_T_1254, _T_1255) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1258 = or(_T_1257, _T_1256) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1259 = eq(io.rw.addr, UInt<10>(0h3b1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1260 = and(_T_1258, _T_1259) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1261 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1262 = eq(io.rw.addr, UInt<10>(0h3b1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1263 = and(_T_1261, _T_1262) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1264 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1265 = eq(_T_1264, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1265 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1266 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1267 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1268 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1269 = or(_T_1266, _T_1267) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1270 = or(_T_1269, _T_1268) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1271 = eq(io.rw.addr, UInt<10>(0h3b2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1272 = and(_T_1270, _T_1271) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1273 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1274 = eq(io.rw.addr, UInt<10>(0h3b2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1275 = and(_T_1273, _T_1274) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1276 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1277 = eq(_T_1276, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1277 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1278 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1279 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1280 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1281 = or(_T_1278, _T_1279) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1282 = or(_T_1281, _T_1280) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1283 = eq(io.rw.addr, UInt<10>(0h3b3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1284 = and(_T_1282, _T_1283) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1285 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1286 = eq(io.rw.addr, UInt<10>(0h3b3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1287 = and(_T_1285, _T_1286) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1288 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1289 = eq(_T_1288, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1289 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1290 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1291 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1292 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1293 = or(_T_1290, _T_1291) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1294 = or(_T_1293, _T_1292) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1295 = eq(io.rw.addr, UInt<10>(0h3b4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1296 = and(_T_1294, _T_1295) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1297 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1298 = eq(io.rw.addr, UInt<10>(0h3b4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1299 = and(_T_1297, _T_1298) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1300 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1301 = eq(_T_1300, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1301 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1302 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1303 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1304 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1305 = or(_T_1302, _T_1303) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1306 = or(_T_1305, _T_1304) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1307 = eq(io.rw.addr, UInt<10>(0h3b5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1308 = and(_T_1306, _T_1307) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1309 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1310 = eq(io.rw.addr, UInt<10>(0h3b5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1311 = and(_T_1309, _T_1310) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1312 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1313 = eq(_T_1312, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1313 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1314 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1315 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1316 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1317 = or(_T_1314, _T_1315) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1318 = or(_T_1317, _T_1316) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1319 = eq(io.rw.addr, UInt<10>(0h3b6)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1320 = and(_T_1318, _T_1319) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1321 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1322 = eq(io.rw.addr, UInt<10>(0h3b6)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1323 = and(_T_1321, _T_1322) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1324 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1325 = eq(_T_1324, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1325 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1326 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1327 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1328 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1329 = or(_T_1326, _T_1327) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1330 = or(_T_1329, _T_1328) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1331 = eq(io.rw.addr, UInt<10>(0h3b7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1332 = and(_T_1330, _T_1331) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1333 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1334 = eq(io.rw.addr, UInt<10>(0h3b7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1335 = and(_T_1333, _T_1334) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1336 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1337 = eq(_T_1336, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1337 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1338 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1339 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1340 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1341 = or(_T_1338, _T_1339) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1342 = or(_T_1341, _T_1340) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1343 = eq(io.rw.addr, UInt<10>(0h3b8)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1344 = and(_T_1342, _T_1343) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1345 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1346 = eq(io.rw.addr, UInt<10>(0h3b8)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1347 = and(_T_1345, _T_1346) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1348 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1349 = eq(_T_1348, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1349 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1350 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1351 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1352 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1353 = or(_T_1350, _T_1351) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1354 = or(_T_1353, _T_1352) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1355 = eq(io.rw.addr, UInt<10>(0h3b9)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1356 = and(_T_1354, _T_1355) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1357 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1358 = eq(io.rw.addr, UInt<10>(0h3b9)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1359 = and(_T_1357, _T_1358) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1360 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1361 = eq(_T_1360, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1361 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1362 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1363 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1364 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1365 = or(_T_1362, _T_1363) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1366 = or(_T_1365, _T_1364) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1367 = eq(io.rw.addr, UInt<10>(0h3ba)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1368 = and(_T_1366, _T_1367) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1369 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1370 = eq(io.rw.addr, UInt<10>(0h3ba)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1371 = and(_T_1369, _T_1370) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1372 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1373 = eq(_T_1372, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1373 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1374 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1375 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1376 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1377 = or(_T_1374, _T_1375) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1378 = or(_T_1377, _T_1376) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1379 = eq(io.rw.addr, UInt<10>(0h3bb)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1380 = and(_T_1378, _T_1379) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1381 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1382 = eq(io.rw.addr, UInt<10>(0h3bb)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1383 = and(_T_1381, _T_1382) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1384 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1385 = eq(_T_1384, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1385 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1386 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1387 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1388 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1389 = or(_T_1386, _T_1387) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1390 = or(_T_1389, _T_1388) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1391 = eq(io.rw.addr, UInt<10>(0h3bc)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1392 = and(_T_1390, _T_1391) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1393 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1394 = eq(io.rw.addr, UInt<10>(0h3bc)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1395 = and(_T_1393, _T_1394) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1396 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1397 = eq(_T_1396, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1397 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1398 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1399 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1400 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1401 = or(_T_1398, _T_1399) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1402 = or(_T_1401, _T_1400) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1403 = eq(io.rw.addr, UInt<10>(0h3bd)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1404 = and(_T_1402, _T_1403) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1405 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1406 = eq(io.rw.addr, UInt<10>(0h3bd)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1407 = and(_T_1405, _T_1406) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1408 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1409 = eq(_T_1408, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1409 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1410 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1411 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1412 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1413 = or(_T_1410, _T_1411) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1414 = or(_T_1413, _T_1412) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1415 = eq(io.rw.addr, UInt<10>(0h3be)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1416 = and(_T_1414, _T_1415) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1417 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1418 = eq(io.rw.addr, UInt<10>(0h3be)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1419 = and(_T_1417, _T_1418) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1420 = andr(UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1421 = eq(_T_1420, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1421 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1422 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1423 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1424 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1425 = or(_T_1422, _T_1423) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1426 = or(_T_1425, _T_1424) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1427 = eq(io.rw.addr, UInt<10>(0h3bf)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1428 = and(_T_1426, _T_1427) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1429 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1430 = eq(io.rw.addr, UInt<10>(0h3bf)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1431 = and(_T_1429, _T_1430) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1432 = andr(UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1433 = eq(_T_1432, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1433 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1434 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1435 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1436 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1437 = or(_T_1434, _T_1435) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1438 = or(_T_1437, _T_1436) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1439 = eq(io.rw.addr, UInt<11>(0h7c1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1440 = and(_T_1438, _T_1439) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1441 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1442 = eq(io.rw.addr, UInt<11>(0h7c1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1443 = and(_T_1441, _T_1442) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1444 = andr(UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1445 = eq(_T_1444, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1445 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1446 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1447 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1448 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1449 = or(_T_1446, _T_1447) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1450 = or(_T_1449, _T_1448) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1451 = eq(io.rw.addr, UInt<12>(0hf12)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1452 = and(_T_1450, _T_1451) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1453 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1454 = eq(io.rw.addr, UInt<12>(0hf12)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1455 = and(_T_1453, _T_1454) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1456 = andr(UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1457 = eq(_T_1456, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1457 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1458 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1459 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1460 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1461 = or(_T_1458, _T_1459) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1462 = or(_T_1461, _T_1460) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1463 = eq(io.rw.addr, UInt<12>(0hf11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1464 = and(_T_1462, _T_1463) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1465 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1466 = eq(io.rw.addr, UInt<12>(0hf11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1467 = and(_T_1465, _T_1466) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1468 = andr(UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1469 = eq(_T_1468, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1469 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1470 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1471 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1472 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1473 = or(_T_1470, _T_1471) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1474 = or(_T_1473, _T_1472) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1475 = eq(io.rw.addr, UInt<12>(0hf13)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1476 = and(_T_1474, _T_1475) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1477 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1478 = eq(io.rw.addr, UInt<12>(0hf13)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1479 = and(_T_1477, _T_1478) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] node _T_1480 = andr(UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:23] node _T_1481 = eq(_T_1480, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:11] when _T_1481 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1186:29] node _T_1482 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1483 = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1484 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_1485 = or(_T_1482, _T_1483) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1486 = or(_T_1485, _T_1484) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_1487 = eq(io.rw.addr, UInt<12>(0hf15)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:74] node _T_1488 = and(_T_1486, _T_1487) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1187:61] else : node _T_1489 = eq(io.rw.cmd, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:31] node _T_1490 = eq(io.rw.addr, UInt<12>(0hf15)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:53] node _T_1491 = and(_T_1489, _T_1490) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1189:40] wire set_vs_dirty : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1193:33] connect set_vs_dirty, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1193:33] wire set_fs_dirty : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1202:33] connect set_fs_dirty, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1202:33] connect io.fcsr_rm, reg_frm @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1211:14] when io.fcsr_flags.valid : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1212:30] node _reg_fflags_T = or(reg_fflags, io.fcsr_flags.bits) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1213:30] connect reg_fflags, _reg_fflags_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1213:16] connect set_fs_dirty, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1214:18] node _csr_wen_T = eq(io.rw.cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _csr_wen_T_1 = eq(io.rw.cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _csr_wen_T_2 = eq(io.rw.cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _csr_wen_T_3 = or(_csr_wen_T, _csr_wen_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _csr_wen_T_4 = or(_csr_wen_T_3, _csr_wen_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _csr_wen_T_5 = eq(io.rw_stall, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1224:59] node csr_wen = and(_csr_wen_T_4, _csr_wen_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1224:56] node _io_csrw_counter_T = and(UInt<1>(0h1), csr_wen) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1225:57] node _io_csrw_counter_T_1 = geq(io.rw.addr, UInt<12>(0hb00)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 214:47] node _io_csrw_counter_T_2 = lt(io.rw.addr, UInt<12>(0hb20)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 214:60] node _io_csrw_counter_T_3 = and(_io_csrw_counter_T_1, _io_csrw_counter_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 214:55] node _io_csrw_counter_T_4 = geq(io.rw.addr, UInt<12>(0hb80)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 214:47] node _io_csrw_counter_T_5 = lt(io.rw.addr, UInt<12>(0hba0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 214:60] node _io_csrw_counter_T_6 = and(_io_csrw_counter_T_4, _io_csrw_counter_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 214:55] node _io_csrw_counter_T_7 = or(_io_csrw_counter_T_3, _io_csrw_counter_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1225:134] node _io_csrw_counter_T_8 = and(_io_csrw_counter_T, _io_csrw_counter_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1225:68] node _io_csrw_counter_T_9 = bits(io.rw.addr, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1225:222] node _io_csrw_counter_T_10 = dshl(UInt<1>(0h1), _io_csrw_counter_T_9) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node _io_csrw_counter_T_11 = mux(_io_csrw_counter_T_8, _io_csrw_counter_T_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1225:25] connect io.csrw_counter, _io_csrw_counter_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1225:19] when csr_wen : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1226:18] when decoded_addr_88_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1230:39] wire new_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] wire _new_mstatus_WIRE : UInt<105> @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect _new_mstatus_WIRE, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T = bits(_new_mstatus_WIRE, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.uie, _new_mstatus_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_1 = bits(_new_mstatus_WIRE, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.sie, _new_mstatus_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_2 = bits(_new_mstatus_WIRE, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.hie, _new_mstatus_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_3 = bits(_new_mstatus_WIRE, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.mie, _new_mstatus_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_4 = bits(_new_mstatus_WIRE, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.upie, _new_mstatus_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_5 = bits(_new_mstatus_WIRE, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.spie, _new_mstatus_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_6 = bits(_new_mstatus_WIRE, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.ube, _new_mstatus_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_7 = bits(_new_mstatus_WIRE, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.mpie, _new_mstatus_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_8 = bits(_new_mstatus_WIRE, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.spp, _new_mstatus_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_9 = bits(_new_mstatus_WIRE, 10, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.vs, _new_mstatus_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_10 = bits(_new_mstatus_WIRE, 12, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.mpp, _new_mstatus_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_11 = bits(_new_mstatus_WIRE, 14, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.fs, _new_mstatus_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_12 = bits(_new_mstatus_WIRE, 16, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.xs, _new_mstatus_T_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_13 = bits(_new_mstatus_WIRE, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.mprv, _new_mstatus_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_14 = bits(_new_mstatus_WIRE, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.sum, _new_mstatus_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_15 = bits(_new_mstatus_WIRE, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.mxr, _new_mstatus_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_16 = bits(_new_mstatus_WIRE, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.tvm, _new_mstatus_T_16 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_17 = bits(_new_mstatus_WIRE, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.tw, _new_mstatus_T_17 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_18 = bits(_new_mstatus_WIRE, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.tsr, _new_mstatus_T_18 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_19 = bits(_new_mstatus_WIRE, 30, 23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.zero1, _new_mstatus_T_19 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_20 = bits(_new_mstatus_WIRE, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.sd_rv32, _new_mstatus_T_20 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_21 = bits(_new_mstatus_WIRE, 33, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.uxl, _new_mstatus_T_21 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_22 = bits(_new_mstatus_WIRE, 35, 34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.sxl, _new_mstatus_T_22 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_23 = bits(_new_mstatus_WIRE, 36, 36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.sbe, _new_mstatus_T_23 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_24 = bits(_new_mstatus_WIRE, 37, 37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.mbe, _new_mstatus_T_24 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_25 = bits(_new_mstatus_WIRE, 38, 38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.gva, _new_mstatus_T_25 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_26 = bits(_new_mstatus_WIRE, 39, 39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.mpv, _new_mstatus_T_26 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_27 = bits(_new_mstatus_WIRE, 62, 40) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.zero2, _new_mstatus_T_27 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_28 = bits(_new_mstatus_WIRE, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.sd, _new_mstatus_T_28 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_29 = bits(_new_mstatus_WIRE, 64, 64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.v, _new_mstatus_T_29 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_30 = bits(_new_mstatus_WIRE, 66, 65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.prv, _new_mstatus_T_30 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_31 = bits(_new_mstatus_WIRE, 67, 67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.dv, _new_mstatus_T_31 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_32 = bits(_new_mstatus_WIRE, 69, 68) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.dprv, _new_mstatus_T_32 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_33 = bits(_new_mstatus_WIRE, 101, 70) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.isa, _new_mstatus_T_33 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_34 = bits(_new_mstatus_WIRE, 102, 102) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.wfi, _new_mstatus_T_34 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_35 = bits(_new_mstatus_WIRE, 103, 103) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.cease, _new_mstatus_T_35 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] node _new_mstatus_T_36 = bits(_new_mstatus_WIRE, 104, 104) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect new_mstatus.debug, _new_mstatus_T_36 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1231:39] connect reg_mstatus.mie, new_mstatus.mie @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1232:23] connect reg_mstatus.mpie, new_mstatus.mpie @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1233:24] node _reg_mstatus_fs_T = orr(new_mstatus.fs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1670:73] node _reg_mstatus_fs_T_1 = mux(_reg_mstatus_fs_T, UInt<2>(0h3), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1670:66] connect reg_mstatus.fs, _reg_mstatus_fs_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1256:55] connect reg_mstatus.vs, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1257:22] when decoded_addr_82_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1259:36] node f = bits(wdata, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1261:20] node _T_1492 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1263:13] node _T_1493 = bits(io.pc, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1263:41] node _T_1494 = eq(_T_1493, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1263:35] node _T_1495 = or(_T_1492, _T_1494) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1263:32] node _T_1496 = bits(wdata, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1263:53] node _T_1497 = or(_T_1495, _T_1496) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1263:45] when _T_1497 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1263:66] node _reg_misa_T = not(wdata) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1265:25] node _reg_misa_T_1 = eq(f, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1265:35] node _reg_misa_T_2 = shl(_reg_misa_T_1, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1265:38] node _reg_misa_T_3 = or(_reg_misa_T, _reg_misa_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1265:32] node _reg_misa_T_4 = not(_reg_misa_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1265:23] node _reg_misa_T_5 = and(_reg_misa_T_4, UInt<64>(0h102d)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1265:55] node _reg_misa_T_6 = not(UInt<64>(0h102d)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1265:75] node _reg_misa_T_7 = and(reg_misa, _reg_misa_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1265:73] node _reg_misa_T_8 = or(_reg_misa_T_5, _reg_misa_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1265:62] connect reg_misa, _reg_misa_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1265:20] when decoded_addr_96_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1268:35] node new_mip_lo_lo_lo = cat(reg_mip.ssip, reg_mip.usip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:59] node new_mip_lo_lo_hi = cat(reg_mip.msip, reg_mip.vssip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:59] node new_mip_lo_lo = cat(new_mip_lo_lo_hi, new_mip_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:59] node new_mip_lo_hi_lo = cat(reg_mip.stip, reg_mip.utip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:59] node new_mip_lo_hi_hi = cat(reg_mip.mtip, reg_mip.vstip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:59] node new_mip_lo_hi = cat(new_mip_lo_hi_hi, new_mip_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:59] node new_mip_lo = cat(new_mip_lo_hi, new_mip_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:59] node new_mip_hi_lo_lo = cat(reg_mip.seip, reg_mip.ueip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:59] node new_mip_hi_lo_hi = cat(reg_mip.meip, reg_mip.vseip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:59] node new_mip_hi_lo = cat(new_mip_hi_lo_hi, new_mip_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:59] node new_mip_hi_hi_lo = cat(reg_mip.rocc, reg_mip.sgeip) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:59] node new_mip_hi_hi_hi_hi = cat(UInt<0>(0h0), reg_mip.zero1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:59] node new_mip_hi_hi_hi = cat(new_mip_hi_hi_hi_hi, reg_mip.debug) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:59] node new_mip_hi_hi = cat(new_mip_hi_hi_hi, new_mip_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:59] node new_mip_hi = cat(new_mip_hi_hi, new_mip_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:59] node _new_mip_T = cat(new_mip_hi, new_mip_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:59] node _new_mip_T_1 = bits(io.rw.cmd, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:13] node _new_mip_T_2 = mux(_new_mip_T_1, _new_mip_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:9] node _new_mip_T_3 = or(_new_mip_T_2, io.rw.wdata) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:30] node _new_mip_T_4 = bits(io.rw.cmd, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:49] node _new_mip_T_5 = andr(_new_mip_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:55] node _new_mip_T_6 = mux(_new_mip_T_5, io.rw.wdata, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:45] node _new_mip_T_7 = not(_new_mip_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:41] node _new_mip_T_8 = and(_new_mip_T_3, _new_mip_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:39] wire new_mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] wire _new_mip_WIRE : UInt<16> @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] connect _new_mip_WIRE, _new_mip_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] node _new_mip_T_9 = bits(_new_mip_WIRE, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] connect new_mip.usip, _new_mip_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] node _new_mip_T_10 = bits(_new_mip_WIRE, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] connect new_mip.ssip, _new_mip_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] node _new_mip_T_11 = bits(_new_mip_WIRE, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] connect new_mip.vssip, _new_mip_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] node _new_mip_T_12 = bits(_new_mip_WIRE, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] connect new_mip.msip, _new_mip_T_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] node _new_mip_T_13 = bits(_new_mip_WIRE, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] connect new_mip.utip, _new_mip_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] node _new_mip_T_14 = bits(_new_mip_WIRE, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] connect new_mip.stip, _new_mip_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] node _new_mip_T_15 = bits(_new_mip_WIRE, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] connect new_mip.vstip, _new_mip_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] node _new_mip_T_16 = bits(_new_mip_WIRE, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] connect new_mip.mtip, _new_mip_T_16 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] node _new_mip_T_17 = bits(_new_mip_WIRE, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] connect new_mip.ueip, _new_mip_T_17 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] node _new_mip_T_18 = bits(_new_mip_WIRE, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] connect new_mip.seip, _new_mip_T_18 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] node _new_mip_T_19 = bits(_new_mip_WIRE, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] connect new_mip.vseip, _new_mip_T_19 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] node _new_mip_T_20 = bits(_new_mip_WIRE, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] connect new_mip.meip, _new_mip_T_20 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] node _new_mip_T_21 = bits(_new_mip_WIRE, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] connect new_mip.sgeip, _new_mip_T_21 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] node _new_mip_T_22 = bits(_new_mip_WIRE, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] connect new_mip.rocc, _new_mip_T_22 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] node _new_mip_T_23 = bits(_new_mip_WIRE, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] connect new_mip.debug, _new_mip_T_23 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] node _new_mip_T_24 = bits(_new_mip_WIRE, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] connect new_mip.zero1, _new_mip_T_24 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1273:88] when decoded_addr_65_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1283:40] node _reg_mie_T = and(wdata, supported_interrupts) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1283:59] connect reg_mie, _reg_mie_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1283:50] when decoded_addr_119_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1284:40] node _reg_mepc_T = not(wdata) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1666:28] node _reg_mepc_T_1 = or(_reg_mepc_T, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1666:31] node _reg_mepc_T_2 = not(_reg_mepc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1666:26] connect reg_mepc, _reg_mepc_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1284:51] when decoded_addr_116_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1285:40] connect reg_mscratch, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1285:55] when decoded_addr_61_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1287:40] connect reg_mtvec, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1287:52] when decoded_addr_24_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1288:40] node _reg_mcause_T = and(wdata, UInt<64>(0h800000000000000f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1288:62] connect reg_mcause, _reg_mcause_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1288:53] when decoded_addr_123_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1289:40] connect reg_mtval, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1289:52] when decoded_addr_117_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1308:47] node _reg_mcountinhibit_T = not(UInt<64>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1308:78] node _reg_mcountinhibit_T_1 = and(wdata, _reg_mcountinhibit_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1308:76] connect reg_mcountinhibit, _reg_mcountinhibit_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1308:67] when decoded_addr_91_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1663:31] node _T_1498 = bits(wdata, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1663:45] connect small_1, _T_1498 @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 67:11] node _large_T_6 = shr(_T_1498, 6) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 68:28] connect large_1, _large_T_6 @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 68:23] when decoded_addr_109_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1663:31] node _T_1499 = bits(wdata, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1663:45] connect small, _T_1499 @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 67:11] node _large_T_7 = shr(_T_1499, 6) @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 68:28] connect large, _large_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/Counters.scala 68:23] when decoded_addr_30_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1314:40] connect set_fs_dirty, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1314:55] connect reg_fflags, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1314:77] when decoded_addr_58_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1315:40] connect set_fs_dirty, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1315:55] connect reg_frm, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1315:74] when decoded_addr_87_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1316:38] connect set_fs_dirty, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1317:22] connect reg_fflags, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1318:20] node _reg_frm_T = shr(wdata, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1319:26] connect reg_frm, _reg_frm_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1319:17] when decoded_addr_40_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1323:38] wire new_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] wire _new_dcsr_WIRE : UInt<32> @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] connect _new_dcsr_WIRE, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] node _new_dcsr_T = bits(_new_dcsr_WIRE, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] connect new_dcsr.prv, _new_dcsr_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] node _new_dcsr_T_1 = bits(_new_dcsr_WIRE, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] connect new_dcsr.step, _new_dcsr_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] node _new_dcsr_T_2 = bits(_new_dcsr_WIRE, 4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] connect new_dcsr.zero1, _new_dcsr_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] node _new_dcsr_T_3 = bits(_new_dcsr_WIRE, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] connect new_dcsr.v, _new_dcsr_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] node _new_dcsr_T_4 = bits(_new_dcsr_WIRE, 8, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] connect new_dcsr.cause, _new_dcsr_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] node _new_dcsr_T_5 = bits(_new_dcsr_WIRE, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] connect new_dcsr.stoptime, _new_dcsr_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] node _new_dcsr_T_6 = bits(_new_dcsr_WIRE, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] connect new_dcsr.stopcycle, _new_dcsr_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] node _new_dcsr_T_7 = bits(_new_dcsr_WIRE, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] connect new_dcsr.zero2, _new_dcsr_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] node _new_dcsr_T_8 = bits(_new_dcsr_WIRE, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] connect new_dcsr.ebreaku, _new_dcsr_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] node _new_dcsr_T_9 = bits(_new_dcsr_WIRE, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] connect new_dcsr.ebreaks, _new_dcsr_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] node _new_dcsr_T_10 = bits(_new_dcsr_WIRE, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] connect new_dcsr.ebreakh, _new_dcsr_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] node _new_dcsr_T_11 = bits(_new_dcsr_WIRE, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] connect new_dcsr.ebreakm, _new_dcsr_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] node _new_dcsr_T_12 = bits(_new_dcsr_WIRE, 27, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] connect new_dcsr.zero3, _new_dcsr_T_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] node _new_dcsr_T_13 = bits(_new_dcsr_WIRE, 29, 28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] connect new_dcsr.zero4, _new_dcsr_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] node _new_dcsr_T_14 = bits(_new_dcsr_WIRE, 31, 30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] connect new_dcsr.xdebugver, _new_dcsr_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1324:38] connect reg_dcsr.step, new_dcsr.step @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1325:23] connect reg_dcsr.ebreakm, new_dcsr.ebreakm @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1326:26] when decoded_addr_78_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1332:42] node _reg_dpc_T = not(wdata) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1666:28] node _reg_dpc_T_1 = or(_reg_dpc_T, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1666:31] node _reg_dpc_T_2 = not(_reg_dpc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1666:26] connect reg_dpc, _reg_dpc_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1332:52] when decoded_addr_48_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1333:43] connect reg_dscratch0, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1333:59] when decoded_addr_85_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1457:41] connect reg_tselect, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1457:55] node _T_1500 = eq(UInt<1>(0h0), reg_tselect) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1460:19] node _T_1501 = eq(reg_bp[0].control.dmode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1460:39] node _T_1502 = or(_T_1501, reg_debug) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1460:57] node _T_1503 = and(_T_1500, _T_1502) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1460:35] when _T_1503 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1460:72] when decoded_addr_9_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1461:44] connect reg_bp[0].address, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1461:57] when decoded_addr_106_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1462:44] skip when decoded_addr_46_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1472:44] wire _reg_bp_0_control_WIRE : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] wire _reg_bp_0_control_WIRE_1 : UInt<64> @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_0_control_WIRE_1, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_0_control_T = bits(_reg_bp_0_control_WIRE_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_0_control_WIRE.r, _reg_bp_0_control_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_0_control_T_1 = bits(_reg_bp_0_control_WIRE_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_0_control_WIRE.w, _reg_bp_0_control_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_0_control_T_2 = bits(_reg_bp_0_control_WIRE_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_0_control_WIRE.x, _reg_bp_0_control_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_0_control_T_3 = bits(_reg_bp_0_control_WIRE_1, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_0_control_WIRE.u, _reg_bp_0_control_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_0_control_T_4 = bits(_reg_bp_0_control_WIRE_1, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_0_control_WIRE.s, _reg_bp_0_control_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_0_control_T_5 = bits(_reg_bp_0_control_WIRE_1, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_0_control_WIRE.h, _reg_bp_0_control_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_0_control_T_6 = bits(_reg_bp_0_control_WIRE_1, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_0_control_WIRE.m, _reg_bp_0_control_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_0_control_T_7 = bits(_reg_bp_0_control_WIRE_1, 8, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_0_control_WIRE.tmatch, _reg_bp_0_control_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_0_control_T_8 = bits(_reg_bp_0_control_WIRE_1, 10, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_0_control_WIRE.zero, _reg_bp_0_control_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_0_control_T_9 = bits(_reg_bp_0_control_WIRE_1, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_0_control_WIRE.chain, _reg_bp_0_control_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_0_control_T_10 = bits(_reg_bp_0_control_WIRE_1, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_0_control_WIRE.action, _reg_bp_0_control_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_0_control_T_11 = bits(_reg_bp_0_control_WIRE_1, 52, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_0_control_WIRE.reserved, _reg_bp_0_control_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_0_control_T_12 = bits(_reg_bp_0_control_WIRE_1, 58, 53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_0_control_WIRE.maskmax, _reg_bp_0_control_T_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_0_control_T_13 = bits(_reg_bp_0_control_WIRE_1, 59, 59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_0_control_WIRE.dmode, _reg_bp_0_control_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_0_control_T_14 = bits(_reg_bp_0_control_WIRE_1, 63, 60) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_0_control_WIRE.ttype, _reg_bp_0_control_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect reg_bp[0].control, _reg_bp_0_control_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:24] node newBPC_lo_lo_hi = cat(reg_bp[0].control.x, reg_bp[0].control.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_lo_lo = cat(newBPC_lo_lo_hi, reg_bp[0].control.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_lo_hi_lo = cat(reg_bp[0].control.s, reg_bp[0].control.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_lo_hi_hi = cat(reg_bp[0].control.m, reg_bp[0].control.h) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_lo_hi = cat(newBPC_lo_hi_hi, newBPC_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_lo = cat(newBPC_lo_hi, newBPC_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_hi_lo_lo = cat(reg_bp[0].control.zero, reg_bp[0].control.tmatch) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_hi_lo_hi = cat(reg_bp[0].control.action, reg_bp[0].control.chain) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_hi_lo = cat(newBPC_hi_lo_hi, newBPC_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_hi_hi_lo = cat(reg_bp[0].control.maskmax, reg_bp[0].control.reserved) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_hi_hi_hi = cat(reg_bp[0].control.ttype, reg_bp[0].control.dmode) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_hi_hi = cat(newBPC_hi_hi_hi, newBPC_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_hi = cat(newBPC_hi_hi, newBPC_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node _newBPC_T = cat(newBPC_hi, newBPC_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node _newBPC_T_1 = bits(io.rw.cmd, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:13] node _newBPC_T_2 = mux(_newBPC_T_1, _newBPC_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:9] node _newBPC_T_3 = or(_newBPC_T_2, io.rw.wdata) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:30] node _newBPC_T_4 = bits(io.rw.cmd, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:49] node _newBPC_T_5 = andr(_newBPC_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:55] node _newBPC_T_6 = mux(_newBPC_T_5, io.rw.wdata, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:45] node _newBPC_T_7 = not(_newBPC_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:41] node _newBPC_T_8 = and(_newBPC_T_3, _newBPC_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:39] wire newBPC : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] wire _newBPC_WIRE : UInt<64> @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect _newBPC_WIRE, _newBPC_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_9 = bits(_newBPC_WIRE, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC.r, _newBPC_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_10 = bits(_newBPC_WIRE, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC.w, _newBPC_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_11 = bits(_newBPC_WIRE, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC.x, _newBPC_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_12 = bits(_newBPC_WIRE, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC.u, _newBPC_T_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_13 = bits(_newBPC_WIRE, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC.s, _newBPC_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_14 = bits(_newBPC_WIRE, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC.h, _newBPC_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_15 = bits(_newBPC_WIRE, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC.m, _newBPC_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_16 = bits(_newBPC_WIRE, 8, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC.tmatch, _newBPC_T_16 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_17 = bits(_newBPC_WIRE, 10, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC.zero, _newBPC_T_17 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_18 = bits(_newBPC_WIRE, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC.chain, _newBPC_T_18 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_19 = bits(_newBPC_WIRE, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC.action, _newBPC_T_19 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_20 = bits(_newBPC_WIRE, 52, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC.reserved, _newBPC_T_20 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_21 = bits(_newBPC_WIRE, 58, 53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC.maskmax, _newBPC_T_21 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_22 = bits(_newBPC_WIRE, 59, 59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC.dmode, _newBPC_T_22 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_23 = bits(_newBPC_WIRE, 63, 60) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC.ttype, _newBPC_T_23 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _dMode_T = and(newBPC.dmode, reg_debug) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1480:38] node _dMode_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1480:68] node _dMode_T_2 = or(UInt<1>(0h0), _dMode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1480:65] node dMode = and(_dMode_T, _dMode_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1480:51] connect reg_bp[0].control.dmode, dMode @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1481:30] node _T_1504 = gt(newBPC.action, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1482:43] node _T_1505 = or(dMode, _T_1504) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1482:25] when _T_1505 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1482:51] connect reg_bp[0].control.action, newBPC.action @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1482:71] else : connect reg_bp[0].control.action, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1482:120] node _reg_bp_0_control_chain_T = or(UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1483:61] node _reg_bp_0_control_chain_T_1 = eq(_reg_bp_0_control_chain_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1483:49] node _reg_bp_0_control_chain_T_2 = and(newBPC.chain, _reg_bp_0_control_chain_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1483:46] node _reg_bp_0_control_chain_T_3 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1483:88] node _reg_bp_0_control_chain_T_4 = or(dMode, _reg_bp_0_control_chain_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1483:85] node _reg_bp_0_control_chain_T_5 = and(_reg_bp_0_control_chain_T_2, _reg_bp_0_control_chain_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1483:75] connect reg_bp[0].control.chain, _reg_bp_0_control_chain_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1483:30] node _T_1506 = eq(UInt<1>(0h1), reg_tselect) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1460:19] node _T_1507 = eq(reg_bp[1].control.dmode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1460:39] node _T_1508 = or(_T_1507, reg_debug) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1460:57] node _T_1509 = and(_T_1506, _T_1508) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1460:35] when _T_1509 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1460:72] when decoded_addr_9_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1461:44] connect reg_bp[1].address, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1461:57] when decoded_addr_106_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1462:44] skip when decoded_addr_46_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1472:44] wire _reg_bp_1_control_WIRE : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] wire _reg_bp_1_control_WIRE_1 : UInt<64> @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_1_control_WIRE_1, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_1_control_T = bits(_reg_bp_1_control_WIRE_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_1_control_WIRE.r, _reg_bp_1_control_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_1_control_T_1 = bits(_reg_bp_1_control_WIRE_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_1_control_WIRE.w, _reg_bp_1_control_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_1_control_T_2 = bits(_reg_bp_1_control_WIRE_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_1_control_WIRE.x, _reg_bp_1_control_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_1_control_T_3 = bits(_reg_bp_1_control_WIRE_1, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_1_control_WIRE.u, _reg_bp_1_control_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_1_control_T_4 = bits(_reg_bp_1_control_WIRE_1, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_1_control_WIRE.s, _reg_bp_1_control_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_1_control_T_5 = bits(_reg_bp_1_control_WIRE_1, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_1_control_WIRE.h, _reg_bp_1_control_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_1_control_T_6 = bits(_reg_bp_1_control_WIRE_1, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_1_control_WIRE.m, _reg_bp_1_control_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_1_control_T_7 = bits(_reg_bp_1_control_WIRE_1, 8, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_1_control_WIRE.tmatch, _reg_bp_1_control_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_1_control_T_8 = bits(_reg_bp_1_control_WIRE_1, 10, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_1_control_WIRE.zero, _reg_bp_1_control_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_1_control_T_9 = bits(_reg_bp_1_control_WIRE_1, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_1_control_WIRE.chain, _reg_bp_1_control_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_1_control_T_10 = bits(_reg_bp_1_control_WIRE_1, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_1_control_WIRE.action, _reg_bp_1_control_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_1_control_T_11 = bits(_reg_bp_1_control_WIRE_1, 52, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_1_control_WIRE.reserved, _reg_bp_1_control_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_1_control_T_12 = bits(_reg_bp_1_control_WIRE_1, 58, 53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_1_control_WIRE.maskmax, _reg_bp_1_control_T_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_1_control_T_13 = bits(_reg_bp_1_control_WIRE_1, 59, 59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_1_control_WIRE.dmode, _reg_bp_1_control_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] node _reg_bp_1_control_T_14 = bits(_reg_bp_1_control_WIRE_1, 63, 60) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect _reg_bp_1_control_WIRE.ttype, _reg_bp_1_control_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:41] connect reg_bp[1].control, _reg_bp_1_control_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1473:24] node newBPC_lo_lo_hi_1 = cat(reg_bp[1].control.x, reg_bp[1].control.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_lo_lo_1 = cat(newBPC_lo_lo_hi_1, reg_bp[1].control.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_lo_hi_lo_1 = cat(reg_bp[1].control.s, reg_bp[1].control.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_lo_hi_hi_1 = cat(reg_bp[1].control.m, reg_bp[1].control.h) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_lo_hi_1 = cat(newBPC_lo_hi_hi_1, newBPC_lo_hi_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_lo_1 = cat(newBPC_lo_hi_1, newBPC_lo_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_hi_lo_lo_1 = cat(reg_bp[1].control.zero, reg_bp[1].control.tmatch) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_hi_lo_hi_1 = cat(reg_bp[1].control.action, reg_bp[1].control.chain) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_hi_lo_1 = cat(newBPC_hi_lo_hi_1, newBPC_hi_lo_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_hi_hi_lo_1 = cat(reg_bp[1].control.maskmax, reg_bp[1].control.reserved) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_hi_hi_hi_1 = cat(reg_bp[1].control.ttype, reg_bp[1].control.dmode) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_hi_hi_1 = cat(newBPC_hi_hi_hi_1, newBPC_hi_hi_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node newBPC_hi_1 = cat(newBPC_hi_hi_1, newBPC_hi_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node _newBPC_T_24 = cat(newBPC_hi_1, newBPC_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:67] node _newBPC_T_25 = bits(io.rw.cmd, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:13] node _newBPC_T_26 = mux(_newBPC_T_25, _newBPC_T_24, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:9] node _newBPC_T_27 = or(_newBPC_T_26, io.rw.wdata) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:30] node _newBPC_T_28 = bits(io.rw.cmd, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:49] node _newBPC_T_29 = andr(_newBPC_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:55] node _newBPC_T_30 = mux(_newBPC_T_29, io.rw.wdata, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:45] node _newBPC_T_31 = not(_newBPC_T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:41] node _newBPC_T_32 = and(_newBPC_T_27, _newBPC_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1645:39] wire newBPC_1 : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] wire _newBPC_WIRE_1 : UInt<64> @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect _newBPC_WIRE_1, _newBPC_T_32 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_33 = bits(_newBPC_WIRE_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC_1.r, _newBPC_T_33 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_34 = bits(_newBPC_WIRE_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC_1.w, _newBPC_T_34 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_35 = bits(_newBPC_WIRE_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC_1.x, _newBPC_T_35 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_36 = bits(_newBPC_WIRE_1, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC_1.u, _newBPC_T_36 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_37 = bits(_newBPC_WIRE_1, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC_1.s, _newBPC_T_37 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_38 = bits(_newBPC_WIRE_1, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC_1.h, _newBPC_T_38 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_39 = bits(_newBPC_WIRE_1, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC_1.m, _newBPC_T_39 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_40 = bits(_newBPC_WIRE_1, 8, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC_1.tmatch, _newBPC_T_40 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_41 = bits(_newBPC_WIRE_1, 10, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC_1.zero, _newBPC_T_41 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_42 = bits(_newBPC_WIRE_1, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC_1.chain, _newBPC_T_42 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_43 = bits(_newBPC_WIRE_1, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC_1.action, _newBPC_T_43 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_44 = bits(_newBPC_WIRE_1, 52, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC_1.reserved, _newBPC_T_44 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_45 = bits(_newBPC_WIRE_1, 58, 53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC_1.maskmax, _newBPC_T_45 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_46 = bits(_newBPC_WIRE_1, 59, 59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC_1.dmode, _newBPC_T_46 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _newBPC_T_47 = bits(_newBPC_WIRE_1, 63, 60) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] connect newBPC_1.ttype, _newBPC_T_47 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1479:96] node _dMode_T_3 = and(newBPC_1.dmode, reg_debug) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1480:38] node _dMode_T_4 = eq(reg_bp[0].control.chain, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1480:68] node _dMode_T_5 = or(reg_bp[0].control.dmode, _dMode_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1480:65] node dMode_1 = and(_dMode_T_3, _dMode_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1480:51] connect reg_bp[1].control.dmode, dMode_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1481:30] node _T_1510 = gt(newBPC_1.action, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1482:43] node _T_1511 = or(dMode_1, _T_1510) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1482:25] when _T_1511 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1482:51] connect reg_bp[1].control.action, newBPC_1.action @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1482:71] else : connect reg_bp[1].control.action, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1482:120] node _reg_bp_1_control_chain_T = or(reg_bp[0].control.chain, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1483:61] node _reg_bp_1_control_chain_T_1 = eq(_reg_bp_1_control_chain_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1483:49] node _reg_bp_1_control_chain_T_2 = and(newBPC_1.chain, _reg_bp_1_control_chain_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1483:46] node _reg_bp_1_control_chain_T_3 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1483:88] node _reg_bp_1_control_chain_T_4 = or(dMode_1, _reg_bp_1_control_chain_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1483:85] node _reg_bp_1_control_chain_T_5 = and(_reg_bp_1_control_chain_T_2, _reg_bp_1_control_chain_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1483:75] connect reg_bp[1].control.chain, _reg_bp_1_control_chain_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1483:30] node _T_1512 = eq(reg_pmp[0].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:60] node _T_1513 = and(decoded_addr_127_2, _T_1512) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:57] when _T_1513 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:76] node _newCfg_T = shr(wdata, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:29] wire newCfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] wire _newCfg_WIRE : UInt<8> @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect _newCfg_WIRE, _newCfg_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_1 = bits(_newCfg_WIRE, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg.r, _newCfg_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_2 = bits(_newCfg_WIRE, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg.w, _newCfg_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_3 = bits(_newCfg_WIRE, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg.x, _newCfg_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_4 = bits(_newCfg_WIRE, 4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg.a, _newCfg_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_5 = bits(_newCfg_WIRE, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg.res, _newCfg_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_6 = bits(_newCfg_WIRE, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg.l, _newCfg_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect reg_pmp[0].cfg, newCfg @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1494:17] node _reg_pmp_0_cfg_w_T = and(newCfg.w, newCfg.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1496:31] connect reg_pmp[0].cfg.w, _reg_pmp_0_cfg_w_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1496:19] node _T_1514 = bits(reg_pmp[1].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _T_1515 = eq(_T_1514, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 47:13] node _T_1516 = bits(reg_pmp[1].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _T_1517 = and(_T_1515, _T_1516) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 47:20] node _T_1518 = and(reg_pmp[1].cfg.l, _T_1517) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 49:62] node _T_1519 = or(reg_pmp[0].cfg.l, _T_1518) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 49:44] node _T_1520 = eq(_T_1519, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:48] node _T_1521 = and(decoded_addr_92_2, _T_1520) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:45] when _T_1521 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:71] connect reg_pmp[0].addr, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1502:18] node _T_1522 = eq(reg_pmp[1].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:60] node _T_1523 = and(decoded_addr_127_2, _T_1522) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:57] when _T_1523 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:76] node _newCfg_T_7 = shr(wdata, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:29] wire newCfg_1 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] wire _newCfg_WIRE_1 : UInt<8> @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect _newCfg_WIRE_1, _newCfg_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_8 = bits(_newCfg_WIRE_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_1.r, _newCfg_T_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_9 = bits(_newCfg_WIRE_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_1.w, _newCfg_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_10 = bits(_newCfg_WIRE_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_1.x, _newCfg_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_11 = bits(_newCfg_WIRE_1, 4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_1.a, _newCfg_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_12 = bits(_newCfg_WIRE_1, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_1.res, _newCfg_T_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_13 = bits(_newCfg_WIRE_1, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_1.l, _newCfg_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect reg_pmp[1].cfg, newCfg_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1494:17] node _reg_pmp_1_cfg_w_T = and(newCfg_1.w, newCfg_1.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1496:31] connect reg_pmp[1].cfg.w, _reg_pmp_1_cfg_w_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1496:19] node _T_1524 = bits(reg_pmp[2].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _T_1525 = eq(_T_1524, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 47:13] node _T_1526 = bits(reg_pmp[2].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _T_1527 = and(_T_1525, _T_1526) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 47:20] node _T_1528 = and(reg_pmp[2].cfg.l, _T_1527) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 49:62] node _T_1529 = or(reg_pmp[1].cfg.l, _T_1528) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 49:44] node _T_1530 = eq(_T_1529, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:48] node _T_1531 = and(decoded_addr_7_2, _T_1530) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:45] when _T_1531 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:71] connect reg_pmp[1].addr, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1502:18] node _T_1532 = eq(reg_pmp[2].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:60] node _T_1533 = and(decoded_addr_127_2, _T_1532) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:57] when _T_1533 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:76] node _newCfg_T_14 = shr(wdata, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:29] wire newCfg_2 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] wire _newCfg_WIRE_2 : UInt<8> @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect _newCfg_WIRE_2, _newCfg_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_15 = bits(_newCfg_WIRE_2, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_2.r, _newCfg_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_16 = bits(_newCfg_WIRE_2, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_2.w, _newCfg_T_16 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_17 = bits(_newCfg_WIRE_2, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_2.x, _newCfg_T_17 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_18 = bits(_newCfg_WIRE_2, 4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_2.a, _newCfg_T_18 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_19 = bits(_newCfg_WIRE_2, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_2.res, _newCfg_T_19 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_20 = bits(_newCfg_WIRE_2, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_2.l, _newCfg_T_20 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect reg_pmp[2].cfg, newCfg_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1494:17] node _reg_pmp_2_cfg_w_T = and(newCfg_2.w, newCfg_2.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1496:31] connect reg_pmp[2].cfg.w, _reg_pmp_2_cfg_w_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1496:19] node _T_1534 = bits(reg_pmp[3].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _T_1535 = eq(_T_1534, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 47:13] node _T_1536 = bits(reg_pmp[3].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _T_1537 = and(_T_1535, _T_1536) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 47:20] node _T_1538 = and(reg_pmp[3].cfg.l, _T_1537) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 49:62] node _T_1539 = or(reg_pmp[2].cfg.l, _T_1538) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 49:44] node _T_1540 = eq(_T_1539, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:48] node _T_1541 = and(decoded_addr_112_2, _T_1540) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:45] when _T_1541 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:71] connect reg_pmp[2].addr, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1502:18] node _T_1542 = eq(reg_pmp[3].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:60] node _T_1543 = and(decoded_addr_127_2, _T_1542) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:57] when _T_1543 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:76] node _newCfg_T_21 = shr(wdata, 24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:29] wire newCfg_3 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] wire _newCfg_WIRE_3 : UInt<8> @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect _newCfg_WIRE_3, _newCfg_T_21 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_22 = bits(_newCfg_WIRE_3, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_3.r, _newCfg_T_22 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_23 = bits(_newCfg_WIRE_3, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_3.w, _newCfg_T_23 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_24 = bits(_newCfg_WIRE_3, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_3.x, _newCfg_T_24 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_25 = bits(_newCfg_WIRE_3, 4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_3.a, _newCfg_T_25 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_26 = bits(_newCfg_WIRE_3, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_3.res, _newCfg_T_26 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_27 = bits(_newCfg_WIRE_3, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_3.l, _newCfg_T_27 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect reg_pmp[3].cfg, newCfg_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1494:17] node _reg_pmp_3_cfg_w_T = and(newCfg_3.w, newCfg_3.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1496:31] connect reg_pmp[3].cfg.w, _reg_pmp_3_cfg_w_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1496:19] node _T_1544 = bits(reg_pmp[4].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _T_1545 = eq(_T_1544, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 47:13] node _T_1546 = bits(reg_pmp[4].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _T_1547 = and(_T_1545, _T_1546) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 47:20] node _T_1548 = and(reg_pmp[4].cfg.l, _T_1547) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 49:62] node _T_1549 = or(reg_pmp[3].cfg.l, _T_1548) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 49:44] node _T_1550 = eq(_T_1549, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:48] node _T_1551 = and(decoded_addr_74_2, _T_1550) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:45] when _T_1551 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:71] connect reg_pmp[3].addr, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1502:18] node _T_1552 = eq(reg_pmp[4].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:60] node _T_1553 = and(decoded_addr_127_2, _T_1552) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:57] when _T_1553 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:76] node _newCfg_T_28 = shr(wdata, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:29] wire newCfg_4 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] wire _newCfg_WIRE_4 : UInt<8> @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect _newCfg_WIRE_4, _newCfg_T_28 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_29 = bits(_newCfg_WIRE_4, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_4.r, _newCfg_T_29 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_30 = bits(_newCfg_WIRE_4, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_4.w, _newCfg_T_30 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_31 = bits(_newCfg_WIRE_4, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_4.x, _newCfg_T_31 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_32 = bits(_newCfg_WIRE_4, 4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_4.a, _newCfg_T_32 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_33 = bits(_newCfg_WIRE_4, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_4.res, _newCfg_T_33 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_34 = bits(_newCfg_WIRE_4, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_4.l, _newCfg_T_34 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect reg_pmp[4].cfg, newCfg_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1494:17] node _reg_pmp_4_cfg_w_T = and(newCfg_4.w, newCfg_4.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1496:31] connect reg_pmp[4].cfg.w, _reg_pmp_4_cfg_w_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1496:19] node _T_1554 = bits(reg_pmp[5].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _T_1555 = eq(_T_1554, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 47:13] node _T_1556 = bits(reg_pmp[5].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _T_1557 = and(_T_1555, _T_1556) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 47:20] node _T_1558 = and(reg_pmp[5].cfg.l, _T_1557) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 49:62] node _T_1559 = or(reg_pmp[4].cfg.l, _T_1558) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 49:44] node _T_1560 = eq(_T_1559, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:48] node _T_1561 = and(decoded_addr_45_2, _T_1560) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:45] when _T_1561 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:71] connect reg_pmp[4].addr, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1502:18] node _T_1562 = eq(reg_pmp[5].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:60] node _T_1563 = and(decoded_addr_127_2, _T_1562) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:57] when _T_1563 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:76] node _newCfg_T_35 = shr(wdata, 40) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:29] wire newCfg_5 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] wire _newCfg_WIRE_5 : UInt<8> @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect _newCfg_WIRE_5, _newCfg_T_35 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_36 = bits(_newCfg_WIRE_5, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_5.r, _newCfg_T_36 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_37 = bits(_newCfg_WIRE_5, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_5.w, _newCfg_T_37 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_38 = bits(_newCfg_WIRE_5, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_5.x, _newCfg_T_38 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_39 = bits(_newCfg_WIRE_5, 4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_5.a, _newCfg_T_39 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_40 = bits(_newCfg_WIRE_5, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_5.res, _newCfg_T_40 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_41 = bits(_newCfg_WIRE_5, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_5.l, _newCfg_T_41 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect reg_pmp[5].cfg, newCfg_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1494:17] node _reg_pmp_5_cfg_w_T = and(newCfg_5.w, newCfg_5.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1496:31] connect reg_pmp[5].cfg.w, _reg_pmp_5_cfg_w_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1496:19] node _T_1564 = bits(reg_pmp[6].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _T_1565 = eq(_T_1564, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 47:13] node _T_1566 = bits(reg_pmp[6].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _T_1567 = and(_T_1565, _T_1566) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 47:20] node _T_1568 = and(reg_pmp[6].cfg.l, _T_1567) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 49:62] node _T_1569 = or(reg_pmp[5].cfg.l, _T_1568) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 49:44] node _T_1570 = eq(_T_1569, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:48] node _T_1571 = and(decoded_addr_18_2, _T_1570) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:45] when _T_1571 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:71] connect reg_pmp[5].addr, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1502:18] node _T_1572 = eq(reg_pmp[6].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:60] node _T_1573 = and(decoded_addr_127_2, _T_1572) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:57] when _T_1573 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:76] node _newCfg_T_42 = shr(wdata, 48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:29] wire newCfg_6 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] wire _newCfg_WIRE_6 : UInt<8> @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect _newCfg_WIRE_6, _newCfg_T_42 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_43 = bits(_newCfg_WIRE_6, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_6.r, _newCfg_T_43 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_44 = bits(_newCfg_WIRE_6, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_6.w, _newCfg_T_44 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_45 = bits(_newCfg_WIRE_6, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_6.x, _newCfg_T_45 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_46 = bits(_newCfg_WIRE_6, 4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_6.a, _newCfg_T_46 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_47 = bits(_newCfg_WIRE_6, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_6.res, _newCfg_T_47 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_48 = bits(_newCfg_WIRE_6, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_6.l, _newCfg_T_48 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect reg_pmp[6].cfg, newCfg_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1494:17] node _reg_pmp_6_cfg_w_T = and(newCfg_6.w, newCfg_6.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1496:31] connect reg_pmp[6].cfg.w, _reg_pmp_6_cfg_w_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1496:19] node _T_1574 = bits(reg_pmp[7].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _T_1575 = eq(_T_1574, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 47:13] node _T_1576 = bits(reg_pmp[7].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _T_1577 = and(_T_1575, _T_1576) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 47:20] node _T_1578 = and(reg_pmp[7].cfg.l, _T_1577) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 49:62] node _T_1579 = or(reg_pmp[6].cfg.l, _T_1578) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 49:44] node _T_1580 = eq(_T_1579, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:48] node _T_1581 = and(decoded_addr_122_2, _T_1580) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:45] when _T_1581 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:71] connect reg_pmp[6].addr, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1502:18] node _T_1582 = eq(reg_pmp[7].cfg.l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:60] node _T_1583 = and(decoded_addr_127_2, _T_1582) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:57] when _T_1583 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1492:76] node _newCfg_T_49 = shr(wdata, 56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:29] wire newCfg_7 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] wire _newCfg_WIRE_7 : UInt<8> @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect _newCfg_WIRE_7, _newCfg_T_49 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_50 = bits(_newCfg_WIRE_7, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_7.r, _newCfg_T_50 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_51 = bits(_newCfg_WIRE_7, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_7.w, _newCfg_T_51 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_52 = bits(_newCfg_WIRE_7, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_7.x, _newCfg_T_52 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_53 = bits(_newCfg_WIRE_7, 4, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_7.a, _newCfg_T_53 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_54 = bits(_newCfg_WIRE_7, 6, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_7.res, _newCfg_T_54 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] node _newCfg_T_55 = bits(_newCfg_WIRE_7, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect newCfg_7.l, _newCfg_T_55 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1493:73] connect reg_pmp[7].cfg, newCfg_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1494:17] node _reg_pmp_7_cfg_w_T = and(newCfg_7.w, newCfg_7.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1496:31] connect reg_pmp[7].cfg.w, _reg_pmp_7_cfg_w_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1496:19] node _T_1584 = bits(reg_pmp[7].cfg.a, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 45:20] node _T_1585 = eq(_T_1584, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 47:13] node _T_1586 = bits(reg_pmp[7].cfg.a, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 46:26] node _T_1587 = and(_T_1585, _T_1586) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 47:20] node _T_1588 = and(reg_pmp[7].cfg.l, _T_1587) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 49:62] node _T_1589 = or(reg_pmp[7].cfg.l, _T_1588) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 49:44] node _T_1590 = eq(_T_1589, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:48] node _T_1591 = and(decoded_addr_103_2, _T_1590) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:45] when _T_1591 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1501:71] connect reg_pmp[7].addr, wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1502:18] when decoded_addr_16_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1507:35] node _reg_custom_0_T = and(wdata, UInt<64>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:23] node _reg_custom_0_T_1 = not(UInt<64>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:40] node _reg_custom_0_T_2 = and(reg_custom_0, _reg_custom_0_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:38] node _reg_custom_0_T_3 = or(_reg_custom_0_T, _reg_custom_0_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:31] connect reg_custom_0, _reg_custom_0_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:13] connect io.customCSRs[0].wen, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1509:16] when decoded_addr_3_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1507:35] node _reg_custom_1_T = and(wdata, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:23] node _reg_custom_1_T_1 = not(UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:40] node _reg_custom_1_T_2 = and(reg_custom_1, _reg_custom_1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:38] node _reg_custom_1_T_3 = or(_reg_custom_1_T, _reg_custom_1_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:31] connect reg_custom_1, _reg_custom_1_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:13] connect io.customCSRs[1].wen, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1509:16] when decoded_addr_32_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1507:35] node _reg_custom_2_T = and(wdata, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:23] node _reg_custom_2_T_1 = not(UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:40] node _reg_custom_2_T_2 = and(reg_custom_2, _reg_custom_2_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:38] node _reg_custom_2_T_3 = or(_reg_custom_2_T, _reg_custom_2_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:31] connect reg_custom_2, _reg_custom_2_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:13] connect io.customCSRs[2].wen, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1509:16] when decoded_addr_114_2 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1507:35] node _reg_custom_3_T = and(wdata, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:23] node _reg_custom_3_T_1 = not(UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:40] node _reg_custom_3_T_2 = and(reg_custom_3, _reg_custom_3_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:38] node _reg_custom_3_T_3 = or(_reg_custom_3_T, _reg_custom_3_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:31] connect reg_custom_3, _reg_custom_3_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1508:13] connect io.customCSRs[3].wen, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1509:16] when io.customCSRs[0].set : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1532:19] node _reg_custom_0_T_4 = and(io.customCSRs[0].sdata, UInt<64>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:24] node _reg_custom_0_T_5 = not(UInt<64>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:41] node _reg_custom_0_T_6 = and(reg_custom_0, _reg_custom_0_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:39] node _reg_custom_0_T_7 = or(_reg_custom_0_T_4, _reg_custom_0_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:32] connect reg_custom_0, _reg_custom_0_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:11] when io.customCSRs[1].set : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1532:19] node _reg_custom_1_T_4 = and(io.customCSRs[1].sdata, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:24] node _reg_custom_1_T_5 = not(UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:41] node _reg_custom_1_T_6 = and(reg_custom_1, _reg_custom_1_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:39] node _reg_custom_1_T_7 = or(_reg_custom_1_T_4, _reg_custom_1_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:32] connect reg_custom_1, _reg_custom_1_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:11] when io.customCSRs[2].set : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1532:19] node _reg_custom_2_T_4 = and(io.customCSRs[2].sdata, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:24] node _reg_custom_2_T_5 = not(UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:41] node _reg_custom_2_T_6 = and(reg_custom_2, _reg_custom_2_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:39] node _reg_custom_2_T_7 = or(_reg_custom_2_T_4, _reg_custom_2_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:32] connect reg_custom_2, _reg_custom_2_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:11] when io.customCSRs[3].set : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1532:19] node _reg_custom_3_T_4 = and(io.customCSRs[3].sdata, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:24] node _reg_custom_3_T_5 = not(UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:41] node _reg_custom_3_T_6 = and(reg_custom_3, _reg_custom_3_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:39] node _reg_custom_3_T_7 = or(_reg_custom_3_T_4, _reg_custom_3_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:32] connect reg_custom_3, _reg_custom_3_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1533:11] node _T_1592 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1564:14] when _T_1592 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1564:22] connect reg_satp.mode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1565:20] connect reg_vsatp.mode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1566:20] connect reg_hgatp.mode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1567:20] connect reg_satp.mode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1570:19] connect reg_satp.ppn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1571:19] connect reg_satp.asid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1572:19] connect reg_vsatp.mode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1575:20] connect reg_vsatp.ppn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1576:20] connect reg_vsatp.asid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1577:20] connect reg_hgatp.mode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1578:20] connect reg_hgatp.ppn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1579:20] connect reg_hgatp.asid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1580:20] connect reg_satp.asid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1583:20] connect reg_vsatp.asid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1584:20] connect reg_hgatp.asid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1587:20] connect reg_vsstatus.xs, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1589:19] connect reg_tselect, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1591:38] connect reg_bp[0].control.ttype, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1593:15] connect reg_bp[0].control.maskmax, UInt<3>(0h4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1594:17] connect reg_bp[0].control.reserved, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1595:18] connect reg_bp[0].control.zero, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1596:14] connect reg_bp[0].control.h, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1597:11] connect reg_bp[0].control.s, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1598:33] connect reg_bp[0].control.u, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1599:27] connect reg_bp[0].control.m, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1600:47] node _T_1593 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1601:17] when _T_1593 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1601:25] connect reg_bp[0].control.action, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1602:18] connect reg_bp[0].control.dmode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1603:17] connect reg_bp[0].control.chain, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1604:17] connect reg_bp[0].control.r, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1605:13] connect reg_bp[0].control.w, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1606:13] connect reg_bp[0].control.x, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1607:13] connect reg_bp[1].control.ttype, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1593:15] connect reg_bp[1].control.maskmax, UInt<3>(0h4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1594:17] connect reg_bp[1].control.reserved, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1595:18] connect reg_bp[1].control.zero, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1596:14] connect reg_bp[1].control.h, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1597:11] connect reg_bp[1].control.s, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1598:33] connect reg_bp[1].control.u, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1599:27] connect reg_bp[1].control.m, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1600:47] node _T_1594 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1601:17] when _T_1594 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1601:25] connect reg_bp[1].control.action, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1602:18] connect reg_bp[1].control.dmode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1603:17] connect reg_bp[1].control.chain, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1604:17] connect reg_bp[1].control.r, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1605:13] connect reg_bp[1].control.w, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1606:13] connect reg_bp[1].control.x, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1607:13] connect reg_bp[0].textra.mselect, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1611:52] connect reg_bp[0].textra.sselect, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1612:52] connect reg_bp[1].textra.mselect, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1611:52] connect reg_bp[1].textra.sselect, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1612:52] wire _reg_bp_1_WIRE : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<33>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.textra.sselect, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.textra.pad1, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] invalidate _reg_bp_1_WIRE.textra.svalue @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.textra.pad2, UInt<48>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.textra.mselect, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] invalidate _reg_bp_1_WIRE.textra.mvalue @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.address, UInt<33>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.control.r, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.control.w, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.control.x, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.control.u, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.control.s, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.control.h, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.control.m, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.control.tmatch, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.control.zero, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.control.chain, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.control.action, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.control.reserved, UInt<40>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.control.maskmax, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.control.dmode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect _reg_bp_1_WIRE.control.ttype, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:23] connect reg_bp[1], _reg_bp_1_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1615:8] connect reg_pmp[0].cfg.res, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1617:17] node _T_1595 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1618:17] when _T_1595 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1618:25] connect reg_pmp[0].cfg.a, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 37:11] connect reg_pmp[0].cfg.l, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 38:11] connect reg_pmp[1].cfg.res, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1617:17] node _T_1596 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1618:17] when _T_1596 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1618:25] connect reg_pmp[1].cfg.a, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 37:11] connect reg_pmp[1].cfg.l, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 38:11] connect reg_pmp[2].cfg.res, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1617:17] node _T_1597 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1618:17] when _T_1597 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1618:25] connect reg_pmp[2].cfg.a, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 37:11] connect reg_pmp[2].cfg.l, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 38:11] connect reg_pmp[3].cfg.res, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1617:17] node _T_1598 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1618:17] when _T_1598 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1618:25] connect reg_pmp[3].cfg.a, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 37:11] connect reg_pmp[3].cfg.l, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 38:11] connect reg_pmp[4].cfg.res, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1617:17] node _T_1599 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1618:17] when _T_1599 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1618:25] connect reg_pmp[4].cfg.a, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 37:11] connect reg_pmp[4].cfg.l, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 38:11] connect reg_pmp[5].cfg.res, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1617:17] node _T_1600 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1618:17] when _T_1600 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1618:25] connect reg_pmp[5].cfg.a, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 37:11] connect reg_pmp[5].cfg.l, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 38:11] connect reg_pmp[6].cfg.res, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1617:17] node _T_1601 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1618:17] when _T_1601 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1618:25] connect reg_pmp[6].cfg.a, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 37:11] connect reg_pmp[6].cfg.l, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 38:11] connect reg_pmp[7].cfg.res, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1617:17] node _T_1602 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1618:17] when _T_1602 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1618:25] connect reg_pmp[7].cfg.a, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 37:11] connect reg_pmp[7].cfg.l, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/PMP.scala 38:11] node _io_trace_0_exception_T = geq(io.retire, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1622:30] node _io_trace_0_exception_T_1 = and(_io_trace_0_exception_T, exception) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1622:37] connect io.trace[0].exception, _io_trace_0_exception_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1622:17] node _io_trace_0_valid_T = gt(io.retire, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1623:26] node _io_trace_0_valid_T_1 = or(_io_trace_0_valid_T, io.trace[0].exception) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1623:32] connect io.trace[0].valid, _io_trace_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1623:13] connect io.trace[0].insn, io.inst[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1624:12] connect io.trace[0].iaddr, io.pc @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1625:13] node _io_trace_0_priv_T = cat(reg_debug, reg_mstatus.prv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1626:18] connect io.trace[0].priv, _io_trace_0_priv_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1626:12] connect io.trace[0].cause, cause @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1627:13] node _io_trace_0_interrupt_T = bits(cause, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1628:25] connect io.trace[0].interrupt, _io_trace_0_interrupt_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1628:17] connect io.trace[0].tval, io.tval @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 1629:12] module BreakpointUnit : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 79:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 79:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 79:7] output io : { flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<33>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[1], flip pc : UInt<33>, flip ea : UInt<33>, flip mcontext : UInt<0>, flip scontext : UInt<0>, xcpt_if : UInt<1>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, debug_if : UInt<1>, debug_ld : UInt<1>, debug_st : UInt<1>, bpwatch : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[1]} @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 80:14] connect io.xcpt_if, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 96:14] connect io.xcpt_ld, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 97:14] connect io.xcpt_st, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 98:14] connect io.debug_if, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 99:15] connect io.debug_ld, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 100:15] connect io.debug_st, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 101:15] node _en_T = eq(io.status.debug, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 30:35] node en_lo = cat(io.bp[0].control.s, io.bp[0].control.u) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 30:56] node en_hi = cat(io.bp[0].control.m, io.bp[0].control.h) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 30:56] node _en_T_1 = cat(en_hi, en_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 30:56] node _en_T_2 = dshr(_en_T_1, io.status.prv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 30:68] node _en_T_3 = bits(_en_T_2, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 30:68] node en = and(_en_T, _en_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 30:50] node cx = and(UInt<1>(0h1), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 55:126] node _r_T = and(en, io.bp[0].control.r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 106:16] node _r_T_1 = bits(io.bp[0].control.tmatch, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 68:23] node _r_T_2 = geq(io.ea, io.bp[0].address) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 65:8] node _r_T_3 = bits(io.bp[0].control.tmatch, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 65:36] node _r_T_4 = xor(_r_T_2, _r_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 65:20] node _r_T_5 = not(io.ea) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 62:6] node _r_T_6 = bits(io.bp[0].control.tmatch, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:56] node _r_T_7 = bits(io.bp[0].address, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:83] node _r_T_8 = and(_r_T_6, _r_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:73] node _r_T_9 = bits(io.bp[0].address, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:83] node _r_T_10 = and(_r_T_8, _r_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:73] node _r_T_11 = bits(io.bp[0].address, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:83] node _r_T_12 = and(_r_T_10, _r_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:73] node r_lo = cat(_r_T_8, _r_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_hi = cat(_r_T_12, _r_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _r_T_13 = cat(r_hi, r_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _r_T_14 = or(_r_T_5, _r_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 62:9] node _r_T_15 = not(io.bp[0].address) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 62:24] node _r_T_16 = bits(io.bp[0].control.tmatch, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:56] node _r_T_17 = bits(io.bp[0].address, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:83] node _r_T_18 = and(_r_T_16, _r_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:73] node _r_T_19 = bits(io.bp[0].address, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:83] node _r_T_20 = and(_r_T_18, _r_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:73] node _r_T_21 = bits(io.bp[0].address, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:83] node _r_T_22 = and(_r_T_20, _r_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:73] node r_lo_1 = cat(_r_T_18, _r_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node r_hi_1 = cat(_r_T_22, _r_T_20) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _r_T_23 = cat(r_hi_1, r_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _r_T_24 = or(_r_T_15, _r_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 62:33] node _r_T_25 = eq(_r_T_14, _r_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 62:19] node _r_T_26 = mux(_r_T_1, _r_T_4, _r_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 68:8] node _r_T_27 = and(_r_T, _r_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 106:32] node r = and(_r_T_27, cx) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 106:58] node _w_T = and(en, io.bp[0].control.w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 107:16] node _w_T_1 = bits(io.bp[0].control.tmatch, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 68:23] node _w_T_2 = geq(io.ea, io.bp[0].address) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 65:8] node _w_T_3 = bits(io.bp[0].control.tmatch, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 65:36] node _w_T_4 = xor(_w_T_2, _w_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 65:20] node _w_T_5 = not(io.ea) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 62:6] node _w_T_6 = bits(io.bp[0].control.tmatch, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:56] node _w_T_7 = bits(io.bp[0].address, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:83] node _w_T_8 = and(_w_T_6, _w_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:73] node _w_T_9 = bits(io.bp[0].address, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:83] node _w_T_10 = and(_w_T_8, _w_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:73] node _w_T_11 = bits(io.bp[0].address, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:83] node _w_T_12 = and(_w_T_10, _w_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:73] node w_lo = cat(_w_T_8, _w_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node w_hi = cat(_w_T_12, _w_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _w_T_13 = cat(w_hi, w_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _w_T_14 = or(_w_T_5, _w_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 62:9] node _w_T_15 = not(io.bp[0].address) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 62:24] node _w_T_16 = bits(io.bp[0].control.tmatch, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:56] node _w_T_17 = bits(io.bp[0].address, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:83] node _w_T_18 = and(_w_T_16, _w_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:73] node _w_T_19 = bits(io.bp[0].address, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:83] node _w_T_20 = and(_w_T_18, _w_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:73] node _w_T_21 = bits(io.bp[0].address, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:83] node _w_T_22 = and(_w_T_20, _w_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:73] node w_lo_1 = cat(_w_T_18, _w_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node w_hi_1 = cat(_w_T_22, _w_T_20) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _w_T_23 = cat(w_hi_1, w_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _w_T_24 = or(_w_T_15, _w_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 62:33] node _w_T_25 = eq(_w_T_14, _w_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 62:19] node _w_T_26 = mux(_w_T_1, _w_T_4, _w_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 68:8] node _w_T_27 = and(_w_T, _w_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 107:32] node w = and(_w_T_27, cx) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 107:58] node _x_T = and(en, io.bp[0].control.x) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 108:16] node _x_T_1 = bits(io.bp[0].control.tmatch, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 68:23] node _x_T_2 = geq(io.pc, io.bp[0].address) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 65:8] node _x_T_3 = bits(io.bp[0].control.tmatch, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 65:36] node _x_T_4 = xor(_x_T_2, _x_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 65:20] node _x_T_5 = not(io.pc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 62:6] node _x_T_6 = bits(io.bp[0].control.tmatch, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:56] node _x_T_7 = bits(io.bp[0].address, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:83] node _x_T_8 = and(_x_T_6, _x_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:73] node _x_T_9 = bits(io.bp[0].address, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:83] node _x_T_10 = and(_x_T_8, _x_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:73] node _x_T_11 = bits(io.bp[0].address, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:83] node _x_T_12 = and(_x_T_10, _x_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:73] node x_lo = cat(_x_T_8, _x_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node x_hi = cat(_x_T_12, _x_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _x_T_13 = cat(x_hi, x_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _x_T_14 = or(_x_T_5, _x_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 62:9] node _x_T_15 = not(io.bp[0].address) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 62:24] node _x_T_16 = bits(io.bp[0].control.tmatch, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:56] node _x_T_17 = bits(io.bp[0].address, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:83] node _x_T_18 = and(_x_T_16, _x_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:73] node _x_T_19 = bits(io.bp[0].address, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:83] node _x_T_20 = and(_x_T_18, _x_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:73] node _x_T_21 = bits(io.bp[0].address, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:83] node _x_T_22 = and(_x_T_20, _x_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 59:73] node x_lo_1 = cat(_x_T_18, _x_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node x_hi_1 = cat(_x_T_22, _x_T_20) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _x_T_23 = cat(x_hi_1, x_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _x_T_24 = or(_x_T_15, _x_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 62:33] node _x_T_25 = eq(_x_T_14, _x_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 62:19] node _x_T_26 = mux(_x_T_1, _x_T_4, _x_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 68:8] node _x_T_27 = and(_x_T, _x_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 108:32] node x = and(_x_T_27, cx) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 108:58] node end = eq(io.bp[0].control.chain, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 109:15] connect io.bpwatch[0].action, io.bp[0].control.action @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 112:16] connect io.bpwatch[0].valid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 113:18] connect io.bpwatch[0].rvalid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 114:19] connect io.bpwatch[0].wvalid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 115:19] connect io.bpwatch[0].ivalid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 116:19] node _T = and(end, r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 118:15] node _T_1 = and(_T, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 118:20] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 118:27] node _io_xcpt_ld_T = eq(io.bp[0].control.action, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 118:51] connect io.xcpt_ld, _io_xcpt_ld_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 118:40] node _io_debug_ld_T = eq(io.bp[0].control.action, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 118:84] connect io.debug_ld, _io_debug_ld_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 118:73] connect io.bpwatch[0].valid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 118:107] connect io.bpwatch[0].rvalid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 118:132] node _T_2 = and(end, w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 119:15] node _T_3 = and(_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 119:20] when _T_3 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 119:27] node _io_xcpt_st_T = eq(io.bp[0].control.action, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 119:51] connect io.xcpt_st, _io_xcpt_st_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 119:40] node _io_debug_st_T = eq(io.bp[0].control.action, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 119:84] connect io.debug_st, _io_debug_st_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 119:73] connect io.bpwatch[0].valid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 119:107] connect io.bpwatch[0].wvalid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 119:132] node _T_4 = and(end, x) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 120:15] node _T_5 = and(_T_4, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 120:20] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 120:27] node _io_xcpt_if_T = eq(io.bp[0].control.action, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 120:51] connect io.xcpt_if, _io_xcpt_if_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 120:40] node _io_debug_if_T = eq(io.bp[0].control.action, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 120:84] connect io.debug_if, _io_debug_if_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 120:73] connect io.bpwatch[0].valid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 120:107] connect io.bpwatch[0].ivalid[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 120:132] node _T_6 = or(end, r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 122:10] node _T_7 = or(end, w) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 122:20] node _T_8 = or(end, x) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Breakpoint.scala 122:30] module RocketALU : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 83:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 83:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 83:7] output io : { flip dw : UInt<1>, flip fn : UInt<5>, flip in2 : UInt<64>, flip in1 : UInt<64>, out : UInt<64>, adder_out : UInt<64>, cmp_out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 72:14] node _in2_inv_T = bits(io.fn, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 58:29] node _in2_inv_T_1 = not(io.in2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 87:35] node in2_inv = mux(_in2_inv_T, _in2_inv_T_1, io.in2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 87:20] node in1_xor_in2 = xor(io.in1, in2_inv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 88:28] node in1_and_in2 = and(io.in1, in2_inv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 89:28] node _io_adder_out_T = add(io.in1, in2_inv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 90:26] node _io_adder_out_T_1 = tail(_io_adder_out_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 90:26] node _io_adder_out_T_2 = bits(io.fn, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 58:29] node _io_adder_out_T_3 = add(_io_adder_out_T_1, _io_adder_out_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 90:36] node _io_adder_out_T_4 = tail(_io_adder_out_T_3, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 90:36] connect io.adder_out, _io_adder_out_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 90:16] node _slt_T = bits(io.in1, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 94:15] node _slt_T_1 = bits(io.in2, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 94:34] node _slt_T_2 = eq(_slt_T, _slt_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 94:24] node _slt_T_3 = bits(io.adder_out, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 94:56] node _slt_T_4 = bits(io.fn, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 61:35] node _slt_T_5 = bits(io.in2, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 95:35] node _slt_T_6 = bits(io.in1, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 95:51] node _slt_T_7 = mux(_slt_T_4, _slt_T_5, _slt_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 95:8] node slt = mux(_slt_T_2, _slt_T_3, _slt_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 94:8] node _io_cmp_out_T = bits(io.fn, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 62:35] node _io_cmp_out_T_1 = bits(io.fn, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 63:30] node _io_cmp_out_T_2 = eq(_io_cmp_out_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 63:26] node _io_cmp_out_T_3 = eq(in1_xor_in2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 96:68] node _io_cmp_out_T_4 = mux(_io_cmp_out_T_2, _io_cmp_out_T_3, slt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 96:41] node _io_cmp_out_T_5 = xor(_io_cmp_out_T, _io_cmp_out_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 96:36] connect io.cmp_out, _io_cmp_out_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 96:14] node _shin_hi_32_T = bits(io.fn, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 58:29] node _shin_hi_32_T_1 = bits(io.in1, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 103:55] node _shin_hi_32_T_2 = and(_shin_hi_32_T, _shin_hi_32_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 103:46] node shin_hi_32 = mux(_shin_hi_32_T_2, UInt<32>(0hffffffff), UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 103:28] node _shin_hi_T = eq(io.dw, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 104:31] node _shin_hi_T_1 = bits(io.in1, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 104:48] node shin_hi = mux(_shin_hi_T, _shin_hi_T_1, shin_hi_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 104:24] node _shamt_T = bits(io.in2, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 105:29] node _shamt_T_1 = eq(io.dw, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 105:42] node _shamt_T_2 = and(_shamt_T, _shamt_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 105:33] node _shamt_T_3 = bits(io.in2, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 105:60] node shamt = cat(_shamt_T_2, _shamt_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 105:22] node _T = bits(io.in1, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 106:34] node shin_r = cat(shin_hi, _T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 106:18] node _shin_T = eq(io.fn, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _shin_T_1 = eq(io.fn, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _shin_T_2 = eq(io.fn, UInt<5>(0h12)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _shin_T_3 = eq(io.fn, UInt<5>(0h13)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _shin_T_4 = or(_shin_T, _shin_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _shin_T_5 = or(_shin_T_4, _shin_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _shin_T_6 = or(_shin_T_5, _shin_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _shin_T_7 = eq(_shin_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 64:33] node _shin_T_8 = shl(UInt<32>(0hffffffff), 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_9 = xor(UInt<64>(0hffffffffffffffff), _shin_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_10 = shr(shin_r, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_11 = and(_shin_T_10, _shin_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_12 = bits(shin_r, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_13 = shl(_shin_T_12, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_14 = not(_shin_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_15 = and(_shin_T_13, _shin_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_16 = or(_shin_T_11, _shin_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_17 = bits(_shin_T_9, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_18 = shl(_shin_T_17, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_19 = xor(_shin_T_9, _shin_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_20 = shr(_shin_T_16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_21 = and(_shin_T_20, _shin_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_22 = bits(_shin_T_16, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_23 = shl(_shin_T_22, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_24 = not(_shin_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_25 = and(_shin_T_23, _shin_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_26 = or(_shin_T_21, _shin_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_27 = bits(_shin_T_19, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_28 = shl(_shin_T_27, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_29 = xor(_shin_T_19, _shin_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_30 = shr(_shin_T_26, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_31 = and(_shin_T_30, _shin_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_32 = bits(_shin_T_26, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_33 = shl(_shin_T_32, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_34 = not(_shin_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_35 = and(_shin_T_33, _shin_T_34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_36 = or(_shin_T_31, _shin_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_37 = bits(_shin_T_29, 59, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_38 = shl(_shin_T_37, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_39 = xor(_shin_T_29, _shin_T_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_40 = shr(_shin_T_36, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_41 = and(_shin_T_40, _shin_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_42 = bits(_shin_T_36, 59, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_43 = shl(_shin_T_42, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_44 = not(_shin_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_45 = and(_shin_T_43, _shin_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_46 = or(_shin_T_41, _shin_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_47 = bits(_shin_T_39, 61, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_48 = shl(_shin_T_47, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_49 = xor(_shin_T_39, _shin_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_50 = shr(_shin_T_46, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_51 = and(_shin_T_50, _shin_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_52 = bits(_shin_T_46, 61, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_53 = shl(_shin_T_52, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_54 = not(_shin_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_55 = and(_shin_T_53, _shin_T_54) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_56 = or(_shin_T_51, _shin_T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_57 = bits(_shin_T_49, 62, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_58 = shl(_shin_T_57, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_59 = xor(_shin_T_49, _shin_T_58) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_60 = shr(_shin_T_56, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_61 = and(_shin_T_60, _shin_T_59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_62 = bits(_shin_T_56, 62, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_63 = shl(_shin_T_62, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_64 = not(_shin_T_59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_65 = and(_shin_T_63, _shin_T_64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node _shin_T_66 = or(_shin_T_61, _shin_T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:46] node shin = mux(_shin_T_7, _shin_T_66, shin_r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 108:17] node _shout_r_T = bits(io.fn, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 58:29] node _shout_r_T_1 = bits(shin, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 109:41] node _shout_r_T_2 = and(_shout_r_T, _shout_r_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 109:35] node _shout_r_T_3 = cat(_shout_r_T_2, shin) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 109:21] node _shout_r_T_4 = asSInt(_shout_r_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 109:57] node _shout_r_T_5 = dshr(_shout_r_T_4, shamt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 109:64] node shout_r = bits(_shout_r_T_5, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 109:73] node _shout_l_T = shl(UInt<32>(0hffffffff), 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_1 = xor(UInt<64>(0hffffffffffffffff), _shout_l_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_2 = shr(shout_r, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_3 = and(_shout_l_T_2, _shout_l_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_4 = bits(shout_r, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_5 = shl(_shout_l_T_4, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_6 = not(_shout_l_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_7 = and(_shout_l_T_5, _shout_l_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_8 = or(_shout_l_T_3, _shout_l_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_9 = bits(_shout_l_T_1, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_10 = shl(_shout_l_T_9, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_11 = xor(_shout_l_T_1, _shout_l_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_12 = shr(_shout_l_T_8, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_13 = and(_shout_l_T_12, _shout_l_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_14 = bits(_shout_l_T_8, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_15 = shl(_shout_l_T_14, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_16 = not(_shout_l_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_17 = and(_shout_l_T_15, _shout_l_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_18 = or(_shout_l_T_13, _shout_l_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_19 = bits(_shout_l_T_11, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_20 = shl(_shout_l_T_19, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_21 = xor(_shout_l_T_11, _shout_l_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_22 = shr(_shout_l_T_18, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_23 = and(_shout_l_T_22, _shout_l_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_24 = bits(_shout_l_T_18, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_25 = shl(_shout_l_T_24, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_26 = not(_shout_l_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_27 = and(_shout_l_T_25, _shout_l_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_28 = or(_shout_l_T_23, _shout_l_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_29 = bits(_shout_l_T_21, 59, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_30 = shl(_shout_l_T_29, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_31 = xor(_shout_l_T_21, _shout_l_T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_32 = shr(_shout_l_T_28, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_33 = and(_shout_l_T_32, _shout_l_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_34 = bits(_shout_l_T_28, 59, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_35 = shl(_shout_l_T_34, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_36 = not(_shout_l_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_37 = and(_shout_l_T_35, _shout_l_T_36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_38 = or(_shout_l_T_33, _shout_l_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_39 = bits(_shout_l_T_31, 61, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_40 = shl(_shout_l_T_39, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_41 = xor(_shout_l_T_31, _shout_l_T_40) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_42 = shr(_shout_l_T_38, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_43 = and(_shout_l_T_42, _shout_l_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_44 = bits(_shout_l_T_38, 61, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_45 = shl(_shout_l_T_44, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_46 = not(_shout_l_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_47 = and(_shout_l_T_45, _shout_l_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_48 = or(_shout_l_T_43, _shout_l_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_49 = bits(_shout_l_T_41, 62, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_50 = shl(_shout_l_T_49, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_51 = xor(_shout_l_T_41, _shout_l_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_52 = shr(_shout_l_T_48, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_53 = and(_shout_l_T_52, _shout_l_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_54 = bits(_shout_l_T_48, 62, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_55 = shl(_shout_l_T_54, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_56 = not(_shout_l_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_l_T_57 = and(_shout_l_T_55, _shout_l_T_56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node shout_l = or(_shout_l_T_53, _shout_l_T_57) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 110:24] node _shout_T = eq(io.fn, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 111:25] node _shout_T_1 = eq(io.fn, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 111:44] node _shout_T_2 = or(_shout_T, _shout_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 111:35] node _shout_T_3 = eq(io.fn, UInt<5>(0h13)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 111:64] node _shout_T_4 = or(_shout_T_2, _shout_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 111:55] node _shout_T_5 = mux(_shout_T_4, shout_r, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 111:18] node _shout_T_6 = eq(io.fn, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 112:25] node _shout_T_7 = mux(_shout_T_6, shout_l, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 112:18] node shout = or(_shout_T_5, _shout_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 111:91] node in2_not_zero = orr(io.in2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 115:29] node _logic_T = eq(io.fn, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 121:25] node _logic_T_1 = eq(io.fn, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 121:45] node _logic_T_2 = or(_logic_T, _logic_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 121:36] node _logic_T_3 = eq(io.fn, UInt<5>(0h19)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 121:64] node _logic_T_4 = or(_logic_T_2, _logic_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 121:55] node _logic_T_5 = eq(io.fn, UInt<5>(0h1a)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 121:84] node _logic_T_6 = or(_logic_T_4, _logic_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 121:75] node _logic_T_7 = mux(_logic_T_6, in1_xor_in2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 121:18] node _logic_T_8 = eq(io.fn, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 122:25] node _logic_T_9 = eq(io.fn, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 122:44] node _logic_T_10 = or(_logic_T_8, _logic_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 122:35] node _logic_T_11 = eq(io.fn, UInt<5>(0h19)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 122:64] node _logic_T_12 = or(_logic_T_10, _logic_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 122:55] node _logic_T_13 = eq(io.fn, UInt<5>(0h18)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 122:84] node _logic_T_14 = or(_logic_T_12, _logic_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 122:75] node _logic_T_15 = mux(_logic_T_14, in1_and_in2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 122:18] node logic = or(_logic_T_7, _logic_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 121:115] node _bext_mask_T = eq(io.fn, UInt<5>(0h13)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 124:52] node _bext_mask_T_1 = and(UInt<1>(0h0), _bext_mask_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 124:43] node _bext_mask_T_2 = not(UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 124:70] node bext_mask = mux(_bext_mask_T_1, UInt<1>(0h1), _bext_mask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 124:22] node _shift_logic_T = geq(io.fn, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 59:31] node _shift_logic_T_1 = leq(io.fn, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 59:48] node _shift_logic_T_2 = and(_shift_logic_T, _shift_logic_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 59:41] node _shift_logic_T_3 = and(_shift_logic_T_2, slt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 125:36] node _shift_logic_T_4 = or(_shift_logic_T_3, logic) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 125:44] node _shift_logic_T_5 = and(shout, bext_mask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 125:61] node shift_logic = or(_shift_logic_T_4, _shift_logic_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 125:52] node _tz_in_T = eq(io.dw, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 132:32] node _tz_in_T_1 = bits(io.in2, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 132:53] node _tz_in_T_2 = eq(_tz_in_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 132:46] node _tz_in_T_3 = cat(_tz_in_T, _tz_in_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 132:43] node _tz_in_T_4 = shl(UInt<32>(0hffffffff), 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_5 = xor(UInt<64>(0hffffffffffffffff), _tz_in_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_6 = shr(io.in1, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_7 = and(_tz_in_T_6, _tz_in_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_8 = bits(io.in1, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_9 = shl(_tz_in_T_8, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_10 = not(_tz_in_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_11 = and(_tz_in_T_9, _tz_in_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_12 = or(_tz_in_T_7, _tz_in_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_13 = bits(_tz_in_T_5, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_14 = shl(_tz_in_T_13, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_15 = xor(_tz_in_T_5, _tz_in_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_16 = shr(_tz_in_T_12, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_17 = and(_tz_in_T_16, _tz_in_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_18 = bits(_tz_in_T_12, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_19 = shl(_tz_in_T_18, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_20 = not(_tz_in_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_21 = and(_tz_in_T_19, _tz_in_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_22 = or(_tz_in_T_17, _tz_in_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_23 = bits(_tz_in_T_15, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_24 = shl(_tz_in_T_23, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_25 = xor(_tz_in_T_15, _tz_in_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_26 = shr(_tz_in_T_22, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_27 = and(_tz_in_T_26, _tz_in_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_28 = bits(_tz_in_T_22, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_29 = shl(_tz_in_T_28, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_30 = not(_tz_in_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_31 = and(_tz_in_T_29, _tz_in_T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_32 = or(_tz_in_T_27, _tz_in_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_33 = bits(_tz_in_T_25, 59, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_34 = shl(_tz_in_T_33, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_35 = xor(_tz_in_T_25, _tz_in_T_34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_36 = shr(_tz_in_T_32, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_37 = and(_tz_in_T_36, _tz_in_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_38 = bits(_tz_in_T_32, 59, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_39 = shl(_tz_in_T_38, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_40 = not(_tz_in_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_41 = and(_tz_in_T_39, _tz_in_T_40) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_42 = or(_tz_in_T_37, _tz_in_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_43 = bits(_tz_in_T_35, 61, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_44 = shl(_tz_in_T_43, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_45 = xor(_tz_in_T_35, _tz_in_T_44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_46 = shr(_tz_in_T_42, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_47 = and(_tz_in_T_46, _tz_in_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_48 = bits(_tz_in_T_42, 61, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_49 = shl(_tz_in_T_48, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_50 = not(_tz_in_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_51 = and(_tz_in_T_49, _tz_in_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_52 = or(_tz_in_T_47, _tz_in_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_53 = bits(_tz_in_T_45, 62, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_54 = shl(_tz_in_T_53, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_55 = xor(_tz_in_T_45, _tz_in_T_54) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_56 = shr(_tz_in_T_52, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_57 = and(_tz_in_T_56, _tz_in_T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_58 = bits(_tz_in_T_52, 62, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_59 = shl(_tz_in_T_58, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_60 = not(_tz_in_T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_61 = and(_tz_in_T_59, _tz_in_T_60) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_62 = or(_tz_in_T_57, _tz_in_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 134:19] node _tz_in_T_63 = bits(io.in1, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 135:25] node _tz_in_T_64 = cat(UInt<1>(0h1), _tz_in_T_63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 135:16] node _tz_in_T_65 = bits(io.in1, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:33] node _tz_in_T_66 = shl(UInt<16>(0hffff), 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_67 = xor(UInt<32>(0hffffffff), _tz_in_T_66) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_68 = shr(_tz_in_T_65, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_69 = and(_tz_in_T_68, _tz_in_T_67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_70 = bits(_tz_in_T_65, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_71 = shl(_tz_in_T_70, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_72 = not(_tz_in_T_67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_73 = and(_tz_in_T_71, _tz_in_T_72) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_74 = or(_tz_in_T_69, _tz_in_T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_75 = bits(_tz_in_T_67, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_76 = shl(_tz_in_T_75, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_77 = xor(_tz_in_T_67, _tz_in_T_76) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_78 = shr(_tz_in_T_74, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_79 = and(_tz_in_T_78, _tz_in_T_77) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_80 = bits(_tz_in_T_74, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_81 = shl(_tz_in_T_80, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_82 = not(_tz_in_T_77) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_83 = and(_tz_in_T_81, _tz_in_T_82) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_84 = or(_tz_in_T_79, _tz_in_T_83) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_85 = bits(_tz_in_T_77, 27, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_86 = shl(_tz_in_T_85, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_87 = xor(_tz_in_T_77, _tz_in_T_86) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_88 = shr(_tz_in_T_84, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_89 = and(_tz_in_T_88, _tz_in_T_87) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_90 = bits(_tz_in_T_84, 27, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_91 = shl(_tz_in_T_90, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_92 = not(_tz_in_T_87) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_93 = and(_tz_in_T_91, _tz_in_T_92) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_94 = or(_tz_in_T_89, _tz_in_T_93) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_95 = bits(_tz_in_T_87, 29, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_96 = shl(_tz_in_T_95, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_97 = xor(_tz_in_T_87, _tz_in_T_96) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_98 = shr(_tz_in_T_94, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_99 = and(_tz_in_T_98, _tz_in_T_97) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_100 = bits(_tz_in_T_94, 29, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_101 = shl(_tz_in_T_100, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_102 = not(_tz_in_T_97) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_103 = and(_tz_in_T_101, _tz_in_T_102) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_104 = or(_tz_in_T_99, _tz_in_T_103) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_105 = bits(_tz_in_T_97, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_106 = shl(_tz_in_T_105, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_107 = xor(_tz_in_T_97, _tz_in_T_106) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_108 = shr(_tz_in_T_104, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_109 = and(_tz_in_T_108, _tz_in_T_107) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_110 = bits(_tz_in_T_104, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_111 = shl(_tz_in_T_110, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_112 = not(_tz_in_T_107) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_113 = and(_tz_in_T_111, _tz_in_T_112) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_114 = or(_tz_in_T_109, _tz_in_T_113) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:26] node _tz_in_T_115 = cat(UInt<1>(0h1), _tz_in_T_114) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 136:16] node _tz_in_T_116 = eq(UInt<1>(0h1), _tz_in_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 132:62] node _tz_in_T_117 = mux(_tz_in_T_116, _tz_in_T_62, io.in1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 132:62] node _tz_in_T_118 = eq(UInt<2>(0h2), _tz_in_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 132:62] node _tz_in_T_119 = mux(_tz_in_T_118, _tz_in_T_64, _tz_in_T_117) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 132:62] node _tz_in_T_120 = eq(UInt<2>(0h3), _tz_in_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 132:62] node tz_in = mux(_tz_in_T_120, _tz_in_T_115, _tz_in_T_119) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 132:62] node _popc_in_T = bits(io.in2, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 138:27] node _popc_in_T_1 = eq(io.dw, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 139:15] node _popc_in_T_2 = bits(io.in1, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 139:32] node _popc_in_T_3 = mux(_popc_in_T_1, _popc_in_T_2, io.in1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 139:8] node _popc_in_T_4 = cat(UInt<1>(0h1), tz_in) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 140:27] node _popc_in_T_5 = bits(_popc_in_T_4, 0, 0) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_6 = bits(_popc_in_T_4, 1, 1) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_7 = bits(_popc_in_T_4, 2, 2) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_8 = bits(_popc_in_T_4, 3, 3) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_9 = bits(_popc_in_T_4, 4, 4) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_10 = bits(_popc_in_T_4, 5, 5) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_11 = bits(_popc_in_T_4, 6, 6) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_12 = bits(_popc_in_T_4, 7, 7) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_13 = bits(_popc_in_T_4, 8, 8) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_14 = bits(_popc_in_T_4, 9, 9) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_15 = bits(_popc_in_T_4, 10, 10) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_16 = bits(_popc_in_T_4, 11, 11) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_17 = bits(_popc_in_T_4, 12, 12) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_18 = bits(_popc_in_T_4, 13, 13) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_19 = bits(_popc_in_T_4, 14, 14) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_20 = bits(_popc_in_T_4, 15, 15) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_21 = bits(_popc_in_T_4, 16, 16) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_22 = bits(_popc_in_T_4, 17, 17) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_23 = bits(_popc_in_T_4, 18, 18) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_24 = bits(_popc_in_T_4, 19, 19) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_25 = bits(_popc_in_T_4, 20, 20) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_26 = bits(_popc_in_T_4, 21, 21) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_27 = bits(_popc_in_T_4, 22, 22) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_28 = bits(_popc_in_T_4, 23, 23) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_29 = bits(_popc_in_T_4, 24, 24) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_30 = bits(_popc_in_T_4, 25, 25) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_31 = bits(_popc_in_T_4, 26, 26) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_32 = bits(_popc_in_T_4, 27, 27) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_33 = bits(_popc_in_T_4, 28, 28) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_34 = bits(_popc_in_T_4, 29, 29) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_35 = bits(_popc_in_T_4, 30, 30) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_36 = bits(_popc_in_T_4, 31, 31) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_37 = bits(_popc_in_T_4, 32, 32) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_38 = bits(_popc_in_T_4, 33, 33) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_39 = bits(_popc_in_T_4, 34, 34) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_40 = bits(_popc_in_T_4, 35, 35) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_41 = bits(_popc_in_T_4, 36, 36) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_42 = bits(_popc_in_T_4, 37, 37) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_43 = bits(_popc_in_T_4, 38, 38) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_44 = bits(_popc_in_T_4, 39, 39) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_45 = bits(_popc_in_T_4, 40, 40) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_46 = bits(_popc_in_T_4, 41, 41) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_47 = bits(_popc_in_T_4, 42, 42) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_48 = bits(_popc_in_T_4, 43, 43) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_49 = bits(_popc_in_T_4, 44, 44) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_50 = bits(_popc_in_T_4, 45, 45) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_51 = bits(_popc_in_T_4, 46, 46) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_52 = bits(_popc_in_T_4, 47, 47) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_53 = bits(_popc_in_T_4, 48, 48) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_54 = bits(_popc_in_T_4, 49, 49) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_55 = bits(_popc_in_T_4, 50, 50) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_56 = bits(_popc_in_T_4, 51, 51) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_57 = bits(_popc_in_T_4, 52, 52) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_58 = bits(_popc_in_T_4, 53, 53) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_59 = bits(_popc_in_T_4, 54, 54) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_60 = bits(_popc_in_T_4, 55, 55) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_61 = bits(_popc_in_T_4, 56, 56) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_62 = bits(_popc_in_T_4, 57, 57) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_63 = bits(_popc_in_T_4, 58, 58) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_64 = bits(_popc_in_T_4, 59, 59) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_65 = bits(_popc_in_T_4, 60, 60) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_66 = bits(_popc_in_T_4, 61, 61) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_67 = bits(_popc_in_T_4, 62, 62) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_68 = bits(_popc_in_T_4, 63, 63) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_69 = bits(_popc_in_T_4, 64, 64) @[src/main/scala/chisel3/util/OneHot.scala 85:71] node _popc_in_T_70 = mux(_popc_in_T_69, UInt<65>(0h10000000000000000), UInt<65>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_71 = mux(_popc_in_T_68, UInt<65>(0h8000000000000000), _popc_in_T_70) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_72 = mux(_popc_in_T_67, UInt<65>(0h4000000000000000), _popc_in_T_71) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_73 = mux(_popc_in_T_66, UInt<65>(0h2000000000000000), _popc_in_T_72) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_74 = mux(_popc_in_T_65, UInt<65>(0h1000000000000000), _popc_in_T_73) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_75 = mux(_popc_in_T_64, UInt<65>(0h800000000000000), _popc_in_T_74) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_76 = mux(_popc_in_T_63, UInt<65>(0h400000000000000), _popc_in_T_75) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_77 = mux(_popc_in_T_62, UInt<65>(0h200000000000000), _popc_in_T_76) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_78 = mux(_popc_in_T_61, UInt<65>(0h100000000000000), _popc_in_T_77) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_79 = mux(_popc_in_T_60, UInt<65>(0h80000000000000), _popc_in_T_78) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_80 = mux(_popc_in_T_59, UInt<65>(0h40000000000000), _popc_in_T_79) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_81 = mux(_popc_in_T_58, UInt<65>(0h20000000000000), _popc_in_T_80) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_82 = mux(_popc_in_T_57, UInt<65>(0h10000000000000), _popc_in_T_81) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_83 = mux(_popc_in_T_56, UInt<65>(0h8000000000000), _popc_in_T_82) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_84 = mux(_popc_in_T_55, UInt<65>(0h4000000000000), _popc_in_T_83) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_85 = mux(_popc_in_T_54, UInt<65>(0h2000000000000), _popc_in_T_84) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_86 = mux(_popc_in_T_53, UInt<65>(0h1000000000000), _popc_in_T_85) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_87 = mux(_popc_in_T_52, UInt<65>(0h800000000000), _popc_in_T_86) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_88 = mux(_popc_in_T_51, UInt<65>(0h400000000000), _popc_in_T_87) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_89 = mux(_popc_in_T_50, UInt<65>(0h200000000000), _popc_in_T_88) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_90 = mux(_popc_in_T_49, UInt<65>(0h100000000000), _popc_in_T_89) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_91 = mux(_popc_in_T_48, UInt<65>(0h80000000000), _popc_in_T_90) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_92 = mux(_popc_in_T_47, UInt<65>(0h40000000000), _popc_in_T_91) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_93 = mux(_popc_in_T_46, UInt<65>(0h20000000000), _popc_in_T_92) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_94 = mux(_popc_in_T_45, UInt<65>(0h10000000000), _popc_in_T_93) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_95 = mux(_popc_in_T_44, UInt<65>(0h8000000000), _popc_in_T_94) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_96 = mux(_popc_in_T_43, UInt<65>(0h4000000000), _popc_in_T_95) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_97 = mux(_popc_in_T_42, UInt<65>(0h2000000000), _popc_in_T_96) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_98 = mux(_popc_in_T_41, UInt<65>(0h1000000000), _popc_in_T_97) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_99 = mux(_popc_in_T_40, UInt<65>(0h800000000), _popc_in_T_98) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_100 = mux(_popc_in_T_39, UInt<65>(0h400000000), _popc_in_T_99) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_101 = mux(_popc_in_T_38, UInt<65>(0h200000000), _popc_in_T_100) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_102 = mux(_popc_in_T_37, UInt<65>(0h100000000), _popc_in_T_101) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_103 = mux(_popc_in_T_36, UInt<65>(0h80000000), _popc_in_T_102) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_104 = mux(_popc_in_T_35, UInt<65>(0h40000000), _popc_in_T_103) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_105 = mux(_popc_in_T_34, UInt<65>(0h20000000), _popc_in_T_104) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_106 = mux(_popc_in_T_33, UInt<65>(0h10000000), _popc_in_T_105) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_107 = mux(_popc_in_T_32, UInt<65>(0h8000000), _popc_in_T_106) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_108 = mux(_popc_in_T_31, UInt<65>(0h4000000), _popc_in_T_107) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_109 = mux(_popc_in_T_30, UInt<65>(0h2000000), _popc_in_T_108) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_110 = mux(_popc_in_T_29, UInt<65>(0h1000000), _popc_in_T_109) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_111 = mux(_popc_in_T_28, UInt<65>(0h800000), _popc_in_T_110) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_112 = mux(_popc_in_T_27, UInt<65>(0h400000), _popc_in_T_111) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_113 = mux(_popc_in_T_26, UInt<65>(0h200000), _popc_in_T_112) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_114 = mux(_popc_in_T_25, UInt<65>(0h100000), _popc_in_T_113) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_115 = mux(_popc_in_T_24, UInt<65>(0h80000), _popc_in_T_114) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_116 = mux(_popc_in_T_23, UInt<65>(0h40000), _popc_in_T_115) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_117 = mux(_popc_in_T_22, UInt<65>(0h20000), _popc_in_T_116) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_118 = mux(_popc_in_T_21, UInt<65>(0h10000), _popc_in_T_117) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_119 = mux(_popc_in_T_20, UInt<65>(0h8000), _popc_in_T_118) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_120 = mux(_popc_in_T_19, UInt<65>(0h4000), _popc_in_T_119) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_121 = mux(_popc_in_T_18, UInt<65>(0h2000), _popc_in_T_120) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_122 = mux(_popc_in_T_17, UInt<65>(0h1000), _popc_in_T_121) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_123 = mux(_popc_in_T_16, UInt<65>(0h800), _popc_in_T_122) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_124 = mux(_popc_in_T_15, UInt<65>(0h400), _popc_in_T_123) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_125 = mux(_popc_in_T_14, UInt<65>(0h200), _popc_in_T_124) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_126 = mux(_popc_in_T_13, UInt<65>(0h100), _popc_in_T_125) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_127 = mux(_popc_in_T_12, UInt<65>(0h80), _popc_in_T_126) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_128 = mux(_popc_in_T_11, UInt<65>(0h40), _popc_in_T_127) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_129 = mux(_popc_in_T_10, UInt<65>(0h20), _popc_in_T_128) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_130 = mux(_popc_in_T_9, UInt<65>(0h10), _popc_in_T_129) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_131 = mux(_popc_in_T_8, UInt<65>(0h8), _popc_in_T_130) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_132 = mux(_popc_in_T_7, UInt<65>(0h4), _popc_in_T_131) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_133 = mux(_popc_in_T_6, UInt<65>(0h2), _popc_in_T_132) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_134 = mux(_popc_in_T_5, UInt<65>(0h1), _popc_in_T_133) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _popc_in_T_135 = sub(_popc_in_T_134, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 140:37] node _popc_in_T_136 = tail(_popc_in_T_135, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 140:37] node _popc_in_T_137 = mux(_popc_in_T, _popc_in_T_3, _popc_in_T_136) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 138:20] node popc_in = bits(_popc_in_T_137, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 140:43] node _count_T = bits(popc_in, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_1 = bits(popc_in, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_2 = bits(popc_in, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_3 = bits(popc_in, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_4 = bits(popc_in, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_5 = bits(popc_in, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_6 = bits(popc_in, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_7 = bits(popc_in, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_8 = bits(popc_in, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_9 = bits(popc_in, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_10 = bits(popc_in, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_11 = bits(popc_in, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_12 = bits(popc_in, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_13 = bits(popc_in, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_14 = bits(popc_in, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_15 = bits(popc_in, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_16 = bits(popc_in, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_17 = bits(popc_in, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_18 = bits(popc_in, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_19 = bits(popc_in, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_20 = bits(popc_in, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_21 = bits(popc_in, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_22 = bits(popc_in, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_23 = bits(popc_in, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_24 = bits(popc_in, 24, 24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_25 = bits(popc_in, 25, 25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_26 = bits(popc_in, 26, 26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_27 = bits(popc_in, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_28 = bits(popc_in, 28, 28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_29 = bits(popc_in, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_30 = bits(popc_in, 30, 30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_31 = bits(popc_in, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_32 = bits(popc_in, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_33 = bits(popc_in, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_34 = bits(popc_in, 34, 34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_35 = bits(popc_in, 35, 35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_36 = bits(popc_in, 36, 36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_37 = bits(popc_in, 37, 37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_38 = bits(popc_in, 38, 38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_39 = bits(popc_in, 39, 39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_40 = bits(popc_in, 40, 40) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_41 = bits(popc_in, 41, 41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_42 = bits(popc_in, 42, 42) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_43 = bits(popc_in, 43, 43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_44 = bits(popc_in, 44, 44) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_45 = bits(popc_in, 45, 45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_46 = bits(popc_in, 46, 46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_47 = bits(popc_in, 47, 47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_48 = bits(popc_in, 48, 48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_49 = bits(popc_in, 49, 49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_50 = bits(popc_in, 50, 50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_51 = bits(popc_in, 51, 51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_52 = bits(popc_in, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_53 = bits(popc_in, 53, 53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_54 = bits(popc_in, 54, 54) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_55 = bits(popc_in, 55, 55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_56 = bits(popc_in, 56, 56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_57 = bits(popc_in, 57, 57) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_58 = bits(popc_in, 58, 58) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_59 = bits(popc_in, 59, 59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_60 = bits(popc_in, 60, 60) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_61 = bits(popc_in, 61, 61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_62 = bits(popc_in, 62, 62) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_63 = bits(popc_in, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_64 = add(_count_T, _count_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_65 = bits(_count_T_64, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_66 = add(_count_T_2, _count_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_67 = bits(_count_T_66, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_68 = add(_count_T_65, _count_T_67) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_69 = bits(_count_T_68, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_70 = add(_count_T_4, _count_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_71 = bits(_count_T_70, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_72 = add(_count_T_6, _count_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_73 = bits(_count_T_72, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_74 = add(_count_T_71, _count_T_73) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_75 = bits(_count_T_74, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_76 = add(_count_T_69, _count_T_75) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_77 = bits(_count_T_76, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_78 = add(_count_T_8, _count_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_79 = bits(_count_T_78, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_80 = add(_count_T_10, _count_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_81 = bits(_count_T_80, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_82 = add(_count_T_79, _count_T_81) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_83 = bits(_count_T_82, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_84 = add(_count_T_12, _count_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_85 = bits(_count_T_84, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_86 = add(_count_T_14, _count_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_87 = bits(_count_T_86, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_88 = add(_count_T_85, _count_T_87) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_89 = bits(_count_T_88, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_90 = add(_count_T_83, _count_T_89) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_91 = bits(_count_T_90, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_92 = add(_count_T_77, _count_T_91) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_93 = bits(_count_T_92, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_94 = add(_count_T_16, _count_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_95 = bits(_count_T_94, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_96 = add(_count_T_18, _count_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_97 = bits(_count_T_96, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_98 = add(_count_T_95, _count_T_97) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_99 = bits(_count_T_98, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_100 = add(_count_T_20, _count_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_101 = bits(_count_T_100, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_102 = add(_count_T_22, _count_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_103 = bits(_count_T_102, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_104 = add(_count_T_101, _count_T_103) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_105 = bits(_count_T_104, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_106 = add(_count_T_99, _count_T_105) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_107 = bits(_count_T_106, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_108 = add(_count_T_24, _count_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_109 = bits(_count_T_108, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_110 = add(_count_T_26, _count_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_111 = bits(_count_T_110, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_112 = add(_count_T_109, _count_T_111) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_113 = bits(_count_T_112, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_114 = add(_count_T_28, _count_T_29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_115 = bits(_count_T_114, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_116 = add(_count_T_30, _count_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_117 = bits(_count_T_116, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_118 = add(_count_T_115, _count_T_117) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_119 = bits(_count_T_118, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_120 = add(_count_T_113, _count_T_119) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_121 = bits(_count_T_120, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_122 = add(_count_T_107, _count_T_121) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_123 = bits(_count_T_122, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_124 = add(_count_T_93, _count_T_123) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_125 = bits(_count_T_124, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_126 = add(_count_T_32, _count_T_33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_127 = bits(_count_T_126, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_128 = add(_count_T_34, _count_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_129 = bits(_count_T_128, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_130 = add(_count_T_127, _count_T_129) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_131 = bits(_count_T_130, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_132 = add(_count_T_36, _count_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_133 = bits(_count_T_132, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_134 = add(_count_T_38, _count_T_39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_135 = bits(_count_T_134, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_136 = add(_count_T_133, _count_T_135) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_137 = bits(_count_T_136, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_138 = add(_count_T_131, _count_T_137) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_139 = bits(_count_T_138, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_140 = add(_count_T_40, _count_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_141 = bits(_count_T_140, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_142 = add(_count_T_42, _count_T_43) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_143 = bits(_count_T_142, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_144 = add(_count_T_141, _count_T_143) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_145 = bits(_count_T_144, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_146 = add(_count_T_44, _count_T_45) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_147 = bits(_count_T_146, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_148 = add(_count_T_46, _count_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_149 = bits(_count_T_148, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_150 = add(_count_T_147, _count_T_149) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_151 = bits(_count_T_150, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_152 = add(_count_T_145, _count_T_151) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_153 = bits(_count_T_152, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_154 = add(_count_T_139, _count_T_153) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_155 = bits(_count_T_154, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_156 = add(_count_T_48, _count_T_49) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_157 = bits(_count_T_156, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_158 = add(_count_T_50, _count_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_159 = bits(_count_T_158, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_160 = add(_count_T_157, _count_T_159) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_161 = bits(_count_T_160, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_162 = add(_count_T_52, _count_T_53) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_163 = bits(_count_T_162, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_164 = add(_count_T_54, _count_T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_165 = bits(_count_T_164, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_166 = add(_count_T_163, _count_T_165) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_167 = bits(_count_T_166, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_168 = add(_count_T_161, _count_T_167) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_169 = bits(_count_T_168, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_170 = add(_count_T_56, _count_T_57) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_171 = bits(_count_T_170, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_172 = add(_count_T_58, _count_T_59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_173 = bits(_count_T_172, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_174 = add(_count_T_171, _count_T_173) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_175 = bits(_count_T_174, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_176 = add(_count_T_60, _count_T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_177 = bits(_count_T_176, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_178 = add(_count_T_62, _count_T_63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_179 = bits(_count_T_178, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_180 = add(_count_T_177, _count_T_179) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_181 = bits(_count_T_180, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_182 = add(_count_T_175, _count_T_181) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_183 = bits(_count_T_182, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_184 = add(_count_T_169, _count_T_183) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_185 = bits(_count_T_184, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_186 = add(_count_T_155, _count_T_185) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_187 = bits(_count_T_186, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node _count_T_188 = add(_count_T_125, _count_T_187) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] node count = bits(_count_T_188, 6, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 141:23] wire in1_bytes : UInt<8>[8] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] wire _in1_bytes_WIRE : UInt<64> @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] connect _in1_bytes_WIRE, io.in1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] node _in1_bytes_T = bits(_in1_bytes_WIRE, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] connect in1_bytes[0], _in1_bytes_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] node _in1_bytes_T_1 = bits(_in1_bytes_WIRE, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] connect in1_bytes[1], _in1_bytes_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] node _in1_bytes_T_2 = bits(_in1_bytes_WIRE, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] connect in1_bytes[2], _in1_bytes_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] node _in1_bytes_T_3 = bits(_in1_bytes_WIRE, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] connect in1_bytes[3], _in1_bytes_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] node _in1_bytes_T_4 = bits(_in1_bytes_WIRE, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] connect in1_bytes[4], _in1_bytes_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] node _in1_bytes_T_5 = bits(_in1_bytes_WIRE, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] connect in1_bytes[5], _in1_bytes_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] node _in1_bytes_T_6 = bits(_in1_bytes_WIRE, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] connect in1_bytes[6], _in1_bytes_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] node _in1_bytes_T_7 = bits(_in1_bytes_WIRE, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] connect in1_bytes[7], _in1_bytes_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 142:34] node _orcb_T = neq(in1_bytes[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:51] node _orcb_T_1 = mux(_orcb_T, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:45] node _orcb_T_2 = neq(in1_bytes[1], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:51] node _orcb_T_3 = mux(_orcb_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:45] node _orcb_T_4 = neq(in1_bytes[2], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:51] node _orcb_T_5 = mux(_orcb_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:45] node _orcb_T_6 = neq(in1_bytes[3], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:51] node _orcb_T_7 = mux(_orcb_T_6, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:45] node _orcb_T_8 = neq(in1_bytes[4], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:51] node _orcb_T_9 = mux(_orcb_T_8, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:45] node _orcb_T_10 = neq(in1_bytes[5], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:51] node _orcb_T_11 = mux(_orcb_T_10, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:45] node _orcb_T_12 = neq(in1_bytes[6], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:51] node _orcb_T_13 = mux(_orcb_T_12, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:45] node _orcb_T_14 = neq(in1_bytes[7], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:51] node _orcb_T_15 = mux(_orcb_T_14, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:45] wire _orcb_WIRE : UInt<8>[8] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:21] connect _orcb_WIRE[0], _orcb_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:21] connect _orcb_WIRE[1], _orcb_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:21] connect _orcb_WIRE[2], _orcb_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:21] connect _orcb_WIRE[3], _orcb_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:21] connect _orcb_WIRE[4], _orcb_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:21] connect _orcb_WIRE[5], _orcb_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:21] connect _orcb_WIRE[6], _orcb_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:21] connect _orcb_WIRE[7], _orcb_T_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:21] node orcb_lo_lo = cat(_orcb_WIRE[1], _orcb_WIRE[0]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:62] node orcb_lo_hi = cat(_orcb_WIRE[3], _orcb_WIRE[2]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:62] node orcb_lo = cat(orcb_lo_hi, orcb_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:62] node orcb_hi_lo = cat(_orcb_WIRE[5], _orcb_WIRE[4]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:62] node orcb_hi_hi = cat(_orcb_WIRE[7], _orcb_WIRE[6]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:62] node orcb_hi = cat(orcb_hi_hi, orcb_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:62] node orcb = cat(orcb_hi, orcb_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 143:62] wire _rev8_WIRE : UInt<8>[8] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 144:21] connect _rev8_WIRE[0], in1_bytes[7] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 144:21] connect _rev8_WIRE[1], in1_bytes[6] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 144:21] connect _rev8_WIRE[2], in1_bytes[5] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 144:21] connect _rev8_WIRE[3], in1_bytes[4] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 144:21] connect _rev8_WIRE[4], in1_bytes[3] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 144:21] connect _rev8_WIRE[5], in1_bytes[2] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 144:21] connect _rev8_WIRE[6], in1_bytes[1] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 144:21] connect _rev8_WIRE[7], in1_bytes[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 144:21] node rev8_lo_lo = cat(_rev8_WIRE[1], _rev8_WIRE[0]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 144:41] node rev8_lo_hi = cat(_rev8_WIRE[3], _rev8_WIRE[2]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 144:41] node rev8_lo = cat(rev8_lo_hi, rev8_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 144:41] node rev8_hi_lo = cat(_rev8_WIRE[5], _rev8_WIRE[4]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 144:41] node rev8_hi_hi = cat(_rev8_WIRE[7], _rev8_WIRE[6]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 144:41] node rev8_hi = cat(rev8_hi_hi, rev8_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 144:41] node rev8 = cat(rev8_hi, rev8_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 144:41] node _unary_T = bits(io.in2, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 145:31] node _unary_T_1 = bits(io.in1, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 148:22] node _unary_T_2 = bits(io.in1, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 149:35] node _unary_T_3 = mux(_unary_T_2, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 149:20] node _unary_T_4 = bits(io.in1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 149:49] node _unary_T_5 = cat(_unary_T_3, _unary_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 149:40] node _unary_T_6 = bits(io.in1, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 150:36] node _unary_T_7 = mux(_unary_T_6, UInt<48>(0hffffffffffff), UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 150:20] node _unary_T_8 = bits(io.in1, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 150:51] node _unary_T_9 = cat(_unary_T_7, _unary_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 150:42] node _unary_T_10 = eq(UInt<10>(0h287), _unary_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 145:45] node _unary_T_11 = mux(_unary_T_10, orcb, count) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 145:45] node _unary_T_12 = eq(UInt<11>(0h6b8), _unary_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 145:45] node _unary_T_13 = mux(_unary_T_12, rev8, _unary_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 145:45] node _unary_T_14 = eq(UInt<8>(0h80), _unary_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 145:45] node _unary_T_15 = mux(_unary_T_14, _unary_T_1, _unary_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 145:45] node _unary_T_16 = eq(UInt<11>(0h604), _unary_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 145:45] node _unary_T_17 = mux(_unary_T_16, _unary_T_5, _unary_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 145:45] node _unary_T_18 = eq(UInt<11>(0h605), _unary_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 145:45] node unary = mux(_unary_T_18, _unary_T_9, _unary_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 145:45] node maxmin_out = mux(io.cmp_out, io.in2, io.in1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 154:23] node _rot_shamt_T = eq(io.dw, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 157:29] node _rot_shamt_T_1 = mux(_rot_shamt_T, UInt<6>(0h20), UInt<7>(0h40)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 157:22] node _rot_shamt_T_2 = sub(_rot_shamt_T_1, shamt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 157:54] node rot_shamt = tail(_rot_shamt_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 157:54] node _rotin_T = bits(io.fn, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:24] node _rotin_T_1 = shl(UInt<32>(0hffffffff), 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_2 = xor(UInt<64>(0hffffffffffffffff), _rotin_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_3 = shr(shin_r, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_4 = and(_rotin_T_3, _rotin_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_5 = bits(shin_r, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_6 = shl(_rotin_T_5, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_7 = not(_rotin_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_8 = and(_rotin_T_6, _rotin_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_9 = or(_rotin_T_4, _rotin_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_10 = bits(_rotin_T_2, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_11 = shl(_rotin_T_10, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_12 = xor(_rotin_T_2, _rotin_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_13 = shr(_rotin_T_9, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_14 = and(_rotin_T_13, _rotin_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_15 = bits(_rotin_T_9, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_16 = shl(_rotin_T_15, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_17 = not(_rotin_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_18 = and(_rotin_T_16, _rotin_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_19 = or(_rotin_T_14, _rotin_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_20 = bits(_rotin_T_12, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_21 = shl(_rotin_T_20, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_22 = xor(_rotin_T_12, _rotin_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_23 = shr(_rotin_T_19, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_24 = and(_rotin_T_23, _rotin_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_25 = bits(_rotin_T_19, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_26 = shl(_rotin_T_25, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_27 = not(_rotin_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_28 = and(_rotin_T_26, _rotin_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_29 = or(_rotin_T_24, _rotin_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_30 = bits(_rotin_T_22, 59, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_31 = shl(_rotin_T_30, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_32 = xor(_rotin_T_22, _rotin_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_33 = shr(_rotin_T_29, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_34 = and(_rotin_T_33, _rotin_T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_35 = bits(_rotin_T_29, 59, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_36 = shl(_rotin_T_35, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_37 = not(_rotin_T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_38 = and(_rotin_T_36, _rotin_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_39 = or(_rotin_T_34, _rotin_T_38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_40 = bits(_rotin_T_32, 61, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_41 = shl(_rotin_T_40, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_42 = xor(_rotin_T_32, _rotin_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_43 = shr(_rotin_T_39, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_44 = and(_rotin_T_43, _rotin_T_42) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_45 = bits(_rotin_T_39, 61, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_46 = shl(_rotin_T_45, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_47 = not(_rotin_T_42) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_48 = and(_rotin_T_46, _rotin_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_49 = or(_rotin_T_44, _rotin_T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_50 = bits(_rotin_T_42, 62, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_51 = shl(_rotin_T_50, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_52 = xor(_rotin_T_42, _rotin_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_53 = shr(_rotin_T_49, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_54 = and(_rotin_T_53, _rotin_T_52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_55 = bits(_rotin_T_49, 62, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_56 = shl(_rotin_T_55, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_57 = not(_rotin_T_52) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_58 = and(_rotin_T_56, _rotin_T_57) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node _rotin_T_59 = or(_rotin_T_54, _rotin_T_58) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:44] node rotin = mux(_rotin_T, shin_r, _rotin_T_59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 158:18] node _rotout_r_T = dshr(rotin, rot_shamt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 159:25] node rotout_r = bits(_rotout_r_T, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 159:38] node _rotout_l_T = shl(UInt<32>(0hffffffff), 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_1 = xor(UInt<64>(0hffffffffffffffff), _rotout_l_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_2 = shr(rotout_r, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_3 = and(_rotout_l_T_2, _rotout_l_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_4 = bits(rotout_r, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_5 = shl(_rotout_l_T_4, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_6 = not(_rotout_l_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_7 = and(_rotout_l_T_5, _rotout_l_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_8 = or(_rotout_l_T_3, _rotout_l_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_9 = bits(_rotout_l_T_1, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_10 = shl(_rotout_l_T_9, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_11 = xor(_rotout_l_T_1, _rotout_l_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_12 = shr(_rotout_l_T_8, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_13 = and(_rotout_l_T_12, _rotout_l_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_14 = bits(_rotout_l_T_8, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_15 = shl(_rotout_l_T_14, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_16 = not(_rotout_l_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_17 = and(_rotout_l_T_15, _rotout_l_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_18 = or(_rotout_l_T_13, _rotout_l_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_19 = bits(_rotout_l_T_11, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_20 = shl(_rotout_l_T_19, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_21 = xor(_rotout_l_T_11, _rotout_l_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_22 = shr(_rotout_l_T_18, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_23 = and(_rotout_l_T_22, _rotout_l_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_24 = bits(_rotout_l_T_18, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_25 = shl(_rotout_l_T_24, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_26 = not(_rotout_l_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_27 = and(_rotout_l_T_25, _rotout_l_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_28 = or(_rotout_l_T_23, _rotout_l_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_29 = bits(_rotout_l_T_21, 59, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_30 = shl(_rotout_l_T_29, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_31 = xor(_rotout_l_T_21, _rotout_l_T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_32 = shr(_rotout_l_T_28, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_33 = and(_rotout_l_T_32, _rotout_l_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_34 = bits(_rotout_l_T_28, 59, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_35 = shl(_rotout_l_T_34, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_36 = not(_rotout_l_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_37 = and(_rotout_l_T_35, _rotout_l_T_36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_38 = or(_rotout_l_T_33, _rotout_l_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_39 = bits(_rotout_l_T_31, 61, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_40 = shl(_rotout_l_T_39, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_41 = xor(_rotout_l_T_31, _rotout_l_T_40) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_42 = shr(_rotout_l_T_38, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_43 = and(_rotout_l_T_42, _rotout_l_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_44 = bits(_rotout_l_T_38, 61, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_45 = shl(_rotout_l_T_44, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_46 = not(_rotout_l_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_47 = and(_rotout_l_T_45, _rotout_l_T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_48 = or(_rotout_l_T_43, _rotout_l_T_47) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_49 = bits(_rotout_l_T_41, 62, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_50 = shl(_rotout_l_T_49, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_51 = xor(_rotout_l_T_41, _rotout_l_T_50) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_52 = shr(_rotout_l_T_48, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_53 = and(_rotout_l_T_52, _rotout_l_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_54 = bits(_rotout_l_T_48, 62, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_55 = shl(_rotout_l_T_54, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_56 = not(_rotout_l_T_51) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_l_T_57 = and(_rotout_l_T_55, _rotout_l_T_56) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node rotout_l = or(_rotout_l_T_53, _rotout_l_T_57) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 160:25] node _rotout_T = bits(io.fn, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 161:25] node _rotout_T_1 = mux(_rotout_T, rotout_r, rotout_l) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 161:19] node _rotout_T_2 = bits(io.fn, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 161:61] node _rotout_T_3 = mux(_rotout_T_2, shout_l, shout_r) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 161:55] node rotout = or(_rotout_T_1, _rotout_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 161:50] node _out_T = eq(UInt<1>(0h0), io.fn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 163:47] node _out_T_1 = mux(_out_T, io.adder_out, shift_logic) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 163:47] node _out_T_2 = eq(UInt<4>(0ha), io.fn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 163:47] node out = mux(_out_T_2, io.adder_out, _out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 163:47] connect io.out, out @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 177:10] node _T_1 = eq(io.dw, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 180:17] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 180:28] node _io_out_T = bits(out, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 180:56] node _io_out_T_1 = mux(_io_out_T, UInt<32>(0hffffffff), UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 180:48] node _io_out_T_2 = bits(out, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 180:66] node _io_out_T_3 = cat(_io_out_T_1, _io_out_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 180:43] connect io.out, _io_out_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/ALU.scala 180:37] module MulDiv : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 40:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 40:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 40:7] output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { fn : UInt<5>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}}, flip kill : UInt<1>, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, full_data : UInt<128>, tag : UInt<5>}}} @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 45:14] regreset state : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 51:22] reg req : { fn : UInt<5>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 53:16] reg count : UInt<7>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 54:18] reg neg_out : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 57:20] reg isHi : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 58:17] reg resHi : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 59:18] reg divisor : UInt<65>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 60:20] reg remainder : UInt<130>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 61:22] wire decoded_plaInput : UInt<3> @[src/main/scala/chisel3/util/pla.scala 77:22] node decoded_invInputs = not(decoded_plaInput) @[src/main/scala/chisel3/util/pla.scala 78:21] wire decoded : UInt<4> @[src/main/scala/chisel3/util/pla.scala 81:23] node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_3_2 = andr(decoded_andMatrixOutputs_andMatrixInput_0) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_4_2 = andr(decoded_andMatrixOutputs_andMatrixInput_0_1) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_1) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node decoded_andMatrixOutputs_1_2 = andr(decoded_andMatrixOutputs_andMatrixInput_0_4) @[src/main/scala/chisel3/util/pla.scala 98:70] node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_invInputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 91:29] node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_2) @[src/main/scala/chisel3/util/pla.scala 98:70] node _decoded_orMatrixOutputs_T = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_5_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_orMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_orMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _decoded_orMatrixOutputs_T_5 = orr(_decoded_orMatrixOutputs_T_4) @[src/main/scala/chisel3/util/pla.scala 114:36] node _decoded_orMatrixOutputs_T_6 = orr(decoded_andMatrixOutputs_4_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node decoded_orMatrixOutputs_lo = cat(_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_1) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_orMatrixOutputs_hi = cat(_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5) @[src/main/scala/chisel3/util/pla.scala 102:36] node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) @[src/main/scala/chisel3/util/pla.scala 102:36] node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 124:31] node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 124:31] node decoded_invMatrixOutputs_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_invMatrixOutputs_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) @[src/main/scala/chisel3/util/pla.scala 120:37] node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] connect decoded, decoded_invMatrixOutputs @[src/main/scala/chisel3/util/pla.scala 129:13] connect decoded_plaInput, io.req.bits.fn @[src/main/scala/chisel3/util/experimental/decode/decoder.scala 35:16] node _T = bits(decoded, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_1 = bits(decoded, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_2 = bits(decoded, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node _T_3 = bits(decoded, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node cmdMul = bits(_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 75:107] node cmdHi = bits(_T_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 75:107] node lhsSigned = bits(_T_2, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 75:107] node rhsSigned = bits(_T_3, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 75:107] node _T_4 = eq(io.req.bits.dw, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 78:60] node _T_5 = and(UInt<1>(0h1), _T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 78:50] node _sign_T = bits(io.req.bits.in1, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 81:38] node _sign_T_1 = bits(io.req.bits.in1, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 81:48] node _sign_T_2 = mux(_T_5, _sign_T, _sign_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 81:29] node lhs_sign = and(lhsSigned, _sign_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 81:23] node _hi_T = mux(lhs_sign, UInt<32>(0hffffffff), UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 82:29] node _hi_T_1 = bits(io.req.bits.in1, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 82:43] node hi = mux(_T_5, _hi_T, _hi_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 82:17] node _T_6 = bits(io.req.bits.in1, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 83:15] node lhs_in = cat(hi, _T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 83:9] node _T_7 = eq(io.req.bits.dw, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 78:60] node _T_8 = and(UInt<1>(0h1), _T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 78:50] node _sign_T_3 = bits(io.req.bits.in2, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 81:38] node _sign_T_4 = bits(io.req.bits.in2, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 81:48] node _sign_T_5 = mux(_T_8, _sign_T_3, _sign_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 81:29] node rhs_sign = and(rhsSigned, _sign_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 81:23] node _hi_T_2 = mux(rhs_sign, UInt<32>(0hffffffff), UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 82:29] node _hi_T_3 = bits(io.req.bits.in2, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 82:43] node hi_1 = mux(_T_8, _hi_T_2, _hi_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 82:17] node _T_9 = bits(io.req.bits.in2, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 83:15] node rhs_in = cat(hi_1, _T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 83:9] node _subtractor_T = bits(remainder, 128, 64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 88:29] node _subtractor_T_1 = sub(_subtractor_T, divisor) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 88:37] node subtractor = tail(_subtractor_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 88:37] node _result_T = bits(remainder, 128, 65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 89:36] node _result_T_1 = bits(remainder, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 89:57] node result = mux(resHi, _result_T, _result_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 89:19] node _negated_remainder_T = sub(UInt<1>(0h0), result) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 90:27] node negated_remainder = tail(_negated_remainder_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 90:27] node _T_10 = eq(state, UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 92:39] when _T_10 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 92:57] node _T_11 = bits(remainder, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 93:20] when _T_11 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 93:27] connect remainder, negated_remainder @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 94:17] node _T_12 = bits(divisor, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 96:18] when _T_12 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 96:25] connect divisor, subtractor @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 97:15] connect state, UInt<3>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 99:11] node _T_13 = eq(state, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 101:39] when _T_13 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 101:57] connect remainder, negated_remainder @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 102:15] connect state, UInt<3>(0h7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 103:11] connect resHi, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 104:11] node _T_14 = eq(state, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 106:39] when _T_14 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 106:50] node _mulReg_T = bits(remainder, 129, 65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 107:31] node _mulReg_T_1 = bits(remainder, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 107:55] node mulReg = cat(_mulReg_T, _mulReg_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 107:21] node mplierSign = bits(remainder, 64, 64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 108:31] node mplier = bits(mulReg, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 109:24] node _accum_T = bits(mulReg, 128, 64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 110:23] node accum = asSInt(_accum_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 110:37] node mpcand = asSInt(divisor) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 111:26] node _prod_T = bits(mplier, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 112:38] node _prod_T_1 = cat(mplierSign, _prod_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 112:19] node _prod_T_2 = asSInt(_prod_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 112:60] node _prod_T_3 = mul(_prod_T_2, mpcand) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 112:67] node _prod_T_4 = add(_prod_T_3, accum) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 112:76] node _prod_T_5 = tail(_prod_T_4, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 112:76] node prod = asSInt(_prod_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 112:76] node _nextMulReg_T = bits(mplier, 63, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 113:38] node nextMulReg_hi = asUInt(prod) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 113:25] node nextMulReg = cat(nextMulReg_hi, _nextMulReg_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 113:25] node _nextMplierSign_T = eq(count, UInt<6>(0h3e)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 114:32] node nextMplierSign = and(_nextMplierSign_T, neg_out) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 114:61] node _eOutMask_T = mul(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 116:54] node _eOutMask_T_1 = bits(_eOutMask_T, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 116:72] node _eOutMask_T_2 = dshr(asSInt(UInt<65>(0h10000000000000000)), _eOutMask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 116:44] node eOutMask = bits(_eOutMask_T_2, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 116:91] node _eOut_T = neq(count, UInt<6>(0h3f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 117:45] node _eOut_T_1 = and(UInt<1>(0h0), _eOut_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 117:36] node _eOut_T_2 = neq(count, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 117:83] node _eOut_T_3 = and(_eOut_T_1, _eOut_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 117:74] node _eOut_T_4 = eq(isHi, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 118:7] node _eOut_T_5 = and(_eOut_T_3, _eOut_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 117:91] node _eOut_T_6 = not(eOutMask) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 118:26] node _eOut_T_7 = and(mplier, _eOut_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 118:24] node _eOut_T_8 = eq(_eOut_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 118:37] node eOut = and(_eOut_T_5, _eOut_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 118:13] node _eOutRes_T = mul(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 119:46] node _eOutRes_T_1 = sub(UInt<7>(0h40), _eOutRes_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 119:38] node _eOutRes_T_2 = tail(_eOutRes_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 119:38] node _eOutRes_T_3 = bits(_eOutRes_T_2, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 119:64] node eOutRes = dshr(mulReg, _eOutRes_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 119:27] node _nextMulReg1_T = bits(nextMulReg, 128, 64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 120:37] node _nextMulReg1_T_1 = mux(eOut, eOutRes, nextMulReg) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 120:55] node _nextMulReg1_T_2 = bits(_nextMulReg1_T_1, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 120:82] node nextMulReg1 = cat(_nextMulReg1_T, _nextMulReg1_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 120:26] node _remainder_T = shr(nextMulReg1, 64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 121:34] node _remainder_T_1 = bits(nextMulReg1, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 121:67] node remainder_hi = cat(_remainder_T, nextMplierSign) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 121:21] node _remainder_T_2 = cat(remainder_hi, _remainder_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 121:21] connect remainder, _remainder_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 121:15] node _count_T = add(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 123:20] node _count_T_1 = tail(_count_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 123:20] connect count, _count_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 123:11] node _T_15 = eq(count, UInt<6>(0h3f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 124:25] node _T_16 = or(eOut, _T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 124:16] when _T_16 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 124:55] connect state, UInt<3>(0h6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 125:13] connect resHi, isHi @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 126:13] node _T_17 = eq(state, UInt<3>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 129:39] when _T_17 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 129:50] node unrolls_less = bits(subtractor, 64, 64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 133:28] node _unrolls_T = bits(remainder, 127, 64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 134:24] node _unrolls_T_1 = bits(subtractor, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 134:45] node _unrolls_T_2 = mux(unrolls_less, _unrolls_T, _unrolls_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 134:14] node _unrolls_T_3 = bits(remainder, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 134:58] node _unrolls_T_4 = eq(unrolls_less, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 134:67] node unrolls_hi = cat(_unrolls_T_2, _unrolls_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 134:10] node unrolls_0 = cat(unrolls_hi, _unrolls_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 134:10] connect remainder, unrolls_0 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 137:15] node _T_18 = eq(count, UInt<7>(0h40)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 138:17] when _T_18 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 138:42] node _state_T = mux(neg_out, UInt<3>(0h5), UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 139:19] connect state, _state_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 139:13] connect resHi, isHi @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 140:13] node _count_T_2 = add(count, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 144:20] node _count_T_3 = tail(_count_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 144:20] connect count, _count_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 144:11] node _divby0_T = eq(count, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 146:24] node _divby0_T_1 = bits(subtractor, 64, 64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 146:46] node _divby0_T_2 = eq(_divby0_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 146:35] node divby0 = and(_divby0_T, _divby0_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 146:32] node _T_19 = eq(isHi, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 159:21] node _T_20 = and(divby0, _T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 159:18] when _T_20 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 159:28] connect neg_out, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 159:38] node _T_21 = and(io.resp.ready, io.resp.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_22 = or(_T_21, io.kill) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 161:22] when _T_22 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 161:34] connect state, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 162:11] node _T_23 = and(io.req.ready, io.req.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_23 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 164:22] node _state_T_1 = or(lhs_sign, rhs_sign) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 165:46] node _state_T_2 = mux(_state_T_1, UInt<3>(0h1), UInt<3>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 165:36] node _state_T_3 = mux(cmdMul, UInt<3>(0h2), _state_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 165:17] connect state, _state_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 165:11] connect isHi, cmdHi @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 166:10] connect resHi, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 167:11] node _count_T_4 = eq(io.req.bits.dw, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 78:60] node _count_T_5 = and(UInt<1>(0h1), _count_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 78:50] node _count_T_6 = and(cmdMul, _count_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 168:46] node _count_T_7 = mux(_count_T_6, UInt<6>(0h20), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 168:38] connect count, _count_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 168:11] node _neg_out_T = neq(lhs_sign, rhs_sign) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 169:46] node _neg_out_T_1 = mux(cmdHi, lhs_sign, _neg_out_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 169:19] connect neg_out, _neg_out_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 169:13] node _divisor_T = cat(rhs_sign, rhs_in) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 170:19] connect divisor, _divisor_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 170:13] connect remainder, lhs_in @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 171:15] connect req, io.req.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 172:9] node _outMul_T = xor(UInt<3>(0h6), UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 175:37] node _outMul_T_1 = and(state, _outMul_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 175:23] node _outMul_T_2 = not(UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 175:70] node _outMul_T_3 = and(UInt<3>(0h6), _outMul_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 175:68] node outMul = eq(_outMul_T_1, _outMul_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 175:52] node _loOut_T = eq(req.dw, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 78:60] node _loOut_T_1 = and(UInt<1>(0h1), _loOut_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 78:50] node _loOut_T_2 = and(UInt<1>(0h1), _loOut_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 176:30] node _loOut_T_3 = and(_loOut_T_2, outMul) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 176:48] node _loOut_T_4 = bits(result, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 176:65] node _loOut_T_5 = bits(result, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 176:82] node loOut = mux(_loOut_T_3, _loOut_T_4, _loOut_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 176:18] node _hiOut_T = eq(req.dw, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 78:60] node _hiOut_T_1 = and(UInt<1>(0h1), _hiOut_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 78:50] node _hiOut_T_2 = bits(loOut, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 177:50] node _hiOut_T_3 = mux(_hiOut_T_2, UInt<32>(0hffffffff), UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 177:39] node _hiOut_T_4 = bits(result, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 177:66] node hiOut = mux(_hiOut_T_1, _hiOut_T_3, _hiOut_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 177:18] connect io.resp.bits.tag, req.tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 178:20] node _io_resp_bits_data_T = cat(hiOut, loOut) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 180:27] connect io.resp.bits.data, _io_resp_bits_data_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 180:21] node _io_resp_bits_full_data_T = bits(remainder, 128, 65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 181:42] node _io_resp_bits_full_data_T_1 = bits(remainder, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 181:63] node _io_resp_bits_full_data_T_2 = cat(_io_resp_bits_full_data_T, _io_resp_bits_full_data_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 181:32] connect io.resp.bits.full_data, _io_resp_bits_full_data_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 181:26] node _io_resp_valid_T = eq(state, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 182:27] node _io_resp_valid_T_1 = eq(state, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 182:51] node _io_resp_valid_T_2 = or(_io_resp_valid_T, _io_resp_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 182:42] connect io.resp.valid, _io_resp_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 182:17] node _io_req_ready_T = eq(state, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 183:25] connect io.req.ready, _io_req_ready_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/Multiplier.scala 183:16] module Arbiter3_LLWB : @[src/main/scala/chisel3/util/Arbiter.scala 133:7] input clock : Clock @[src/main/scala/chisel3/util/Arbiter.scala 133:7] input reset : Reset @[src/main/scala/chisel3/util/Arbiter.scala 133:7] output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, tag : UInt<5>}}[3], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, tag : UInt<5>}}, chosen : UInt<2>} @[src/main/scala/chisel3/util/Arbiter.scala 140:14] connect io.chosen, UInt<2>(0h2) @[src/main/scala/chisel3/util/Arbiter.scala 142:13] connect io.out.bits, io.in[2].bits @[src/main/scala/chisel3/util/Arbiter.scala 143:15] when io.in[1].valid : @[src/main/scala/chisel3/util/Arbiter.scala 145:26] connect io.chosen, UInt<1>(0h1) @[src/main/scala/chisel3/util/Arbiter.scala 146:17] connect io.out.bits, io.in[1].bits @[src/main/scala/chisel3/util/Arbiter.scala 147:19] when io.in[0].valid : @[src/main/scala/chisel3/util/Arbiter.scala 145:26] connect io.chosen, UInt<1>(0h0) @[src/main/scala/chisel3/util/Arbiter.scala 146:17] connect io.out.bits, io.in[0].bits @[src/main/scala/chisel3/util/Arbiter.scala 147:19] node _grant_T = or(io.in[0].valid, io.in[1].valid) @[src/main/scala/chisel3/util/Arbiter.scala 45:68] node grant_1 = eq(io.in[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Arbiter.scala 45:78] node grant_2 = eq(_grant_T, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Arbiter.scala 45:78] node _io_in_0_ready_T = and(UInt<1>(0h1), io.out.ready) @[src/main/scala/chisel3/util/Arbiter.scala 153:19] connect io.in[0].ready, _io_in_0_ready_T @[src/main/scala/chisel3/util/Arbiter.scala 153:14] node _io_in_1_ready_T = and(grant_1, io.out.ready) @[src/main/scala/chisel3/util/Arbiter.scala 153:19] connect io.in[1].ready, _io_in_1_ready_T @[src/main/scala/chisel3/util/Arbiter.scala 153:14] node _io_in_2_ready_T = and(grant_2, io.out.ready) @[src/main/scala/chisel3/util/Arbiter.scala 153:19] connect io.in[2].ready, _io_in_2_ready_T @[src/main/scala/chisel3/util/Arbiter.scala 153:14] node _io_out_valid_T = eq(grant_2, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Arbiter.scala 154:19] node _io_out_valid_T_1 = or(_io_out_valid_T, io.in[2].valid) @[src/main/scala/chisel3/util/Arbiter.scala 154:31] connect io.out.valid, _io_out_valid_T_1 @[src/main/scala/chisel3/util/Arbiter.scala 154:16] extmodule plusarg_reader : @[hardware/upstream/rocket-chip/src/main/scala/util/PlusArg.scala 45:7] output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "max_core_cycles=%d" parameter WIDTH = 32 module PlusArgTimeout : @[hardware/upstream/rocket-chip/src/main/scala/util/PlusArg.scala 58:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/PlusArg.scala 58:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/PlusArg.scala 58:7] output io : { flip count : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/util/PlusArg.scala 59:14] inst plusarg_reader of plusarg_reader @[hardware/upstream/rocket-chip/src/main/scala/util/PlusArg.scala 62:19] node _T = gt(plusarg_reader.out, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/PlusArg.scala 63:13] when _T : @[hardware/upstream/rocket-chip/src/main/scala/util/PlusArg.scala 63:20] node _T_1 = lt(io.count, plusarg_reader.out) @[hardware/upstream/rocket-chip/src/main/scala/util/PlusArg.scala 64:22] node _T_2 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/PlusArg.scala 64:12] node _T_3 = eq(_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/PlusArg.scala 64:12] when _T_3 : @[hardware/upstream/rocket-chip/src/main/scala/util/PlusArg.scala 64:12] node _T_4 = eq(_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/PlusArg.scala 64:12] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/PlusArg.scala 64:12] printf(clock, UInt<1>(0h1), "Assertion failed: Timeout exceeded: Kill the emulation after INT rdtime cycles. Off if 0.\n at PlusArg.scala:64 assert (io.count < max, s\"Timeout exceeded: $docstring\")\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/util/PlusArg.scala 64:12] assert(clock, _T_1, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/util/PlusArg.scala 64:12] module Rocket : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 158:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 158:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 158:7] output io : { flip hartid : UInt<1>, flip reset_vector : UInt<32>, flip interrupts : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, lip : UInt<1>[0]}, imem : { might_request : UInt<1>, flip clock_enabled : UInt<1>, req : { valid : UInt<1>, bits : { pc : UInt<34>, speculative : UInt<1>}}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<33>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<1>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<34>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, flip gpa : { valid : UInt<1>, bits : UInt<34>}, flip gpa_is_pte : UInt<1>, btb_update : { valid : UInt<1>, bits : { prediction : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<1>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<33>, target : UInt<33>, taken : UInt<1>, isValid : UInt<1>, br_pc : UInt<33>, cfiType : UInt<2>}}, bht_update : { valid : UInt<1>, bits : { prediction : { history : UInt<8>, value : UInt<1>}, pc : UInt<33>, branch : UInt<1>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : { valid : UInt<1>, bits : { cfiType : UInt<2>, returnAddr : UInt<33>}}, flush_icache : UInt<1>, flip npc : UInt<34>, flip perf : { acquire : UInt<1>, tlbMiss : UInt<1>}, progress : UInt<1>}, dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<34>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, flip ptw : { flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<52>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<33>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], perf : { l2miss : UInt<1>, l2hit : UInt<1>, pte_miss : UInt<1>, pte_hit : UInt<1>}, flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}, clock_enabled : UInt<1>}, flip fpu : { flip hartid : UInt<1>, flip time : UInt<64>, flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, flip v_sew : UInt<3>, store_data : UInt<64>, toint_data : UInt<64>, flip ll_resp_val : UInt<1>, flip ll_resp_type : UInt<3>, flip ll_resp_tag : UInt<5>, flip ll_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip keep_clock_enabled : UInt<1>}, flip rocc : { flip cmd : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { rd : UInt<5>, data : UInt<64>}}, mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<34>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, busy : UInt<1>, interrupt : UInt<1>, flip exception : UInt<1>, flip csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}, trace : { insns : { valid : UInt<1>, iaddr : UInt<34>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<34>}[1], time : UInt<64>}, bpwatch : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[1], cease : UInt<1>, wfi : UInt<1>, flip traceStall : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 138:14] regreset clock_en_reg : UInt<1>, clock, reset, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 164:29] reg long_latency_stall : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 165:31] reg id_reg_pause : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 166:25] reg imem_might_request_reg : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 167:35] wire clock_en : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 168:29] connect clock_en, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 168:29] wire _hits_WIRE : UInt<1>[18] @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE[4], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE[5], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE[6], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE[7], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE[8], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE[9], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE[10], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE[11], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE[12], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE[13], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE[14], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE[15], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE[16], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE[17], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] wire hits : UInt<1>[18] @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:25] connect hits, _hits_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:25] wire _hits_WIRE_1 : UInt<1>[11] @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE_1[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE_1[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE_1[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE_1[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE_1[4], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE_1[5], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE_1[6], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE_1[7], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE_1[8], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE_1[9], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE_1[10], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] wire hits_1 : UInt<1>[11] @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:25] connect hits_1, _hits_WIRE_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:25] wire _hits_WIRE_2 : UInt<1>[6] @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE_2[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE_2[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE_2[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE_2[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE_2[4], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] connect _hits_WIRE_2[5], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:33] wire hits_2 : UInt<1>[6] @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:25] connect hits_2, _hits_WIRE_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/Events.scala 13:25] reg ex_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 248:20] reg mem_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 249:21] reg wb_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 250:20] reg ex_reg_xcpt_interrupt : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 252:35] reg ex_reg_valid : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 253:35] reg ex_reg_rvc : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 254:35] reg ex_reg_btb_resp : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<1>, bht : { history : UInt<8>, value : UInt<1>}}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 255:35] reg ex_reg_xcpt : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 256:35] reg ex_reg_flush_pipe : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 257:35] reg ex_reg_load_use : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 258:35] reg ex_reg_cause : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 259:35] reg ex_reg_replay : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 260:26] reg ex_reg_pc : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 261:22] reg ex_reg_mem_size : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 262:28] reg ex_reg_hls : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 263:23] reg ex_reg_inst : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 264:24] reg ex_reg_raw_inst : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 265:28] reg ex_reg_wphit : UInt<1>[1], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 266:36] reg ex_reg_set_vconfig : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 267:36] reg mem_reg_xcpt_interrupt : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 269:36] reg mem_reg_valid : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 270:36] reg mem_reg_rvc : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 271:36] reg mem_reg_btb_resp : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<33>, entry : UInt<1>, bht : { history : UInt<8>, value : UInt<1>}}, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 272:36] reg mem_reg_xcpt : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 273:36] reg mem_reg_replay : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 274:36] reg mem_reg_flush_pipe : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 275:36] reg mem_reg_cause : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 276:36] reg mem_reg_slow_bypass : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 277:36] reg mem_reg_load : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 278:36] reg mem_reg_store : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 279:36] reg mem_reg_set_vconfig : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 280:36] reg mem_reg_sfence : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 281:27] reg mem_reg_pc : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 282:23] reg mem_reg_inst : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 283:25] reg mem_reg_mem_size : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 284:29] reg mem_reg_hls_or_dv : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 285:30] reg mem_reg_raw_inst : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 286:29] reg mem_reg_wdata : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 287:26] reg mem_reg_rs2 : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 288:24] reg mem_br_taken : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 289:25] wire take_pc_mem : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 290:25] reg mem_reg_wphit : UInt<1>[1], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 291:35] reg wb_reg_valid : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 293:35] reg wb_reg_xcpt : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 294:35] reg wb_reg_replay : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 295:35] reg wb_reg_flush_pipe : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 296:35] reg wb_reg_cause : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 297:35] reg wb_reg_set_vconfig : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 298:35] reg wb_reg_sfence : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 299:26] reg wb_reg_pc : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 300:22] reg wb_reg_mem_size : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 301:28] reg wb_reg_hls_or_dv : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 302:29] reg wb_reg_hfence_v : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 303:28] reg wb_reg_hfence_g : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 304:28] reg wb_reg_inst : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 305:24] reg wb_reg_raw_inst : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 306:28] reg wb_reg_wdata : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 307:25] reg wb_reg_rs2 : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 308:23] reg wb_reg_br_taken : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 309:28] wire take_pc_wb : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 310:24] reg wb_reg_wphit : UInt<1>[1], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 311:35] node take_pc_mem_wb = or(take_pc_wb, take_pc_mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 313:35] inst ibuf of IBuf @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 317:20] connect ibuf.clock, clock connect ibuf.reset, reset connect ibuf.io.imem, io.imem.resp @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 321:16] connect ibuf.io.kill, take_pc_mem_wb @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 322:16] wire id_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 327:21] wire id_ctrl_decoder_decoded_plaInput : UInt<32> @[src/main/scala/chisel3/util/pla.scala 77:22] node id_ctrl_decoder_decoded_invInputs = not(id_ctrl_decoder_decoded_plaInput) @[src/main/scala/chisel3/util/pla.scala 78:21] wire id_ctrl_decoder_decoded : UInt<42> @[src/main/scala/chisel3/util/pla.scala 81:23] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_63_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_66_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_1) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_9_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_2) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_0_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_3) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_91_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_4) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_76_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_5) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_60_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_6) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_27_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_7) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_lo_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_116_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_8) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_82_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_9) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_43_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_10) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_120_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_11) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_33_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_12) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_7_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_13) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_62_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_14) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_24_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_15) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_115_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_16) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_93_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_17) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_18_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_18) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_61_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_19) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_34_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_20) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_84_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_21) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_121_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_22) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_104_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_23) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_37_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_24) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_51_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_25) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_17_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_26) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_80_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_27) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_lo_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_40_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_28) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_64_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_29) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_21_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_30) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_59_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_31) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_38_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_32) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_14_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_33) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_118_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_34) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_92_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_35) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_36_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_36) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_119_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_37) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_56_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_38) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_15_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_39) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_83_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_40) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_112_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_41) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_75_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_42) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_12_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_43) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_89_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_44) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_35_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_45) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_99_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_46) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_117_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_47) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_96_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_48) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_3_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_49) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_103_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_50) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_31_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_51) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_97_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_52) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_102_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_53) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_48_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_54) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_85_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_55) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_114_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_56) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_19_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_57) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_5_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_58) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_54_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_59) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_47_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_60) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_58_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_61) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_42_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_62) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_78_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_63) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_55_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_64) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_72_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_65) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_108_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_66) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_95_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_67) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_106_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_68) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_4_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_69) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_13_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_70) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_71) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_110_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_71) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_109_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_72) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_49_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_73) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_53_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_74) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_94_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_75) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_76) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_28_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_76) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_77) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_8_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_77) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_68_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_78) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_79) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_44_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_79) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_74_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_80) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_81) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_88_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_81) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_45_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_82) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = bits(id_ctrl_decoder_decoded_plaInput, 20, 20) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = bits(id_ctrl_decoder_decoded_plaInput, 22, 22) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_30_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_83) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = bits(id_ctrl_decoder_decoded_plaInput, 20, 20) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = bits(id_ctrl_decoder_decoded_plaInput, 22, 22) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_67_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_84) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_85) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_41_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_85) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_86) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_6_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_86) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_87) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_86_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_87) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_88) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_70_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_88) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_89) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_32_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_89) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_1_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_90) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_52_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_91) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_92) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_10_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_92) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_93) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_57_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_93) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = bits(id_ctrl_decoder_decoded_plaInput, 21, 21) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_94) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_20_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_94) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = bits(id_ctrl_decoder_decoded_plaInput, 21, 21) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_100_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_95) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_96) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_22_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_96) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_39_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_97) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_98) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_113_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_98) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_16_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_99) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_100) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_90_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_100) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = bits(id_ctrl_decoder_decoded_plaInput, 20, 20) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_111_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_101) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = bits(id_ctrl_decoder_decoded_plaInput, 20, 20) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_23_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_102) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_73_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_103) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_11_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_104) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_105) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_87_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_105) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_81_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_106) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = bits(id_ctrl_decoder_decoded_plaInput, 21, 21) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = bits(id_ctrl_decoder_decoded_plaInput, 24, 24) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_107) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_2_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_107) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = bits(id_ctrl_decoder_decoded_plaInput, 21, 21) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = bits(id_ctrl_decoder_decoded_plaInput, 24, 24) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_108) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_79_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_108) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_107_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_109) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_110) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_105_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_110) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_111) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_98_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_111) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_112) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_25_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_112) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_113) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_71_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_113) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_114) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_65_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_114) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_115) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_77_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_115) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_116) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_101_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_116) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_117) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_69_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_117) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_118) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_26_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_118) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_119) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_50_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_119) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_120) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_29_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_120) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 91:29] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) @[src/main/scala/chisel3/util/pla.scala 90:45] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_lo_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_hi_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118) @[src/main/scala/chisel3/util/pla.scala 98:53] node _id_ctrl_decoder_decoded_andMatrixOutputs_T_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_121) @[src/main/scala/chisel3/util/pla.scala 98:53] node id_ctrl_decoder_decoded_andMatrixOutputs_46_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_121) @[src/main/scala/chisel3/util/pla.scala 98:70] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_77_2, id_ctrl_decoder_decoded_andMatrixOutputs_50_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_29_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_73_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_81_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_52_2, id_ctrl_decoder_decoded_andMatrixOutputs_10_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_57_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_49_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_53_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_1 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_12_2, id_ctrl_decoder_decoded_andMatrixOutputs_74_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_88_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_3 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_4 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_76_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_5 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_17_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_6 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_118_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_7 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_99_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_20_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_2_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_37_2, id_ctrl_decoder_decoded_andMatrixOutputs_118_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_99_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_1) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_9 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_8) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_65_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_26_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_74_2, id_ctrl_decoder_decoded_andMatrixOutputs_88_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_105_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_114_2, id_ctrl_decoder_decoded_andMatrixOutputs_54_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_8_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_48_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_15_2, id_ctrl_decoder_decoded_andMatrixOutputs_12_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_80_2, id_ctrl_decoder_decoded_andMatrixOutputs_64_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_118_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_62_2, id_ctrl_decoder_decoded_andMatrixOutputs_121_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_104_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_27_2, id_ctrl_decoder_decoded_andMatrixOutputs_120_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_7_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_91_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_63_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_11 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_10) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_110_2, id_ctrl_decoder_decoded_andMatrixOutputs_109_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_8_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_13 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_12) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_101_2, id_ctrl_decoder_decoded_andMatrixOutputs_46_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_11_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_87_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_70_2, id_ctrl_decoder_decoded_andMatrixOutputs_32_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_115_2, id_ctrl_decoder_decoded_andMatrixOutputs_18_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_56_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_3) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_15 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_14) @[src/main/scala/chisel3/util/pla.scala 114:36] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_16 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_115_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_86_2, id_ctrl_decoder_decoded_andMatrixOutputs_70_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_87_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_75_2, id_ctrl_decoder_decoded_andMatrixOutputs_6_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_115_2, id_ctrl_decoder_decoded_andMatrixOutputs_18_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_4) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_18 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_17) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_65_2, id_ctrl_decoder_decoded_andMatrixOutputs_26_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_111_2, id_ctrl_decoder_decoded_andMatrixOutputs_73_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_87_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_86_2, id_ctrl_decoder_decoded_andMatrixOutputs_70_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_115_2, id_ctrl_decoder_decoded_andMatrixOutputs_18_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_6_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_5) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_20 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_19) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_41_2, id_ctrl_decoder_decoded_andMatrixOutputs_1_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_82_2, id_ctrl_decoder_decoded_andMatrixOutputs_112_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_21 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_6) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_22 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_21) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_88_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_23 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_39_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_24 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_23) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_74_2, id_ctrl_decoder_decoded_andMatrixOutputs_88_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_25 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_107_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_26 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_25) @[src/main/scala/chisel3/util/pla.scala 114:36] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_27 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_12_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_12_2, id_ctrl_decoder_decoded_andMatrixOutputs_74_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_45_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_92_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_66_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_28 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_7) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_29 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_28) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_94_2, id_ctrl_decoder_decoded_andMatrixOutputs_68_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_58_2, id_ctrl_decoder_decoded_andMatrixOutputs_78_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_13_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_48_2, id_ctrl_decoder_decoded_andMatrixOutputs_114_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_54_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_80_2, id_ctrl_decoder_decoded_andMatrixOutputs_64_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_38_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_30 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_8) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_31 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_30) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_113_2, id_ctrl_decoder_decoded_andMatrixOutputs_16_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_90_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_44_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_22_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_72_2, id_ctrl_decoder_decoded_andMatrixOutputs_108_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_106_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_34_2, id_ctrl_decoder_decoded_andMatrixOutputs_3_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_103_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_32 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_9) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_33 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_32) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_5_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_102_2, id_ctrl_decoder_decoded_andMatrixOutputs_85_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_31_2, id_ctrl_decoder_decoded_andMatrixOutputs_97_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_15_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_34 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_10) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_35 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_34) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_113_2, id_ctrl_decoder_decoded_andMatrixOutputs_16_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_90_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_102_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_35_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_36 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_11) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_37 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_36) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_74_2, id_ctrl_decoder_decoded_andMatrixOutputs_88_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_48_2, id_ctrl_decoder_decoded_andMatrixOutputs_47_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_102_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_92_2, id_ctrl_decoder_decoded_andMatrixOutputs_15_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_12_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_80_2, id_ctrl_decoder_decoded_andMatrixOutputs_59_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_84_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_104_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_27_2, id_ctrl_decoder_decoded_andMatrixOutputs_33_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_63_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_0_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_38 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_12) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_39 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_38) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_95_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_61_2, id_ctrl_decoder_decoded_andMatrixOutputs_104_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_40 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_13) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_41 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_40) @[src/main/scala/chisel3/util/pla.scala 114:36] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_27_2, id_ctrl_decoder_decoded_andMatrixOutputs_104_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_43 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_42) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_19_2, id_ctrl_decoder_decoded_andMatrixOutputs_55_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_4_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_36_2, id_ctrl_decoder_decoded_andMatrixOutputs_15_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_48_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_40_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_21_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_63_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_60_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_44 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_14) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_45 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_44) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_88_2, id_ctrl_decoder_decoded_andMatrixOutputs_101_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_46_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_54_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_74_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_102_2, id_ctrl_decoder_decoded_andMatrixOutputs_48_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_114_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_15_2, id_ctrl_decoder_decoded_andMatrixOutputs_12_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_117_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_64_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_92_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_62_2, id_ctrl_decoder_decoded_andMatrixOutputs_84_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_80_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_120_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_7_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_63_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_46 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_15) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_47 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_46) @[src/main/scala/chisel3/util/pla.scala 114:36] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_116_2, id_ctrl_decoder_decoded_andMatrixOutputs_104_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_49 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_48) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_19_2, id_ctrl_decoder_decoded_andMatrixOutputs_55_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_4_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_15_2, id_ctrl_decoder_decoded_andMatrixOutputs_48_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_21_2, id_ctrl_decoder_decoded_andMatrixOutputs_92_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_104_2, id_ctrl_decoder_decoded_andMatrixOutputs_40_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_27_2, id_ctrl_decoder_decoded_andMatrixOutputs_121_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_63_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_20 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_50 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_16) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_51 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_50) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_95_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_114_2, id_ctrl_decoder_decoded_andMatrixOutputs_54_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_15_2, id_ctrl_decoder_decoded_andMatrixOutputs_48_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_80_2, id_ctrl_decoder_decoded_andMatrixOutputs_64_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_92_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_61_2, id_ctrl_decoder_decoded_andMatrixOutputs_84_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_120_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_62_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_27_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_63_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_0_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_21 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_52 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_17) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_53 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_52) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_88_2, id_ctrl_decoder_decoded_andMatrixOutputs_101_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_46_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_54_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_74_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_102_2, id_ctrl_decoder_decoded_andMatrixOutputs_48_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_114_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_15_2, id_ctrl_decoder_decoded_andMatrixOutputs_12_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_117_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_64_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_92_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_62_2, id_ctrl_decoder_decoded_andMatrixOutputs_84_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_80_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_120_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_63_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_0_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_22 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_54 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_18) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_55 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_54) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_74_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_88_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_12_2, id_ctrl_decoder_decoded_andMatrixOutputs_102_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_54_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_62_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_24_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_82_2, id_ctrl_decoder_decoded_andMatrixOutputs_43_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_120_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_23 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_56 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_lo_19) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_57 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_56) @[src/main/scala/chisel3/util/pla.scala 114:36] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_58 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_121_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_59 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_104_2) @[src/main/scala/chisel3/util/pla.scala 114:36] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_61_2, id_ctrl_decoder_decoded_andMatrixOutputs_102_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_61 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_60) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_71_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_111_2, id_ctrl_decoder_decoded_andMatrixOutputs_73_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_87_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_20 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_86_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_70_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_115_2, id_ctrl_decoder_decoded_andMatrixOutputs_18_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_119_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_24 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_62 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_24, id_ctrl_decoder_decoded_orMatrixOutputs_lo_20) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_63 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_62) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_26_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_87_2, id_ctrl_decoder_decoded_andMatrixOutputs_79_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_71_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_111_2, id_ctrl_decoder_decoded_andMatrixOutputs_73_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_86_2, id_ctrl_decoder_decoded_andMatrixOutputs_70_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_100_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_67_2, id_ctrl_decoder_decoded_andMatrixOutputs_6_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_74_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_45_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_114_2, id_ctrl_decoder_decoded_andMatrixOutputs_54_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_102_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_48_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_21 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_15_2, id_ctrl_decoder_decoded_andMatrixOutputs_12_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_64_2, id_ctrl_decoder_decoded_andMatrixOutputs_59_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_92_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_51_2, id_ctrl_decoder_decoded_andMatrixOutputs_80_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_18_2, id_ctrl_decoder_decoded_andMatrixOutputs_84_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_104_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_62_2, id_ctrl_decoder_decoded_andMatrixOutputs_93_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_27_2, id_ctrl_decoder_decoded_andMatrixOutputs_120_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_7_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_76_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_63_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_0_2) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6) @[src/main/scala/chisel3/util/pla.scala 114:19] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_25 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_64 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_25, id_ctrl_decoder_decoded_orMatrixOutputs_lo_21) @[src/main/scala/chisel3/util/pla.scala 114:19] node _id_ctrl_decoder_decoded_orMatrixOutputs_T_65 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_64) @[src/main/scala/chisel3/util/pla.scala 114:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_3, _id_ctrl_decoder_decoded_orMatrixOutputs_T_1) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_5) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, _id_ctrl_decoder_decoded_orMatrixOutputs_T_4) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_9, _id_ctrl_decoder_decoded_orMatrixOutputs_T_7) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = cat(UInt<1>(0h0), _id_ctrl_decoder_decoded_orMatrixOutputs_T_13) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, _id_ctrl_decoder_decoded_orMatrixOutputs_T_11) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_16, _id_ctrl_decoder_decoded_orMatrixOutputs_T_15) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_22, _id_ctrl_decoder_decoded_orMatrixOutputs_T_20) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, _id_ctrl_decoder_decoded_orMatrixOutputs_T_18) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_27, _id_ctrl_decoder_decoded_orMatrixOutputs_T_26) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, _id_ctrl_decoder_decoded_orMatrixOutputs_T_24) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_31, _id_ctrl_decoder_decoded_orMatrixOutputs_T_29) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, UInt<1>(0h0)) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_lo_22 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_35, _id_ctrl_decoder_decoded_orMatrixOutputs_T_33) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_39, UInt<1>(0h0)) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, _id_ctrl_decoder_decoded_orMatrixOutputs_T_37) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_43, _id_ctrl_decoder_decoded_orMatrixOutputs_T_41) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_49, _id_ctrl_decoder_decoded_orMatrixOutputs_T_47) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, _id_ctrl_decoder_decoded_orMatrixOutputs_T_45) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_53, _id_ctrl_decoder_decoded_orMatrixOutputs_T_51) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_57, _id_ctrl_decoder_decoded_orMatrixOutputs_T_55) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, UInt<1>(0h0)) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_61, _id_ctrl_decoder_decoded_orMatrixOutputs_T_59) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, _id_ctrl_decoder_decoded_orMatrixOutputs_T_58) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_65, _id_ctrl_decoder_decoded_orMatrixOutputs_T_63) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, UInt<1>(0h0)) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs_hi_26 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19) @[src/main/scala/chisel3/util/pla.scala 102:36] node id_ctrl_decoder_decoded_orMatrixOutputs = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_26, id_ctrl_decoder_decoded_orMatrixOutputs_lo_22) @[src/main/scala/chisel3/util/pla.scala 102:36] node _id_ctrl_decoder_decoded_invMatrixOutputs_T = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 0, 0) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_1 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 1, 1) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_2 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 2, 2) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_3 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 3, 3) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_4 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 4, 4) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_5 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 5, 5) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_6 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 6, 6) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_7 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 7, 7) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_8 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 8, 8) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_9 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 9, 9) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_10 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 10, 10) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_11 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 11, 11) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_12 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 12, 12) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_13 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 13, 13) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_14 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 14, 14) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_15 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 15, 15) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_16 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 16, 16) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_17 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 17, 17) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_18 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 18, 18) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_19 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 19, 19) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_20 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 20, 20) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_21 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 21, 21) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_22 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 22, 22) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_23 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 23, 23) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_24 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 24, 24) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_25 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 25, 25) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_26 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 26, 26) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_27 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 27, 27) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_28 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 28, 28) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_29 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 29, 29) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_30 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 30, 30) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_31 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 31, 31) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_32 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 32, 32) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_33 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 33, 33) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_34 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 34, 34) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_35 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 35, 35) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_36 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 36, 36) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_37 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 37, 37) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_38 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 38, 38) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_39 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 39, 39) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_40 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 40, 40) @[src/main/scala/chisel3/util/pla.scala 124:31] node _id_ctrl_decoder_decoded_invMatrixOutputs_T_41 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 41, 41) @[src/main/scala/chisel3/util/pla.scala 124:31] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_1, _id_ctrl_decoder_decoded_invMatrixOutputs_T) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_4, _id_ctrl_decoder_decoded_invMatrixOutputs_T_3) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_2) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_6, _id_ctrl_decoder_decoded_invMatrixOutputs_T_5) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_9, _id_ctrl_decoder_decoded_invMatrixOutputs_T_8) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_7) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_11, _id_ctrl_decoder_decoded_invMatrixOutputs_T_10) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_14, _id_ctrl_decoder_decoded_invMatrixOutputs_T_13) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_12) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_17, _id_ctrl_decoder_decoded_invMatrixOutputs_T_16) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_15) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_20, _id_ctrl_decoder_decoded_invMatrixOutputs_T_19) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_18) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_22, _id_ctrl_decoder_decoded_invMatrixOutputs_T_21) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_25, _id_ctrl_decoder_decoded_invMatrixOutputs_T_24) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_23) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_27, _id_ctrl_decoder_decoded_invMatrixOutputs_T_26) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_30, _id_ctrl_decoder_decoded_invMatrixOutputs_T_29) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_28) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_32, _id_ctrl_decoder_decoded_invMatrixOutputs_T_31) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_35, _id_ctrl_decoder_decoded_invMatrixOutputs_T_34) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_33) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_38, _id_ctrl_decoder_decoded_invMatrixOutputs_T_37) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_36) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_41, _id_ctrl_decoder_decoded_invMatrixOutputs_T_40) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_39) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] node id_ctrl_decoder_decoded_invMatrixOutputs = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo) @[src/main/scala/chisel3/util/pla.scala 120:37] connect id_ctrl_decoder_decoded, id_ctrl_decoder_decoded_invMatrixOutputs @[src/main/scala/chisel3/util/pla.scala 129:13] connect id_ctrl_decoder_decoded_plaInput, ibuf.io.inst[0].bits.inst.bits @[src/main/scala/chisel3/util/experimental/decode/decoder.scala 35:16] node id_ctrl_decoder_0 = bits(id_ctrl_decoder_decoded, 41, 41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_1 = bits(id_ctrl_decoder_decoded, 40, 40) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_2 = bits(id_ctrl_decoder_decoded, 39, 39) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_3 = bits(id_ctrl_decoder_decoded, 38, 38) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_4 = bits(id_ctrl_decoder_decoded, 37, 37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_5 = bits(id_ctrl_decoder_decoded, 36, 36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_6 = bits(id_ctrl_decoder_decoded, 35, 35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_7 = bits(id_ctrl_decoder_decoded, 34, 34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_8 = bits(id_ctrl_decoder_decoded, 33, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_9 = bits(id_ctrl_decoder_decoded, 30, 29) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_10 = bits(id_ctrl_decoder_decoded, 28, 26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_11 = bits(id_ctrl_decoder_decoded, 25, 25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_12 = bits(id_ctrl_decoder_decoded, 24, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_13 = bits(id_ctrl_decoder_decoded, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_14 = bits(id_ctrl_decoder_decoded, 18, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_15 = bits(id_ctrl_decoder_decoded, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_16 = bits(id_ctrl_decoder_decoded, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_17 = bits(id_ctrl_decoder_decoded, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_18 = bits(id_ctrl_decoder_decoded, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_19 = bits(id_ctrl_decoder_decoded, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_20 = bits(id_ctrl_decoder_decoded, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_21 = bits(id_ctrl_decoder_decoded, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_22 = bits(id_ctrl_decoder_decoded, 6, 4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_23 = bits(id_ctrl_decoder_decoded, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_24 = bits(id_ctrl_decoder_decoded, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_25 = bits(id_ctrl_decoder_decoded, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] node id_ctrl_decoder_26 = bits(id_ctrl_decoder_decoded, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Decode.scala 50:77] connect id_ctrl.legal, id_ctrl_decoder_0 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.fp, id_ctrl_decoder_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.rocc, id_ctrl_decoder_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.branch, id_ctrl_decoder_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.jal, id_ctrl_decoder_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.jalr, id_ctrl_decoder_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.rxs2, id_ctrl_decoder_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.rxs1, id_ctrl_decoder_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.sel_alu2, id_ctrl_decoder_8 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.sel_alu1, id_ctrl_decoder_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.sel_imm, id_ctrl_decoder_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.alu_dw, id_ctrl_decoder_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.alu_fn, id_ctrl_decoder_12 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.mem, id_ctrl_decoder_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.mem_cmd, id_ctrl_decoder_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.rfs1, id_ctrl_decoder_15 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.rfs2, id_ctrl_decoder_16 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.rfs3, id_ctrl_decoder_17 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.wfd, id_ctrl_decoder_18 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.mul, id_ctrl_decoder_19 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.div, id_ctrl_decoder_20 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.wxd, id_ctrl_decoder_21 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.csr, id_ctrl_decoder_22 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.fence_i, id_ctrl_decoder_23 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.fence, id_ctrl_decoder_24 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.amo, id_ctrl_decoder_25 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] connect id_ctrl.dp, id_ctrl_decoder_26 @[hardware/upstream/rocket-chip/src/main/scala/rocket/IDecode.scala 66:42] node id_raddr3 = bits(ibuf.io.inst[0].bits.inst.rs3, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 332:72] node id_raddr2 = bits(ibuf.io.inst[0].bits.inst.rs2, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 332:72] node id_raddr1 = bits(ibuf.io.inst[0].bits.inst.rs1, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 332:72] node id_waddr = bits(ibuf.io.inst[0].bits.inst.rd, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 332:72] wire id_load_use : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 338:25] regreset id_reg_fence : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 339:29] cmem rf : UInt<64> [31] @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1350:15] wire id_rs_0 : UInt @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1356:26] node _id_rs_T = eq(id_raddr1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1357:41] node _id_rs_T_1 = and(UInt<1>(0h0), _id_rs_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1357:33] node _id_rs_T_2 = bits(id_raddr1, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1351:44] node _id_rs_T_3 = not(_id_rs_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1351:39] infer mport id_rs_MPORT = rf[_id_rs_T_3], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1351:38] node _id_rs_T_4 = mux(_id_rs_T_1, UInt<1>(0h0), id_rs_MPORT) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1357:25] connect id_rs_0, _id_rs_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1357:19] wire id_rs_1 : UInt @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1356:26] node _id_rs_T_5 = eq(id_raddr2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1357:41] node _id_rs_T_6 = and(UInt<1>(0h0), _id_rs_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1357:33] node _id_rs_T_7 = bits(id_raddr2, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1351:44] node _id_rs_T_8 = not(_id_rs_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1351:39] infer mport id_rs_MPORT_1 = rf[_id_rs_T_8], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1351:38] node _id_rs_T_9 = mux(_id_rs_T_6, UInt<1>(0h0), id_rs_MPORT_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1357:25] connect id_rs_1, _id_rs_T_9 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1357:19] wire ctrl_killd : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 344:24] node _id_npc_T = asSInt(ibuf.io.pc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 345:28] node _id_npc_sign_T = eq(UInt<3>(0h3), UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1372:24] node _id_npc_sign_T_1 = bits(ibuf.io.inst[0].bits.inst.bits, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1372:44] node _id_npc_sign_T_2 = asSInt(_id_npc_sign_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1372:49] node id_npc_sign = mux(_id_npc_sign_T, asSInt(UInt<1>(0h0)), _id_npc_sign_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1372:19] node _id_npc_b30_20_T = eq(UInt<3>(0h3), UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1373:26] node _id_npc_b30_20_T_1 = bits(ibuf.io.inst[0].bits.inst.bits, 30, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1373:41] node _id_npc_b30_20_T_2 = asSInt(_id_npc_b30_20_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1373:49] node id_npc_b30_20 = mux(_id_npc_b30_20_T, _id_npc_b30_20_T_2, id_npc_sign) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1373:21] node _id_npc_b19_12_T = neq(UInt<3>(0h3), UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:26] node _id_npc_b19_12_T_1 = neq(UInt<3>(0h3), UInt<3>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:43] node _id_npc_b19_12_T_2 = and(_id_npc_b19_12_T, _id_npc_b19_12_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:36] node _id_npc_b19_12_T_3 = bits(ibuf.io.inst[0].bits.inst.bits, 19, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:65] node _id_npc_b19_12_T_4 = asSInt(_id_npc_b19_12_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:73] node id_npc_b19_12 = mux(_id_npc_b19_12_T_2, id_npc_sign, _id_npc_b19_12_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:21] node _id_npc_b11_T = eq(UInt<3>(0h3), UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1375:23] node _id_npc_b11_T_1 = eq(UInt<3>(0h3), UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1375:40] node _id_npc_b11_T_2 = or(_id_npc_b11_T, _id_npc_b11_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1375:33] node _id_npc_b11_T_3 = eq(UInt<3>(0h3), UInt<3>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1376:23] node _id_npc_b11_T_4 = bits(ibuf.io.inst[0].bits.inst.bits, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1376:39] node _id_npc_b11_T_5 = asSInt(_id_npc_b11_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1376:44] node _id_npc_b11_T_6 = eq(UInt<3>(0h3), UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1377:23] node _id_npc_b11_T_7 = bits(ibuf.io.inst[0].bits.inst.bits, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1377:39] node _id_npc_b11_T_8 = asSInt(_id_npc_b11_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1377:43] node _id_npc_b11_T_9 = mux(_id_npc_b11_T_6, _id_npc_b11_T_8, id_npc_sign) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1377:18] node _id_npc_b11_T_10 = mux(_id_npc_b11_T_3, _id_npc_b11_T_5, _id_npc_b11_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1376:18] node id_npc_b11 = mux(_id_npc_b11_T_2, asSInt(UInt<1>(0h0)), _id_npc_b11_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1375:18] node _id_npc_b10_5_T = eq(UInt<3>(0h3), UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:25] node _id_npc_b10_5_T_1 = eq(UInt<3>(0h3), UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:42] node _id_npc_b10_5_T_2 = or(_id_npc_b10_5_T, _id_npc_b10_5_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:35] node _id_npc_b10_5_T_3 = bits(ibuf.io.inst[0].bits.inst.bits, 30, 25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:62] node id_npc_b10_5 = mux(_id_npc_b10_5_T_2, UInt<1>(0h0), _id_npc_b10_5_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:20] node _id_npc_b4_1_T = eq(UInt<3>(0h3), UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1379:24] node _id_npc_b4_1_T_1 = eq(UInt<3>(0h3), UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:24] node _id_npc_b4_1_T_2 = eq(UInt<3>(0h3), UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:41] node _id_npc_b4_1_T_3 = or(_id_npc_b4_1_T_1, _id_npc_b4_1_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:34] node _id_npc_b4_1_T_4 = bits(ibuf.io.inst[0].bits.inst.bits, 11, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:57] node _id_npc_b4_1_T_5 = eq(UInt<3>(0h3), UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1381:24] node _id_npc_b4_1_T_6 = bits(ibuf.io.inst[0].bits.inst.bits, 19, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1381:39] node _id_npc_b4_1_T_7 = bits(ibuf.io.inst[0].bits.inst.bits, 24, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1381:52] node _id_npc_b4_1_T_8 = mux(_id_npc_b4_1_T_5, _id_npc_b4_1_T_6, _id_npc_b4_1_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1381:19] node _id_npc_b4_1_T_9 = mux(_id_npc_b4_1_T_3, _id_npc_b4_1_T_4, _id_npc_b4_1_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:19] node id_npc_b4_1 = mux(_id_npc_b4_1_T, UInt<1>(0h0), _id_npc_b4_1_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1379:19] node _id_npc_b0_T = eq(UInt<3>(0h3), UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1382:22] node _id_npc_b0_T_1 = bits(ibuf.io.inst[0].bits.inst.bits, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1382:37] node _id_npc_b0_T_2 = eq(UInt<3>(0h3), UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1383:22] node _id_npc_b0_T_3 = bits(ibuf.io.inst[0].bits.inst.bits, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1383:37] node _id_npc_b0_T_4 = eq(UInt<3>(0h3), UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1384:22] node _id_npc_b0_T_5 = bits(ibuf.io.inst[0].bits.inst.bits, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1384:37] node _id_npc_b0_T_6 = mux(_id_npc_b0_T_4, _id_npc_b0_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1384:17] node _id_npc_b0_T_7 = mux(_id_npc_b0_T_2, _id_npc_b0_T_3, _id_npc_b0_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1383:17] node id_npc_b0 = mux(_id_npc_b0_T, _id_npc_b0_T_1, _id_npc_b0_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1382:17] node id_npc_lo_hi = cat(id_npc_b10_5, id_npc_b4_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node id_npc_lo = cat(id_npc_lo_hi, id_npc_b0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node id_npc_hi_lo_lo = asUInt(id_npc_b11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node id_npc_hi_lo_hi = asUInt(id_npc_b19_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node id_npc_hi_lo = cat(id_npc_hi_lo_hi, id_npc_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node id_npc_hi_hi_lo = asUInt(id_npc_b30_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node id_npc_hi_hi_hi = asUInt(id_npc_sign) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node id_npc_hi_hi = cat(id_npc_hi_hi_hi, id_npc_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node id_npc_hi = cat(id_npc_hi_hi, id_npc_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node _id_npc_T_1 = cat(id_npc_hi, id_npc_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node _id_npc_T_2 = asSInt(_id_npc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:53] node _id_npc_T_3 = add(_id_npc_T, _id_npc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 345:35] node _id_npc_T_4 = tail(_id_npc_T_3, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 345:35] node _id_npc_T_5 = asSInt(_id_npc_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 345:35] node id_npc = asUInt(_id_npc_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 345:65] inst csr of CSRFile @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 347:19] connect csr.clock, clock connect csr.reset, reset node _id_csr_en_T = eq(id_ctrl.csr, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _id_csr_en_T_1 = eq(id_ctrl.csr, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _id_csr_en_T_2 = eq(id_ctrl.csr, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _id_csr_en_T_3 = or(_id_csr_en_T, _id_csr_en_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node id_csr_en = or(_id_csr_en_T_3, _id_csr_en_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node id_system_insn = eq(id_ctrl.csr, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 349:36] node _id_csr_ren_T = eq(id_ctrl.csr, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _id_csr_ren_T_1 = eq(id_ctrl.csr, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _id_csr_ren_T_2 = or(_id_csr_ren_T, _id_csr_ren_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _id_csr_ren_T_3 = eq(ibuf.io.inst[0].bits.inst.rs1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 350:81] node id_csr_ren = and(_id_csr_ren_T_2, _id_csr_ren_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 350:54] node _id_csr_T = and(id_system_insn, id_ctrl.mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 351:35] node _id_csr_T_1 = mux(id_csr_ren, UInt<3>(0h2), id_ctrl.csr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 351:61] node id_csr = mux(_id_csr_T, UInt<3>(0h0), _id_csr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 351:19] node _id_csr_flush_T = eq(id_csr_ren, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 352:54] node _id_csr_flush_T_1 = and(id_csr_en, _id_csr_flush_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 352:51] node _id_csr_flush_T_2 = and(_id_csr_flush_T_1, csr.io.decode[0].write_flush) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 352:66] node id_csr_flush = or(id_system_insn, _id_csr_flush_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 352:37] node _id_set_vconfig_T = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>(0h8000707f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 353:100] node _id_set_vconfig_T_1 = eq(UInt<15>(0h7057), _id_set_vconfig_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 353:100] node _id_set_vconfig_T_2 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>(0hc000707f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 353:100] node _id_set_vconfig_T_3 = eq(UInt<32>(0hc0007057), _id_set_vconfig_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 353:100] node _id_set_vconfig_T_4 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>(0hfe00707f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 353:100] node _id_set_vconfig_T_5 = eq(UInt<32>(0h80007057), _id_set_vconfig_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 353:100] node _id_set_vconfig_T_6 = or(_id_set_vconfig_T_1, _id_set_vconfig_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _id_set_vconfig_T_7 = or(_id_set_vconfig_T_6, _id_set_vconfig_T_5) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node id_set_vconfig = and(_id_set_vconfig_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 353:120] connect id_ctrl.vec, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 355:15] node _id_illegal_insn_T = eq(id_ctrl.legal, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 388:25] node _id_illegal_insn_T_1 = or(id_ctrl.mul, id_ctrl.div) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 389:18] node _id_illegal_insn_T_2 = bits(csr.io.status.isa, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 389:55] node _id_illegal_insn_T_3 = eq(_id_illegal_insn_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 389:37] node _id_illegal_insn_T_4 = and(_id_illegal_insn_T_1, _id_illegal_insn_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 389:34] node _id_illegal_insn_T_5 = or(_id_illegal_insn_T, _id_illegal_insn_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 388:40] node _id_illegal_insn_T_6 = bits(csr.io.status.isa, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 390:38] node _id_illegal_insn_T_7 = eq(_id_illegal_insn_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 390:20] node _id_illegal_insn_T_8 = and(id_ctrl.amo, _id_illegal_insn_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 390:17] node _id_illegal_insn_T_9 = or(_id_illegal_insn_T_5, _id_illegal_insn_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 389:65] node _id_illegal_insn_T_10 = eq(id_ctrl.vec, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 391:73] node _id_illegal_insn_T_11 = and(io.fpu.illegal_rm, _id_illegal_insn_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 391:70] node _id_illegal_insn_T_12 = or(csr.io.decode[0].fp_illegal, _id_illegal_insn_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 391:48] node _id_illegal_insn_T_13 = and(id_ctrl.fp, _id_illegal_insn_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 391:16] node _id_illegal_insn_T_14 = or(_id_illegal_insn_T_9, _id_illegal_insn_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 390:48] node _id_illegal_insn_T_15 = or(id_ctrl.vec, id_set_vconfig) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 392:18] node _id_illegal_insn_T_16 = and(_id_illegal_insn_T_15, csr.io.decode[0].vector_illegal) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 392:37] node _id_illegal_insn_T_17 = or(_id_illegal_insn_T_14, _id_illegal_insn_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 391:88] node _id_illegal_insn_T_18 = bits(csr.io.status.isa, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 393:37] node _id_illegal_insn_T_19 = eq(_id_illegal_insn_T_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 393:19] node _id_illegal_insn_T_20 = and(id_ctrl.dp, _id_illegal_insn_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 393:16] node _id_illegal_insn_T_21 = or(_id_illegal_insn_T_17, _id_illegal_insn_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 392:72] node _id_illegal_insn_T_22 = bits(csr.io.status.isa, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 394:51] node _id_illegal_insn_T_23 = eq(_id_illegal_insn_T_22, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 394:33] node _id_illegal_insn_T_24 = and(ibuf.io.inst[0].bits.rvc, _id_illegal_insn_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 394:30] node _id_illegal_insn_T_25 = or(_id_illegal_insn_T_21, _id_illegal_insn_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 393:47] node _id_illegal_insn_T_26 = and(UInt<1>(0h0), id_ctrl.rxs2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 395:23] node _id_illegal_insn_T_27 = or(_id_illegal_insn_T_25, _id_illegal_insn_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 394:61] node _id_illegal_insn_T_28 = and(UInt<1>(0h0), id_ctrl.rxs1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 396:23] node _id_illegal_insn_T_29 = or(_id_illegal_insn_T_27, _id_illegal_insn_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 395:39] node _id_illegal_insn_T_30 = and(UInt<1>(0h0), id_ctrl.wxd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 397:22] node _id_illegal_insn_T_31 = or(_id_illegal_insn_T_29, _id_illegal_insn_T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 396:39] node _id_illegal_insn_T_32 = and(id_ctrl.rocc, csr.io.decode[0].rocc_illegal) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 398:18] node _id_illegal_insn_T_33 = or(_id_illegal_insn_T_31, _id_illegal_insn_T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 397:37] node _id_illegal_insn_T_34 = eq(id_csr_ren, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 399:52] node _id_illegal_insn_T_35 = and(_id_illegal_insn_T_34, csr.io.decode[0].write_illegal) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 399:64] node _id_illegal_insn_T_36 = or(csr.io.decode[0].read_illegal, _id_illegal_insn_T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 399:49] node _id_illegal_insn_T_37 = and(id_csr_en, _id_illegal_insn_T_36) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 399:15] node _id_illegal_insn_T_38 = or(_id_illegal_insn_T_33, _id_illegal_insn_T_37) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 398:51] node _id_illegal_insn_T_39 = eq(ibuf.io.inst[0].bits.rvc, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 400:5] node _id_illegal_insn_T_40 = and(id_system_insn, csr.io.decode[0].system_illegal) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 400:50] node _id_illegal_insn_T_41 = and(_id_illegal_insn_T_39, _id_illegal_insn_T_40) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 400:31] node id_illegal_insn = or(_id_illegal_insn_T_38, _id_illegal_insn_T_41) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 399:99] node _id_virtual_insn_T = eq(id_csr_ren, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 402:22] node _id_virtual_insn_T_1 = and(_id_virtual_insn_T, csr.io.decode[0].write_illegal) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 402:34] node _id_virtual_insn_T_2 = eq(_id_virtual_insn_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 402:20] node _id_virtual_insn_T_3 = and(id_csr_en, _id_virtual_insn_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 402:17] node _id_virtual_insn_T_4 = and(_id_virtual_insn_T_3, csr.io.decode[0].virtual_access_illegal) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 402:69] node _id_virtual_insn_T_5 = eq(ibuf.io.inst[0].bits.rvc, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 403:7] node _id_virtual_insn_T_6 = and(_id_virtual_insn_T_5, id_system_insn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 403:33] node _id_virtual_insn_T_7 = and(_id_virtual_insn_T_6, csr.io.decode[0].virtual_system_illegal) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 403:51] node _id_virtual_insn_T_8 = or(_id_virtual_insn_T_4, _id_virtual_insn_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 402:113] node id_virtual_insn = and(id_ctrl.legal, _id_virtual_insn_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 401:39] node id_amo_aq = bits(ibuf.io.inst[0].bits.inst.bits, 26, 26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 405:29] node id_amo_rl = bits(ibuf.io.inst[0].bits.inst.bits, 25, 25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 406:29] node id_fence_pred = bits(ibuf.io.inst[0].bits.inst.bits, 27, 24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 407:33] node id_fence_succ = bits(ibuf.io.inst[0].bits.inst.bits, 23, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 408:33] node _id_fence_next_T = and(id_ctrl.amo, id_amo_aq) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 409:52] node id_fence_next = or(id_ctrl.fence, _id_fence_next_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 409:37] node _id_mem_busy_T = eq(io.dmem.ordered, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 410:21] node id_mem_busy = or(_id_mem_busy_T, io.dmem.req.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 410:38] node _T = eq(id_mem_busy, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 411:9] when _T : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 411:23] connect id_reg_fence, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 411:38] node _id_rocc_busy_T = and(ex_reg_valid, ex_ctrl.rocc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 413:35] node _id_rocc_busy_T_1 = or(io.rocc.busy, _id_rocc_busy_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 413:19] node _id_rocc_busy_T_2 = and(mem_reg_valid, mem_ctrl.rocc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 414:20] node _id_rocc_busy_T_3 = or(_id_rocc_busy_T_1, _id_rocc_busy_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 413:51] node _id_rocc_busy_T_4 = and(wb_reg_valid, wb_ctrl.rocc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 414:53] node _id_rocc_busy_T_5 = or(_id_rocc_busy_T_3, _id_rocc_busy_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 414:37] node id_rocc_busy = and(UInt<1>(0h0), _id_rocc_busy_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 412:34] node _id_csr_rocc_write_T = and(UInt<1>(0h0), id_csr_en) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 415:87] node _id_csr_rocc_write_T_1 = eq(id_csr_ren, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 415:103] node id_csr_rocc_write = and(_id_csr_rocc_write_T, _id_csr_rocc_write_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 415:100] node _id_do_fence_T = or(id_ctrl.fence, id_csr_rocc_write) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 417:64] node _id_do_fence_T_1 = and(id_rocc_busy, _id_do_fence_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 417:46] node _id_do_fence_T_2 = and(UInt<1>(0h0), id_ctrl.fence) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 418:17] node _id_do_fence_T_3 = or(_id_do_fence_T_1, _id_do_fence_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 417:86] node _id_do_fence_T_4 = and(id_ctrl.amo, id_amo_rl) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 419:33] node _id_do_fence_T_5 = or(_id_do_fence_T_4, id_ctrl.fence_i) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 419:46] node _id_do_fence_T_6 = or(id_ctrl.mem, id_ctrl.rocc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 419:97] node _id_do_fence_T_7 = and(id_reg_fence, _id_do_fence_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 419:81] node _id_do_fence_T_8 = or(_id_do_fence_T_5, _id_do_fence_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 419:65] node _id_do_fence_T_9 = and(id_mem_busy, _id_do_fence_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 419:17] node _id_do_fence_T_10 = or(_id_do_fence_T_3, _id_do_fence_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 418:34] wire id_do_fence : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 417:32] connect id_do_fence, _id_do_fence_T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 417:32] inst bpu of BreakpointUnit @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 421:19] connect bpu.clock, clock connect bpu.reset, reset connect bpu.io.status.uie, csr.io.status.uie @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.sie, csr.io.status.sie @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.hie, csr.io.status.hie @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.mie, csr.io.status.mie @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.upie, csr.io.status.upie @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.spie, csr.io.status.spie @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.ube, csr.io.status.ube @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.mpie, csr.io.status.mpie @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.spp, csr.io.status.spp @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.vs, csr.io.status.vs @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.mpp, csr.io.status.mpp @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.fs, csr.io.status.fs @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.xs, csr.io.status.xs @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.mprv, csr.io.status.mprv @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.sum, csr.io.status.sum @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.mxr, csr.io.status.mxr @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.tvm, csr.io.status.tvm @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.tw, csr.io.status.tw @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.tsr, csr.io.status.tsr @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.zero1, csr.io.status.zero1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.sd_rv32, csr.io.status.sd_rv32 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.uxl, csr.io.status.uxl @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.sxl, csr.io.status.sxl @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.sbe, csr.io.status.sbe @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.mbe, csr.io.status.mbe @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.gva, csr.io.status.gva @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.mpv, csr.io.status.mpv @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.zero2, csr.io.status.zero2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.sd, csr.io.status.sd @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.v, csr.io.status.v @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.prv, csr.io.status.prv @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.dv, csr.io.status.dv @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.dprv, csr.io.status.dprv @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.isa, csr.io.status.isa @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.wfi, csr.io.status.wfi @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.cease, csr.io.status.cease @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.status.debug, csr.io.status.debug @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 422:17] connect bpu.io.bp[0].textra.sselect, csr.io.bp[0].textra.sselect @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].textra.pad1, csr.io.bp[0].textra.pad1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].textra.svalue, csr.io.bp[0].textra.svalue @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].textra.pad2, csr.io.bp[0].textra.pad2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].textra.mselect, csr.io.bp[0].textra.mselect @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].textra.mvalue, csr.io.bp[0].textra.mvalue @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].address, csr.io.bp[0].address @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].control.r, csr.io.bp[0].control.r @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].control.w, csr.io.bp[0].control.w @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].control.x, csr.io.bp[0].control.x @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].control.u, csr.io.bp[0].control.u @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].control.s, csr.io.bp[0].control.s @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].control.h, csr.io.bp[0].control.h @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].control.m, csr.io.bp[0].control.m @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].control.tmatch, csr.io.bp[0].control.tmatch @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].control.zero, csr.io.bp[0].control.zero @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].control.chain, csr.io.bp[0].control.chain @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].control.action, csr.io.bp[0].control.action @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].control.reserved, csr.io.bp[0].control.reserved @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].control.maskmax, csr.io.bp[0].control.maskmax @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].control.dmode, csr.io.bp[0].control.dmode @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.bp[0].control.ttype, csr.io.bp[0].control.ttype @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 423:13] connect bpu.io.pc, ibuf.io.pc @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 424:13] connect bpu.io.ea, mem_reg_wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 425:13] connect bpu.io.mcontext, csr.io.mcontext @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 426:19] connect bpu.io.scontext, csr.io.scontext @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 427:19] node _T_1 = or(csr.io.interrupt, bpu.io.debug_if) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] node _T_2 = or(_T_1, bpu.io.xcpt_if) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] node _T_3 = or(_T_2, ibuf.io.inst[0].bits.xcpt0.pf.inst) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] node _T_4 = or(_T_3, ibuf.io.inst[0].bits.xcpt0.gf.inst) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] node _T_5 = or(_T_4, ibuf.io.inst[0].bits.xcpt0.ae.inst) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] node _T_6 = or(_T_5, ibuf.io.inst[0].bits.xcpt1.pf.inst) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] node _T_7 = or(_T_6, ibuf.io.inst[0].bits.xcpt1.gf.inst) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] node _T_8 = or(_T_7, ibuf.io.inst[0].bits.xcpt1.ae.inst) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] node _T_9 = or(_T_8, id_virtual_insn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] node _T_10 = or(_T_9, id_illegal_insn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] wire id_xcpt : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:14] connect id_xcpt, _T_10 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:14] node _T_11 = mux(id_virtual_insn, UInt<5>(0h16), UInt<2>(0h2)) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _T_12 = mux(ibuf.io.inst[0].bits.xcpt1.ae.inst, UInt<1>(0h1), _T_11) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _T_13 = mux(ibuf.io.inst[0].bits.xcpt1.gf.inst, UInt<5>(0h14), _T_12) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _T_14 = mux(ibuf.io.inst[0].bits.xcpt1.pf.inst, UInt<4>(0hc), _T_13) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _T_15 = mux(ibuf.io.inst[0].bits.xcpt0.ae.inst, UInt<1>(0h1), _T_14) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _T_16 = mux(ibuf.io.inst[0].bits.xcpt0.gf.inst, UInt<5>(0h14), _T_15) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _T_17 = mux(ibuf.io.inst[0].bits.xcpt0.pf.inst, UInt<4>(0hc), _T_16) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _T_18 = mux(bpu.io.xcpt_if, UInt<2>(0h3), _T_17) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _T_19 = mux(bpu.io.debug_if, UInt<4>(0he), _T_18) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _T_20 = mux(csr.io.interrupt, csr.io.interrupt_cause, _T_19) @[src/main/scala/chisel3/util/Mux.scala 50:70] wire id_cause : UInt @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:50] connect id_cause, _T_20 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:50] node _T_21 = eq(id_cause, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:47] node _T_22 = and(id_xcpt, _T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:37] node _T_23 = eq(id_cause, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:47] node _T_24 = and(id_xcpt, _T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:37] node _T_25 = eq(id_cause, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:47] node _T_26 = and(id_xcpt, _T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:37] node _T_27 = eq(id_cause, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:47] node _T_28 = and(id_xcpt, _T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:37] node dcache_bypass_data = bits(io.dmem.resp.bits.data_word_bypass, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 456:62] node _ex_waddr_T = bits(ex_reg_inst, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 460:29] node ex_waddr = and(_ex_waddr_T, UInt<5>(0h1f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 460:36] node _mem_waddr_T = bits(mem_reg_inst, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 461:31] node mem_waddr = and(_mem_waddr_T, UInt<5>(0h1f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 461:38] node _wb_waddr_T = bits(wb_reg_inst, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 462:29] node wb_waddr = and(_wb_waddr_T, UInt<5>(0h1f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 462:36] node bypass_sources_1_1 = and(ex_reg_valid, ex_ctrl.wxd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 465:19] node _bypass_sources_T = and(mem_reg_valid, mem_ctrl.wxd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 466:20] node _bypass_sources_T_1 = eq(mem_ctrl.mem, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 466:39] node bypass_sources_2_1 = and(_bypass_sources_T, _bypass_sources_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 466:36] node bypass_sources_3_1 = and(mem_reg_valid, mem_ctrl.wxd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 467:20] node _id_bypass_src_T = eq(UInt<1>(0h0), id_raddr1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 468:82] node id_bypass_src_0_0 = and(UInt<1>(0h1), _id_bypass_src_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 468:74] node _id_bypass_src_T_1 = eq(ex_waddr, id_raddr1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 468:82] node id_bypass_src_0_1 = and(bypass_sources_1_1, _id_bypass_src_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 468:74] node _id_bypass_src_T_2 = eq(mem_waddr, id_raddr1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 468:82] node id_bypass_src_0_2 = and(bypass_sources_2_1, _id_bypass_src_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 468:74] node _id_bypass_src_T_3 = eq(mem_waddr, id_raddr1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 468:82] node id_bypass_src_0_3 = and(bypass_sources_3_1, _id_bypass_src_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 468:74] node _id_bypass_src_T_4 = eq(UInt<1>(0h0), id_raddr2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 468:82] node id_bypass_src_1_0 = and(UInt<1>(0h1), _id_bypass_src_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 468:74] node _id_bypass_src_T_5 = eq(ex_waddr, id_raddr2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 468:82] node id_bypass_src_1_1 = and(bypass_sources_1_1, _id_bypass_src_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 468:74] node _id_bypass_src_T_6 = eq(mem_waddr, id_raddr2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 468:82] node id_bypass_src_1_2 = and(bypass_sources_2_1, _id_bypass_src_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 468:74] node _id_bypass_src_T_7 = eq(mem_waddr, id_raddr2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 468:82] node id_bypass_src_1_3 = and(bypass_sources_3_1, _id_bypass_src_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 468:74] reg ex_reg_rs_bypass : UInt<1>[2], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 472:29] reg ex_reg_rs_lsb : UInt<2>[2], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 473:26] reg ex_reg_rs_msb : UInt[2], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 474:26] node _ex_rs_T = eq(ex_reg_rs_lsb[0], UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _ex_rs_T_1 = mux(_ex_rs_T, mem_reg_wdata, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _ex_rs_T_2 = eq(ex_reg_rs_lsb[0], UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _ex_rs_T_3 = mux(_ex_rs_T_2, wb_reg_wdata, _ex_rs_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _ex_rs_T_4 = eq(ex_reg_rs_lsb[0], UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _ex_rs_T_5 = mux(_ex_rs_T_4, dcache_bypass_data, _ex_rs_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _ex_rs_T_6 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 476:69] node ex_rs_0 = mux(ex_reg_rs_bypass[0], _ex_rs_T_5, _ex_rs_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 476:14] node _ex_rs_T_7 = eq(ex_reg_rs_lsb[1], UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _ex_rs_T_8 = mux(_ex_rs_T_7, mem_reg_wdata, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _ex_rs_T_9 = eq(ex_reg_rs_lsb[1], UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _ex_rs_T_10 = mux(_ex_rs_T_9, wb_reg_wdata, _ex_rs_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _ex_rs_T_11 = eq(ex_reg_rs_lsb[1], UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:86] node _ex_rs_T_12 = mux(_ex_rs_T_11, dcache_bypass_data, _ex_rs_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 40:76] node _ex_rs_T_13 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1]) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 476:69] node ex_rs_1 = mux(ex_reg_rs_bypass[1], _ex_rs_T_12, _ex_rs_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 476:14] node _ex_imm_sign_T = eq(ex_ctrl.sel_imm, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1372:24] node _ex_imm_sign_T_1 = bits(ex_reg_inst, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1372:44] node _ex_imm_sign_T_2 = asSInt(_ex_imm_sign_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1372:49] node ex_imm_sign = mux(_ex_imm_sign_T, asSInt(UInt<1>(0h0)), _ex_imm_sign_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1372:19] node _ex_imm_b30_20_T = eq(ex_ctrl.sel_imm, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1373:26] node _ex_imm_b30_20_T_1 = bits(ex_reg_inst, 30, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1373:41] node _ex_imm_b30_20_T_2 = asSInt(_ex_imm_b30_20_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1373:49] node ex_imm_b30_20 = mux(_ex_imm_b30_20_T, _ex_imm_b30_20_T_2, ex_imm_sign) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1373:21] node _ex_imm_b19_12_T = neq(ex_ctrl.sel_imm, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:26] node _ex_imm_b19_12_T_1 = neq(ex_ctrl.sel_imm, UInt<3>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:43] node _ex_imm_b19_12_T_2 = and(_ex_imm_b19_12_T, _ex_imm_b19_12_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:36] node _ex_imm_b19_12_T_3 = bits(ex_reg_inst, 19, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:65] node _ex_imm_b19_12_T_4 = asSInt(_ex_imm_b19_12_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:73] node ex_imm_b19_12 = mux(_ex_imm_b19_12_T_2, ex_imm_sign, _ex_imm_b19_12_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:21] node _ex_imm_b11_T = eq(ex_ctrl.sel_imm, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1375:23] node _ex_imm_b11_T_1 = eq(ex_ctrl.sel_imm, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1375:40] node _ex_imm_b11_T_2 = or(_ex_imm_b11_T, _ex_imm_b11_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1375:33] node _ex_imm_b11_T_3 = eq(ex_ctrl.sel_imm, UInt<3>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1376:23] node _ex_imm_b11_T_4 = bits(ex_reg_inst, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1376:39] node _ex_imm_b11_T_5 = asSInt(_ex_imm_b11_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1376:44] node _ex_imm_b11_T_6 = eq(ex_ctrl.sel_imm, UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1377:23] node _ex_imm_b11_T_7 = bits(ex_reg_inst, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1377:39] node _ex_imm_b11_T_8 = asSInt(_ex_imm_b11_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1377:43] node _ex_imm_b11_T_9 = mux(_ex_imm_b11_T_6, _ex_imm_b11_T_8, ex_imm_sign) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1377:18] node _ex_imm_b11_T_10 = mux(_ex_imm_b11_T_3, _ex_imm_b11_T_5, _ex_imm_b11_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1376:18] node ex_imm_b11 = mux(_ex_imm_b11_T_2, asSInt(UInt<1>(0h0)), _ex_imm_b11_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1375:18] node _ex_imm_b10_5_T = eq(ex_ctrl.sel_imm, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:25] node _ex_imm_b10_5_T_1 = eq(ex_ctrl.sel_imm, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:42] node _ex_imm_b10_5_T_2 = or(_ex_imm_b10_5_T, _ex_imm_b10_5_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:35] node _ex_imm_b10_5_T_3 = bits(ex_reg_inst, 30, 25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:62] node ex_imm_b10_5 = mux(_ex_imm_b10_5_T_2, UInt<1>(0h0), _ex_imm_b10_5_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:20] node _ex_imm_b4_1_T = eq(ex_ctrl.sel_imm, UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1379:24] node _ex_imm_b4_1_T_1 = eq(ex_ctrl.sel_imm, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:24] node _ex_imm_b4_1_T_2 = eq(ex_ctrl.sel_imm, UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:41] node _ex_imm_b4_1_T_3 = or(_ex_imm_b4_1_T_1, _ex_imm_b4_1_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:34] node _ex_imm_b4_1_T_4 = bits(ex_reg_inst, 11, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:57] node _ex_imm_b4_1_T_5 = eq(ex_ctrl.sel_imm, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1381:24] node _ex_imm_b4_1_T_6 = bits(ex_reg_inst, 19, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1381:39] node _ex_imm_b4_1_T_7 = bits(ex_reg_inst, 24, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1381:52] node _ex_imm_b4_1_T_8 = mux(_ex_imm_b4_1_T_5, _ex_imm_b4_1_T_6, _ex_imm_b4_1_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1381:19] node _ex_imm_b4_1_T_9 = mux(_ex_imm_b4_1_T_3, _ex_imm_b4_1_T_4, _ex_imm_b4_1_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:19] node ex_imm_b4_1 = mux(_ex_imm_b4_1_T, UInt<1>(0h0), _ex_imm_b4_1_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1379:19] node _ex_imm_b0_T = eq(ex_ctrl.sel_imm, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1382:22] node _ex_imm_b0_T_1 = bits(ex_reg_inst, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1382:37] node _ex_imm_b0_T_2 = eq(ex_ctrl.sel_imm, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1383:22] node _ex_imm_b0_T_3 = bits(ex_reg_inst, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1383:37] node _ex_imm_b0_T_4 = eq(ex_ctrl.sel_imm, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1384:22] node _ex_imm_b0_T_5 = bits(ex_reg_inst, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1384:37] node _ex_imm_b0_T_6 = mux(_ex_imm_b0_T_4, _ex_imm_b0_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1384:17] node _ex_imm_b0_T_7 = mux(_ex_imm_b0_T_2, _ex_imm_b0_T_3, _ex_imm_b0_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1383:17] node ex_imm_b0 = mux(_ex_imm_b0_T, _ex_imm_b0_T_1, _ex_imm_b0_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1382:17] node ex_imm_lo_hi = cat(ex_imm_b10_5, ex_imm_b4_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node ex_imm_lo = cat(ex_imm_lo_hi, ex_imm_b0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node ex_imm_hi_lo_lo = asUInt(ex_imm_b11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node ex_imm_hi_lo_hi = asUInt(ex_imm_b19_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node ex_imm_hi_lo = cat(ex_imm_hi_lo_hi, ex_imm_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node ex_imm_hi_hi_lo = asUInt(ex_imm_b30_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node ex_imm_hi_hi_hi = asUInt(ex_imm_sign) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node ex_imm_hi_hi = cat(ex_imm_hi_hi_hi, ex_imm_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node ex_imm_hi = cat(ex_imm_hi_hi, ex_imm_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node _ex_imm_T = cat(ex_imm_hi, ex_imm_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node ex_imm = asSInt(_ex_imm_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:53] node _ex_rs1shl_T = bits(ex_reg_inst, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 478:34] node _ex_rs1shl_T_1 = bits(ex_rs_0, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 478:47] node _ex_rs1shl_T_2 = mux(_ex_rs1shl_T, _ex_rs1shl_T_1, ex_rs_0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 478:22] node _ex_rs1shl_T_3 = bits(ex_reg_inst, 14, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 478:79] node ex_rs1shl = dshl(_ex_rs1shl_T_2, _ex_rs1shl_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 478:65] node _ex_op1_T = asSInt(ex_rs_0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 480:24] node _ex_op1_T_1 = asSInt(ex_reg_pc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 481:24] node _ex_op1_T_2 = eq(UInt<2>(0h1), ex_ctrl.sel_alu1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 479:48] node _ex_op1_T_3 = mux(_ex_op1_T_2, _ex_op1_T, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 479:48] node _ex_op1_T_4 = eq(UInt<2>(0h2), ex_ctrl.sel_alu1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 479:48] node _ex_op1_T_5 = mux(_ex_op1_T_4, _ex_op1_T_1, _ex_op1_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 479:48] node _ex_op1_T_6 = eq(UInt<2>(0h3), ex_ctrl.sel_alu1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 479:48] node ex_op1 = mux(_ex_op1_T_6, asSInt(UInt<1>(0h0)), _ex_op1_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 479:48] node _ex_op2_oh_T = bits(ex_ctrl.sel_alu2, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 484:48] node _ex_op2_oh_T_1 = shr(ex_reg_inst, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 484:66] node _ex_op2_oh_T_2 = mux(_ex_op2_oh_T, _ex_op2_oh_T_1, ex_rs_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 484:31] node _ex_op2_oh_T_3 = bits(_ex_op2_oh_T_2, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 484:90] node _ex_op2_oh_T_4 = dshl(UInt<1>(0h1), _ex_op2_oh_T_3) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node ex_op2_oh = asSInt(_ex_op2_oh_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 484:112] node _ex_op2_T = asSInt(ex_rs_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 486:24] node _ex_op2_T_1 = mux(ex_reg_rvc, asSInt(UInt<3>(0h2)), asSInt(UInt<4>(0h4))) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 488:19] node _ex_op2_T_2 = eq(UInt<3>(0h2), ex_ctrl.sel_alu2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 485:48] node _ex_op2_T_3 = mux(_ex_op2_T_2, _ex_op2_T, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 485:48] node _ex_op2_T_4 = eq(UInt<3>(0h3), ex_ctrl.sel_alu2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 485:48] node _ex_op2_T_5 = mux(_ex_op2_T_4, ex_imm, _ex_op2_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 485:48] node _ex_op2_T_6 = eq(UInt<3>(0h1), ex_ctrl.sel_alu2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 485:48] node ex_op2 = mux(_ex_op2_T_6, _ex_op2_T_1, _ex_op2_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 485:48] inst alu of RocketALU @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 511:19] connect alu.clock, clock connect alu.reset, reset connect alu.io.dw, ex_ctrl.alu_dw @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 512:13] connect alu.io.fn, ex_ctrl.alu_fn @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 513:13] node _alu_io_in2_T = asUInt(ex_op2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 514:24] connect alu.io.in2, _alu_io_in2_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 514:14] node _alu_io_in1_T = asUInt(ex_op1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 515:24] connect alu.io.in1, _alu_io_in1_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 515:14] inst div of MulDiv @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 518:19] connect div.clock, clock connect div.reset, reset node _div_io_req_valid_T = and(ex_reg_valid, ex_ctrl.div) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 519:36] connect div.io.req.valid, _div_io_req_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 519:20] connect div.io.req.bits.dw, ex_ctrl.alu_dw @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 520:22] connect div.io.req.bits.fn, ex_ctrl.alu_fn @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 521:22] connect div.io.req.bits.in1, ex_rs_0 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 522:23] connect div.io.req.bits.in2, ex_rs_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 523:23] connect div.io.req.bits.tag, ex_waddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 524:23] node _ex_reg_valid_T = eq(ctrl_killd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 532:19] connect ex_reg_valid, _ex_reg_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 532:16] node _ex_reg_replay_T = eq(take_pc_mem_wb, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 533:20] node _ex_reg_replay_T_1 = and(_ex_reg_replay_T, ibuf.io.inst[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 533:29] node _ex_reg_replay_T_2 = and(_ex_reg_replay_T_1, ibuf.io.inst[0].bits.replay) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 533:54] connect ex_reg_replay, _ex_reg_replay_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 533:17] node _ex_reg_xcpt_T = eq(ctrl_killd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 534:18] node _ex_reg_xcpt_T_1 = and(_ex_reg_xcpt_T, id_xcpt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 534:30] connect ex_reg_xcpt, _ex_reg_xcpt_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 534:15] node _ex_reg_xcpt_interrupt_T = eq(take_pc_mem_wb, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 535:28] node _ex_reg_xcpt_interrupt_T_1 = and(_ex_reg_xcpt_interrupt_T, ibuf.io.inst[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 535:37] node _ex_reg_xcpt_interrupt_T_2 = and(_ex_reg_xcpt_interrupt_T_1, csr.io.interrupt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 535:62] connect ex_reg_xcpt_interrupt, _ex_reg_xcpt_interrupt_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 535:25] node _T_29 = eq(ctrl_killd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 537:9] when _T_29 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 537:22] connect ex_ctrl, id_ctrl @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 538:13] connect ex_reg_rvc, ibuf.io.inst[0].bits.rvc @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 539:16] connect ex_ctrl.csr, id_csr @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 540:17] node _T_30 = eq(id_fence_succ, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 541:42] node _T_31 = and(id_ctrl.fence, _T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 541:25] when _T_31 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 541:51] connect id_reg_pause, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 541:66] when id_fence_next : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 542:26] connect id_reg_fence, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 542:41] when id_xcpt : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 543:20] connect ex_ctrl.alu_fn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 544:22] connect ex_ctrl.alu_dw, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 545:22] connect ex_ctrl.sel_alu1, UInt<2>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 546:24] connect ex_ctrl.sel_alu2, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 547:24] node hi = cat(ibuf.io.inst[0].bits.xcpt1.pf.inst, ibuf.io.inst[0].bits.xcpt1.gf.inst) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 548:22] node _T_32 = cat(hi, ibuf.io.inst[0].bits.xcpt1.ae.inst) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 548:22] node _T_33 = orr(_T_32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 548:29] when _T_33 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 548:34] connect ex_ctrl.sel_alu1, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 549:26] connect ex_ctrl.sel_alu2, UInt<3>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 550:26] connect ex_reg_rvc, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 551:20] node hi_1 = cat(ibuf.io.inst[0].bits.xcpt0.pf.inst, ibuf.io.inst[0].bits.xcpt0.gf.inst) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 553:40] node _T_34 = cat(hi_1, ibuf.io.inst[0].bits.xcpt0.ae.inst) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 553:40] node _T_35 = orr(_T_34) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 553:47] node _T_36 = or(bpu.io.xcpt_if, _T_35) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 553:28] when _T_36 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 553:52] connect ex_ctrl.sel_alu1, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 554:26] connect ex_ctrl.sel_alu2, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 555:26] node _ex_reg_flush_pipe_T = or(id_ctrl.fence_i, id_csr_flush) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 558:42] connect ex_reg_flush_pipe, _ex_reg_flush_pipe_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 558:23] connect ex_reg_load_use, id_load_use @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 559:21] node _ex_reg_hls_T = and(UInt<1>(0h0), id_system_insn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 560:37] node _ex_reg_hls_T_1 = eq(id_ctrl.mem_cmd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _ex_reg_hls_T_2 = eq(id_ctrl.mem_cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _ex_reg_hls_T_3 = eq(id_ctrl.mem_cmd, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _ex_reg_hls_T_4 = or(_ex_reg_hls_T_1, _ex_reg_hls_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _ex_reg_hls_T_5 = or(_ex_reg_hls_T_4, _ex_reg_hls_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _ex_reg_hls_T_6 = and(_ex_reg_hls_T, _ex_reg_hls_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 560:55] connect ex_reg_hls, _ex_reg_hls_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 560:16] node _ex_reg_mem_size_T = and(UInt<1>(0h0), id_system_insn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 561:46] node _ex_reg_mem_size_T_1 = bits(ibuf.io.inst[0].bits.inst.bits, 27, 26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 561:75] node _ex_reg_mem_size_T_2 = bits(ibuf.io.inst[0].bits.inst.bits, 13, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 561:95] node _ex_reg_mem_size_T_3 = mux(_ex_reg_mem_size_T, _ex_reg_mem_size_T_1, _ex_reg_mem_size_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 561:27] connect ex_reg_mem_size, _ex_reg_mem_size_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 561:21] node _T_37 = eq(id_ctrl.mem_cmd, UInt<5>(0h14)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_38 = eq(id_ctrl.mem_cmd, UInt<5>(0h15)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_39 = eq(id_ctrl.mem_cmd, UInt<5>(0h16)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_40 = eq(id_ctrl.mem_cmd, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _T_41 = or(_T_37, _T_38) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_42 = or(_T_41, _T_39) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _T_43 = or(_T_42, _T_40) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] when _T_43 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 562:81] node _ex_reg_mem_size_T_4 = neq(id_raddr2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 563:40] node _ex_reg_mem_size_T_5 = neq(id_raddr1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 563:59] node _ex_reg_mem_size_T_6 = cat(_ex_reg_mem_size_T_4, _ex_reg_mem_size_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 563:29] connect ex_reg_mem_size, _ex_reg_mem_size_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 563:23] node _T_44 = eq(id_ctrl.mem_cmd, UInt<5>(0h14)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 565:27] node _T_45 = and(_T_44, csr.io.status.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 565:40] when _T_45 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 565:60] connect ex_ctrl.mem_cmd, UInt<5>(0h15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 566:23] node _do_bypass_T = or(id_bypass_src_0_0, id_bypass_src_0_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 575:48] node _do_bypass_T_1 = or(_do_bypass_T, id_bypass_src_0_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 575:48] node do_bypass = or(_do_bypass_T_1, id_bypass_src_0_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 575:48] node _bypass_src_T = mux(id_bypass_src_0_2, UInt<2>(0h2), UInt<2>(0h3)) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _bypass_src_T_1 = mux(id_bypass_src_0_1, UInt<1>(0h1), _bypass_src_T) @[src/main/scala/chisel3/util/Mux.scala 50:70] node bypass_src = mux(id_bypass_src_0_0, UInt<1>(0h0), _bypass_src_T_1) @[src/main/scala/chisel3/util/Mux.scala 50:70] connect ex_reg_rs_bypass[0], do_bypass @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 577:27] connect ex_reg_rs_lsb[0], bypass_src @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 578:24] node _T_46 = eq(do_bypass, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 579:26] node _T_47 = and(id_ctrl.rxs1, _T_46) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 579:23] when _T_47 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 579:38] node _ex_reg_rs_lsb_0_T = bits(id_rs_0, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 580:37] connect ex_reg_rs_lsb[0], _ex_reg_rs_lsb_0_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 580:26] node _ex_reg_rs_msb_0_T = shr(id_rs_0, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 581:38] connect ex_reg_rs_msb[0], _ex_reg_rs_msb_0_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 581:26] node _do_bypass_T_2 = or(id_bypass_src_1_0, id_bypass_src_1_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 575:48] node _do_bypass_T_3 = or(_do_bypass_T_2, id_bypass_src_1_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 575:48] node do_bypass_1 = or(_do_bypass_T_3, id_bypass_src_1_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 575:48] node _bypass_src_T_2 = mux(id_bypass_src_1_2, UInt<2>(0h2), UInt<2>(0h3)) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _bypass_src_T_3 = mux(id_bypass_src_1_1, UInt<1>(0h1), _bypass_src_T_2) @[src/main/scala/chisel3/util/Mux.scala 50:70] node bypass_src_1 = mux(id_bypass_src_1_0, UInt<1>(0h0), _bypass_src_T_3) @[src/main/scala/chisel3/util/Mux.scala 50:70] connect ex_reg_rs_bypass[1], do_bypass_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 577:27] connect ex_reg_rs_lsb[1], bypass_src_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 578:24] node _T_48 = eq(do_bypass_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 579:26] node _T_49 = and(id_ctrl.rxs2, _T_48) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 579:23] when _T_49 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 579:38] node _ex_reg_rs_lsb_1_T = bits(id_rs_1, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 580:37] connect ex_reg_rs_lsb[1], _ex_reg_rs_lsb_1_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 580:26] node _ex_reg_rs_msb_1_T = shr(id_rs_1, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 581:38] connect ex_reg_rs_msb[1], _ex_reg_rs_msb_1_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 581:26] node _T_50 = or(id_illegal_insn, id_virtual_insn) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 584:27] when _T_50 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 584:47] node _inst_T = bits(ibuf.io.inst[0].bits.raw, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 585:62] node inst = mux(ibuf.io.inst[0].bits.rvc, _inst_T, ibuf.io.inst[0].bits.raw) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 585:21] connect ex_reg_rs_bypass[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 586:27] node _ex_reg_rs_lsb_0_T_1 = bits(inst, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 587:31] connect ex_reg_rs_lsb[0], _ex_reg_rs_lsb_0_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 587:24] node _ex_reg_rs_msb_0_T_1 = shr(inst, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 588:32] connect ex_reg_rs_msb[0], _ex_reg_rs_msb_0_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 588:24] node _T_51 = eq(ctrl_killd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 591:9] node _T_52 = or(_T_51, csr.io.interrupt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 591:21] node _T_53 = or(_T_52, ibuf.io.inst[0].bits.replay) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 591:41] when _T_53 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 591:73] connect ex_reg_cause, id_cause @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 592:18] connect ex_reg_inst, ibuf.io.inst[0].bits.inst.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 593:17] connect ex_reg_raw_inst, ibuf.io.inst[0].bits.raw @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 594:21] connect ex_reg_pc, ibuf.io.pc @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 595:15] connect ex_reg_btb_resp, ibuf.io.btb_resp @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 596:21] connect ex_reg_wphit[0], bpu.io.bpwatch[0].ivalid[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 597:18] node _ex_reg_set_vconfig_T = eq(id_xcpt, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 598:45] node _ex_reg_set_vconfig_T_1 = and(id_set_vconfig, _ex_reg_set_vconfig_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 598:42] connect ex_reg_set_vconfig, _ex_reg_set_vconfig_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 598:24] node _ex_pc_valid_T = or(ex_reg_valid, ex_reg_replay) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 602:34] node ex_pc_valid = or(_ex_pc_valid_T, ex_reg_xcpt_interrupt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 602:51] node _wb_dcache_miss_T = eq(io.dmem.resp.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 603:39] node wb_dcache_miss = and(wb_ctrl.mem, _wb_dcache_miss_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 603:36] node _replay_ex_structural_T = eq(io.dmem.req.ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 604:45] node _replay_ex_structural_T_1 = and(ex_ctrl.mem, _replay_ex_structural_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 604:42] node _replay_ex_structural_T_2 = eq(div.io.req.ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 605:45] node _replay_ex_structural_T_3 = and(ex_ctrl.div, _replay_ex_structural_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 605:42] node _replay_ex_structural_T_4 = or(_replay_ex_structural_T_1, _replay_ex_structural_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 604:64] node _replay_ex_structural_T_5 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 606:45] node _replay_ex_structural_T_6 = and(ex_ctrl.vec, _replay_ex_structural_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 606:42] node replay_ex_structural = or(_replay_ex_structural_T_4, _replay_ex_structural_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 605:63] node replay_ex_load_use = and(wb_dcache_miss, ex_reg_load_use) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 607:43] node _replay_ex_T = or(replay_ex_structural, replay_ex_load_use) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 608:75] node _replay_ex_T_1 = and(ex_reg_valid, _replay_ex_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 608:50] node replay_ex = or(ex_reg_replay, _replay_ex_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 608:33] node _ctrl_killx_T = or(take_pc_mem_wb, replay_ex) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 609:35] node _ctrl_killx_T_1 = eq(ex_reg_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 609:51] node ctrl_killx = or(_ctrl_killx_T, _ctrl_killx_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 609:48] node _ex_slow_bypass_T = eq(ex_ctrl.mem_cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 611:40] node _ex_slow_bypass_T_1 = lt(ex_reg_mem_size, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 611:69] node ex_slow_bypass = or(_ex_slow_bypass_T, _ex_slow_bypass_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 611:50] node _ex_sfence_T = and(UInt<1>(0h0), ex_ctrl.mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 612:29] node _ex_sfence_T_1 = eq(ex_ctrl.mem_cmd, UInt<5>(0h14)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 612:64] node _ex_sfence_T_2 = eq(ex_ctrl.mem_cmd, UInt<5>(0h15)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 612:96] node _ex_sfence_T_3 = or(_ex_sfence_T_1, _ex_sfence_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 612:77] node _ex_sfence_T_4 = eq(ex_ctrl.mem_cmd, UInt<5>(0h16)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 612:129] node _ex_sfence_T_5 = or(_ex_sfence_T_3, _ex_sfence_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 612:110] node ex_sfence = and(_ex_sfence_T, _ex_sfence_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 612:44] node _T_54 = or(ex_reg_xcpt_interrupt, ex_reg_xcpt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 615:28] wire ex_xcpt : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:14] connect ex_xcpt, _T_54 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:14] wire ex_cause : UInt @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:50] connect ex_cause, ex_reg_cause @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:50] node _T_55 = eq(ex_cause, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:47] node _T_56 = and(ex_xcpt, _T_55) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:37] node _T_57 = eq(ex_cause, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:47] node _T_58 = and(ex_xcpt, _T_57) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:37] node _T_59 = eq(ex_cause, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:47] node _T_60 = and(ex_xcpt, _T_59) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:37] node _T_61 = eq(ex_cause, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:47] node _T_62 = and(ex_xcpt, _T_61) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:37] node _mem_pc_valid_T = or(mem_reg_valid, mem_reg_replay) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 621:36] node mem_pc_valid = or(_mem_pc_valid_T, mem_reg_xcpt_interrupt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 621:54] node _mem_br_target_T = asSInt(mem_reg_pc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 622:34] node _mem_br_target_T_1 = and(mem_ctrl.branch, mem_br_taken) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 623:25] node _mem_br_target_sign_T = eq(UInt<3>(0h1), UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1372:24] node _mem_br_target_sign_T_1 = bits(mem_reg_inst, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1372:44] node _mem_br_target_sign_T_2 = asSInt(_mem_br_target_sign_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1372:49] node mem_br_target_sign = mux(_mem_br_target_sign_T, asSInt(UInt<1>(0h0)), _mem_br_target_sign_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1372:19] node _mem_br_target_b30_20_T = eq(UInt<3>(0h1), UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1373:26] node _mem_br_target_b30_20_T_1 = bits(mem_reg_inst, 30, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1373:41] node _mem_br_target_b30_20_T_2 = asSInt(_mem_br_target_b30_20_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1373:49] node mem_br_target_b30_20 = mux(_mem_br_target_b30_20_T, _mem_br_target_b30_20_T_2, mem_br_target_sign) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1373:21] node _mem_br_target_b19_12_T = neq(UInt<3>(0h1), UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:26] node _mem_br_target_b19_12_T_1 = neq(UInt<3>(0h1), UInt<3>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:43] node _mem_br_target_b19_12_T_2 = and(_mem_br_target_b19_12_T, _mem_br_target_b19_12_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:36] node _mem_br_target_b19_12_T_3 = bits(mem_reg_inst, 19, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:65] node _mem_br_target_b19_12_T_4 = asSInt(_mem_br_target_b19_12_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:73] node mem_br_target_b19_12 = mux(_mem_br_target_b19_12_T_2, mem_br_target_sign, _mem_br_target_b19_12_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:21] node _mem_br_target_b11_T = eq(UInt<3>(0h1), UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1375:23] node _mem_br_target_b11_T_1 = eq(UInt<3>(0h1), UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1375:40] node _mem_br_target_b11_T_2 = or(_mem_br_target_b11_T, _mem_br_target_b11_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1375:33] node _mem_br_target_b11_T_3 = eq(UInt<3>(0h1), UInt<3>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1376:23] node _mem_br_target_b11_T_4 = bits(mem_reg_inst, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1376:39] node _mem_br_target_b11_T_5 = asSInt(_mem_br_target_b11_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1376:44] node _mem_br_target_b11_T_6 = eq(UInt<3>(0h1), UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1377:23] node _mem_br_target_b11_T_7 = bits(mem_reg_inst, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1377:39] node _mem_br_target_b11_T_8 = asSInt(_mem_br_target_b11_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1377:43] node _mem_br_target_b11_T_9 = mux(_mem_br_target_b11_T_6, _mem_br_target_b11_T_8, mem_br_target_sign) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1377:18] node _mem_br_target_b11_T_10 = mux(_mem_br_target_b11_T_3, _mem_br_target_b11_T_5, _mem_br_target_b11_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1376:18] node mem_br_target_b11 = mux(_mem_br_target_b11_T_2, asSInt(UInt<1>(0h0)), _mem_br_target_b11_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1375:18] node _mem_br_target_b10_5_T = eq(UInt<3>(0h1), UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:25] node _mem_br_target_b10_5_T_1 = eq(UInt<3>(0h1), UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:42] node _mem_br_target_b10_5_T_2 = or(_mem_br_target_b10_5_T, _mem_br_target_b10_5_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:35] node _mem_br_target_b10_5_T_3 = bits(mem_reg_inst, 30, 25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:62] node mem_br_target_b10_5 = mux(_mem_br_target_b10_5_T_2, UInt<1>(0h0), _mem_br_target_b10_5_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:20] node _mem_br_target_b4_1_T = eq(UInt<3>(0h1), UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1379:24] node _mem_br_target_b4_1_T_1 = eq(UInt<3>(0h1), UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:24] node _mem_br_target_b4_1_T_2 = eq(UInt<3>(0h1), UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:41] node _mem_br_target_b4_1_T_3 = or(_mem_br_target_b4_1_T_1, _mem_br_target_b4_1_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:34] node _mem_br_target_b4_1_T_4 = bits(mem_reg_inst, 11, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:57] node _mem_br_target_b4_1_T_5 = eq(UInt<3>(0h1), UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1381:24] node _mem_br_target_b4_1_T_6 = bits(mem_reg_inst, 19, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1381:39] node _mem_br_target_b4_1_T_7 = bits(mem_reg_inst, 24, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1381:52] node _mem_br_target_b4_1_T_8 = mux(_mem_br_target_b4_1_T_5, _mem_br_target_b4_1_T_6, _mem_br_target_b4_1_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1381:19] node _mem_br_target_b4_1_T_9 = mux(_mem_br_target_b4_1_T_3, _mem_br_target_b4_1_T_4, _mem_br_target_b4_1_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:19] node mem_br_target_b4_1 = mux(_mem_br_target_b4_1_T, UInt<1>(0h0), _mem_br_target_b4_1_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1379:19] node _mem_br_target_b0_T = eq(UInt<3>(0h1), UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1382:22] node _mem_br_target_b0_T_1 = bits(mem_reg_inst, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1382:37] node _mem_br_target_b0_T_2 = eq(UInt<3>(0h1), UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1383:22] node _mem_br_target_b0_T_3 = bits(mem_reg_inst, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1383:37] node _mem_br_target_b0_T_4 = eq(UInt<3>(0h1), UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1384:22] node _mem_br_target_b0_T_5 = bits(mem_reg_inst, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1384:37] node _mem_br_target_b0_T_6 = mux(_mem_br_target_b0_T_4, _mem_br_target_b0_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1384:17] node _mem_br_target_b0_T_7 = mux(_mem_br_target_b0_T_2, _mem_br_target_b0_T_3, _mem_br_target_b0_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1383:17] node mem_br_target_b0 = mux(_mem_br_target_b0_T, _mem_br_target_b0_T_1, _mem_br_target_b0_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1382:17] node mem_br_target_lo_hi = cat(mem_br_target_b10_5, mem_br_target_b4_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node mem_br_target_lo = cat(mem_br_target_lo_hi, mem_br_target_b0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node mem_br_target_hi_lo_lo = asUInt(mem_br_target_b11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node mem_br_target_hi_lo_hi = asUInt(mem_br_target_b19_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node mem_br_target_hi_lo = cat(mem_br_target_hi_lo_hi, mem_br_target_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node mem_br_target_hi_hi_lo = asUInt(mem_br_target_b30_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node mem_br_target_hi_hi_hi = asUInt(mem_br_target_sign) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node mem_br_target_hi_hi = cat(mem_br_target_hi_hi_hi, mem_br_target_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node mem_br_target_hi = cat(mem_br_target_hi_hi, mem_br_target_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node _mem_br_target_T_2 = cat(mem_br_target_hi, mem_br_target_lo) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node _mem_br_target_T_3 = asSInt(_mem_br_target_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:53] node _mem_br_target_sign_T_3 = eq(UInt<3>(0h3), UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1372:24] node _mem_br_target_sign_T_4 = bits(mem_reg_inst, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1372:44] node _mem_br_target_sign_T_5 = asSInt(_mem_br_target_sign_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1372:49] node mem_br_target_sign_1 = mux(_mem_br_target_sign_T_3, asSInt(UInt<1>(0h0)), _mem_br_target_sign_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1372:19] node _mem_br_target_b30_20_T_3 = eq(UInt<3>(0h3), UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1373:26] node _mem_br_target_b30_20_T_4 = bits(mem_reg_inst, 30, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1373:41] node _mem_br_target_b30_20_T_5 = asSInt(_mem_br_target_b30_20_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1373:49] node mem_br_target_b30_20_1 = mux(_mem_br_target_b30_20_T_3, _mem_br_target_b30_20_T_5, mem_br_target_sign_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1373:21] node _mem_br_target_b19_12_T_5 = neq(UInt<3>(0h3), UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:26] node _mem_br_target_b19_12_T_6 = neq(UInt<3>(0h3), UInt<3>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:43] node _mem_br_target_b19_12_T_7 = and(_mem_br_target_b19_12_T_5, _mem_br_target_b19_12_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:36] node _mem_br_target_b19_12_T_8 = bits(mem_reg_inst, 19, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:65] node _mem_br_target_b19_12_T_9 = asSInt(_mem_br_target_b19_12_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:73] node mem_br_target_b19_12_1 = mux(_mem_br_target_b19_12_T_7, mem_br_target_sign_1, _mem_br_target_b19_12_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1374:21] node _mem_br_target_b11_T_11 = eq(UInt<3>(0h3), UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1375:23] node _mem_br_target_b11_T_12 = eq(UInt<3>(0h3), UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1375:40] node _mem_br_target_b11_T_13 = or(_mem_br_target_b11_T_11, _mem_br_target_b11_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1375:33] node _mem_br_target_b11_T_14 = eq(UInt<3>(0h3), UInt<3>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1376:23] node _mem_br_target_b11_T_15 = bits(mem_reg_inst, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1376:39] node _mem_br_target_b11_T_16 = asSInt(_mem_br_target_b11_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1376:44] node _mem_br_target_b11_T_17 = eq(UInt<3>(0h3), UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1377:23] node _mem_br_target_b11_T_18 = bits(mem_reg_inst, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1377:39] node _mem_br_target_b11_T_19 = asSInt(_mem_br_target_b11_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1377:43] node _mem_br_target_b11_T_20 = mux(_mem_br_target_b11_T_17, _mem_br_target_b11_T_19, mem_br_target_sign_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1377:18] node _mem_br_target_b11_T_21 = mux(_mem_br_target_b11_T_14, _mem_br_target_b11_T_16, _mem_br_target_b11_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1376:18] node mem_br_target_b11_1 = mux(_mem_br_target_b11_T_13, asSInt(UInt<1>(0h0)), _mem_br_target_b11_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1375:18] node _mem_br_target_b10_5_T_4 = eq(UInt<3>(0h3), UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:25] node _mem_br_target_b10_5_T_5 = eq(UInt<3>(0h3), UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:42] node _mem_br_target_b10_5_T_6 = or(_mem_br_target_b10_5_T_4, _mem_br_target_b10_5_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:35] node _mem_br_target_b10_5_T_7 = bits(mem_reg_inst, 30, 25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:62] node mem_br_target_b10_5_1 = mux(_mem_br_target_b10_5_T_6, UInt<1>(0h0), _mem_br_target_b10_5_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1378:20] node _mem_br_target_b4_1_T_10 = eq(UInt<3>(0h3), UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1379:24] node _mem_br_target_b4_1_T_11 = eq(UInt<3>(0h3), UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:24] node _mem_br_target_b4_1_T_12 = eq(UInt<3>(0h3), UInt<3>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:41] node _mem_br_target_b4_1_T_13 = or(_mem_br_target_b4_1_T_11, _mem_br_target_b4_1_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:34] node _mem_br_target_b4_1_T_14 = bits(mem_reg_inst, 11, 8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:57] node _mem_br_target_b4_1_T_15 = eq(UInt<3>(0h3), UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1381:24] node _mem_br_target_b4_1_T_16 = bits(mem_reg_inst, 19, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1381:39] node _mem_br_target_b4_1_T_17 = bits(mem_reg_inst, 24, 21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1381:52] node _mem_br_target_b4_1_T_18 = mux(_mem_br_target_b4_1_T_15, _mem_br_target_b4_1_T_16, _mem_br_target_b4_1_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1381:19] node _mem_br_target_b4_1_T_19 = mux(_mem_br_target_b4_1_T_13, _mem_br_target_b4_1_T_14, _mem_br_target_b4_1_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1380:19] node mem_br_target_b4_1_1 = mux(_mem_br_target_b4_1_T_10, UInt<1>(0h0), _mem_br_target_b4_1_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1379:19] node _mem_br_target_b0_T_8 = eq(UInt<3>(0h3), UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1382:22] node _mem_br_target_b0_T_9 = bits(mem_reg_inst, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1382:37] node _mem_br_target_b0_T_10 = eq(UInt<3>(0h3), UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1383:22] node _mem_br_target_b0_T_11 = bits(mem_reg_inst, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1383:37] node _mem_br_target_b0_T_12 = eq(UInt<3>(0h3), UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1384:22] node _mem_br_target_b0_T_13 = bits(mem_reg_inst, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1384:37] node _mem_br_target_b0_T_14 = mux(_mem_br_target_b0_T_12, _mem_br_target_b0_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1384:17] node _mem_br_target_b0_T_15 = mux(_mem_br_target_b0_T_10, _mem_br_target_b0_T_11, _mem_br_target_b0_T_14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1383:17] node mem_br_target_b0_1 = mux(_mem_br_target_b0_T_8, _mem_br_target_b0_T_9, _mem_br_target_b0_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1382:17] node mem_br_target_lo_hi_1 = cat(mem_br_target_b10_5_1, mem_br_target_b4_1_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node mem_br_target_lo_1 = cat(mem_br_target_lo_hi_1, mem_br_target_b0_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node mem_br_target_hi_lo_lo_1 = asUInt(mem_br_target_b11_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node mem_br_target_hi_lo_hi_1 = asUInt(mem_br_target_b19_12_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node mem_br_target_hi_lo_1 = cat(mem_br_target_hi_lo_hi_1, mem_br_target_hi_lo_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node mem_br_target_hi_hi_lo_1 = asUInt(mem_br_target_b30_20_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node mem_br_target_hi_hi_hi_1 = asUInt(mem_br_target_sign_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node mem_br_target_hi_hi_1 = cat(mem_br_target_hi_hi_hi_1, mem_br_target_hi_hi_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node mem_br_target_hi_1 = cat(mem_br_target_hi_hi_1, mem_br_target_hi_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node _mem_br_target_T_4 = cat(mem_br_target_hi_1, mem_br_target_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:8] node _mem_br_target_T_5 = asSInt(_mem_br_target_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1386:53] node _mem_br_target_T_6 = mux(mem_reg_rvc, asSInt(UInt<3>(0h2)), asSInt(UInt<4>(0h4))) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 625:8] node _mem_br_target_T_7 = mux(mem_ctrl.jal, _mem_br_target_T_5, _mem_br_target_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 624:8] node _mem_br_target_T_8 = mux(_mem_br_target_T_1, _mem_br_target_T_3, _mem_br_target_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 623:8] node _mem_br_target_T_9 = add(_mem_br_target_T, _mem_br_target_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 622:41] node _mem_br_target_T_10 = tail(_mem_br_target_T_9, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 622:41] node mem_br_target = asSInt(_mem_br_target_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 622:41] node _mem_npc_T = or(mem_ctrl.jalr, mem_reg_sfence) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 626:36] node _mem_npc_a_T = shr(mem_reg_wdata, 33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1324:17] node mem_npc_a = asSInt(_mem_npc_a_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1324:23] node _mem_npc_msb_T = eq(mem_npc_a, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:21] node _mem_npc_msb_T_1 = eq(mem_npc_a, asSInt(UInt<1>(0h1))) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:34] node _mem_npc_msb_T_2 = or(_mem_npc_msb_T, _mem_npc_msb_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:29] node _mem_npc_msb_T_3 = bits(mem_reg_wdata, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:46] node _mem_npc_msb_T_4 = bits(mem_reg_wdata, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:54] node _mem_npc_msb_T_5 = eq(_mem_npc_msb_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:51] node mem_npc_msb = mux(_mem_npc_msb_T_2, _mem_npc_msb_T_3, _mem_npc_msb_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:18] node _mem_npc_T_1 = bits(mem_reg_wdata, 32, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1326:16] node _mem_npc_T_2 = cat(mem_npc_msb, _mem_npc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1326:8] node _mem_npc_T_3 = asSInt(_mem_npc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 626:106] node _mem_npc_T_4 = mux(_mem_npc_T, _mem_npc_T_3, mem_br_target) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 626:21] node _mem_npc_T_5 = and(_mem_npc_T_4, asSInt(UInt<2>(0h2))) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 626:129] node _mem_npc_T_6 = asSInt(_mem_npc_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 626:129] node mem_npc = asUInt(_mem_npc_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 626:139] node _mem_wrong_npc_T = neq(mem_npc, ex_reg_pc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 628:30] node _mem_wrong_npc_T_1 = or(ibuf.io.inst[0].valid, ibuf.io.imem.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 629:31] node _mem_wrong_npc_T_2 = neq(mem_npc, ibuf.io.pc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 629:62] node _mem_wrong_npc_T_3 = mux(_mem_wrong_npc_T_1, _mem_wrong_npc_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 629:8] node mem_wrong_npc = mux(ex_pc_valid, _mem_wrong_npc_T, _mem_wrong_npc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 628:8] node _mem_npc_misaligned_T = bits(csr.io.status.isa, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 630:46] node _mem_npc_misaligned_T_1 = eq(_mem_npc_misaligned_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 630:28] node _mem_npc_misaligned_T_2 = bits(mem_npc, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 630:66] node _mem_npc_misaligned_T_3 = and(_mem_npc_misaligned_T_1, _mem_npc_misaligned_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 630:56] node _mem_npc_misaligned_T_4 = eq(mem_reg_sfence, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 630:73] node mem_npc_misaligned = and(_mem_npc_misaligned_T_3, _mem_npc_misaligned_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 630:70] node _mem_int_wdata_T = eq(mem_reg_xcpt, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 631:27] node _mem_int_wdata_T_1 = xor(mem_ctrl.jalr, mem_npc_misaligned) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 631:59] node _mem_int_wdata_T_2 = and(_mem_int_wdata_T, _mem_int_wdata_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 631:41] node _mem_int_wdata_T_3 = asSInt(mem_reg_wdata) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 631:111] node _mem_int_wdata_T_4 = mux(_mem_int_wdata_T_2, mem_br_target, _mem_int_wdata_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 631:26] node mem_int_wdata = asUInt(_mem_int_wdata_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 631:119] node _mem_cfi_T = or(mem_ctrl.branch, mem_ctrl.jalr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 632:33] node mem_cfi = or(_mem_cfi_T, mem_ctrl.jal) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 632:50] node _mem_cfi_taken_T = and(mem_ctrl.branch, mem_br_taken) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 633:40] node _mem_cfi_taken_T_1 = or(_mem_cfi_taken_T, mem_ctrl.jalr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 633:57] node mem_cfi_taken = or(_mem_cfi_taken_T_1, mem_ctrl.jal) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 633:74] node _mem_direction_misprediction_T = and(UInt<1>(0h0), mem_reg_btb_resp.taken) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 634:85] node _mem_direction_misprediction_T_1 = neq(mem_br_taken, _mem_direction_misprediction_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 634:69] node mem_direction_misprediction = and(mem_ctrl.branch, _mem_direction_misprediction_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 634:53] node _take_pc_mem_T = eq(mem_reg_xcpt, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 636:35] node _take_pc_mem_T_1 = and(mem_reg_valid, _take_pc_mem_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 636:32] node _take_pc_mem_T_2 = or(mem_cfi_taken, mem_reg_sfence) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 636:71] node _take_pc_mem_T_3 = and(_take_pc_mem_T_1, _take_pc_mem_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 636:49] connect take_pc_mem, _take_pc_mem_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 636:15] node _mem_reg_valid_T = eq(ctrl_killx, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 638:20] connect mem_reg_valid, _mem_reg_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 638:17] node _mem_reg_replay_T = eq(take_pc_mem_wb, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 639:21] node _mem_reg_replay_T_1 = and(_mem_reg_replay_T, replay_ex) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 639:37] connect mem_reg_replay, _mem_reg_replay_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 639:18] node _mem_reg_xcpt_T = eq(ctrl_killx, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 640:19] node _mem_reg_xcpt_T_1 = and(_mem_reg_xcpt_T, ex_xcpt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 640:31] connect mem_reg_xcpt, _mem_reg_xcpt_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 640:16] node _mem_reg_xcpt_interrupt_T = eq(take_pc_mem_wb, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 641:29] node _mem_reg_xcpt_interrupt_T_1 = and(_mem_reg_xcpt_interrupt_T, ex_reg_xcpt_interrupt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 641:45] connect mem_reg_xcpt_interrupt, _mem_reg_xcpt_interrupt_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 641:26] node _T_63 = and(mem_reg_valid, mem_reg_flush_pipe) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 645:23] when _T_63 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 645:46] connect mem_reg_sfence, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 646:20] else : when ex_pc_valid : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 647:28] connect mem_ctrl, ex_ctrl @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 648:14] connect mem_reg_rvc, ex_reg_rvc @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 649:17] node _mem_reg_load_T = eq(ex_ctrl.mem_cmd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_load_T_1 = eq(ex_ctrl.mem_cmd, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_load_T_2 = eq(ex_ctrl.mem_cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_load_T_3 = eq(ex_ctrl.mem_cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_load_T_4 = or(_mem_reg_load_T, _mem_reg_load_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _mem_reg_load_T_5 = or(_mem_reg_load_T_4, _mem_reg_load_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _mem_reg_load_T_6 = or(_mem_reg_load_T_5, _mem_reg_load_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _mem_reg_load_T_7 = eq(ex_ctrl.mem_cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_load_T_8 = eq(ex_ctrl.mem_cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_load_T_9 = eq(ex_ctrl.mem_cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_load_T_10 = eq(ex_ctrl.mem_cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_load_T_11 = or(_mem_reg_load_T_7, _mem_reg_load_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _mem_reg_load_T_12 = or(_mem_reg_load_T_11, _mem_reg_load_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _mem_reg_load_T_13 = or(_mem_reg_load_T_12, _mem_reg_load_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _mem_reg_load_T_14 = eq(ex_ctrl.mem_cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_load_T_15 = eq(ex_ctrl.mem_cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_load_T_16 = eq(ex_ctrl.mem_cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_load_T_17 = eq(ex_ctrl.mem_cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_load_T_18 = eq(ex_ctrl.mem_cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_load_T_19 = or(_mem_reg_load_T_14, _mem_reg_load_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _mem_reg_load_T_20 = or(_mem_reg_load_T_19, _mem_reg_load_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _mem_reg_load_T_21 = or(_mem_reg_load_T_20, _mem_reg_load_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _mem_reg_load_T_22 = or(_mem_reg_load_T_21, _mem_reg_load_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _mem_reg_load_T_23 = or(_mem_reg_load_T_13, _mem_reg_load_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node _mem_reg_load_T_24 = or(_mem_reg_load_T_6, _mem_reg_load_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 89:68] node _mem_reg_load_T_25 = and(ex_ctrl.mem, _mem_reg_load_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 650:33] connect mem_reg_load, _mem_reg_load_T_25 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 650:18] node _mem_reg_store_T = eq(ex_ctrl.mem_cmd, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:32] node _mem_reg_store_T_1 = eq(ex_ctrl.mem_cmd, UInt<5>(0h11)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:49] node _mem_reg_store_T_2 = or(_mem_reg_store_T, _mem_reg_store_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:42] node _mem_reg_store_T_3 = eq(ex_ctrl.mem_cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:66] node _mem_reg_store_T_4 = or(_mem_reg_store_T_2, _mem_reg_store_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:59] node _mem_reg_store_T_5 = eq(ex_ctrl.mem_cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_store_T_6 = eq(ex_ctrl.mem_cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_store_T_7 = eq(ex_ctrl.mem_cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_store_T_8 = eq(ex_ctrl.mem_cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_store_T_9 = or(_mem_reg_store_T_5, _mem_reg_store_T_6) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _mem_reg_store_T_10 = or(_mem_reg_store_T_9, _mem_reg_store_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _mem_reg_store_T_11 = or(_mem_reg_store_T_10, _mem_reg_store_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _mem_reg_store_T_12 = eq(ex_ctrl.mem_cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_store_T_13 = eq(ex_ctrl.mem_cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_store_T_14 = eq(ex_ctrl.mem_cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_store_T_15 = eq(ex_ctrl.mem_cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_store_T_16 = eq(ex_ctrl.mem_cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _mem_reg_store_T_17 = or(_mem_reg_store_T_12, _mem_reg_store_T_13) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _mem_reg_store_T_18 = or(_mem_reg_store_T_17, _mem_reg_store_T_14) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _mem_reg_store_T_19 = or(_mem_reg_store_T_18, _mem_reg_store_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _mem_reg_store_T_20 = or(_mem_reg_store_T_19, _mem_reg_store_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _mem_reg_store_T_21 = or(_mem_reg_store_T_11, _mem_reg_store_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node _mem_reg_store_T_22 = or(_mem_reg_store_T_4, _mem_reg_store_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 90:76] node _mem_reg_store_T_23 = and(ex_ctrl.mem, _mem_reg_store_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 651:34] connect mem_reg_store, _mem_reg_store_T_23 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 651:19] connect mem_reg_sfence, ex_sfence @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 652:20] connect mem_reg_btb_resp, ex_reg_btb_resp @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 653:22] connect mem_reg_flush_pipe, ex_reg_flush_pipe @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 654:24] connect mem_reg_slow_bypass, ex_slow_bypass @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 655:25] connect mem_reg_wphit, ex_reg_wphit @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 656:19] connect mem_reg_set_vconfig, ex_reg_set_vconfig @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 657:25] connect mem_reg_cause, ex_cause @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 659:19] connect mem_reg_inst, ex_reg_inst @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 660:18] connect mem_reg_raw_inst, ex_reg_raw_inst @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 661:22] connect mem_reg_mem_size, ex_reg_mem_size @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 662:22] connect mem_reg_hls_or_dv, io.dmem.req.bits.dv @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 663:23] connect mem_reg_pc, ex_reg_pc @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 664:16] node _mem_reg_wdata_T = mux(ex_reg_set_vconfig, alu.io.out, alu.io.out) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 666:25] connect mem_reg_wdata, _mem_reg_wdata_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 666:19] connect mem_br_taken, alu.io.cmp_out @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 667:18] node _T_64 = or(ex_ctrl.mem, ex_ctrl.rocc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 670:40] node _T_65 = or(_T_64, ex_sfence) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 670:56] node _T_66 = and(ex_ctrl.rxs2, _T_65) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 670:24] when _T_66 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 670:71] node size = mux(ex_ctrl.rocc, UInt<2>(0h3), ex_reg_mem_size) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 671:21] wire mem_reg_rs2_size : UInt<2> @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 11:18] connect mem_reg_rs2_size, size @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 12:8] node mem_reg_rs2_dat_padded = pad(ex_rs_1, 64) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 13:27] node _mem_reg_rs2_T = eq(mem_reg_rs2_size, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 29:19] node _mem_reg_rs2_T_1 = bits(mem_reg_rs2_dat_padded, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 29:69] node _mem_reg_rs2_T_2 = cat(_mem_reg_rs2_T_1, _mem_reg_rs2_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 29:32] node _mem_reg_rs2_T_3 = cat(_mem_reg_rs2_T_2, _mem_reg_rs2_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 29:32] node _mem_reg_rs2_T_4 = cat(_mem_reg_rs2_T_3, _mem_reg_rs2_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 29:32] node _mem_reg_rs2_T_5 = eq(mem_reg_rs2_size, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 29:19] node _mem_reg_rs2_T_6 = bits(mem_reg_rs2_dat_padded, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 29:69] node _mem_reg_rs2_T_7 = cat(_mem_reg_rs2_T_6, _mem_reg_rs2_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 29:32] node _mem_reg_rs2_T_8 = cat(_mem_reg_rs2_T_7, _mem_reg_rs2_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 29:32] node _mem_reg_rs2_T_9 = eq(mem_reg_rs2_size, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 29:19] node _mem_reg_rs2_T_10 = bits(mem_reg_rs2_dat_padded, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 29:69] node _mem_reg_rs2_T_11 = cat(_mem_reg_rs2_T_10, _mem_reg_rs2_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 29:32] node _mem_reg_rs2_T_12 = mux(_mem_reg_rs2_T_9, _mem_reg_rs2_T_11, mem_reg_rs2_dat_padded) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 29:13] node _mem_reg_rs2_T_13 = mux(_mem_reg_rs2_T_5, _mem_reg_rs2_T_8, _mem_reg_rs2_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 29:13] node _mem_reg_rs2_T_14 = mux(_mem_reg_rs2_T, _mem_reg_rs2_T_4, _mem_reg_rs2_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/AMOALU.scala 29:13] connect mem_reg_rs2, _mem_reg_rs2_T_14 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 672:19] node _T_67 = and(ex_ctrl.jalr, csr.io.status.debug) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 677:24] when _T_67 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 677:48] connect mem_ctrl.fence_i, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 679:24] connect mem_reg_flush_pipe, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 680:26] node _mem_breakpoint_T = and(mem_reg_load, bpu.io.xcpt_ld) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 684:38] node _mem_breakpoint_T_1 = and(mem_reg_store, bpu.io.xcpt_st) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 684:75] node mem_breakpoint = or(_mem_breakpoint_T, _mem_breakpoint_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 684:57] node _mem_debug_breakpoint_T = and(mem_reg_load, bpu.io.debug_ld) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 685:44] node _mem_debug_breakpoint_T_1 = and(mem_reg_store, bpu.io.debug_st) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 685:82] node mem_debug_breakpoint = or(_mem_debug_breakpoint_T, _mem_debug_breakpoint_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 685:64] node _T_68 = or(mem_debug_breakpoint, mem_breakpoint) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] wire mem_ldst_xcpt : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:14] connect mem_ldst_xcpt, _T_68 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:14] node _T_69 = mux(mem_debug_breakpoint, UInt<4>(0he), UInt<2>(0h3)) @[src/main/scala/chisel3/util/Mux.scala 50:70] wire mem_ldst_cause : UInt @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:50] connect mem_ldst_cause, _T_69 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:50] node _T_70 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 691:29] node _T_71 = and(mem_reg_valid, mem_npc_misaligned) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 692:20] node _T_72 = and(mem_reg_valid, mem_ldst_xcpt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 693:20] node _T_73 = or(_T_70, _T_71) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] node _T_74 = or(_T_73, _T_72) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] wire mem_xcpt : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:14] connect mem_xcpt, _T_74 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:14] node _T_75 = mux(_T_71, UInt<1>(0h0), mem_ldst_cause) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _T_76 = mux(_T_70, mem_reg_cause, _T_75) @[src/main/scala/chisel3/util/Mux.scala 50:70] wire mem_cause : UInt @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:50] connect mem_cause, _T_76 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:50] node _T_77 = eq(mem_cause, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:47] node _T_78 = and(mem_xcpt, _T_77) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:37] node _T_79 = eq(mem_cause, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:47] node _T_80 = and(mem_xcpt, _T_79) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:37] node _T_81 = eq(mem_cause, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:47] node _T_82 = and(mem_xcpt, _T_81) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:37] node _T_83 = eq(mem_cause, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:47] node _T_84 = and(mem_xcpt, _T_83) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:37] node _T_85 = eq(mem_cause, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:47] node _T_86 = and(mem_xcpt, _T_85) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:37] node _dcache_kill_mem_T = and(mem_reg_valid, mem_ctrl.wxd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 702:39] node dcache_kill_mem = and(_dcache_kill_mem_T, io.dmem.replay_next) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 702:55] node _fpu_kill_mem_T = and(mem_reg_valid, mem_ctrl.fp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 703:36] node fpu_kill_mem = and(_fpu_kill_mem_T, io.fpu.nack_mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 703:51] node _vec_kill_mem_T = and(mem_reg_valid, mem_ctrl.mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 704:36] node vec_kill_mem = and(_vec_kill_mem_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 704:52] node vec_kill_all = and(mem_reg_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 705:36] node _replay_mem_T = or(dcache_kill_mem, mem_reg_replay) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 706:37] node _replay_mem_T_1 = or(_replay_mem_T, fpu_kill_mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 706:55] node _replay_mem_T_2 = or(_replay_mem_T_1, vec_kill_mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 706:71] node replay_mem = or(_replay_mem_T_2, vec_kill_all) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 706:87] node _killm_common_T = or(dcache_kill_mem, take_pc_wb) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 707:38] node _killm_common_T_1 = or(_killm_common_T, mem_reg_xcpt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 707:52] node _killm_common_T_2 = eq(mem_reg_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 707:71] node killm_common = or(_killm_common_T_1, _killm_common_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 707:68] node _div_io_kill_T = and(div.io.req.ready, div.io.req.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] reg div_io_kill_REG : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 708:41] connect div_io_kill_REG, _div_io_kill_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 708:41] node _div_io_kill_T_1 = and(killm_common, div_io_kill_REG) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 708:31] connect div.io.kill, _div_io_kill_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 708:15] node _ctrl_killm_T = or(killm_common, mem_xcpt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 709:33] node _ctrl_killm_T_1 = or(_ctrl_killm_T, fpu_kill_mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 709:45] node ctrl_killm = or(_ctrl_killm_T_1, vec_kill_mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 709:61] node _wb_reg_valid_T = eq(ctrl_killm, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 712:19] connect wb_reg_valid, _wb_reg_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 712:16] node _wb_reg_replay_T = eq(take_pc_wb, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 713:34] node _wb_reg_replay_T_1 = and(replay_mem, _wb_reg_replay_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 713:31] connect wb_reg_replay, _wb_reg_replay_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 713:17] node _wb_reg_xcpt_T = eq(take_pc_wb, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 714:30] node _wb_reg_xcpt_T_1 = and(mem_xcpt, _wb_reg_xcpt_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 714:27] node _wb_reg_xcpt_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 714:45] node _wb_reg_xcpt_T_3 = and(_wb_reg_xcpt_T_1, _wb_reg_xcpt_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 714:42] connect wb_reg_xcpt, _wb_reg_xcpt_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 714:15] node _wb_reg_flush_pipe_T = eq(ctrl_killm, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 715:24] node _wb_reg_flush_pipe_T_1 = and(_wb_reg_flush_pipe_T, mem_reg_flush_pipe) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 715:36] connect wb_reg_flush_pipe, _wb_reg_flush_pipe_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 715:21] when mem_pc_valid : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 716:23] connect wb_ctrl, mem_ctrl @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 717:13] connect wb_reg_sfence, mem_reg_sfence @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 718:19] node _wb_reg_wdata_T = eq(mem_reg_xcpt, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 719:25] node _wb_reg_wdata_T_1 = and(_wb_reg_wdata_T, mem_ctrl.fp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 719:39] node _wb_reg_wdata_T_2 = and(_wb_reg_wdata_T_1, mem_ctrl.wxd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 719:54] node _wb_reg_wdata_T_3 = mux(_wb_reg_wdata_T_2, io.fpu.toint_data, mem_int_wdata) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 719:24] connect wb_reg_wdata, _wb_reg_wdata_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 719:18] node _T_87 = or(mem_ctrl.rocc, mem_reg_sfence) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 720:25] node _T_88 = or(_T_87, mem_reg_set_vconfig) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 720:43] when _T_88 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 720:67] connect wb_reg_rs2, mem_reg_rs2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 721:18] connect wb_reg_cause, mem_cause @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 723:18] connect wb_reg_inst, mem_reg_inst @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 724:17] connect wb_reg_raw_inst, mem_reg_raw_inst @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 725:21] connect wb_reg_mem_size, mem_reg_mem_size @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 726:21] connect wb_reg_hls_or_dv, mem_reg_hls_or_dv @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 727:22] node _wb_reg_hfence_v_T = eq(mem_ctrl.mem_cmd, UInt<5>(0h15)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 728:41] connect wb_reg_hfence_v, _wb_reg_hfence_v_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 728:21] node _wb_reg_hfence_g_T = eq(mem_ctrl.mem_cmd, UInt<5>(0h16)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 729:41] connect wb_reg_hfence_g, _wb_reg_hfence_g_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 729:21] connect wb_reg_pc, mem_reg_pc @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 730:15] connect wb_reg_br_taken, mem_br_taken @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 731:21] node _T_89 = and(bpu.io.bpwatch[0].rvalid[0], mem_reg_load) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 732:80] node _T_90 = and(bpu.io.bpwatch[0].wvalid[0], mem_reg_store) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 732:115] node _T_91 = or(_T_89, _T_90) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 732:97] node _T_92 = or(mem_reg_wphit[0], _T_91) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 76:75] connect wb_reg_wphit[0], _T_92 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 732:18] connect wb_reg_set_vconfig, mem_reg_set_vconfig @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 733:24] node _T_93 = and(wb_reg_valid, wb_ctrl.mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 738:19] node _T_94 = and(_T_93, io.dmem.s2_xcpt.pf.st) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 738:34] node _T_95 = and(wb_reg_valid, wb_ctrl.mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 739:19] node _T_96 = and(_T_95, io.dmem.s2_xcpt.pf.ld) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 739:34] node _T_97 = and(wb_reg_valid, wb_ctrl.mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 740:19] node _T_98 = and(_T_97, io.dmem.s2_xcpt.gf.st) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 740:34] node _T_99 = and(wb_reg_valid, wb_ctrl.mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 741:19] node _T_100 = and(_T_99, io.dmem.s2_xcpt.gf.ld) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 741:34] node _T_101 = and(wb_reg_valid, wb_ctrl.mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 742:19] node _T_102 = and(_T_101, io.dmem.s2_xcpt.ae.st) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 742:34] node _T_103 = and(wb_reg_valid, wb_ctrl.mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 743:19] node _T_104 = and(_T_103, io.dmem.s2_xcpt.ae.ld) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 743:34] node _T_105 = and(wb_reg_valid, wb_ctrl.mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 744:19] node _T_106 = and(_T_105, io.dmem.s2_xcpt.ma.st) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 744:34] node _T_107 = and(wb_reg_valid, wb_ctrl.mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 745:19] node _T_108 = and(_T_107, io.dmem.s2_xcpt.ma.ld) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 745:34] node _T_109 = or(wb_reg_xcpt, _T_94) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] node _T_110 = or(_T_109, _T_96) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] node _T_111 = or(_T_110, _T_98) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] node _T_112 = or(_T_111, _T_100) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] node _T_113 = or(_T_112, _T_102) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] node _T_114 = or(_T_113, _T_104) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] node _T_115 = or(_T_114, _T_106) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] node _T_116 = or(_T_115, _T_108) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:35] wire wb_xcpt : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:14] connect wb_xcpt, _T_116 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:14] node _T_117 = mux(_T_106, UInt<3>(0h6), UInt<3>(0h4)) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _T_118 = mux(_T_104, UInt<3>(0h5), _T_117) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _T_119 = mux(_T_102, UInt<3>(0h7), _T_118) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _T_120 = mux(_T_100, UInt<5>(0h15), _T_119) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _T_121 = mux(_T_98, UInt<5>(0h17), _T_120) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _T_122 = mux(_T_96, UInt<4>(0hd), _T_121) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _T_123 = mux(_T_94, UInt<4>(0hf), _T_122) @[src/main/scala/chisel3/util/Mux.scala 50:70] node _T_124 = mux(wb_reg_xcpt, wb_reg_cause, _T_123) @[src/main/scala/chisel3/util/Mux.scala 50:70] wire wb_cause : UInt @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:50] connect wb_cause, _T_124 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1309:50] node _T_125 = eq(wb_cause, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:47] node _T_126 = and(wb_xcpt, _T_125) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:37] node _T_127 = eq(wb_cause, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:47] node _T_128 = and(wb_xcpt, _T_127) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:37] node _T_129 = eq(wb_cause, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:47] node _T_130 = and(wb_xcpt, _T_129) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:37] node _T_131 = eq(wb_cause, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:47] node _T_132 = and(wb_xcpt, _T_131) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1313:37] node _wb_pc_valid_T = or(wb_reg_valid, wb_reg_replay) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 762:34] node wb_pc_valid = or(_wb_pc_valid_T, wb_reg_xcpt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 762:51] node wb_wxd = and(wb_reg_valid, wb_ctrl.wxd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 763:29] node _wb_set_sboard_T = or(wb_ctrl.div, wb_dcache_miss) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 764:35] node _wb_set_sboard_T_1 = or(_wb_set_sboard_T, wb_ctrl.rocc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 764:53] node wb_set_sboard = or(_wb_set_sboard_T_1, wb_ctrl.vec) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 764:69] node replay_wb_common = or(io.dmem.s2_nack, wb_reg_replay) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 765:42] node _replay_wb_rocc_T = and(wb_reg_valid, wb_ctrl.rocc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 766:37] node _replay_wb_rocc_T_1 = eq(io.rocc.cmd.ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 766:56] node replay_wb_rocc = and(_replay_wb_rocc_T, _replay_wb_rocc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 766:53] node replay_wb_csr = and(wb_reg_valid, csr.io.rw_stall) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 767:42] node replay_wb_vec = and(wb_reg_valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 768:36] node _replay_wb_T = or(replay_wb_common, replay_wb_rocc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 769:36] node _replay_wb_T_1 = or(_replay_wb_T, replay_wb_csr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 769:54] node replay_wb = or(_replay_wb_T_1, replay_wb_vec) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 769:71] node _take_pc_wb_T = or(replay_wb, wb_xcpt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 770:27] node _take_pc_wb_T_1 = or(_take_pc_wb_T, csr.io.eret) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 770:38] node _take_pc_wb_T_2 = or(_take_pc_wb_T_1, wb_reg_flush_pipe) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 770:53] connect take_pc_wb, _take_pc_wb_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 770:14] node _dmem_resp_xpu_T = bits(io.dmem.resp.bits.tag, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 773:45] node dmem_resp_xpu = eq(_dmem_resp_xpu_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 773:23] node dmem_resp_fpu = bits(io.dmem.resp.bits.tag, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 774:45] node dmem_resp_waddr = bits(io.dmem.resp.bits.tag, 5, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 775:46] node dmem_resp_valid = and(io.dmem.resp.valid, io.dmem.resp.bits.has_data) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 776:44] node dmem_resp_replay = and(dmem_resp_valid, io.dmem.resp.bits.replay) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 777:42] inst ll_arb of Arbiter3_LLWB @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 784:22] connect ll_arb.clock, clock connect ll_arb.reset, reset connect ll_arb.io.in[0].valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 785:32] connect ll_arb.io.in[1].valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 785:32] connect ll_arb.io.in[2].valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 785:32] invalidate ll_arb.io.in[0].bits.tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 786:31] invalidate ll_arb.io.in[0].bits.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 786:31] invalidate ll_arb.io.in[1].bits.tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 786:31] invalidate ll_arb.io.in[1].bits.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 786:31] invalidate ll_arb.io.in[2].bits.tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 786:31] invalidate ll_arb.io.in[2].bits.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 786:31] wire ll_wdata : UInt @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 787:26] connect ll_wdata, ll_arb.io.out.bits.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 787:26] wire ll_waddr : UInt @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 788:26] connect ll_waddr, ll_arb.io.out.bits.tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 788:26] node _ll_wen_T = and(ll_arb.io.out.ready, ll_arb.io.out.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire ll_wen : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 789:24] connect ll_wen, _ll_wen_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 789:24] node _ll_arb_io_out_ready_T = eq(wb_wxd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 790:26] connect ll_arb.io.out.ready, _ll_arb_io_out_ready_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 790:23] connect div.io.resp.ready, ll_arb.io.in[0].ready @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 792:21] connect ll_arb.io.in[0].valid, div.io.resp.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 793:25] connect ll_arb.io.in[0].bits.data, div.io.resp.bits.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 794:29] connect ll_arb.io.in[0].bits.tag, div.io.resp.bits.tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 795:28] connect io.rocc.resp.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 804:24] connect io.rocc.mem.req.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 805:27] invalidate io.rocc.mem.clock_enabled @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.keep_clock_enabled @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.perf.storeBufferEmptyAfterStore @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.perf.storeBufferEmptyAfterLoad @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.perf.canAcceptLoadThenLoad @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.perf.canAcceptStoreThenRMW @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.perf.canAcceptStoreThenLoad @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.perf.blocked @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.perf.tlbMiss @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.perf.grant @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.perf.release @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.perf.acquire @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.store_pending @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.ordered @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.s2_gpa_is_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.s2_gpa @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.s2_xcpt.ae.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.s2_xcpt.ae.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.s2_xcpt.gf.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.s2_xcpt.gf.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.s2_xcpt.pf.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.s2_xcpt.pf.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.s2_xcpt.ma.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.s2_xcpt.ma.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.replay_next @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.resp.bits.store_data @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.resp.bits.data_raw @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.resp.bits.data_word_bypass @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.resp.bits.has_data @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.resp.bits.replay @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.resp.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.resp.bits.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.resp.bits.dv @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.resp.bits.dprv @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.resp.bits.signed @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.resp.bits.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.resp.bits.cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.resp.bits.tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.resp.bits.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.resp.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.s2_paddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.s2_uncached @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.s2_kill @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.s2_nack_cause_raw @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.s2_nack @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.s1_data.mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.s1_data.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.s1_kill @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.req.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.req.bits.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.req.bits.no_xcpt @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.req.bits.no_alloc @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.req.bits.no_resp @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.req.bits.phys @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.req.bits.dv @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.req.bits.dprv @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.req.bits.signed @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.req.bits.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.req.bits.cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.req.bits.tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.req.bits.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.req.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] invalidate io.rocc.mem.req.ready @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 815:15] node _T_133 = and(dmem_resp_replay, dmem_resp_xpu) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 817:26] when _T_133 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 817:44] connect ll_arb.io.out.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 818:25] connect ll_waddr, dmem_resp_waddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 819:14] connect ll_wen, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 820:12] node _wb_valid_T = eq(replay_wb, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 823:34] node _wb_valid_T_1 = and(wb_reg_valid, _wb_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 823:31] node _wb_valid_T_2 = eq(wb_xcpt, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 823:48] node wb_valid = and(_wb_valid_T_1, _wb_valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 823:45] node wb_wen = and(wb_valid, wb_ctrl.wxd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 824:25] node rf_wen = or(wb_wen, ll_wen) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 825:23] node rf_waddr = mux(ll_wen, ll_waddr, wb_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 826:21] node _rf_wdata_T = and(dmem_resp_valid, dmem_resp_xpu) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 827:38] node _rf_wdata_T_1 = bits(io.dmem.resp.bits.data, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 827:78] node _rf_wdata_T_2 = neq(wb_ctrl.csr, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 829:34] node _rf_wdata_T_3 = mux(wb_ctrl.mul, wb_reg_wdata, wb_reg_wdata) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 830:21] node _rf_wdata_T_4 = mux(_rf_wdata_T_2, csr.io.rw.rdata, _rf_wdata_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 829:21] node _rf_wdata_T_5 = mux(ll_wen, ll_wdata, _rf_wdata_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 828:21] node rf_wdata = mux(_rf_wdata_T, _rf_wdata_T_1, _rf_wdata_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 827:21] when rf_wen : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 832:17] node _T_134 = neq(rf_waddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1362:16] when _T_134 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1362:25] node _T_135 = bits(rf_waddr, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1351:44] node _T_136 = not(_T_135) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1351:39] infer mport MPORT = rf[_T_136], clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1351:38] connect MPORT, rf_wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1363:20] node _T_137 = eq(rf_waddr, id_raddr1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1365:20] when _T_137 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1365:31] connect id_rs_0, rf_wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1365:39] node _T_138 = eq(rf_waddr, id_raddr2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1365:20] when _T_138 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1365:31] connect id_rs_1, rf_wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1365:39] connect csr.io.ungated_clock, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 857:24] connect csr.io.decode[0].inst, ibuf.io.inst[0].bits.inst.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 858:25] connect csr.io.exception, wb_xcpt @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 859:20] connect csr.io.cause, wb_cause @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 860:16] connect csr.io.retire, wb_valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 861:17] node _csr_io_inst_0_T = bits(wb_reg_raw_inst, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 862:66] node _csr_io_inst_0_T_1 = andr(_csr_io_inst_0_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 862:73] node _csr_io_inst_0_T_2 = shr(wb_reg_inst, 16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 862:91] node _csr_io_inst_0_T_3 = mux(_csr_io_inst_0_T_1, _csr_io_inst_0_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 862:50] node _csr_io_inst_0_T_4 = bits(wb_reg_raw_inst, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 862:119] node _csr_io_inst_0_T_5 = cat(_csr_io_inst_0_T_3, _csr_io_inst_0_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 862:46] connect csr.io.inst[0], _csr_io_inst_0_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 862:18] connect csr.io.interrupts.meip, io.interrupts.meip @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 863:21] connect csr.io.interrupts.msip, io.interrupts.msip @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 863:21] connect csr.io.interrupts.mtip, io.interrupts.mtip @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 863:21] connect csr.io.interrupts.debug, io.interrupts.debug @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 863:21] connect csr.io.hartid, io.hartid @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 864:17] connect io.fpu.fcsr_rm, csr.io.fcsr_rm @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 865:18] node _csr_io_fcsr_flags_valid_T = or(io.fpu.fcsr_flags.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 868:54] connect csr.io.fcsr_flags.valid, _csr_io_fcsr_flags_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 868:27] node _csr_io_fcsr_flags_bits_T = mux(io.fpu.fcsr_flags.valid, UInt<5>(0h1f), UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 869:59] node _csr_io_fcsr_flags_bits_T_1 = and(io.fpu.fcsr_flags.bits, _csr_io_fcsr_flags_bits_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 869:53] node _csr_io_fcsr_flags_bits_T_2 = mux(UInt<1>(0h0), UInt<5>(0h1f), UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 869:116] node _csr_io_fcsr_flags_bits_T_3 = and(UInt<5>(0h0), _csr_io_fcsr_flags_bits_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 869:110] node _csr_io_fcsr_flags_bits_T_4 = or(_csr_io_fcsr_flags_bits_T_1, _csr_io_fcsr_flags_bits_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 869:89] connect csr.io.fcsr_flags.bits, _csr_io_fcsr_flags_bits_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 869:26] node _io_fpu_time_T = bits(csr.io.time, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 870:29] connect io.fpu.time, _io_fpu_time_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 870:15] connect io.fpu.hartid, io.hartid @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 871:17] connect csr.io.rocc_interrupt, io.rocc.interrupt @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 872:25] connect csr.io.pc, wb_reg_pc @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 873:13] node tval_dmem_addr = eq(wb_reg_xcpt, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 875:24] node _tval_any_addr_T = eq(wb_reg_cause, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _tval_any_addr_T_1 = eq(wb_reg_cause, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _tval_any_addr_T_2 = eq(wb_reg_cause, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _tval_any_addr_T_3 = eq(wb_reg_cause, UInt<5>(0h14)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _tval_any_addr_T_4 = or(_tval_any_addr_T, _tval_any_addr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _tval_any_addr_T_5 = or(_tval_any_addr_T_4, _tval_any_addr_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _tval_any_addr_T_6 = or(_tval_any_addr_T_5, _tval_any_addr_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node tval_any_addr = or(tval_dmem_addr, _tval_any_addr_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 876:38] node tval_inst = eq(wb_reg_cause, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 878:32] node _tval_valid_T = or(tval_any_addr, tval_inst) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 879:46] node tval_valid = and(wb_xcpt, _tval_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 879:28] node _csr_io_gva_T = and(tval_any_addr, csr.io.status.v) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 880:43] node _csr_io_gva_T_1 = and(tval_dmem_addr, wb_reg_hls_or_dv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 880:80] node _csr_io_gva_T_2 = or(_csr_io_gva_T, _csr_io_gva_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 880:62] node _csr_io_gva_T_3 = and(wb_xcpt, _csr_io_gva_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 880:25] connect csr.io.gva, _csr_io_gva_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 880:14] node _csr_io_tval_a_T = shr(wb_reg_wdata, 33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1324:17] node csr_io_tval_a = asSInt(_csr_io_tval_a_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1324:23] node _csr_io_tval_msb_T = eq(csr_io_tval_a, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:21] node _csr_io_tval_msb_T_1 = eq(csr_io_tval_a, asSInt(UInt<1>(0h1))) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:34] node _csr_io_tval_msb_T_2 = or(_csr_io_tval_msb_T, _csr_io_tval_msb_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:29] node _csr_io_tval_msb_T_3 = bits(wb_reg_wdata, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:46] node _csr_io_tval_msb_T_4 = bits(wb_reg_wdata, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:54] node _csr_io_tval_msb_T_5 = eq(_csr_io_tval_msb_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:51] node csr_io_tval_msb = mux(_csr_io_tval_msb_T_2, _csr_io_tval_msb_T_3, _csr_io_tval_msb_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:18] node _csr_io_tval_T = bits(wb_reg_wdata, 32, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1326:16] node _csr_io_tval_T_1 = cat(csr_io_tval_msb, _csr_io_tval_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1326:8] node _csr_io_tval_T_2 = mux(tval_valid, _csr_io_tval_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 881:21] connect csr.io.tval, _csr_io_tval_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 881:15] node _htval_valid_imem_T = eq(wb_reg_cause, UInt<5>(0h14)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 883:56] node htval_valid_imem = and(wb_reg_xcpt, _htval_valid_imem_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 883:40] node htval_imem = mux(htval_valid_imem, io.imem.gpa.bits, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 884:25] node _T_139 = eq(htval_valid_imem, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 885:12] node _T_140 = or(_T_139, io.imem.gpa.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 885:30] node _T_141 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 885:11] node _T_142 = eq(_T_141, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 885:11] when _T_142 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 885:11] node _T_143 = eq(_T_140, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 885:11] when _T_143 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 885:11] printf(clock, UInt<1>(0h1), "Assertion failed\n at RocketCore.scala:885 assert(!htval_valid_imem || io.imem.gpa.valid)\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 885:11] assert(clock, _T_140, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 885:11] node _htval_valid_dmem_T = and(wb_xcpt, tval_dmem_addr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 887:36] node _htval_valid_dmem_T_1 = cat(io.dmem.s2_xcpt.gf.ld, io.dmem.s2_xcpt.gf.st) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 887:76] node _htval_valid_dmem_T_2 = orr(_htval_valid_dmem_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 887:83] node _htval_valid_dmem_T_3 = and(_htval_valid_dmem_T, _htval_valid_dmem_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 887:54] node _htval_valid_dmem_T_4 = cat(io.dmem.s2_xcpt.pf.ld, io.dmem.s2_xcpt.pf.st) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 887:110] node _htval_valid_dmem_T_5 = orr(_htval_valid_dmem_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 887:117] node _htval_valid_dmem_T_6 = eq(_htval_valid_dmem_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 887:90] node htval_valid_dmem = and(_htval_valid_dmem_T_3, _htval_valid_dmem_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 887:87] node htval_dmem = mux(htval_valid_dmem, io.dmem.s2_gpa, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 888:25] node _htval_T = or(htval_dmem, htval_imem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 890:29] node htval = shr(_htval_T, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 890:43] node _mhtinst_read_pseudo_T = and(io.imem.gpa_is_pte, htval_valid_imem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 892:51] node _mhtinst_read_pseudo_T_1 = and(io.dmem.s2_gpa_is_pte, htval_valid_dmem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 892:98] node mhtinst_read_pseudo = or(_mhtinst_read_pseudo_T, _mhtinst_read_pseudo_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 892:72] connect csr.io.htval, htval @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 929:16] connect csr.io.mhtinst_read_pseudo, mhtinst_read_pseudo @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 930:30] connect io.ptw.ptbr, csr.io.ptbr @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 931:15] connect io.ptw.hgatp, csr.io.hgatp @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 932:16] connect io.ptw.vsatp, csr.io.vsatp @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 933:16] connect csr.io.customCSRs[0].sdata, io.ptw.customCSRs.csrs[0].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect csr.io.customCSRs[0].set, io.ptw.customCSRs.csrs[0].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect csr.io.customCSRs[0].stall, io.ptw.customCSRs.csrs[0].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect io.ptw.customCSRs.csrs[0].value, csr.io.customCSRs[0].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect io.ptw.customCSRs.csrs[0].wdata, csr.io.customCSRs[0].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect io.ptw.customCSRs.csrs[0].wen, csr.io.customCSRs[0].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect io.ptw.customCSRs.csrs[0].ren, csr.io.customCSRs[0].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect csr.io.customCSRs[1].sdata, io.ptw.customCSRs.csrs[1].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect csr.io.customCSRs[1].set, io.ptw.customCSRs.csrs[1].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect csr.io.customCSRs[1].stall, io.ptw.customCSRs.csrs[1].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect io.ptw.customCSRs.csrs[1].value, csr.io.customCSRs[1].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect io.ptw.customCSRs.csrs[1].wdata, csr.io.customCSRs[1].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect io.ptw.customCSRs.csrs[1].wen, csr.io.customCSRs[1].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect io.ptw.customCSRs.csrs[1].ren, csr.io.customCSRs[1].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect csr.io.customCSRs[2].sdata, io.ptw.customCSRs.csrs[2].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect csr.io.customCSRs[2].set, io.ptw.customCSRs.csrs[2].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect csr.io.customCSRs[2].stall, io.ptw.customCSRs.csrs[2].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect io.ptw.customCSRs.csrs[2].value, csr.io.customCSRs[2].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect io.ptw.customCSRs.csrs[2].wdata, csr.io.customCSRs[2].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect io.ptw.customCSRs.csrs[2].wen, csr.io.customCSRs[2].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect io.ptw.customCSRs.csrs[2].ren, csr.io.customCSRs[2].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect csr.io.customCSRs[3].sdata, io.ptw.customCSRs.csrs[3].sdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect csr.io.customCSRs[3].set, io.ptw.customCSRs.csrs[3].set @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect csr.io.customCSRs[3].stall, io.ptw.customCSRs.csrs[3].stall @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect io.ptw.customCSRs.csrs[3].value, csr.io.customCSRs[3].value @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect io.ptw.customCSRs.csrs[3].wdata, csr.io.customCSRs[3].wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect io.ptw.customCSRs.csrs[3].wen, csr.io.customCSRs[3].wen @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect io.ptw.customCSRs.csrs[3].ren, csr.io.customCSRs[3].ren @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 934:79] connect io.ptw.status, csr.io.status @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 935:17] connect io.ptw.hstatus, csr.io.hstatus @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 936:18] connect io.ptw.gstatus, csr.io.gstatus @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 937:18] connect io.ptw.pmp, csr.io.pmp @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 938:14] node _csr_io_rw_addr_T = bits(wb_reg_inst, 31, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 939:32] connect csr.io.rw.addr, _csr_io_rw_addr_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 939:18] node _csr_io_rw_cmd_T = mux(wb_reg_valid, UInt<1>(0h0), UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 183:15] node _csr_io_rw_cmd_T_1 = not(_csr_io_rw_cmd_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 183:11] node _csr_io_rw_cmd_T_2 = and(wb_ctrl.csr, _csr_io_rw_cmd_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/CSR.scala 183:9] connect csr.io.rw.cmd, _csr_io_rw_cmd_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 940:17] connect csr.io.rw.wdata, wb_reg_wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 941:19] connect io.trace.time, csr.io.time @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 945:17] connect io.trace.insns, csr.io.trace @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 946:18] connect io.trace.insns, csr.io.trace @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 988:20] connect io.bpwatch[0].valid[0], wb_reg_wphit[0] @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 991:20] connect io.bpwatch[0].action, csr.io.bp[0].control.action @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 992:18] connect io.bpwatch[0].rvalid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 994:28] connect io.bpwatch[0].wvalid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 995:28] connect io.bpwatch[0].ivalid[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 996:28] node _hazard_targets_T = neq(id_raddr1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 999:55] node hazard_targets_0_1 = and(id_ctrl.rxs1, _hazard_targets_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 999:42] node _hazard_targets_T_1 = neq(id_raddr2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1000:55] node hazard_targets_1_1 = and(id_ctrl.rxs2, _hazard_targets_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1000:42] node _hazard_targets_T_2 = neq(id_waddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1001:55] node hazard_targets_2_1 = and(id_ctrl.wxd, _hazard_targets_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1001:42] regreset _r : UInt<32>, clock, reset, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1336:29] node _r_T = shr(_r, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1337:35] node r = shl(_r_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1337:40] node _T_144 = dshl(UInt<1>(0h1), ll_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1340:58] node _T_145 = mux(ll_wen, _T_144, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1340:49] node _T_146 = not(_T_145) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1332:64] node _T_147 = and(r, _T_146) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1332:62] node _T_148 = or(UInt<1>(0h0), ll_wen) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1343:17] when _T_148 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1344:18] connect _r, _T_147 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1344:23] node _id_sboard_hazard_T = dshr(r, id_raddr1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1333:35] node _id_sboard_hazard_T_1 = bits(_id_sboard_hazard_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1333:35] node _id_sboard_hazard_T_2 = eq(ll_waddr, id_raddr1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1011:70] node _id_sboard_hazard_T_3 = and(ll_wen, _id_sboard_hazard_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1011:58] node _id_sboard_hazard_T_4 = eq(_id_sboard_hazard_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1014:80] node _id_sboard_hazard_T_5 = and(_id_sboard_hazard_T_1, _id_sboard_hazard_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1014:77] node _id_sboard_hazard_T_6 = and(hazard_targets_0_1, _id_sboard_hazard_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _id_sboard_hazard_T_7 = dshr(r, id_raddr2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1333:35] node _id_sboard_hazard_T_8 = bits(_id_sboard_hazard_T_7, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1333:35] node _id_sboard_hazard_T_9 = eq(ll_waddr, id_raddr2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1011:70] node _id_sboard_hazard_T_10 = and(ll_wen, _id_sboard_hazard_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1011:58] node _id_sboard_hazard_T_11 = eq(_id_sboard_hazard_T_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1014:80] node _id_sboard_hazard_T_12 = and(_id_sboard_hazard_T_8, _id_sboard_hazard_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1014:77] node _id_sboard_hazard_T_13 = and(hazard_targets_1_1, _id_sboard_hazard_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _id_sboard_hazard_T_14 = dshr(r, id_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1333:35] node _id_sboard_hazard_T_15 = bits(_id_sboard_hazard_T_14, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1333:35] node _id_sboard_hazard_T_16 = eq(ll_waddr, id_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1011:70] node _id_sboard_hazard_T_17 = and(ll_wen, _id_sboard_hazard_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1011:58] node _id_sboard_hazard_T_18 = eq(_id_sboard_hazard_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1014:80] node _id_sboard_hazard_T_19 = and(_id_sboard_hazard_T_15, _id_sboard_hazard_T_18) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1014:77] node _id_sboard_hazard_T_20 = and(hazard_targets_2_1, _id_sboard_hazard_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _id_sboard_hazard_T_21 = or(_id_sboard_hazard_T_6, _id_sboard_hazard_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node id_sboard_hazard = or(_id_sboard_hazard_T_21, _id_sboard_hazard_T_20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node _T_149 = and(wb_set_sboard, wb_wen) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1015:28] node _T_150 = dshl(UInt<1>(0h1), wb_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1340:58] node _T_151 = mux(_T_149, _T_150, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1340:49] node _T_152 = or(_T_147, _T_151) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1331:60] node _T_153 = or(_T_148, _T_149) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1343:17] when _T_153 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1344:18] connect _r, _T_152 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1344:23] node _ex_cannot_bypass_T = neq(ex_ctrl.csr, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1018:38] node _ex_cannot_bypass_T_1 = or(_ex_cannot_bypass_T, ex_ctrl.jalr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1018:48] node _ex_cannot_bypass_T_2 = or(_ex_cannot_bypass_T_1, ex_ctrl.mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1018:64] node _ex_cannot_bypass_T_3 = or(_ex_cannot_bypass_T_2, ex_ctrl.mul) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1018:79] node _ex_cannot_bypass_T_4 = or(_ex_cannot_bypass_T_3, ex_ctrl.div) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1018:94] node _ex_cannot_bypass_T_5 = or(_ex_cannot_bypass_T_4, ex_ctrl.fp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1018:109] node _ex_cannot_bypass_T_6 = or(_ex_cannot_bypass_T_5, ex_ctrl.rocc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1018:123] node ex_cannot_bypass = or(_ex_cannot_bypass_T_6, ex_ctrl.vec) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1018:139] node _data_hazard_ex_T = eq(id_raddr1, ex_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1019:70] node _data_hazard_ex_T_1 = and(hazard_targets_0_1, _data_hazard_ex_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _data_hazard_ex_T_2 = eq(id_raddr2, ex_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1019:70] node _data_hazard_ex_T_3 = and(hazard_targets_1_1, _data_hazard_ex_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _data_hazard_ex_T_4 = eq(id_waddr, ex_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1019:70] node _data_hazard_ex_T_5 = and(hazard_targets_2_1, _data_hazard_ex_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _data_hazard_ex_T_6 = or(_data_hazard_ex_T_1, _data_hazard_ex_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node _data_hazard_ex_T_7 = or(_data_hazard_ex_T_6, _data_hazard_ex_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node data_hazard_ex = and(ex_ctrl.wxd, _data_hazard_ex_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1019:36] node _fp_data_hazard_ex_T = and(id_ctrl.fp, ex_ctrl.wfd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1020:38] node _fp_data_hazard_ex_T_1 = eq(id_raddr1, ex_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1020:90] node _fp_data_hazard_ex_T_2 = and(io.fpu.dec.ren1, _fp_data_hazard_ex_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _fp_data_hazard_ex_T_3 = eq(id_raddr2, ex_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1020:90] node _fp_data_hazard_ex_T_4 = and(io.fpu.dec.ren2, _fp_data_hazard_ex_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _fp_data_hazard_ex_T_5 = eq(id_raddr3, ex_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1020:90] node _fp_data_hazard_ex_T_6 = and(io.fpu.dec.ren3, _fp_data_hazard_ex_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _fp_data_hazard_ex_T_7 = eq(id_waddr, ex_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1020:90] node _fp_data_hazard_ex_T_8 = and(io.fpu.dec.wen, _fp_data_hazard_ex_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _fp_data_hazard_ex_T_9 = or(_fp_data_hazard_ex_T_2, _fp_data_hazard_ex_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node _fp_data_hazard_ex_T_10 = or(_fp_data_hazard_ex_T_9, _fp_data_hazard_ex_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node _fp_data_hazard_ex_T_11 = or(_fp_data_hazard_ex_T_10, _fp_data_hazard_ex_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node fp_data_hazard_ex = and(_fp_data_hazard_ex_T, _fp_data_hazard_ex_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1020:53] node _id_ex_hazard_T = and(data_hazard_ex, ex_cannot_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1021:54] node _id_ex_hazard_T_1 = or(_id_ex_hazard_T, fp_data_hazard_ex) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1021:74] node id_ex_hazard = and(ex_reg_valid, _id_ex_hazard_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1021:35] node mem_mem_cmd_bh = and(UInt<1>(0h1), mem_reg_slow_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1025:41] node _mem_cannot_bypass_T = neq(mem_ctrl.csr, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1027:40] node _mem_cannot_bypass_T_1 = and(mem_ctrl.mem, mem_mem_cmd_bh) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1027:66] node _mem_cannot_bypass_T_2 = or(_mem_cannot_bypass_T, _mem_cannot_bypass_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1027:50] node _mem_cannot_bypass_T_3 = or(_mem_cannot_bypass_T_2, mem_ctrl.mul) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1027:84] node _mem_cannot_bypass_T_4 = or(_mem_cannot_bypass_T_3, mem_ctrl.div) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1027:100] node _mem_cannot_bypass_T_5 = or(_mem_cannot_bypass_T_4, mem_ctrl.fp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1027:116] node _mem_cannot_bypass_T_6 = or(_mem_cannot_bypass_T_5, mem_ctrl.rocc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1027:131] node mem_cannot_bypass = or(_mem_cannot_bypass_T_6, mem_ctrl.vec) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1027:148] node _data_hazard_mem_T = eq(id_raddr1, mem_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1028:72] node _data_hazard_mem_T_1 = and(hazard_targets_0_1, _data_hazard_mem_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _data_hazard_mem_T_2 = eq(id_raddr2, mem_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1028:72] node _data_hazard_mem_T_3 = and(hazard_targets_1_1, _data_hazard_mem_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _data_hazard_mem_T_4 = eq(id_waddr, mem_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1028:72] node _data_hazard_mem_T_5 = and(hazard_targets_2_1, _data_hazard_mem_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _data_hazard_mem_T_6 = or(_data_hazard_mem_T_1, _data_hazard_mem_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node _data_hazard_mem_T_7 = or(_data_hazard_mem_T_6, _data_hazard_mem_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node data_hazard_mem = and(mem_ctrl.wxd, _data_hazard_mem_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1028:38] node _fp_data_hazard_mem_T = and(id_ctrl.fp, mem_ctrl.wfd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1029:39] node _fp_data_hazard_mem_T_1 = eq(id_raddr1, mem_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1029:92] node _fp_data_hazard_mem_T_2 = and(io.fpu.dec.ren1, _fp_data_hazard_mem_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _fp_data_hazard_mem_T_3 = eq(id_raddr2, mem_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1029:92] node _fp_data_hazard_mem_T_4 = and(io.fpu.dec.ren2, _fp_data_hazard_mem_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _fp_data_hazard_mem_T_5 = eq(id_raddr3, mem_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1029:92] node _fp_data_hazard_mem_T_6 = and(io.fpu.dec.ren3, _fp_data_hazard_mem_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _fp_data_hazard_mem_T_7 = eq(id_waddr, mem_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1029:92] node _fp_data_hazard_mem_T_8 = and(io.fpu.dec.wen, _fp_data_hazard_mem_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _fp_data_hazard_mem_T_9 = or(_fp_data_hazard_mem_T_2, _fp_data_hazard_mem_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node _fp_data_hazard_mem_T_10 = or(_fp_data_hazard_mem_T_9, _fp_data_hazard_mem_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node _fp_data_hazard_mem_T_11 = or(_fp_data_hazard_mem_T_10, _fp_data_hazard_mem_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node fp_data_hazard_mem = and(_fp_data_hazard_mem_T, _fp_data_hazard_mem_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1029:55] node _id_mem_hazard_T = and(data_hazard_mem, mem_cannot_bypass) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1030:57] node _id_mem_hazard_T_1 = or(_id_mem_hazard_T, fp_data_hazard_mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1030:78] node id_mem_hazard = and(mem_reg_valid, _id_mem_hazard_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1030:37] node _id_load_use_T = and(mem_reg_valid, data_hazard_mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1031:32] node _id_load_use_T_1 = and(_id_load_use_T, mem_ctrl.mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1031:51] connect id_load_use, _id_load_use_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1031:15] node _id_vconfig_hazard_T = and(ex_reg_valid, ex_reg_set_vconfig) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1033:19] node _id_vconfig_hazard_T_1 = and(mem_reg_valid, mem_reg_set_vconfig) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1034:20] node _id_vconfig_hazard_T_2 = or(_id_vconfig_hazard_T, _id_vconfig_hazard_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1033:42] node _id_vconfig_hazard_T_3 = and(wb_reg_valid, wb_reg_set_vconfig) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1035:19] node _id_vconfig_hazard_T_4 = or(_id_vconfig_hazard_T_2, _id_vconfig_hazard_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1034:44] node id_vconfig_hazard = and(id_ctrl.vec, _id_vconfig_hazard_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1032:39] node _data_hazard_wb_T = eq(id_raddr1, wb_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1038:70] node _data_hazard_wb_T_1 = and(hazard_targets_0_1, _data_hazard_wb_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _data_hazard_wb_T_2 = eq(id_raddr2, wb_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1038:70] node _data_hazard_wb_T_3 = and(hazard_targets_1_1, _data_hazard_wb_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _data_hazard_wb_T_4 = eq(id_waddr, wb_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1038:70] node _data_hazard_wb_T_5 = and(hazard_targets_2_1, _data_hazard_wb_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _data_hazard_wb_T_6 = or(_data_hazard_wb_T_1, _data_hazard_wb_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node _data_hazard_wb_T_7 = or(_data_hazard_wb_T_6, _data_hazard_wb_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node data_hazard_wb = and(wb_ctrl.wxd, _data_hazard_wb_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1038:36] node _fp_data_hazard_wb_T = and(id_ctrl.fp, wb_ctrl.wfd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1039:38] node _fp_data_hazard_wb_T_1 = eq(id_raddr1, wb_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1039:90] node _fp_data_hazard_wb_T_2 = and(io.fpu.dec.ren1, _fp_data_hazard_wb_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _fp_data_hazard_wb_T_3 = eq(id_raddr2, wb_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1039:90] node _fp_data_hazard_wb_T_4 = and(io.fpu.dec.ren2, _fp_data_hazard_wb_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _fp_data_hazard_wb_T_5 = eq(id_raddr3, wb_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1039:90] node _fp_data_hazard_wb_T_6 = and(io.fpu.dec.ren3, _fp_data_hazard_wb_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _fp_data_hazard_wb_T_7 = eq(id_waddr, wb_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1039:90] node _fp_data_hazard_wb_T_8 = and(io.fpu.dec.wen, _fp_data_hazard_wb_T_7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _fp_data_hazard_wb_T_9 = or(_fp_data_hazard_wb_T_2, _fp_data_hazard_wb_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node _fp_data_hazard_wb_T_10 = or(_fp_data_hazard_wb_T_9, _fp_data_hazard_wb_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node _fp_data_hazard_wb_T_11 = or(_fp_data_hazard_wb_T_10, _fp_data_hazard_wb_T_8) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node fp_data_hazard_wb = and(_fp_data_hazard_wb_T, _fp_data_hazard_wb_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1039:53] node _id_wb_hazard_T = and(data_hazard_wb, wb_set_sboard) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1040:54] node _id_wb_hazard_T_1 = or(_id_wb_hazard_T, fp_data_hazard_wb) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1040:71] node id_wb_hazard = and(wb_reg_valid, _id_wb_hazard_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1040:35] regreset _id_stall_fpu_r : UInt<32>, clock, reset, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1336:29] node _id_stall_fpu_T = or(wb_dcache_miss, wb_ctrl.vec) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1044:36] node _id_stall_fpu_T_1 = and(_id_stall_fpu_T, wb_ctrl.wfd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1044:52] node _id_stall_fpu_T_2 = or(_id_stall_fpu_T_1, io.fpu.sboard_set) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1044:67] node _id_stall_fpu_T_3 = and(_id_stall_fpu_T_2, wb_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1044:89] node _id_stall_fpu_T_4 = dshl(UInt<1>(0h1), wb_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1340:58] node _id_stall_fpu_T_5 = mux(_id_stall_fpu_T_3, _id_stall_fpu_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1340:49] node _id_stall_fpu_T_6 = or(_id_stall_fpu_r, _id_stall_fpu_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1331:60] node _id_stall_fpu_T_7 = or(UInt<1>(0h0), _id_stall_fpu_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1343:17] when _id_stall_fpu_T_7 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1344:18] connect _id_stall_fpu_r, _id_stall_fpu_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1344:23] node _id_stall_fpu_T_8 = and(dmem_resp_replay, dmem_resp_fpu) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1046:39] node _id_stall_fpu_T_9 = or(_id_stall_fpu_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1046:57] node _id_stall_fpu_T_10 = dshl(UInt<1>(0h1), io.fpu.ll_resp_tag) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1340:58] node _id_stall_fpu_T_11 = mux(_id_stall_fpu_T_9, _id_stall_fpu_T_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1340:49] node _id_stall_fpu_T_12 = not(_id_stall_fpu_T_11) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1332:64] node _id_stall_fpu_T_13 = and(_id_stall_fpu_T_6, _id_stall_fpu_T_12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1332:62] node _id_stall_fpu_T_14 = or(_id_stall_fpu_T_7, _id_stall_fpu_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1343:17] when _id_stall_fpu_T_14 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1344:18] connect _id_stall_fpu_r, _id_stall_fpu_T_13 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1344:23] node _id_stall_fpu_T_15 = dshl(UInt<1>(0h1), io.fpu.sboard_clra) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1340:58] node _id_stall_fpu_T_16 = mux(io.fpu.sboard_clr, _id_stall_fpu_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1340:49] node _id_stall_fpu_T_17 = not(_id_stall_fpu_T_16) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1332:64] node _id_stall_fpu_T_18 = and(_id_stall_fpu_T_13, _id_stall_fpu_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1332:62] node _id_stall_fpu_T_19 = or(_id_stall_fpu_T_14, io.fpu.sboard_clr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1343:17] when _id_stall_fpu_T_19 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1344:18] connect _id_stall_fpu_r, _id_stall_fpu_T_18 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1344:23] node _id_stall_fpu_T_20 = dshr(_id_stall_fpu_r, id_raddr1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1333:35] node _id_stall_fpu_T_21 = bits(_id_stall_fpu_T_20, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1333:35] node _id_stall_fpu_T_22 = and(io.fpu.dec.ren1, _id_stall_fpu_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _id_stall_fpu_T_23 = dshr(_id_stall_fpu_r, id_raddr2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1333:35] node _id_stall_fpu_T_24 = bits(_id_stall_fpu_T_23, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1333:35] node _id_stall_fpu_T_25 = and(io.fpu.dec.ren2, _id_stall_fpu_T_24) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _id_stall_fpu_T_26 = dshr(_id_stall_fpu_r, id_raddr3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1333:35] node _id_stall_fpu_T_27 = bits(_id_stall_fpu_T_26, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1333:35] node _id_stall_fpu_T_28 = and(io.fpu.dec.ren3, _id_stall_fpu_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _id_stall_fpu_T_29 = dshr(_id_stall_fpu_r, id_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1333:35] node _id_stall_fpu_T_30 = bits(_id_stall_fpu_T_29, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1333:35] node _id_stall_fpu_T_31 = and(io.fpu.dec.wen, _id_stall_fpu_T_30) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:27] node _id_stall_fpu_T_32 = or(_id_stall_fpu_T_22, _id_stall_fpu_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node _id_stall_fpu_T_33 = or(_id_stall_fpu_T_32, _id_stall_fpu_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] node id_stall_fpu = or(_id_stall_fpu_T_33, _id_stall_fpu_T_31) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1318:50] reg dcache_blocked_blocked : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1054:22] node _dcache_blocked_blocked_T = eq(io.dmem.req.ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1055:16] node _dcache_blocked_blocked_T_1 = and(_dcache_blocked_blocked_T, io.dmem.clock_enabled) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1055:35] node _dcache_blocked_blocked_T_2 = eq(io.dmem.perf.grant, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1055:63] node _dcache_blocked_blocked_T_3 = and(_dcache_blocked_blocked_T_1, _dcache_blocked_blocked_T_2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1055:60] node _dcache_blocked_blocked_T_4 = or(dcache_blocked_blocked, io.dmem.req.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1055:95] node _dcache_blocked_blocked_T_5 = or(_dcache_blocked_blocked_T_4, io.dmem.s2_nack) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1055:116] node _dcache_blocked_blocked_T_6 = and(_dcache_blocked_blocked_T_3, _dcache_blocked_blocked_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1055:83] connect dcache_blocked_blocked, _dcache_blocked_blocked_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1055:13] node _dcache_blocked_T = eq(io.dmem.perf.grant, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1056:16] node dcache_blocked = and(dcache_blocked_blocked, _dcache_blocked_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1056:13] reg rocc_blocked : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1058:25] node _rocc_blocked_T = eq(wb_xcpt, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1059:19] node _rocc_blocked_T_1 = eq(io.rocc.cmd.ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1059:31] node _rocc_blocked_T_2 = and(_rocc_blocked_T, _rocc_blocked_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1059:28] node _rocc_blocked_T_3 = or(io.rocc.cmd.valid, rocc_blocked) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1059:72] node _rocc_blocked_T_4 = and(_rocc_blocked_T_2, _rocc_blocked_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1059:50] connect rocc_blocked, _rocc_blocked_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1059:16] node _ctrl_stalld_T = or(id_ex_hazard, id_mem_hazard) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1062:18] node _ctrl_stalld_T_1 = or(_ctrl_stalld_T, id_wb_hazard) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1062:35] node _ctrl_stalld_T_2 = or(_ctrl_stalld_T_1, id_sboard_hazard) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1062:51] node _ctrl_stalld_T_3 = or(_ctrl_stalld_T_2, id_vconfig_hazard) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1062:71] node _ctrl_stalld_T_4 = or(ex_reg_valid, mem_reg_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1064:40] node _ctrl_stalld_T_5 = or(_ctrl_stalld_T_4, wb_reg_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1064:57] node _ctrl_stalld_T_6 = and(csr.io.singleStep, _ctrl_stalld_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1064:23] node _ctrl_stalld_T_7 = or(_ctrl_stalld_T_3, _ctrl_stalld_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1063:23] node _ctrl_stalld_T_8 = and(id_csr_en, csr.io.decode[0].fp_csr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1065:15] node _ctrl_stalld_T_9 = eq(io.fpu.fcsr_rdy, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1065:45] node _ctrl_stalld_T_10 = and(_ctrl_stalld_T_8, _ctrl_stalld_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1065:42] node _ctrl_stalld_T_11 = or(_ctrl_stalld_T_7, _ctrl_stalld_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1064:74] node _ctrl_stalld_T_12 = and(id_csr_en, csr.io.decode[0].vector_csr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1066:15] node _ctrl_stalld_T_13 = and(_ctrl_stalld_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1066:46] node _ctrl_stalld_T_14 = or(_ctrl_stalld_T_11, _ctrl_stalld_T_13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1065:62] node _ctrl_stalld_T_15 = and(id_ctrl.fp, id_stall_fpu) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1067:16] node _ctrl_stalld_T_16 = or(_ctrl_stalld_T_14, _ctrl_stalld_T_15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1066:61] node _ctrl_stalld_T_17 = and(id_ctrl.mem, dcache_blocked) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1068:17] node _ctrl_stalld_T_18 = or(_ctrl_stalld_T_16, _ctrl_stalld_T_17) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1067:32] node _ctrl_stalld_T_19 = and(id_ctrl.rocc, rocc_blocked) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1069:18] node _ctrl_stalld_T_20 = or(_ctrl_stalld_T_18, _ctrl_stalld_T_19) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1068:35] node _ctrl_stalld_T_21 = eq(wb_wxd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1070:65] node _ctrl_stalld_T_22 = and(div.io.resp.valid, _ctrl_stalld_T_21) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1070:62] node _ctrl_stalld_T_23 = or(div.io.req.ready, _ctrl_stalld_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1070:40] node _ctrl_stalld_T_24 = eq(_ctrl_stalld_T_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1070:21] node _ctrl_stalld_T_25 = or(_ctrl_stalld_T_24, div.io.req.valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1070:75] node _ctrl_stalld_T_26 = and(id_ctrl.div, _ctrl_stalld_T_25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1070:17] node _ctrl_stalld_T_27 = or(_ctrl_stalld_T_20, _ctrl_stalld_T_26) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1069:34] node _ctrl_stalld_T_28 = eq(clock_en, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1071:5] node _ctrl_stalld_T_29 = or(_ctrl_stalld_T_27, _ctrl_stalld_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1070:96] node _ctrl_stalld_T_30 = or(_ctrl_stalld_T_29, id_do_fence) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1071:15] node _ctrl_stalld_T_31 = or(_ctrl_stalld_T_30, csr.io.csr_stall) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1072:17] node _ctrl_stalld_T_32 = or(_ctrl_stalld_T_31, id_reg_pause) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1073:22] node ctrl_stalld = or(_ctrl_stalld_T_32, io.traceStall) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1074:18] node _ctrl_killd_T = eq(ibuf.io.inst[0].valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1076:17] node _ctrl_killd_T_1 = or(_ctrl_killd_T, ibuf.io.inst[0].bits.replay) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1076:40] node _ctrl_killd_T_2 = or(_ctrl_killd_T_1, take_pc_mem_wb) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1076:71] node _ctrl_killd_T_3 = or(_ctrl_killd_T_2, ctrl_stalld) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1076:89] node _ctrl_killd_T_4 = or(_ctrl_killd_T_3, csr.io.interrupt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1076:104] connect ctrl_killd, _ctrl_killd_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1076:14] connect io.imem.req.valid, take_pc_mem_wb @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1078:21] node _io_imem_req_bits_speculative_T = eq(take_pc_wb, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1079:35] connect io.imem.req.bits.speculative, _io_imem_req_bits_speculative_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1079:32] node _io_imem_req_bits_pc_T = or(wb_xcpt, csr.io.eret) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1081:17] node _io_imem_req_bits_pc_T_1 = mux(replay_wb, wb_reg_pc, mem_npc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1082:8] node _io_imem_req_bits_pc_T_2 = mux(_io_imem_req_bits_pc_T, csr.io.evec, _io_imem_req_bits_pc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1081:8] connect io.imem.req.bits.pc, _io_imem_req_bits_pc_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1080:23] node _io_imem_flush_icache_T = and(wb_reg_valid, wb_ctrl.fence_i) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1084:40] node _io_imem_flush_icache_T_1 = eq(io.dmem.s2_nack, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1084:62] node _io_imem_flush_icache_T_2 = and(_io_imem_flush_icache_T, _io_imem_flush_icache_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1084:59] connect io.imem.flush_icache, _io_imem_flush_icache_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1084:24] node _io_imem_might_request_imem_might_request_reg_T = or(ex_pc_valid, mem_pc_valid) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1086:43] node _io_imem_might_request_imem_might_request_reg_T_1 = bits(io.ptw.customCSRs.csrs[0].value, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tile/CustomCSRs.scala 44:61] node _io_imem_might_request_imem_might_request_reg_T_2 = or(_io_imem_might_request_imem_might_request_reg_T, _io_imem_might_request_imem_might_request_reg_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1086:59] node _io_imem_might_request_imem_might_request_reg_T_3 = or(_io_imem_might_request_imem_might_request_reg_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1086:103] connect imem_might_request_reg, _io_imem_might_request_imem_might_request_reg_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1086:28] connect io.imem.might_request, imem_might_request_reg @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1085:25] node _io_imem_progress_T = eq(replay_wb_common, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1089:47] node _io_imem_progress_T_1 = and(wb_reg_valid, _io_imem_progress_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1089:44] reg io_imem_progress_REG : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1089:30] connect io_imem_progress_REG, _io_imem_progress_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1089:30] connect io.imem.progress, io_imem_progress_REG @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1089:20] node _io_imem_sfence_valid_T = and(wb_reg_valid, wb_reg_sfence) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1090:40] connect io.imem.sfence.valid, _io_imem_sfence_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1090:24] node _io_imem_sfence_bits_rs1_T = bits(wb_reg_mem_size, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1091:45] connect io.imem.sfence.bits.rs1, _io_imem_sfence_bits_rs1_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1091:27] node _io_imem_sfence_bits_rs2_T = bits(wb_reg_mem_size, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1092:45] connect io.imem.sfence.bits.rs2, _io_imem_sfence_bits_rs2_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1092:27] connect io.imem.sfence.bits.addr, wb_reg_wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1093:28] connect io.imem.sfence.bits.asid, wb_reg_rs2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1094:28] connect io.imem.sfence.bits.hv, wb_reg_hfence_v @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1095:26] connect io.imem.sfence.bits.hg, wb_reg_hfence_g @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1096:26] connect io.ptw.sfence.bits.hg, io.imem.sfence.bits.hg @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1097:17] connect io.ptw.sfence.bits.hv, io.imem.sfence.bits.hv @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1097:17] connect io.ptw.sfence.bits.asid, io.imem.sfence.bits.asid @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1097:17] connect io.ptw.sfence.bits.addr, io.imem.sfence.bits.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1097:17] connect io.ptw.sfence.bits.rs2, io.imem.sfence.bits.rs2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1097:17] connect io.ptw.sfence.bits.rs1, io.imem.sfence.bits.rs1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1097:17] connect io.ptw.sfence.valid, io.imem.sfence.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1097:17] node _ibuf_io_inst_0_ready_T = eq(ctrl_stalld, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1099:28] connect ibuf.io.inst[0].ready, _ibuf_io_inst_0_ready_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1099:25] node _io_imem_btb_update_valid_T = eq(take_pc_wb, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1101:48] node _io_imem_btb_update_valid_T_1 = and(mem_reg_valid, _io_imem_btb_update_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1101:45] node _io_imem_btb_update_valid_T_2 = and(_io_imem_btb_update_valid_T_1, mem_wrong_npc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1101:60] node _io_imem_btb_update_valid_T_3 = eq(mem_cfi, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1101:81] node _io_imem_btb_update_valid_T_4 = or(_io_imem_btb_update_valid_T_3, mem_cfi_taken) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1101:90] node _io_imem_btb_update_valid_T_5 = and(_io_imem_btb_update_valid_T_2, _io_imem_btb_update_valid_T_4) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1101:77] connect io.imem.btb_update.valid, _io_imem_btb_update_valid_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1101:28] connect io.imem.btb_update.bits.isValid, mem_cfi @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1102:35] node _io_imem_btb_update_bits_cfiType_T = or(mem_ctrl.jal, mem_ctrl.jalr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1104:23] node _io_imem_btb_update_bits_cfiType_T_1 = bits(mem_waddr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1104:53] node _io_imem_btb_update_bits_cfiType_T_2 = and(_io_imem_btb_update_bits_cfiType_T, _io_imem_btb_update_bits_cfiType_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1104:41] node _io_imem_btb_update_bits_cfiType_T_3 = bits(mem_reg_inst, 19, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1105:39] node _io_imem_btb_update_bits_cfiType_T_4 = and(_io_imem_btb_update_bits_cfiType_T_3, UInt<5>(0h1f)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1105:47] node _io_imem_btb_update_bits_cfiType_T_5 = and(_io_imem_btb_update_bits_cfiType_T_4, UInt<5>(0h1b)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1105:64] node _io_imem_btb_update_bits_cfiType_T_6 = eq(UInt<1>(0h1), _io_imem_btb_update_bits_cfiType_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1105:64] node _io_imem_btb_update_bits_cfiType_T_7 = and(mem_ctrl.jalr, _io_imem_btb_update_bits_cfiType_T_6) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1105:23] node _io_imem_btb_update_bits_cfiType_T_8 = or(mem_ctrl.jal, mem_ctrl.jalr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1106:22] node _io_imem_btb_update_bits_cfiType_T_9 = mux(_io_imem_btb_update_bits_cfiType_T_8, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1106:8] node _io_imem_btb_update_bits_cfiType_T_10 = mux(_io_imem_btb_update_bits_cfiType_T_7, UInt<2>(0h3), _io_imem_btb_update_bits_cfiType_T_9) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1105:8] node _io_imem_btb_update_bits_cfiType_T_11 = mux(_io_imem_btb_update_bits_cfiType_T_2, UInt<2>(0h2), _io_imem_btb_update_bits_cfiType_T_10) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1104:8] connect io.imem.btb_update.bits.cfiType, _io_imem_btb_update_bits_cfiType_T_11 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1103:35] connect io.imem.btb_update.bits.target, io.imem.req.bits.pc @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1108:34] node _io_imem_btb_update_bits_br_pc_T = mux(mem_reg_rvc, UInt<1>(0h0), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1109:74] node _io_imem_btb_update_bits_br_pc_T_1 = add(mem_reg_pc, _io_imem_btb_update_bits_br_pc_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1109:69] node _io_imem_btb_update_bits_br_pc_T_2 = tail(_io_imem_btb_update_bits_br_pc_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1109:69] connect io.imem.btb_update.bits.br_pc, _io_imem_btb_update_bits_br_pc_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1109:33] node _io_imem_btb_update_bits_pc_T = not(io.imem.btb_update.bits.br_pc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1110:35] node _io_imem_btb_update_bits_pc_T_1 = or(_io_imem_btb_update_bits_pc_T, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1110:66] node _io_imem_btb_update_bits_pc_T_2 = not(_io_imem_btb_update_bits_pc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1110:33] connect io.imem.btb_update.bits.pc, _io_imem_btb_update_bits_pc_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1110:30] connect io.imem.btb_update.bits.prediction, mem_reg_btb_resp @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1111:38] invalidate io.imem.btb_update.bits.taken @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1112:33] node _io_imem_bht_update_valid_T = eq(take_pc_wb, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1114:48] node _io_imem_bht_update_valid_T_1 = and(mem_reg_valid, _io_imem_bht_update_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1114:45] connect io.imem.bht_update.valid, _io_imem_bht_update_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1114:28] connect io.imem.bht_update.bits.pc, io.imem.btb_update.bits.pc @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1115:30] connect io.imem.bht_update.bits.taken, mem_br_taken @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1116:33] connect io.imem.bht_update.bits.mispredict, mem_wrong_npc @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1117:38] connect io.imem.bht_update.bits.branch, mem_ctrl.branch @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1118:34] connect io.imem.bht_update.bits.prediction, mem_reg_btb_resp.bht @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1119:38] invalidate io.imem.ras_update.bits.returnAddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1122:22] invalidate io.imem.ras_update.bits.cfiType @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1122:22] invalidate io.imem.ras_update.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1122:22] node _io_fpu_valid_T = eq(ctrl_killd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1124:19] node _io_fpu_valid_T_1 = and(_io_fpu_valid_T, id_ctrl.fp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1124:31] connect io.fpu.valid, _io_fpu_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1124:16] connect io.fpu.killx, ctrl_killx @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1125:16] node _io_fpu_killm_T = or(killm_common, vec_kill_mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1126:32] connect io.fpu.killm, _io_fpu_killm_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1126:16] connect io.fpu.inst, ibuf.io.inst[0].bits.inst.bits @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1127:15] connect io.fpu.fromint_data, ex_rs_0 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1128:23] node _io_fpu_ll_resp_val_T = and(dmem_resp_valid, dmem_resp_fpu) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1129:41] connect io.fpu.ll_resp_val, _io_fpu_ll_resp_val_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1129:22] connect io.fpu.ll_resp_data, io.dmem.resp.bits.data_word_bypass @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1130:23] connect io.fpu.ll_resp_type, io.dmem.resp.bits.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1131:23] connect io.fpu.ll_resp_tag, dmem_resp_waddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1132:22] node _io_fpu_keep_clock_enabled_T = bits(io.ptw.customCSRs.csrs[0].value, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tile/CustomCSRs.scala 45:59] connect io.fpu.keep_clock_enabled, _io_fpu_keep_clock_enabled_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1133:29] connect io.fpu.v_sew, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1135:16] node _io_dmem_req_valid_T = and(ex_reg_valid, ex_ctrl.mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1160:41] connect io.dmem.req.valid, _io_dmem_req_valid_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1160:25] node ex_dcache_tag = cat(ex_waddr, ex_ctrl.fp) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1161:26] connect io.dmem.req.bits.tag, ex_dcache_tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1163:25] connect io.dmem.req.bits.cmd, ex_ctrl.mem_cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1164:25] connect io.dmem.req.bits.size, ex_reg_mem_size @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1165:25] node _io_dmem_req_bits_signed_T = bits(ex_reg_inst, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1166:58] node _io_dmem_req_bits_signed_T_1 = bits(ex_reg_inst, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1166:75] node _io_dmem_req_bits_signed_T_2 = mux(ex_reg_hls, _io_dmem_req_bits_signed_T, _io_dmem_req_bits_signed_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1166:34] node _io_dmem_req_bits_signed_T_3 = eq(_io_dmem_req_bits_signed_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1166:30] connect io.dmem.req.bits.signed, _io_dmem_req_bits_signed_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1166:27] connect io.dmem.req.bits.phys, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1167:25] node _io_dmem_req_bits_addr_a_T = shr(ex_rs_0, 33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1324:17] node io_dmem_req_bits_addr_a = asSInt(_io_dmem_req_bits_addr_a_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1324:23] node _io_dmem_req_bits_addr_msb_T = eq(io_dmem_req_bits_addr_a, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:21] node _io_dmem_req_bits_addr_msb_T_1 = eq(io_dmem_req_bits_addr_a, asSInt(UInt<1>(0h1))) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:34] node _io_dmem_req_bits_addr_msb_T_2 = or(_io_dmem_req_bits_addr_msb_T, _io_dmem_req_bits_addr_msb_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:29] node _io_dmem_req_bits_addr_msb_T_3 = bits(alu.io.adder_out, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:46] node _io_dmem_req_bits_addr_msb_T_4 = bits(alu.io.adder_out, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:54] node _io_dmem_req_bits_addr_msb_T_5 = eq(_io_dmem_req_bits_addr_msb_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:51] node io_dmem_req_bits_addr_msb = mux(_io_dmem_req_bits_addr_msb_T_2, _io_dmem_req_bits_addr_msb_T_3, _io_dmem_req_bits_addr_msb_T_5) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1325:18] node _io_dmem_req_bits_addr_T = bits(alu.io.adder_out, 32, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1326:16] node _io_dmem_req_bits_addr_T_1 = cat(io_dmem_req_bits_addr_msb, _io_dmem_req_bits_addr_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1326:8] connect io.dmem.req.bits.addr, _io_dmem_req_bits_addr_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1168:25] node _io_dmem_req_bits_dprv_T = mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1170:31] connect io.dmem.req.bits.dprv, _io_dmem_req_bits_dprv_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1170:25] node _io_dmem_req_bits_dv_T = or(ex_reg_hls, csr.io.status.dv) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1171:37] connect io.dmem.req.bits.dv, _io_dmem_req_bits_dv_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1171:23] node _io_dmem_req_bits_no_resp_T = eq(ex_ctrl.mem_cmd, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_dmem_req_bits_no_resp_T_1 = eq(ex_ctrl.mem_cmd, UInt<5>(0h10)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_dmem_req_bits_no_resp_T_2 = eq(ex_ctrl.mem_cmd, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_dmem_req_bits_no_resp_T_3 = eq(ex_ctrl.mem_cmd, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_dmem_req_bits_no_resp_T_4 = or(_io_dmem_req_bits_no_resp_T, _io_dmem_req_bits_no_resp_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_dmem_req_bits_no_resp_T_5 = or(_io_dmem_req_bits_no_resp_T_4, _io_dmem_req_bits_no_resp_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_dmem_req_bits_no_resp_T_6 = or(_io_dmem_req_bits_no_resp_T_5, _io_dmem_req_bits_no_resp_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_dmem_req_bits_no_resp_T_7 = eq(ex_ctrl.mem_cmd, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_dmem_req_bits_no_resp_T_8 = eq(ex_ctrl.mem_cmd, UInt<4>(0h9)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_dmem_req_bits_no_resp_T_9 = eq(ex_ctrl.mem_cmd, UInt<4>(0ha)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_dmem_req_bits_no_resp_T_10 = eq(ex_ctrl.mem_cmd, UInt<4>(0hb)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_dmem_req_bits_no_resp_T_11 = or(_io_dmem_req_bits_no_resp_T_7, _io_dmem_req_bits_no_resp_T_8) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_dmem_req_bits_no_resp_T_12 = or(_io_dmem_req_bits_no_resp_T_11, _io_dmem_req_bits_no_resp_T_9) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_dmem_req_bits_no_resp_T_13 = or(_io_dmem_req_bits_no_resp_T_12, _io_dmem_req_bits_no_resp_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_dmem_req_bits_no_resp_T_14 = eq(ex_ctrl.mem_cmd, UInt<4>(0h8)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_dmem_req_bits_no_resp_T_15 = eq(ex_ctrl.mem_cmd, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_dmem_req_bits_no_resp_T_16 = eq(ex_ctrl.mem_cmd, UInt<4>(0hd)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_dmem_req_bits_no_resp_T_17 = eq(ex_ctrl.mem_cmd, UInt<4>(0he)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_dmem_req_bits_no_resp_T_18 = eq(ex_ctrl.mem_cmd, UInt<4>(0hf)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 17:47] node _io_dmem_req_bits_no_resp_T_19 = or(_io_dmem_req_bits_no_resp_T_14, _io_dmem_req_bits_no_resp_T_15) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_dmem_req_bits_no_resp_T_20 = or(_io_dmem_req_bits_no_resp_T_19, _io_dmem_req_bits_no_resp_T_16) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_dmem_req_bits_no_resp_T_21 = or(_io_dmem_req_bits_no_resp_T_20, _io_dmem_req_bits_no_resp_T_17) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_dmem_req_bits_no_resp_T_22 = or(_io_dmem_req_bits_no_resp_T_21, _io_dmem_req_bits_no_resp_T_18) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 82:59] node _io_dmem_req_bits_no_resp_T_23 = or(_io_dmem_req_bits_no_resp_T_13, _io_dmem_req_bits_no_resp_T_22) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 87:44] node _io_dmem_req_bits_no_resp_T_24 = or(_io_dmem_req_bits_no_resp_T_6, _io_dmem_req_bits_no_resp_T_23) @[hardware/upstream/rocket-chip/src/main/scala/rocket/Consts.scala 89:68] node _io_dmem_req_bits_no_resp_T_25 = eq(_io_dmem_req_bits_no_resp_T_24, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1172:31] node _io_dmem_req_bits_no_resp_T_26 = eq(ex_ctrl.fp, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1172:60] node _io_dmem_req_bits_no_resp_T_27 = eq(ex_waddr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1172:84] node _io_dmem_req_bits_no_resp_T_28 = and(_io_dmem_req_bits_no_resp_T_26, _io_dmem_req_bits_no_resp_T_27) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1172:72] node _io_dmem_req_bits_no_resp_T_29 = or(_io_dmem_req_bits_no_resp_T_25, _io_dmem_req_bits_no_resp_T_28) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1172:56] connect io.dmem.req.bits.no_resp, _io_dmem_req_bits_no_resp_T_29 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1172:28] invalidate io.dmem.req.bits.no_alloc @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1173:29] invalidate io.dmem.req.bits.no_xcpt @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1174:28] invalidate io.dmem.req.bits.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1175:25] invalidate io.dmem.req.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1176:25] node _io_dmem_s1_data_data_T = mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1178:63] connect io.dmem.s1_data.data, _io_dmem_s1_data_data_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1178:24] invalidate io.dmem.s1_data.mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1179:24] node _io_dmem_s1_kill_T = or(killm_common, mem_ldst_xcpt) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1181:35] node _io_dmem_s1_kill_T_1 = or(_io_dmem_s1_kill_T, fpu_kill_mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1181:52] node _io_dmem_s1_kill_T_2 = or(_io_dmem_s1_kill_T_1, vec_kill_mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1181:68] connect io.dmem.s1_kill, _io_dmem_s1_kill_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1181:19] connect io.dmem.s2_kill, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1182:19] node _io_dmem_keep_clock_enabled_T = and(ibuf.io.inst[0].valid, id_ctrl.mem) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1184:55] node _io_dmem_keep_clock_enabled_T_1 = eq(csr.io.csr_stall, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1184:73] node _io_dmem_keep_clock_enabled_T_2 = and(_io_dmem_keep_clock_enabled_T, _io_dmem_keep_clock_enabled_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1184:70] connect io.dmem.keep_clock_enabled, _io_dmem_keep_clock_enabled_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1184:30] node _io_rocc_cmd_valid_T = and(wb_reg_valid, wb_ctrl.rocc) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1186:37] node _io_rocc_cmd_valid_T_1 = eq(replay_wb_common, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1186:56] node _io_rocc_cmd_valid_T_2 = and(_io_rocc_cmd_valid_T, _io_rocc_cmd_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1186:53] connect io.rocc.cmd.valid, _io_rocc_cmd_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1186:21] node _io_rocc_exception_T = orr(csr.io.status.xs) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1187:52] node _io_rocc_exception_T_1 = and(wb_xcpt, _io_rocc_exception_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1187:32] connect io.rocc.exception, _io_rocc_exception_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1187:21] connect io.rocc.cmd.bits.status, csr.io.status @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1188:27] wire _io_rocc_cmd_bits_inst_WIRE : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] wire _io_rocc_cmd_bits_inst_WIRE_1 : UInt<32> @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] connect _io_rocc_cmd_bits_inst_WIRE_1, wb_reg_inst @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] node _io_rocc_cmd_bits_inst_T = bits(_io_rocc_cmd_bits_inst_WIRE_1, 6, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] connect _io_rocc_cmd_bits_inst_WIRE.opcode, _io_rocc_cmd_bits_inst_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] node _io_rocc_cmd_bits_inst_T_1 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 11, 7) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] connect _io_rocc_cmd_bits_inst_WIRE.rd, _io_rocc_cmd_bits_inst_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] node _io_rocc_cmd_bits_inst_T_2 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] connect _io_rocc_cmd_bits_inst_WIRE.xs2, _io_rocc_cmd_bits_inst_T_2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] node _io_rocc_cmd_bits_inst_T_3 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] connect _io_rocc_cmd_bits_inst_WIRE.xs1, _io_rocc_cmd_bits_inst_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] node _io_rocc_cmd_bits_inst_T_4 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] connect _io_rocc_cmd_bits_inst_WIRE.xd, _io_rocc_cmd_bits_inst_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] node _io_rocc_cmd_bits_inst_T_5 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 19, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] connect _io_rocc_cmd_bits_inst_WIRE.rs1, _io_rocc_cmd_bits_inst_T_5 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] node _io_rocc_cmd_bits_inst_T_6 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 24, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] connect _io_rocc_cmd_bits_inst_WIRE.rs2, _io_rocc_cmd_bits_inst_T_6 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] node _io_rocc_cmd_bits_inst_T_7 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 31, 25) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] connect _io_rocc_cmd_bits_inst_WIRE.funct, _io_rocc_cmd_bits_inst_T_7 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:48] connect io.rocc.cmd.bits.inst, _io_rocc_cmd_bits_inst_WIRE @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1189:25] connect io.rocc.cmd.bits.rs1, wb_reg_wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1190:24] connect io.rocc.cmd.bits.rs2, wb_reg_rs2 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1191:24] node _unpause_T = bits(csr.io.time, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1194:28] node _unpause_T_1 = eq(_unpause_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1194:62] node _unpause_T_2 = or(_unpause_T_1, csr.io.inhibit_cycle) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1194:70] node _unpause_T_3 = or(_unpause_T_2, io.dmem.perf.release) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1194:94] node unpause = or(_unpause_T_3, take_pc_mem_wb) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1194:118] when unpause : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1195:18] connect id_reg_pause, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1195:33] node _io_cease_T = eq(clock_en_reg, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1196:38] node _io_cease_T_1 = and(csr.io.status.cease, _io_cease_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1196:35] connect io.cease, _io_cease_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1196:12] connect io.wfi, csr.io.status.wfi @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1197:10] reg icache_blocked_REG : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1214:55] connect icache_blocked_REG, io.imem.resp.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1214:55] node _icache_blocked_T = or(io.imem.resp.valid, icache_blocked_REG) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1214:45] node icache_blocked = eq(_icache_blocked_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1214:24] wire coreMonitorBundle : { clock : Clock, reset : UInt<1>, excpt : UInt<1>, priv_mode : UInt<3>, hartid : UInt<64>, timer : UInt<32>, valid : UInt<1>, pc : UInt<64>, wrdst : UInt<5>, wrdata : UInt<64>, wrenx : UInt<1>, wrenf : UInt<1>, rd0src : UInt<5>, rd0val : UInt<64>, rd1src : UInt<5>, rd1val : UInt<64>, inst : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1217:31] connect coreMonitorBundle.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1219:27] connect coreMonitorBundle.reset, reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1220:27] connect coreMonitorBundle.hartid, io.hartid @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1221:28] node _coreMonitorBundle_timer_T = bits(csr.io.time, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1222:41] connect coreMonitorBundle.timer, _coreMonitorBundle_timer_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1222:27] node _coreMonitorBundle_valid_T = eq(csr.io.trace[0].exception, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1223:55] node _coreMonitorBundle_valid_T_1 = and(csr.io.trace[0].valid, _coreMonitorBundle_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1223:52] connect coreMonitorBundle.valid, _coreMonitorBundle_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1223:27] node _coreMonitorBundle_pc_T = bits(csr.io.trace[0].iaddr, 33, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1224:48] node _coreMonitorBundle_pc_T_1 = bits(_coreMonitorBundle_pc_T, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:38] node _coreMonitorBundle_pc_T_2 = mux(_coreMonitorBundle_pc_T_1, UInt<30>(0h3fffffff), UInt<30>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:20] node _coreMonitorBundle_pc_T_3 = cat(_coreMonitorBundle_pc_T_2, _coreMonitorBundle_pc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 133:15] connect coreMonitorBundle.pc, _coreMonitorBundle_pc_T_3 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1224:24] node _coreMonitorBundle_wrenx_T = eq(wb_set_sboard, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1225:40] node _coreMonitorBundle_wrenx_T_1 = and(wb_wen, _coreMonitorBundle_wrenx_T) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1225:37] connect coreMonitorBundle.wrenx, _coreMonitorBundle_wrenx_T_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1225:27] connect coreMonitorBundle.wrenf, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1226:27] connect coreMonitorBundle.wrdst, wb_waddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1227:27] connect coreMonitorBundle.wrdata, rf_wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1228:28] node _coreMonitorBundle_rd0src_T = bits(wb_reg_inst, 19, 15) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1229:42] connect coreMonitorBundle.rd0src, _coreMonitorBundle_rd0src_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1229:28] reg coreMonitorBundle_rd0val_REG : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1230:46] connect coreMonitorBundle_rd0val_REG, ex_rs_0 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1230:46] reg coreMonitorBundle_rd0val_REG_1 : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1230:38] connect coreMonitorBundle_rd0val_REG_1, coreMonitorBundle_rd0val_REG @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1230:38] connect coreMonitorBundle.rd0val, coreMonitorBundle_rd0val_REG_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1230:28] node _coreMonitorBundle_rd1src_T = bits(wb_reg_inst, 24, 20) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1231:42] connect coreMonitorBundle.rd1src, _coreMonitorBundle_rd1src_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1231:28] reg coreMonitorBundle_rd1val_REG : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1232:46] connect coreMonitorBundle_rd1val_REG, ex_rs_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1232:46] reg coreMonitorBundle_rd1val_REG_1 : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1232:38] connect coreMonitorBundle_rd1val_REG_1, coreMonitorBundle_rd1val_REG @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1232:38] connect coreMonitorBundle.rd1val, coreMonitorBundle_rd1val_REG_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1232:28] connect coreMonitorBundle.inst, csr.io.trace[0].insn @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1233:26] connect coreMonitorBundle.excpt, csr.io.trace[0].exception @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1234:27] connect coreMonitorBundle.priv_mode, csr.io.trace[0].priv @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1235:31] when csr.io.trace[0].valid : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1264:34] node _T_154 = or(wb_ctrl.wxd, wb_ctrl.wfd) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1268:26] node _T_155 = mux(_T_154, coreMonitorBundle.wrdst, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1268:13] node _T_156 = mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1269:13] node _T_157 = or(wb_ctrl.rxs1, wb_ctrl.rfs1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1271:27] node _T_158 = mux(_T_157, coreMonitorBundle.rd0src, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1271:13] node _T_159 = or(wb_ctrl.rxs1, wb_ctrl.rfs1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1272:27] node _T_160 = mux(_T_159, coreMonitorBundle.rd0val, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1272:13] node _T_161 = or(wb_ctrl.rxs2, wb_ctrl.rfs2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1273:27] node _T_162 = mux(_T_161, coreMonitorBundle.rd1src, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1273:13] node _T_163 = or(wb_ctrl.rxs2, wb_ctrl.rfs2) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1274:27] node _T_164 = mux(_T_163, coreMonitorBundle.rd1val, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1274:13] node _T_165 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1265:13] node _T_166 = eq(_T_165, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1265:13] when _T_166 : @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1265:13] printf(clock, UInt<1>(0h1), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid, coreMonitorBundle.pc, _T_155, _T_156, coreMonitorBundle.wrenx, _T_158, _T_160, _T_162, _T_164, coreMonitorBundle.inst, coreMonitorBundle.inst) : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1265:13] wire xrfWriteBundle : { clock : Clock, reset : UInt<1>, excpt : UInt<1>, priv_mode : UInt<3>, hartid : UInt<64>, timer : UInt<32>, valid : UInt<1>, pc : UInt<64>, wrdst : UInt<5>, wrdata : UInt<64>, wrenx : UInt<1>, wrenf : UInt<1>, rd0src : UInt<5>, rd0val : UInt<64>, rd1src : UInt<5>, rd1val : UInt<64>, inst : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1280:28] connect xrfWriteBundle.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1282:24] connect xrfWriteBundle.reset, reset @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1283:24] connect xrfWriteBundle.hartid, io.hartid @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1284:25] node _xrfWriteBundle_timer_T = bits(csr.io.time, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1285:38] connect xrfWriteBundle.timer, _xrfWriteBundle_timer_T @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1285:24] connect xrfWriteBundle.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1286:24] connect xrfWriteBundle.pc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1287:21] connect xrfWriteBundle.wrdst, rf_waddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1288:24] node _xrfWriteBundle_wrenx_T = and(csr.io.trace[0].valid, wb_wen) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1289:61] node _xrfWriteBundle_wrenx_T_1 = eq(wb_waddr, rf_waddr) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1289:84] node _xrfWriteBundle_wrenx_T_2 = and(_xrfWriteBundle_wrenx_T, _xrfWriteBundle_wrenx_T_1) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1289:71] node _xrfWriteBundle_wrenx_T_3 = eq(_xrfWriteBundle_wrenx_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1289:37] node _xrfWriteBundle_wrenx_T_4 = and(rf_wen, _xrfWriteBundle_wrenx_T_3) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1289:34] connect xrfWriteBundle.wrenx, _xrfWriteBundle_wrenx_T_4 @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1289:24] connect xrfWriteBundle.wrenf, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1290:24] connect xrfWriteBundle.wrdata, rf_wdata @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1291:25] connect xrfWriteBundle.rd0src, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1292:25] connect xrfWriteBundle.rd0val, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1293:25] connect xrfWriteBundle.rd1src, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1294:25] connect xrfWriteBundle.rd1val, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1295:25] connect xrfWriteBundle.inst, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1296:23] connect xrfWriteBundle.excpt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1297:24] connect xrfWriteBundle.priv_mode, csr.io.trace[0].priv @[hardware/upstream/rocket-chip/src/main/scala/rocket/RocketCore.scala 1298:28] inst PlusArgTimeout of PlusArgTimeout @[hardware/upstream/rocket-chip/src/main/scala/util/PlusArg.scala 89:11] connect PlusArgTimeout.clock, clock connect PlusArgTimeout.reset, reset connect PlusArgTimeout.io.count, csr.io.time @[hardware/upstream/rocket-chip/src/main/scala/util/PlusArg.scala 89:82] module RocketTile : @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 166:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 166:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 166:7] output auto : { flip buffer_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, wfi_out : UInt<1>[1], cease_out : UInt<1>[1], halt_out : UInt<1>[1], flip int_local_in_2 : UInt<1>[1], flip int_local_in_1 : UInt<1>[2], flip int_local_in_0 : UInt<1>[1], trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, ctx : UInt<32>, tval : UInt<32>, cause : UInt<32>, time : UInt<32>}, trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<34>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<34>}[1], time : UInt<64>}, flip reset_vector_in : UInt<32>, flip hartid_in : UInt<1>} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] inst tlMasterXbar of TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u @[hardware/upstream/rocket-chip/src/main/scala/subsystem/HierarchicalElement.scala 55:42] connect tlMasterXbar.clock, clock connect tlMasterXbar.reset, reset inst tlSlaveXbar of TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u @[hardware/upstream/rocket-chip/src/main/scala/subsystem/HierarchicalElement.scala 56:41] connect tlSlaveXbar.clock, clock connect tlSlaveXbar.reset, reset inst intXbar of IntXbar_i3_o1 @[hardware/upstream/rocket-chip/src/main/scala/subsystem/HierarchicalElement.scala 57:37] inst broadcast of BundleBridgeNexus_UInt1 @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/package.scala 25:31] inst broadcast_1 of BundleBridgeNexus_UInt32 @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/package.scala 25:31] inst nexus of BundleBridgeNexus_UInt1_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 93:27] inst nexus_1 of BundleBridgeNexus_TraceAux @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 93:27] inst broadcast_2 of BundleBridgeNexus_NoOutput_4 @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/package.scala 25:31] inst widget of TLWidthWidget8_5 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 230:28] connect widget.clock, clock connect widget.reset, reset inst dcache of DCache @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 278:43] connect dcache.clock, clock connect dcache.reset, reset inst frontend of Frontend @[hardware/upstream/rocket-chip/src/main/scala/rocket/Frontend.scala 393:28] connect frontend.clock, clock connect frontend.reset, reset inst widget_1 of TLWidthWidget8_6 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 230:28] connect widget_1.clock, clock connect widget_1.reset, reset inst fragmenter of TLFragmenter @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 345:34] connect fragmenter.clock, clock connect fragmenter.reset, reset inst widget_2 of TLWidthWidget8_7 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/WidthWidget.scala 230:28] connect widget_2.clock, clock connect widget_2.reset, reset inst dtim_adapter of ScratchpadSlavePort @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 79:15] connect dtim_adapter.clock, clock connect dtim_adapter.reset, reset inst fragmenter_1 of TLFragmenter_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Fragmenter.scala 345:34] connect fragmenter_1.clock, clock connect fragmenter_1.reset, reset inst buffer of TLBuffer_a32d64s1k1z4u_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 75:28] connect buffer.clock, clock connect buffer.reset, reset inst buffer_1 of TLBuffer_a32d64s2k1z3u @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 75:28] connect buffer_1.clock, clock connect buffer_1.reset, reset wire tlOtherMastersNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate tlOtherMastersNodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlOtherMastersNodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire tlOtherMastersNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tlOtherMastersNodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlOtherMastersNodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect tlOtherMastersNodeOut, tlOtherMastersNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire hartIdSinkNodeIn : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate hartIdSinkNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire hartidOut : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate hartidOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire hartidIn : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate hartidIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect hartidOut, hartidIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire resetVectorSinkNodeIn : UInt<32> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate resetVectorSinkNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire reset_vectorOut : UInt<32> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate reset_vectorOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire reset_vectorIn : UInt<32> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate reset_vectorIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect reset_vectorOut, reset_vectorIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire traceSourceNodeOut : { insns : { valid : UInt<1>, iaddr : UInt<34>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<34>}[1], time : UInt<64>} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate traceSourceNodeOut.time @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate traceSourceNodeOut.insns[0].tval @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate traceSourceNodeOut.insns[0].cause @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate traceSourceNodeOut.insns[0].interrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate traceSourceNodeOut.insns[0].exception @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate traceSourceNodeOut.insns[0].priv @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate traceSourceNodeOut.insns[0].insn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate traceSourceNodeOut.insns[0].iaddr @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate traceSourceNodeOut.insns[0].valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire traceCoreSourceNodeOut : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, ctx : UInt<32>, tval : UInt<32>, cause : UInt<32>, time : UInt<32>} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate traceCoreSourceNodeOut.time @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate traceCoreSourceNodeOut.cause @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate traceCoreSourceNodeOut.tval @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate traceCoreSourceNodeOut.ctx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate traceCoreSourceNodeOut.priv @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate traceCoreSourceNodeOut.group[0].ilastsize @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate traceCoreSourceNodeOut.group[0].itype @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate traceCoreSourceNodeOut.group[0].iaddr @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate traceCoreSourceNodeOut.group[0].iretire @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire bundleIn_x_sourceOpt : { enable : UInt<1>, stall : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tile/BaseTile.scala 311:19] connect bundleIn_x_sourceOpt.stall, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/BaseTile.scala 312:16] connect bundleIn_x_sourceOpt.enable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/BaseTile.scala 313:16] wire traceAuxSinkNodeIn : { enable : UInt<1>, stall : UInt<1>} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate traceAuxSinkNodeIn.stall @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate traceAuxSinkNodeIn.enable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire bpwatchSourceNodeOut : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate bpwatchSourceNodeOut[0].action @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bpwatchSourceNodeOut[0].ivalid[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bpwatchSourceNodeOut[0].wvalid[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bpwatchSourceNodeOut[0].rvalid[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate bpwatchSourceNodeOut[0].valid[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire int_localOut : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate int_localOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_int_localOut : UInt<1>[2] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_int_localOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_int_localOut[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_int_localOut_1 : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_int_localOut_1[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire int_localIn : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate int_localIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire x1_int_localIn : UInt<1>[2] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate x1_int_localIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate x1_int_localIn[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire x1_int_localIn_1 : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate x1_int_localIn_1[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect int_localOut, int_localIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect x1_int_localOut, x1_int_localIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect x1_int_localOut_1, x1_int_localIn_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire intSinkNodeIn : UInt<1>[4] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate intSinkNodeIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate intSinkNodeIn[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate intSinkNodeIn[2] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate intSinkNodeIn[3] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire haltNodeOut : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate haltNodeOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire ceaseNodeOut : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate ceaseNodeOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire wfiNodeOut : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate wfiNodeOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire slaveNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate slaveNodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate slaveNodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire slaveNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate slaveNodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate slaveNodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect slaveNodeOut, slaveNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect buffer.auto.in, tlOtherMastersNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect tlMasterXbar.auto.anon_out.d, tlOtherMastersNodeIn.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tlOtherMastersNodeIn.a.bits, tlMasterXbar.auto.anon_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tlOtherMastersNodeIn.a.valid, tlMasterXbar.auto.anon_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tlMasterXbar.auto.anon_out.a.ready, tlOtherMastersNodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect fragmenter_1.auto.anon_in, tlSlaveXbar.auto.anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect intSinkNodeIn, intXbar.auto.anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect hartIdSinkNodeIn, broadcast.auto.out_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect dcache.auto.hart_id_sink_in, broadcast.auto.out_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect broadcast.auto.in, hartidOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect resetVectorSinkNodeIn, broadcast_1.auto.out_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect frontend.auto.reset_vector_sink_in, broadcast_1.auto.out_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect broadcast_1.auto.in, reset_vectorOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect dcache.auto.mmio_address_prefix_sink_in, nexus.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect traceAuxSinkNodeIn, nexus_1.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect broadcast_2.auto.in[0], bpwatchSourceNodeOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect intXbar.auto.anon_in_0[0], int_localOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect intXbar.auto.anon_in_1[0], x1_int_localOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect intXbar.auto.anon_in_1[1], x1_int_localOut[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect intXbar.auto.anon_in_2[0], x1_int_localOut_1[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect tlMasterXbar.auto.anon_in_0, widget.auto.anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect widget.auto.anon_in, dcache.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect widget_1.auto.anon_in, frontend.auto.icache_master_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect tlMasterXbar.auto.anon_in_1, widget_1.auto.anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tlSlaveXbar.auto.anon_in, slaveNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect dtim_adapter.auto.in, fragmenter_1.auto.anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect buffer_1.auto.out.d, slaveNodeIn.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect slaveNodeIn.a.bits, buffer_1.auto.out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect slaveNodeIn.a.valid, buffer_1.auto.out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect buffer_1.auto.out.a.ready, slaveNodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect hartidIn, auto.hartid_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect reset_vectorIn, auto.reset_vector_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.trace_source_out, traceSourceNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.trace_core_source_out, traceCoreSourceNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect int_localIn, auto.int_local_in_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect x1_int_localIn, auto.int_local_in_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect x1_int_localIn_1, auto.int_local_in_2 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.halt_out, haltNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.cease_out, ceaseNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.wfi_out, wfiNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect buffer.auto.out.d, auto.buffer_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.buffer_out.a.bits, buffer.auto.out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.buffer_out.a.valid, buffer.auto.out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect buffer.auto.out.a.ready, auto.buffer_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect buffer_1.auto.in, auto.buffer_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] invalidate dcache.io.tlb_port.s2_kill @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.prefetchable @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.must_alloc @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.cacheable @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.ma.inst @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.ma.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.ma.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.ae.inst @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.ae.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.ae.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.gf.inst @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.gf.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.gf.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.pf.inst @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.pf.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.pf.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.gpa_is_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.gpa @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.paddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.s1_resp.miss @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.req.bits.v @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.req.bits.prv @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.req.bits.cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.req.bits.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.req.bits.passthrough @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.req.bits.vaddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.req.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] invalidate dcache.io.tlb_port.req.ready @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 284:31] inst fpuOpt of FPU @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 289:62] connect fpuOpt.clock, clock connect fpuOpt.reset, reset connect fpuOpt.io.cp_req.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 308:27] invalidate fpuOpt.io.cp_req.bits.in3 @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.in2 @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.in1 @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.fmt @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.typ @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.fmaCmd @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.rm @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.vec @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.wflags @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.sqrt @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.div @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.fma @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.fastpipe @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.toint @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.fromint @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.typeTagOut @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.typeTagIn @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.swap23 @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.swap12 @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.ren3 @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.ren2 @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.ren1 @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.wen @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] invalidate fpuOpt.io.cp_req.bits.ldst @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 309:26] connect fpuOpt.io.cp_resp.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 310:28] inst dcacheArb of HellaCacheArbiter @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 292:25] connect dcacheArb.clock, clock connect dcacheArb.reset, reset connect dcache.io.cpu, dcacheArb.io.mem @[hardware/upstream/rocket-chip/src/main/scala/rocket/HellaCache.scala 293:30] inst ptw of PTW @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 822:19] connect ptw.clock, clock connect ptw.reset, reset invalidate ptw.io.mem.clock_enabled @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.keep_clock_enabled @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.perf.storeBufferEmptyAfterStore @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.perf.storeBufferEmptyAfterLoad @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.perf.canAcceptLoadThenLoad @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.perf.canAcceptStoreThenRMW @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.perf.canAcceptStoreThenLoad @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.perf.blocked @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.perf.tlbMiss @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.perf.grant @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.perf.release @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.perf.acquire @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.store_pending @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.ordered @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.s2_gpa_is_pte @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.s2_gpa @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.s2_xcpt.ae.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.s2_xcpt.ae.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.s2_xcpt.gf.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.s2_xcpt.gf.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.s2_xcpt.pf.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.s2_xcpt.pf.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.s2_xcpt.ma.st @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.s2_xcpt.ma.ld @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.replay_next @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.resp.bits.store_data @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.resp.bits.data_raw @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.resp.bits.data_word_bypass @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.resp.bits.has_data @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.resp.bits.replay @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.resp.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.resp.bits.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.resp.bits.dv @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.resp.bits.dprv @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.resp.bits.signed @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.resp.bits.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.resp.bits.cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.resp.bits.tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.resp.bits.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.resp.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.s2_paddr @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.s2_uncached @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.s2_kill @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.s2_nack_cause_raw @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.s2_nack @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.s1_data.mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.s1_data.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.s1_kill @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.req.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.req.bits.data @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.req.bits.no_xcpt @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.req.bits.no_alloc @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.req.bits.no_resp @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.req.bits.phys @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.req.bits.dv @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.req.bits.dprv @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.req.bits.signed @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.req.bits.size @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.req.bits.cmd @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.req.bits.tag @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.req.bits.addr @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.req.valid @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] invalidate ptw.io.mem.req.ready @[hardware/upstream/rocket-chip/src/main/scala/rocket/PTW.scala 823:14] inst core of Rocket @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 170:20] connect core.clock, clock connect core.reset, reset invalidate core.io.reset_vector @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 177:24] connect core.io.traceStall, traceAuxSinkNodeIn.stall @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 200:24] connect haltNodeOut[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/Interrupts.scala 97:28] connect ceaseNodeOut[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/Interrupts.scala 117:14] regreset wfiNodeOut_0_REG : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/Interrupts.scala 131:36] connect wfiNodeOut_0_REG, core.io.wfi @[hardware/upstream/rocket-chip/src/main/scala/tile/Interrupts.scala 131:36] connect wfiNodeOut[0], wfiNodeOut_0_REG @[hardware/upstream/rocket-chip/src/main/scala/tile/Interrupts.scala 131:12] connect core.io.interrupts.debug, intSinkNodeIn[0] @[hardware/upstream/rocket-chip/src/main/scala/tile/Interrupts.scala 87:93] connect core.io.interrupts.msip, intSinkNodeIn[1] @[hardware/upstream/rocket-chip/src/main/scala/tile/Interrupts.scala 87:93] connect core.io.interrupts.mtip, intSinkNodeIn[2] @[hardware/upstream/rocket-chip/src/main/scala/tile/Interrupts.scala 87:93] connect core.io.interrupts.meip, intSinkNodeIn[3] @[hardware/upstream/rocket-chip/src/main/scala/tile/Interrupts.scala 87:93] connect traceSourceNodeOut, core.io.trace @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 226:32] connect bpwatchSourceNodeOut, core.io.bpwatch @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 228:34] connect core.io.hartid, hartIdSinkNodeIn @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 229:18] connect frontend.io.cpu, core.io.imem @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 234:32] connect fpuOpt.io.keep_clock_enabled, core.io.fpu.keep_clock_enabled @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.sboard_clra, fpuOpt.io.sboard_clra @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.sboard_clr, fpuOpt.io.sboard_clr @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.sboard_set, fpuOpt.io.sboard_set @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.dec.vec, fpuOpt.io.dec.vec @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.dec.wflags, fpuOpt.io.dec.wflags @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.dec.sqrt, fpuOpt.io.dec.sqrt @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.dec.div, fpuOpt.io.dec.div @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.dec.fma, fpuOpt.io.dec.fma @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.dec.fastpipe, fpuOpt.io.dec.fastpipe @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.dec.toint, fpuOpt.io.dec.toint @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.dec.fromint, fpuOpt.io.dec.fromint @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.dec.typeTagOut, fpuOpt.io.dec.typeTagOut @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.dec.typeTagIn, fpuOpt.io.dec.typeTagIn @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.dec.swap23, fpuOpt.io.dec.swap23 @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.dec.swap12, fpuOpt.io.dec.swap12 @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.dec.ren3, fpuOpt.io.dec.ren3 @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.dec.ren2, fpuOpt.io.dec.ren2 @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.dec.ren1, fpuOpt.io.dec.ren1 @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.dec.wen, fpuOpt.io.dec.wen @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.dec.ldst, fpuOpt.io.dec.ldst @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect fpuOpt.io.killm, core.io.fpu.killm @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect fpuOpt.io.killx, core.io.fpu.killx @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.illegal_rm, fpuOpt.io.illegal_rm @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.nack_mem, fpuOpt.io.nack_mem @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.fcsr_rdy, fpuOpt.io.fcsr_rdy @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect fpuOpt.io.valid, core.io.fpu.valid @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect fpuOpt.io.ll_resp_data, core.io.fpu.ll_resp_data @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect fpuOpt.io.ll_resp_tag, core.io.fpu.ll_resp_tag @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect fpuOpt.io.ll_resp_type, core.io.fpu.ll_resp_type @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect fpuOpt.io.ll_resp_val, core.io.fpu.ll_resp_val @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.toint_data, fpuOpt.io.toint_data @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.store_data, fpuOpt.io.store_data @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect fpuOpt.io.v_sew, core.io.fpu.v_sew @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.fcsr_flags.bits, fpuOpt.io.fcsr_flags.bits @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.fpu.fcsr_flags.valid, fpuOpt.io.fcsr_flags.valid @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect fpuOpt.io.fcsr_rm, core.io.fpu.fcsr_rm @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect fpuOpt.io.fromint_data, core.io.fpu.fromint_data @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect fpuOpt.io.inst, core.io.fpu.inst @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect fpuOpt.io.time, core.io.fpu.time @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect fpuOpt.io.hartid, core.io.fpu.hartid @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 237:17] connect core.io.ptw, ptw.io.dpath @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 247:15] connect core.io.rocc.cmd.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 265:28] connect core.io.rocc.resp.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 266:29] invalidate core.io.rocc.resp.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 267:28] invalidate core.io.rocc.resp.bits.rd @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 267:28] invalidate core.io.rocc.busy @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 268:23] invalidate core.io.rocc.interrupt @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 269:28] invalidate core.io.rocc.mem.clock_enabled @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.keep_clock_enabled @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterStore @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterLoad @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.perf.canAcceptLoadThenLoad @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.perf.canAcceptStoreThenRMW @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.perf.canAcceptStoreThenLoad @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.perf.blocked @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.perf.tlbMiss @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.perf.grant @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.perf.release @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.perf.acquire @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.store_pending @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.ordered @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.s2_gpa_is_pte @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.s2_gpa @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.s2_xcpt.ae.st @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.s2_xcpt.ae.ld @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.s2_xcpt.gf.st @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.s2_xcpt.gf.ld @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.s2_xcpt.pf.st @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.s2_xcpt.pf.ld @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.s2_xcpt.ma.st @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.s2_xcpt.ma.ld @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.replay_next @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.resp.bits.store_data @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.resp.bits.data_raw @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.resp.bits.data_word_bypass @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.resp.bits.has_data @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.resp.bits.replay @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.resp.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.resp.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.resp.bits.dv @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.resp.bits.dprv @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.resp.bits.signed @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.resp.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.resp.bits.cmd @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.resp.bits.tag @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.resp.bits.addr @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.resp.valid @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.s2_paddr @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.s2_uncached @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.s2_kill @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.s2_nack_cause_raw @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.s2_nack @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.s1_data.mask @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.s1_data.data @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.s1_kill @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.req.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.req.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.req.bits.no_xcpt @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.req.bits.no_alloc @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.req.bits.no_resp @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.req.bits.phys @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.req.bits.dv @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.req.bits.dprv @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.req.bits.signed @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.req.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.req.bits.cmd @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.req.bits.tag @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.req.bits.addr @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.req.valid @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] invalidate core.io.rocc.mem.req.ready @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 272:20] connect dcacheArb.io.requestor[0], core.io.dmem @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 284:26] connect dcacheArb.io.requestor[1], dtim_adapter.io.dmem @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 284:26] connect ptw.io.requestor[0], dcache.io.ptw @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 285:20] connect ptw.io.requestor[1], frontend.io.ptw @[hardware/upstream/rocket-chip/src/main/scala/tile/RocketTile.scala 285:20] module HierarchicalElementResetDomain : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 14:9] output auto : { flip rockettile_buffer_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, rockettile_buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, rockettile_wfi_out : UInt<1>[1], rockettile_cease_out : UInt<1>[1], rockettile_halt_out : UInt<1>[1], flip rockettile_int_local_in_2 : UInt<1>[1], flip rockettile_int_local_in_1 : UInt<1>[2], flip rockettile_int_local_in_0 : UInt<1>[1], rockettile_trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, ctx : UInt<32>, tval : UInt<32>, cause : UInt<32>, time : UInt<32>}, rockettile_trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<34>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<34>}[1], time : UInt<64>}, flip rockettile_reset_vector_in : UInt<32>, flip rockettile_hartid_in : UInt<1>, flip clock_in : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 21:19] output reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 22:19] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] inst rockettile of RocketTile @[hardware/upstream/rocket-chip/src/main/scala/subsystem/HasTiles.scala 164:59] connect rockettile.clock, childClock connect rockettile.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate clockNodeIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate clockNodeIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect clockNodeIn, auto.clock_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect rockettile.auto.hartid_in, auto.rockettile_hartid_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect rockettile.auto.reset_vector_in, auto.rockettile_reset_vector_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.rockettile_trace_source_out.time, rockettile.auto.trace_source_out.time @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.rockettile_trace_source_out.insns, rockettile.auto.trace_source_out.insns @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.rockettile_trace_core_source_out.time, rockettile.auto.trace_core_source_out.time @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.rockettile_trace_core_source_out.cause, rockettile.auto.trace_core_source_out.cause @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.rockettile_trace_core_source_out.tval, rockettile.auto.trace_core_source_out.tval @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.rockettile_trace_core_source_out.ctx, rockettile.auto.trace_core_source_out.ctx @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.rockettile_trace_core_source_out.priv, rockettile.auto.trace_core_source_out.priv @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.rockettile_trace_core_source_out.group, rockettile.auto.trace_core_source_out.group @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect rockettile.auto.int_local_in_0[0], auto.rockettile_int_local_in_0[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect rockettile.auto.int_local_in_1[0], auto.rockettile_int_local_in_1[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect rockettile.auto.int_local_in_1[1], auto.rockettile_int_local_in_1[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect rockettile.auto.int_local_in_2[0], auto.rockettile_int_local_in_2[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.rockettile_halt_out, rockettile.auto.halt_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.rockettile_cease_out, rockettile.auto.cease_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.rockettile_wfi_out, rockettile.auto.wfi_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect rockettile.auto.buffer_out.d, auto.rockettile_buffer_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.rockettile_buffer_out.a.bits, rockettile.auto.buffer_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.rockettile_buffer_out.a.valid, rockettile.auto.buffer_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect rockettile.auto.buffer_out.a.ready, auto.rockettile_buffer_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect rockettile.auto.buffer_in, auto.rockettile_buffer_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect childClock, clockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 15:16] connect childReset, clockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 16:16] connect clock, clockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 23:11] connect reset, clockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 24:11] module FixedClockBroadcast_1_1 : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 104:9] output auto : { flip anon_in : { clock : Clock, reset : Reset}, anon_out : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire anonOut : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire anonIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonOut, anonIn @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 109:21] module Queue2_TLBundleA_a32d64s1k1z4u_1 : @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input clock : Clock @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input reset : Reset @[src/main/scala/chisel3/util/Decoupled.scala 243:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, count : UInt<2>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} [2] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] regreset enq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset deq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] infer mport MPORT = ram[enq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 270:24] node wrap = eq(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T = add(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_1 = tail(_value_T, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect enq_ptr_value, _value_T_1 @[src/main/scala/chisel3/util/Counter.scala 77:15] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] node wrap_1 = eq(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_3 = tail(_value_T_2, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect deq_ptr_value, _value_T_3 @[src/main/scala/chisel3/util/Counter.scala 77:15] node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] infer mport io_deq_bits_MPORT = ram[deq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module Queue2_TLBundleD_a32d64s1k1z4u_1 : @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input clock : Clock @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input reset : Reset @[src/main/scala/chisel3/util/Decoupled.scala 243:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, count : UInt<2>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} [2] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] regreset enq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset deq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] infer mport MPORT = ram[enq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 270:24] node wrap = eq(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T = add(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_1 = tail(_value_T, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect enq_ptr_value, _value_T_1 @[src/main/scala/chisel3/util/Counter.scala 77:15] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] node wrap_1 = eq(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_3 = tail(_value_T_2, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect deq_ptr_value, _value_T_3 @[src/main/scala/chisel3/util/Counter.scala 77:15] node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] infer mport io_deq_bits_MPORT = ram[deq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module TLBuffer_a32d64s1k1z4u_2 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] inst nodeOut_a_q of Queue2_TLBundleA_a32d64s1k1z4u_1 @[src/main/scala/chisel3/util/Decoupled.scala 362:21] connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid @[src/main/scala/chisel3/util/Decoupled.scala 364:22] connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.fetch, nodeIn.a.bits.user.amba_prot.fetch @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.secure, nodeIn.a.bits.user.amba_prot.secure @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.privileged, nodeIn.a.bits.user.amba_prot.privileged @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.writealloc, nodeIn.a.bits.user.amba_prot.writealloc @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.readalloc, nodeIn.a.bits.user.amba_prot.readalloc @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.modifiable, nodeIn.a.bits.user.amba_prot.modifiable @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.user.amba_prot.bufferable, nodeIn.a.bits.user.amba_prot.bufferable @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready @[src/main/scala/chisel3/util/Decoupled.scala 366:17] connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] inst nodeIn_d_q of Queue2_TLBundleD_a32d64s1k1z4u_1 @[src/main/scala/chisel3/util/Decoupled.scala 362:21] connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid @[src/main/scala/chisel3/util/Decoupled.scala 364:22] connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready @[src/main/scala/chisel3/util/Decoupled.scala 366:17] connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 52:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 53:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 54:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 55:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 56:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 57:21] module Queue2_TLBundleA_a32d64s2k1z3u : @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input clock : Clock @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input reset : Reset @[src/main/scala/chisel3/util/Decoupled.scala 243:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, count : UInt<2>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} [2] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] regreset enq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset deq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] infer mport MPORT = ram[enq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 270:24] node wrap = eq(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T = add(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_1 = tail(_value_T, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect enq_ptr_value, _value_T_1 @[src/main/scala/chisel3/util/Counter.scala 77:15] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] node wrap_1 = eq(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_3 = tail(_value_T_2, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect deq_ptr_value, _value_T_3 @[src/main/scala/chisel3/util/Counter.scala 77:15] node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] infer mport io_deq_bits_MPORT = ram[deq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module Queue2_TLBundleD_a32d64s2k1z3u : @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input clock : Clock @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input reset : Reset @[src/main/scala/chisel3/util/Decoupled.scala 243:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, count : UInt<2>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} [2] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] regreset enq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset deq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] infer mport MPORT = ram[enq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 270:24] node wrap = eq(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T = add(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_1 = tail(_value_T, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect enq_ptr_value, _value_T_1 @[src/main/scala/chisel3/util/Counter.scala 77:15] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] node wrap_1 = eq(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_3 = tail(_value_T_2, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect deq_ptr_value, _value_T_3 @[src/main/scala/chisel3/util/Counter.scala 77:15] node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] infer mport io_deq_bits_MPORT = ram[deq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module TLBuffer_a32d64s2k1z3u_1 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 40:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] inst nodeOut_a_q of Queue2_TLBundleA_a32d64s2k1z3u @[src/main/scala/chisel3/util/Decoupled.scala 362:21] connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid @[src/main/scala/chisel3/util/Decoupled.scala 364:22] connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready @[src/main/scala/chisel3/util/Decoupled.scala 366:17] connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 44:13] inst nodeIn_d_q of Queue2_TLBundleD_a32d64s2k1z3u @[src/main/scala/chisel3/util/Decoupled.scala 362:21] connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid @[src/main/scala/chisel3/util/Decoupled.scala 364:22] connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready @[src/main/scala/chisel3/util/Decoupled.scala 366:17] connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 45:13] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 52:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 53:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 54:20] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 55:21] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 56:21] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 57:21] module NonSyncResetSynchronizerPrimitiveShiftReg_d3_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 37:15] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 37:15] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 37:15] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] reg sync_0 : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:66] reg sync_1 : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:66] reg sync_2 : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:66] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module SynchronizerShiftReg_w1_d3_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 169:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 169:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 169:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 173:39] inst output_chain of NonSyncResetSynchronizerPrimitiveShiftReg_d3_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, reset connect output_chain.io.d, _output_T @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 175:8] module IntSyncAsyncCrossingSink_n1x1_1 : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 74:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 74:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 74:9] output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] inst chain of SynchronizerShiftReg_w1_d3_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect chain.clock, clock connect chain.reset, reset connect chain.io.d, nodeIn.sync[0] @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _WIRE : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] wire _WIRE_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _WIRE_1, chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] node _T = bits(_WIRE_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _WIRE[0], _T @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect nodeOut, _WIRE @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 77:11] module IntSyncSyncCrossingSink_n1x2 : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 96:9] output auto : { flip in : { sync : UInt<1>[2]}, out : UInt<1>[2]} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeIn : { sync : UInt<1>[2]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.sync[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : UInt<1>[2] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut, nodeIn.sync @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 100:11] module IntSyncSyncCrossingSink_n1x1 : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 96:9] output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeIn : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut, nodeIn.sync @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 100:11] module IntSyncSyncCrossingSink_n1x1_1 : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 96:9] output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeIn : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut, nodeIn.sync @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 100:11] module AsyncResetRegVec_w1_i0_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 56:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 56:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 56:7] output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 59:14] node _reg_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 61:29] regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 61:50] when io.en : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 62:16] connect reg, io.d @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 63:9] connect io.q, reg @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 65:8] module IntSyncCrossingSource_n1x1_1 : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 41:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 41:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 41:9] output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] inst reg of AsyncResetRegVec_w1_i0_1 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 86:21] connect reg.clock, clock connect reg.reset, reset connect reg.io.d, nodeIn[0] @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 88:14] connect reg.io.en, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 89:15] node _T = bits(reg.io.q, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 45:50] connect nodeOut.sync[0], _T @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 45:16] module IntSyncSyncCrossingSink_n1x1_2 : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 96:9] output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeIn : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut, nodeIn.sync @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 100:11] module AsyncResetRegVec_w1_i0_2 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 56:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 56:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 56:7] output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 59:14] node _reg_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 61:29] regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 61:50] when io.en : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 62:16] connect reg, io.d @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 63:9] connect io.q, reg @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 65:8] module IntSyncCrossingSource_n1x1_2 : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 41:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 41:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 41:9] output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] inst reg of AsyncResetRegVec_w1_i0_2 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 86:21] connect reg.clock, clock connect reg.reset, reset connect reg.io.d, nodeIn[0] @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 88:14] connect reg.io.en, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 89:15] node _T = bits(reg.io.q, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 45:50] connect nodeOut.sync[0], _T @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 45:16] module IntSyncSyncCrossingSink_n1x1_3 : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 96:9] output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeIn : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut, nodeIn.sync @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 100:11] module AsyncResetRegVec_w1_i0_3 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 56:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 56:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 56:7] output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 59:14] node _reg_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 61:29] regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 61:50] when io.en : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 62:16] connect reg, io.d @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 63:9] connect io.q, reg @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 65:8] module IntSyncCrossingSource_n1x1_3 : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 41:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 41:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 41:9] output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] inst reg of AsyncResetRegVec_w1_i0_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 86:21] connect reg.clock, clock connect reg.reset, reset connect reg.io.d, nodeIn[0] @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 88:14] connect reg.io.en, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 89:15] node _T = bits(reg.io.q, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 45:50] connect nodeOut.sync[0], _T @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 45:16] module TilePRCIDomain : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 14:9] output auto : { intsink_out_2 : UInt<1>[1], intsink_out_1 : UInt<1>[1], intsink_out_0 : UInt<1>[1], flip intsink_in : { sync : UInt<1>[1]}, element_reset_domain_rockettile_trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, ctx : UInt<32>, tval : UInt<32>, cause : UInt<32>, time : UInt<32>}, element_reset_domain_rockettile_trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<34>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<34>}[1], time : UInt<64>}, flip element_reset_domain_rockettile_reset_vector_in : UInt<32>, flip element_reset_domain_rockettile_hartid_in : UInt<1>, flip int_in_clock_xing_in_1 : { sync : UInt<1>[1]}, flip int_in_clock_xing_in_0 : { sync : UInt<1>[2]}, flip tl_slave_clock_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_master_clock_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tap_clock_in : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 21:19] output reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 22:19] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] inst element_reset_domain of HierarchicalElementResetDomain @[hardware/upstream/rocket-chip/src/main/scala/subsystem/HierarchicalElementPRCIDomain.scala 52:40] inst clockNode of FixedClockBroadcast_1_1 @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 115:114] inst buffer of TLBuffer_a32d64s1k1z4u_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 75:28] connect buffer.clock, childClock connect buffer.reset, childReset inst buffer_1 of TLBuffer_a32d64s2k1z3u_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Buffer.scala 75:28] connect buffer_1.clock, childClock connect buffer_1.reset, childReset inst intsink of IntSyncAsyncCrossingSink_n1x1_1 @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 86:29] connect intsink.clock, childClock connect intsink.reset, childReset inst intsink_1 of IntSyncSyncCrossingSink_n1x2 @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 109:29] inst intsink_2 of IntSyncSyncCrossingSink_n1x1 @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 109:29] inst intsink_3 of IntSyncSyncCrossingSink_n1x1_1 @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 109:29] inst intsource of IntSyncCrossingSource_n1x1_1 @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 29:31] connect intsource.clock, childClock connect intsource.reset, childReset inst intsink_4 of IntSyncSyncCrossingSink_n1x1_2 @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 109:29] inst intsource_1 of IntSyncCrossingSource_n1x1_2 @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 29:31] connect intsource_1.clock, childClock connect intsource_1.reset, childReset inst intsink_5 of IntSyncSyncCrossingSink_n1x1_3 @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 109:29] inst intsource_2 of IntSyncCrossingSource_n1x1_3 @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 29:31] connect intsource_2.clock, childClock connect intsource_2.reset, childReset wire tapClockNodeOut : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate tapClockNodeOut.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tapClockNodeOut.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire tapClockNodeIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tapClockNodeIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tapClockNodeIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect tapClockNodeOut, tapClockNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire tlMasterClockXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate tlMasterClockXingOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlMasterClockXingOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire tlMasterClockXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tlMasterClockXingIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlMasterClockXingIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect tlMasterClockXingOut, tlMasterClockXingIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire tlSlaveClockXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate tlSlaveClockXingOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate tlSlaveClockXingOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire tlSlaveClockXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<2>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tlSlaveClockXingIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlSlaveClockXingIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect tlSlaveClockXingOut, tlSlaveClockXingIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire intInClockXingOut : { sync : UInt<1>[2]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate intInClockXingOut.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate intInClockXingOut.sync[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire intInClockXingIn : { sync : UInt<1>[2]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate intInClockXingIn.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate intInClockXingIn.sync[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect intInClockXingOut, intInClockXingIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire intInClockXingOut_1 : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate intInClockXingOut_1.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire intInClockXingIn_1 : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate intInClockXingIn_1.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect intInClockXingOut_1, intInClockXingIn_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire intOutClockXingOut : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate intOutClockXingOut.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire intOutClockXingIn : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate intOutClockXingIn.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect intOutClockXingOut, intOutClockXingIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire intOutClockXingOut_1 : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate intOutClockXingOut_1.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire intOutClockXingIn_1 : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate intOutClockXingIn_1.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect intOutClockXingOut_1, intOutClockXingIn_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire intOutClockXingOut_2 : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate intOutClockXingOut_2.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire intOutClockXingIn_2 : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate intOutClockXingIn_2.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect intOutClockXingOut_2, intOutClockXingIn_2 @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire intOutClockXingOut_3 : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate intOutClockXingOut_3.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire intOutClockXingIn_3 : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate intOutClockXingIn_3.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect intOutClockXingOut_3, intOutClockXingIn_3 @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire intOutClockXingOut_4 : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate intOutClockXingOut_4.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire intOutClockXingIn_4 : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate intOutClockXingIn_4.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect intOutClockXingOut_4, intOutClockXingIn_4 @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire intOutClockXingOut_5 : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate intOutClockXingOut_5.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire intOutClockXingIn_5 : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate intOutClockXingIn_5.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect intOutClockXingOut_5, intOutClockXingIn_5 @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect clockNode.auto.anon_in, tapClockNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect element_reset_domain.auto.clock_in, clockNode.auto.anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect intsource.auto.in[0], element_reset_domain.auto.rockettile_halt_out[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect intsource_2.auto.in[0], element_reset_domain.auto.rockettile_cease_out[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect intsource_1.auto.in[0], element_reset_domain.auto.rockettile_wfi_out[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect buffer.auto.in, element_reset_domain.auto.rockettile_buffer_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect buffer.auto.out.d, tlMasterClockXingIn.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tlMasterClockXingIn.a.bits, buffer.auto.out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tlMasterClockXingIn.a.valid, buffer.auto.out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect buffer.auto.out.a.ready, tlMasterClockXingIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect element_reset_domain.auto.rockettile_buffer_in, buffer_1.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect buffer_1.auto.in, tlSlaveClockXingOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect element_reset_domain.auto.rockettile_int_local_in_0[0], intsink.auto.out[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect element_reset_domain.auto.rockettile_int_local_in_1[0], intsink_1.auto.out[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect element_reset_domain.auto.rockettile_int_local_in_1[1], intsink_1.auto.out[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect intsink_1.auto.in.sync[0], intInClockXingOut.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect intsink_1.auto.in.sync[1], intInClockXingOut.sync[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect element_reset_domain.auto.rockettile_int_local_in_2[0], intsink_2.auto.out[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect intsink_2.auto.in.sync[0], intInClockXingOut_1.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect intsink_3.auto.in.sync[0], intOutClockXingOut.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect intOutClockXingIn, intOutClockXingOut_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect intOutClockXingIn_1, intsource.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect intsink_4.auto.in.sync[0], intOutClockXingOut_2.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect intOutClockXingIn_2, intOutClockXingOut_3 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect intOutClockXingIn_3, intsource_1.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect intsink_5.auto.in.sync[0], intOutClockXingOut_4.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect intOutClockXingIn_4, intOutClockXingOut_5 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect intOutClockXingIn_5, intsource_2.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tapClockNodeIn, auto.tap_clock_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.tl_master_clock_xing_out, tlMasterClockXingOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect tlSlaveClockXingIn, auto.tl_slave_clock_xing_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect intInClockXingIn, auto.int_in_clock_xing_in_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect intInClockXingIn_1, auto.int_in_clock_xing_in_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect element_reset_domain.auto.rockettile_hartid_in, auto.element_reset_domain_rockettile_hartid_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect element_reset_domain.auto.rockettile_reset_vector_in, auto.element_reset_domain_rockettile_reset_vector_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.element_reset_domain_rockettile_trace_source_out.time, element_reset_domain.auto.rockettile_trace_source_out.time @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.element_reset_domain_rockettile_trace_source_out.insns, element_reset_domain.auto.rockettile_trace_source_out.insns @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.element_reset_domain_rockettile_trace_core_source_out.time, element_reset_domain.auto.rockettile_trace_core_source_out.time @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.element_reset_domain_rockettile_trace_core_source_out.cause, element_reset_domain.auto.rockettile_trace_core_source_out.cause @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.element_reset_domain_rockettile_trace_core_source_out.tval, element_reset_domain.auto.rockettile_trace_core_source_out.tval @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.element_reset_domain_rockettile_trace_core_source_out.ctx, element_reset_domain.auto.rockettile_trace_core_source_out.ctx @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.element_reset_domain_rockettile_trace_core_source_out.priv, element_reset_domain.auto.rockettile_trace_core_source_out.priv @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.element_reset_domain_rockettile_trace_core_source_out.group, element_reset_domain.auto.rockettile_trace_core_source_out.group @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect intsink.auto.in.sync[0], auto.intsink_in.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.intsink_out_0, intsink_3.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.intsink_out_1, intsink_4.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.intsink_out_2, intsink_5.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect childClock, tapClockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 15:16] connect childReset, tapClockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 16:16] connect clock, tapClockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 23:11] connect reset, tapClockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 24:11] module IntXbar_i1_o1 : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 22:9] output auto : { flip anon_in : UInt<1>[1], anon_out : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire anonOut : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire anonIn : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonOut[0], anonIn[0] @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 25:44] module IntXbar_i1_o1_1 : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 22:9] output auto : { flip anon_in : UInt<1>[1], anon_out : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire anonOut : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire anonIn : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonOut[0], anonIn[0] @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 25:44] module IntXbar_i1_o1_2 : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 22:9] output auto : { flip anon_in : UInt<1>[1], anon_out : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire anonOut : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire anonIn : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.anon_out, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect anonOut[0], anonIn[0] @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 25:44] module BundleBridgeNexus_UInt1_2 : @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 21:9] output auto : { out : UInt<1>} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeOut : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] node outputs_0 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/subsystem/HasTiles.scala 78:32] connect nodeOut, outputs_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 59:67] module BundleBridgeNexus_UInt32_1 : @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 21:9] output auto : { flip in : UInt<32>, out : UInt<32>} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeIn : UInt<32> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : UInt<32> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut, nodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 59:67] module CLINT : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala 64:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala 64:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala 64:9] output auto : { int_out : UInt<1>[2], flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output io : { flip rtcTick : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala 67:16] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire intnodeOut : UInt<1>[2] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate intnodeOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate intnodeOut[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.int_out, intnodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] regreset time : UInt<64>, clock, reset, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala 71:23] when io.rtcTick : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala 72:23] node _time_T = add(time, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala 72:38] node _time_T_1 = tail(_time_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala 72:38] connect time, _time_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala 72:30] reg timecmp_0 : UInt<64>, clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala 75:41] regreset ipi_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala 76:41] node _intnodeOut_0_T = bits(ipi_0, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala 80:37] connect intnodeOut[0], _intnodeOut_0_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala 80:14] node _intnodeOut_1_T = geq(time, timecmp_0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala 81:43] connect intnodeOut[1], _intnodeOut_1_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala 81:14] node pad = or(timecmp_0, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 152:19] node _oldBytes_T = bits(pad, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:57] node _oldBytes_T_1 = bits(pad, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:57] node _oldBytes_T_2 = bits(pad, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:57] node _oldBytes_T_3 = bits(pad, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:57] node _oldBytes_T_4 = bits(pad, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:57] node _oldBytes_T_5 = bits(pad, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:57] node _oldBytes_T_6 = bits(pad, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:57] node _oldBytes_T_7 = bits(pad, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:57] wire oldBytes : UInt<8>[8] @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:47] connect oldBytes[0], _oldBytes_T @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:47] connect oldBytes[1], _oldBytes_T_1 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:47] connect oldBytes[2], _oldBytes_T_2 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:47] connect oldBytes[3], _oldBytes_T_3 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:47] connect oldBytes[4], _oldBytes_T_4 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:47] connect oldBytes[5], _oldBytes_T_5 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:47] connect oldBytes[6], _oldBytes_T_6 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:47] connect oldBytes[7], _oldBytes_T_7 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:47] wire newBytes : UInt<8>[8] @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 154:31] connect newBytes, oldBytes @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 154:31] wire _valids_WIRE : UInt<1>[8] @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:53] connect _valids_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:53] connect _valids_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:53] connect _valids_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:53] connect _valids_WIRE[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:53] connect _valids_WIRE[4], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:53] connect _valids_WIRE[5], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:53] connect _valids_WIRE[6], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:53] connect _valids_WIRE[7], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:53] wire valids : UInt<1>[8] @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:29] connect valids, _valids_WIRE @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:29] node _T = or(valids[0], valids[1]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:27] node _T_1 = or(_T, valids[2]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:27] node _T_2 = or(_T_1, valids[3]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:27] node _T_3 = or(_T_2, valids[4]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:27] node _T_4 = or(_T_3, valids[5]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:27] node _T_5 = or(_T_4, valids[6]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:27] node _T_6 = or(_T_5, valids[7]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:27] when _T_6 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:34] node timecmp_0_lo_lo = cat(newBytes[1], newBytes[0]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:52] node timecmp_0_lo_hi = cat(newBytes[3], newBytes[2]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:52] node timecmp_0_lo = cat(timecmp_0_lo_hi, timecmp_0_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:52] node timecmp_0_hi_lo = cat(newBytes[5], newBytes[4]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:52] node timecmp_0_hi_hi = cat(newBytes[7], newBytes[6]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:52] node timecmp_0_hi = cat(timecmp_0_hi_hi, timecmp_0_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:52] node _timecmp_0_T = cat(timecmp_0_hi, timecmp_0_lo) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:52] connect timecmp_0, _timecmp_0_T @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:40] node pad_1 = or(time, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 152:19] node _oldBytes_T_8 = bits(pad_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:57] node _oldBytes_T_9 = bits(pad_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:57] node _oldBytes_T_10 = bits(pad_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:57] node _oldBytes_T_11 = bits(pad_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:57] node _oldBytes_T_12 = bits(pad_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:57] node _oldBytes_T_13 = bits(pad_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:57] node _oldBytes_T_14 = bits(pad_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:57] node _oldBytes_T_15 = bits(pad_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:57] wire oldBytes_1 : UInt<8>[8] @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:47] connect oldBytes_1[0], _oldBytes_T_8 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:47] connect oldBytes_1[1], _oldBytes_T_9 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:47] connect oldBytes_1[2], _oldBytes_T_10 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:47] connect oldBytes_1[3], _oldBytes_T_11 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:47] connect oldBytes_1[4], _oldBytes_T_12 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:47] connect oldBytes_1[5], _oldBytes_T_13 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:47] connect oldBytes_1[6], _oldBytes_T_14 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:47] connect oldBytes_1[7], _oldBytes_T_15 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 153:47] wire newBytes_1 : UInt<8>[8] @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 154:31] connect newBytes_1, oldBytes_1 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 154:31] wire _valids_WIRE_1 : UInt<1>[8] @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:53] connect _valids_WIRE_1[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:53] connect _valids_WIRE_1[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:53] connect _valids_WIRE_1[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:53] connect _valids_WIRE_1[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:53] connect _valids_WIRE_1[4], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:53] connect _valids_WIRE_1[5], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:53] connect _valids_WIRE_1[6], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:53] connect _valids_WIRE_1[7], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:53] wire valids_1 : UInt<1>[8] @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:29] connect valids_1, _valids_WIRE_1 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 155:29] node _T_7 = or(valids_1[0], valids_1[1]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:27] node _T_8 = or(_T_7, valids_1[2]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:27] node _T_9 = or(_T_8, valids_1[3]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:27] node _T_10 = or(_T_9, valids_1[4]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:27] node _T_11 = or(_T_10, valids_1[5]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:27] node _T_12 = or(_T_11, valids_1[6]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:27] node _T_13 = or(_T_12, valids_1[7]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:27] when _T_13 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:34] node time_lo_lo = cat(newBytes_1[1], newBytes_1[0]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:52] node time_lo_hi = cat(newBytes_1[3], newBytes_1[2]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:52] node time_lo = cat(time_lo_hi, time_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:52] node time_hi_lo = cat(newBytes_1[5], newBytes_1[4]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:52] node time_hi_hi = cat(newBytes_1[7], newBytes_1[6]) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:52] node time_hi = cat(time_hi_hi, time_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:52] node _time_T_2 = cat(time_hi, time_lo) @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:52] connect time, _time_T_2 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 156:40] wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<13>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 73:18] node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 74:36] connect in.bits.read, _in_bits_read_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 74:19] node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 192:34] connect in.bits.index, _in_bits_index_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 75:19] connect in.bits.data, nodeIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 76:19] connect in.bits.mask, nodeIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 77:19] connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 83:20] connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 84:20] wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<13>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front.bits, in.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_maskMatch = not(UInt<13>(0h1800)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_findex = and(out_front.bits.index, out_maskMatch) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_bindex = and(out_front.bits.index, out_maskMatch) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T = eq(out_findex, UInt<13>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1 = eq(out_bindex, UInt<13>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2 = eq(out_findex, UInt<13>(0h7ff)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3 = eq(out_bindex, UInt<13>(0h7ff)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4 = eq(out_findex, UInt<13>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5 = eq(out_bindex, UInt<13>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rivalid : UInt<1>[18] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wivalid : UInt<1>[18] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_roready : UInt<1>[18] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_woready : UInt<1>[18] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T = bits(out_front.bits.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask = cat(out_backMask_hi, out_backMask_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T = bits(out_frontMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask = orr(_out_rimask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T = bits(out_frontMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask = andr(_out_wimask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T = bits(out_backMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask = orr(_out_romask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T = bits(out_backMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask = andr(_out_womask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid = and(out_rivalid[0], out_rimask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready = and(out_roready[0], out_romask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid = and(out_wivalid[0], out_wimask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready = and(out_woready[0], out_womask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6 = bits(out_front.bits.data, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect ipi_0, _out_T_6 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_7 = and(out_f_rivalid, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8 = and(UInt<1>(0h1), out_f_roready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9 = and(out_f_wivalid, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10 = and(UInt<1>(0h1), out_f_woready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11 = eq(out_rimask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12 = eq(out_wimask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_13 = eq(out_romask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_14 = eq(out_womask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_15 = or(ipi_0, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_16 = bits(_out_T_15, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1 = bits(out_frontMask, 31, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1 = orr(_out_rimask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1 = bits(out_frontMask, 31, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1 = andr(_out_wimask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1 = bits(out_backMask, 31, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1 = orr(_out_romask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1 = bits(out_backMask, 31, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1 = andr(_out_womask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1 = and(out_roready[1], out_romask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1 = and(out_woready[1], out_womask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_17 = bits(out_front.bits.data, 31, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_18 = and(out_f_rivalid_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_19 = and(UInt<1>(0h1), out_f_roready_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_20 = eq(out_rimask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_21 = eq(out_wimask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_22 = eq(out_romask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_23 = eq(out_womask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T = or(_out_T_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend = cat(UInt<1>(0h0), _out_prepend_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_24 = or(out_prepend, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_25 = bits(_out_T_24, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_2 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_2 = orr(_out_rimask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_2 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_2 = andr(_out_wimask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_2 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_2 = orr(_out_romask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_2 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_2 = andr(_out_womask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_2 = and(out_roready[2], out_romask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_2 = and(out_woready[2], out_womask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_26 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect valids_1[0], out_f_woready_2 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 159:17] when out_f_woready_2 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:20] connect newBytes_1[0], _out_T_26 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:33] node _out_T_27 = and(out_f_rivalid_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_28 = and(UInt<1>(0h1), out_f_roready_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_29 = and(out_f_wivalid_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_30 = and(UInt<1>(0h1), out_f_woready_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_31 = eq(out_rimask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_32 = eq(out_wimask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_33 = eq(out_romask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_34 = eq(out_womask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_35 = or(oldBytes_1[0], UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_36 = bits(_out_T_35, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_3 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_3 = orr(_out_rimask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_3 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_3 = andr(_out_wimask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_3 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_3 = orr(_out_romask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_3 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_3 = andr(_out_womask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_3 = and(out_roready[3], out_romask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_3 = and(out_woready[3], out_womask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_37 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect valids_1[1], out_f_woready_3 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 159:17] when out_f_woready_3 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:20] connect newBytes_1[1], _out_T_37 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:33] node _out_T_38 = and(out_f_rivalid_3, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_39 = and(UInt<1>(0h1), out_f_roready_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_40 = and(out_f_wivalid_3, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_41 = and(UInt<1>(0h1), out_f_woready_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_42 = eq(out_rimask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_43 = eq(out_wimask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_44 = eq(out_romask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_45 = eq(out_womask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1 = or(_out_T_36, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1 = cat(oldBytes_1[1], _out_prepend_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_46 = or(out_prepend_1, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_47 = bits(_out_T_46, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_4 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_4 = orr(_out_rimask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_4 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_4 = andr(_out_wimask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_4 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_4 = orr(_out_romask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_4 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_4 = andr(_out_womask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_4 = and(out_roready[4], out_romask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_4 = and(out_woready[4], out_womask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_48 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect valids_1[2], out_f_woready_4 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 159:17] when out_f_woready_4 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:20] connect newBytes_1[2], _out_T_48 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:33] node _out_T_49 = and(out_f_rivalid_4, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_50 = and(UInt<1>(0h1), out_f_roready_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_51 = and(out_f_wivalid_4, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_52 = and(UInt<1>(0h1), out_f_woready_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_53 = eq(out_rimask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_54 = eq(out_wimask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_55 = eq(out_romask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_56 = eq(out_womask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_2 = or(_out_T_47, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_2 = cat(oldBytes_1[2], _out_prepend_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_57 = or(out_prepend_2, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_58 = bits(_out_T_57, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_5 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_5 = orr(_out_rimask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_5 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_5 = andr(_out_wimask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_5 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_5 = orr(_out_romask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_5 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_5 = andr(_out_womask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_5 = and(out_roready[5], out_romask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_5 = and(out_woready[5], out_womask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_59 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect valids_1[3], out_f_woready_5 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 159:17] when out_f_woready_5 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:20] connect newBytes_1[3], _out_T_59 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:33] node _out_T_60 = and(out_f_rivalid_5, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_61 = and(UInt<1>(0h1), out_f_roready_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_62 = and(out_f_wivalid_5, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_63 = and(UInt<1>(0h1), out_f_woready_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_64 = eq(out_rimask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_65 = eq(out_wimask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_66 = eq(out_romask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_67 = eq(out_womask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_3 = or(_out_T_58, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_3 = cat(oldBytes_1[3], _out_prepend_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_68 = or(out_prepend_3, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_69 = bits(_out_T_68, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_6 = bits(out_frontMask, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_6 = orr(_out_rimask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_6 = bits(out_frontMask, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_6 = andr(_out_wimask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_6 = bits(out_backMask, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_6 = orr(_out_romask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_6 = bits(out_backMask, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_6 = andr(_out_womask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_6 = and(out_roready[6], out_romask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_6 = and(out_woready[6], out_womask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_70 = bits(out_front.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect valids_1[4], out_f_woready_6 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 159:17] when out_f_woready_6 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:20] connect newBytes_1[4], _out_T_70 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:33] node _out_T_71 = and(out_f_rivalid_6, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_72 = and(UInt<1>(0h1), out_f_roready_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_73 = and(out_f_wivalid_6, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_74 = and(UInt<1>(0h1), out_f_woready_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_75 = eq(out_rimask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_76 = eq(out_wimask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_77 = eq(out_romask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_78 = eq(out_womask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_4 = or(_out_T_69, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_4 = cat(oldBytes_1[4], _out_prepend_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_79 = or(out_prepend_4, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_80 = bits(_out_T_79, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_7 = bits(out_frontMask, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_7 = orr(_out_rimask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_7 = bits(out_frontMask, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_7 = andr(_out_wimask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_7 = bits(out_backMask, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_7 = orr(_out_romask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_7 = bits(out_backMask, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_7 = andr(_out_womask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_7 = and(out_roready[7], out_romask_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_7 = and(out_woready[7], out_womask_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_81 = bits(out_front.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect valids_1[5], out_f_woready_7 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 159:17] when out_f_woready_7 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:20] connect newBytes_1[5], _out_T_81 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:33] node _out_T_82 = and(out_f_rivalid_7, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_83 = and(UInt<1>(0h1), out_f_roready_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_84 = and(out_f_wivalid_7, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_85 = and(UInt<1>(0h1), out_f_woready_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_86 = eq(out_rimask_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_87 = eq(out_wimask_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_88 = eq(out_romask_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_89 = eq(out_womask_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_5 = or(_out_T_80, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_5 = cat(oldBytes_1[5], _out_prepend_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_90 = or(out_prepend_5, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_91 = bits(_out_T_90, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_8 = bits(out_frontMask, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_8 = orr(_out_rimask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_8 = bits(out_frontMask, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_8 = andr(_out_wimask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_8 = bits(out_backMask, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_8 = orr(_out_romask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_8 = bits(out_backMask, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_8 = andr(_out_womask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_8 = and(out_roready[8], out_romask_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_8 = and(out_woready[8], out_womask_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_92 = bits(out_front.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect valids_1[6], out_f_woready_8 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 159:17] when out_f_woready_8 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:20] connect newBytes_1[6], _out_T_92 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:33] node _out_T_93 = and(out_f_rivalid_8, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_94 = and(UInt<1>(0h1), out_f_roready_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_95 = and(out_f_wivalid_8, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_96 = and(UInt<1>(0h1), out_f_woready_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_97 = eq(out_rimask_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_98 = eq(out_wimask_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_99 = eq(out_romask_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_100 = eq(out_womask_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_6 = or(_out_T_91, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_6 = cat(oldBytes_1[6], _out_prepend_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_101 = or(out_prepend_6, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_102 = bits(_out_T_101, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_9 = bits(out_frontMask, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_9 = orr(_out_rimask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_9 = bits(out_frontMask, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_9 = andr(_out_wimask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_9 = bits(out_backMask, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_9 = orr(_out_romask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_9 = bits(out_backMask, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_9 = andr(_out_womask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_9 = and(out_roready[9], out_romask_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_9 = and(out_woready[9], out_womask_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_103 = bits(out_front.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect valids_1[7], out_f_woready_9 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 159:17] when out_f_woready_9 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:20] connect newBytes_1[7], _out_T_103 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:33] node _out_T_104 = and(out_f_rivalid_9, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_105 = and(UInt<1>(0h1), out_f_roready_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_106 = and(out_f_wivalid_9, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_107 = and(UInt<1>(0h1), out_f_woready_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_108 = eq(out_rimask_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_109 = eq(out_wimask_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_110 = eq(out_romask_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_111 = eq(out_womask_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_7 = or(_out_T_102, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_7 = cat(oldBytes_1[7], _out_prepend_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_112 = or(out_prepend_7, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_113 = bits(_out_T_112, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_10 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_10 = orr(_out_rimask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_10 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_10 = andr(_out_wimask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_10 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_10 = orr(_out_romask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_10 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_10 = andr(_out_womask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_10 = and(out_roready[10], out_romask_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_10 = and(out_woready[10], out_womask_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_114 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect valids[0], out_f_woready_10 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 159:17] when out_f_woready_10 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:20] connect newBytes[0], _out_T_114 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:33] node _out_T_115 = and(out_f_rivalid_10, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_116 = and(UInt<1>(0h1), out_f_roready_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_117 = and(out_f_wivalid_10, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_118 = and(UInt<1>(0h1), out_f_woready_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_119 = eq(out_rimask_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_120 = eq(out_wimask_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_121 = eq(out_romask_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_122 = eq(out_womask_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_123 = or(oldBytes[0], UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_124 = bits(_out_T_123, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_11 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_11 = orr(_out_rimask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_11 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_11 = andr(_out_wimask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_11 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_11 = orr(_out_romask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_11 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_11 = andr(_out_womask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_11 = and(out_roready[11], out_romask_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_11 = and(out_woready[11], out_womask_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_125 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect valids[1], out_f_woready_11 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 159:17] when out_f_woready_11 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:20] connect newBytes[1], _out_T_125 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:33] node _out_T_126 = and(out_f_rivalid_11, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_127 = and(UInt<1>(0h1), out_f_roready_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_128 = and(out_f_wivalid_11, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_129 = and(UInt<1>(0h1), out_f_woready_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_130 = eq(out_rimask_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_131 = eq(out_wimask_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_132 = eq(out_romask_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_133 = eq(out_womask_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_8 = or(_out_T_124, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_8 = cat(oldBytes[1], _out_prepend_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_134 = or(out_prepend_8, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_135 = bits(_out_T_134, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_12 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_12 = orr(_out_rimask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_12 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_12 = andr(_out_wimask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_12 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_12 = orr(_out_romask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_12 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_12 = andr(_out_womask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_12 = and(out_roready[12], out_romask_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_12 = and(out_woready[12], out_womask_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_136 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect valids[2], out_f_woready_12 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 159:17] when out_f_woready_12 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:20] connect newBytes[2], _out_T_136 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:33] node _out_T_137 = and(out_f_rivalid_12, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_138 = and(UInt<1>(0h1), out_f_roready_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_139 = and(out_f_wivalid_12, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_140 = and(UInt<1>(0h1), out_f_woready_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_141 = eq(out_rimask_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_142 = eq(out_wimask_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_143 = eq(out_romask_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_144 = eq(out_womask_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_9 = or(_out_T_135, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_9 = cat(oldBytes[2], _out_prepend_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_145 = or(out_prepend_9, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_146 = bits(_out_T_145, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_13 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_13 = orr(_out_rimask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_13 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_13 = andr(_out_wimask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_13 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_13 = orr(_out_romask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_13 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_13 = andr(_out_womask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_13 = and(out_roready[13], out_romask_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_13 = and(out_woready[13], out_womask_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_147 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect valids[3], out_f_woready_13 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 159:17] when out_f_woready_13 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:20] connect newBytes[3], _out_T_147 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:33] node _out_T_148 = and(out_f_rivalid_13, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_149 = and(UInt<1>(0h1), out_f_roready_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_150 = and(out_f_wivalid_13, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_151 = and(UInt<1>(0h1), out_f_woready_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_152 = eq(out_rimask_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_153 = eq(out_wimask_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_154 = eq(out_romask_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_155 = eq(out_womask_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_10 = or(_out_T_146, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_10 = cat(oldBytes[3], _out_prepend_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_156 = or(out_prepend_10, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_157 = bits(_out_T_156, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_14 = bits(out_frontMask, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_14 = orr(_out_rimask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_14 = bits(out_frontMask, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_14 = andr(_out_wimask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_14 = bits(out_backMask, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_14 = orr(_out_romask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_14 = bits(out_backMask, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_14 = andr(_out_womask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_14 = and(out_roready[14], out_romask_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_14 = and(out_woready[14], out_womask_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_158 = bits(out_front.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect valids[4], out_f_woready_14 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 159:17] when out_f_woready_14 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:20] connect newBytes[4], _out_T_158 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:33] node _out_T_159 = and(out_f_rivalid_14, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_160 = and(UInt<1>(0h1), out_f_roready_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_161 = and(out_f_wivalid_14, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_162 = and(UInt<1>(0h1), out_f_woready_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_163 = eq(out_rimask_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_164 = eq(out_wimask_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_165 = eq(out_romask_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_166 = eq(out_womask_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_11 = or(_out_T_157, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_11 = cat(oldBytes[4], _out_prepend_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_167 = or(out_prepend_11, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_168 = bits(_out_T_167, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_15 = bits(out_frontMask, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_15 = orr(_out_rimask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_15 = bits(out_frontMask, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_15 = andr(_out_wimask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_15 = bits(out_backMask, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_15 = orr(_out_romask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_15 = bits(out_backMask, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_15 = andr(_out_womask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_15 = and(out_roready[15], out_romask_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_15 = and(out_woready[15], out_womask_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_169 = bits(out_front.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect valids[5], out_f_woready_15 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 159:17] when out_f_woready_15 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:20] connect newBytes[5], _out_T_169 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:33] node _out_T_170 = and(out_f_rivalid_15, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_171 = and(UInt<1>(0h1), out_f_roready_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_172 = and(out_f_wivalid_15, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_173 = and(UInt<1>(0h1), out_f_woready_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_174 = eq(out_rimask_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_175 = eq(out_wimask_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_176 = eq(out_romask_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_177 = eq(out_womask_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_12 = or(_out_T_168, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_12 = cat(oldBytes[5], _out_prepend_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_178 = or(out_prepend_12, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_179 = bits(_out_T_178, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_16 = bits(out_frontMask, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_16 = orr(_out_rimask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_16 = bits(out_frontMask, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_16 = andr(_out_wimask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_16 = bits(out_backMask, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_16 = orr(_out_romask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_16 = bits(out_backMask, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_16 = andr(_out_womask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_16 = and(out_rivalid[16], out_rimask_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_16 = and(out_roready[16], out_romask_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_16 = and(out_wivalid[16], out_wimask_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_16 = and(out_woready[16], out_womask_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_180 = bits(out_front.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect valids[6], out_f_woready_16 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 159:17] when out_f_woready_16 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:20] connect newBytes[6], _out_T_180 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:33] node _out_T_181 = and(out_f_rivalid_16, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_182 = and(UInt<1>(0h1), out_f_roready_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_183 = and(out_f_wivalid_16, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_184 = and(UInt<1>(0h1), out_f_woready_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_185 = eq(out_rimask_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_186 = eq(out_wimask_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_187 = eq(out_romask_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_188 = eq(out_womask_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_13 = or(_out_T_179, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_13 = cat(oldBytes[6], _out_prepend_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_189 = or(out_prepend_13, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_190 = bits(_out_T_189, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_17 = bits(out_frontMask, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_17 = orr(_out_rimask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_17 = bits(out_frontMask, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_17 = andr(_out_wimask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_17 = bits(out_backMask, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_17 = orr(_out_romask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_17 = bits(out_backMask, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_17 = andr(_out_womask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_17 = and(out_rivalid[17], out_rimask_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_17 = and(out_roready[17], out_romask_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_17 = and(out_wivalid[17], out_wimask_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_17 = and(out_woready[17], out_womask_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_191 = bits(out_front.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect valids[7], out_f_woready_17 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 159:17] when out_f_woready_17 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:20] connect newBytes[7], _out_T_191 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 160:33] node _out_T_192 = and(out_f_rivalid_17, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_193 = and(UInt<1>(0h1), out_f_roready_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_194 = and(out_f_wivalid_17, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_195 = and(UInt<1>(0h1), out_f_woready_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_196 = eq(out_rimask_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_197 = eq(out_wimask_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_198 = eq(out_romask_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_199 = eq(out_womask_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_14 = or(_out_T_190, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_14 = cat(oldBytes[7], _out_prepend_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_200 = or(out_prepend_14, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_201 = bits(_out_T_200, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T = bits(out_front.bits.index, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_9 = bits(out_front.bits.index, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_10 = bits(out_front.bits.index, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_11 = bits(out_front.bits.index, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_12 = bits(out_front.bits.index, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex = cat(_out_iindex_T_12, _out_iindex_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T = bits(out_front.bits.index, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_9 = bits(out_front.bits.index, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_10 = bits(out_front.bits.index, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_11 = bits(out_front.bits.index, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_12 = bits(out_front.bits.index, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex = cat(_out_oindex_T_12, _out_oindex_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node out_backSel_0 = bits(_out_backSel_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_1 = bits(_out_backSel_T, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_2 = bits(_out_backSel_T, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_3 = bits(_out_backSel_T, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T = and(in.valid, out_front.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[1], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[0], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[17], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[16], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[15], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[14], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[13], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[12], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[11], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[10], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_8 = eq(_out_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_2 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_2, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[9], _out_rifireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[8], _out_rifireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[7], _out_rifireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[6], _out_rifireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[5], _out_rifireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[4], _out_rifireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[3], _out_rifireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[2], _out_rifireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_12 = eq(_out_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_3 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_3, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_rifireMux_WIRE : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_wifireMux_T = and(in.valid, out_front.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[1], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[0], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[17], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[16], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[15], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[14], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[13], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[12], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[11], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[10], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_9 = eq(_out_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_2 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_2, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[9], _out_wifireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[8], _out_wifireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[7], _out_wifireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[6], _out_wifireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[5], _out_wifireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[4], _out_wifireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[3], _out_wifireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[2], _out_wifireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_13 = eq(_out_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_3 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_3, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_wifireMux_WIRE : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_rofireMux_T = and(out_front.valid, out.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[1], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[0], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[17], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[16], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[15], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[14], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[13], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[12], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[11], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[10], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_8 = eq(_out_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_2 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_2, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[9], _out_rofireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[8], _out_rofireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[7], _out_rofireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[6], _out_rofireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[5], _out_rofireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[4], _out_rofireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[3], _out_rofireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[2], _out_rofireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_12 = eq(_out_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_3 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_3, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_rofireMux_WIRE : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_wofireMux_T = and(out_front.valid, out.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[1], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[0], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[17], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[16], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[15], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[14], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[13], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[12], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[11], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[10], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_9 = eq(_out_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_2 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_2, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[9], _out_wofireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[8], _out_wofireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[7], _out_wofireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[6], _out_wofireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[5], _out_wofireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[4], _out_wofireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[3], _out_wofireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[2], _out_wofireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_13 = eq(_out_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_3 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_3, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_wofireMux_WIRE : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_in_ready_T = and(out_front.ready, out_iready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect in.ready, _out_in_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_front_valid_T = and(in.valid, out_iready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front.valid, _out_front_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_front_ready_T = and(out.ready, out_oready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front.ready, _out_front_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_out_valid_T = and(out_front.valid, out_oready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.valid, _out_out_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.read, out_front.bits.read @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_out_bits_data_WIRE : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[0], _out_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[1], _out_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[2], _out_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[3], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_out_bits_data_WIRE_1 : UInt<64>[4] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[0], _out_T_25 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[1], _out_T_201 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[2], _out_T_113 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.data, _out_out_bits_data_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.extra, out_front.bits.extra @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect in.valid, nodeIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 90:15] connect nodeIn.a.ready, in.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 91:15] connect nodeIn.d.valid, out.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 92:15] connect out.ready, nodeIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 93:15] wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 792:17] connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 793:15] connect nodeIn_d_bits_d.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 794:15] connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 795:15] connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 796:15] connect nodeIn_d_bits_d.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 797:15] connect nodeIn_d_bits_d.denied, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 798:15] invalidate nodeIn_d_bits_d.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 801:15] connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 802:15] connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.data, nodeIn_d_bits_d.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.source, nodeIn_d_bits_d.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.size, nodeIn_d_bits_d.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.param, nodeIn_d_bits_d.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.data, out.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 100:17] node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 105:25] connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 105:19] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<26>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 108:22] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<26>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 109:22] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 110:22] module AsyncResetRegVec_w2_i0 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 56:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 56:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 56:7] output io : { flip d : UInt<2>, q : UInt<2>, flip en : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 59:14] node _reg_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 61:29] regreset reg : UInt<2>, clock, _reg_T, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 61:50] when io.en : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 62:16] connect reg, io.d @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 63:9] connect io.q, reg @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 65:8] module IntSyncCrossingSource_n1x2 : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 41:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 41:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 41:9] output auto : { flip in : UInt<1>[2], out : { sync : UInt<1>[2]}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : UInt<1>[2] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { sync : UInt<1>[2]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.sync[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] node _T = cat(nodeIn[1], nodeIn[0]) @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 45:36] inst reg of AsyncResetRegVec_w2_i0 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 86:21] connect reg.clock, clock connect reg.reset, reset connect reg.io.d, _T @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 88:14] connect reg.io.en, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 89:15] node _T_1 = bits(reg.io.q, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 45:50] node _T_2 = bits(reg.io.q, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 45:50] connect nodeOut.sync[0], _T_1 @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 45:16] connect nodeOut.sync[1], _T_2 @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 45:16] module CLINTClockSinkDomain : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 14:9] output auto : { flip clint_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, int_in_clock_xing_out : { sync : UInt<1>[2]}, flip clock_in : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] input tick : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala 113:20] output clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 21:19] output reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 22:19] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] inst clint of CLINT @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala 110:48] connect clint.clock, childClock connect clint.reset, childReset inst intsource of IntSyncCrossingSource_n1x2 @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 29:31] connect intsource.clock, childClock connect intsource.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate clockNodeIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate clockNodeIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire intInClockXingOut : { sync : UInt<1>[2]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate intInClockXingOut.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate intInClockXingOut.sync[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire intInClockXingIn : { sync : UInt<1>[2]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate intInClockXingIn.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate intInClockXingIn.sync[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect intInClockXingOut, intInClockXingIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect intsource.auto.in[0], clint.auto.int_out[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect intsource.auto.in[1], clint.auto.int_out[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect intInClockXingIn, intsource.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect clockNodeIn, auto.clock_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.int_in_clock_xing_out, intInClockXingOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect clint.auto.in, auto.clint_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect clint.io.rtcTick, tick @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala 114:31] connect childClock, clockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 15:16] connect childReset, clockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 16:16] connect clock, clockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 23:11] connect reset, clockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 24:11] module LevelGateway : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] output io : { flip interrupt : UInt<1>, plic : { valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 32:14] regreset inFlight : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 37:25] node _T = and(io.interrupt, io.plic.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:22] when _T : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:40] connect inFlight, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:51] when io.plic.complete : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:27] connect inFlight, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:38] node _io_plic_valid_T = eq(inFlight, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:36] node _io_plic_valid_T_1 = and(io.interrupt, _io_plic_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:33] connect io.plic.valid, _io_plic_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:17] module LevelGateway_1 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] output io : { flip interrupt : UInt<1>, plic : { valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 32:14] regreset inFlight : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 37:25] node _T = and(io.interrupt, io.plic.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:22] when _T : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:40] connect inFlight, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:51] when io.plic.complete : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:27] connect inFlight, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:38] node _io_plic_valid_T = eq(inFlight, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:36] node _io_plic_valid_T_1 = and(io.interrupt, _io_plic_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:33] connect io.plic.valid, _io_plic_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:17] module LevelGateway_2 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] output io : { flip interrupt : UInt<1>, plic : { valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 32:14] regreset inFlight : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 37:25] node _T = and(io.interrupt, io.plic.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:22] when _T : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:40] connect inFlight, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:51] when io.plic.complete : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:27] connect inFlight, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:38] node _io_plic_valid_T = eq(inFlight, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:36] node _io_plic_valid_T_1 = and(io.interrupt, _io_plic_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:33] connect io.plic.valid, _io_plic_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:17] module LevelGateway_3 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] output io : { flip interrupt : UInt<1>, plic : { valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 32:14] regreset inFlight : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 37:25] node _T = and(io.interrupt, io.plic.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:22] when _T : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:40] connect inFlight, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:51] when io.plic.complete : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:27] connect inFlight, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:38] node _io_plic_valid_T = eq(inFlight, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:36] node _io_plic_valid_T_1 = and(io.interrupt, _io_plic_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:33] connect io.plic.valid, _io_plic_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:17] module LevelGateway_4 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] output io : { flip interrupt : UInt<1>, plic : { valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 32:14] regreset inFlight : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 37:25] node _T = and(io.interrupt, io.plic.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:22] when _T : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:40] connect inFlight, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:51] when io.plic.complete : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:27] connect inFlight, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:38] node _io_plic_valid_T = eq(inFlight, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:36] node _io_plic_valid_T_1 = and(io.interrupt, _io_plic_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:33] connect io.plic.valid, _io_plic_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:17] module LevelGateway_5 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] output io : { flip interrupt : UInt<1>, plic : { valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 32:14] regreset inFlight : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 37:25] node _T = and(io.interrupt, io.plic.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:22] when _T : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:40] connect inFlight, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:51] when io.plic.complete : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:27] connect inFlight, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:38] node _io_plic_valid_T = eq(inFlight, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:36] node _io_plic_valid_T_1 = and(io.interrupt, _io_plic_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:33] connect io.plic.valid, _io_plic_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:17] module LevelGateway_6 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] output io : { flip interrupt : UInt<1>, plic : { valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 32:14] regreset inFlight : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 37:25] node _T = and(io.interrupt, io.plic.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:22] when _T : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:40] connect inFlight, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:51] when io.plic.complete : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:27] connect inFlight, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:38] node _io_plic_valid_T = eq(inFlight, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:36] node _io_plic_valid_T_1 = and(io.interrupt, _io_plic_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:33] connect io.plic.valid, _io_plic_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:17] module LevelGateway_7 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] output io : { flip interrupt : UInt<1>, plic : { valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 32:14] regreset inFlight : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 37:25] node _T = and(io.interrupt, io.plic.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:22] when _T : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:40] connect inFlight, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:51] when io.plic.complete : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:27] connect inFlight, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:38] node _io_plic_valid_T = eq(inFlight, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:36] node _io_plic_valid_T_1 = and(io.interrupt, _io_plic_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:33] connect io.plic.valid, _io_plic_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:17] module LevelGateway_8 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] output io : { flip interrupt : UInt<1>, plic : { valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 32:14] regreset inFlight : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 37:25] node _T = and(io.interrupt, io.plic.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:22] when _T : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:40] connect inFlight, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:51] when io.plic.complete : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:27] connect inFlight, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:38] node _io_plic_valid_T = eq(inFlight, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:36] node _io_plic_valid_T_1 = and(io.interrupt, _io_plic_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:33] connect io.plic.valid, _io_plic_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:17] module LevelGateway_9 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] output io : { flip interrupt : UInt<1>, plic : { valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 32:14] regreset inFlight : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 37:25] node _T = and(io.interrupt, io.plic.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:22] when _T : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:40] connect inFlight, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:51] when io.plic.complete : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:27] connect inFlight, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:38] node _io_plic_valid_T = eq(inFlight, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:36] node _io_plic_valid_T_1 = and(io.interrupt, _io_plic_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:33] connect io.plic.valid, _io_plic_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:17] module LevelGateway_10 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 31:7] output io : { flip interrupt : UInt<1>, plic : { valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 32:14] regreset inFlight : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 37:25] node _T = and(io.interrupt, io.plic.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:22] when _T : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:40] connect inFlight, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 38:51] when io.plic.complete : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:27] connect inFlight, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 39:38] node _io_plic_valid_T = eq(inFlight, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:36] node _io_plic_valid_T_1 = and(io.interrupt, _io_plic_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:33] connect io.plic.valid, _io_plic_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 40:17] module PLICFanIn : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 336:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 336:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 336:7] output io : { flip prio : UInt<3>[11], flip ip : UInt<11>, dev : UInt<4>, max : UInt<3>} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 337:14] node effectivePriority_0 = shl(UInt<1>(0h1), 3) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:32] node _effectivePriority_T = bits(io.ip, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:55] node _effectivePriority_T_1 = bits(io.ip, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:55] node _effectivePriority_T_2 = bits(io.ip, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:55] node _effectivePriority_T_3 = bits(io.ip, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:55] node _effectivePriority_T_4 = bits(io.ip, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:55] node _effectivePriority_T_5 = bits(io.ip, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:55] node _effectivePriority_T_6 = bits(io.ip, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:55] node _effectivePriority_T_7 = bits(io.ip, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:55] node _effectivePriority_T_8 = bits(io.ip, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:55] node _effectivePriority_T_9 = bits(io.ip, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:55] node _effectivePriority_T_10 = bits(io.ip, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:55] node effectivePriority_1 = cat(_effectivePriority_T, io.prio[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:100] node effectivePriority_2 = cat(_effectivePriority_T_1, io.prio[1]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:100] node effectivePriority_3 = cat(_effectivePriority_T_2, io.prio[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:100] node effectivePriority_4 = cat(_effectivePriority_T_3, io.prio[3]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:100] node effectivePriority_5 = cat(_effectivePriority_T_4, io.prio[4]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:100] node effectivePriority_6 = cat(_effectivePriority_T_5, io.prio[5]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:100] node effectivePriority_7 = cat(_effectivePriority_T_6, io.prio[6]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:100] node effectivePriority_8 = cat(_effectivePriority_T_7, io.prio[7]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:100] node effectivePriority_9 = cat(_effectivePriority_T_8, io.prio[8]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:100] node effectivePriority_10 = cat(_effectivePriority_T_9, io.prio[9]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:100] node effectivePriority_11 = cat(_effectivePriority_T_10, io.prio[10]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 353:100] node _left_left_left_T = geq(effectivePriority_0, effectivePriority_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:20] node _left_left_left_T_1 = or(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:57] node left_left_left_1 = mux(_left_left_left_T, effectivePriority_0, effectivePriority_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node left_left_left_2 = mux(_left_left_left_T, UInt<1>(0h0), _left_left_left_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _left_left_right_T = geq(effectivePriority_2, effectivePriority_3) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:20] node _left_left_right_T_1 = or(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:57] node left_left_right_1 = mux(_left_left_right_T, effectivePriority_2, effectivePriority_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node left_left_right_2 = mux(_left_left_right_T, UInt<1>(0h0), _left_left_right_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _left_left_T = geq(left_left_left_1, left_left_right_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:20] node _left_left_T_1 = or(UInt<2>(0h2), left_left_right_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:57] node left_left_1 = mux(_left_left_T, left_left_left_1, left_left_right_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node left_left_2 = mux(_left_left_T, left_left_left_2, _left_left_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _left_right_left_T = geq(effectivePriority_4, effectivePriority_5) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:20] node _left_right_left_T_1 = or(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:57] node left_right_left_1 = mux(_left_right_left_T, effectivePriority_4, effectivePriority_5) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node left_right_left_2 = mux(_left_right_left_T, UInt<1>(0h0), _left_right_left_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _left_right_right_T = geq(effectivePriority_6, effectivePriority_7) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:20] node _left_right_right_T_1 = or(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:57] node left_right_right_1 = mux(_left_right_right_T, effectivePriority_6, effectivePriority_7) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node left_right_right_2 = mux(_left_right_right_T, UInt<1>(0h0), _left_right_right_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _left_right_T = geq(left_right_left_1, left_right_right_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:20] node _left_right_T_1 = or(UInt<2>(0h2), left_right_right_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:57] node left_right_1 = mux(_left_right_T, left_right_left_1, left_right_right_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node left_right_2 = mux(_left_right_T, left_right_left_2, _left_right_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _left_T = geq(left_left_1, left_right_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:20] node _left_T_1 = or(UInt<3>(0h4), left_right_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:57] node left_1 = mux(_left_T, left_left_1, left_right_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node left_2 = mux(_left_T, left_left_2, _left_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _right_left_T = geq(effectivePriority_8, effectivePriority_9) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:20] node _right_left_T_1 = or(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:57] node right_left_1 = mux(_right_left_T, effectivePriority_8, effectivePriority_9) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node right_left_2 = mux(_right_left_T, UInt<1>(0h0), _right_left_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _right_right_T = geq(effectivePriority_10, effectivePriority_11) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:20] node _right_right_T_1 = or(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:57] node right_right_1 = mux(_right_right_T, effectivePriority_10, effectivePriority_11) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node right_right_2 = mux(_right_right_T, UInt<1>(0h0), _right_right_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _right_T = geq(right_left_1, right_right_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:20] node _right_T_1 = or(UInt<2>(0h2), right_right_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:57] node right_1 = mux(_right_T, right_left_1, right_right_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node right_2 = mux(_right_T, right_left_2, _right_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] node _T = geq(left_1, right_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:20] node _T_1 = or(UInt<4>(0h8), right_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 349:57] node maxPri = mux(_T, left_1, right_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:9] node maxDev = mux(_T, left_2, _T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 35:36] connect io.max, maxPri @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 355:10] connect io.dev, maxDev @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 356:10] module Queue1_RegMapperInput_i23_m8 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegMapper.scala 71:32] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegMapper.scala 71:32] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegMapper.scala 71:32] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<23>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<23>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}}, count : UInt<1>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { read : UInt<1>, index : UInt<23>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}} [1] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] wire enq_ptr_value : UInt @[src/main/scala/chisel3/util/Counter.scala 61:73] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:73] wire deq_ptr_value : UInt @[src/main/scala/chisel3/util/Counter.scala 61:73] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:73] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] wire _WIRE : UInt @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect _WIRE, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 270:8] infer mport MPORT = ram[_WIRE], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT.extra, io.enq.bits.extra @[src/main/scala/chisel3/util/Decoupled.scala 270:24] connect MPORT.mask, io.enq.bits.mask @[src/main/scala/chisel3/util/Decoupled.scala 270:24] connect MPORT.data, io.enq.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 270:24] connect MPORT.index, io.enq.bits.index @[src/main/scala/chisel3/util/Decoupled.scala 270:24] connect MPORT.read, io.enq.bits.read @[src/main/scala/chisel3/util/Decoupled.scala 270:24] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] skip node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] wire _io_deq_bits_WIRE : UInt @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect _io_deq_bits_WIRE, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 293:23] infer mport io_deq_bits_MPORT = ram[_io_deq_bits_WIRE], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module TLPLIC : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 132:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 132:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 132:9] output auto : { flip int_in : UInt<1>[11], int_out : UInt<1>[1], flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire intnodeIn : UInt<1>[11] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate intnodeIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate intnodeIn[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate intnodeIn[2] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate intnodeIn[3] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate intnodeIn[4] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate intnodeIn[5] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate intnodeIn[6] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate intnodeIn[7] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate intnodeIn[8] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate intnodeIn[9] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate intnodeIn[10] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire intnodeOut : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate intnodeOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.int_out, intnodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect intnodeIn, auto.int_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] inst gateways_gateway of LevelGateway @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 158:27] connect gateways_gateway.clock, clock connect gateways_gateway.reset, reset connect gateways_gateway.io.interrupt, intnodeIn[0] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 159:28] inst gateways_gateway_1 of LevelGateway_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 158:27] connect gateways_gateway_1.clock, clock connect gateways_gateway_1.reset, reset connect gateways_gateway_1.io.interrupt, intnodeIn[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 159:28] inst gateways_gateway_2 of LevelGateway_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 158:27] connect gateways_gateway_2.clock, clock connect gateways_gateway_2.reset, reset connect gateways_gateway_2.io.interrupt, intnodeIn[2] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 159:28] inst gateways_gateway_3 of LevelGateway_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 158:27] connect gateways_gateway_3.clock, clock connect gateways_gateway_3.reset, reset connect gateways_gateway_3.io.interrupt, intnodeIn[3] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 159:28] inst gateways_gateway_4 of LevelGateway_4 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 158:27] connect gateways_gateway_4.clock, clock connect gateways_gateway_4.reset, reset connect gateways_gateway_4.io.interrupt, intnodeIn[4] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 159:28] inst gateways_gateway_5 of LevelGateway_5 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 158:27] connect gateways_gateway_5.clock, clock connect gateways_gateway_5.reset, reset connect gateways_gateway_5.io.interrupt, intnodeIn[5] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 159:28] inst gateways_gateway_6 of LevelGateway_6 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 158:27] connect gateways_gateway_6.clock, clock connect gateways_gateway_6.reset, reset connect gateways_gateway_6.io.interrupt, intnodeIn[6] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 159:28] inst gateways_gateway_7 of LevelGateway_7 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 158:27] connect gateways_gateway_7.clock, clock connect gateways_gateway_7.reset, reset connect gateways_gateway_7.io.interrupt, intnodeIn[7] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 159:28] inst gateways_gateway_8 of LevelGateway_8 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 158:27] connect gateways_gateway_8.clock, clock connect gateways_gateway_8.reset, reset connect gateways_gateway_8.io.interrupt, intnodeIn[8] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 159:28] inst gateways_gateway_9 of LevelGateway_9 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 158:27] connect gateways_gateway_9.clock, clock connect gateways_gateway_9.reset, reset connect gateways_gateway_9.io.interrupt, intnodeIn[9] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 159:28] inst gateways_gateway_10 of LevelGateway_10 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 158:27] connect gateways_gateway_10.clock, clock connect gateways_gateway_10.reset, reset connect gateways_gateway_10.io.interrupt, intnodeIn[10] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 159:28] reg priority : UInt<3>[11], clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 165:31] reg threshold : UInt<3>[1], clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 168:31] wire _pending_WIRE : UInt<1>[11] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 170:55] connect _pending_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 170:55] connect _pending_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 170:55] connect _pending_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 170:55] connect _pending_WIRE[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 170:55] connect _pending_WIRE[4], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 170:55] connect _pending_WIRE[5], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 170:55] connect _pending_WIRE[6], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 170:55] connect _pending_WIRE[7], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 170:55] connect _pending_WIRE[8], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 170:55] connect _pending_WIRE[9], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 170:55] connect _pending_WIRE[10], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 170:55] regreset pending : UInt<1>[11], clock, reset, _pending_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 170:26] reg enables_0_0 : UInt<7>, clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 176:26] reg enables_0_1 : UInt<4>, clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 178:51] node _enableVec_T = cat(enables_0_1, enables_0_0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 180:49] wire enableVec : UInt<11>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 180:28] connect enableVec[0], _enableVec_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 180:28] node _enableVec0_T = cat(enableVec[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 181:52] wire enableVec0 : UInt<12>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 181:29] connect enableVec0[0], _enableVec0_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 181:29] reg maxDevs : UInt<4>[1], clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 183:22] node pendingUInt_lo_lo = cat(pending[1], pending[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 184:26] node pendingUInt_lo_hi_hi = cat(pending[4], pending[3]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 184:26] node pendingUInt_lo_hi = cat(pendingUInt_lo_hi_hi, pending[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 184:26] node pendingUInt_lo = cat(pendingUInt_lo_hi, pendingUInt_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 184:26] node pendingUInt_hi_lo_hi = cat(pending[7], pending[6]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 184:26] node pendingUInt_hi_lo = cat(pendingUInt_hi_lo_hi, pending[5]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 184:26] node pendingUInt_hi_hi_hi = cat(pending[10], pending[9]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 184:26] node pendingUInt_hi_hi = cat(pendingUInt_hi_hi_hi, pending[8]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 184:26] node pendingUInt_hi = cat(pendingUInt_hi_hi, pendingUInt_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 184:26] node pendingUInt = cat(pendingUInt_hi, pendingUInt_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 184:26] inst fanin of PLICFanIn @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 187:27] connect fanin.clock, clock connect fanin.reset, reset connect fanin.io.prio[0], priority[0] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 188:23] connect fanin.io.prio[1], priority[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 188:23] connect fanin.io.prio[2], priority[2] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 188:23] connect fanin.io.prio[3], priority[3] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 188:23] connect fanin.io.prio[4], priority[4] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 188:23] connect fanin.io.prio[5], priority[5] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 188:23] connect fanin.io.prio[6], priority[6] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 188:23] connect fanin.io.prio[7], priority[7] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 188:23] connect fanin.io.prio[8], priority[8] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 188:23] connect fanin.io.prio[9], priority[9] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 188:23] connect fanin.io.prio[10], priority[10] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 188:23] node _fanin_io_ip_T = and(enableVec[0], pendingUInt) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 189:40] connect fanin.io.ip, _fanin_io_ip_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 189:21] connect maxDevs[0], fanin.io.dev @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 190:23] reg intnodeOut_0_REG : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 191:45] connect intnodeOut_0_REG, fanin.io.max @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 191:45] node _intnodeOut_0_T = gt(intnodeOut_0_REG, threshold[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 191:60] connect intnodeOut[0], _intnodeOut_0_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 191:21] wire claimer : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 248:23] node _T = sub(claimer[0], UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 249:46] node _T_1 = tail(_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 249:46] node _T_2 = and(claimer[0], _T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 249:28] node _T_3 = eq(_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 249:54] node _T_4 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 249:11] node _T_5 = eq(_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 249:11] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 249:11] node _T_6 = eq(_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 249:11] when _T_6 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 249:11] printf(clock, UInt<1>(0h1), "Assertion failed\n at Plic.scala:249 assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 249:11] assert(clock, _T_3, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 249:11] node claiming = mux(claimer[0], maxDevs[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 250:49] node claimedDevs_shiftAmount = bits(claiming, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _claimedDevs_T = dshl(UInt<1>(0h1), claimedDevs_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _claimedDevs_T_1 = bits(_claimedDevs_T, 11, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node _claimedDevs_T_2 = bits(_claimedDevs_T_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:62] node _claimedDevs_T_3 = bits(_claimedDevs_T_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:62] node _claimedDevs_T_4 = bits(_claimedDevs_T_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:62] node _claimedDevs_T_5 = bits(_claimedDevs_T_1, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:62] node _claimedDevs_T_6 = bits(_claimedDevs_T_1, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:62] node _claimedDevs_T_7 = bits(_claimedDevs_T_1, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:62] node _claimedDevs_T_8 = bits(_claimedDevs_T_1, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:62] node _claimedDevs_T_9 = bits(_claimedDevs_T_1, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:62] node _claimedDevs_T_10 = bits(_claimedDevs_T_1, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:62] node _claimedDevs_T_11 = bits(_claimedDevs_T_1, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:62] node _claimedDevs_T_12 = bits(_claimedDevs_T_1, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:62] node _claimedDevs_T_13 = bits(_claimedDevs_T_1, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:62] wire claimedDevs : UInt<1>[12] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:30] connect claimedDevs[0], _claimedDevs_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:30] connect claimedDevs[1], _claimedDevs_T_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:30] connect claimedDevs[2], _claimedDevs_T_4 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:30] connect claimedDevs[3], _claimedDevs_T_5 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:30] connect claimedDevs[4], _claimedDevs_T_6 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:30] connect claimedDevs[5], _claimedDevs_T_7 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:30] connect claimedDevs[6], _claimedDevs_T_8 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:30] connect claimedDevs[7], _claimedDevs_T_9 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:30] connect claimedDevs[8], _claimedDevs_T_10 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:30] connect claimedDevs[9], _claimedDevs_T_11 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:30] connect claimedDevs[10], _claimedDevs_T_12 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:30] connect claimedDevs[11], _claimedDevs_T_13 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 251:30] node _gateway_io_plic_ready_T = eq(pending[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:18] connect gateways_gateway.io.plic.ready, _gateway_io_plic_ready_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:15] node _T_7 = or(claimedDevs[1], gateways_gateway.io.plic.valid) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:15] when _T_7 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:27] node _pending_0_T = eq(claimedDevs[1], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:34] connect pending[0], _pending_0_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:31] node _gateway_io_plic_ready_T_1 = eq(pending[1], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:18] connect gateways_gateway_1.io.plic.ready, _gateway_io_plic_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:15] node _T_8 = or(claimedDevs[2], gateways_gateway_1.io.plic.valid) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:15] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:27] node _pending_1_T = eq(claimedDevs[2], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:34] connect pending[1], _pending_1_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:31] node _gateway_io_plic_ready_T_2 = eq(pending[2], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:18] connect gateways_gateway_2.io.plic.ready, _gateway_io_plic_ready_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:15] node _T_9 = or(claimedDevs[3], gateways_gateway_2.io.plic.valid) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:15] when _T_9 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:27] node _pending_2_T = eq(claimedDevs[3], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:34] connect pending[2], _pending_2_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:31] node _gateway_io_plic_ready_T_3 = eq(pending[3], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:18] connect gateways_gateway_3.io.plic.ready, _gateway_io_plic_ready_T_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:15] node _T_10 = or(claimedDevs[4], gateways_gateway_3.io.plic.valid) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:15] when _T_10 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:27] node _pending_3_T = eq(claimedDevs[4], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:34] connect pending[3], _pending_3_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:31] node _gateway_io_plic_ready_T_4 = eq(pending[4], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:18] connect gateways_gateway_4.io.plic.ready, _gateway_io_plic_ready_T_4 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:15] node _T_11 = or(claimedDevs[5], gateways_gateway_4.io.plic.valid) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:15] when _T_11 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:27] node _pending_4_T = eq(claimedDevs[5], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:34] connect pending[4], _pending_4_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:31] node _gateway_io_plic_ready_T_5 = eq(pending[5], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:18] connect gateways_gateway_5.io.plic.ready, _gateway_io_plic_ready_T_5 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:15] node _T_12 = or(claimedDevs[6], gateways_gateway_5.io.plic.valid) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:15] when _T_12 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:27] node _pending_5_T = eq(claimedDevs[6], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:34] connect pending[5], _pending_5_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:31] node _gateway_io_plic_ready_T_6 = eq(pending[6], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:18] connect gateways_gateway_6.io.plic.ready, _gateway_io_plic_ready_T_6 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:15] node _T_13 = or(claimedDevs[7], gateways_gateway_6.io.plic.valid) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:15] when _T_13 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:27] node _pending_6_T = eq(claimedDevs[7], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:34] connect pending[6], _pending_6_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:31] node _gateway_io_plic_ready_T_7 = eq(pending[7], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:18] connect gateways_gateway_7.io.plic.ready, _gateway_io_plic_ready_T_7 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:15] node _T_14 = or(claimedDevs[8], gateways_gateway_7.io.plic.valid) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:15] when _T_14 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:27] node _pending_7_T = eq(claimedDevs[8], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:34] connect pending[7], _pending_7_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:31] node _gateway_io_plic_ready_T_8 = eq(pending[8], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:18] connect gateways_gateway_8.io.plic.ready, _gateway_io_plic_ready_T_8 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:15] node _T_15 = or(claimedDevs[9], gateways_gateway_8.io.plic.valid) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:15] when _T_15 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:27] node _pending_8_T = eq(claimedDevs[9], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:34] connect pending[8], _pending_8_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:31] node _gateway_io_plic_ready_T_9 = eq(pending[9], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:18] connect gateways_gateway_9.io.plic.ready, _gateway_io_plic_ready_T_9 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:15] node _T_16 = or(claimedDevs[10], gateways_gateway_9.io.plic.valid) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:15] when _T_16 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:27] node _pending_9_T = eq(claimedDevs[10], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:34] connect pending[9], _pending_9_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:31] node _gateway_io_plic_ready_T_10 = eq(pending[10], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:18] connect gateways_gateway_10.io.plic.ready, _gateway_io_plic_ready_T_10 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 254:15] node _T_17 = or(claimedDevs[11], gateways_gateway_10.io.plic.valid) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:15] when _T_17 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:27] node _pending_10_T = eq(claimedDevs[11], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:34] connect pending[10], _pending_10_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 255:31] wire completer : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 265:25] node _T_18 = sub(completer[0], UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 266:50] node _T_19 = tail(_T_18, 1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 266:50] node _T_20 = and(completer[0], _T_19) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 266:30] node _T_21 = eq(_T_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 266:58] node _T_22 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 266:11] node _T_23 = eq(_T_22, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 266:11] when _T_23 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 266:11] node _T_24 = eq(_T_21, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 266:11] when _T_24 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 266:11] printf(clock, UInt<1>(0h1), "Assertion failed\n at Plic.scala:266 assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 266:11] assert(clock, _T_21, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 266:11] wire completerDev : UInt<4> @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 267:28] node completedDevs_shiftAmount = bits(completerDev, 3, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _completedDevs_T = dshl(UInt<1>(0h1), completedDevs_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _completedDevs_T_1 = bits(_completedDevs_T, 11, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node completedDevs = mux(completer[0], _completedDevs_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 268:28] node _T_25 = bits(completedDevs, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 269:33] node _T_26 = bits(completedDevs, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 269:33] node _T_27 = bits(completedDevs, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 269:33] node _T_28 = bits(completedDevs, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 269:33] node _T_29 = bits(completedDevs, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 269:33] node _T_30 = bits(completedDevs, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 269:33] node _T_31 = bits(completedDevs, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 269:33] node _T_32 = bits(completedDevs, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 269:33] node _T_33 = bits(completedDevs, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 269:33] node _T_34 = bits(completedDevs, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 269:33] node _T_35 = bits(completedDevs, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 269:33] node _T_36 = bits(completedDevs, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 269:33] connect gateways_gateway.io.plic.complete, _T_26 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 270:19] connect gateways_gateway_1.io.plic.complete, _T_27 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 270:19] connect gateways_gateway_2.io.plic.complete, _T_28 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 270:19] connect gateways_gateway_3.io.plic.complete, _T_29 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 270:19] connect gateways_gateway_4.io.plic.complete, _T_30 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 270:19] connect gateways_gateway_5.io.plic.complete, _T_31 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 270:19] connect gateways_gateway_6.io.plic.complete, _T_32 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 270:19] connect gateways_gateway_7.io.plic.complete, _T_33 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 270:19] connect gateways_gateway_8.io.plic.complete, _T_34 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 270:19] connect gateways_gateway_9.io.plic.complete, _T_35 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 270:19] connect gateways_gateway_10.io.plic.complete, _T_36 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 270:19] wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<23>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 73:18] node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 74:36] connect in.bits.read, _in_bits_read_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 74:19] node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 192:34] connect in.bits.index, _in_bits_index_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 75:19] connect in.bits.data, nodeIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 76:19] connect in.bits.mask, nodeIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 77:19] connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 83:20] connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 84:20] wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<23>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front.bits, in.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] inst out_back_front_q of Queue1_RegMapperInput_i23_m8 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_back_front_q.clock, clock connect out_back_front_q.reset, reset connect out_back_front_q.io.enq, out_front @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_maskMatch = not(UInt<23>(0h40607)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_findex = and(out_front.bits.index, out_maskMatch) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_bindex = and(out_back_front_q.io.deq.bits.index, out_maskMatch) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T = eq(out_findex, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1 = eq(out_bindex, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2 = eq(out_findex, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3 = eq(out_bindex, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4 = eq(out_findex, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5 = eq(out_bindex, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6 = eq(out_findex, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7 = eq(out_bindex, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8 = eq(out_findex, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9 = eq(out_bindex, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10 = eq(out_findex, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11 = eq(out_bindex, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12 = eq(out_findex, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_13 = eq(out_bindex, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_14 = eq(out_findex, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_15 = eq(out_bindex, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_16 = eq(out_findex, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_17 = eq(out_bindex, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rivalid : UInt<1>[29] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wivalid : UInt<1>[29] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_roready : UInt<1>[29] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_woready : UInt<1>[29] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T = bits(out_back_front_q.io.deq.bits.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_1 = bits(out_back_front_q.io.deq.bits.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_2 = bits(out_back_front_q.io.deq.bits.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_3 = bits(out_back_front_q.io.deq.bits.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_4 = bits(out_back_front_q.io.deq.bits.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_5 = bits(out_back_front_q.io.deq.bits.mask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_6 = bits(out_back_front_q.io.deq.bits.mask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_7 = bits(out_back_front_q.io.deq.bits.mask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask = cat(out_backMask_hi, out_backMask_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T = bits(out_frontMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask = orr(_out_rimask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T = bits(out_frontMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask = andr(_out_wimask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T = bits(out_backMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask = orr(_out_romask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T = bits(out_backMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask = andr(_out_womask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid = and(out_rivalid[0], out_rimask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready = and(out_roready[0], out_romask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid = and(out_wivalid[0], out_wimask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready = and(out_woready[0], out_womask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_18 = bits(out_back_front_q.io.deq.bits.data, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect priority[9], _out_T_18 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_19 = and(out_f_rivalid, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_20 = and(UInt<1>(0h1), out_f_roready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_21 = and(out_f_wivalid, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_22 = and(UInt<1>(0h1), out_f_woready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_23 = eq(out_rimask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_24 = eq(out_wimask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_25 = eq(out_romask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_26 = eq(out_womask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_27 = or(priority[9], UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_28 = bits(_out_T_27, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1 = bits(out_frontMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1 = orr(_out_rimask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1 = bits(out_frontMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1 = andr(_out_wimask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1 = bits(out_backMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1 = orr(_out_romask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1 = bits(out_backMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1 = andr(_out_womask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1 = and(out_roready[1], out_romask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1 = and(out_woready[1], out_womask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_29 = bits(out_back_front_q.io.deq.bits.data, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect priority[10], _out_T_29 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_30 = and(out_f_rivalid_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_31 = and(UInt<1>(0h1), out_f_roready_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_32 = and(out_f_wivalid_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_33 = and(UInt<1>(0h1), out_f_woready_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_34 = eq(out_rimask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_35 = eq(out_wimask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_36 = eq(out_romask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_37 = eq(out_womask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T = or(_out_T_28, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend = cat(priority[10], _out_prepend_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_38 = or(out_prepend, UInt<35>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_39 = bits(_out_T_38, 34, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_2 = bits(out_frontMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_2 = orr(_out_rimask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_2 = bits(out_frontMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_2 = andr(_out_wimask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_2 = bits(out_backMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_2 = orr(_out_romask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_2 = bits(out_backMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_2 = andr(_out_womask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_2 = and(out_roready[2], out_romask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_2 = and(out_woready[2], out_womask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_40 = bits(out_back_front_q.io.deq.bits.data, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_2 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect priority[1], _out_T_40 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_41 = and(out_f_rivalid_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_42 = and(UInt<1>(0h1), out_f_roready_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_43 = and(out_f_wivalid_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_44 = and(UInt<1>(0h1), out_f_woready_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_45 = eq(out_rimask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_46 = eq(out_wimask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_47 = eq(out_romask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_48 = eq(out_womask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_49 = or(priority[1], UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_50 = bits(_out_T_49, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_3 = bits(out_frontMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_3 = orr(_out_rimask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_3 = bits(out_frontMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_3 = andr(_out_wimask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_3 = bits(out_backMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_3 = orr(_out_romask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_3 = bits(out_backMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_3 = andr(_out_womask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_3 = and(out_roready[3], out_romask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_3 = and(out_woready[3], out_womask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_51 = bits(out_back_front_q.io.deq.bits.data, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_3 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect priority[2], _out_T_51 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_52 = and(out_f_rivalid_3, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_53 = and(UInt<1>(0h1), out_f_roready_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_54 = and(out_f_wivalid_3, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_55 = and(UInt<1>(0h1), out_f_woready_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_56 = eq(out_rimask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_57 = eq(out_wimask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_58 = eq(out_romask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_59 = eq(out_womask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1 = or(_out_T_50, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1 = cat(priority[2], _out_prepend_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_60 = or(out_prepend_1, UInt<35>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_61 = bits(_out_T_60, 34, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_4 = bits(out_frontMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_4 = orr(_out_rimask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_4 = bits(out_frontMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_4 = andr(_out_wimask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_4 = bits(out_backMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_4 = orr(_out_romask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_4 = bits(out_backMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_4 = andr(_out_womask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_4 = and(out_roready[4], out_romask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_4 = and(out_woready[4], out_womask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_62 = bits(out_back_front_q.io.deq.bits.data, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_63 = and(out_f_rivalid_4, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_64 = and(UInt<1>(0h1), out_f_roready_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_65 = eq(out_rimask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_66 = eq(out_wimask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_67 = eq(out_romask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_68 = eq(out_womask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_69 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_70 = bits(_out_T_69, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_5 = bits(out_frontMask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_5 = orr(_out_rimask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_5 = bits(out_frontMask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_5 = andr(_out_wimask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_5 = bits(out_backMask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_5 = orr(_out_romask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_5 = bits(out_backMask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_5 = andr(_out_womask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_5 = and(out_roready[5], out_romask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_5 = and(out_woready[5], out_womask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_71 = bits(out_back_front_q.io.deq.bits.data, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_72 = and(out_f_rivalid_5, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_73 = and(UInt<1>(0h1), out_f_roready_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_74 = eq(out_rimask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_75 = eq(out_wimask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_76 = eq(out_romask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_77 = eq(out_womask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_2 = or(_out_T_70, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_2 = cat(pending[0], _out_prepend_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_78 = or(out_prepend_2, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_79 = bits(_out_T_78, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_6 = bits(out_frontMask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_6 = orr(_out_rimask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_6 = bits(out_frontMask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_6 = andr(_out_wimask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_6 = bits(out_backMask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_6 = orr(_out_romask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_6 = bits(out_backMask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_6 = andr(_out_womask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_6 = and(out_roready[6], out_romask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_6 = and(out_woready[6], out_womask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_80 = bits(out_back_front_q.io.deq.bits.data, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_81 = and(out_f_rivalid_6, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_82 = and(UInt<1>(0h1), out_f_roready_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_83 = eq(out_rimask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_84 = eq(out_wimask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_85 = eq(out_romask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_86 = eq(out_womask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_3 = or(_out_T_79, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_3 = cat(pending[1], _out_prepend_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_87 = or(out_prepend_3, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_88 = bits(_out_T_87, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_7 = bits(out_frontMask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_7 = orr(_out_rimask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_7 = bits(out_frontMask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_7 = andr(_out_wimask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_7 = bits(out_backMask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_7 = orr(_out_romask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_7 = bits(out_backMask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_7 = andr(_out_womask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_7 = and(out_roready[7], out_romask_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_7 = and(out_woready[7], out_womask_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_89 = bits(out_back_front_q.io.deq.bits.data, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_90 = and(out_f_rivalid_7, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_91 = and(UInt<1>(0h1), out_f_roready_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_92 = eq(out_rimask_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_93 = eq(out_wimask_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_94 = eq(out_romask_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_95 = eq(out_womask_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_4 = or(_out_T_88, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_4 = cat(pending[2], _out_prepend_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_96 = or(out_prepend_4, UInt<4>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_97 = bits(_out_T_96, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_8 = bits(out_frontMask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_8 = orr(_out_rimask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_8 = bits(out_frontMask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_8 = andr(_out_wimask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_8 = bits(out_backMask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_8 = orr(_out_romask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_8 = bits(out_backMask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_8 = andr(_out_womask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_8 = and(out_roready[8], out_romask_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_8 = and(out_woready[8], out_womask_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_98 = bits(out_back_front_q.io.deq.bits.data, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_99 = and(out_f_rivalid_8, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_100 = and(UInt<1>(0h1), out_f_roready_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_101 = eq(out_rimask_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_102 = eq(out_wimask_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_103 = eq(out_romask_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_104 = eq(out_womask_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_5 = or(_out_T_97, UInt<4>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_5 = cat(pending[3], _out_prepend_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_105 = or(out_prepend_5, UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_106 = bits(_out_T_105, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_9 = bits(out_frontMask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_9 = orr(_out_rimask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_9 = bits(out_frontMask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_9 = andr(_out_wimask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_9 = bits(out_backMask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_9 = orr(_out_romask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_9 = bits(out_backMask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_9 = andr(_out_womask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_9 = and(out_roready[9], out_romask_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_9 = and(out_woready[9], out_womask_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_107 = bits(out_back_front_q.io.deq.bits.data, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_108 = and(out_f_rivalid_9, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_109 = and(UInt<1>(0h1), out_f_roready_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_110 = eq(out_rimask_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_111 = eq(out_wimask_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_112 = eq(out_romask_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_113 = eq(out_womask_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_6 = or(_out_T_106, UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_6 = cat(pending[4], _out_prepend_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_114 = or(out_prepend_6, UInt<6>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_115 = bits(_out_T_114, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_10 = bits(out_frontMask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_10 = orr(_out_rimask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_10 = bits(out_frontMask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_10 = andr(_out_wimask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_10 = bits(out_backMask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_10 = orr(_out_romask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_10 = bits(out_backMask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_10 = andr(_out_womask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_10 = and(out_roready[10], out_romask_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_10 = and(out_woready[10], out_womask_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_116 = bits(out_back_front_q.io.deq.bits.data, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_117 = and(out_f_rivalid_10, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_118 = and(UInt<1>(0h1), out_f_roready_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_119 = eq(out_rimask_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_120 = eq(out_wimask_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_121 = eq(out_romask_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_122 = eq(out_womask_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_7 = or(_out_T_115, UInt<6>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_7 = cat(pending[5], _out_prepend_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_123 = or(out_prepend_7, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_124 = bits(_out_T_123, 6, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_11 = bits(out_frontMask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_11 = orr(_out_rimask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_11 = bits(out_frontMask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_11 = andr(_out_wimask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_11 = bits(out_backMask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_11 = orr(_out_romask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_11 = bits(out_backMask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_11 = andr(_out_womask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_11 = and(out_roready[11], out_romask_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_11 = and(out_woready[11], out_womask_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_125 = bits(out_back_front_q.io.deq.bits.data, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_126 = and(out_f_rivalid_11, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_127 = and(UInt<1>(0h1), out_f_roready_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_128 = eq(out_rimask_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_129 = eq(out_wimask_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_130 = eq(out_romask_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_131 = eq(out_womask_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_8 = or(_out_T_124, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_8 = cat(pending[6], _out_prepend_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_132 = or(out_prepend_8, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_133 = bits(_out_T_132, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_12 = bits(out_frontMask, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_12 = orr(_out_rimask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_12 = bits(out_frontMask, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_12 = andr(_out_wimask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_12 = bits(out_backMask, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_12 = orr(_out_romask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_12 = bits(out_backMask, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_12 = andr(_out_womask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_12 = and(out_roready[12], out_romask_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_12 = and(out_woready[12], out_womask_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_134 = bits(out_back_front_q.io.deq.bits.data, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_135 = and(out_f_rivalid_12, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_136 = and(UInt<1>(0h1), out_f_roready_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_137 = eq(out_rimask_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_138 = eq(out_wimask_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_139 = eq(out_romask_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_140 = eq(out_womask_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_9 = or(_out_T_133, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_9 = cat(pending[7], _out_prepend_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_141 = or(out_prepend_9, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_142 = bits(_out_T_141, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_13 = bits(out_frontMask, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_13 = orr(_out_rimask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_13 = bits(out_frontMask, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_13 = andr(_out_wimask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_13 = bits(out_backMask, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_13 = orr(_out_romask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_13 = bits(out_backMask, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_13 = andr(_out_womask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_13 = and(out_roready[13], out_romask_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_13 = and(out_woready[13], out_womask_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_143 = bits(out_back_front_q.io.deq.bits.data, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_144 = and(out_f_rivalid_13, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_145 = and(UInt<1>(0h1), out_f_roready_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_146 = eq(out_rimask_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_147 = eq(out_wimask_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_148 = eq(out_romask_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_149 = eq(out_womask_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_10 = or(_out_T_142, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_10 = cat(pending[8], _out_prepend_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_150 = or(out_prepend_10, UInt<10>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_151 = bits(_out_T_150, 9, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_14 = bits(out_frontMask, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_14 = orr(_out_rimask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_14 = bits(out_frontMask, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_14 = andr(_out_wimask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_14 = bits(out_backMask, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_14 = orr(_out_romask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_14 = bits(out_backMask, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_14 = andr(_out_womask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_14 = and(out_roready[14], out_romask_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_14 = and(out_woready[14], out_womask_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_152 = bits(out_back_front_q.io.deq.bits.data, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_153 = and(out_f_rivalid_14, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_154 = and(UInt<1>(0h1), out_f_roready_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_155 = eq(out_rimask_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_156 = eq(out_wimask_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_157 = eq(out_romask_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_158 = eq(out_womask_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_11 = or(_out_T_151, UInt<10>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_11 = cat(pending[9], _out_prepend_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_159 = or(out_prepend_11, UInt<11>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_160 = bits(_out_T_159, 10, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_15 = bits(out_frontMask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_15 = orr(_out_rimask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_15 = bits(out_frontMask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_15 = andr(_out_wimask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_15 = bits(out_backMask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_15 = orr(_out_romask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_15 = bits(out_backMask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_15 = andr(_out_womask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_15 = and(out_roready[15], out_romask_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_15 = and(out_woready[15], out_womask_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_161 = bits(out_back_front_q.io.deq.bits.data, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_162 = and(out_f_rivalid_15, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_163 = and(UInt<1>(0h1), out_f_roready_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_164 = eq(out_rimask_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_165 = eq(out_wimask_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_166 = eq(out_romask_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_167 = eq(out_womask_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_12 = or(_out_T_160, UInt<11>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_12 = cat(pending[10], _out_prepend_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_168 = or(out_prepend_12, UInt<12>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_169 = bits(_out_T_168, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_16 = bits(out_frontMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_16 = orr(_out_rimask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_16 = bits(out_frontMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_16 = andr(_out_wimask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_16 = bits(out_backMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_16 = orr(_out_romask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_16 = bits(out_backMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_16 = andr(_out_womask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_16 = and(out_rivalid[16], out_rimask_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_16 = and(out_roready[16], out_romask_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_16 = and(out_wivalid[16], out_wimask_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_16 = and(out_woready[16], out_womask_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_170 = bits(out_back_front_q.io.deq.bits.data, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_16 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect priority[3], _out_T_170 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_171 = and(out_f_rivalid_16, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_172 = and(UInt<1>(0h1), out_f_roready_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_173 = and(out_f_wivalid_16, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_174 = and(UInt<1>(0h1), out_f_woready_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_175 = eq(out_rimask_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_176 = eq(out_wimask_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_177 = eq(out_romask_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_178 = eq(out_womask_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_179 = or(priority[3], UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_180 = bits(_out_T_179, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_17 = bits(out_frontMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_17 = orr(_out_rimask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_17 = bits(out_frontMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_17 = andr(_out_wimask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_17 = bits(out_backMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_17 = orr(_out_romask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_17 = bits(out_backMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_17 = andr(_out_womask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_17 = and(out_rivalid[17], out_rimask_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_17 = and(out_roready[17], out_romask_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_17 = and(out_wivalid[17], out_wimask_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_17 = and(out_woready[17], out_womask_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_181 = bits(out_back_front_q.io.deq.bits.data, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_17 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect priority[4], _out_T_181 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_182 = and(out_f_rivalid_17, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_183 = and(UInt<1>(0h1), out_f_roready_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_184 = and(out_f_wivalid_17, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_185 = and(UInt<1>(0h1), out_f_woready_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_186 = eq(out_rimask_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_187 = eq(out_wimask_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_188 = eq(out_romask_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_189 = eq(out_womask_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_13 = or(_out_T_180, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_13 = cat(priority[4], _out_prepend_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_190 = or(out_prepend_13, UInt<35>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_191 = bits(_out_T_190, 34, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_18 = bits(out_frontMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_18 = orr(_out_rimask_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_18 = bits(out_frontMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_18 = andr(_out_wimask_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_18 = bits(out_backMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_18 = orr(_out_romask_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_18 = bits(out_backMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_18 = andr(_out_womask_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_18 = and(out_rivalid[18], out_rimask_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_18 = and(out_roready[18], out_romask_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_18 = and(out_wivalid[18], out_wimask_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_18 = and(out_woready[18], out_womask_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_192 = bits(out_back_front_q.io.deq.bits.data, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_18 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect priority[5], _out_T_192 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_193 = and(out_f_rivalid_18, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_194 = and(UInt<1>(0h1), out_f_roready_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_195 = and(out_f_wivalid_18, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_196 = and(UInt<1>(0h1), out_f_woready_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_197 = eq(out_rimask_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_198 = eq(out_wimask_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_199 = eq(out_romask_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_200 = eq(out_womask_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_201 = or(priority[5], UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_202 = bits(_out_T_201, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_19 = bits(out_frontMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_19 = orr(_out_rimask_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_19 = bits(out_frontMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_19 = andr(_out_wimask_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_19 = bits(out_backMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_19 = orr(_out_romask_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_19 = bits(out_backMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_19 = andr(_out_womask_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_19 = and(out_rivalid[19], out_rimask_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_19 = and(out_roready[19], out_romask_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_19 = and(out_wivalid[19], out_wimask_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_19 = and(out_woready[19], out_womask_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_203 = bits(out_back_front_q.io.deq.bits.data, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_19 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect priority[6], _out_T_203 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_204 = and(out_f_rivalid_19, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_205 = and(UInt<1>(0h1), out_f_roready_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_206 = and(out_f_wivalid_19, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_207 = and(UInt<1>(0h1), out_f_woready_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_208 = eq(out_rimask_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_209 = eq(out_wimask_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_210 = eq(out_romask_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_211 = eq(out_womask_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_14 = or(_out_T_202, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_14 = cat(priority[6], _out_prepend_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_212 = or(out_prepend_14, UInt<35>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_213 = bits(_out_T_212, 34, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_20 = bits(out_frontMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_20 = orr(_out_rimask_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_20 = bits(out_frontMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_20 = andr(_out_wimask_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_20 = bits(out_backMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_20 = orr(_out_romask_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_20 = bits(out_backMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_20 = andr(_out_womask_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_20 = and(out_rivalid[20], out_rimask_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_20 = and(out_roready[20], out_romask_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_20 = and(out_wivalid[20], out_wimask_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_20 = and(out_woready[20], out_womask_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_214 = bits(out_back_front_q.io.deq.bits.data, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_20 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect threshold[0], _out_T_214 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_215 = and(out_f_rivalid_20, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_216 = and(UInt<1>(0h1), out_f_roready_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_217 = and(out_f_wivalid_20, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_218 = and(UInt<1>(0h1), out_f_woready_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_219 = eq(out_rimask_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_220 = eq(out_wimask_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_221 = eq(out_romask_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_222 = eq(out_womask_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_223 = or(threshold[0], UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_224 = bits(_out_T_223, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_21 = bits(out_frontMask, 31, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_21 = orr(_out_rimask_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_21 = bits(out_frontMask, 31, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_21 = andr(_out_wimask_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_21 = bits(out_backMask, 31, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_21 = orr(_out_romask_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_21 = bits(out_backMask, 31, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_21 = andr(_out_womask_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_21 = and(out_rivalid[21], out_rimask_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_21 = and(out_roready[21], out_romask_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_21 = and(out_wivalid[21], out_wimask_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_21 = and(out_woready[21], out_womask_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_225 = bits(out_back_front_q.io.deq.bits.data, 31, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_226 = and(out_f_rivalid_21, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_227 = and(UInt<1>(0h1), out_f_roready_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_228 = eq(out_rimask_21, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_229 = eq(out_wimask_21, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_230 = eq(out_romask_21, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_231 = eq(out_womask_21, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_15 = or(_out_T_224, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_15 = cat(UInt<1>(0h0), _out_prepend_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_232 = or(out_prepend_15, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_233 = bits(_out_T_232, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_22 = bits(out_frontMask, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_22 = orr(_out_rimask_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_22 = bits(out_frontMask, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_22 = andr(_out_wimask_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_22 = bits(out_backMask, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_22 = orr(_out_romask_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_22 = bits(out_backMask, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_22 = andr(_out_womask_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_22 = and(out_rivalid[22], out_rimask_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_22 = and(out_roready[22], out_romask_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_22 = and(out_wivalid[22], out_wimask_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_22 = and(out_woready[22], out_womask_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect claimer[0], out_f_roready_22 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 292:24] node _out_T_234 = bits(out_back_front_q.io.deq.bits.data, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_235 = bits(_out_T_234, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] node _out_T_236 = eq(completerDev, _out_T_235) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 296:33] node _out_T_237 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 296:19] node _out_T_238 = eq(_out_T_237, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 296:19] when _out_T_238 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 296:19] node _out_T_239 = eq(_out_T_236, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 296:19] when _out_T_239 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 296:19] printf(clock, UInt<1>(0h1), "Assertion failed: completerDev should be consistent for all harts\n at Plic.scala:296 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n") : out_printf @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 296:19] assert(clock, _out_T_236, UInt<1>(0h1), "") : out_assert @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 296:19] node _out_completerDev_T = bits(_out_T_234, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 164:13] connect completerDev, _out_completerDev_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 298:26] node _out_completer_0_T = dshr(enableVec0[0], completerDev) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 299:51] node _out_completer_0_T_1 = bits(_out_completer_0_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 299:51] node _out_completer_0_T_2 = and(out_f_woready_22, _out_completer_0_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 299:35] connect completer[0], _out_completer_0_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 299:26] node _out_T_240 = and(out_f_rivalid_22, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_241 = and(UInt<1>(0h1), out_f_roready_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_242 = and(out_f_wivalid_22, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_243 = and(UInt<1>(0h1), out_f_woready_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_244 = eq(out_rimask_22, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_245 = eq(out_wimask_22, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_246 = eq(out_romask_22, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_247 = eq(out_womask_22, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_16 = or(_out_T_233, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_16 = cat(maxDevs[0], _out_prepend_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_248 = or(out_prepend_16, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_249 = bits(_out_T_248, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_23 = bits(out_frontMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_23 = orr(_out_rimask_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_23 = bits(out_frontMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_23 = andr(_out_wimask_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_23 = bits(out_backMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_23 = orr(_out_romask_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_23 = bits(out_backMask, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_23 = andr(_out_womask_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_23 = and(out_rivalid[23], out_rimask_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_23 = and(out_roready[23], out_romask_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_23 = and(out_wivalid[23], out_wimask_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_23 = and(out_woready[23], out_womask_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_250 = bits(out_back_front_q.io.deq.bits.data, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_23 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect priority[7], _out_T_250 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_251 = and(out_f_rivalid_23, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_252 = and(UInt<1>(0h1), out_f_roready_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_253 = and(out_f_wivalid_23, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_254 = and(UInt<1>(0h1), out_f_woready_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_255 = eq(out_rimask_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_256 = eq(out_wimask_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_257 = eq(out_romask_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_258 = eq(out_womask_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_259 = or(priority[7], UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_260 = bits(_out_T_259, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_24 = bits(out_frontMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_24 = orr(_out_rimask_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_24 = bits(out_frontMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_24 = andr(_out_wimask_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_24 = bits(out_backMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_24 = orr(_out_romask_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_24 = bits(out_backMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_24 = andr(_out_womask_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_24 = and(out_rivalid[24], out_rimask_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_24 = and(out_roready[24], out_romask_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_24 = and(out_wivalid[24], out_wimask_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_24 = and(out_woready[24], out_womask_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_261 = bits(out_back_front_q.io.deq.bits.data, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_24 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect priority[8], _out_T_261 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_262 = and(out_f_rivalid_24, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_263 = and(UInt<1>(0h1), out_f_roready_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_264 = and(out_f_wivalid_24, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_265 = and(UInt<1>(0h1), out_f_woready_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_266 = eq(out_rimask_24, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_267 = eq(out_wimask_24, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_268 = eq(out_romask_24, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_269 = eq(out_womask_24, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_17 = or(_out_T_260, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_17 = cat(priority[8], _out_prepend_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_270 = or(out_prepend_17, UInt<35>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_271 = bits(_out_T_270, 34, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_25 = bits(out_frontMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_25 = orr(_out_rimask_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_25 = bits(out_frontMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_25 = andr(_out_wimask_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_25 = bits(out_backMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_25 = orr(_out_romask_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_25 = bits(out_backMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_25 = andr(_out_womask_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_25 = and(out_rivalid[25], out_rimask_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_25 = and(out_roready[25], out_romask_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_25 = and(out_wivalid[25], out_wimask_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_25 = and(out_woready[25], out_womask_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_272 = bits(out_back_front_q.io.deq.bits.data, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_273 = and(out_f_rivalid_25, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_274 = and(UInt<1>(0h1), out_f_roready_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_275 = eq(out_rimask_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_276 = eq(out_wimask_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_277 = eq(out_romask_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_278 = eq(out_womask_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_279 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_280 = bits(_out_T_279, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_26 = bits(out_frontMask, 7, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_26 = orr(_out_rimask_T_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_26 = bits(out_frontMask, 7, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_26 = andr(_out_wimask_T_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_26 = bits(out_backMask, 7, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_26 = orr(_out_romask_T_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_26 = bits(out_backMask, 7, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_26 = andr(_out_womask_T_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_26 = and(out_rivalid[26], out_rimask_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_26 = and(out_roready[26], out_romask_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_26 = and(out_wivalid[26], out_wimask_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_26 = and(out_woready[26], out_womask_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_281 = bits(out_back_front_q.io.deq.bits.data, 7, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_26 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect enables_0_0, _out_T_281 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_282 = and(out_f_rivalid_26, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_283 = and(UInt<1>(0h1), out_f_roready_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_284 = and(out_f_wivalid_26, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_285 = and(UInt<1>(0h1), out_f_woready_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_286 = eq(out_rimask_26, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_287 = eq(out_wimask_26, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_288 = eq(out_romask_26, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_289 = eq(out_womask_26, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_18 = or(_out_T_280, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_18 = cat(enables_0_0, _out_prepend_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_290 = or(out_prepend_18, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_291 = bits(_out_T_290, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_27 = bits(out_frontMask, 11, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_27 = orr(_out_rimask_T_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_27 = bits(out_frontMask, 11, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_27 = andr(_out_wimask_T_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_27 = bits(out_backMask, 11, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_27 = orr(_out_romask_T_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_27 = bits(out_backMask, 11, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_27 = andr(_out_womask_T_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_27 = and(out_rivalid[27], out_rimask_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_27 = and(out_roready[27], out_romask_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_27 = and(out_wivalid[27], out_wimask_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_27 = and(out_woready[27], out_womask_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_292 = bits(out_back_front_q.io.deq.bits.data, 11, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_27 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect enables_0_1, _out_T_292 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_293 = and(out_f_rivalid_27, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_294 = and(UInt<1>(0h1), out_f_roready_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_295 = and(out_f_wivalid_27, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_296 = and(UInt<1>(0h1), out_f_woready_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_297 = eq(out_rimask_27, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_298 = eq(out_wimask_27, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_299 = eq(out_romask_27, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_300 = eq(out_womask_27, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_19 = or(_out_T_291, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_19 = cat(enables_0_1, _out_prepend_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_301 = or(out_prepend_19, UInt<12>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_302 = bits(_out_T_301, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_28 = bits(out_frontMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_28 = orr(_out_rimask_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_28 = bits(out_frontMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_28 = andr(_out_wimask_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_28 = bits(out_backMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_28 = orr(_out_romask_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_28 = bits(out_backMask, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_28 = andr(_out_womask_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_28 = and(out_rivalid[28], out_rimask_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_28 = and(out_roready[28], out_romask_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_28 = and(out_wivalid[28], out_wimask_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_28 = and(out_woready[28], out_womask_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_303 = bits(out_back_front_q.io.deq.bits.data, 34, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_28 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect priority[0], _out_T_303 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_304 = and(out_f_rivalid_28, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_305 = and(UInt<1>(0h1), out_f_roready_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_306 = and(out_f_wivalid_28, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_307 = and(UInt<1>(0h1), out_f_woready_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_308 = eq(out_rimask_28, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_309 = eq(out_wimask_28, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_310 = eq(out_romask_28, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_311 = eq(out_womask_28, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_20 = or(UInt<1>(0h0), UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_20 = cat(priority[0], _out_prepend_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_312 = or(out_prepend_20, UInt<35>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_313 = bits(_out_T_312, 34, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T = bits(out_front.bits.index, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_9 = bits(out_front.bits.index, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_10 = bits(out_front.bits.index, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_11 = bits(out_front.bits.index, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_12 = bits(out_front.bits.index, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_13 = bits(out_front.bits.index, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_14 = bits(out_front.bits.index, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_15 = bits(out_front.bits.index, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_16 = bits(out_front.bits.index, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_17 = bits(out_front.bits.index, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_18 = bits(out_front.bits.index, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_19 = bits(out_front.bits.index, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_20 = bits(out_front.bits.index, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_21 = bits(out_front.bits.index, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_22 = bits(out_front.bits.index, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex_lo_hi = cat(_out_iindex_T_2, _out_iindex_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex_lo = cat(out_iindex_lo_hi, _out_iindex_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex_hi_hi = cat(_out_iindex_T_18, _out_iindex_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex_hi = cat(out_iindex_hi_hi, _out_iindex_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex = cat(out_iindex_hi, out_iindex_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T = bits(out_back_front_q.io.deq.bits.index, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_1 = bits(out_back_front_q.io.deq.bits.index, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_2 = bits(out_back_front_q.io.deq.bits.index, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_3 = bits(out_back_front_q.io.deq.bits.index, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_4 = bits(out_back_front_q.io.deq.bits.index, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_5 = bits(out_back_front_q.io.deq.bits.index, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_6 = bits(out_back_front_q.io.deq.bits.index, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_7 = bits(out_back_front_q.io.deq.bits.index, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_8 = bits(out_back_front_q.io.deq.bits.index, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_9 = bits(out_back_front_q.io.deq.bits.index, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_10 = bits(out_back_front_q.io.deq.bits.index, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_11 = bits(out_back_front_q.io.deq.bits.index, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_12 = bits(out_back_front_q.io.deq.bits.index, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_13 = bits(out_back_front_q.io.deq.bits.index, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_14 = bits(out_back_front_q.io.deq.bits.index, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_15 = bits(out_back_front_q.io.deq.bits.index, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_16 = bits(out_back_front_q.io.deq.bits.index, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_17 = bits(out_back_front_q.io.deq.bits.index, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_18 = bits(out_back_front_q.io.deq.bits.index, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_19 = bits(out_back_front_q.io.deq.bits.index, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_20 = bits(out_back_front_q.io.deq.bits.index, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_21 = bits(out_back_front_q.io.deq.bits.index, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_22 = bits(out_back_front_q.io.deq.bits.index, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex_lo_hi = cat(_out_oindex_T_2, _out_oindex_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex_lo = cat(out_oindex_lo_hi, _out_oindex_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex_hi_hi = cat(_out_oindex_T_18, _out_oindex_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex_hi = cat(out_oindex_hi_hi, _out_oindex_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex = cat(out_oindex_hi, out_oindex_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_4 = bits(_out_frontSel_T, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_5 = bits(_out_frontSel_T, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_6 = bits(_out_frontSel_T, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_7 = bits(_out_frontSel_T, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_8 = bits(_out_frontSel_T, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_9 = bits(_out_frontSel_T, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_10 = bits(_out_frontSel_T, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_11 = bits(_out_frontSel_T, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_12 = bits(_out_frontSel_T, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_13 = bits(_out_frontSel_T, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_14 = bits(_out_frontSel_T, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_15 = bits(_out_frontSel_T, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_16 = bits(_out_frontSel_T, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_17 = bits(_out_frontSel_T, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_18 = bits(_out_frontSel_T, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_19 = bits(_out_frontSel_T, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_20 = bits(_out_frontSel_T, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_21 = bits(_out_frontSel_T, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_22 = bits(_out_frontSel_T, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_23 = bits(_out_frontSel_T, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_24 = bits(_out_frontSel_T, 24, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_25 = bits(_out_frontSel_T, 25, 25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_26 = bits(_out_frontSel_T, 26, 26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_27 = bits(_out_frontSel_T, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_28 = bits(_out_frontSel_T, 28, 28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_29 = bits(_out_frontSel_T, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_30 = bits(_out_frontSel_T, 30, 30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_31 = bits(_out_frontSel_T, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_32 = bits(_out_frontSel_T, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_33 = bits(_out_frontSel_T, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_34 = bits(_out_frontSel_T, 34, 34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_35 = bits(_out_frontSel_T, 35, 35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_36 = bits(_out_frontSel_T, 36, 36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_37 = bits(_out_frontSel_T, 37, 37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_38 = bits(_out_frontSel_T, 38, 38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_39 = bits(_out_frontSel_T, 39, 39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_40 = bits(_out_frontSel_T, 40, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_41 = bits(_out_frontSel_T, 41, 41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_42 = bits(_out_frontSel_T, 42, 42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_43 = bits(_out_frontSel_T, 43, 43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_44 = bits(_out_frontSel_T, 44, 44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_45 = bits(_out_frontSel_T, 45, 45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_46 = bits(_out_frontSel_T, 46, 46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_47 = bits(_out_frontSel_T, 47, 47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_48 = bits(_out_frontSel_T, 48, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_49 = bits(_out_frontSel_T, 49, 49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_50 = bits(_out_frontSel_T, 50, 50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_51 = bits(_out_frontSel_T, 51, 51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_52 = bits(_out_frontSel_T, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_53 = bits(_out_frontSel_T, 53, 53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_54 = bits(_out_frontSel_T, 54, 54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_55 = bits(_out_frontSel_T, 55, 55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_56 = bits(_out_frontSel_T, 56, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_57 = bits(_out_frontSel_T, 57, 57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_58 = bits(_out_frontSel_T, 58, 58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_59 = bits(_out_frontSel_T, 59, 59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_60 = bits(_out_frontSel_T, 60, 60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_61 = bits(_out_frontSel_T, 61, 61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_62 = bits(_out_frontSel_T, 62, 62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_63 = bits(_out_frontSel_T, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node out_backSel_0 = bits(_out_backSel_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_1 = bits(_out_backSel_T, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_2 = bits(_out_backSel_T, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_3 = bits(_out_backSel_T, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_4 = bits(_out_backSel_T, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_5 = bits(_out_backSel_T, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_6 = bits(_out_backSel_T, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_7 = bits(_out_backSel_T, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_8 = bits(_out_backSel_T, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_9 = bits(_out_backSel_T, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_10 = bits(_out_backSel_T, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_11 = bits(_out_backSel_T, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_12 = bits(_out_backSel_T, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_13 = bits(_out_backSel_T, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_14 = bits(_out_backSel_T, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_15 = bits(_out_backSel_T, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_16 = bits(_out_backSel_T, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_17 = bits(_out_backSel_T, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_18 = bits(_out_backSel_T, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_19 = bits(_out_backSel_T, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_20 = bits(_out_backSel_T, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_21 = bits(_out_backSel_T, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_22 = bits(_out_backSel_T, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_23 = bits(_out_backSel_T, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_24 = bits(_out_backSel_T, 24, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_25 = bits(_out_backSel_T, 25, 25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_26 = bits(_out_backSel_T, 26, 26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_27 = bits(_out_backSel_T, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_28 = bits(_out_backSel_T, 28, 28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_29 = bits(_out_backSel_T, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_30 = bits(_out_backSel_T, 30, 30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_31 = bits(_out_backSel_T, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_32 = bits(_out_backSel_T, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_33 = bits(_out_backSel_T, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_34 = bits(_out_backSel_T, 34, 34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_35 = bits(_out_backSel_T, 35, 35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_36 = bits(_out_backSel_T, 36, 36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_37 = bits(_out_backSel_T, 37, 37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_38 = bits(_out_backSel_T, 38, 38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_39 = bits(_out_backSel_T, 39, 39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_40 = bits(_out_backSel_T, 40, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_41 = bits(_out_backSel_T, 41, 41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_42 = bits(_out_backSel_T, 42, 42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_43 = bits(_out_backSel_T, 43, 43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_44 = bits(_out_backSel_T, 44, 44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_45 = bits(_out_backSel_T, 45, 45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_46 = bits(_out_backSel_T, 46, 46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_47 = bits(_out_backSel_T, 47, 47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_48 = bits(_out_backSel_T, 48, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_49 = bits(_out_backSel_T, 49, 49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_50 = bits(_out_backSel_T, 50, 50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_51 = bits(_out_backSel_T, 51, 51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_52 = bits(_out_backSel_T, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_53 = bits(_out_backSel_T, 53, 53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_54 = bits(_out_backSel_T, 54, 54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_55 = bits(_out_backSel_T, 55, 55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_56 = bits(_out_backSel_T, 56, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_57 = bits(_out_backSel_T, 57, 57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_58 = bits(_out_backSel_T, 58, 58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_59 = bits(_out_backSel_T, 59, 59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_60 = bits(_out_backSel_T, 60, 60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_61 = bits(_out_backSel_T, 61, 61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_62 = bits(_out_backSel_T, 62, 62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_63 = bits(_out_backSel_T, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T = and(in.valid, out_front.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[28], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_4 = eq(_out_T_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[3], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[2], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_2 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_2, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[17], _out_rifireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[16], _out_rifireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_12 = eq(_out_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_3 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_3, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[19], _out_rifireMux_T_15 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[18], _out_rifireMux_T_15 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_16 = eq(_out_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_4 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_18 = and(_out_rifireMux_T_1, out_frontSel_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_19 = and(_out_rifireMux_T_18, _out_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_4, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[24], _out_rifireMux_T_19 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[23], _out_rifireMux_T_19 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_20 = eq(_out_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_21 = or(out_rifireMux_out_4, _out_rifireMux_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_5 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_22 = and(_out_rifireMux_T_1, out_frontSel_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_23 = and(_out_rifireMux_T_22, _out_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_5, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[1], _out_rifireMux_T_23 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[0], _out_rifireMux_T_23 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_24 = eq(_out_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_25 = or(out_rifireMux_out_5, _out_rifireMux_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_6 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_26 = and(_out_rifireMux_T_1, out_frontSel_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_27 = and(_out_rifireMux_T_26, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_6, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_28 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_29 = or(out_rifireMux_out_6, _out_rifireMux_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_7 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_30 = and(_out_rifireMux_T_1, out_frontSel_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_31 = and(_out_rifireMux_T_30, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_7, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_32 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_33 = or(out_rifireMux_out_7, _out_rifireMux_T_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_8 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_34 = and(_out_rifireMux_T_1, out_frontSel_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_35 = and(_out_rifireMux_T_34, _out_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_8, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[15], _out_rifireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[14], _out_rifireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[13], _out_rifireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[12], _out_rifireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[11], _out_rifireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[10], _out_rifireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[9], _out_rifireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[8], _out_rifireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[7], _out_rifireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[6], _out_rifireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[5], _out_rifireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[4], _out_rifireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_36 = eq(_out_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_37 = or(out_rifireMux_out_8, _out_rifireMux_T_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_9 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_38 = and(_out_rifireMux_T_1, out_frontSel_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_39 = and(_out_rifireMux_T_38, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_9, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_40 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_41 = or(out_rifireMux_out_9, _out_rifireMux_T_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_10 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_42 = and(_out_rifireMux_T_1, out_frontSel_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_43 = and(_out_rifireMux_T_42, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_10, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_44 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_45 = or(out_rifireMux_out_10, _out_rifireMux_T_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_11 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_46 = and(_out_rifireMux_T_1, out_frontSel_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_47 = and(_out_rifireMux_T_46, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_11, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_48 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_49 = or(out_rifireMux_out_11, _out_rifireMux_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_12 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_50 = and(_out_rifireMux_T_1, out_frontSel_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_51 = and(_out_rifireMux_T_50, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_12, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_52 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_53 = or(out_rifireMux_out_12, _out_rifireMux_T_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_13 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_54 = and(_out_rifireMux_T_1, out_frontSel_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_55 = and(_out_rifireMux_T_54, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_13, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_56 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_57 = or(out_rifireMux_out_13, _out_rifireMux_T_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_14 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_58 = and(_out_rifireMux_T_1, out_frontSel_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_59 = and(_out_rifireMux_T_58, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_14, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_60 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_61 = or(out_rifireMux_out_14, _out_rifireMux_T_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_15 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_62 = and(_out_rifireMux_T_1, out_frontSel_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_63 = and(_out_rifireMux_T_62, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_15, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_64 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_65 = or(out_rifireMux_out_15, _out_rifireMux_T_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_16 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_66 = and(_out_rifireMux_T_1, out_frontSel_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_67 = and(_out_rifireMux_T_66, _out_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_16, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[27], _out_rifireMux_T_67 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[26], _out_rifireMux_T_67 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[25], _out_rifireMux_T_67 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_68 = eq(_out_T_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_69 = or(out_rifireMux_out_16, _out_rifireMux_T_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_17 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_70 = and(_out_rifireMux_T_1, out_frontSel_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_71 = and(_out_rifireMux_T_70, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_17, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_72 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_73 = or(out_rifireMux_out_17, _out_rifireMux_T_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_18 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_74 = and(_out_rifireMux_T_1, out_frontSel_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_75 = and(_out_rifireMux_T_74, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_18, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_76 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_77 = or(out_rifireMux_out_18, _out_rifireMux_T_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_19 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_78 = and(_out_rifireMux_T_1, out_frontSel_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_79 = and(_out_rifireMux_T_78, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_19, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_80 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_81 = or(out_rifireMux_out_19, _out_rifireMux_T_80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_20 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_82 = and(_out_rifireMux_T_1, out_frontSel_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_83 = and(_out_rifireMux_T_82, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_20, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_84 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_85 = or(out_rifireMux_out_20, _out_rifireMux_T_84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_21 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_86 = and(_out_rifireMux_T_1, out_frontSel_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_87 = and(_out_rifireMux_T_86, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_21, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_88 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_89 = or(out_rifireMux_out_21, _out_rifireMux_T_88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_22 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_90 = and(_out_rifireMux_T_1, out_frontSel_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_91 = and(_out_rifireMux_T_90, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_22, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_92 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_93 = or(out_rifireMux_out_22, _out_rifireMux_T_92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_23 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_94 = and(_out_rifireMux_T_1, out_frontSel_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_95 = and(_out_rifireMux_T_94, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_23, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_96 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_97 = or(out_rifireMux_out_23, _out_rifireMux_T_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_24 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_98 = and(_out_rifireMux_T_1, out_frontSel_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_99 = and(_out_rifireMux_T_98, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_24, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_100 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_101 = or(out_rifireMux_out_24, _out_rifireMux_T_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_25 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_102 = and(_out_rifireMux_T_1, out_frontSel_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_103 = and(_out_rifireMux_T_102, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_25, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_104 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_105 = or(out_rifireMux_out_25, _out_rifireMux_T_104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_26 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_106 = and(_out_rifireMux_T_1, out_frontSel_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_107 = and(_out_rifireMux_T_106, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_26, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_108 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_109 = or(out_rifireMux_out_26, _out_rifireMux_T_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_27 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_110 = and(_out_rifireMux_T_1, out_frontSel_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_111 = and(_out_rifireMux_T_110, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_27, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_112 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_113 = or(out_rifireMux_out_27, _out_rifireMux_T_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_28 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_114 = and(_out_rifireMux_T_1, out_frontSel_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_115 = and(_out_rifireMux_T_114, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_28, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_116 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_117 = or(out_rifireMux_out_28, _out_rifireMux_T_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_29 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_118 = and(_out_rifireMux_T_1, out_frontSel_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_119 = and(_out_rifireMux_T_118, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_29, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_120 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_121 = or(out_rifireMux_out_29, _out_rifireMux_T_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_30 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_122 = and(_out_rifireMux_T_1, out_frontSel_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_123 = and(_out_rifireMux_T_122, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_30, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_124 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_125 = or(out_rifireMux_out_30, _out_rifireMux_T_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_31 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_126 = and(_out_rifireMux_T_1, out_frontSel_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_127 = and(_out_rifireMux_T_126, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_31, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_128 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_129 = or(out_rifireMux_out_31, _out_rifireMux_T_128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_32 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_130 = and(_out_rifireMux_T_1, out_frontSel_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_131 = and(_out_rifireMux_T_130, _out_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_32, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[22], _out_rifireMux_T_131 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[21], _out_rifireMux_T_131 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[20], _out_rifireMux_T_131 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_132 = eq(_out_T_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_133 = or(out_rifireMux_out_32, _out_rifireMux_T_132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_33 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_134 = and(_out_rifireMux_T_1, out_frontSel_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_135 = and(_out_rifireMux_T_134, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_33, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_136 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_137 = or(out_rifireMux_out_33, _out_rifireMux_T_136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_34 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_138 = and(_out_rifireMux_T_1, out_frontSel_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_139 = and(_out_rifireMux_T_138, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_34, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_140 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_141 = or(out_rifireMux_out_34, _out_rifireMux_T_140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_35 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_142 = and(_out_rifireMux_T_1, out_frontSel_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_143 = and(_out_rifireMux_T_142, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_35, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_144 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_145 = or(out_rifireMux_out_35, _out_rifireMux_T_144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_36 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_146 = and(_out_rifireMux_T_1, out_frontSel_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_147 = and(_out_rifireMux_T_146, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_36, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_148 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_149 = or(out_rifireMux_out_36, _out_rifireMux_T_148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_37 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_150 = and(_out_rifireMux_T_1, out_frontSel_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_151 = and(_out_rifireMux_T_150, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_37, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_152 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_153 = or(out_rifireMux_out_37, _out_rifireMux_T_152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_38 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_154 = and(_out_rifireMux_T_1, out_frontSel_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_155 = and(_out_rifireMux_T_154, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_38, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_156 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_157 = or(out_rifireMux_out_38, _out_rifireMux_T_156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_39 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_158 = and(_out_rifireMux_T_1, out_frontSel_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_159 = and(_out_rifireMux_T_158, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_39, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_160 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_161 = or(out_rifireMux_out_39, _out_rifireMux_T_160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_40 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_162 = and(_out_rifireMux_T_1, out_frontSel_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_163 = and(_out_rifireMux_T_162, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_40, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_164 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_165 = or(out_rifireMux_out_40, _out_rifireMux_T_164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_41 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_166 = and(_out_rifireMux_T_1, out_frontSel_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_167 = and(_out_rifireMux_T_166, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_41, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_168 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_169 = or(out_rifireMux_out_41, _out_rifireMux_T_168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_42 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_170 = and(_out_rifireMux_T_1, out_frontSel_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_171 = and(_out_rifireMux_T_170, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_42, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_172 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_173 = or(out_rifireMux_out_42, _out_rifireMux_T_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_43 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_174 = and(_out_rifireMux_T_1, out_frontSel_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_175 = and(_out_rifireMux_T_174, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_43, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_176 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_177 = or(out_rifireMux_out_43, _out_rifireMux_T_176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_44 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_178 = and(_out_rifireMux_T_1, out_frontSel_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_179 = and(_out_rifireMux_T_178, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_44, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_180 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_181 = or(out_rifireMux_out_44, _out_rifireMux_T_180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_45 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_182 = and(_out_rifireMux_T_1, out_frontSel_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_183 = and(_out_rifireMux_T_182, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_45, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_184 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_185 = or(out_rifireMux_out_45, _out_rifireMux_T_184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_46 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_186 = and(_out_rifireMux_T_1, out_frontSel_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_187 = and(_out_rifireMux_T_186, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_46, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_188 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_189 = or(out_rifireMux_out_46, _out_rifireMux_T_188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_47 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_190 = and(_out_rifireMux_T_1, out_frontSel_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_191 = and(_out_rifireMux_T_190, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_47, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_192 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_193 = or(out_rifireMux_out_47, _out_rifireMux_T_192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_48 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_194 = and(_out_rifireMux_T_1, out_frontSel_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_195 = and(_out_rifireMux_T_194, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_48, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_196 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_197 = or(out_rifireMux_out_48, _out_rifireMux_T_196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_49 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_198 = and(_out_rifireMux_T_1, out_frontSel_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_199 = and(_out_rifireMux_T_198, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_49, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_200 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_201 = or(out_rifireMux_out_49, _out_rifireMux_T_200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_50 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_202 = and(_out_rifireMux_T_1, out_frontSel_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_203 = and(_out_rifireMux_T_202, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_50, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_204 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_205 = or(out_rifireMux_out_50, _out_rifireMux_T_204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_51 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_206 = and(_out_rifireMux_T_1, out_frontSel_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_207 = and(_out_rifireMux_T_206, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_51, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_208 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_209 = or(out_rifireMux_out_51, _out_rifireMux_T_208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_52 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_210 = and(_out_rifireMux_T_1, out_frontSel_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_211 = and(_out_rifireMux_T_210, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_52, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_212 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_213 = or(out_rifireMux_out_52, _out_rifireMux_T_212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_53 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_214 = and(_out_rifireMux_T_1, out_frontSel_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_215 = and(_out_rifireMux_T_214, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_53, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_216 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_217 = or(out_rifireMux_out_53, _out_rifireMux_T_216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_54 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_218 = and(_out_rifireMux_T_1, out_frontSel_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_219 = and(_out_rifireMux_T_218, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_54, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_220 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_221 = or(out_rifireMux_out_54, _out_rifireMux_T_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_55 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_222 = and(_out_rifireMux_T_1, out_frontSel_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_223 = and(_out_rifireMux_T_222, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_55, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_224 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_225 = or(out_rifireMux_out_55, _out_rifireMux_T_224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_56 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_226 = and(_out_rifireMux_T_1, out_frontSel_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_227 = and(_out_rifireMux_T_226, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_56, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_228 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_229 = or(out_rifireMux_out_56, _out_rifireMux_T_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_57 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_230 = and(_out_rifireMux_T_1, out_frontSel_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_231 = and(_out_rifireMux_T_230, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_57, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_232 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_233 = or(out_rifireMux_out_57, _out_rifireMux_T_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_58 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_234 = and(_out_rifireMux_T_1, out_frontSel_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_235 = and(_out_rifireMux_T_234, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_58, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_236 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_237 = or(out_rifireMux_out_58, _out_rifireMux_T_236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_59 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_238 = and(_out_rifireMux_T_1, out_frontSel_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_239 = and(_out_rifireMux_T_238, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_59, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_240 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_241 = or(out_rifireMux_out_59, _out_rifireMux_T_240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_60 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_242 = and(_out_rifireMux_T_1, out_frontSel_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_243 = and(_out_rifireMux_T_242, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_60, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_244 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_245 = or(out_rifireMux_out_60, _out_rifireMux_T_244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_61 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_246 = and(_out_rifireMux_T_1, out_frontSel_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_247 = and(_out_rifireMux_T_246, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_61, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_248 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_249 = or(out_rifireMux_out_61, _out_rifireMux_T_248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_62 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_250 = and(_out_rifireMux_T_1, out_frontSel_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_251 = and(_out_rifireMux_T_250, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_62, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_252 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_253 = or(out_rifireMux_out_62, _out_rifireMux_T_252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_63 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_254 = and(_out_rifireMux_T_1, out_frontSel_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_255 = and(_out_rifireMux_T_254, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_63, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_256 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_257 = or(out_rifireMux_out_63, _out_rifireMux_T_256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_258 = geq(out_iindex, UInt<7>(0h40)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_rifireMux_WIRE : UInt<1>[64] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[4], _out_rifireMux_T_21 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[5], _out_rifireMux_T_25 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[6], _out_rifireMux_T_29 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[7], _out_rifireMux_T_33 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[8], _out_rifireMux_T_37 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[9], _out_rifireMux_T_41 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[10], _out_rifireMux_T_45 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[11], _out_rifireMux_T_49 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[12], _out_rifireMux_T_53 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[13], _out_rifireMux_T_57 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[14], _out_rifireMux_T_61 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[15], _out_rifireMux_T_65 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[16], _out_rifireMux_T_69 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[17], _out_rifireMux_T_73 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[18], _out_rifireMux_T_77 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[19], _out_rifireMux_T_81 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[20], _out_rifireMux_T_85 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[21], _out_rifireMux_T_89 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[22], _out_rifireMux_T_93 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[23], _out_rifireMux_T_97 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[24], _out_rifireMux_T_101 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[25], _out_rifireMux_T_105 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[26], _out_rifireMux_T_109 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[27], _out_rifireMux_T_113 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[28], _out_rifireMux_T_117 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[29], _out_rifireMux_T_121 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[30], _out_rifireMux_T_125 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[31], _out_rifireMux_T_129 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[32], _out_rifireMux_T_133 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[33], _out_rifireMux_T_137 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[34], _out_rifireMux_T_141 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[35], _out_rifireMux_T_145 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[36], _out_rifireMux_T_149 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[37], _out_rifireMux_T_153 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[38], _out_rifireMux_T_157 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[39], _out_rifireMux_T_161 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[40], _out_rifireMux_T_165 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[41], _out_rifireMux_T_169 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[42], _out_rifireMux_T_173 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[43], _out_rifireMux_T_177 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[44], _out_rifireMux_T_181 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[45], _out_rifireMux_T_185 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[46], _out_rifireMux_T_189 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[47], _out_rifireMux_T_193 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[48], _out_rifireMux_T_197 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[49], _out_rifireMux_T_201 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[50], _out_rifireMux_T_205 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[51], _out_rifireMux_T_209 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[52], _out_rifireMux_T_213 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[53], _out_rifireMux_T_217 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[54], _out_rifireMux_T_221 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[55], _out_rifireMux_T_225 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[56], _out_rifireMux_T_229 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[57], _out_rifireMux_T_233 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[58], _out_rifireMux_T_237 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[59], _out_rifireMux_T_241 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[60], _out_rifireMux_T_245 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[61], _out_rifireMux_T_249 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[62], _out_rifireMux_T_253 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[63], _out_rifireMux_T_257 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_rifireMux = mux(_out_rifireMux_T_258, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_wifireMux_T = and(in.valid, out_front.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[28], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_5 = eq(_out_T_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[3], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[2], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_2 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_2, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[17], _out_wifireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[16], _out_wifireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_13 = eq(_out_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_3 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_3, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[19], _out_wifireMux_T_16 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[18], _out_wifireMux_T_16 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_17 = eq(_out_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_4 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_19 = and(_out_wifireMux_T_2, out_frontSel_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_20 = and(_out_wifireMux_T_19, _out_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_4, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[24], _out_wifireMux_T_20 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[23], _out_wifireMux_T_20 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_21 = eq(_out_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_22 = or(out_wifireMux_out_4, _out_wifireMux_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_5 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_23 = and(_out_wifireMux_T_2, out_frontSel_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_24 = and(_out_wifireMux_T_23, _out_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_5, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[1], _out_wifireMux_T_24 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[0], _out_wifireMux_T_24 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_25 = eq(_out_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_26 = or(out_wifireMux_out_5, _out_wifireMux_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_6 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_27 = and(_out_wifireMux_T_2, out_frontSel_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_28 = and(_out_wifireMux_T_27, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_6, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_29 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_30 = or(out_wifireMux_out_6, _out_wifireMux_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_7 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_31 = and(_out_wifireMux_T_2, out_frontSel_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_32 = and(_out_wifireMux_T_31, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_7, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_34 = or(out_wifireMux_out_7, _out_wifireMux_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_8 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_35 = and(_out_wifireMux_T_2, out_frontSel_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_36 = and(_out_wifireMux_T_35, _out_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_8, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[15], _out_wifireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[14], _out_wifireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[13], _out_wifireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[12], _out_wifireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[11], _out_wifireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[10], _out_wifireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[9], _out_wifireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[8], _out_wifireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[7], _out_wifireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[6], _out_wifireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[5], _out_wifireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[4], _out_wifireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_37 = eq(_out_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_38 = or(out_wifireMux_out_8, _out_wifireMux_T_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_9 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_39 = and(_out_wifireMux_T_2, out_frontSel_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_40 = and(_out_wifireMux_T_39, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_9, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_41 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_42 = or(out_wifireMux_out_9, _out_wifireMux_T_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_10 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_43 = and(_out_wifireMux_T_2, out_frontSel_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_44 = and(_out_wifireMux_T_43, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_10, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_45 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_46 = or(out_wifireMux_out_10, _out_wifireMux_T_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_11 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_47 = and(_out_wifireMux_T_2, out_frontSel_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_48 = and(_out_wifireMux_T_47, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_11, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_49 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_50 = or(out_wifireMux_out_11, _out_wifireMux_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_12 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_51 = and(_out_wifireMux_T_2, out_frontSel_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_52 = and(_out_wifireMux_T_51, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_12, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_53 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_54 = or(out_wifireMux_out_12, _out_wifireMux_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_13 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_55 = and(_out_wifireMux_T_2, out_frontSel_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_56 = and(_out_wifireMux_T_55, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_13, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_57 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_58 = or(out_wifireMux_out_13, _out_wifireMux_T_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_14 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_59 = and(_out_wifireMux_T_2, out_frontSel_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_60 = and(_out_wifireMux_T_59, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_14, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_61 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_62 = or(out_wifireMux_out_14, _out_wifireMux_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_15 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_63 = and(_out_wifireMux_T_2, out_frontSel_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_64 = and(_out_wifireMux_T_63, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_15, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_65 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_66 = or(out_wifireMux_out_15, _out_wifireMux_T_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_16 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_67 = and(_out_wifireMux_T_2, out_frontSel_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_68 = and(_out_wifireMux_T_67, _out_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_16, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[27], _out_wifireMux_T_68 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[26], _out_wifireMux_T_68 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[25], _out_wifireMux_T_68 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_69 = eq(_out_T_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_70 = or(out_wifireMux_out_16, _out_wifireMux_T_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_17 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_71 = and(_out_wifireMux_T_2, out_frontSel_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_72 = and(_out_wifireMux_T_71, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_17, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_73 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_74 = or(out_wifireMux_out_17, _out_wifireMux_T_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_18 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_75 = and(_out_wifireMux_T_2, out_frontSel_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_76 = and(_out_wifireMux_T_75, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_18, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_77 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_78 = or(out_wifireMux_out_18, _out_wifireMux_T_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_19 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_79 = and(_out_wifireMux_T_2, out_frontSel_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_80 = and(_out_wifireMux_T_79, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_19, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_81 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_82 = or(out_wifireMux_out_19, _out_wifireMux_T_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_20 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_83 = and(_out_wifireMux_T_2, out_frontSel_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_84 = and(_out_wifireMux_T_83, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_20, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_85 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_86 = or(out_wifireMux_out_20, _out_wifireMux_T_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_21 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_87 = and(_out_wifireMux_T_2, out_frontSel_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_88 = and(_out_wifireMux_T_87, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_21, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_89 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_90 = or(out_wifireMux_out_21, _out_wifireMux_T_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_22 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_91 = and(_out_wifireMux_T_2, out_frontSel_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_92 = and(_out_wifireMux_T_91, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_22, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_93 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_94 = or(out_wifireMux_out_22, _out_wifireMux_T_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_23 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_95 = and(_out_wifireMux_T_2, out_frontSel_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_96 = and(_out_wifireMux_T_95, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_23, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_97 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_98 = or(out_wifireMux_out_23, _out_wifireMux_T_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_24 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_99 = and(_out_wifireMux_T_2, out_frontSel_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_100 = and(_out_wifireMux_T_99, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_24, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_101 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_102 = or(out_wifireMux_out_24, _out_wifireMux_T_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_25 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_103 = and(_out_wifireMux_T_2, out_frontSel_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_104 = and(_out_wifireMux_T_103, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_25, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_105 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_106 = or(out_wifireMux_out_25, _out_wifireMux_T_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_26 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_107 = and(_out_wifireMux_T_2, out_frontSel_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_108 = and(_out_wifireMux_T_107, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_26, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_109 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_110 = or(out_wifireMux_out_26, _out_wifireMux_T_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_27 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_111 = and(_out_wifireMux_T_2, out_frontSel_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_112 = and(_out_wifireMux_T_111, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_27, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_113 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_114 = or(out_wifireMux_out_27, _out_wifireMux_T_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_28 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_115 = and(_out_wifireMux_T_2, out_frontSel_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_116 = and(_out_wifireMux_T_115, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_28, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_117 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_118 = or(out_wifireMux_out_28, _out_wifireMux_T_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_29 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_119 = and(_out_wifireMux_T_2, out_frontSel_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_120 = and(_out_wifireMux_T_119, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_29, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_121 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_122 = or(out_wifireMux_out_29, _out_wifireMux_T_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_30 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_123 = and(_out_wifireMux_T_2, out_frontSel_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_124 = and(_out_wifireMux_T_123, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_30, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_125 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_126 = or(out_wifireMux_out_30, _out_wifireMux_T_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_31 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_127 = and(_out_wifireMux_T_2, out_frontSel_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_128 = and(_out_wifireMux_T_127, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_31, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_129 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_130 = or(out_wifireMux_out_31, _out_wifireMux_T_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_32 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_131 = and(_out_wifireMux_T_2, out_frontSel_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_132 = and(_out_wifireMux_T_131, _out_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_32, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[22], _out_wifireMux_T_132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[21], _out_wifireMux_T_132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[20], _out_wifireMux_T_132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_133 = eq(_out_T_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_134 = or(out_wifireMux_out_32, _out_wifireMux_T_133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_33 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_135 = and(_out_wifireMux_T_2, out_frontSel_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_136 = and(_out_wifireMux_T_135, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_33, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_137 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_138 = or(out_wifireMux_out_33, _out_wifireMux_T_137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_34 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_139 = and(_out_wifireMux_T_2, out_frontSel_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_140 = and(_out_wifireMux_T_139, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_34, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_141 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_142 = or(out_wifireMux_out_34, _out_wifireMux_T_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_35 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_143 = and(_out_wifireMux_T_2, out_frontSel_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_144 = and(_out_wifireMux_T_143, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_35, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_145 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_146 = or(out_wifireMux_out_35, _out_wifireMux_T_145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_36 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_147 = and(_out_wifireMux_T_2, out_frontSel_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_148 = and(_out_wifireMux_T_147, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_36, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_149 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_150 = or(out_wifireMux_out_36, _out_wifireMux_T_149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_37 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_151 = and(_out_wifireMux_T_2, out_frontSel_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_152 = and(_out_wifireMux_T_151, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_37, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_153 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_154 = or(out_wifireMux_out_37, _out_wifireMux_T_153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_38 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_155 = and(_out_wifireMux_T_2, out_frontSel_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_156 = and(_out_wifireMux_T_155, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_38, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_157 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_158 = or(out_wifireMux_out_38, _out_wifireMux_T_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_39 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_159 = and(_out_wifireMux_T_2, out_frontSel_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_160 = and(_out_wifireMux_T_159, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_39, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_161 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_162 = or(out_wifireMux_out_39, _out_wifireMux_T_161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_40 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_163 = and(_out_wifireMux_T_2, out_frontSel_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_164 = and(_out_wifireMux_T_163, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_40, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_165 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_166 = or(out_wifireMux_out_40, _out_wifireMux_T_165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_41 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_167 = and(_out_wifireMux_T_2, out_frontSel_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_168 = and(_out_wifireMux_T_167, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_41, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_169 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_170 = or(out_wifireMux_out_41, _out_wifireMux_T_169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_42 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_171 = and(_out_wifireMux_T_2, out_frontSel_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_172 = and(_out_wifireMux_T_171, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_42, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_173 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_174 = or(out_wifireMux_out_42, _out_wifireMux_T_173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_43 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_175 = and(_out_wifireMux_T_2, out_frontSel_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_176 = and(_out_wifireMux_T_175, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_43, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_177 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_178 = or(out_wifireMux_out_43, _out_wifireMux_T_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_44 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_179 = and(_out_wifireMux_T_2, out_frontSel_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_180 = and(_out_wifireMux_T_179, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_44, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_181 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_182 = or(out_wifireMux_out_44, _out_wifireMux_T_181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_45 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_183 = and(_out_wifireMux_T_2, out_frontSel_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_184 = and(_out_wifireMux_T_183, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_45, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_185 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_186 = or(out_wifireMux_out_45, _out_wifireMux_T_185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_46 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_187 = and(_out_wifireMux_T_2, out_frontSel_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_188 = and(_out_wifireMux_T_187, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_46, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_189 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_190 = or(out_wifireMux_out_46, _out_wifireMux_T_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_47 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_191 = and(_out_wifireMux_T_2, out_frontSel_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_192 = and(_out_wifireMux_T_191, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_47, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_193 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_194 = or(out_wifireMux_out_47, _out_wifireMux_T_193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_48 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_195 = and(_out_wifireMux_T_2, out_frontSel_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_196 = and(_out_wifireMux_T_195, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_48, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_197 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_198 = or(out_wifireMux_out_48, _out_wifireMux_T_197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_49 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_199 = and(_out_wifireMux_T_2, out_frontSel_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_200 = and(_out_wifireMux_T_199, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_49, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_201 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_202 = or(out_wifireMux_out_49, _out_wifireMux_T_201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_50 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_203 = and(_out_wifireMux_T_2, out_frontSel_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_204 = and(_out_wifireMux_T_203, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_50, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_205 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_206 = or(out_wifireMux_out_50, _out_wifireMux_T_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_51 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_207 = and(_out_wifireMux_T_2, out_frontSel_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_208 = and(_out_wifireMux_T_207, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_51, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_209 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_210 = or(out_wifireMux_out_51, _out_wifireMux_T_209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_52 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_211 = and(_out_wifireMux_T_2, out_frontSel_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_212 = and(_out_wifireMux_T_211, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_52, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_213 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_214 = or(out_wifireMux_out_52, _out_wifireMux_T_213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_53 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_215 = and(_out_wifireMux_T_2, out_frontSel_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_216 = and(_out_wifireMux_T_215, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_53, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_217 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_218 = or(out_wifireMux_out_53, _out_wifireMux_T_217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_54 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_219 = and(_out_wifireMux_T_2, out_frontSel_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_220 = and(_out_wifireMux_T_219, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_54, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_221 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_222 = or(out_wifireMux_out_54, _out_wifireMux_T_221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_55 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_223 = and(_out_wifireMux_T_2, out_frontSel_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_224 = and(_out_wifireMux_T_223, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_55, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_225 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_226 = or(out_wifireMux_out_55, _out_wifireMux_T_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_56 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_227 = and(_out_wifireMux_T_2, out_frontSel_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_228 = and(_out_wifireMux_T_227, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_56, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_229 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_230 = or(out_wifireMux_out_56, _out_wifireMux_T_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_57 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_231 = and(_out_wifireMux_T_2, out_frontSel_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_232 = and(_out_wifireMux_T_231, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_57, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_233 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_234 = or(out_wifireMux_out_57, _out_wifireMux_T_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_58 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_235 = and(_out_wifireMux_T_2, out_frontSel_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_236 = and(_out_wifireMux_T_235, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_58, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_237 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_238 = or(out_wifireMux_out_58, _out_wifireMux_T_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_59 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_239 = and(_out_wifireMux_T_2, out_frontSel_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_240 = and(_out_wifireMux_T_239, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_59, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_241 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_242 = or(out_wifireMux_out_59, _out_wifireMux_T_241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_60 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_243 = and(_out_wifireMux_T_2, out_frontSel_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_244 = and(_out_wifireMux_T_243, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_60, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_245 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_246 = or(out_wifireMux_out_60, _out_wifireMux_T_245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_61 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_247 = and(_out_wifireMux_T_2, out_frontSel_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_248 = and(_out_wifireMux_T_247, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_61, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_249 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_250 = or(out_wifireMux_out_61, _out_wifireMux_T_249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_62 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_251 = and(_out_wifireMux_T_2, out_frontSel_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_252 = and(_out_wifireMux_T_251, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_62, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_253 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_254 = or(out_wifireMux_out_62, _out_wifireMux_T_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_63 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_255 = and(_out_wifireMux_T_2, out_frontSel_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_256 = and(_out_wifireMux_T_255, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_63, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_257 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_258 = or(out_wifireMux_out_63, _out_wifireMux_T_257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_259 = geq(out_iindex, UInt<7>(0h40)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_wifireMux_WIRE : UInt<1>[64] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[4], _out_wifireMux_T_22 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[5], _out_wifireMux_T_26 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[6], _out_wifireMux_T_30 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[7], _out_wifireMux_T_34 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[8], _out_wifireMux_T_38 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[9], _out_wifireMux_T_42 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[10], _out_wifireMux_T_46 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[11], _out_wifireMux_T_50 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[12], _out_wifireMux_T_54 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[13], _out_wifireMux_T_58 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[14], _out_wifireMux_T_62 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[15], _out_wifireMux_T_66 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[16], _out_wifireMux_T_70 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[17], _out_wifireMux_T_74 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[18], _out_wifireMux_T_78 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[19], _out_wifireMux_T_82 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[20], _out_wifireMux_T_86 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[21], _out_wifireMux_T_90 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[22], _out_wifireMux_T_94 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[23], _out_wifireMux_T_98 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[24], _out_wifireMux_T_102 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[25], _out_wifireMux_T_106 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[26], _out_wifireMux_T_110 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[27], _out_wifireMux_T_114 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[28], _out_wifireMux_T_118 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[29], _out_wifireMux_T_122 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[30], _out_wifireMux_T_126 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[31], _out_wifireMux_T_130 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[32], _out_wifireMux_T_134 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[33], _out_wifireMux_T_138 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[34], _out_wifireMux_T_142 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[35], _out_wifireMux_T_146 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[36], _out_wifireMux_T_150 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[37], _out_wifireMux_T_154 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[38], _out_wifireMux_T_158 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[39], _out_wifireMux_T_162 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[40], _out_wifireMux_T_166 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[41], _out_wifireMux_T_170 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[42], _out_wifireMux_T_174 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[43], _out_wifireMux_T_178 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[44], _out_wifireMux_T_182 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[45], _out_wifireMux_T_186 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[46], _out_wifireMux_T_190 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[47], _out_wifireMux_T_194 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[48], _out_wifireMux_T_198 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[49], _out_wifireMux_T_202 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[50], _out_wifireMux_T_206 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[51], _out_wifireMux_T_210 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[52], _out_wifireMux_T_214 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[53], _out_wifireMux_T_218 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[54], _out_wifireMux_T_222 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[55], _out_wifireMux_T_226 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[56], _out_wifireMux_T_230 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[57], _out_wifireMux_T_234 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[58], _out_wifireMux_T_238 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[59], _out_wifireMux_T_242 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[60], _out_wifireMux_T_246 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[61], _out_wifireMux_T_250 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[62], _out_wifireMux_T_254 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[63], _out_wifireMux_T_258 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_wifireMux = mux(_out_wifireMux_T_259, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_rofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_back_front_q.io.deq.bits.read) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[28], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_4 = eq(_out_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[3], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[2], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_2 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_2, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[17], _out_rofireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[16], _out_rofireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_12 = eq(_out_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_3 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_3, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[19], _out_rofireMux_T_15 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[18], _out_rofireMux_T_15 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_16 = eq(_out_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_4 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_18 = and(_out_rofireMux_T_1, out_backSel_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_19 = and(_out_rofireMux_T_18, _out_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_4, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[24], _out_rofireMux_T_19 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[23], _out_rofireMux_T_19 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_20 = eq(_out_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_21 = or(out_rofireMux_out_4, _out_rofireMux_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_5 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_22 = and(_out_rofireMux_T_1, out_backSel_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_23 = and(_out_rofireMux_T_22, _out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_5, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[1], _out_rofireMux_T_23 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[0], _out_rofireMux_T_23 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_24 = eq(_out_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_25 = or(out_rofireMux_out_5, _out_rofireMux_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_6 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_26 = and(_out_rofireMux_T_1, out_backSel_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_27 = and(_out_rofireMux_T_26, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_6, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_28 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_29 = or(out_rofireMux_out_6, _out_rofireMux_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_7 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_30 = and(_out_rofireMux_T_1, out_backSel_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_31 = and(_out_rofireMux_T_30, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_7, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_32 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_33 = or(out_rofireMux_out_7, _out_rofireMux_T_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_8 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_34 = and(_out_rofireMux_T_1, out_backSel_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_35 = and(_out_rofireMux_T_34, _out_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_8, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[15], _out_rofireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[14], _out_rofireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[13], _out_rofireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[12], _out_rofireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[11], _out_rofireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[10], _out_rofireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[9], _out_rofireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[8], _out_rofireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[7], _out_rofireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[6], _out_rofireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[5], _out_rofireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[4], _out_rofireMux_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_36 = eq(_out_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_37 = or(out_rofireMux_out_8, _out_rofireMux_T_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_9 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_38 = and(_out_rofireMux_T_1, out_backSel_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_39 = and(_out_rofireMux_T_38, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_9, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_40 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_41 = or(out_rofireMux_out_9, _out_rofireMux_T_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_10 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_42 = and(_out_rofireMux_T_1, out_backSel_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_43 = and(_out_rofireMux_T_42, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_10, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_44 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_45 = or(out_rofireMux_out_10, _out_rofireMux_T_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_11 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_46 = and(_out_rofireMux_T_1, out_backSel_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_47 = and(_out_rofireMux_T_46, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_11, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_48 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_49 = or(out_rofireMux_out_11, _out_rofireMux_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_12 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_50 = and(_out_rofireMux_T_1, out_backSel_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_51 = and(_out_rofireMux_T_50, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_12, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_52 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_53 = or(out_rofireMux_out_12, _out_rofireMux_T_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_13 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_54 = and(_out_rofireMux_T_1, out_backSel_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_55 = and(_out_rofireMux_T_54, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_13, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_56 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_57 = or(out_rofireMux_out_13, _out_rofireMux_T_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_14 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_58 = and(_out_rofireMux_T_1, out_backSel_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_59 = and(_out_rofireMux_T_58, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_14, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_60 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_61 = or(out_rofireMux_out_14, _out_rofireMux_T_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_15 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_62 = and(_out_rofireMux_T_1, out_backSel_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_63 = and(_out_rofireMux_T_62, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_15, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_64 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_65 = or(out_rofireMux_out_15, _out_rofireMux_T_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_16 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_66 = and(_out_rofireMux_T_1, out_backSel_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_67 = and(_out_rofireMux_T_66, _out_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_16, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[27], _out_rofireMux_T_67 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[26], _out_rofireMux_T_67 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[25], _out_rofireMux_T_67 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_68 = eq(_out_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_69 = or(out_rofireMux_out_16, _out_rofireMux_T_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_17 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_70 = and(_out_rofireMux_T_1, out_backSel_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_71 = and(_out_rofireMux_T_70, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_17, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_72 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_73 = or(out_rofireMux_out_17, _out_rofireMux_T_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_18 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_74 = and(_out_rofireMux_T_1, out_backSel_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_75 = and(_out_rofireMux_T_74, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_18, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_76 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_77 = or(out_rofireMux_out_18, _out_rofireMux_T_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_19 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_78 = and(_out_rofireMux_T_1, out_backSel_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_79 = and(_out_rofireMux_T_78, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_19, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_80 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_81 = or(out_rofireMux_out_19, _out_rofireMux_T_80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_20 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_82 = and(_out_rofireMux_T_1, out_backSel_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_83 = and(_out_rofireMux_T_82, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_20, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_84 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_85 = or(out_rofireMux_out_20, _out_rofireMux_T_84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_21 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_86 = and(_out_rofireMux_T_1, out_backSel_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_87 = and(_out_rofireMux_T_86, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_21, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_88 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_89 = or(out_rofireMux_out_21, _out_rofireMux_T_88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_22 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_90 = and(_out_rofireMux_T_1, out_backSel_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_91 = and(_out_rofireMux_T_90, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_22, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_92 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_93 = or(out_rofireMux_out_22, _out_rofireMux_T_92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_23 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_94 = and(_out_rofireMux_T_1, out_backSel_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_95 = and(_out_rofireMux_T_94, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_23, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_96 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_97 = or(out_rofireMux_out_23, _out_rofireMux_T_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_24 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_98 = and(_out_rofireMux_T_1, out_backSel_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_99 = and(_out_rofireMux_T_98, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_24, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_100 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_101 = or(out_rofireMux_out_24, _out_rofireMux_T_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_25 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_102 = and(_out_rofireMux_T_1, out_backSel_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_103 = and(_out_rofireMux_T_102, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_25, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_104 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_105 = or(out_rofireMux_out_25, _out_rofireMux_T_104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_26 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_106 = and(_out_rofireMux_T_1, out_backSel_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_107 = and(_out_rofireMux_T_106, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_26, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_108 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_109 = or(out_rofireMux_out_26, _out_rofireMux_T_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_27 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_110 = and(_out_rofireMux_T_1, out_backSel_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_111 = and(_out_rofireMux_T_110, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_27, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_112 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_113 = or(out_rofireMux_out_27, _out_rofireMux_T_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_28 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_114 = and(_out_rofireMux_T_1, out_backSel_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_115 = and(_out_rofireMux_T_114, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_28, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_116 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_117 = or(out_rofireMux_out_28, _out_rofireMux_T_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_29 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_118 = and(_out_rofireMux_T_1, out_backSel_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_119 = and(_out_rofireMux_T_118, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_29, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_120 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_121 = or(out_rofireMux_out_29, _out_rofireMux_T_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_30 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_122 = and(_out_rofireMux_T_1, out_backSel_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_123 = and(_out_rofireMux_T_122, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_30, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_124 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_125 = or(out_rofireMux_out_30, _out_rofireMux_T_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_31 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_126 = and(_out_rofireMux_T_1, out_backSel_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_127 = and(_out_rofireMux_T_126, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_31, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_128 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_129 = or(out_rofireMux_out_31, _out_rofireMux_T_128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_32 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_130 = and(_out_rofireMux_T_1, out_backSel_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_131 = and(_out_rofireMux_T_130, _out_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_32, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[22], _out_rofireMux_T_131 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[21], _out_rofireMux_T_131 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[20], _out_rofireMux_T_131 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_132 = eq(_out_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_133 = or(out_rofireMux_out_32, _out_rofireMux_T_132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_33 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_134 = and(_out_rofireMux_T_1, out_backSel_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_135 = and(_out_rofireMux_T_134, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_33, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_136 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_137 = or(out_rofireMux_out_33, _out_rofireMux_T_136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_34 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_138 = and(_out_rofireMux_T_1, out_backSel_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_139 = and(_out_rofireMux_T_138, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_34, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_140 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_141 = or(out_rofireMux_out_34, _out_rofireMux_T_140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_35 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_142 = and(_out_rofireMux_T_1, out_backSel_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_143 = and(_out_rofireMux_T_142, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_35, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_144 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_145 = or(out_rofireMux_out_35, _out_rofireMux_T_144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_36 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_146 = and(_out_rofireMux_T_1, out_backSel_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_147 = and(_out_rofireMux_T_146, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_36, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_148 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_149 = or(out_rofireMux_out_36, _out_rofireMux_T_148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_37 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_150 = and(_out_rofireMux_T_1, out_backSel_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_151 = and(_out_rofireMux_T_150, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_37, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_152 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_153 = or(out_rofireMux_out_37, _out_rofireMux_T_152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_38 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_154 = and(_out_rofireMux_T_1, out_backSel_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_155 = and(_out_rofireMux_T_154, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_38, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_156 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_157 = or(out_rofireMux_out_38, _out_rofireMux_T_156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_39 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_158 = and(_out_rofireMux_T_1, out_backSel_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_159 = and(_out_rofireMux_T_158, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_39, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_160 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_161 = or(out_rofireMux_out_39, _out_rofireMux_T_160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_40 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_162 = and(_out_rofireMux_T_1, out_backSel_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_163 = and(_out_rofireMux_T_162, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_40, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_164 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_165 = or(out_rofireMux_out_40, _out_rofireMux_T_164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_41 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_166 = and(_out_rofireMux_T_1, out_backSel_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_167 = and(_out_rofireMux_T_166, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_41, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_168 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_169 = or(out_rofireMux_out_41, _out_rofireMux_T_168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_42 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_170 = and(_out_rofireMux_T_1, out_backSel_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_171 = and(_out_rofireMux_T_170, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_42, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_172 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_173 = or(out_rofireMux_out_42, _out_rofireMux_T_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_43 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_174 = and(_out_rofireMux_T_1, out_backSel_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_175 = and(_out_rofireMux_T_174, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_43, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_176 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_177 = or(out_rofireMux_out_43, _out_rofireMux_T_176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_44 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_178 = and(_out_rofireMux_T_1, out_backSel_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_179 = and(_out_rofireMux_T_178, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_44, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_180 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_181 = or(out_rofireMux_out_44, _out_rofireMux_T_180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_45 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_182 = and(_out_rofireMux_T_1, out_backSel_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_183 = and(_out_rofireMux_T_182, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_45, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_184 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_185 = or(out_rofireMux_out_45, _out_rofireMux_T_184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_46 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_186 = and(_out_rofireMux_T_1, out_backSel_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_187 = and(_out_rofireMux_T_186, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_46, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_188 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_189 = or(out_rofireMux_out_46, _out_rofireMux_T_188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_47 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_190 = and(_out_rofireMux_T_1, out_backSel_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_191 = and(_out_rofireMux_T_190, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_47, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_192 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_193 = or(out_rofireMux_out_47, _out_rofireMux_T_192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_48 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_194 = and(_out_rofireMux_T_1, out_backSel_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_195 = and(_out_rofireMux_T_194, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_48, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_196 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_197 = or(out_rofireMux_out_48, _out_rofireMux_T_196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_49 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_198 = and(_out_rofireMux_T_1, out_backSel_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_199 = and(_out_rofireMux_T_198, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_49, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_200 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_201 = or(out_rofireMux_out_49, _out_rofireMux_T_200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_50 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_202 = and(_out_rofireMux_T_1, out_backSel_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_203 = and(_out_rofireMux_T_202, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_50, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_204 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_205 = or(out_rofireMux_out_50, _out_rofireMux_T_204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_51 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_206 = and(_out_rofireMux_T_1, out_backSel_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_207 = and(_out_rofireMux_T_206, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_51, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_208 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_209 = or(out_rofireMux_out_51, _out_rofireMux_T_208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_52 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_210 = and(_out_rofireMux_T_1, out_backSel_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_211 = and(_out_rofireMux_T_210, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_52, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_212 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_213 = or(out_rofireMux_out_52, _out_rofireMux_T_212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_53 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_214 = and(_out_rofireMux_T_1, out_backSel_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_215 = and(_out_rofireMux_T_214, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_53, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_216 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_217 = or(out_rofireMux_out_53, _out_rofireMux_T_216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_54 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_218 = and(_out_rofireMux_T_1, out_backSel_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_219 = and(_out_rofireMux_T_218, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_54, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_220 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_221 = or(out_rofireMux_out_54, _out_rofireMux_T_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_55 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_222 = and(_out_rofireMux_T_1, out_backSel_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_223 = and(_out_rofireMux_T_222, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_55, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_224 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_225 = or(out_rofireMux_out_55, _out_rofireMux_T_224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_56 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_226 = and(_out_rofireMux_T_1, out_backSel_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_227 = and(_out_rofireMux_T_226, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_56, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_228 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_229 = or(out_rofireMux_out_56, _out_rofireMux_T_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_57 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_230 = and(_out_rofireMux_T_1, out_backSel_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_231 = and(_out_rofireMux_T_230, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_57, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_232 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_233 = or(out_rofireMux_out_57, _out_rofireMux_T_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_58 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_234 = and(_out_rofireMux_T_1, out_backSel_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_235 = and(_out_rofireMux_T_234, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_58, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_236 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_237 = or(out_rofireMux_out_58, _out_rofireMux_T_236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_59 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_238 = and(_out_rofireMux_T_1, out_backSel_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_239 = and(_out_rofireMux_T_238, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_59, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_240 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_241 = or(out_rofireMux_out_59, _out_rofireMux_T_240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_60 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_242 = and(_out_rofireMux_T_1, out_backSel_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_243 = and(_out_rofireMux_T_242, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_60, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_244 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_245 = or(out_rofireMux_out_60, _out_rofireMux_T_244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_61 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_246 = and(_out_rofireMux_T_1, out_backSel_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_247 = and(_out_rofireMux_T_246, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_61, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_248 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_249 = or(out_rofireMux_out_61, _out_rofireMux_T_248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_62 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_250 = and(_out_rofireMux_T_1, out_backSel_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_251 = and(_out_rofireMux_T_250, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_62, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_252 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_253 = or(out_rofireMux_out_62, _out_rofireMux_T_252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_63 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_254 = and(_out_rofireMux_T_1, out_backSel_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_255 = and(_out_rofireMux_T_254, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_63, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_256 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_257 = or(out_rofireMux_out_63, _out_rofireMux_T_256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_258 = geq(out_oindex, UInt<7>(0h40)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_rofireMux_WIRE : UInt<1>[64] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[4], _out_rofireMux_T_21 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[5], _out_rofireMux_T_25 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[6], _out_rofireMux_T_29 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[7], _out_rofireMux_T_33 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[8], _out_rofireMux_T_37 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[9], _out_rofireMux_T_41 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[10], _out_rofireMux_T_45 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[11], _out_rofireMux_T_49 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[12], _out_rofireMux_T_53 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[13], _out_rofireMux_T_57 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[14], _out_rofireMux_T_61 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[15], _out_rofireMux_T_65 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[16], _out_rofireMux_T_69 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[17], _out_rofireMux_T_73 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[18], _out_rofireMux_T_77 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[19], _out_rofireMux_T_81 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[20], _out_rofireMux_T_85 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[21], _out_rofireMux_T_89 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[22], _out_rofireMux_T_93 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[23], _out_rofireMux_T_97 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[24], _out_rofireMux_T_101 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[25], _out_rofireMux_T_105 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[26], _out_rofireMux_T_109 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[27], _out_rofireMux_T_113 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[28], _out_rofireMux_T_117 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[29], _out_rofireMux_T_121 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[30], _out_rofireMux_T_125 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[31], _out_rofireMux_T_129 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[32], _out_rofireMux_T_133 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[33], _out_rofireMux_T_137 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[34], _out_rofireMux_T_141 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[35], _out_rofireMux_T_145 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[36], _out_rofireMux_T_149 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[37], _out_rofireMux_T_153 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[38], _out_rofireMux_T_157 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[39], _out_rofireMux_T_161 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[40], _out_rofireMux_T_165 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[41], _out_rofireMux_T_169 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[42], _out_rofireMux_T_173 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[43], _out_rofireMux_T_177 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[44], _out_rofireMux_T_181 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[45], _out_rofireMux_T_185 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[46], _out_rofireMux_T_189 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[47], _out_rofireMux_T_193 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[48], _out_rofireMux_T_197 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[49], _out_rofireMux_T_201 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[50], _out_rofireMux_T_205 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[51], _out_rofireMux_T_209 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[52], _out_rofireMux_T_213 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[53], _out_rofireMux_T_217 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[54], _out_rofireMux_T_221 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[55], _out_rofireMux_T_225 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[56], _out_rofireMux_T_229 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[57], _out_rofireMux_T_233 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[58], _out_rofireMux_T_237 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[59], _out_rofireMux_T_241 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[60], _out_rofireMux_T_245 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[61], _out_rofireMux_T_249 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[62], _out_rofireMux_T_253 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[63], _out_rofireMux_T_257 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_rofireMux = mux(_out_rofireMux_T_258, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_wofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1 = eq(out_back_front_q.io.deq.bits.read, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[28], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_5 = eq(_out_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[3], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[2], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_2 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_2, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[17], _out_wofireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[16], _out_wofireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_13 = eq(_out_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_3 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_3, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[19], _out_wofireMux_T_16 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[18], _out_wofireMux_T_16 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_17 = eq(_out_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_4 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_19 = and(_out_wofireMux_T_2, out_backSel_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_20 = and(_out_wofireMux_T_19, _out_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_4, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[24], _out_wofireMux_T_20 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[23], _out_wofireMux_T_20 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_21 = eq(_out_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_22 = or(out_wofireMux_out_4, _out_wofireMux_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_5 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_23 = and(_out_wofireMux_T_2, out_backSel_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_24 = and(_out_wofireMux_T_23, _out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_5, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[1], _out_wofireMux_T_24 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[0], _out_wofireMux_T_24 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_25 = eq(_out_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_26 = or(out_wofireMux_out_5, _out_wofireMux_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_6 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_27 = and(_out_wofireMux_T_2, out_backSel_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_28 = and(_out_wofireMux_T_27, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_6, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_29 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_30 = or(out_wofireMux_out_6, _out_wofireMux_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_7 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_31 = and(_out_wofireMux_T_2, out_backSel_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_32 = and(_out_wofireMux_T_31, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_7, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_34 = or(out_wofireMux_out_7, _out_wofireMux_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_8 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_35 = and(_out_wofireMux_T_2, out_backSel_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_36 = and(_out_wofireMux_T_35, _out_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_8, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[15], _out_wofireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[14], _out_wofireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[13], _out_wofireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[12], _out_wofireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[11], _out_wofireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[10], _out_wofireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[9], _out_wofireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[8], _out_wofireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[7], _out_wofireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[6], _out_wofireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[5], _out_wofireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[4], _out_wofireMux_T_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_37 = eq(_out_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_38 = or(out_wofireMux_out_8, _out_wofireMux_T_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_9 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_39 = and(_out_wofireMux_T_2, out_backSel_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_40 = and(_out_wofireMux_T_39, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_9, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_41 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_42 = or(out_wofireMux_out_9, _out_wofireMux_T_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_10 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_43 = and(_out_wofireMux_T_2, out_backSel_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_44 = and(_out_wofireMux_T_43, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_10, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_45 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_46 = or(out_wofireMux_out_10, _out_wofireMux_T_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_11 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_47 = and(_out_wofireMux_T_2, out_backSel_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_48 = and(_out_wofireMux_T_47, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_11, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_49 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_50 = or(out_wofireMux_out_11, _out_wofireMux_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_12 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_51 = and(_out_wofireMux_T_2, out_backSel_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_52 = and(_out_wofireMux_T_51, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_12, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_53 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_54 = or(out_wofireMux_out_12, _out_wofireMux_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_13 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_55 = and(_out_wofireMux_T_2, out_backSel_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_56 = and(_out_wofireMux_T_55, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_13, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_57 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_58 = or(out_wofireMux_out_13, _out_wofireMux_T_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_14 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_59 = and(_out_wofireMux_T_2, out_backSel_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_60 = and(_out_wofireMux_T_59, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_14, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_61 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_62 = or(out_wofireMux_out_14, _out_wofireMux_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_15 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_63 = and(_out_wofireMux_T_2, out_backSel_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_64 = and(_out_wofireMux_T_63, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_15, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_65 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_66 = or(out_wofireMux_out_15, _out_wofireMux_T_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_16 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_67 = and(_out_wofireMux_T_2, out_backSel_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_68 = and(_out_wofireMux_T_67, _out_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_16, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[27], _out_wofireMux_T_68 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[26], _out_wofireMux_T_68 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[25], _out_wofireMux_T_68 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_69 = eq(_out_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_70 = or(out_wofireMux_out_16, _out_wofireMux_T_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_17 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_71 = and(_out_wofireMux_T_2, out_backSel_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_72 = and(_out_wofireMux_T_71, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_17, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_73 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_74 = or(out_wofireMux_out_17, _out_wofireMux_T_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_18 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_75 = and(_out_wofireMux_T_2, out_backSel_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_76 = and(_out_wofireMux_T_75, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_18, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_77 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_78 = or(out_wofireMux_out_18, _out_wofireMux_T_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_19 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_79 = and(_out_wofireMux_T_2, out_backSel_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_80 = and(_out_wofireMux_T_79, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_19, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_81 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_82 = or(out_wofireMux_out_19, _out_wofireMux_T_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_20 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_83 = and(_out_wofireMux_T_2, out_backSel_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_84 = and(_out_wofireMux_T_83, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_20, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_85 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_86 = or(out_wofireMux_out_20, _out_wofireMux_T_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_21 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_87 = and(_out_wofireMux_T_2, out_backSel_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_88 = and(_out_wofireMux_T_87, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_21, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_89 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_90 = or(out_wofireMux_out_21, _out_wofireMux_T_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_22 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_91 = and(_out_wofireMux_T_2, out_backSel_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_92 = and(_out_wofireMux_T_91, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_22, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_93 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_94 = or(out_wofireMux_out_22, _out_wofireMux_T_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_23 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_95 = and(_out_wofireMux_T_2, out_backSel_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_96 = and(_out_wofireMux_T_95, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_23, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_97 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_98 = or(out_wofireMux_out_23, _out_wofireMux_T_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_24 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_99 = and(_out_wofireMux_T_2, out_backSel_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_100 = and(_out_wofireMux_T_99, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_24, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_101 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_102 = or(out_wofireMux_out_24, _out_wofireMux_T_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_25 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_103 = and(_out_wofireMux_T_2, out_backSel_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_104 = and(_out_wofireMux_T_103, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_25, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_105 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_106 = or(out_wofireMux_out_25, _out_wofireMux_T_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_26 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_107 = and(_out_wofireMux_T_2, out_backSel_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_108 = and(_out_wofireMux_T_107, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_26, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_109 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_110 = or(out_wofireMux_out_26, _out_wofireMux_T_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_27 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_111 = and(_out_wofireMux_T_2, out_backSel_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_112 = and(_out_wofireMux_T_111, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_27, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_113 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_114 = or(out_wofireMux_out_27, _out_wofireMux_T_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_28 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_115 = and(_out_wofireMux_T_2, out_backSel_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_116 = and(_out_wofireMux_T_115, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_28, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_117 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_118 = or(out_wofireMux_out_28, _out_wofireMux_T_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_29 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_119 = and(_out_wofireMux_T_2, out_backSel_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_120 = and(_out_wofireMux_T_119, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_29, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_121 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_122 = or(out_wofireMux_out_29, _out_wofireMux_T_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_30 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_123 = and(_out_wofireMux_T_2, out_backSel_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_124 = and(_out_wofireMux_T_123, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_30, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_125 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_126 = or(out_wofireMux_out_30, _out_wofireMux_T_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_31 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_127 = and(_out_wofireMux_T_2, out_backSel_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_128 = and(_out_wofireMux_T_127, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_31, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_129 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_130 = or(out_wofireMux_out_31, _out_wofireMux_T_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_32 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_131 = and(_out_wofireMux_T_2, out_backSel_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_132 = and(_out_wofireMux_T_131, _out_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_32, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[22], _out_wofireMux_T_132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[21], _out_wofireMux_T_132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[20], _out_wofireMux_T_132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_133 = eq(_out_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_134 = or(out_wofireMux_out_32, _out_wofireMux_T_133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_33 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_135 = and(_out_wofireMux_T_2, out_backSel_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_136 = and(_out_wofireMux_T_135, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_33, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_137 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_138 = or(out_wofireMux_out_33, _out_wofireMux_T_137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_34 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_139 = and(_out_wofireMux_T_2, out_backSel_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_140 = and(_out_wofireMux_T_139, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_34, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_141 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_142 = or(out_wofireMux_out_34, _out_wofireMux_T_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_35 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_143 = and(_out_wofireMux_T_2, out_backSel_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_144 = and(_out_wofireMux_T_143, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_35, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_145 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_146 = or(out_wofireMux_out_35, _out_wofireMux_T_145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_36 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_147 = and(_out_wofireMux_T_2, out_backSel_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_148 = and(_out_wofireMux_T_147, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_36, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_149 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_150 = or(out_wofireMux_out_36, _out_wofireMux_T_149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_37 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_151 = and(_out_wofireMux_T_2, out_backSel_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_152 = and(_out_wofireMux_T_151, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_37, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_153 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_154 = or(out_wofireMux_out_37, _out_wofireMux_T_153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_38 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_155 = and(_out_wofireMux_T_2, out_backSel_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_156 = and(_out_wofireMux_T_155, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_38, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_157 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_158 = or(out_wofireMux_out_38, _out_wofireMux_T_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_39 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_159 = and(_out_wofireMux_T_2, out_backSel_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_160 = and(_out_wofireMux_T_159, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_39, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_161 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_162 = or(out_wofireMux_out_39, _out_wofireMux_T_161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_40 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_163 = and(_out_wofireMux_T_2, out_backSel_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_164 = and(_out_wofireMux_T_163, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_40, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_165 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_166 = or(out_wofireMux_out_40, _out_wofireMux_T_165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_41 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_167 = and(_out_wofireMux_T_2, out_backSel_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_168 = and(_out_wofireMux_T_167, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_41, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_169 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_170 = or(out_wofireMux_out_41, _out_wofireMux_T_169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_42 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_171 = and(_out_wofireMux_T_2, out_backSel_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_172 = and(_out_wofireMux_T_171, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_42, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_173 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_174 = or(out_wofireMux_out_42, _out_wofireMux_T_173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_43 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_175 = and(_out_wofireMux_T_2, out_backSel_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_176 = and(_out_wofireMux_T_175, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_43, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_177 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_178 = or(out_wofireMux_out_43, _out_wofireMux_T_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_44 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_179 = and(_out_wofireMux_T_2, out_backSel_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_180 = and(_out_wofireMux_T_179, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_44, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_181 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_182 = or(out_wofireMux_out_44, _out_wofireMux_T_181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_45 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_183 = and(_out_wofireMux_T_2, out_backSel_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_184 = and(_out_wofireMux_T_183, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_45, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_185 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_186 = or(out_wofireMux_out_45, _out_wofireMux_T_185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_46 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_187 = and(_out_wofireMux_T_2, out_backSel_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_188 = and(_out_wofireMux_T_187, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_46, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_189 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_190 = or(out_wofireMux_out_46, _out_wofireMux_T_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_47 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_191 = and(_out_wofireMux_T_2, out_backSel_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_192 = and(_out_wofireMux_T_191, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_47, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_193 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_194 = or(out_wofireMux_out_47, _out_wofireMux_T_193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_48 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_195 = and(_out_wofireMux_T_2, out_backSel_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_196 = and(_out_wofireMux_T_195, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_48, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_197 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_198 = or(out_wofireMux_out_48, _out_wofireMux_T_197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_49 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_199 = and(_out_wofireMux_T_2, out_backSel_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_200 = and(_out_wofireMux_T_199, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_49, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_201 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_202 = or(out_wofireMux_out_49, _out_wofireMux_T_201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_50 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_203 = and(_out_wofireMux_T_2, out_backSel_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_204 = and(_out_wofireMux_T_203, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_50, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_205 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_206 = or(out_wofireMux_out_50, _out_wofireMux_T_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_51 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_207 = and(_out_wofireMux_T_2, out_backSel_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_208 = and(_out_wofireMux_T_207, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_51, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_209 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_210 = or(out_wofireMux_out_51, _out_wofireMux_T_209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_52 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_211 = and(_out_wofireMux_T_2, out_backSel_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_212 = and(_out_wofireMux_T_211, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_52, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_213 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_214 = or(out_wofireMux_out_52, _out_wofireMux_T_213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_53 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_215 = and(_out_wofireMux_T_2, out_backSel_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_216 = and(_out_wofireMux_T_215, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_53, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_217 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_218 = or(out_wofireMux_out_53, _out_wofireMux_T_217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_54 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_219 = and(_out_wofireMux_T_2, out_backSel_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_220 = and(_out_wofireMux_T_219, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_54, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_221 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_222 = or(out_wofireMux_out_54, _out_wofireMux_T_221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_55 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_223 = and(_out_wofireMux_T_2, out_backSel_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_224 = and(_out_wofireMux_T_223, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_55, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_225 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_226 = or(out_wofireMux_out_55, _out_wofireMux_T_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_56 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_227 = and(_out_wofireMux_T_2, out_backSel_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_228 = and(_out_wofireMux_T_227, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_56, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_229 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_230 = or(out_wofireMux_out_56, _out_wofireMux_T_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_57 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_231 = and(_out_wofireMux_T_2, out_backSel_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_232 = and(_out_wofireMux_T_231, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_57, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_233 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_234 = or(out_wofireMux_out_57, _out_wofireMux_T_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_58 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_235 = and(_out_wofireMux_T_2, out_backSel_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_236 = and(_out_wofireMux_T_235, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_58, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_237 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_238 = or(out_wofireMux_out_58, _out_wofireMux_T_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_59 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_239 = and(_out_wofireMux_T_2, out_backSel_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_240 = and(_out_wofireMux_T_239, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_59, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_241 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_242 = or(out_wofireMux_out_59, _out_wofireMux_T_241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_60 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_243 = and(_out_wofireMux_T_2, out_backSel_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_244 = and(_out_wofireMux_T_243, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_60, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_245 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_246 = or(out_wofireMux_out_60, _out_wofireMux_T_245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_61 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_247 = and(_out_wofireMux_T_2, out_backSel_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_248 = and(_out_wofireMux_T_247, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_61, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_249 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_250 = or(out_wofireMux_out_61, _out_wofireMux_T_249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_62 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_251 = and(_out_wofireMux_T_2, out_backSel_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_252 = and(_out_wofireMux_T_251, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_62, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_253 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_254 = or(out_wofireMux_out_62, _out_wofireMux_T_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_63 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_255 = and(_out_wofireMux_T_2, out_backSel_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_256 = and(_out_wofireMux_T_255, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_63, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_257 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_258 = or(out_wofireMux_out_63, _out_wofireMux_T_257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_259 = geq(out_oindex, UInt<7>(0h40)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_wofireMux_WIRE : UInt<1>[64] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[4], _out_wofireMux_T_22 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[5], _out_wofireMux_T_26 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[6], _out_wofireMux_T_30 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[7], _out_wofireMux_T_34 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[8], _out_wofireMux_T_38 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[9], _out_wofireMux_T_42 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[10], _out_wofireMux_T_46 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[11], _out_wofireMux_T_50 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[12], _out_wofireMux_T_54 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[13], _out_wofireMux_T_58 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[14], _out_wofireMux_T_62 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[15], _out_wofireMux_T_66 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[16], _out_wofireMux_T_70 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[17], _out_wofireMux_T_74 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[18], _out_wofireMux_T_78 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[19], _out_wofireMux_T_82 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[20], _out_wofireMux_T_86 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[21], _out_wofireMux_T_90 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[22], _out_wofireMux_T_94 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[23], _out_wofireMux_T_98 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[24], _out_wofireMux_T_102 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[25], _out_wofireMux_T_106 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[26], _out_wofireMux_T_110 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[27], _out_wofireMux_T_114 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[28], _out_wofireMux_T_118 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[29], _out_wofireMux_T_122 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[30], _out_wofireMux_T_126 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[31], _out_wofireMux_T_130 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[32], _out_wofireMux_T_134 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[33], _out_wofireMux_T_138 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[34], _out_wofireMux_T_142 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[35], _out_wofireMux_T_146 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[36], _out_wofireMux_T_150 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[37], _out_wofireMux_T_154 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[38], _out_wofireMux_T_158 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[39], _out_wofireMux_T_162 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[40], _out_wofireMux_T_166 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[41], _out_wofireMux_T_170 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[42], _out_wofireMux_T_174 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[43], _out_wofireMux_T_178 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[44], _out_wofireMux_T_182 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[45], _out_wofireMux_T_186 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[46], _out_wofireMux_T_190 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[47], _out_wofireMux_T_194 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[48], _out_wofireMux_T_198 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[49], _out_wofireMux_T_202 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[50], _out_wofireMux_T_206 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[51], _out_wofireMux_T_210 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[52], _out_wofireMux_T_214 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[53], _out_wofireMux_T_218 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[54], _out_wofireMux_T_222 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[55], _out_wofireMux_T_226 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[56], _out_wofireMux_T_230 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[57], _out_wofireMux_T_234 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[58], _out_wofireMux_T_238 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[59], _out_wofireMux_T_242 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[60], _out_wofireMux_T_246 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[61], _out_wofireMux_T_250 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[62], _out_wofireMux_T_254 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[63], _out_wofireMux_T_258 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_wofireMux = mux(_out_wofireMux_T_259, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oready = mux(out_back_front_q.io.deq.bits.read, out_rofireMux, out_wofireMux) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_in_ready_T = and(out_front.ready, out_iready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect in.ready, _out_in_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_front_valid_T = and(in.valid, out_iready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front.valid, _out_front_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_front_q_io_deq_ready_T = and(out.ready, out_oready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_back_front_q.io.deq.ready, _out_front_q_io_deq_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_out_valid_T = and(out_back_front_q.io.deq.valid, out_oready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.valid, _out_out_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.read, out_back_front_q.io.deq.bits.read @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_out_bits_data_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 52:28] connect out_out_bits_data_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 52:28] node _out_out_bits_data_T = eq(UInt<1>(0h0), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_17 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_1 = eq(UInt<1>(0h1), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_2 = eq(UInt<2>(0h2), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_2 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_3 = eq(UInt<2>(0h3), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_3 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_9 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_4 = eq(UInt<3>(0h4), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_13 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_5 = eq(UInt<3>(0h5), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_5 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_6 = eq(UInt<4>(0h8), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_6 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_7 = eq(UInt<5>(0h10), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_7 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_15 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_8 = eq(UInt<6>(0h20), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_8 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] wire out_out_bits_data_out_1 : UInt @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 52:28] connect out_out_bits_data_out_1, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 52:28] node _out_out_bits_data_T_9 = eq(UInt<1>(0h0), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_9 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_313 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_10 = eq(UInt<1>(0h1), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_10 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_61 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_11 = eq(UInt<2>(0h2), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_11 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_191 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_12 = eq(UInt<2>(0h3), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_12 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_213 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_13 = eq(UInt<3>(0h4), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_13 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_271 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_14 = eq(UInt<3>(0h5), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_14 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_39 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_15 = eq(UInt<4>(0h8), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_15 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_169 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_16 = eq(UInt<5>(0h10), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_16 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_302 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_17 = eq(UInt<6>(0h20), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_17 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_249 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] node _out_out_bits_data_T_18 = mux(out_out_bits_data_out, out_out_bits_data_out_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.data, _out_out_bits_data_T_18 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.extra, out_back_front_q.io.deq.bits.extra @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect in.valid, nodeIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 90:15] connect nodeIn.a.ready, in.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 91:15] connect nodeIn.d.valid, out.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 92:15] connect out.ready, nodeIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 93:15] wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 792:17] connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 793:15] connect nodeIn_d_bits_d.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 794:15] connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 795:15] connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 796:15] connect nodeIn_d_bits_d.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 797:15] connect nodeIn_d_bits_d.denied, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 798:15] invalidate nodeIn_d_bits_d.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 801:15] connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 802:15] connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.data, nodeIn_d_bits_d.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.source, nodeIn_d_bits_d.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.size, nodeIn_d_bits_d.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.param, nodeIn_d_bits_d.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.data, out.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 100:17] node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 105:25] connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 105:19] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<28>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 108:22] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<28>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 109:22] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 110:22] node _claimed_T = gt(maxDevs[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 316:46] node claimed = and(claimer[0], _claimed_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 316:32] node _T_37 = or(claimed, completer[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 318:69] regreset r : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 318:42] when _T_37 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 318:42] connect r, claimed @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 318:42] node _T_38 = and(claimed, r) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 318:30] node _T_39 = or(claimed, completer[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 319:73] regreset r_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 319:44] when _T_39 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 319:44] connect r_1, completer[0] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 319:44] node _T_40 = and(completer[0], r_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 319:32] node _ep_T = cat(enables_0_1, enables_0_0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node ep_lo_lo = cat(pending[1], pending[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 321:44] node ep_lo_hi_hi = cat(pending[4], pending[3]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 321:44] node ep_lo_hi = cat(ep_lo_hi_hi, pending[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 321:44] node ep_lo = cat(ep_lo_hi, ep_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 321:44] node ep_hi_lo_hi = cat(pending[7], pending[6]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 321:44] node ep_hi_lo = cat(ep_hi_lo_hi, pending[5]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 321:44] node ep_hi_hi_hi = cat(pending[10], pending[9]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 321:44] node ep_hi_hi = cat(ep_hi_hi_hi, pending[8]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 321:44] node ep_hi = cat(ep_hi_hi, ep_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 321:44] node _ep_T_1 = cat(ep_hi, ep_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 321:44] node ep = and(_ep_T, _ep_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 321:34] reg ep2 : UInt, clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 322:24] connect ep2, ep @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 322:24] node _diff_T = not(ep2) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 323:23] node diff = and(ep, _diff_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 323:21] node _T_41 = sub(diff, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 324:36] node _T_42 = tail(_T_41, 1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 324:36] node _T_43 = and(diff, _T_42) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 324:28] node _T_44 = neq(_T_43, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 324:44] node _T_45 = shl(UInt<1>(0h1), 3) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 327:34] node _T_46 = gt(maxDevs[0], _T_45) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 327:27] node _T_47 = cat(UInt<1>(0h1), threshold[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 327:79] node _T_48 = leq(maxDevs[0], _T_47) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 327:73] node _T_49 = and(_T_46, _T_48) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 327:59] module AsyncResetRegVec_w1_i0_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 56:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 56:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 56:7] output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 59:14] node _reg_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 61:29] regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 61:50] when io.en : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 62:16] connect reg, io.d @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 63:9] connect io.q, reg @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 65:8] module IntSyncCrossingSource_n1x1_4 : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 41:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 41:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 41:9] output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] inst reg of AsyncResetRegVec_w1_i0_4 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 86:21] connect reg.clock, clock connect reg.reset, reset connect reg.io.d, nodeIn[0] @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 88:14] connect reg.io.en, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncResetReg.scala 89:15] node _T = bits(reg.io.q, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 45:50] connect nodeOut.sync[0], _T @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 45:16] module PLICClockSinkDomain : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 14:9] output auto : { flip plic_int_in : UInt<1>[11], flip plic_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, int_in_clock_xing_out : { sync : UInt<1>[1]}, flip clock_in : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 21:19] output reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 22:19] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] inst plic of TLPLIC @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Plic.scala 365:46] connect plic.clock, childClock connect plic.reset, childReset inst intsource of IntSyncCrossingSource_n1x1_4 @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 29:31] connect intsource.clock, childClock connect intsource.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate clockNodeIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate clockNodeIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire intInClockXingOut : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate intInClockXingOut.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire intInClockXingIn : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate intInClockXingIn.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect intInClockXingOut, intInClockXingIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect intsource.auto.in[0], plic.auto.int_out[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect intInClockXingIn, intsource.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect clockNodeIn, auto.clock_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.int_in_clock_xing_out, intInClockXingOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect plic.auto.in, auto.plic_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect plic.auto.int_in[0], auto.plic_int_in[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect plic.auto.int_in[1], auto.plic_int_in[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect plic.auto.int_in[2], auto.plic_int_in[2] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect plic.auto.int_in[3], auto.plic_int_in[3] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect plic.auto.int_in[4], auto.plic_int_in[4] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect plic.auto.int_in[5], auto.plic_int_in[5] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect plic.auto.int_in[6], auto.plic_int_in[6] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect plic.auto.int_in[7], auto.plic_int_in[7] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect plic.auto.int_in[8], auto.plic_int_in[8] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect plic.auto.int_in[9], auto.plic_int_in[9] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect plic.auto.int_in[10], auto.plic_int_in[10] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect childClock, clockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 15:16] connect childReset, clockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 16:16] connect clock, clockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 23:11] connect reset, clockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 24:11] module TLXbar_dmixbar_i1_o2_a9d32s1k1z2u : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 74:9] output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate anonIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate anonIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_anonOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_anonOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.anon_out_0, anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.anon_out_1, x1_anonOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect anonIn, auto.anon_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 159:18] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.data, anonIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.mask, anonIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.address, anonIn.a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.source, anonIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.size, anonIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.param, anonIn.a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.bits.opcode, anonIn.a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect in[0].a.valid, anonIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] connect anonIn.a.ready, in[0].a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 165:37] node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:55] connect in[0].a.bits.source, _in_0_a_bits_source_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 166:29] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_1.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] invalidate _WIRE_1.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 178:17] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_3.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] invalidate _WIRE_3.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 179:21] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 180:23] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 181:26] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_9.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] invalidate _WIRE_9.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 189:17] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_11.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] invalidate _WIRE_11.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 190:20] wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.bits, _WIRE_12.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, _WIRE_12.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.ready, _WIRE_12.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 191:23] wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_14.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.bits, _WIRE_14.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.valid, _WIRE_14.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.ready, _WIRE_14.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_15.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 192:26] connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.data, in[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.denied, in[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.sink, in[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.source, in[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.size, in[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.param, in[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.opcode, in[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.valid, in[0].d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect in[0].d.ready, anonIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 196:40] connect anonIn.d.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 197:32] wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.bits, _WIRE_16.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.valid, _WIRE_16.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.ready, _WIRE_16.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_17.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_17.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] invalidate _WIRE_17.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 208:17] wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_18.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.bits, _WIRE_18.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.valid, _WIRE_18.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_19.ready, _WIRE_18.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_19.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_19.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] invalidate _WIRE_19.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 209:21] wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_20.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.bits, _WIRE_20.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.valid, _WIRE_20.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.ready, _WIRE_20.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_21.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 210:23] wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.bits, _WIRE_22.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.valid, _WIRE_22.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, _WIRE_22.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 211:26] wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 216:19] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.data, out[0].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.mask, out[0].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.address, out[0].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.source, out[0].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.size, out[0].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.param, out[0].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.bits.opcode, out[0].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect anonOut.a.valid, out[0].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[0].a.ready, anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.bits, _WIRE_24.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.valid, _WIRE_24.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.ready, _WIRE_24.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_25.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_25.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_26.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.bits, _WIRE_26.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.valid, _WIRE_26.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_27.ready, _WIRE_26.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_27.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_27.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_28.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.bits, _WIRE_28.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.valid, _WIRE_28.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.ready, _WIRE_28.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_29.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.bits, _WIRE_30.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.valid, _WIRE_30.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.ready, _WIRE_30.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.bits, _WIRE_32.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.valid, _WIRE_32.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.ready, _WIRE_32.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_33.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_33.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_34.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.bits, _WIRE_34.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.valid, _WIRE_34.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_35.ready, _WIRE_34.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_35.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_35.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_36.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.bits, _WIRE_36.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.valid, _WIRE_36.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.ready, _WIRE_36.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_37.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_38.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.bits, _WIRE_38.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.valid, _WIRE_38.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.ready, _WIRE_38.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_39.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.data, anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.denied, anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.sink, anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.source, anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.size, anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.param, anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.bits.opcode, anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[0].d.valid, anonOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect anonOut.d.ready, out[0].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[0].d.bits.sink, _out_0_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_40.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.bits, _WIRE_40.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.valid, _WIRE_40.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_41.ready, _WIRE_40.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_41.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_41.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_41.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_42.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.bits, _WIRE_42.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.valid, _WIRE_42.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_43.ready, _WIRE_42.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_43.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_43.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_43.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_44.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.bits, _WIRE_44.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.valid, _WIRE_44.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.ready, _WIRE_44.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_45.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_46.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.bits, _WIRE_46.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.valid, _WIRE_46.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.ready, _WIRE_46.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_47.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.data, out[1].a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.mask, out[1].a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.address, out[1].a.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.source, out[1].a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.size, out[1].a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.param, out[1].a.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect x1_anonOut.a.valid, out[1].a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] connect out[1].a.ready, x1_anonOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 222:41] wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_48.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_49.bits, _WIRE_48.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_49.valid, _WIRE_48.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_49.ready, _WIRE_48.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_49.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] invalidate _WIRE_49.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 233:18] wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.address, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_50.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_51.bits, _WIRE_50.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_51.valid, _WIRE_50.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_51.ready, _WIRE_50.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_51.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] invalidate _WIRE_51.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 234:21] wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_52.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.bits, _WIRE_52.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.valid, _WIRE_52.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.ready, _WIRE_52.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_53.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 235:24] wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.address, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_54.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.bits, _WIRE_54.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.valid, _WIRE_54.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.ready, _WIRE_54.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_55.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 236:27] wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_56.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_57.bits, _WIRE_56.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_57.valid, _WIRE_56.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_57.ready, _WIRE_56.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_57.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] invalidate _WIRE_57.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 243:19] wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.address, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_58.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_59.bits, _WIRE_58.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_59.valid, _WIRE_58.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_59.ready, _WIRE_58.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_59.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] invalidate _WIRE_59.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 244:22] wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_60.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.bits, _WIRE_60.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.valid, _WIRE_60.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.ready, _WIRE_60.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_61.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 245:24] wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.address, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_62.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.bits, _WIRE_62.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.valid, _WIRE_62.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.ready, _WIRE_62.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_63.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 246:27] connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.data, x1_anonOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.denied, x1_anonOut.d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.sink, x1_anonOut.d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.source, x1_anonOut.d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.size, x1_anonOut.d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.param, x1_anonOut.d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect out[1].d.valid, x1_anonOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] connect x1_anonOut.d.ready, out[1].d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 250:29] node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:53] connect out[1].d.bits.sink, _out_1_d_bits_sink_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 251:28] wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_64.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_64.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_64.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_65.bits, _WIRE_64.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_65.valid, _WIRE_64.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_65.ready, _WIRE_64.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_65.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_65.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] invalidate _WIRE_65.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 263:18] wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_66.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_66.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_66.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_67.bits, _WIRE_66.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_67.valid, _WIRE_66.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_67.ready, _WIRE_66.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_67.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_67.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] invalidate _WIRE_67.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 264:22] wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_68.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_68.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_68.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.bits, _WIRE_68.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.valid, _WIRE_68.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.ready, _WIRE_68.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_69.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 265:24] wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_70.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_70.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_70.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.bits, _WIRE_70.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.valid, _WIRE_70.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.ready, _WIRE_70.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_71.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 266:27] wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _addressC_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.bits, _addressC_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.valid, _addressC_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _addressC_WIRE_1.ready, _addressC_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_1 = cvt(_requestAIO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<10>(0h1c0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_3 = asSInt(_requestAIO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<7>(0h44)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_6 = cvt(_requestAIO_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<10>(0h1f4))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_8 = asSInt(_requestAIO_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _requestAIO_T_10 = xor(in[0].a.bits.address, UInt<7>(0h58)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_11 = cvt(_requestAIO_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<10>(0h1f8))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_13 = asSInt(_requestAIO_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _requestAIO_T_15 = xor(in[0].a.bits.address, UInt<7>(0h60)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_16 = cvt(_requestAIO_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_17 = and(_requestAIO_T_16, asSInt(UInt<10>(0h1e0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_18 = asSInt(_requestAIO_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_19 = eq(_requestAIO_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _requestAIO_T_20 = xor(in[0].a.bits.address, UInt<8>(0h80)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_21 = cvt(_requestAIO_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_22 = and(_requestAIO_T_21, asSInt(UInt<10>(0h180))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_23 = asSInt(_requestAIO_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_24 = eq(_requestAIO_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _requestAIO_T_25 = xor(in[0].a.bits.address, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_26 = cvt(_requestAIO_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_27 = and(_requestAIO_T_26, asSInt(UInt<10>(0h100))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_28 = asSInt(_requestAIO_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_29 = eq(_requestAIO_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _requestAIO_T_30 = or(_requestAIO_T_4, _requestAIO_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 291:92] node _requestAIO_T_31 = or(_requestAIO_T_30, _requestAIO_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 291:92] node _requestAIO_T_32 = or(_requestAIO_T_31, _requestAIO_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 291:92] node _requestAIO_T_33 = or(_requestAIO_T_32, _requestAIO_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 291:92] node _requestAIO_T_34 = or(_requestAIO_T_33, _requestAIO_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 291:92] node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestAIO_T_35 = xor(in[0].a.bits.address, UInt<7>(0h40)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_36 = cvt(_requestAIO_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_37 = and(_requestAIO_T_36, asSInt(UInt<10>(0h1f4))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_38 = asSInt(_requestAIO_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_39 = eq(_requestAIO_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _requestAIO_T_40 = xor(in[0].a.bits.address, UInt<7>(0h50)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestAIO_T_41 = cvt(_requestAIO_T_40) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestAIO_T_42 = and(_requestAIO_T_41, asSInt(UInt<10>(0h1f8))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_43 = asSInt(_requestAIO_T_42) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestAIO_T_44 = eq(_requestAIO_T_43, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _requestAIO_T_45 = or(_requestAIO_T_39, _requestAIO_T_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 291:92] node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 307:107] node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_1 = cvt(_requestCIO_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_3 = asSInt(_requestCIO_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _requestCIO_T_6 = cvt(_requestCIO_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_8 = asSInt(_requestCIO_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 308:107] wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node requestBOI_0_0 = eq(_requestBOI_WIRE_1.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 48:9] wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node requestBOI_1_0 = eq(_requestBOI_WIRE_3.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 48:9] node requestDOI_0_0 = eq(out[0].d.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 48:9] node requestDOI_1_0 = eq(out[1].d.bits.source, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 48:9] wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] node _beatsAI_decode_T = dshl(UInt<2>(0h3), in[0].a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsAI_decode = shr(_beatsAI_decode_T_2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T = dshl(UInt<2>(0h3), _beatsBO_WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode = shr(_beatsBO_decode_T_2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _beatsBO_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _beatsBO_decode_T_3 = dshl(UInt<2>(0h3), _beatsBO_WIRE_3.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _beatsCI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _beatsCI_decode_T = dshl(UInt<2>(0h3), _beatsCI_WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsCI_decode = shr(_beatsCI_decode_T_2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 102:36] node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T = dshl(UInt<2>(0h3), out[0].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode = shr(_beatsDO_decode_T_2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _beatsDO_decode_T_3 = dshl(UInt<2>(0h3), out[1].d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _beatsEI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsAOI_filtered[0].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsAOI_filtered[1].bits, in[0].a.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _portsAOI_in_0_a_ready_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsBIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _portsBIO_WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_3.bits, _portsBIO_WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_3.valid, _portsBIO_WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _portsBIO_WIRE_3.ready, _portsBIO_WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_3.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_3.valid, _portsBIO_filtered_0_valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect _portsBIO_WIRE_3.ready, portsBIO_filtered_1[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _portsCOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsCOI_T_2 = or(_portsCOI_T, _portsCOI_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _portsCOI_WIRE_2 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsCOI_WIRE_2, _portsCOI_T_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.data, out[0].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.source, out[0].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.size, out[0].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.param, out[0].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect out[0].d.ready, portsDIO_filtered[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect out[1].d.ready, portsDIO_filtered_1[0].ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _portsEOI_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 352:24] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 354:24] node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:54] node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:40] connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 355:25] node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _portsEOI_T_2 = or(_portsEOI_T, _portsEOI_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _portsEOI_WIRE_2 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsEOI_WIRE_2, _portsEOI_T_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 357:17] connect out[0].a, portsAOI_filtered[0] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_72.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_73.bits, _WIRE_72.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_73.valid, _WIRE_72.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_73.ready, _WIRE_72.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_73.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_73.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_74.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_74.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_74.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_75.bits, _WIRE_74.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_75.valid, _WIRE_74.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_75.ready, _WIRE_74.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_75.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] connect out[1].a, portsAOI_filtered[1] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 53:12] wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_76.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_76.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_76.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_76.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_76.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_76.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_76.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_76.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_76.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_77.bits, _WIRE_76.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_77.valid, _WIRE_76.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_77.ready, _WIRE_76.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] invalidate _WIRE_77.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_77.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_78.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_78.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_78.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_79.bits, _WIRE_78.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_79.valid, _WIRE_78.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_79.ready, _WIRE_78.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] invalidate _WIRE_79.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] connect portsCOI_filtered[1].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 332:73] connect portsEOI_filtered[1].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 333:73] wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_80.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_80.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_80.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_80.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_80.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_80.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_80.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_80.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_80.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_80.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_81.bits, _WIRE_80.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_81.valid, _WIRE_80.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_81.ready, _WIRE_80.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] invalidate _WIRE_81.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_81.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_81.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_81.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_81.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_81.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_81.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] invalidate _WIRE_81.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 51:23] regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 60:30] node idle = eq(beatsLeft, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 61:28] node latch = and(idle, in[0].d.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 62:24] node _readys_T = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:51] node readys_valid = bits(_readys_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 21:23] node _readys_T_1 = eq(readys_valid, _readys_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:19] node _readys_T_2 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] when _readys_T_3 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] when _readys_T_4 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 22:12] regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 23:23] node _readys_filter_T = not(readys_mask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 24:30] node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 24:28] node readys_filter = cat(_readys_filter_T_1, readys_valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 24:21] node _readys_unready_T = shr(readys_filter, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 263:48] node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 263:43] node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 264:17] node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 25:52] node _readys_unready_T_4 = shl(readys_mask, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 25:66] node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 25:58] node _readys_readys_T = shr(readys_unready, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:29] node _readys_readys_T_1 = bits(readys_unready, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:48] node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:39] node readys_readys = not(_readys_readys_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 26:18] node _readys_T_5 = orr(readys_valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 27:27] node _readys_T_6 = and(latch, _readys_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 27:18] when _readys_T_6 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 27:32] node _readys_mask_T = and(readys_readys, readys_valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 28:29] node _readys_mask_T_1 = shl(_readys_mask_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 255:17] connect readys_mask, _readys_mask_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 28:12] node _readys_T_7 = bits(readys_readys, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 30:11] node _readys_T_8 = bits(_readys_T_7, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] node _readys_T_9 = bits(_readys_T_7, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] wire readys : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[0], _readys_T_8 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[1], _readys_T_9 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] node _winner_T = and(readys[0], portsDIO_filtered[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] node _winner_T_1 = and(readys[1], portsDIO_filtered_1[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] wire winner : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[0], _winner_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[1], _winner_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] node prefixOR_1 = or(UInt<1>(0h0), winner[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node _prefixOR_T = or(prefixOR_1, winner[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_1 = eq(winner[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_2 = or(_T, _T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_4 = eq(winner[1], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_5 = or(_T_3, _T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_6 = and(_T_2, _T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:77] node _T_7 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_8 = eq(_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_9 = eq(_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] when _T_9 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] assert(clock, _T_6, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_10 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:31] node _T_11 = eq(_T_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:15] node _T_12 = or(winner[0], winner[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:54] node _T_13 = or(_T_11, _T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:36] node _T_14 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node _T_15 = eq(_T_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] when _T_15 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node _T_16 = eq(_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] when _T_16 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node maskedBeats_0 = mux(winner[0], beatsDO_0, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node maskedBeats_1 = mux(winner[1], beatsDO_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node initBeats = or(maskedBeats_0, maskedBeats_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 84:44] node _beatsLeft_T = and(in[0].d.ready, in[0].d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:52] node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:52] node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:23] connect beatsLeft, _beatsLeft_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:17] wire _state_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] regreset state : UInt<1>[2], clock, reset, _state_WIRE @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:26] node muxState = mux(idle, winner, state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 89:25] connect state, muxState @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 90:13] node allowed = mux(idle, readys, state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 92:24] node _filtered_0_ready_T = and(in[0].d.ready, allowed[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect portsDIO_filtered[0].ready, _filtered_0_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _filtered_0_ready_T_1 = and(in[0].d.ready, allowed[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:46] node _in_0_d_valid_T_1 = mux(state[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_2 = mux(state[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_valid_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_valid_T_4 = mux(idle, _in_0_d_valid_T, _in_0_d_valid_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:24] connect in[0].d.valid, _in_0_d_valid_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:18] wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T = mux(muxState[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_1 = mux(muxState[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_1 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_3 = mux(muxState[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_4 = mux(muxState[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_2 : UInt<32> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_3 : { } @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_4 : { } @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_6 = mux(muxState[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_7 = mux(muxState[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_5 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_9 = mux(muxState[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_10 = mux(muxState[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_6 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_12 = mux(muxState[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_13 = mux(muxState[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_7 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_15 = mux(muxState[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_16 = mux(muxState[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_8 : UInt<2> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_18 = mux(muxState[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_19 = mux(muxState[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_9 : UInt<2> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_21 = mux(muxState[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_22 = mux(muxState[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _in_0_d_bits_WIRE_10 : UInt<3> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.data, _in_0_d_bits_WIRE.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.source, _in_0_d_bits_WIRE.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.size, _in_0_d_bits_WIRE.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.param, _in_0_d_bits_WIRE.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect portsBIO_filtered[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] connect portsBIO_filtered_1[0].ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Xbar.scala 339:73] module DMIToTL : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 90:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 90:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 90:9] output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output io : { flip dmi : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<32>, op : UInt<2>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<32>, resp : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 91:16] wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] wire src : UInt @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 97:24] connect src, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 97:24] node _addr_T = shl(io.dmi.req.bits.addr, 2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 98:46] wire addr : UInt @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 98:24] connect addr, _addr_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 98:24] node _gbits_legal_T = leq(UInt<1>(0h0), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _gbits_legal_T_1 = leq(UInt<2>(0h2), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _gbits_legal_T_2 = and(_gbits_legal_T, _gbits_legal_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _gbits_legal_T_3 = or(UInt<1>(0h0), _gbits_legal_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _gbits_legal_T_4 = xor(addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _gbits_legal_T_5 = cvt(_gbits_legal_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _gbits_legal_T_6 = and(_gbits_legal_T_5, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_7 = asSInt(_gbits_legal_T_6) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_8 = eq(_gbits_legal_T_7, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _gbits_legal_T_9 = and(_gbits_legal_T_3, _gbits_legal_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node gbits_legal = or(UInt<1>(0h0), _gbits_legal_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire gbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 460:17] connect gbits.opcode, UInt<3>(0h4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 461:15] connect gbits.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 462:15] connect gbits.size, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 463:15] connect gbits.source, src @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 464:15] connect gbits.address, addr @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 465:15] node _gbits_a_mask_sizeOH_T = or(UInt<2>(0h2), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node gbits_a_mask_sizeOH_shiftAmount = bits(_gbits_a_mask_sizeOH_T, 0, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _gbits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), gbits_a_mask_sizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _gbits_a_mask_sizeOH_T_2 = bits(_gbits_a_mask_sizeOH_T_1, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node gbits_a_mask_sizeOH = or(_gbits_a_mask_sizeOH_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] node gbits_a_mask_sub_sub_0_1 = geq(UInt<2>(0h2), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 206:21] node gbits_a_mask_sub_size = bits(gbits_a_mask_sizeOH, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node gbits_a_mask_sub_bit = bits(addr, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node gbits_a_mask_sub_nbit = eq(gbits_a_mask_sub_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node gbits_a_mask_sub_0_2 = and(UInt<1>(0h1), gbits_a_mask_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _gbits_a_mask_sub_acc_T = and(gbits_a_mask_sub_size, gbits_a_mask_sub_0_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node gbits_a_mask_sub_0_1 = or(gbits_a_mask_sub_sub_0_1, _gbits_a_mask_sub_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node gbits_a_mask_sub_1_2 = and(UInt<1>(0h1), gbits_a_mask_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _gbits_a_mask_sub_acc_T_1 = and(gbits_a_mask_sub_size, gbits_a_mask_sub_1_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node gbits_a_mask_sub_1_1 = or(gbits_a_mask_sub_sub_0_1, _gbits_a_mask_sub_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node gbits_a_mask_size = bits(gbits_a_mask_sizeOH, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node gbits_a_mask_bit = bits(addr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node gbits_a_mask_nbit = eq(gbits_a_mask_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node gbits_a_mask_eq = and(gbits_a_mask_sub_0_2, gbits_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _gbits_a_mask_acc_T = and(gbits_a_mask_size, gbits_a_mask_eq) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node gbits_a_mask_acc = or(gbits_a_mask_sub_0_1, _gbits_a_mask_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node gbits_a_mask_eq_1 = and(gbits_a_mask_sub_0_2, gbits_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _gbits_a_mask_acc_T_1 = and(gbits_a_mask_size, gbits_a_mask_eq_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node gbits_a_mask_acc_1 = or(gbits_a_mask_sub_0_1, _gbits_a_mask_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node gbits_a_mask_eq_2 = and(gbits_a_mask_sub_1_2, gbits_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _gbits_a_mask_acc_T_2 = and(gbits_a_mask_size, gbits_a_mask_eq_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node gbits_a_mask_acc_2 = or(gbits_a_mask_sub_1_1, _gbits_a_mask_acc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node gbits_a_mask_eq_3 = and(gbits_a_mask_sub_1_2, gbits_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _gbits_a_mask_acc_T_3 = and(gbits_a_mask_size, gbits_a_mask_eq_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node gbits_a_mask_acc_3 = or(gbits_a_mask_sub_1_1, _gbits_a_mask_acc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node gbits_a_mask_lo = cat(gbits_a_mask_acc_1, gbits_a_mask_acc) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node gbits_a_mask_hi = cat(gbits_a_mask_acc_3, gbits_a_mask_acc_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node _gbits_a_mask_T = cat(gbits_a_mask_hi, gbits_a_mask_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] connect gbits.mask, _gbits_a_mask_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 468:15] invalidate gbits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 469:15] connect gbits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 470:15] node _pfbits_legal_T = leq(UInt<1>(0h0), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _pfbits_legal_T_1 = leq(UInt<2>(0h2), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _pfbits_legal_T_2 = and(_pfbits_legal_T, _pfbits_legal_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _pfbits_legal_T_3 = or(UInt<1>(0h0), _pfbits_legal_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _pfbits_legal_T_4 = xor(addr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pfbits_legal_T_5 = cvt(_pfbits_legal_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pfbits_legal_T_6 = and(_pfbits_legal_T_5, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_7 = asSInt(_pfbits_legal_T_6) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_8 = eq(_pfbits_legal_T_7, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pfbits_legal_T_9 = and(_pfbits_legal_T_3, _pfbits_legal_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node pfbits_legal = or(UInt<1>(0h0), _pfbits_legal_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire pfbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 480:17] connect pfbits.opcode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 481:15] connect pfbits.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 482:15] connect pfbits.size, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 483:15] connect pfbits.source, src @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 484:15] connect pfbits.address, addr @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 485:15] node _pfbits_a_mask_sizeOH_T = or(UInt<2>(0h2), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node pfbits_a_mask_sizeOH_shiftAmount = bits(_pfbits_a_mask_sizeOH_T, 0, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _pfbits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), pfbits_a_mask_sizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _pfbits_a_mask_sizeOH_T_2 = bits(_pfbits_a_mask_sizeOH_T_1, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node pfbits_a_mask_sizeOH = or(_pfbits_a_mask_sizeOH_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] node pfbits_a_mask_sub_sub_0_1 = geq(UInt<2>(0h2), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 206:21] node pfbits_a_mask_sub_size = bits(pfbits_a_mask_sizeOH, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node pfbits_a_mask_sub_bit = bits(addr, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node pfbits_a_mask_sub_nbit = eq(pfbits_a_mask_sub_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node pfbits_a_mask_sub_0_2 = and(UInt<1>(0h1), pfbits_a_mask_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _pfbits_a_mask_sub_acc_T = and(pfbits_a_mask_sub_size, pfbits_a_mask_sub_0_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node pfbits_a_mask_sub_0_1 = or(pfbits_a_mask_sub_sub_0_1, _pfbits_a_mask_sub_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node pfbits_a_mask_sub_1_2 = and(UInt<1>(0h1), pfbits_a_mask_sub_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _pfbits_a_mask_sub_acc_T_1 = and(pfbits_a_mask_sub_size, pfbits_a_mask_sub_1_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node pfbits_a_mask_sub_1_1 = or(pfbits_a_mask_sub_sub_0_1, _pfbits_a_mask_sub_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node pfbits_a_mask_size = bits(pfbits_a_mask_sizeOH, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node pfbits_a_mask_bit = bits(addr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 210:26] node pfbits_a_mask_nbit = eq(pfbits_a_mask_bit, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node pfbits_a_mask_eq = and(pfbits_a_mask_sub_0_2, pfbits_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _pfbits_a_mask_acc_T = and(pfbits_a_mask_size, pfbits_a_mask_eq) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node pfbits_a_mask_acc = or(pfbits_a_mask_sub_0_1, _pfbits_a_mask_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node pfbits_a_mask_eq_1 = and(pfbits_a_mask_sub_0_2, pfbits_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _pfbits_a_mask_acc_T_1 = and(pfbits_a_mask_size, pfbits_a_mask_eq_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node pfbits_a_mask_acc_1 = or(pfbits_a_mask_sub_0_1, _pfbits_a_mask_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node pfbits_a_mask_eq_2 = and(pfbits_a_mask_sub_1_2, pfbits_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _pfbits_a_mask_acc_T_2 = and(pfbits_a_mask_size, pfbits_a_mask_eq_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node pfbits_a_mask_acc_2 = or(pfbits_a_mask_sub_1_1, _pfbits_a_mask_acc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node pfbits_a_mask_eq_3 = and(pfbits_a_mask_sub_1_2, pfbits_a_mask_bit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _pfbits_a_mask_acc_T_3 = and(pfbits_a_mask_size, pfbits_a_mask_eq_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node pfbits_a_mask_acc_3 = or(pfbits_a_mask_sub_1_1, _pfbits_a_mask_acc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node pfbits_a_mask_lo = cat(pfbits_a_mask_acc_1, pfbits_a_mask_acc) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node pfbits_a_mask_hi = cat(pfbits_a_mask_acc_3, pfbits_a_mask_acc_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node _pfbits_a_mask_T = cat(pfbits_a_mask_hi, pfbits_a_mask_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] connect pfbits.mask, _pfbits_a_mask_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 488:15] connect pfbits.data, io.dmi.req.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 489:15] connect pfbits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 490:15] node _nbits_legal_T = leq(UInt<1>(0h0), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _nbits_legal_T_1 = leq(UInt<2>(0h2), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _nbits_legal_T_2 = and(_nbits_legal_T, _nbits_legal_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _nbits_legal_T_3 = or(UInt<1>(0h0), _nbits_legal_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _nbits_legal_T_4 = xor(UInt<7>(0h48), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _nbits_legal_T_5 = cvt(_nbits_legal_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _nbits_legal_T_6 = and(_nbits_legal_T_5, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _nbits_legal_T_7 = asSInt(_nbits_legal_T_6) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _nbits_legal_T_8 = eq(_nbits_legal_T_7, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _nbits_legal_T_9 = and(_nbits_legal_T_3, _nbits_legal_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node nbits_legal = or(UInt<1>(0h0), _nbits_legal_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire nbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 480:17] connect nbits.opcode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 481:15] connect nbits.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 482:15] connect nbits.size, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 483:15] connect nbits.source, src @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 484:15] connect nbits.address, UInt<7>(0h48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 485:15] node _nbits_a_mask_sizeOH_T = or(UInt<2>(0h2), UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node nbits_a_mask_sizeOH_shiftAmount = bits(_nbits_a_mask_sizeOH_T, 0, 0) @[src/main/scala/chisel3/util/OneHot.scala 64:49] node _nbits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), nbits_a_mask_sizeOH_shiftAmount) @[src/main/scala/chisel3/util/OneHot.scala 65:12] node _nbits_a_mask_sizeOH_T_2 = bits(_nbits_a_mask_sizeOH_T_1, 1, 0) @[src/main/scala/chisel3/util/OneHot.scala 65:27] node nbits_a_mask_sizeOH = or(_nbits_a_mask_sizeOH_T_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] node nbits_a_mask_sub_sub_0_1 = geq(UInt<2>(0h2), UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 206:21] node nbits_a_mask_sub_size = bits(nbits_a_mask_sizeOH, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node nbits_a_mask_sub_nbit = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node nbits_a_mask_sub_0_2 = and(UInt<1>(0h1), nbits_a_mask_sub_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _nbits_a_mask_sub_acc_T = and(nbits_a_mask_sub_size, nbits_a_mask_sub_0_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node nbits_a_mask_sub_0_1 = or(nbits_a_mask_sub_sub_0_1, _nbits_a_mask_sub_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node nbits_a_mask_sub_1_2 = and(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _nbits_a_mask_sub_acc_T_1 = and(nbits_a_mask_sub_size, nbits_a_mask_sub_1_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node nbits_a_mask_sub_1_1 = or(nbits_a_mask_sub_sub_0_1, _nbits_a_mask_sub_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node nbits_a_mask_size = bits(nbits_a_mask_sizeOH, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 209:26] node nbits_a_mask_nbit = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 211:20] node nbits_a_mask_eq = and(nbits_a_mask_sub_0_2, nbits_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _nbits_a_mask_acc_T = and(nbits_a_mask_size, nbits_a_mask_eq) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node nbits_a_mask_acc = or(nbits_a_mask_sub_0_1, _nbits_a_mask_acc_T) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node nbits_a_mask_eq_1 = and(nbits_a_mask_sub_0_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _nbits_a_mask_acc_T_1 = and(nbits_a_mask_size, nbits_a_mask_eq_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node nbits_a_mask_acc_1 = or(nbits_a_mask_sub_0_1, _nbits_a_mask_acc_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node nbits_a_mask_eq_2 = and(nbits_a_mask_sub_1_2, nbits_a_mask_nbit) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _nbits_a_mask_acc_T_2 = and(nbits_a_mask_size, nbits_a_mask_eq_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node nbits_a_mask_acc_2 = or(nbits_a_mask_sub_1_1, _nbits_a_mask_acc_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node nbits_a_mask_eq_3 = and(nbits_a_mask_sub_1_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 214:27] node _nbits_a_mask_acc_T_3 = and(nbits_a_mask_size, nbits_a_mask_eq_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:38] node nbits_a_mask_acc_3 = or(nbits_a_mask_sub_1_1, _nbits_a_mask_acc_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 215:29] node nbits_a_mask_lo = cat(nbits_a_mask_acc_1, nbits_a_mask_acc) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node nbits_a_mask_hi = cat(nbits_a_mask_acc_3, nbits_a_mask_acc_2) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] node _nbits_a_mask_T = cat(nbits_a_mask_hi, nbits_a_mask_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 222:10] connect nbits.mask, _nbits_a_mask_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 488:15] connect nbits.data, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 489:15] connect nbits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 490:15] node _T = eq(io.dmi.req.bits.op, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 112:30] when _T : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 112:64] connect nodeOut.a.bits, pfbits @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 112:76] else : node _T_1 = eq(io.dmi.req.bits.op, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 113:37] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 113:64] connect nodeOut.a.bits, gbits @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 113:76] else : connect nodeOut.a.bits, nbits @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 114:76] connect nodeOut.a.valid, io.dmi.req.valid @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 117:22] connect io.dmi.req.ready, nodeOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 118:22] connect io.dmi.resp.valid, nodeOut.d.valid @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 120:28] connect nodeOut.d.ready, io.dmi.resp.ready @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 121:28] node _io_dmi_resp_bits_resp_T = or(nodeOut.d.bits.corrupt, nodeOut.d.bits.denied) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 122:53] node _io_dmi_resp_bits_resp_T_1 = mux(_io_dmi_resp_bits_resp_T, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 122:34] connect io.dmi.resp.bits.resp, _io_dmi_resp_bits_resp_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 122:28] connect io.dmi.resp.bits.data, nodeOut.d.bits.data @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 123:28] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 126:16] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 127:16] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/DMI.scala 128:16] module TLDebugModuleOuter : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 340:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 340:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 340:9] output auto : { flip dmi_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, int_out : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output io : { ctrl : { flip debugUnavail : UInt<1>[1], ndreset : UInt<1>, dmactive : UInt<1>, flip dmactiveAck : UInt<1>}, innerCtrl : { flip ready : UInt<1>, valid : UInt<1>, bits : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[1], hrmask : UInt<1>[1]}}, flip hgDebugInt : UInt<1>[1]} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 348:16] wire intnodeOut : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate intnodeOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire dmiNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate dmiNodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.int_out, intnodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect dmiNodeIn, auto.dmi_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] node _T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 366:36] wire _DMCONTROLReset_WIRE : { haltreq : UInt<1>, resumereq : UInt<1>, hartreset : UInt<1>, ackhavereset : UInt<1>, reserved0 : UInt<1>, hasel : UInt<1>, hartsello : UInt<10>, hartselhi : UInt<10>, reserved1 : UInt<2>, setresethaltreq : UInt<1>, clrresethaltreq : UInt<1>, ndmreset : UInt<1>, dmactive : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 377:47] connect _DMCONTROLReset_WIRE.dmactive, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 377:47] connect _DMCONTROLReset_WIRE.ndmreset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 377:47] connect _DMCONTROLReset_WIRE.clrresethaltreq, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 377:47] connect _DMCONTROLReset_WIRE.setresethaltreq, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 377:47] connect _DMCONTROLReset_WIRE.reserved1, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 377:47] connect _DMCONTROLReset_WIRE.hartselhi, UInt<10>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 377:47] connect _DMCONTROLReset_WIRE.hartsello, UInt<10>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 377:47] connect _DMCONTROLReset_WIRE.hasel, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 377:47] connect _DMCONTROLReset_WIRE.reserved0, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 377:47] connect _DMCONTROLReset_WIRE.ackhavereset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 377:47] connect _DMCONTROLReset_WIRE.hartreset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 377:47] connect _DMCONTROLReset_WIRE.resumereq, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 377:47] connect _DMCONTROLReset_WIRE.haltreq, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 377:47] wire DMCONTROLReset : { haltreq : UInt<1>, resumereq : UInt<1>, hartreset : UInt<1>, ackhavereset : UInt<1>, reserved0 : UInt<1>, hasel : UInt<1>, hartsello : UInt<10>, hartselhi : UInt<10>, reserved1 : UInt<2>, setresethaltreq : UInt<1>, clrresethaltreq : UInt<1>, ndmreset : UInt<1>, dmactive : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 377:34] connect DMCONTROLReset, _DMCONTROLReset_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 377:34] wire _DMCONTROLNxt_WIRE : { haltreq : UInt<1>, resumereq : UInt<1>, hartreset : UInt<1>, ackhavereset : UInt<1>, reserved0 : UInt<1>, hasel : UInt<1>, hartsello : UInt<10>, hartselhi : UInt<10>, reserved1 : UInt<2>, setresethaltreq : UInt<1>, clrresethaltreq : UInt<1>, ndmreset : UInt<1>, dmactive : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 378:45] connect _DMCONTROLNxt_WIRE.dmactive, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 378:45] connect _DMCONTROLNxt_WIRE.ndmreset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 378:45] connect _DMCONTROLNxt_WIRE.clrresethaltreq, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 378:45] connect _DMCONTROLNxt_WIRE.setresethaltreq, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 378:45] connect _DMCONTROLNxt_WIRE.reserved1, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 378:45] connect _DMCONTROLNxt_WIRE.hartselhi, UInt<10>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 378:45] connect _DMCONTROLNxt_WIRE.hartsello, UInt<10>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 378:45] connect _DMCONTROLNxt_WIRE.hasel, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 378:45] connect _DMCONTROLNxt_WIRE.reserved0, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 378:45] connect _DMCONTROLNxt_WIRE.ackhavereset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 378:45] connect _DMCONTROLNxt_WIRE.hartreset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 378:45] connect _DMCONTROLNxt_WIRE.resumereq, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 378:45] connect _DMCONTROLNxt_WIRE.haltreq, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 378:45] wire DMCONTROLNxt : { haltreq : UInt<1>, resumereq : UInt<1>, hartreset : UInt<1>, ackhavereset : UInt<1>, reserved0 : UInt<1>, hasel : UInt<1>, hartsello : UInt<10>, hartselhi : UInt<10>, reserved1 : UInt<2>, setresethaltreq : UInt<1>, clrresethaltreq : UInt<1>, ndmreset : UInt<1>, dmactive : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 378:32] connect DMCONTROLNxt, _DMCONTROLNxt_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 378:32] wire _DMCONTROLReg_WIRE : { haltreq : UInt<1>, resumereq : UInt<1>, hartreset : UInt<1>, ackhavereset : UInt<1>, reserved0 : UInt<1>, hasel : UInt<1>, hartsello : UInt<10>, hartselhi : UInt<10>, reserved1 : UInt<2>, setresethaltreq : UInt<1>, clrresethaltreq : UInt<1>, ndmreset : UInt<1>, dmactive : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 379:68] connect _DMCONTROLReg_WIRE.dmactive, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 379:68] connect _DMCONTROLReg_WIRE.ndmreset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 379:68] connect _DMCONTROLReg_WIRE.clrresethaltreq, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 379:68] connect _DMCONTROLReg_WIRE.setresethaltreq, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 379:68] connect _DMCONTROLReg_WIRE.reserved1, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 379:68] connect _DMCONTROLReg_WIRE.hartselhi, UInt<10>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 379:68] connect _DMCONTROLReg_WIRE.hartsello, UInt<10>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 379:68] connect _DMCONTROLReg_WIRE.hasel, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 379:68] connect _DMCONTROLReg_WIRE.reserved0, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 379:68] connect _DMCONTROLReg_WIRE.ackhavereset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 379:68] connect _DMCONTROLReg_WIRE.hartreset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 379:68] connect _DMCONTROLReg_WIRE.resumereq, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 379:68] connect _DMCONTROLReg_WIRE.haltreq, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 379:68] regreset DMCONTROLReg : { haltreq : UInt<1>, resumereq : UInt<1>, hartreset : UInt<1>, ackhavereset : UInt<1>, reserved0 : UInt<1>, hasel : UInt<1>, hartsello : UInt<10>, hartselhi : UInt<10>, reserved1 : UInt<2>, setresethaltreq : UInt<1>, clrresethaltreq : UInt<1>, ndmreset : UInt<1>, dmactive : UInt<1>}, clock, _T, _DMCONTROLReg_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 379:31] connect DMCONTROLReg, DMCONTROLNxt @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 379:31] wire _DMCONTROLWrData_WIRE : { haltreq : UInt<1>, resumereq : UInt<1>, hartreset : UInt<1>, ackhavereset : UInt<1>, reserved0 : UInt<1>, hasel : UInt<1>, hartsello : UInt<10>, hartselhi : UInt<10>, reserved1 : UInt<2>, setresethaltreq : UInt<1>, clrresethaltreq : UInt<1>, ndmreset : UInt<1>, dmactive : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 382:48] connect _DMCONTROLWrData_WIRE.dmactive, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 382:48] connect _DMCONTROLWrData_WIRE.ndmreset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 382:48] connect _DMCONTROLWrData_WIRE.clrresethaltreq, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 382:48] connect _DMCONTROLWrData_WIRE.setresethaltreq, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 382:48] connect _DMCONTROLWrData_WIRE.reserved1, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 382:48] connect _DMCONTROLWrData_WIRE.hartselhi, UInt<10>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 382:48] connect _DMCONTROLWrData_WIRE.hartsello, UInt<10>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 382:48] connect _DMCONTROLWrData_WIRE.hasel, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 382:48] connect _DMCONTROLWrData_WIRE.reserved0, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 382:48] connect _DMCONTROLWrData_WIRE.ackhavereset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 382:48] connect _DMCONTROLWrData_WIRE.hartreset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 382:48] connect _DMCONTROLWrData_WIRE.resumereq, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 382:48] connect _DMCONTROLWrData_WIRE.haltreq, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 382:48] wire DMCONTROLWrData : { haltreq : UInt<1>, resumereq : UInt<1>, hartreset : UInt<1>, ackhavereset : UInt<1>, reserved0 : UInt<1>, hasel : UInt<1>, hartsello : UInt<10>, hartselhi : UInt<10>, reserved1 : UInt<2>, setresethaltreq : UInt<1>, clrresethaltreq : UInt<1>, ndmreset : UInt<1>, dmactive : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 382:35] connect DMCONTROLWrData, _DMCONTROLWrData_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 382:35] wire dmactiveWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 384:39] connect dmactiveWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 384:39] wire ndmresetWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 385:39] connect ndmresetWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 385:39] wire clrresethaltreqWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 386:39] connect clrresethaltreqWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 386:39] wire setresethaltreqWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 387:39] connect setresethaltreqWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 387:39] wire hartselloWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 388:39] connect hartselloWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 388:39] wire haselWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 389:39] connect haselWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 389:39] wire ackhaveresetWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 390:39] connect ackhaveresetWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 390:39] wire hartresetWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 391:39] connect hartresetWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 391:39] wire resumereqWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 392:39] connect resumereqWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 392:39] wire haltreqWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 393:39] connect haltreqWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 393:39] connect DMCONTROLNxt, DMCONTROLReg @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 397:18] node _T_1 = not(DMCONTROLReg.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 398:11] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 398:22] connect DMCONTROLNxt, DMCONTROLReset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 399:20] else : node _T_2 = and(UInt<1>(0h1), ndmresetWrEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 401:29] when _T_2 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 401:47] connect DMCONTROLNxt.ndmreset, DMCONTROLWrData.ndmreset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 401:75] node _T_3 = and(UInt<1>(0h1), hartselloWrEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 402:29] when _T_3 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 402:47] node _DMCONTROLNxt_hartsello_T = and(DMCONTROLWrData.hartsello, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 402:104] connect DMCONTROLNxt.hartsello, _DMCONTROLNxt_hartsello_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 402:75] node _T_4 = and(UInt<1>(0h1), haselWrEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 403:29] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 403:47] connect DMCONTROLNxt.hasel, DMCONTROLWrData.hasel @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 403:75] node _T_5 = and(UInt<1>(0h1), hartresetWrEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 404:29] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 404:47] connect DMCONTROLNxt.hartreset, DMCONTROLWrData.hartreset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 404:75] node _T_6 = and(UInt<1>(0h1), haltreqWrEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 405:29] when _T_6 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 405:47] connect DMCONTROLNxt.haltreq, DMCONTROLWrData.haltreq @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 405:75] when dmactiveWrEn : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 409:25] connect DMCONTROLNxt.dmactive, DMCONTROLWrData.dmactive @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 410:29] wire _HARTINFORdData_WIRE : { reserved0 : UInt<8>, nscratch : UInt<4>, reserved1 : UInt<3>, dataaccess : UInt<1>, datasize : UInt<4>, dataaddr : UInt<12>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 418:47] connect _HARTINFORdData_WIRE.dataaddr, UInt<12>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 418:47] connect _HARTINFORdData_WIRE.datasize, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 418:47] connect _HARTINFORdData_WIRE.dataaccess, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 418:47] connect _HARTINFORdData_WIRE.reserved1, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 418:47] connect _HARTINFORdData_WIRE.nscratch, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 418:47] connect _HARTINFORdData_WIRE.reserved0, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 418:47] wire HARTINFORdData : { reserved0 : UInt<8>, nscratch : UInt<4>, reserved1 : UInt<3>, dataaccess : UInt<1>, datasize : UInt<4>, dataaddr : UInt<12>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 418:34] connect HARTINFORdData, _HARTINFORdData_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 418:34] when UInt<1>(0h1) : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 419:44] connect HARTINFORdData.dataaccess, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 420:34] connect HARTINFORdData.datasize, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 421:34] connect HARTINFORdData.dataaddr, UInt<10>(0h380) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 422:34] connect HARTINFORdData.nscratch, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 423:34] wire _hamask_WIRE : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 432:34] connect _hamask_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 432:34] wire hamask : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 432:26] connect hamask, _hamask_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 432:26] wire _HAWINDOWSELWrData_WIRE : { reserved0 : UInt<17>, hawindowsel : UInt<15>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 437:50] connect _HAWINDOWSELWrData_WIRE.hawindowsel, UInt<15>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 437:50] connect _HAWINDOWSELWrData_WIRE.reserved0, UInt<17>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 437:50] wire HAWINDOWSELWrData : { reserved0 : UInt<17>, hawindowsel : UInt<15>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 437:37] connect HAWINDOWSELWrData, _HAWINDOWSELWrData_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 437:37] wire HAWINDOWSELWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 438:37] connect HAWINDOWSELWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 438:37] wire _HAWINDOWRdData_WIRE : { maskdata : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 440:47] connect _HAWINDOWRdData_WIRE.maskdata, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 440:47] wire HAWINDOWRdData : { maskdata : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 440:34] connect HAWINDOWRdData, _HAWINDOWRdData_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 440:34] wire _HAWINDOWWrData_WIRE : { maskdata : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 441:47] connect _HAWINDOWWrData_WIRE.maskdata, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 441:47] wire HAWINDOWWrData : { maskdata : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 441:34] connect HAWINDOWWrData, _HAWINDOWWrData_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 441:34] wire HAWINDOWWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 442:34] connect HAWINDOWWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 442:34] wire _HAWINDOWSELNxt_WIRE : { reserved0 : UInt<17>, hawindowsel : UInt<15>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 450:47] connect _HAWINDOWSELNxt_WIRE.hawindowsel, UInt<15>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 450:47] connect _HAWINDOWSELNxt_WIRE.reserved0, UInt<17>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 450:47] wire HAWINDOWSELNxt : { reserved0 : UInt<17>, hawindowsel : UInt<15>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 450:34] connect HAWINDOWSELNxt, _HAWINDOWSELNxt_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 450:34] wire _HAWINDOWSELReg_WIRE : { reserved0 : UInt<17>, hawindowsel : UInt<15>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 451:72] connect _HAWINDOWSELReg_WIRE.hawindowsel, UInt<15>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 451:72] connect _HAWINDOWSELReg_WIRE.reserved0, UInt<17>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 451:72] regreset HAWINDOWSELReg : { reserved0 : UInt<17>, hawindowsel : UInt<15>}, clock, _T, _HAWINDOWSELReg_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 451:33] connect HAWINDOWSELReg, HAWINDOWSELNxt @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 451:33] wire hrmask : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 517:25] wire hrmaskNxt : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 518:25] wire _hrmaskReg_WIRE : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 519:62] connect _hrmaskReg_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 519:62] regreset hrmaskReg : UInt<1>[1], clock, _T, _hrmaskReg_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 519:28] connect hrmaskReg, hrmaskNxt @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 519:28] connect hrmaskNxt, hrmaskReg @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 521:15] node _T_7 = not(DMCONTROLReg.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 523:13] node _T_8 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 523:26] node _T_9 = or(_T_7, _T_8) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 523:23] when _T_9 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 523:44] connect hrmaskNxt[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 524:30] else : node _T_10 = and(clrresethaltreqWrEn, DMCONTROLWrData.clrresethaltreq) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 525:39] node _T_11 = eq(io.innerCtrl.bits.hartsel, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 446:35] node _T_12 = or(_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 446:47] node _T_13 = and(_T_10, _T_12) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 525:74] when _T_13 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 525:102] connect hrmaskNxt[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 526:30] else : node _T_14 = and(setresethaltreqWrEn, DMCONTROLWrData.setresethaltreq) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 527:39] node _T_15 = eq(io.innerCtrl.bits.hartsel, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 446:35] node _T_16 = or(_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 446:47] node _T_17 = and(_T_14, _T_16) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 527:74] when _T_17 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 527:102] connect hrmaskNxt[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 528:30] connect hrmask, hrmaskNxt @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 531:12] node _T_18 = and(DMCONTROLReg.dmactive, io.ctrl.dmactiveAck) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 534:43] wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<3>, data : UInt<32>, mask : UInt<4>, extra : { tlrr_extra : { source : UInt<1>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 73:18] node _in_bits_read_T = eq(dmiNodeIn.a.bits.opcode, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 74:36] connect in.bits.read, _in_bits_read_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 74:19] node _in_bits_index_T = shr(dmiNodeIn.a.bits.address, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 192:34] connect in.bits.index, _in_bits_index_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 75:19] connect in.bits.data, dmiNodeIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 76:19] connect in.bits.mask, dmiNodeIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 77:19] connect in.bits.extra.tlrr_extra.source, dmiNodeIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 83:20] connect in.bits.extra.tlrr_extra.size, dmiNodeIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 84:20] wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<32>, extra : { tlrr_extra : { source : UInt<1>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<3>, data : UInt<32>, mask : UInt<4>, extra : { tlrr_extra : { source : UInt<1>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front.bits, in.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_maskMatch = not(UInt<3>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_findex = and(out_front.bits.index, out_maskMatch) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_bindex = and(out_front.bits.index, out_maskMatch) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T = eq(out_findex, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1 = eq(out_bindex, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2 = eq(out_findex, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3 = eq(out_bindex, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rivalid : UInt<1>[18] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wivalid : UInt<1>[18] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_roready : UInt<1>[18] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_woready : UInt<1>[18] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_4 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_5 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_6 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_7 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo = cat(_out_frontMask_T_5, _out_frontMask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi = cat(_out_frontMask_T_7, _out_frontMask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T = bits(out_front.bits.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_4 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_5 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_6 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_7 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo = cat(_out_backMask_T_5, _out_backMask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi = cat(_out_backMask_T_7, _out_backMask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask = cat(out_backMask_hi, out_backMask_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T = bits(out_frontMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask = orr(_out_rimask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T = bits(out_frontMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask = andr(_out_wimask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T = bits(out_backMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask = orr(_out_romask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T = bits(out_backMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask = andr(_out_womask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid = and(out_rivalid[0], out_rimask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready = and(out_roready[0], out_romask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid = and(out_wivalid[0], out_wimask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready = and(out_woready[0], out_womask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4 = bits(out_front.bits.data, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmactiveWrEn, out_f_woready @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 309:15] connect DMCONTROLWrData.dmactive, _out_T_4 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 310:12] node _out_T_5 = and(out_f_rivalid, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6 = and(UInt<1>(0h1), out_f_roready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7 = and(out_f_wivalid, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8 = and(UInt<1>(0h1), out_f_woready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9 = eq(out_rimask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10 = eq(out_wimask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11 = eq(out_romask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12 = eq(out_womask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_13 = or(_T_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_14 = bits(_out_T_13, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1 = bits(out_frontMask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1 = orr(_out_rimask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1 = bits(out_frontMask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1 = andr(_out_wimask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1 = bits(out_backMask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1 = orr(_out_romask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1 = bits(out_backMask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1 = andr(_out_womask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1 = and(out_roready[1], out_romask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1 = and(out_woready[1], out_womask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_15 = bits(out_front.bits.data, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect ndmresetWrEn, out_f_woready_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 309:15] connect DMCONTROLWrData.ndmreset, _out_T_15 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 310:12] node _out_T_16 = and(out_f_rivalid_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_17 = and(UInt<1>(0h1), out_f_roready_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_18 = and(out_f_wivalid_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_19 = and(UInt<1>(0h1), out_f_woready_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_20 = eq(out_rimask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_21 = eq(out_wimask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_22 = eq(out_romask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_23 = eq(out_womask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T = or(_out_T_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend = cat(DMCONTROLReg.ndmreset, _out_prepend_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_24 = or(out_prepend, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_25 = bits(_out_T_24, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_2 = bits(out_frontMask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_2 = orr(_out_rimask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_2 = bits(out_frontMask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_2 = andr(_out_wimask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_2 = bits(out_backMask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_2 = orr(_out_romask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_2 = bits(out_backMask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_2 = andr(_out_womask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_2 = and(out_roready[2], out_romask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_2 = and(out_woready[2], out_womask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_26 = bits(out_front.bits.data, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect clrresethaltreqWrEn, out_f_woready_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 309:15] connect DMCONTROLWrData.clrresethaltreq, _out_T_26 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 310:12] node _out_T_27 = and(out_f_wivalid_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_28 = and(UInt<1>(0h1), out_f_woready_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_29 = eq(out_rimask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_30 = eq(out_wimask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_31 = eq(out_romask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_32 = eq(out_womask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1 = or(_out_T_25, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1 = cat(UInt<1>(0h0), _out_prepend_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_33 = or(out_prepend_1, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_34 = bits(_out_T_33, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_3 = bits(out_frontMask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_3 = orr(_out_rimask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_3 = bits(out_frontMask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_3 = andr(_out_wimask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_3 = bits(out_backMask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_3 = orr(_out_romask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_3 = bits(out_backMask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_3 = andr(_out_womask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_3 = and(out_roready[3], out_romask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_3 = and(out_woready[3], out_womask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_35 = bits(out_front.bits.data, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect setresethaltreqWrEn, out_f_woready_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 309:15] connect DMCONTROLWrData.setresethaltreq, _out_T_35 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 310:12] node _out_T_36 = and(out_f_wivalid_3, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_37 = and(UInt<1>(0h1), out_f_woready_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_38 = eq(out_rimask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_39 = eq(out_wimask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_40 = eq(out_romask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_41 = eq(out_womask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_2 = or(_out_T_34, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_2 = cat(UInt<1>(0h0), _out_prepend_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_42 = or(out_prepend_2, UInt<4>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_43 = bits(_out_T_42, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_4 = bits(out_frontMask, 15, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_4 = orr(_out_rimask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_4 = bits(out_frontMask, 15, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_4 = andr(_out_wimask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_4 = bits(out_backMask, 15, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_4 = orr(_out_romask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_4 = bits(out_backMask, 15, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_4 = andr(_out_womask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_4 = and(out_roready[4], out_romask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_4 = and(out_woready[4], out_womask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_44 = bits(out_front.bits.data, 15, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_45 = and(out_f_rivalid_4, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_46 = and(UInt<1>(0h1), out_f_roready_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_47 = eq(out_rimask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_48 = eq(out_wimask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_49 = eq(out_romask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_50 = eq(out_womask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_3 = or(_out_T_43, UInt<4>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_3 = cat(UInt<1>(0h0), _out_prepend_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_51 = or(out_prepend_3, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_52 = bits(_out_T_51, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_5 = bits(out_frontMask, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_5 = orr(_out_rimask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_5 = bits(out_frontMask, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_5 = andr(_out_wimask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_5 = bits(out_backMask, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_5 = orr(_out_romask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_5 = bits(out_backMask, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_5 = andr(_out_womask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_5 = and(out_roready[5], out_romask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_5 = and(out_woready[5], out_womask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_53 = bits(out_front.bits.data, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_54 = and(out_f_rivalid_5, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_55 = and(UInt<1>(0h1), out_f_roready_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_56 = eq(out_rimask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_57 = eq(out_wimask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_58 = eq(out_romask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_59 = eq(out_womask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_4 = or(_out_T_52, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_4 = cat(UInt<1>(0h0), _out_prepend_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_60 = or(out_prepend_4, UInt<17>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_61 = bits(_out_T_60, 16, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_6 = bits(out_frontMask, 25, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_6 = orr(_out_rimask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_6 = bits(out_frontMask, 25, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_6 = andr(_out_wimask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_6 = bits(out_backMask, 25, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_6 = orr(_out_romask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_6 = bits(out_backMask, 25, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_6 = andr(_out_womask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_6 = and(out_roready[6], out_romask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_6 = and(out_woready[6], out_womask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_62 = bits(out_front.bits.data, 25, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_63 = and(out_f_rivalid_6, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_64 = and(UInt<1>(0h1), out_f_roready_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_65 = eq(out_rimask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_66 = eq(out_wimask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_67 = eq(out_romask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_68 = eq(out_womask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_5 = or(_out_T_61, UInt<17>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_5 = cat(UInt<1>(0h0), _out_prepend_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_69 = or(out_prepend_5, UInt<26>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_70 = bits(_out_T_69, 25, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_7 = bits(out_frontMask, 26, 26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_7 = orr(_out_rimask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_7 = bits(out_frontMask, 26, 26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_7 = andr(_out_wimask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_7 = bits(out_backMask, 26, 26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_7 = orr(_out_romask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_7 = bits(out_backMask, 26, 26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_7 = andr(_out_womask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_7 = and(out_roready[7], out_romask_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_7 = and(out_woready[7], out_womask_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_71 = bits(out_front.bits.data, 26, 26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_72 = and(out_f_rivalid_7, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_73 = and(UInt<1>(0h1), out_f_roready_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_74 = eq(out_rimask_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_75 = eq(out_wimask_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_76 = eq(out_romask_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_77 = eq(out_womask_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_6 = or(_out_T_70, UInt<26>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_6 = cat(UInt<1>(0h0), _out_prepend_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_78 = or(out_prepend_6, UInt<27>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_79 = bits(_out_T_78, 26, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_8 = bits(out_frontMask, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_8 = orr(_out_rimask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_8 = bits(out_frontMask, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_8 = andr(_out_wimask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_8 = bits(out_backMask, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_8 = orr(_out_romask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_8 = bits(out_backMask, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_8 = andr(_out_womask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_8 = and(out_roready[8], out_romask_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_8 = and(out_woready[8], out_womask_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_80 = bits(out_front.bits.data, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_81 = and(out_f_rivalid_8, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_82 = and(UInt<1>(0h1), out_f_roready_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_83 = eq(out_rimask_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_84 = eq(out_wimask_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_85 = eq(out_romask_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_86 = eq(out_womask_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_7 = or(_out_T_79, UInt<27>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_7 = cat(UInt<1>(0h0), _out_prepend_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_87 = or(out_prepend_7, UInt<28>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_88 = bits(_out_T_87, 27, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_9 = bits(out_frontMask, 28, 28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_9 = orr(_out_rimask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_9 = bits(out_frontMask, 28, 28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_9 = andr(_out_wimask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_9 = bits(out_backMask, 28, 28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_9 = orr(_out_romask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_9 = bits(out_backMask, 28, 28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_9 = andr(_out_womask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_9 = and(out_roready[9], out_romask_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_9 = and(out_woready[9], out_womask_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_89 = bits(out_front.bits.data, 28, 28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect ackhaveresetWrEn, out_f_woready_9 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 309:15] connect DMCONTROLWrData.ackhavereset, _out_T_89 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 310:12] node _out_T_90 = and(out_f_wivalid_9, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_91 = and(UInt<1>(0h1), out_f_woready_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_92 = eq(out_rimask_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_93 = eq(out_wimask_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_94 = eq(out_romask_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_95 = eq(out_womask_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_8 = or(_out_T_88, UInt<28>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_8 = cat(UInt<1>(0h0), _out_prepend_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_96 = or(out_prepend_8, UInt<29>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_97 = bits(_out_T_96, 28, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_10 = bits(out_frontMask, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_10 = orr(_out_rimask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_10 = bits(out_frontMask, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_10 = andr(_out_wimask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_10 = bits(out_backMask, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_10 = orr(_out_romask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_10 = bits(out_backMask, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_10 = andr(_out_womask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_10 = and(out_roready[10], out_romask_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_10 = and(out_woready[10], out_womask_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_98 = bits(out_front.bits.data, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_99 = and(out_f_rivalid_10, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_100 = and(UInt<1>(0h1), out_f_roready_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_101 = eq(out_rimask_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_102 = eq(out_wimask_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_103 = eq(out_romask_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_104 = eq(out_womask_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_9 = or(_out_T_97, UInt<29>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_9 = cat(UInt<1>(0h0), _out_prepend_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_105 = or(out_prepend_9, UInt<30>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_106 = bits(_out_T_105, 29, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_11 = bits(out_frontMask, 30, 30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_11 = orr(_out_rimask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_11 = bits(out_frontMask, 30, 30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_11 = andr(_out_wimask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_11 = bits(out_backMask, 30, 30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_11 = orr(_out_romask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_11 = bits(out_backMask, 30, 30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_11 = andr(_out_womask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_11 = and(out_roready[11], out_romask_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_11 = and(out_woready[11], out_womask_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_107 = bits(out_front.bits.data, 30, 30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect resumereqWrEn, out_f_woready_11 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 309:15] connect DMCONTROLWrData.resumereq, _out_T_107 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 310:12] node _out_T_108 = and(out_f_wivalid_11, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_109 = and(UInt<1>(0h1), out_f_woready_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_110 = eq(out_rimask_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_111 = eq(out_wimask_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_112 = eq(out_romask_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_113 = eq(out_womask_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_10 = or(_out_T_106, UInt<30>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_10 = cat(UInt<1>(0h0), _out_prepend_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_114 = or(out_prepend_10, UInt<31>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_115 = bits(_out_T_114, 30, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_12 = bits(out_frontMask, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_12 = orr(_out_rimask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_12 = bits(out_frontMask, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_12 = andr(_out_wimask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_12 = bits(out_backMask, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_12 = orr(_out_romask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_12 = bits(out_backMask, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_12 = andr(_out_womask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_12 = and(out_roready[12], out_romask_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_12 = and(out_woready[12], out_womask_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_116 = bits(out_front.bits.data, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect haltreqWrEn, out_f_woready_12 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 309:15] connect DMCONTROLWrData.haltreq, _out_T_116 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 310:12] node _out_T_117 = and(out_f_rivalid_12, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_118 = and(UInt<1>(0h1), out_f_roready_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_119 = and(out_f_wivalid_12, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_120 = and(UInt<1>(0h1), out_f_woready_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_121 = eq(out_rimask_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_122 = eq(out_wimask_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_123 = eq(out_romask_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_124 = eq(out_womask_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_11 = or(_out_T_115, UInt<31>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_11 = cat(DMCONTROLReg.haltreq, _out_prepend_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_125 = or(out_prepend_11, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_126 = bits(_out_T_125, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_13 = bits(out_frontMask, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_13 = orr(_out_rimask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_13 = bits(out_frontMask, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_13 = andr(_out_wimask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_13 = bits(out_backMask, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_13 = orr(_out_romask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_13 = bits(out_backMask, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_13 = andr(_out_womask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_13 = and(out_roready[13], out_romask_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_13 = and(out_woready[13], out_womask_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_127 = bits(out_front.bits.data, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_128 = and(out_f_rivalid_13, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_129 = and(UInt<1>(0h1), out_f_roready_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_130 = eq(out_rimask_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_131 = eq(out_wimask_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_132 = eq(out_romask_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_133 = eq(out_womask_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_134 = or(HARTINFORdData.dataaddr, UInt<12>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_135 = bits(_out_T_134, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_14 = bits(out_frontMask, 15, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_14 = orr(_out_rimask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_14 = bits(out_frontMask, 15, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_14 = andr(_out_wimask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_14 = bits(out_backMask, 15, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_14 = orr(_out_romask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_14 = bits(out_backMask, 15, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_14 = andr(_out_womask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_14 = and(out_roready[14], out_romask_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_14 = and(out_woready[14], out_womask_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_136 = bits(out_front.bits.data, 15, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_137 = and(out_f_rivalid_14, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_138 = and(UInt<1>(0h1), out_f_roready_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_139 = eq(out_rimask_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_140 = eq(out_wimask_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_141 = eq(out_romask_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_142 = eq(out_womask_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_12 = or(_out_T_135, UInt<12>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_12 = cat(HARTINFORdData.datasize, _out_prepend_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_143 = or(out_prepend_12, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_144 = bits(_out_T_143, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_15 = bits(out_frontMask, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_15 = orr(_out_rimask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_15 = bits(out_frontMask, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_15 = andr(_out_wimask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_15 = bits(out_backMask, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_15 = orr(_out_romask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_15 = bits(out_backMask, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_15 = andr(_out_womask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_15 = and(out_roready[15], out_romask_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_15 = and(out_woready[15], out_womask_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_145 = bits(out_front.bits.data, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_146 = and(out_f_rivalid_15, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_147 = and(UInt<1>(0h1), out_f_roready_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_148 = eq(out_rimask_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_149 = eq(out_wimask_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_150 = eq(out_romask_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_151 = eq(out_womask_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_13 = or(_out_T_144, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_13 = cat(HARTINFORdData.dataaccess, _out_prepend_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_152 = or(out_prepend_13, UInt<17>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_153 = bits(_out_T_152, 16, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_16 = bits(out_frontMask, 19, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_16 = orr(_out_rimask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_16 = bits(out_frontMask, 19, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_16 = andr(_out_wimask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_16 = bits(out_backMask, 19, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_16 = orr(_out_romask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_16 = bits(out_backMask, 19, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_16 = andr(_out_womask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_16 = and(out_rivalid[16], out_rimask_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_16 = and(out_roready[16], out_romask_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_16 = and(out_wivalid[16], out_wimask_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_16 = and(out_woready[16], out_womask_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_154 = bits(out_front.bits.data, 19, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_155 = and(out_f_rivalid_16, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_156 = and(UInt<1>(0h1), out_f_roready_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_157 = eq(out_rimask_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_158 = eq(out_wimask_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_159 = eq(out_romask_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_160 = eq(out_womask_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_14 = or(_out_T_153, UInt<17>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_14 = cat(UInt<1>(0h0), _out_prepend_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_161 = or(out_prepend_14, UInt<20>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_162 = bits(_out_T_161, 19, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_17 = bits(out_frontMask, 23, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_17 = orr(_out_rimask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_17 = bits(out_frontMask, 23, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_17 = andr(_out_wimask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_17 = bits(out_backMask, 23, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_17 = orr(_out_romask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_17 = bits(out_backMask, 23, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_17 = andr(_out_womask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_17 = and(out_rivalid[17], out_rimask_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_17 = and(out_roready[17], out_romask_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_17 = and(out_wivalid[17], out_wimask_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_17 = and(out_woready[17], out_womask_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_163 = bits(out_front.bits.data, 23, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_164 = and(out_f_rivalid_17, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_165 = and(UInt<1>(0h1), out_f_roready_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_166 = eq(out_rimask_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_167 = eq(out_wimask_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_168 = eq(out_romask_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_169 = eq(out_womask_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_15 = or(_out_T_162, UInt<20>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_15 = cat(HARTINFORdData.nscratch, _out_prepend_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_170 = or(out_prepend_15, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_171 = bits(_out_T_170, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T = bits(out_front.bits.index, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex = bits(out_front.bits.index, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_1 = bits(out_front.bits.index, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T = bits(out_front.bits.index, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex = bits(out_front.bits.index, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_1 = bits(out_front.bits.index, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node out_backSel_0 = bits(_out_backSel_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_1 = bits(_out_backSel_T, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T = and(in.valid, out_front.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[12], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[11], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[10], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[9], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[8], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[7], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[6], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[5], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[4], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[3], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[2], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[1], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[0], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[17], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[16], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[15], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[14], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[13], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_10 = geq(out_iindex, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_rifireMux_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_rifireMux = mux(_out_rifireMux_T_10, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_wifireMux_T = and(in.valid, out_front.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[12], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[11], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[10], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[9], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[8], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[7], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[6], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[5], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[4], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[3], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[2], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[1], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[0], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[17], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[16], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[15], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[14], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[13], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_11 = geq(out_iindex, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_wifireMux_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_wifireMux = mux(_out_wifireMux_T_11, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_rofireMux_T = and(out_front.valid, out.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[12], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[11], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[10], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[9], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[8], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[7], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[6], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[5], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[4], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[3], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[2], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[1], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[0], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[17], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[16], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[15], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[14], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[13], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_10 = geq(out_oindex, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_rofireMux_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_rofireMux = mux(_out_rofireMux_T_10, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_wofireMux_T = and(out_front.valid, out.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[12], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[11], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[10], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[9], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[8], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[7], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[6], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[5], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[4], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[3], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[2], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[1], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[0], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[17], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[16], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[15], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[14], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[13], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_11 = geq(out_oindex, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_wofireMux_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_wofireMux = mux(_out_wofireMux_T_11, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_in_ready_T = and(out_front.ready, out_iready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect in.ready, _out_in_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_front_valid_T = and(in.valid, out_iready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front.valid, _out_front_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_front_ready_T = and(out.ready, out_oready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front.ready, _out_front_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_out_valid_T = and(out_front.valid, out_oready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.valid, _out_out_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.read, out_front.bits.read @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_out_bits_data_T = geq(out_oindex, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_out_bits_data_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[0], _out_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[1], _out_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_out_bits_data_T_2 = geq(out_oindex, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_out_bits_data_WIRE_1 : UInt<32>[2] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[0], _out_T_126 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[1], _out_T_171 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.data, _out_out_bits_data_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.extra, out_front.bits.extra @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect in.valid, dmiNodeIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 90:15] connect dmiNodeIn.a.ready, in.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 91:15] connect dmiNodeIn.d.valid, out.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 92:15] connect out.ready, dmiNodeIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 93:15] wire dmiNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 792:17] connect dmiNodeIn_d_bits_d.opcode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 793:15] connect dmiNodeIn_d_bits_d.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 794:15] connect dmiNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 795:15] connect dmiNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 796:15] connect dmiNodeIn_d_bits_d.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 797:15] connect dmiNodeIn_d_bits_d.denied, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 798:15] invalidate dmiNodeIn_d_bits_d.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 801:15] connect dmiNodeIn_d_bits_d.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 802:15] connect dmiNodeIn.d.bits.corrupt, dmiNodeIn_d_bits_d.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect dmiNodeIn.d.bits.data, dmiNodeIn_d_bits_d.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect dmiNodeIn.d.bits.denied, dmiNodeIn_d_bits_d.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect dmiNodeIn.d.bits.sink, dmiNodeIn_d_bits_d.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect dmiNodeIn.d.bits.source, dmiNodeIn_d_bits_d.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect dmiNodeIn.d.bits.size, dmiNodeIn_d_bits_d.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect dmiNodeIn.d.bits.param, dmiNodeIn_d_bits_d.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect dmiNodeIn.d.bits.opcode, dmiNodeIn_d_bits_d.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect dmiNodeIn.d.bits.data, out.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 100:17] node _dmiNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 105:25] connect dmiNodeIn.d.bits.opcode, _dmiNodeIn_d_bits_opcode_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 105:19] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 108:22] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 109:22] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 110:22] wire _debugIntNxt_WIRE : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 599:39] connect _debugIntNxt_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 599:39] wire debugIntNxt : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 599:31] connect debugIntNxt, _debugIntNxt_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 599:31] wire _debugIntRegs_WIRE : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 600:67] connect _debugIntRegs_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 600:67] regreset debugIntRegs : UInt<1>[1], clock, _T, _debugIntRegs_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 600:31] connect debugIntRegs, debugIntNxt @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 600:31] connect debugIntNxt, debugIntRegs @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 602:17] node _intnodeOut_0_T = or(debugIntRegs[0], io.hgDebugInt[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 605:60] connect intnodeOut[0], _intnodeOut_0_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 605:33] node _T_19 = not(DMCONTROLReg.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 610:13] node _T_20 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 610:26] node _T_21 = or(_T_19, _T_20) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 610:23] when _T_21 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 610:44] connect debugIntNxt[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 611:32] else : node _T_22 = eq(DMCONTROLWrData.hartsello, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 613:58] node _T_23 = or(_T_22, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 614:11] node _T_24 = and(haltreqWrEn, _T_23) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 613:27] when _T_24 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 614:96] connect debugIntNxt[0], DMCONTROLWrData.haltreq @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 615:34] wire innerCtrlValid : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 629:30] regreset innerCtrlValidReg : UInt<1>, clock, _T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 630:36] regreset innerCtrlResumeReqReg : UInt<1>, clock, _T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 631:40] regreset innerCtrlAckHaveResetReg : UInt<1>, clock, _T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 632:43] node _innerCtrlValid_T = or(hartselloWrEn, resumereqWrEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 634:37] node _innerCtrlValid_T_1 = or(_innerCtrlValid_T, ackhaveresetWrEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 634:53] node _innerCtrlValid_T_2 = or(_innerCtrlValid_T_1, setresethaltreqWrEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 634:72] node _innerCtrlValid_T_3 = or(_innerCtrlValid_T_2, clrresethaltreqWrEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 634:94] node _innerCtrlValid_T_4 = or(_innerCtrlValid_T_3, haselWrEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 634:116] node _innerCtrlValid_T_5 = and(HAWINDOWWrEn, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 635:22] node _innerCtrlValid_T_6 = or(_innerCtrlValid_T_4, _innerCtrlValid_T_5) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 634:128] connect innerCtrlValid, _innerCtrlValid_T_6 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 634:20] node _innerCtrlValidReg_T = not(io.innerCtrl.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 637:54] node _innerCtrlValidReg_T_1 = and(io.innerCtrl.valid, _innerCtrlValidReg_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 637:52] connect innerCtrlValidReg, _innerCtrlValidReg_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 637:30] node _innerCtrlResumeReqReg_T = not(io.innerCtrl.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 638:63] node _innerCtrlResumeReqReg_T_1 = and(io.innerCtrl.bits.resumereq, _innerCtrlResumeReqReg_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 638:61] connect innerCtrlResumeReqReg, _innerCtrlResumeReqReg_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 638:30] node _innerCtrlAckHaveResetReg_T = not(io.innerCtrl.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 639:66] node _innerCtrlAckHaveResetReg_T_1 = and(io.innerCtrl.bits.ackhavereset, _innerCtrlAckHaveResetReg_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 639:64] connect innerCtrlAckHaveResetReg, _innerCtrlAckHaveResetReg_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 639:30] node _io_innerCtrl_valid_T = or(innerCtrlValid, innerCtrlValidReg) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 641:54] connect io.innerCtrl.valid, _io_innerCtrl_valid_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 641:36] node _io_innerCtrl_bits_hartsel_T = mux(hartselloWrEn, DMCONTROLWrData.hartsello, DMCONTROLReg.hartsello) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 642:42] connect io.innerCtrl.bits.hartsel, _io_innerCtrl_bits_hartsel_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 642:36] node _io_innerCtrl_bits_resumereq_T = and(resumereqWrEn, DMCONTROLWrData.resumereq) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 643:54] node _io_innerCtrl_bits_resumereq_T_1 = or(_io_innerCtrl_bits_resumereq_T, innerCtrlResumeReqReg) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 643:83] connect io.innerCtrl.bits.resumereq, _io_innerCtrl_bits_resumereq_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 643:36] node _io_innerCtrl_bits_ackhavereset_T = and(ackhaveresetWrEn, DMCONTROLWrData.ackhavereset) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 644:57] node _io_innerCtrl_bits_ackhavereset_T_1 = or(_io_innerCtrl_bits_ackhavereset_T, innerCtrlAckHaveResetReg) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 644:89] connect io.innerCtrl.bits.ackhavereset, _io_innerCtrl_bits_ackhavereset_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 644:36] connect io.innerCtrl.bits.hrmask, hrmask @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 645:36] invalidate io.innerCtrl.bits.hasel @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 650:31] invalidate io.innerCtrl.bits.hamask[0] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 651:32] connect io.ctrl.ndreset, DMCONTROLReg.ndmreset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 654:21] connect io.ctrl.dmactive, DMCONTROLReg.dmactive @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 655:22] module IntSyncCrossingSource_n1x1_Registered : @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 48:9] output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeIn : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut.sync, nodeIn @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 52:16] module TLBusBypassBar : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 69:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 69:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 69:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output io : { flip bypass : UInt<1>, pending : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 70:16] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate x1_nodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate x1_nodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out_0, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.out_1, x1_nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] regreset in_reset : UInt<1>, clock, reset, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 82:27] connect in_reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 82:27] reg bypass_reg : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 83:25] node bypass = mux(in_reset, io.bypass, bypass_reg) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 84:21] regreset flight : UInt<2>, clock, reset, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 295:25] node _T = and(nodeIn.a.ready, nodeIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _r_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node r_beats1_decode = shr(_r_beats1_decode_T_2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _r_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node r_beats1_opdata = eq(_r_beats1_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset r_counter : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node r_counter1 = tail(_r_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node a_first = eq(r_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _r_last_T = eq(r_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node a_last = or(_r_last_T, _r_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node r_3 = and(a_last, _T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _r_count_T = not(r_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node r_4 = and(r_beats1, _r_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _r_counter_T = mux(a_first, r_beats1, r_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect r_counter, _r_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _T_1 = and(_WIRE_1.ready, _WIRE_1.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _r_beats1_decode_T_3 = dshl(UInt<2>(0h3), _WIRE_1.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _r_beats1_opdata_T_1 = bits(_WIRE_1.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:37] node r_beats1_opdata_1 = eq(_r_beats1_opdata_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 97:28] node r_beats1_1 = mux(UInt<1>(0h0), r_beats1_decode_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset r_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node r_counter1_1 = tail(_r_counter1_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node b_first = eq(r_counter_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node b_last = or(_r_last_T_2, _r_last_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node r_3_1 = and(b_last, _T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _r_count_T_1 = not(r_counter1_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node r_4_1 = and(r_beats1_1, _r_count_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _r_counter_T_1 = mux(b_first, r_beats1_1, r_counter1_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect r_counter_1, _r_counter_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _T_2 = and(_WIRE_3.ready, _WIRE_3.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _r_beats1_decode_T_6 = dshl(UInt<2>(0h3), _WIRE_3.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _r_beats1_decode_T_7 = bits(_r_beats1_decode_T_6, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _r_beats1_decode_T_8 = not(_r_beats1_decode_T_7) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node r_beats1_decode_2 = shr(_r_beats1_decode_T_8, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node r_beats1_opdata_2 = bits(_WIRE_3.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 102:36] node r_beats1_2 = mux(UInt<1>(0h0), r_beats1_decode_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset r_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _r_counter1_T_2 = sub(r_counter_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node r_counter1_2 = tail(_r_counter1_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node c_first = eq(r_counter_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _r_last_T_4 = eq(r_counter_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _r_last_T_5 = eq(r_beats1_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node c_last = or(_r_last_T_4, _r_last_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node r_3_2 = and(c_last, _T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _r_count_T_2 = not(r_counter1_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node r_4_2 = and(r_beats1_2, _r_count_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _T_2 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _r_counter_T_2 = mux(c_first, r_beats1_2, r_counter1_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect r_counter_2, _r_counter_T_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node _T_3 = and(nodeIn.d.ready, nodeIn.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _r_beats1_decode_T_9 = dshl(UInt<2>(0h3), nodeIn.d.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _r_beats1_decode_T_10 = bits(_r_beats1_decode_T_9, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _r_beats1_decode_T_11 = not(_r_beats1_decode_T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node r_beats1_decode_3 = shr(_r_beats1_decode_T_11, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node r_beats1_opdata_3 = bits(nodeIn.d.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node r_beats1_3 = mux(r_beats1_opdata_3, r_beats1_decode_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset r_counter_3 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _r_counter1_T_3 = sub(r_counter_3, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node r_counter1_3 = tail(_r_counter1_T_3, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node d_first = eq(r_counter_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _r_last_T_6 = eq(r_counter_3, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _r_last_T_7 = eq(r_beats1_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node d_last = or(_r_last_T_6, _r_last_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node r_3_3 = and(d_last, _T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _r_count_T_3 = not(r_counter1_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node r_4_3 = and(r_beats1_3, _r_count_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _T_3 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _r_counter_T_3 = mux(d_first, r_beats1_3, r_counter1_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect r_counter_3, _r_counter_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] node _T_4 = and(_WIRE_5.ready, _WIRE_5.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] regreset r_counter_4 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _r_counter1_T_4 = sub(r_counter_4, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node r_counter1_4 = tail(_r_counter1_T_4, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node e_first = eq(r_counter_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _r_last_T_8 = eq(r_counter_4, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _r_last_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node e_last = or(_r_last_T_8, _r_last_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node r_3_4 = and(e_last, _T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _r_count_T_4 = not(r_counter1_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node r_4_4 = and(UInt<1>(0h0), _r_count_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _r_counter_T_4 = mux(e_first, UInt<1>(0h0), r_counter1_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect r_counter_4, _r_counter_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _T_5 = bits(_WIRE_11.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 68:36] node _T_6 = bits(_WIRE_11.bits.opcode, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 68:51] node c_request = and(_T_5, _T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 68:40] wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_12.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.bits, _WIRE_12.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.valid, _WIRE_12.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_13.ready, _WIRE_12.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _T_7 = bits(_WIRE_13.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 82:37] node _T_8 = eq(_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 82:28] node _T_9 = bits(_WIRE_13.bits.opcode, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 82:53] node _T_10 = eq(_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 82:44] node c_response = or(_T_8, _T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 82:41] node _T_11 = bits(nodeIn.d.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 71:36] node _T_12 = bits(nodeIn.d.bits.opcode, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 71:52] node _T_13 = eq(_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 71:43] node d_request = and(_T_11, _T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 71:40] wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_14.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_14.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_14.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_15.bits, _WIRE_14.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_15.valid, _WIRE_14.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_15.ready, _WIRE_14.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_16.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.bits, _WIRE_16.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.valid, _WIRE_16.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_17.ready, _WIRE_16.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] node _a_inc_T = and(nodeIn.a.ready, nodeIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _a_inc_T_1 = and(_a_inc_T, a_first) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 310:26] node a_inc = and(_a_inc_T_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 310:37] wire _b_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_inc_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_inc_WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_inc_WIRE.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_inc_WIRE.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_inc_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_inc_WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_inc_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_inc_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_inc_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_inc_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _b_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _b_inc_WIRE_1.bits, _b_inc_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _b_inc_WIRE_1.valid, _b_inc_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _b_inc_WIRE_1.ready, _b_inc_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _b_inc_T = and(_b_inc_WIRE_1.ready, _b_inc_WIRE_1.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _b_inc_T_1 = and(_b_inc_T, b_first) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 311:26] node b_inc = and(_b_inc_T_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 311:37] wire _c_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_inc_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_inc_WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_inc_WIRE.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_inc_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_inc_WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_inc_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_inc_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_inc_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_inc_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _c_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _c_inc_WIRE_1.bits, _c_inc_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _c_inc_WIRE_1.valid, _c_inc_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _c_inc_WIRE_1.ready, _c_inc_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _c_inc_T = and(_c_inc_WIRE_1.ready, _c_inc_WIRE_1.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _c_inc_T_1 = and(_c_inc_T, c_first) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 312:26] node c_inc = and(_c_inc_T_1, c_request) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 312:37] node _d_inc_T = and(nodeIn.d.ready, nodeIn.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _d_inc_T_1 = and(_d_inc_T, d_first) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 313:26] node d_inc = and(_d_inc_T_1, d_request) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 313:37] wire _e_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _e_inc_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _e_inc_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _e_inc_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _e_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _e_inc_WIRE_1.bits, _e_inc_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _e_inc_WIRE_1.valid, _e_inc_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _e_inc_WIRE_1.ready, _e_inc_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] node _e_inc_T = and(_e_inc_WIRE_1.ready, _e_inc_WIRE_1.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _e_inc_T_1 = and(_e_inc_T, e_first) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 314:26] node e_inc = and(_e_inc_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 314:37] node inc = cat(a_inc, d_inc) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 315:18] node _a_dec_T = and(nodeIn.a.ready, nodeIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _a_dec_T_1 = and(_a_dec_T, a_last) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 317:26] node a_dec = and(_a_dec_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 317:36] wire _b_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_dec_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_dec_WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_dec_WIRE.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_dec_WIRE.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_dec_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_dec_WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_dec_WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_dec_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_dec_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _b_dec_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _b_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _b_dec_WIRE_1.bits, _b_dec_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _b_dec_WIRE_1.valid, _b_dec_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _b_dec_WIRE_1.ready, _b_dec_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] node _b_dec_T = and(_b_dec_WIRE_1.ready, _b_dec_WIRE_1.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _b_dec_T_1 = and(_b_dec_T, b_last) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 318:26] node b_dec = and(_b_dec_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 318:36] wire _c_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_dec_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_dec_WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_dec_WIRE.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_dec_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_dec_WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_dec_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_dec_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_dec_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_dec_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _c_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _c_dec_WIRE_1.bits, _c_dec_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _c_dec_WIRE_1.valid, _c_dec_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _c_dec_WIRE_1.ready, _c_dec_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] node _c_dec_T = and(_c_dec_WIRE_1.ready, _c_dec_WIRE_1.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _c_dec_T_1 = and(_c_dec_T, c_last) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 319:26] node c_dec = and(_c_dec_T_1, c_response) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 319:36] node _d_dec_T = and(nodeIn.d.ready, nodeIn.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _d_dec_T_1 = and(_d_dec_T, d_last) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 320:26] node d_dec = and(_d_dec_T_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 320:36] wire _e_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _e_dec_WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _e_dec_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _e_dec_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _e_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _e_dec_WIRE_1.bits, _e_dec_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _e_dec_WIRE_1.valid, _e_dec_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _e_dec_WIRE_1.ready, _e_dec_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] node _e_dec_T = and(_e_dec_WIRE_1.ready, _e_dec_WIRE_1.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _e_dec_T_1 = and(_e_dec_T, e_last) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 321:26] node e_dec = and(_e_dec_T_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 321:36] node dec = cat(a_dec, d_dec) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 322:18] node _next_flight_T = bits(inc, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 324:40] node _next_flight_T_1 = bits(inc, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 324:40] node _next_flight_T_2 = add(_next_flight_T, _next_flight_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 324:40] node _next_flight_T_3 = bits(_next_flight_T_2, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 324:40] node _next_flight_T_4 = add(flight, _next_flight_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 324:30] node _next_flight_T_5 = tail(_next_flight_T_4, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 324:30] node _next_flight_T_6 = bits(dec, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 324:56] node _next_flight_T_7 = bits(dec, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 324:56] node _next_flight_T_8 = add(_next_flight_T_6, _next_flight_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 324:56] node _next_flight_T_9 = bits(_next_flight_T_8, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 324:56] node _next_flight_T_10 = sub(_next_flight_T_5, _next_flight_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 324:46] node next_flight = tail(_next_flight_T_10, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 324:46] connect flight, next_flight @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 325:12] node _io_pending_T = gt(flight, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 87:27] connect io.pending, _io_pending_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 87:16] node _T_14 = eq(next_flight, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 88:36] node _T_15 = or(in_reset, _T_14) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 88:20] when _T_15 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 88:46] connect bypass_reg, io.bypass @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 88:59] node _stall_T = neq(bypass, io.bypass) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 89:25] node _stall_T_1 = and(nodeIn.a.ready, nodeIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _stall_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _stall_beats1_decode_T_1 = bits(_stall_beats1_decode_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _stall_beats1_decode_T_2 = not(_stall_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node stall_beats1_decode = shr(_stall_beats1_decode_T_2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _stall_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node stall_beats1_opdata = eq(_stall_beats1_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node stall_beats1 = mux(stall_beats1_opdata, stall_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset stall_counter : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _stall_counter1_T = sub(stall_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node stall_counter1 = tail(_stall_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node stall_first = eq(stall_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _stall_last_T = eq(stall_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _stall_last_T_1 = eq(stall_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node stall_last = or(_stall_last_T, _stall_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node stall_done = and(stall_last, _stall_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _stall_count_T = not(stall_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node stall_count = and(stall_beats1, _stall_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _stall_T_1 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _stall_counter_T = mux(stall_first, stall_beats1, stall_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect stall_counter, _stall_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node stall = and(_stall_T, stall_first) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 89:40] node _nodeOut_a_valid_T = eq(stall, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 91:21] node _nodeOut_a_valid_T_1 = and(_nodeOut_a_valid_T, nodeIn.a.valid) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 91:28] node _nodeOut_a_valid_T_2 = and(_nodeOut_a_valid_T_1, bypass) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 91:42] connect nodeOut.a.valid, _nodeOut_a_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 91:18] node _nodeOut_a_valid_T_3 = eq(stall, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 92:21] node _nodeOut_a_valid_T_4 = and(_nodeOut_a_valid_T_3, nodeIn.a.valid) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 92:28] node _nodeOut_a_valid_T_5 = eq(bypass, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 92:45] node _nodeOut_a_valid_T_6 = and(_nodeOut_a_valid_T_4, _nodeOut_a_valid_T_5) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 92:42] connect x1_nodeOut.a.valid, _nodeOut_a_valid_T_6 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 92:18] node _nodeIn_a_ready_T = eq(stall, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 93:21] node _nodeIn_a_ready_T_1 = mux(bypass, nodeOut.a.ready, x1_nodeOut.a.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 93:34] node _nodeIn_a_ready_T_2 = and(_nodeIn_a_ready_T, _nodeIn_a_ready_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 93:28] connect nodeIn.a.ready, _nodeIn_a_ready_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 93:18] connect nodeOut.a.bits, nodeIn.a.bits @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 94:18] connect x1_nodeOut.a.bits, nodeIn.a.bits @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 95:18] node _nodeOut_d_ready_T = and(nodeIn.d.ready, bypass) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 97:32] connect nodeOut.d.ready, _nodeOut_d_ready_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 97:18] node _nodeOut_d_ready_T_1 = eq(bypass, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 98:35] node _nodeOut_d_ready_T_2 = and(nodeIn.d.ready, _nodeOut_d_ready_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 98:32] connect x1_nodeOut.d.ready, _nodeOut_d_ready_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 98:18] node _nodeIn_d_valid_T = mux(bypass, nodeOut.d.valid, x1_nodeOut.d.valid) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 99:24] connect nodeIn.d.valid, _nodeIn_d_valid_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 99:18] wire nodeIn_d_bits_out : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 100:53] connect nodeIn_d_bits_out, nodeIn.d.bits @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 100:53] connect nodeIn_d_bits_out, nodeOut.d.bits @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 100:70] wire nodeIn_d_bits_out_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 100:53] connect nodeIn_d_bits_out_1, nodeIn.d.bits @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 100:53] connect nodeIn_d_bits_out_1, x1_nodeOut.d.bits @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 100:70] node _nodeIn_d_bits_T = mux(bypass, nodeIn_d_bits_out, nodeIn_d_bits_out_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 101:21] connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_T.corrupt @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 101:15] connect nodeIn.d.bits.data, _nodeIn_d_bits_T.data @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 101:15] connect nodeIn.d.bits.denied, _nodeIn_d_bits_T.denied @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 101:15] connect nodeIn.d.bits.sink, _nodeIn_d_bits_T.sink @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 101:15] connect nodeIn.d.bits.source, _nodeIn_d_bits_T.source @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 101:15] connect nodeIn.d.bits.size, _nodeIn_d_bits_T.size @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 101:15] connect nodeIn.d.bits.param, _nodeIn_d_bits_T.param @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 101:15] connect nodeIn.d.bits.opcode, _nodeIn_d_bits_T.opcode @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 101:15] wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_18.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_18.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_18.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_18.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_18.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_18.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_18.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_18.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_18.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_18.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_19.bits, _WIRE_18.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_19.valid, _WIRE_18.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_19.ready, _WIRE_18.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_19.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 122:18] wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_20.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_20.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_20.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_20.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_20.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_20.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_20.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_20.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_20.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_21.bits, _WIRE_20.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_21.valid, _WIRE_20.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_21.ready, _WIRE_20.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_21.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 123:18] wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_22.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.bits, _WIRE_22.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.valid, _WIRE_22.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, _WIRE_22.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_23.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 124:18] wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.address, UInt<128>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_24.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.bits, _WIRE_24.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.valid, _WIRE_24.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.ready, _WIRE_24.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_25.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 126:20] wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_26.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_26.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_26.bits.address, UInt<128>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_26.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_26.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_26.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_26.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_26.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_26.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_27.bits, _WIRE_26.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_27.valid, _WIRE_26.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_27.ready, _WIRE_26.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_27.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 127:20] wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_28.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_28.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_28.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_29.bits, _WIRE_28.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_29.valid, _WIRE_28.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_29.ready, _WIRE_28.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_29.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 128:20] wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_30.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.bits, _WIRE_30.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.valid, _WIRE_30.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.ready, _WIRE_30.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_31.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 130:20] wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_32.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.bits, _WIRE_32.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.valid, _WIRE_32.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.ready, _WIRE_32.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_33.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 131:20] wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_34.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_34.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_34.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_35.bits, _WIRE_34.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_35.valid, _WIRE_34.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_35.ready, _WIRE_34.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_35.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 132:20] module TLError_1 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 21:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 21:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 21:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] wire da : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 28:18] regreset idle : UInt<1>, clock, reset, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 29:23] node _a_last_T = and(nodeIn.a.ready, nodeIn.a.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _a_last_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _a_last_beats1_decode_T_1 = bits(_a_last_beats1_decode_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _a_last_beats1_decode_T_2 = not(_a_last_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node a_last_beats1_decode = shr(_a_last_beats1_decode_T_2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node _a_last_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node a_last_beats1_opdata = eq(_a_last_beats1_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node a_last_beats1 = mux(a_last_beats1_opdata, a_last_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset a_last_counter : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _a_last_counter1_T = sub(a_last_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node a_last_counter1 = tail(_a_last_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node a_last_first = eq(a_last_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _a_last_last_T = eq(a_last_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _a_last_last_T_1 = eq(a_last_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node a_last = or(_a_last_last_T, _a_last_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node a_last_done = and(a_last, _a_last_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _a_last_count_T = not(a_last_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node a_last_count = and(a_last_beats1, _a_last_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _a_last_T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _a_last_counter_T = mux(a_last_first, a_last_beats1, a_last_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect a_last_counter, _a_last_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node _T = and(da.ready, da.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _r_beats1_decode_T = dshl(UInt<2>(0h3), da.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node r_beats1_decode = shr(_r_beats1_decode_T_2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node r_beats1_opdata = bits(da.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset r_counter : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node r_counter1 = tail(_r_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node da_first = eq(r_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _r_last_T = eq(r_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node da_last = or(_r_last_T, _r_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node r_3 = and(da_last, _T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _r_count_T = not(r_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node r_4 = and(r_beats1, _r_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _r_counter_T = mux(da_first, r_beats1, r_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect r_counter, _r_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node _T_1 = or(idle, da_first) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 34:18] node _T_2 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 34:12] node _T_3 = eq(_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 34:12] when _T_3 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 34:12] node _T_4 = eq(_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 34:12] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 34:12] printf(clock, UInt<1>(0h1), "Assertion failed\n at Error.scala:34 assert (idle || da_first) // we only send Grant, never GrantData => simplified flow control below\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 34:12] assert(clock, _T_1, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 34:12] node _nodeIn_a_ready_T = and(da.ready, da_last) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 35:26] node _nodeIn_a_ready_T_1 = and(_nodeIn_a_ready_T, idle) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 35:37] node _nodeIn_a_ready_T_2 = eq(a_last, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 35:49] node _nodeIn_a_ready_T_3 = or(_nodeIn_a_ready_T_1, _nodeIn_a_ready_T_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 35:46] connect nodeIn.a.ready, _nodeIn_a_ready_T_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 35:13] node _da_valid_T = and(nodeIn.a.valid, a_last) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 36:25] node _da_valid_T_1 = and(_da_valid_T, idle) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 36:35] connect da.valid, _da_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 36:14] wire _da_bits_opcode_WIRE : UInt<3>[8] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 47:27] connect _da_bits_opcode_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 47:27] connect _da_bits_opcode_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 47:27] connect _da_bits_opcode_WIRE[2], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 47:27] connect _da_bits_opcode_WIRE[3], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 47:27] connect _da_bits_opcode_WIRE[4], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 47:27] connect _da_bits_opcode_WIRE[5], UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 47:27] connect _da_bits_opcode_WIRE[6], UInt<3>(0h4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 47:27] connect _da_bits_opcode_WIRE[7], UInt<3>(0h4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 47:27] connect da.bits.opcode, _da_bits_opcode_WIRE[nodeIn.a.bits.opcode] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 38:21] connect da.bits.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 39:21] connect da.bits.size, nodeIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 40:21] connect da.bits.source, nodeIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 41:21] connect da.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 42:21] connect da.bits.denied, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 43:21] connect da.bits.data, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 44:21] node da_bits_corrupt_opdata = bits(da.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] connect da.bits.corrupt, da_bits_corrupt_opdata @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 45:21] wire _c_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_WIRE.bits.address, UInt<128>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_WIRE.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _c_WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect c.bits, _c_WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect c.valid, _c_WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect c.ready, _c_WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] wire dc : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 49:20] node _c_last_T = and(c.ready, c.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _c_last_beats1_decode_T = dshl(UInt<2>(0h3), c.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _c_last_beats1_decode_T_1 = bits(_c_last_beats1_decode_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _c_last_beats1_decode_T_2 = not(_c_last_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node c_last_beats1_decode = shr(_c_last_beats1_decode_T_2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node c_last_beats1_opdata = bits(c.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 102:36] node c_last_beats1 = mux(UInt<1>(0h0), c_last_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset c_last_counter : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _c_last_counter1_T = sub(c_last_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node c_last_counter1 = tail(_c_last_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node c_last_first = eq(c_last_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _c_last_last_T = eq(c_last_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _c_last_last_T_1 = eq(c_last_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node c_last = or(_c_last_last_T, _c_last_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node c_last_done = and(c_last, _c_last_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _c_last_count_T = not(c_last_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node c_last_count = and(c_last_beats1, _c_last_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _c_last_T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _c_last_counter_T = mux(c_last_first, c_last_beats1, c_last_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect c_last_counter, _c_last_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node _dc_last_T = and(dc.ready, dc.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _dc_last_beats1_decode_T = dshl(UInt<2>(0h3), dc.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _dc_last_beats1_decode_T_1 = bits(_dc_last_beats1_decode_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _dc_last_beats1_decode_T_2 = not(_dc_last_beats1_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node dc_last_beats1_decode = shr(_dc_last_beats1_decode_T_2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node dc_last_beats1_opdata = bits(dc.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node dc_last_beats1 = mux(dc_last_beats1_opdata, dc_last_beats1_decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset dc_last_counter : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 229:27] node _dc_last_counter1_T = sub(dc_last_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node dc_last_counter1 = tail(_dc_last_counter1_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 230:28] node dc_last_first = eq(dc_last_counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 231:25] node _dc_last_last_T = eq(dc_last_counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:25] node _dc_last_last_T_1 = eq(dc_last_beats1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:43] node dc_last = or(_dc_last_last_T, _dc_last_last_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 232:33] node dc_last_done = and(dc_last, _dc_last_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 233:22] node _dc_last_count_T = not(dc_last_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:27] node dc_last_count = and(dc_last_beats1, _dc_last_count_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 234:25] when _dc_last_T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 235:17] node _dc_last_counter_T = mux(dc_last_first, dc_last_beats1, dc_last_counter1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:21] connect dc_last_counter, _dc_last_counter_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 236:15] node _T_5 = and(da.ready, da.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_6 = eq(da.bits.opcode, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 55:39] node _T_7 = and(_T_5, _T_6) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 55:21] when _T_7 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 55:50] connect idle, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 55:57] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] node _T_8 = and(_WIRE_1.ready, _WIRE_1.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 56:24] connect idle, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 56:31] node _c_ready_T = and(dc.ready, dc_last) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 58:28] node _c_ready_T_1 = eq(c_last, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 58:43] node _c_ready_T_2 = or(_c_ready_T, _c_ready_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 58:40] connect c.ready, _c_ready_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 58:15] node _dc_valid_T = and(c.valid, c_last) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 59:27] connect dc.valid, _dc_valid_T @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 59:16] connect dc.bits.opcode, UInt<3>(0h6) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 62:23] wire _dc_bits_param_WIRE : UInt<2>[3] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 63:33] connect _dc_bits_param_WIRE[0], UInt<2>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 63:33] connect _dc_bits_param_WIRE[1], UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 63:33] connect _dc_bits_param_WIRE[2], UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 63:33] node _dc_bits_param_T = bits(c.bits.param, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 63:61] connect dc.bits.param, _dc_bits_param_WIRE[_dc_bits_param_T] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 63:23] connect dc.bits.size, c.bits.size @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 64:23] connect dc.bits.source, c.bits.source @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 65:23] connect dc.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 66:23] connect dc.bits.denied, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 67:23] connect dc.bits.data, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 68:23] connect dc.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 69:23] node _decode_T = dshl(UInt<2>(0h3), dc.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _decode_T_1 = bits(_decode_T, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _decode_T_2 = not(_decode_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node decode = shr(_decode_T_2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node opdata = bits(dc.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node _T_9 = mux(opdata, decode, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] node _decode_T_3 = dshl(UInt<2>(0h3), da.bits.size) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:71] node _decode_T_4 = bits(_decode_T_3, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:76] node _decode_T_5 = not(_decode_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 244:46] node decode_1 = shr(_decode_T_5, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 220:59] node opdata_1 = bits(da.bits.opcode, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 106:36] node _T_10 = mux(opdata_1, decode_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 221:14] regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 60:30] node idle_1 = eq(beatsLeft, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 61:28] node latch = and(idle_1, nodeIn.d.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 62:24] node _readys_T = cat(da.valid, dc.valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:51] node _readys_T_1 = shl(_readys_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:48] node _readys_T_2 = bits(_readys_T_1, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:53] node _readys_T_3 = or(_readys_T, _readys_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 254:43] node _readys_T_4 = bits(_readys_T_3, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 255:17] node _readys_T_5 = shl(_readys_T_4, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 16:78] node _readys_T_6 = bits(_readys_T_5, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 16:83] node _readys_T_7 = not(_readys_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 16:61] node _readys_T_8 = bits(_readys_T_7, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] node _readys_T_9 = bits(_readys_T_7, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:76] wire readys : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[0], _readys_T_8 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] connect readys[1], _readys_T_9 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 68:27] node _winner_T = and(readys[0], dc.valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] node _winner_T_1 = and(readys[1], da.valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:69] wire winner : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[0], _winner_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] connect winner[1], _winner_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 71:27] node prefixOR_1 = or(UInt<1>(0h0), winner[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node _prefixOR_T = or(prefixOR_1, winner[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 76:48] node _T_11 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_12 = eq(winner[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_13 = or(_T_11, _T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_14 = eq(prefixOR_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:56] node _T_15 = eq(winner[1], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:62] node _T_16 = or(_T_14, _T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:59] node _T_17 = and(_T_13, _T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:77] node _T_18 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_19 = eq(_T_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] when _T_19 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_20 = eq(_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] when _T_20 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] assert(clock, _T_17, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 77:13] node _T_21 = or(dc.valid, da.valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:31] node _T_22 = eq(_T_21, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:15] node _T_23 = or(winner[0], winner[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:54] node _T_24 = or(_T_22, _T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:36] node _T_25 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node _T_26 = eq(_T_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] when _T_26 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node _T_27 = eq(_T_24, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] when _T_27 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] assert(clock, _T_24, UInt<1>(0h1), "") : assert_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 79:14] node maskedBeats_0 = mux(winner[0], _T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node maskedBeats_1 = mux(winner[1], _T_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 82:69] node initBeats = or(maskedBeats_0, maskedBeats_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 84:44] node _beatsLeft_T = and(nodeIn.d.ready, nodeIn.d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:52] node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:52] node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:23] connect beatsLeft, _beatsLeft_T_3 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 85:17] wire _state_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] connect _state_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:34] regreset state : UInt<1>[2], clock, reset, _state_WIRE @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 88:26] node muxState = mux(idle_1, winner, state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 89:25] connect state, muxState @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 90:13] node allowed = mux(idle_1, readys, state) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 92:24] node _dc_ready_T = and(nodeIn.d.ready, allowed[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect dc.ready, _dc_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _da_ready_T = and(nodeIn.d.ready, allowed[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:31] connect da.ready, _da_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 94:17] node _nodeIn_d_valid_T = or(dc.valid, da.valid) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:46] node _nodeIn_d_valid_T_1 = mux(state[0], dc.valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_valid_T_2 = mux(state[1], da.valid, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_valid_T_3 = or(_nodeIn_d_valid_T_1, _nodeIn_d_valid_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeIn_d_valid_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_valid_WIRE, _nodeIn_d_valid_T_3 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_valid_T_4 = mux(idle_1, _nodeIn_d_valid_T, _nodeIn_d_valid_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:24] connect nodeIn.d.valid, _nodeIn_d_valid_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 96:18] wire _nodeIn_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T = mux(muxState[0], dc.bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_1 = mux(muxState[1], da.bits.corrupt, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_2 = or(_nodeIn_d_bits_T, _nodeIn_d_bits_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeIn_d_bits_WIRE_1 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_bits_WIRE_1, _nodeIn_d_bits_T_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_bits_WIRE.corrupt, _nodeIn_d_bits_WIRE_1 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_3 = mux(muxState[0], dc.bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_4 = mux(muxState[1], da.bits.data, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_5 = or(_nodeIn_d_bits_T_3, _nodeIn_d_bits_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeIn_d_bits_WIRE_2 : UInt<32> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_bits_WIRE_2, _nodeIn_d_bits_T_5 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_bits_WIRE.data, _nodeIn_d_bits_WIRE_2 @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeIn_d_bits_WIRE_3 : { } @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_bits_WIRE.echo, _nodeIn_d_bits_WIRE_3 @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeIn_d_bits_WIRE_4 : { } @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_bits_WIRE.user, _nodeIn_d_bits_WIRE_4 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_6 = mux(muxState[0], dc.bits.denied, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_7 = mux(muxState[1], da.bits.denied, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_8 = or(_nodeIn_d_bits_T_6, _nodeIn_d_bits_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeIn_d_bits_WIRE_5 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_bits_WIRE_5, _nodeIn_d_bits_T_8 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_bits_WIRE.denied, _nodeIn_d_bits_WIRE_5 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_9 = mux(muxState[0], dc.bits.sink, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_10 = mux(muxState[1], da.bits.sink, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_11 = or(_nodeIn_d_bits_T_9, _nodeIn_d_bits_T_10) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeIn_d_bits_WIRE_6 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_bits_WIRE_6, _nodeIn_d_bits_T_11 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_bits_WIRE.sink, _nodeIn_d_bits_WIRE_6 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_12 = mux(muxState[0], dc.bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_13 = mux(muxState[1], da.bits.source, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_14 = or(_nodeIn_d_bits_T_12, _nodeIn_d_bits_T_13) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeIn_d_bits_WIRE_7 : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_bits_WIRE_7, _nodeIn_d_bits_T_14 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_bits_WIRE.source, _nodeIn_d_bits_WIRE_7 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_15 = mux(muxState[0], dc.bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_16 = mux(muxState[1], da.bits.size, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_17 = or(_nodeIn_d_bits_T_15, _nodeIn_d_bits_T_16) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeIn_d_bits_WIRE_8 : UInt<2> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_bits_WIRE_8, _nodeIn_d_bits_T_17 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_bits_WIRE.size, _nodeIn_d_bits_WIRE_8 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_18 = mux(muxState[0], dc.bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_19 = mux(muxState[1], da.bits.param, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_20 = or(_nodeIn_d_bits_T_18, _nodeIn_d_bits_T_19) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeIn_d_bits_WIRE_9 : UInt<2> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_bits_WIRE_9, _nodeIn_d_bits_T_20 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_bits_WIRE.param, _nodeIn_d_bits_WIRE_9 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_21 = mux(muxState[0], dc.bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_22 = mux(muxState[1], da.bits.opcode, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_d_bits_T_23 = or(_nodeIn_d_bits_T_21, _nodeIn_d_bits_T_22) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeIn_d_bits_WIRE_10 : UInt<3> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_bits_WIRE_10, _nodeIn_d_bits_T_23 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_d_bits_WIRE.opcode, _nodeIn_d_bits_WIRE_10 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_WIRE.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeIn.d.bits.data, _nodeIn_d_bits_WIRE.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeIn.d.bits.denied, _nodeIn_d_bits_WIRE.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeIn.d.bits.sink, _nodeIn_d_bits_WIRE.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeIn.d.bits.source, _nodeIn_d_bits_WIRE.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeIn.d.bits.size, _nodeIn_d_bits_WIRE.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeIn.d.bits.param, _nodeIn_d_bits_WIRE.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] connect nodeIn.d.bits.opcode, _nodeIn_d_bits_WIRE.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Arbiter.scala 97:17] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.address, UInt<128>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_3.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 78:16] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/Error.scala 81:16] module TLBusBypass : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 44:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 44:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 44:9] output auto : { node_out_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, flip node_in_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output io : { flip bypass : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 45:16] inst bar of TLBusBypassBar @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 20:33] connect bar.clock, clock connect bar.reset, reset inst error of TLError_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 30:40] connect error.clock, clock connect error.reset, reset wire nodeInOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeInOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeInOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire nodeInIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeInIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeInIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect nodeInOut, nodeInIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire nodeOutOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOutOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOutOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire nodeOutIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeOutIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeOutIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect nodeOutOut, nodeOutIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect bar.auto.in, nodeInOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect error.auto.in, bar.auto.out_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect bar.auto.out_1.d, nodeOutIn.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect nodeOutIn.a.bits, bar.auto.out_1.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect nodeOutIn.a.valid, bar.auto.out_1.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect bar.auto.out_1.a.ready, nodeOutIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect nodeInIn, auto.node_in_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.node_out_out, nodeOutOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect bar.io.bypass, io.bypass @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala 48:26] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_source_valid_0.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_2 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_2 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_2 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_2 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_source_valid_1.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_3 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_3 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_2 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_sink_extend.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_3 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_sink_valid.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncQueueSource_TLBundleA_a9d32s1k1z2u : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 70:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 70:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 70:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, async : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 73:14] wire sink_ready : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 81:28] connect sink_ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 81:28] reg mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 82:16] node _widx_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 83:30] node _widx_T_1 = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _widx_T_2 = eq(sink_ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 83:77] wire widx_incremented : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 51:27] regreset widx_widx_bin : UInt, clock, _widx_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 52:25] connect widx_widx_bin, widx_incremented @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 52:25] node _widx_incremented_T = add(widx_widx_bin, _widx_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:43] node _widx_incremented_T_1 = tail(_widx_incremented_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:43] node _widx_incremented_T_2 = mux(_widx_T_2, UInt<1>(0h0), _widx_incremented_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:23] connect widx_incremented, _widx_incremented_T_2 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:17] node _widx_T_3 = shr(widx_incremented, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 54:32] node widx = xor(widx_incremented, _widx_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 54:17] inst ridx_ridx_gray of AsyncResetSynchronizerShiftReg_w1_d3_i0 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect ridx_ridx_gray.clock, clock connect ridx_ridx_gray.reset, reset connect ridx_ridx_gray.io.d, io.async.ridx @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire ridx : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect ridx, ridx_ridx_gray.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] node _ready_T = xor(ridx, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 85:44] node _ready_T_1 = neq(widx, _ready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 85:34] node ready = and(sink_ready, _ready_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 85:26] node _T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 88:22] connect mem[0], io.enq.bits @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 88:35] node _ready_reg_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 90:35] regreset ready_reg : UInt<1>, clock, _ready_reg_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 90:56] connect ready_reg, ready @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 90:56] node _io_enq_ready_T = and(ready_reg, sink_ready) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 91:29] connect io.enq.ready, _io_enq_ready_T @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 91:16] node _widx_reg_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 93:34] regreset widx_gray : UInt, clock, _widx_reg_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 93:55] connect widx_gray, widx @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 93:55] connect io.async.widx, widx_gray @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 94:17] connect io.async.mem, mem @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 98:31] inst source_valid_0 of AsyncValidSync @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 102:32] inst source_valid_1 of AsyncValidSync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 103:32] inst sink_extend of AsyncValidSync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 105:30] inst sink_valid of AsyncValidSync_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 106:30] node _source_valid_0_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 107:36] node _source_valid_0_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 107:46] node _source_valid_0_reset_T_2 = or(_source_valid_0_reset_T, _source_valid_0_reset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 107:43] node _source_valid_0_reset_T_3 = asAsyncReset(_source_valid_0_reset_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 107:65] connect source_valid_0.reset, _source_valid_0_reset_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 107:26] node _source_valid_1_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 108:36] node _source_valid_1_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 108:46] node _source_valid_1_reset_T_2 = or(_source_valid_1_reset_T, _source_valid_1_reset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 108:43] node _source_valid_1_reset_T_3 = asAsyncReset(_source_valid_1_reset_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 108:65] connect source_valid_1.reset, _source_valid_1_reset_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 108:26] node _sink_extend_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 109:36] node _sink_extend_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 109:46] node _sink_extend_reset_T_2 = or(_sink_extend_reset_T, _sink_extend_reset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 109:43] node _sink_extend_reset_T_3 = asAsyncReset(_sink_extend_reset_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 109:65] connect sink_extend.reset, _sink_extend_reset_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 109:26] node _sink_valid_reset_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 110:35] connect sink_valid.reset, _sink_valid_reset_T @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 110:26] connect source_valid_0.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 112:26] connect source_valid_1.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 113:26] connect sink_extend.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 114:26] connect sink_valid.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 115:26] connect source_valid_0.io.in, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 117:26] connect source_valid_1.io.in, source_valid_0.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 118:26] connect io.async.safe.widx_valid, source_valid_1.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 119:20] connect sink_extend.io.in, io.async.safe.ridx_valid @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 120:23] connect sink_valid.io.in, sink_extend.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 121:22] connect sink_ready, sink_valid.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 122:16] node _io_async_safe_source_reset_n_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 123:34] node _io_async_safe_source_reset_n_T_1 = eq(_io_async_safe_source_reset_n_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 123:27] connect io.async.safe.source_reset_n, _io_async_safe_source_reset_n_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 123:24] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_5 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_5 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_5 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module ClockCrossingReg_w43 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 191:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 191:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 191:7] output io : { flip d : UInt<43>, q : UInt<43>, flip en : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 195:14] reg cdc_reg : UInt<43>, clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 201:76] when io.en : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 201:76] connect cdc_reg, io.d @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 201:76] connect io.q, cdc_reg @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 202:8] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_6 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_6 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_6 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_6 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_sink_valid_0.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_7 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_7 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_5 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_sink_valid_1.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_8 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_8 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_6 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_source_extend.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_9 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_9 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_9 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_7 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_9 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_source_valid.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncQueueSink_TLBundleD_a9d32s1k1z2u : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 136:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 136:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 136:7] output io : { deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}, flip async : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 139:14] wire source_ready : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 147:30] connect source_ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 147:30] node _ridx_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 148:30] node _ridx_T_1 = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _ridx_T_2 = eq(source_ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 148:77] wire ridx_incremented : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 51:27] regreset ridx_ridx_bin : UInt, clock, _ridx_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 52:25] connect ridx_ridx_bin, ridx_incremented @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 52:25] node _ridx_incremented_T = add(ridx_ridx_bin, _ridx_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:43] node _ridx_incremented_T_1 = tail(_ridx_incremented_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:43] node _ridx_incremented_T_2 = mux(_ridx_T_2, UInt<1>(0h0), _ridx_incremented_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:23] connect ridx_incremented, _ridx_incremented_T_2 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:17] node _ridx_T_3 = shr(ridx_incremented, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 54:32] node ridx = xor(ridx_incremented, _ridx_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 54:17] inst widx_widx_gray of AsyncResetSynchronizerShiftReg_w1_d3_i0_5 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect widx_widx_gray.clock, clock connect widx_widx_gray.reset, reset connect widx_widx_gray.io.d, io.async.widx @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire widx : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect widx, widx_widx_gray.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] node _valid_T = neq(ridx, widx) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 150:36] node valid = and(source_ready, _valid_T) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 150:28] inst io_deq_bits_deq_bits_reg of ClockCrossingReg_w43 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 207:25] connect io_deq_bits_deq_bits_reg.clock, clock connect io_deq_bits_deq_bits_reg.reset, reset node io_deq_bits_deq_bits_reg_io_d_lo_lo = cat(io.async.mem[0].data, io.async.mem[0].corrupt) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node io_deq_bits_deq_bits_reg_io_d_lo_hi_hi = cat(io.async.mem[0].denied, UInt<0>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node io_deq_bits_deq_bits_reg_io_d_lo_hi = cat(io_deq_bits_deq_bits_reg_io_d_lo_hi_hi, UInt<0>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node io_deq_bits_deq_bits_reg_io_d_lo = cat(io_deq_bits_deq_bits_reg_io_d_lo_hi, io_deq_bits_deq_bits_reg_io_d_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node io_deq_bits_deq_bits_reg_io_d_hi_lo = cat(io.async.mem[0].source, io.async.mem[0].sink) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node io_deq_bits_deq_bits_reg_io_d_hi_hi_hi = cat(io.async.mem[0].opcode, io.async.mem[0].param) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node io_deq_bits_deq_bits_reg_io_d_hi_hi = cat(io_deq_bits_deq_bits_reg_io_d_hi_hi_hi, io.async.mem[0].size) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node io_deq_bits_deq_bits_reg_io_d_hi = cat(io_deq_bits_deq_bits_reg_io_d_hi_hi, io_deq_bits_deq_bits_reg_io_d_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node _io_deq_bits_deq_bits_reg_io_d_T = cat(io_deq_bits_deq_bits_reg_io_d_hi, io_deq_bits_deq_bits_reg_io_d_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] connect io_deq_bits_deq_bits_reg.io.d, _io_deq_bits_deq_bits_reg_io_d_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:18] connect io_deq_bits_deq_bits_reg.io.en, valid @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 210:19] wire _io_deq_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] wire _io_deq_bits_WIRE_1 : UInt<43> @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE_1, io_deq_bits_deq_bits_reg.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T = bits(_io_deq_bits_WIRE_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.corrupt, _io_deq_bits_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_1 = bits(_io_deq_bits_WIRE_1, 32, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.data, _io_deq_bits_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_2 = bits(_io_deq_bits_WIRE_1, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.denied, _io_deq_bits_T_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_3 = bits(_io_deq_bits_WIRE_1, 34, 34) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.sink, _io_deq_bits_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_4 = bits(_io_deq_bits_WIRE_1, 35, 35) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.source, _io_deq_bits_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_5 = bits(_io_deq_bits_WIRE_1, 37, 36) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.size, _io_deq_bits_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_6 = bits(_io_deq_bits_WIRE_1, 39, 38) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.param, _io_deq_bits_T_6 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_7 = bits(_io_deq_bits_WIRE_1, 42, 40) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.opcode, _io_deq_bits_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect io.deq.bits, _io_deq_bits_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 163:15] node _valid_reg_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 165:35] regreset valid_reg : UInt<1>, clock, _valid_reg_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 165:56] connect valid_reg, valid @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 165:56] node _io_deq_valid_T = and(valid_reg, source_ready) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 166:29] connect io.deq.valid, _io_deq_valid_T @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 166:16] node _ridx_reg_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 168:34] regreset ridx_gray : UInt, clock, _ridx_reg_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 168:55] connect ridx_gray, ridx @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 168:55] connect io.async.ridx, ridx_gray @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 169:17] inst sink_valid_0 of AsyncValidSync_4 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 172:33] inst sink_valid_1 of AsyncValidSync_5 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 173:33] inst source_extend of AsyncValidSync_6 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 175:31] inst source_valid of AsyncValidSync_7 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 176:31] node _sink_valid_0_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 177:35] node _sink_valid_0_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 177:45] node _sink_valid_0_reset_T_2 = or(_sink_valid_0_reset_T, _sink_valid_0_reset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 177:42] node _sink_valid_0_reset_T_3 = asAsyncReset(_sink_valid_0_reset_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 177:66] connect sink_valid_0.reset, _sink_valid_0_reset_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 177:25] node _sink_valid_1_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 178:35] node _sink_valid_1_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 178:45] node _sink_valid_1_reset_T_2 = or(_sink_valid_1_reset_T, _sink_valid_1_reset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 178:42] node _sink_valid_1_reset_T_3 = asAsyncReset(_sink_valid_1_reset_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 178:66] connect sink_valid_1.reset, _sink_valid_1_reset_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 178:25] node _source_extend_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 179:35] node _source_extend_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 179:45] node _source_extend_reset_T_2 = or(_source_extend_reset_T, _source_extend_reset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 179:42] node _source_extend_reset_T_3 = asAsyncReset(_source_extend_reset_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 179:66] connect source_extend.reset, _source_extend_reset_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 179:25] node _source_valid_reset_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 180:34] connect source_valid.reset, _source_valid_reset_T @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 180:25] connect sink_valid_0.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 182:25] connect sink_valid_1.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 183:25] connect source_extend.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 184:25] connect source_valid.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 185:25] connect sink_valid_0.io.in, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 187:24] connect sink_valid_1.io.in, sink_valid_0.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 188:24] connect io.async.safe.ridx_valid, sink_valid_1.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 189:20] connect source_extend.io.in, io.async.safe.widx_valid @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 190:25] connect source_valid.io.in, source_extend.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 191:24] connect source_ready, source_valid.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 192:18] node _io_async_safe_sink_reset_n_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 193:32] node _io_async_safe_sink_reset_n_T_1 = eq(_io_async_safe_sink_reset_n_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 193:25] connect io.async.safe.sink_reset_n, _io_async_safe_sink_reset_n_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 193:22] module TLAsyncCrossingSource_a9d32s1k1z2u : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 23:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 23:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 23:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.e.safe.sink_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.e.safe.source_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.e.safe.widx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.e.safe.ridx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.e.widx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.e.ridx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.e.mem[0].sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.safe.sink_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.safe.source_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.safe.widx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.safe.ridx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.widx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.ridx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.mem[0].corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.mem[0].data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.mem[0].denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.mem[0].sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.mem[0].source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.mem[0].size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.mem[0].param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.mem[0].opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.c.safe.sink_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.c.safe.source_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.c.safe.widx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.c.safe.ridx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.c.widx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.c.ridx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.c.mem[0].corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.c.mem[0].data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.c.mem[0].address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.c.mem[0].source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.c.mem[0].size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.c.mem[0].param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.c.mem[0].opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.b.safe.sink_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.b.safe.source_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.b.safe.widx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.b.safe.ridx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.b.widx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.b.ridx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.b.mem[0].corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.b.mem[0].data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.b.mem[0].mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.b.mem[0].address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.b.mem[0].source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.b.mem[0].size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.b.mem[0].param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.b.mem[0].opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.safe.sink_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.safe.source_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.safe.widx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.safe.ridx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.widx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.ridx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.mem[0].corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.mem[0].data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.mem[0].mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.mem[0].address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.mem[0].source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.mem[0].size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.mem[0].param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.mem[0].opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] inst nodeOut_a_source of AsyncQueueSource_TLBundleA_a9d32s1k1z2u @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 220:24] connect nodeOut_a_source.clock, clock connect nodeOut_a_source.reset, reset connect nodeOut_a_source.io.enq, nodeIn.a @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 221:19] connect nodeOut_a_source.io.async.safe.sink_reset_n, nodeOut.a.safe.sink_reset_n @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 30:13] connect nodeOut.a.safe.source_reset_n, nodeOut_a_source.io.async.safe.source_reset_n @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 30:13] connect nodeOut.a.safe.widx_valid, nodeOut_a_source.io.async.safe.widx_valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 30:13] connect nodeOut_a_source.io.async.safe.ridx_valid, nodeOut.a.safe.ridx_valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 30:13] connect nodeOut.a.widx, nodeOut_a_source.io.async.widx @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 30:13] connect nodeOut_a_source.io.async.ridx, nodeOut.a.ridx @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 30:13] connect nodeOut.a.mem, nodeOut_a_source.io.async.mem @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 30:13] inst nodeIn_d_sink of AsyncQueueSink_TLBundleD_a9d32s1k1z2u @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 211:22] connect nodeIn_d_sink.clock, clock connect nodeIn_d_sink.reset, reset connect nodeIn_d_sink.io.async, nodeOut.d @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 212:19] connect nodeIn.d.bits, nodeIn_d_sink.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 31:12] connect nodeIn.d.valid, nodeIn_d_sink.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 31:12] connect nodeIn_d_sink.io.deq.ready, nodeIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 31:12] node _T = and(nodeIn.a.valid, nodeIn.a.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 32:21] node _T_1 = eq(nodeIn.a.ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 32:21] node _T_2 = and(nodeIn.a.valid, _T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 32:21] node _T_3 = eq(nodeIn.a.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 32:21] node _T_4 = and(_T_3, nodeIn.a.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 32:21] node _T_5 = eq(nodeIn.a.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 32:21] node _T_6 = eq(nodeIn.a.ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 32:21] node _T_7 = and(_T_5, _T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 32:21] node _T_8 = and(nodeIn.d.valid, nodeIn.d.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 33:21] node _T_9 = eq(nodeIn.d.ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 33:21] node _T_10 = and(nodeIn.d.valid, _T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 33:21] node _T_11 = eq(nodeIn.d.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 33:21] node _T_12 = and(_T_11, nodeIn.d.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 33:21] node _T_13 = eq(nodeIn.d.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 33:21] node _T_14 = eq(nodeIn.d.ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 33:21] node _T_15 = and(_T_13, _T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 33:21] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 43:20] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 44:20] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 45:20] connect nodeOut.b.ridx, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 46:20] connect nodeOut.c.widx, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 47:20] connect nodeOut.e.widx, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 48:20] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_10 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_10 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_10 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_11 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_11 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_12 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_12 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_8 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_source_valid_0.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_13 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_13 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_13 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_9 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_13 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_source_valid_1.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_14 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_14 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_14 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_10 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_14 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_sink_extend.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_15 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_15 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_15 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_11 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_15 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_sink_valid.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncQueueSource_DebugInternalBundle : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 70:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 70:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 70:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[1], hrmask : UInt<1>[1]}}, async : { mem : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[1], hrmask : UInt<1>[1]}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 73:14] wire sink_ready : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 81:28] connect sink_ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 81:28] reg mem : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[1], hrmask : UInt<1>[1]}[1], clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 82:16] node _widx_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 83:30] node _widx_T_1 = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _widx_T_2 = eq(sink_ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 83:77] wire widx_incremented : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 51:27] regreset widx_widx_bin : UInt, clock, _widx_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 52:25] connect widx_widx_bin, widx_incremented @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 52:25] node _widx_incremented_T = add(widx_widx_bin, _widx_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:43] node _widx_incremented_T_1 = tail(_widx_incremented_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:43] node _widx_incremented_T_2 = mux(_widx_T_2, UInt<1>(0h0), _widx_incremented_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:23] connect widx_incremented, _widx_incremented_T_2 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:17] node _widx_T_3 = shr(widx_incremented, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 54:32] node widx = xor(widx_incremented, _widx_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 54:17] inst ridx_ridx_gray of AsyncResetSynchronizerShiftReg_w1_d3_i0_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect ridx_ridx_gray.clock, clock connect ridx_ridx_gray.reset, reset connect ridx_ridx_gray.io.d, io.async.ridx @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire ridx : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect ridx, ridx_ridx_gray.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] node _ready_T = xor(ridx, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 85:44] node _ready_T_1 = neq(widx, _ready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 85:34] node ready = and(sink_ready, _ready_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 85:26] node _T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 88:22] connect mem[0], io.enq.bits @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 88:35] node _ready_reg_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 90:35] regreset ready_reg : UInt<1>, clock, _ready_reg_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 90:56] connect ready_reg, ready @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 90:56] node _io_enq_ready_T = and(ready_reg, sink_ready) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 91:29] connect io.enq.ready, _io_enq_ready_T @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 91:16] node _widx_reg_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 93:34] regreset widx_gray : UInt, clock, _widx_reg_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 93:55] connect widx_gray, widx @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 93:55] connect io.async.widx, widx_gray @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 94:17] connect io.async.mem, mem @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 98:31] inst source_valid_0 of AsyncValidSync_8 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 102:32] inst source_valid_1 of AsyncValidSync_9 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 103:32] inst sink_extend of AsyncValidSync_10 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 105:30] inst sink_valid of AsyncValidSync_11 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 106:30] node _source_valid_0_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 107:36] node _source_valid_0_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 107:46] node _source_valid_0_reset_T_2 = or(_source_valid_0_reset_T, _source_valid_0_reset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 107:43] node _source_valid_0_reset_T_3 = asAsyncReset(_source_valid_0_reset_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 107:65] connect source_valid_0.reset, _source_valid_0_reset_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 107:26] node _source_valid_1_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 108:36] node _source_valid_1_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 108:46] node _source_valid_1_reset_T_2 = or(_source_valid_1_reset_T, _source_valid_1_reset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 108:43] node _source_valid_1_reset_T_3 = asAsyncReset(_source_valid_1_reset_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 108:65] connect source_valid_1.reset, _source_valid_1_reset_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 108:26] node _sink_extend_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 109:36] node _sink_extend_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 109:46] node _sink_extend_reset_T_2 = or(_sink_extend_reset_T, _sink_extend_reset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 109:43] node _sink_extend_reset_T_3 = asAsyncReset(_sink_extend_reset_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 109:65] connect sink_extend.reset, _sink_extend_reset_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 109:26] node _sink_valid_reset_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 110:35] connect sink_valid.reset, _sink_valid_reset_T @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 110:26] connect source_valid_0.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 112:26] connect source_valid_1.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 113:26] connect sink_extend.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 114:26] connect sink_valid.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 115:26] connect source_valid_0.io.in, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 117:26] connect source_valid_1.io.in, source_valid_0.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 118:26] connect io.async.safe.widx_valid, source_valid_1.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 119:20] connect sink_extend.io.in, io.async.safe.ridx_valid @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 120:23] connect sink_valid.io.in, sink_extend.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 121:22] connect sink_ready, sink_valid.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 122:16] node _io_async_safe_source_reset_n_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 123:34] node _io_async_safe_source_reset_n_T_1 = eq(_io_async_safe_source_reset_n_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 123:27] connect io.async.safe.source_reset_n, _io_async_safe_source_reset_n_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 123:24] module TLDebugModuleOuterAsync : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 709:9] output auto : { asource_out : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}, int_out : { sync : UInt<1>[1]}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output io : { flip dmi_clock : Clock, flip dmi_reset : Reset, flip dmi : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<32>, op : UInt<2>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<32>, resp : UInt<2>}}}, ctrl : { flip debugUnavail : UInt<1>[1], ndreset : UInt<1>, dmactive : UInt<1>, flip dmactiveAck : UInt<1>}, innerCtrl : { mem : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[1], hrmask : UInt<1>[1]}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip hgDebugInt : UInt<1>[1]} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 713:16] input rf_reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 732:22] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] inst dmiXbar of TLXbar_dmixbar_i1_o2_a9d32s1k1z2u @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 675:28] connect dmiXbar.clock, childClock connect dmiXbar.reset, childReset inst dmi2tl of DMIToTL @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 678:28] connect dmi2tl.clock, childClock connect dmi2tl.reset, childReset inst dmOuter of TLDebugModuleOuter @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 700:27] connect dmOuter.clock, childClock connect dmOuter.reset, childReset inst intsource of IntSyncCrossingSource_n1x1_Registered @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Crossing.scala 29:31] inst dmiBypass of TLBusBypass @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 704:29] connect dmiBypass.clock, childClock connect dmiBypass.reset, childReset inst asource of TLAsyncCrossingSource_a9d32s1k1z2u @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 94:29] connect asource.clock, childClock connect asource.reset, childReset wire intnodeOut : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate intnodeOut.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire intnodeIn : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate intnodeIn.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect intnodeOut, intnodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] connect dmiBypass.auto.node_in_in, dmiXbar.auto.anon_out_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect dmOuter.auto.dmi_in, dmiXbar.auto.anon_out_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect dmiXbar.auto.anon_in, dmi2tl.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect intsource.auto.in[0], dmOuter.auto.int_out[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect intnodeIn, intsource.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect asource.auto.in, dmiBypass.auto.node_out_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect auto.int_out, intnodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect asource.auto.out.e.safe.sink_reset_n, auto.asource_out.e.safe.sink_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.asource_out.e.safe.source_reset_n, asource.auto.out.e.safe.source_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.asource_out.e.safe.widx_valid, asource.auto.out.e.safe.widx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect asource.auto.out.e.safe.ridx_valid, auto.asource_out.e.safe.ridx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.asource_out.e.widx, asource.auto.out.e.widx @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect asource.auto.out.e.ridx, auto.asource_out.e.ridx @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.asource_out.e.mem, asource.auto.out.e.mem @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect asource.auto.out.d, auto.asource_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect asource.auto.out.c.safe.sink_reset_n, auto.asource_out.c.safe.sink_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.asource_out.c.safe.source_reset_n, asource.auto.out.c.safe.source_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.asource_out.c.safe.widx_valid, asource.auto.out.c.safe.widx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect asource.auto.out.c.safe.ridx_valid, auto.asource_out.c.safe.ridx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.asource_out.c.widx, asource.auto.out.c.widx @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect asource.auto.out.c.ridx, auto.asource_out.c.ridx @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.asource_out.c.mem, asource.auto.out.c.mem @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect asource.auto.out.b, auto.asource_out.b @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect asource.auto.out.a.safe.sink_reset_n, auto.asource_out.a.safe.sink_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.asource_out.a.safe.source_reset_n, asource.auto.out.a.safe.source_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.asource_out.a.safe.widx_valid, asource.auto.out.a.safe.widx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect asource.auto.out.a.safe.ridx_valid, auto.asource_out.a.safe.ridx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.asource_out.a.widx, asource.auto.out.a.widx @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect asource.auto.out.a.ridx, auto.asource_out.a.ridx @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.asource_out.a.mem, asource.auto.out.a.mem @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect childClock, io.dmi_clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 734:16] connect childReset, io.dmi_reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 735:16] connect dmi2tl.io.dmi, io.dmi @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 739:43] inst dmactiveAck_dmactiveAckSync of AsyncResetSynchronizerShiftReg_w1_d3_i0_10 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect dmactiveAck_dmactiveAckSync.clock, childClock connect dmactiveAck_dmactiveAckSync.reset, childReset connect dmactiveAck_dmactiveAckSync.io.d, io.ctrl.dmactiveAck @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire dmactiveAck : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect dmactiveAck, dmactiveAck_dmactiveAckSync.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] node _dmiBypass_io_bypass_T = not(io.ctrl.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 742:37] node _dmiBypass_io_bypass_T_1 = not(dmactiveAck) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 742:57] node _dmiBypass_io_bypass_T_2 = or(_dmiBypass_io_bypass_T, _dmiBypass_io_bypass_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 742:55] connect dmiBypass.io.bypass, _dmiBypass_io_bypass_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 742:34] connect dmOuter.io.ctrl.dmactiveAck, io.ctrl.dmactiveAck @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 744:15] connect io.ctrl.dmactive, dmOuter.io.ctrl.dmactive @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 744:15] connect io.ctrl.ndreset, dmOuter.io.ctrl.ndreset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 744:15] connect dmOuter.io.ctrl.debugUnavail[0], io.ctrl.debugUnavail[0] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 744:15] connect dmOuter.io.ctrl.dmactiveAck, dmactiveAck @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 745:42] inst io_innerCtrl_source of AsyncQueueSource_DebugInternalBundle @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 220:24] connect io_innerCtrl_source.clock, childClock connect io_innerCtrl_source.reset, childReset connect io_innerCtrl_source.io.enq, dmOuter.io.innerCtrl @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 221:19] connect io_innerCtrl_source.io.async.safe.sink_reset_n, io.innerCtrl.safe.sink_reset_n @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 746:20] connect io.innerCtrl.safe.source_reset_n, io_innerCtrl_source.io.async.safe.source_reset_n @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 746:20] connect io.innerCtrl.safe.widx_valid, io_innerCtrl_source.io.async.safe.widx_valid @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 746:20] connect io_innerCtrl_source.io.async.safe.ridx_valid, io.innerCtrl.safe.ridx_valid @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 746:20] connect io.innerCtrl.widx, io_innerCtrl_source.io.async.widx @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 746:20] connect io_innerCtrl_source.io.async.ridx, io.innerCtrl.ridx @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 746:20] connect io.innerCtrl.mem, io_innerCtrl_source.io.async.mem @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 746:20] connect dmOuter.io.hgDebugInt[0], io.hgDebugInt[0] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 747:36] module Queue2_TLBundleD_a32d8s1k1z4u : @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input clock : Clock @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input reset : Reset @[src/main/scala/chisel3/util/Decoupled.scala 243:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}, count : UInt<2>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>} [2] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] regreset enq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset deq_ptr_value : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] infer mport MPORT = ram[enq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 270:24] node wrap = eq(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T = add(enq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_1 = tail(_value_T, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect enq_ptr_value, _value_T_1 @[src/main/scala/chisel3/util/Counter.scala 77:15] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] node wrap_1 = eq(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _value_T_3 = tail(_value_T_2, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect deq_ptr_value, _value_T_3 @[src/main/scala/chisel3/util/Counter.scala 77:15] node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] infer mport io_deq_bits_MPORT = ram[deq_ptr_value], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<2>(0h2), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module SBToTL : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 273:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 273:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 273:9] output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output io : { flip rdEn : UInt<1>, flip wrEn : UInt<1>, flip addrIn : UInt<128>, flip dataIn : UInt<128>, flip sizeIn : UInt<3>, rdLegal : UInt<1>, wrLegal : UInt<1>, rdDone : UInt<1>, wrDone : UInt<1>, respError : UInt<1>, dataOut : UInt<8>, rdLoad : UInt<1>[8], sbStateOut : UInt<3>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 274:16] input rf_reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 289:28] wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] regreset sbState : UInt, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 295:26] inst d_q of Queue2_TLBundleD_a32d8s1k1z4u @[src/main/scala/chisel3/util/Decoupled.scala 362:21] connect d_q.clock, clock connect d_q.reset, reset connect d_q.io.enq.valid, nodeOut.d.valid @[src/main/scala/chisel3/util/Decoupled.scala 364:22] connect d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect d_q.io.enq.bits.data, nodeOut.d.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect d_q.io.enq.bits.denied, nodeOut.d.bits.denied @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect d_q.io.enq.bits.sink, nodeOut.d.bits.sink @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect d_q.io.enq.bits.source, nodeOut.d.bits.source @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect d_q.io.enq.bits.size, nodeOut.d.bits.size @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect d_q.io.enq.bits.param, nodeOut.d.bits.param @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeOut.d.ready, d_q.io.enq.ready @[src/main/scala/chisel3/util/Decoupled.scala 366:17] node _q_io_deq_ready_T = eq(sbState, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 299:25] node _q_io_deq_ready_T_1 = eq(sbState, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 299:62] node _q_io_deq_ready_T_2 = or(_q_io_deq_ready_T, _q_io_deq_ready_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 299:50] connect d_q.io.deq.ready, _q_io_deq_ready_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 299:13] wire muxedData : UInt<8> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 301:29] connect muxedData, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 301:29] regreset counter : UInt<4>, clock, reset, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 307:26] wire vecData : UInt<8>[8] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 308:25] node _vecData_0_T = bits(io.dataIn, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 309:63] connect vecData[0], _vecData_0_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 309:51] node _vecData_1_T = bits(io.dataIn, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 309:63] connect vecData[1], _vecData_1_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 309:51] node _vecData_2_T = bits(io.dataIn, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 309:63] connect vecData[2], _vecData_2_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 309:51] node _vecData_3_T = bits(io.dataIn, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 309:63] connect vecData[3], _vecData_3_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 309:51] node _vecData_4_T = bits(io.dataIn, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 309:63] connect vecData[4], _vecData_4_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 309:51] node _vecData_5_T = bits(io.dataIn, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 309:63] connect vecData[5], _vecData_5_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 309:51] node _vecData_6_T = bits(io.dataIn, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 309:63] connect vecData[6], _vecData_6_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 309:51] node _vecData_7_T = bits(io.dataIn, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 309:63] connect vecData[7], _vecData_7_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 309:51] node _muxedData_T = bits(counter, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 310:33] connect muxedData, vecData[_muxedData_T] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 310:15] node _rdLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _rdLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _rdLegal_addr_T_2 = and(_rdLegal_addr_T, _rdLegal_addr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _rdLegal_addr_T_3 = or(UInt<1>(0h1), _rdLegal_addr_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _rdLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _rdLegal_addr_T_5 = cvt(_rdLegal_addr_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _rdLegal_addr_T_6 = and(_rdLegal_addr_T_5, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_7 = asSInt(_rdLegal_addr_T_6) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_8 = eq(_rdLegal_addr_T_7, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _rdLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h3000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _rdLegal_addr_T_10 = cvt(_rdLegal_addr_T_9) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _rdLegal_addr_T_11 = and(_rdLegal_addr_T_10, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_12 = asSInt(_rdLegal_addr_T_11) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_13 = eq(_rdLegal_addr_T_12, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _rdLegal_addr_T_14 = xor(io.addrIn, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _rdLegal_addr_T_15 = cvt(_rdLegal_addr_T_14) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _rdLegal_addr_T_16 = and(_rdLegal_addr_T_15, asSInt(UInt<17>(0h10000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_17 = asSInt(_rdLegal_addr_T_16) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_18 = eq(_rdLegal_addr_T_17, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _rdLegal_addr_T_19 = xor(io.addrIn, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _rdLegal_addr_T_20 = cvt(_rdLegal_addr_T_19) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _rdLegal_addr_T_21 = and(_rdLegal_addr_T_20, asSInt(UInt<17>(0h10000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_22 = asSInt(_rdLegal_addr_T_21) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_23 = eq(_rdLegal_addr_T_22, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _rdLegal_addr_T_24 = xor(io.addrIn, UInt<28>(0hc000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _rdLegal_addr_T_25 = cvt(_rdLegal_addr_T_24) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _rdLegal_addr_T_26 = and(_rdLegal_addr_T_25, asSInt(UInt<27>(0h4000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_27 = asSInt(_rdLegal_addr_T_26) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_28 = eq(_rdLegal_addr_T_27, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _rdLegal_addr_T_29 = xor(io.addrIn, UInt<29>(0h10013000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _rdLegal_addr_T_30 = cvt(_rdLegal_addr_T_29) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _rdLegal_addr_T_31 = and(_rdLegal_addr_T_30, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_32 = asSInt(_rdLegal_addr_T_31) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_33 = eq(_rdLegal_addr_T_32, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _rdLegal_addr_T_34 = xor(io.addrIn, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _rdLegal_addr_T_35 = cvt(_rdLegal_addr_T_34) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _rdLegal_addr_T_36 = and(_rdLegal_addr_T_35, asSInt(UInt<14>(0h2000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_37 = asSInt(_rdLegal_addr_T_36) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_38 = eq(_rdLegal_addr_T_37, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _rdLegal_addr_T_39 = xor(io.addrIn, UInt<29>(0h10020000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _rdLegal_addr_T_40 = cvt(_rdLegal_addr_T_39) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _rdLegal_addr_T_41 = and(_rdLegal_addr_T_40, asSInt(UInt<16>(0h8000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_42 = asSInt(_rdLegal_addr_T_41) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_43 = eq(_rdLegal_addr_T_42, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _rdLegal_addr_T_44 = xor(io.addrIn, UInt<29>(0h10028000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _rdLegal_addr_T_45 = cvt(_rdLegal_addr_T_44) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _rdLegal_addr_T_46 = and(_rdLegal_addr_T_45, asSInt(UInt<14>(0h2000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_47 = asSInt(_rdLegal_addr_T_46) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_48 = eq(_rdLegal_addr_T_47, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _rdLegal_addr_T_49 = xor(io.addrIn, UInt<29>(0h1002a000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _rdLegal_addr_T_50 = cvt(_rdLegal_addr_T_49) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _rdLegal_addr_T_51 = and(_rdLegal_addr_T_50, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_52 = asSInt(_rdLegal_addr_T_51) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_53 = eq(_rdLegal_addr_T_52, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _rdLegal_addr_T_54 = xor(io.addrIn, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _rdLegal_addr_T_55 = cvt(_rdLegal_addr_T_54) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _rdLegal_addr_T_56 = and(_rdLegal_addr_T_55, asSInt(UInt<21>(0h100000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_57 = asSInt(_rdLegal_addr_T_56) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _rdLegal_addr_T_58 = eq(_rdLegal_addr_T_57, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _rdLegal_addr_T_59 = or(_rdLegal_addr_T_8, _rdLegal_addr_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _rdLegal_addr_T_60 = or(_rdLegal_addr_T_59, _rdLegal_addr_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _rdLegal_addr_T_61 = or(_rdLegal_addr_T_60, _rdLegal_addr_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _rdLegal_addr_T_62 = or(_rdLegal_addr_T_61, _rdLegal_addr_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _rdLegal_addr_T_63 = or(_rdLegal_addr_T_62, _rdLegal_addr_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _rdLegal_addr_T_64 = or(_rdLegal_addr_T_63, _rdLegal_addr_T_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _rdLegal_addr_T_65 = or(_rdLegal_addr_T_64, _rdLegal_addr_T_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _rdLegal_addr_T_66 = or(_rdLegal_addr_T_65, _rdLegal_addr_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _rdLegal_addr_T_67 = or(_rdLegal_addr_T_66, _rdLegal_addr_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _rdLegal_addr_T_68 = or(_rdLegal_addr_T_67, _rdLegal_addr_T_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _rdLegal_addr_T_69 = and(_rdLegal_addr_T_3, _rdLegal_addr_T_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node rdLegal_addr = or(UInt<1>(0h0), _rdLegal_addr_T_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node _wrLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _wrLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _wrLegal_addr_T_2 = and(_wrLegal_addr_T, _wrLegal_addr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _wrLegal_addr_T_3 = or(UInt<1>(0h1), _wrLegal_addr_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _wrLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _wrLegal_addr_T_5 = cvt(_wrLegal_addr_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _wrLegal_addr_T_6 = and(_wrLegal_addr_T_5, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_7 = asSInt(_wrLegal_addr_T_6) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_8 = eq(_wrLegal_addr_T_7, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _wrLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h3000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _wrLegal_addr_T_10 = cvt(_wrLegal_addr_T_9) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _wrLegal_addr_T_11 = and(_wrLegal_addr_T_10, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_12 = asSInt(_wrLegal_addr_T_11) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_13 = eq(_wrLegal_addr_T_12, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _wrLegal_addr_T_14 = xor(io.addrIn, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _wrLegal_addr_T_15 = cvt(_wrLegal_addr_T_14) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _wrLegal_addr_T_16 = and(_wrLegal_addr_T_15, asSInt(UInt<17>(0h10000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_17 = asSInt(_wrLegal_addr_T_16) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_18 = eq(_wrLegal_addr_T_17, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _wrLegal_addr_T_19 = xor(io.addrIn, UInt<28>(0hc000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _wrLegal_addr_T_20 = cvt(_wrLegal_addr_T_19) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _wrLegal_addr_T_21 = and(_wrLegal_addr_T_20, asSInt(UInt<27>(0h4000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_22 = asSInt(_wrLegal_addr_T_21) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_23 = eq(_wrLegal_addr_T_22, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _wrLegal_addr_T_24 = xor(io.addrIn, UInt<29>(0h10013000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _wrLegal_addr_T_25 = cvt(_wrLegal_addr_T_24) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _wrLegal_addr_T_26 = and(_wrLegal_addr_T_25, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_27 = asSInt(_wrLegal_addr_T_26) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_28 = eq(_wrLegal_addr_T_27, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _wrLegal_addr_T_29 = xor(io.addrIn, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _wrLegal_addr_T_30 = cvt(_wrLegal_addr_T_29) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _wrLegal_addr_T_31 = and(_wrLegal_addr_T_30, asSInt(UInt<14>(0h2000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_32 = asSInt(_wrLegal_addr_T_31) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_33 = eq(_wrLegal_addr_T_32, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _wrLegal_addr_T_34 = xor(io.addrIn, UInt<29>(0h10020000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _wrLegal_addr_T_35 = cvt(_wrLegal_addr_T_34) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _wrLegal_addr_T_36 = and(_wrLegal_addr_T_35, asSInt(UInt<16>(0h8000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_37 = asSInt(_wrLegal_addr_T_36) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_38 = eq(_wrLegal_addr_T_37, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _wrLegal_addr_T_39 = xor(io.addrIn, UInt<29>(0h10028000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _wrLegal_addr_T_40 = cvt(_wrLegal_addr_T_39) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _wrLegal_addr_T_41 = and(_wrLegal_addr_T_40, asSInt(UInt<14>(0h2000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_42 = asSInt(_wrLegal_addr_T_41) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_43 = eq(_wrLegal_addr_T_42, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _wrLegal_addr_T_44 = xor(io.addrIn, UInt<29>(0h1002a000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _wrLegal_addr_T_45 = cvt(_wrLegal_addr_T_44) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _wrLegal_addr_T_46 = and(_wrLegal_addr_T_45, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_47 = asSInt(_wrLegal_addr_T_46) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_48 = eq(_wrLegal_addr_T_47, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _wrLegal_addr_T_49 = xor(io.addrIn, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _wrLegal_addr_T_50 = cvt(_wrLegal_addr_T_49) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _wrLegal_addr_T_51 = and(_wrLegal_addr_T_50, asSInt(UInt<21>(0h100000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_52 = asSInt(_wrLegal_addr_T_51) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_53 = eq(_wrLegal_addr_T_52, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _wrLegal_addr_T_54 = or(_wrLegal_addr_T_8, _wrLegal_addr_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _wrLegal_addr_T_55 = or(_wrLegal_addr_T_54, _wrLegal_addr_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _wrLegal_addr_T_56 = or(_wrLegal_addr_T_55, _wrLegal_addr_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _wrLegal_addr_T_57 = or(_wrLegal_addr_T_56, _wrLegal_addr_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _wrLegal_addr_T_58 = or(_wrLegal_addr_T_57, _wrLegal_addr_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _wrLegal_addr_T_59 = or(_wrLegal_addr_T_58, _wrLegal_addr_T_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _wrLegal_addr_T_60 = or(_wrLegal_addr_T_59, _wrLegal_addr_T_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _wrLegal_addr_T_61 = or(_wrLegal_addr_T_60, _wrLegal_addr_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _wrLegal_addr_T_62 = or(_wrLegal_addr_T_61, _wrLegal_addr_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _wrLegal_addr_T_63 = and(_wrLegal_addr_T_3, _wrLegal_addr_T_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _wrLegal_addr_T_64 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _wrLegal_addr_T_65 = xor(io.addrIn, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _wrLegal_addr_T_66 = cvt(_wrLegal_addr_T_65) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _wrLegal_addr_T_67 = and(_wrLegal_addr_T_66, asSInt(UInt<17>(0h10000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_68 = asSInt(_wrLegal_addr_T_67) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _wrLegal_addr_T_69 = eq(_wrLegal_addr_T_68, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _wrLegal_addr_T_70 = and(_wrLegal_addr_T_64, _wrLegal_addr_T_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _wrLegal_addr_T_71 = or(UInt<1>(0h0), _wrLegal_addr_T_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node wrLegal_addr = or(_wrLegal_addr_T_71, _wrLegal_addr_T_70) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node _gbits_legal_T = leq(UInt<1>(0h0), io.sizeIn) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _gbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _gbits_legal_T_2 = and(_gbits_legal_T, _gbits_legal_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _gbits_legal_T_3 = or(UInt<1>(0h0), _gbits_legal_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _gbits_legal_T_4 = xor(io.addrIn, UInt<13>(0h1000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _gbits_legal_T_5 = cvt(_gbits_legal_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _gbits_legal_T_6 = and(_gbits_legal_T_5, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_7 = asSInt(_gbits_legal_T_6) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_8 = eq(_gbits_legal_T_7, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _gbits_legal_T_9 = and(_gbits_legal_T_3, _gbits_legal_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _gbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _gbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _gbits_legal_T_12 = and(_gbits_legal_T_10, _gbits_legal_T_11) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _gbits_legal_T_13 = or(UInt<1>(0h0), _gbits_legal_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _gbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _gbits_legal_T_15 = cvt(_gbits_legal_T_14) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _gbits_legal_T_16 = and(_gbits_legal_T_15, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_17 = asSInt(_gbits_legal_T_16) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_18 = eq(_gbits_legal_T_17, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _gbits_legal_T_19 = xor(io.addrIn, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _gbits_legal_T_20 = cvt(_gbits_legal_T_19) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _gbits_legal_T_21 = and(_gbits_legal_T_20, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_22 = asSInt(_gbits_legal_T_21) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_23 = eq(_gbits_legal_T_22, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _gbits_legal_T_24 = xor(io.addrIn, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _gbits_legal_T_25 = cvt(_gbits_legal_T_24) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _gbits_legal_T_26 = and(_gbits_legal_T_25, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_27 = asSInt(_gbits_legal_T_26) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_28 = eq(_gbits_legal_T_27, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _gbits_legal_T_29 = xor(io.addrIn, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _gbits_legal_T_30 = cvt(_gbits_legal_T_29) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _gbits_legal_T_31 = and(_gbits_legal_T_30, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_32 = asSInt(_gbits_legal_T_31) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_33 = eq(_gbits_legal_T_32, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _gbits_legal_T_34 = xor(io.addrIn, UInt<29>(0h10000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _gbits_legal_T_35 = cvt(_gbits_legal_T_34) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _gbits_legal_T_36 = and(_gbits_legal_T_35, asSInt(UInt<33>(0hfa018000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_37 = asSInt(_gbits_legal_T_36) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_38 = eq(_gbits_legal_T_37, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _gbits_legal_T_39 = xor(io.addrIn, UInt<29>(0h10008000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _gbits_legal_T_40 = cvt(_gbits_legal_T_39) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _gbits_legal_T_41 = and(_gbits_legal_T_40, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_42 = asSInt(_gbits_legal_T_41) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_43 = eq(_gbits_legal_T_42, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _gbits_legal_T_44 = xor(io.addrIn, UInt<29>(0h10011000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _gbits_legal_T_45 = cvt(_gbits_legal_T_44) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _gbits_legal_T_46 = and(_gbits_legal_T_45, asSInt(UInt<33>(0hfa01d000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_47 = asSInt(_gbits_legal_T_46) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_48 = eq(_gbits_legal_T_47, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _gbits_legal_T_49 = xor(io.addrIn, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _gbits_legal_T_50 = cvt(_gbits_legal_T_49) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _gbits_legal_T_51 = and(_gbits_legal_T_50, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_52 = asSInt(_gbits_legal_T_51) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_53 = eq(_gbits_legal_T_52, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _gbits_legal_T_54 = xor(io.addrIn, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _gbits_legal_T_55 = cvt(_gbits_legal_T_54) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _gbits_legal_T_56 = and(_gbits_legal_T_55, asSInt(UInt<33>(0hfa000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_57 = asSInt(_gbits_legal_T_56) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _gbits_legal_T_58 = eq(_gbits_legal_T_57, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _gbits_legal_T_59 = or(_gbits_legal_T_18, _gbits_legal_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _gbits_legal_T_60 = or(_gbits_legal_T_59, _gbits_legal_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _gbits_legal_T_61 = or(_gbits_legal_T_60, _gbits_legal_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _gbits_legal_T_62 = or(_gbits_legal_T_61, _gbits_legal_T_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _gbits_legal_T_63 = or(_gbits_legal_T_62, _gbits_legal_T_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _gbits_legal_T_64 = or(_gbits_legal_T_63, _gbits_legal_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _gbits_legal_T_65 = or(_gbits_legal_T_64, _gbits_legal_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _gbits_legal_T_66 = or(_gbits_legal_T_65, _gbits_legal_T_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _gbits_legal_T_67 = and(_gbits_legal_T_13, _gbits_legal_T_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _gbits_legal_T_68 = or(UInt<1>(0h0), _gbits_legal_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node gbits_legal = or(_gbits_legal_T_68, _gbits_legal_T_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire gbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 460:17] connect gbits.opcode, UInt<3>(0h4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 461:15] connect gbits.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 462:15] connect gbits.size, io.sizeIn @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 463:15] connect gbits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 464:15] connect gbits.address, io.addrIn @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 465:15] invalidate gbits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] invalidate gbits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] invalidate gbits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] invalidate gbits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] invalidate gbits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] invalidate gbits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] invalidate gbits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 466:15] node _gbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node gbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] connect gbits.mask, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 468:15] invalidate gbits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 469:15] connect gbits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 470:15] node _pfbits_legal_T = leq(UInt<1>(0h0), io.sizeIn) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _pfbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _pfbits_legal_T_2 = and(_pfbits_legal_T, _pfbits_legal_T_1) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _pfbits_legal_T_3 = or(UInt<1>(0h0), _pfbits_legal_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _pfbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h2000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pfbits_legal_T_5 = cvt(_pfbits_legal_T_4) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pfbits_legal_T_6 = and(_pfbits_legal_T_5, asSInt(UInt<33>(0hfa01e000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_7 = asSInt(_pfbits_legal_T_6) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_8 = eq(_pfbits_legal_T_7, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pfbits_legal_T_9 = and(_pfbits_legal_T_3, _pfbits_legal_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _pfbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:28] node _pfbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:38] node _pfbits_legal_T_12 = and(_pfbits_legal_T_10, _pfbits_legal_T_11) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 94:33] node _pfbits_legal_T_13 = or(UInt<1>(0h0), _pfbits_legal_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _pfbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pfbits_legal_T_15 = cvt(_pfbits_legal_T_14) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pfbits_legal_T_16 = and(_pfbits_legal_T_15, asSInt(UInt<33>(0hfa01e000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_17 = asSInt(_pfbits_legal_T_16) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_18 = eq(_pfbits_legal_T_17, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pfbits_legal_T_19 = xor(io.addrIn, UInt<26>(0h2000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pfbits_legal_T_20 = cvt(_pfbits_legal_T_19) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pfbits_legal_T_21 = and(_pfbits_legal_T_20, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_22 = asSInt(_pfbits_legal_T_21) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_23 = eq(_pfbits_legal_T_22, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pfbits_legal_T_24 = xor(io.addrIn, UInt<28>(0h8000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pfbits_legal_T_25 = cvt(_pfbits_legal_T_24) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pfbits_legal_T_26 = and(_pfbits_legal_T_25, asSInt(UInt<33>(0hf8000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_27 = asSInt(_pfbits_legal_T_26) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_28 = eq(_pfbits_legal_T_27, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pfbits_legal_T_29 = xor(io.addrIn, UInt<29>(0h10000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pfbits_legal_T_30 = cvt(_pfbits_legal_T_29) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pfbits_legal_T_31 = and(_pfbits_legal_T_30, asSInt(UInt<33>(0hfa018000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_32 = asSInt(_pfbits_legal_T_31) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_33 = eq(_pfbits_legal_T_32, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pfbits_legal_T_34 = xor(io.addrIn, UInt<29>(0h10008000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pfbits_legal_T_35 = cvt(_pfbits_legal_T_34) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pfbits_legal_T_36 = and(_pfbits_legal_T_35, asSInt(UInt<33>(0hfa01c000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_37 = asSInt(_pfbits_legal_T_36) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_38 = eq(_pfbits_legal_T_37, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pfbits_legal_T_39 = xor(io.addrIn, UInt<29>(0h10012000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pfbits_legal_T_40 = cvt(_pfbits_legal_T_39) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pfbits_legal_T_41 = and(_pfbits_legal_T_40, asSInt(UInt<33>(0hfa01e000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_42 = asSInt(_pfbits_legal_T_41) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_43 = eq(_pfbits_legal_T_42, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pfbits_legal_T_44 = xor(io.addrIn, UInt<29>(0h10014000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pfbits_legal_T_45 = cvt(_pfbits_legal_T_44) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pfbits_legal_T_46 = and(_pfbits_legal_T_45, asSInt(UInt<33>(0hfa01e000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_47 = asSInt(_pfbits_legal_T_46) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_48 = eq(_pfbits_legal_T_47, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pfbits_legal_T_49 = xor(io.addrIn, UInt<32>(0h80000000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pfbits_legal_T_50 = cvt(_pfbits_legal_T_49) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pfbits_legal_T_51 = and(_pfbits_legal_T_50, asSInt(UInt<33>(0hfa000000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_52 = asSInt(_pfbits_legal_T_51) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_53 = eq(_pfbits_legal_T_52, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pfbits_legal_T_54 = or(_pfbits_legal_T_18, _pfbits_legal_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _pfbits_legal_T_55 = or(_pfbits_legal_T_54, _pfbits_legal_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _pfbits_legal_T_56 = or(_pfbits_legal_T_55, _pfbits_legal_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _pfbits_legal_T_57 = or(_pfbits_legal_T_56, _pfbits_legal_T_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _pfbits_legal_T_58 = or(_pfbits_legal_T_57, _pfbits_legal_T_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _pfbits_legal_T_59 = or(_pfbits_legal_T_58, _pfbits_legal_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _pfbits_legal_T_60 = or(_pfbits_legal_T_59, _pfbits_legal_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 685:42] node _pfbits_legal_T_61 = and(_pfbits_legal_T_13, _pfbits_legal_T_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _pfbits_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:29] node _pfbits_legal_T_63 = xor(io.addrIn, UInt<17>(0h10000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _pfbits_legal_T_64 = cvt(_pfbits_legal_T_63) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _pfbits_legal_T_65 = and(_pfbits_legal_T_64, asSInt(UInt<33>(0hfa010000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_66 = asSInt(_pfbits_legal_T_65) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _pfbits_legal_T_67 = eq(_pfbits_legal_T_66, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _pfbits_legal_T_68 = and(_pfbits_legal_T_62, _pfbits_legal_T_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 684:54] node _pfbits_legal_T_69 = or(UInt<1>(0h0), _pfbits_legal_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node _pfbits_legal_T_70 = or(_pfbits_legal_T_69, _pfbits_legal_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] node pfbits_legal = or(_pfbits_legal_T_70, _pfbits_legal_T_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Parameters.scala 686:26] wire pfbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 480:17] connect pfbits.opcode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 481:15] connect pfbits.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 482:15] connect pfbits.size, io.sizeIn @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 483:15] connect pfbits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 484:15] connect pfbits.address, io.addrIn @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 485:15] invalidate pfbits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate pfbits.user.amba_prot.secure @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate pfbits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate pfbits.user.amba_prot.writealloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate pfbits.user.amba_prot.readalloc @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate pfbits.user.amba_prot.modifiable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] invalidate pfbits.user.amba_prot.bufferable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 486:15] node _pfbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:34] node pfbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/Misc.scala 202:81] connect pfbits.mask, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 488:15] connect pfbits.data, muxedData @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 489:15] connect pfbits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 490:15] connect io.rdLegal, rdLegal_addr @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 318:16] connect io.wrLegal, wrLegal_addr @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 319:16] connect io.sbStateOut, sbState @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 321:19] node _T = eq(sbState, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 322:18] when _T : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 322:42] connect nodeOut.a.bits, gbits @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 322:54] else : connect nodeOut.a.bits, pfbits @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 323:54] connect nodeOut.a.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 326:20] connect nodeOut.a.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 327:20] connect nodeOut.a.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 328:20] connect nodeOut.a.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 329:20] connect nodeOut.a.bits.user.amba_prot.privileged, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 330:20] connect nodeOut.a.bits.user.amba_prot.secure, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 331:20] connect nodeOut.a.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 332:20] node respError = or(d_q.io.deq.bits.denied, d_q.io.deq.bits.corrupt) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 335:35] connect io.respError, respError @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 336:18] node _wrTxValid_T = eq(sbState, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 338:29] node _wrTxValid_T_1 = and(_wrTxValid_T, nodeOut.a.valid) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 338:53] node wrTxValid = and(_wrTxValid_T_1, nodeOut.a.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 338:69] node _rdTxValid_T = eq(sbState, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 339:29] node _rdTxValid_T_1 = and(_rdTxValid_T, d_q.io.deq.valid) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 339:53] node rdTxValid = and(_rdTxValid_T_1, d_q.io.deq.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 339:70] node _txLast_T = dshl(UInt<1>(0h1), io.sizeIn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 340:39] node _txLast_T_1 = sub(_txLast_T, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 340:53] node _txLast_T_2 = tail(_txLast_T_1, 1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 340:53] node txLast = eq(counter, _txLast_T_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 340:29] node _counter_T = or(wrTxValid, rdTxValid) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 341:31] node _counter_T_1 = and(_counter_T, txLast) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 341:45] node _counter_T_2 = or(wrTxValid, rdTxValid) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 342:31] node _counter_T_3 = add(counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 342:63] node _counter_T_4 = tail(_counter_T_3, 1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 342:63] node _counter_T_5 = mux(_counter_T_2, _counter_T_4, counter) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 342:19] node _counter_T_6 = mux(_counter_T_1, UInt<1>(0h0), _counter_T_5) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 341:19] connect counter, _counter_T_6 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 341:13] node _io_rdLoad_0_T = eq(counter, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:45] node _io_rdLoad_0_T_1 = and(rdTxValid, _io_rdLoad_0_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:33] connect io.rdLoad[0], _io_rdLoad_0_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:20] node _io_rdLoad_1_T = eq(counter, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:45] node _io_rdLoad_1_T_1 = and(rdTxValid, _io_rdLoad_1_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:33] connect io.rdLoad[1], _io_rdLoad_1_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:20] node _io_rdLoad_2_T = eq(counter, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:45] node _io_rdLoad_2_T_1 = and(rdTxValid, _io_rdLoad_2_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:33] connect io.rdLoad[2], _io_rdLoad_2_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:20] node _io_rdLoad_3_T = eq(counter, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:45] node _io_rdLoad_3_T_1 = and(rdTxValid, _io_rdLoad_3_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:33] connect io.rdLoad[3], _io_rdLoad_3_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:20] node _io_rdLoad_4_T = eq(counter, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:45] node _io_rdLoad_4_T_1 = and(rdTxValid, _io_rdLoad_4_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:33] connect io.rdLoad[4], _io_rdLoad_4_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:20] node _io_rdLoad_5_T = eq(counter, UInt<3>(0h5)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:45] node _io_rdLoad_5_T_1 = and(rdTxValid, _io_rdLoad_5_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:33] connect io.rdLoad[5], _io_rdLoad_5_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:20] node _io_rdLoad_6_T = eq(counter, UInt<3>(0h6)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:45] node _io_rdLoad_6_T_1 = and(rdTxValid, _io_rdLoad_6_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:33] connect io.rdLoad[6], _io_rdLoad_6_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:20] node _io_rdLoad_7_T = eq(counter, UInt<3>(0h7)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:45] node _io_rdLoad_7_T_1 = and(rdTxValid, _io_rdLoad_7_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:33] connect io.rdLoad[7], _io_rdLoad_7_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 345:20] node _T_1 = eq(sbState, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 349:19] when _T_1 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 349:33] node _sbState_T = and(io.rdEn, io.rdLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 350:30] node _sbState_T_1 = and(io.wrEn, io.wrLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 351:30] node _sbState_T_2 = mux(_sbState_T_1, UInt<2>(0h2), sbState) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 351:21] node _sbState_T_3 = mux(_sbState_T, UInt<1>(0h1), _sbState_T_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 350:21] connect sbState, _sbState_T_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 350:15] else : node _T_2 = eq(sbState, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 352:25] when _T_2 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 352:48] node _sbState_T_4 = and(nodeOut.a.valid, nodeOut.a.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 353:35] node _sbState_T_5 = mux(_sbState_T_4, UInt<2>(0h3), sbState) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 353:21] connect sbState, _sbState_T_5 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 353:15] else : node _T_3 = eq(sbState, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 354:25] when _T_3 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 354:49] node _sbState_T_6 = and(wrTxValid, txLast) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 355:32] node _sbState_T_7 = mux(_sbState_T_6, UInt<3>(0h4), sbState) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 355:21] connect sbState, _sbState_T_7 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 355:15] else : node _T_4 = eq(sbState, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 356:25] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 356:49] node _sbState_T_8 = and(rdTxValid, txLast) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 357:32] node _sbState_T_9 = mux(_sbState_T_8, UInt<1>(0h0), sbState) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 357:21] connect sbState, _sbState_T_9 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 357:15] else : node _T_5 = eq(sbState, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 358:25] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 358:50] node _sbState_T_10 = and(d_q.io.deq.valid, d_q.io.deq.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 359:36] node _sbState_T_11 = mux(_sbState_T_10, UInt<1>(0h0), sbState) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 359:21] connect sbState, _sbState_T_11 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 359:15] node _io_rdDone_T = and(rdTxValid, txLast) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 362:29] connect io.rdDone, _io_rdDone_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 362:16] node _io_wrDone_T = eq(sbState, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 363:28] node _io_wrDone_T_1 = and(_io_wrDone_T, d_q.io.deq.valid) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 363:54] node _io_wrDone_T_2 = and(_io_wrDone_T_1, d_q.io.deq.ready) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 363:71] connect io.wrDone, _io_wrDone_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 363:16] connect io.dataOut, d_q.io.deq.bits.data @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 364:16] node _nodeOut_a_valid_T = eq(sbState, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 366:28] node _nodeOut_a_valid_T_1 = eq(sbState, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 366:64] node _nodeOut_a_valid_T_2 = or(_nodeOut_a_valid_T, _nodeOut_a_valid_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 366:52] connect nodeOut.a.valid, _nodeOut_a_valid_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 366:16] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 369:16] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 370:16] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 371:16] node _T_6 = eq(sbState, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 373:21] node _T_7 = eq(sbState, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 374:21] node _T_8 = or(_T_6, _T_7) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 373:35] node _T_9 = eq(sbState, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 375:21] node _T_10 = or(_T_8, _T_9) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 374:44] node _T_11 = eq(sbState, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 376:21] node _T_12 = or(_T_10, _T_11) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 375:45] node _T_13 = eq(sbState, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 377:21] node _T_14 = or(_T_12, _T_13) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 376:45] node _T_15 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 373:12] node _T_16 = eq(_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 373:12] when _T_16 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 373:12] node _T_17 = eq(_T_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 373:12] when _T_17 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 373:12] printf(clock, UInt<1>(0h1), "Assertion failed: SBA state machine in undefined state\n at SBA.scala:373 assert (sbState === Idle.id.U ||\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 373:12] assert(clock, _T_14, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 373:12] node _T_18 = eq(sbState, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 379:29] node _T_19 = eq(sbState, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 380:29] node _T_20 = eq(sbState, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 381:29] node _T_21 = eq(sbState, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 382:29] node _T_22 = eq(sbState, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 383:29] node _T_23 = eq(io.rdLegal, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 385:32] node _T_24 = and(io.rdEn, _T_23) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 385:29] node _T_25 = eq(io.wrLegal, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 386:32] node _T_26 = and(io.wrEn, _T_25) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 386:29] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_16 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_16 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_16 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module TLDebugModuleInner : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 790:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 790:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 790:9] output auto : { sb2tlOpt_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, flip custom_in : { flip addr : UInt<1>, data : UInt<0>, ready : UInt<1>, flip valid : UInt<1>}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip dmi_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output io : { flip dmactive : UInt<1>, flip innerCtrl : { flip ready : UInt<1>, valid : UInt<1>, bits : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[1], hrmask : UInt<1>[1]}}, flip debugUnavail : UInt<1>[1], hgDebugInt : UInt<1>[1], flip hartIsInReset : UInt<1>[1], flip tl_clock : Clock, flip tl_reset : Reset} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 802:16] inst sb2tlOpt of SBToTL @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 782:52] connect sb2tlOpt.clock, clock connect sb2tlOpt.reset, reset wire dmiNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate dmiNodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate dmiNodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire tlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tlNodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate tlNodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire customNodeIn : { flip addr : UInt<1>, data : UInt<0>, ready : UInt<1>, flip valid : UInt<1>} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate customNodeIn.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate customNodeIn.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate customNodeIn.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate customNodeIn.addr @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect dmiNodeIn, auto.dmi_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect tlNodeIn, auto.tl_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect customNodeIn, auto.custom_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect sb2tlOpt.auto.out.d, auto.sb2tlOpt_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.sb2tlOpt_out.a.bits, sb2tlOpt.auto.out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.sb2tlOpt_out.a.valid, sb2tlOpt.auto.out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect sb2tlOpt.auto.out.a.ready, auto.sb2tlOpt_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect sb2tlOpt.clock, io.tl_clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 833:23] connect sb2tlOpt.reset, io.tl_reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 834:23] connect sb2tlOpt.rf_reset, io.tl_reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 835:26] reg haltedBitRegs : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 860:31] reg resumeReqRegs : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 862:31] reg haveResetBitRegs : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 864:31] wire resumeAcks : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 868:32] wire hartHaltedWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 874:36] wire hartHaltedId : UInt<10> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 875:36] wire hartGoingWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 876:36] wire hartGoingId : UInt<10> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 877:36] wire hartResumingWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 878:36] wire hartResumingId : UInt<10> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 879:36] wire hartExceptionWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 880:36] wire hartExceptionId : UInt<10> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 881:36] wire _dmiProgramBufferRdEn_WIRE : UInt<1>[64] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[4], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[5], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[6], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[7], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[8], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[9], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[10], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[11], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[12], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[13], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[14], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[15], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[16], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[17], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[18], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[19], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[20], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[21], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[22], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[23], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[24], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[25], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[26], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[27], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[28], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[29], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[30], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[31], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[32], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[33], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[34], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[35], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[36], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[37], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[38], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[39], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[40], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[41], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[42], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[43], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[44], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[45], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[46], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[47], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[48], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[49], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[50], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[51], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[52], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[53], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[54], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[55], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[56], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[57], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[58], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[59], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[60], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[61], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[62], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] connect _dmiProgramBufferRdEn_WIRE[63], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:48] wire dmiProgramBufferRdEn : UInt<1>[64] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:40] connect dmiProgramBufferRdEn, _dmiProgramBufferRdEn_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 886:40] wire dmiProgramBufferAccessLegal : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 887:47] connect dmiProgramBufferAccessLegal, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 887:47] wire _dmiProgramBufferWrEnMaybe_WIRE : UInt<1>[64] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[4], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[5], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[6], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[7], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[8], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[9], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[10], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[11], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[12], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[13], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[14], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[15], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[16], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[17], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[18], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[19], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[20], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[21], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[22], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[23], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[24], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[25], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[26], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[27], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[28], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[29], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[30], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[31], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[32], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[33], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[34], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[35], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[36], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[37], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[38], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[39], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[40], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[41], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[42], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[43], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[44], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[45], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[46], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[47], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[48], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[49], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[50], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[51], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[52], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[53], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[54], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[55], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[56], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[57], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[58], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[59], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[60], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[61], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[62], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] connect _dmiProgramBufferWrEnMaybe_WIRE[63], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:53] wire dmiProgramBufferWrEnMaybe : UInt<1>[64] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:45] connect dmiProgramBufferWrEnMaybe, _dmiProgramBufferWrEnMaybe_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 888:45] wire _dmiAbstractDataRdEn_WIRE : UInt<1>[8] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 890:47] connect _dmiAbstractDataRdEn_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 890:47] connect _dmiAbstractDataRdEn_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 890:47] connect _dmiAbstractDataRdEn_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 890:47] connect _dmiAbstractDataRdEn_WIRE[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 890:47] connect _dmiAbstractDataRdEn_WIRE[4], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 890:47] connect _dmiAbstractDataRdEn_WIRE[5], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 890:47] connect _dmiAbstractDataRdEn_WIRE[6], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 890:47] connect _dmiAbstractDataRdEn_WIRE[7], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 890:47] wire dmiAbstractDataRdEn : UInt<1>[8] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 890:39] connect dmiAbstractDataRdEn, _dmiAbstractDataRdEn_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 890:39] wire dmiAbstractDataAccessLegal : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 891:46] connect dmiAbstractDataAccessLegal, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 891:46] wire _dmiAbstractDataWrEnMaybe_WIRE : UInt<1>[8] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 892:52] connect _dmiAbstractDataWrEnMaybe_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 892:52] connect _dmiAbstractDataWrEnMaybe_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 892:52] connect _dmiAbstractDataWrEnMaybe_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 892:52] connect _dmiAbstractDataWrEnMaybe_WIRE[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 892:52] connect _dmiAbstractDataWrEnMaybe_WIRE[4], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 892:52] connect _dmiAbstractDataWrEnMaybe_WIRE[5], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 892:52] connect _dmiAbstractDataWrEnMaybe_WIRE[6], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 892:52] connect _dmiAbstractDataWrEnMaybe_WIRE[7], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 892:52] wire dmiAbstractDataWrEnMaybe : UInt<1>[8] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 892:44] connect dmiAbstractDataWrEnMaybe, _dmiAbstractDataWrEnMaybe_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 892:44] reg selectedHartReg : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 900:30] wire _hamaskFull_WIRE : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 902:38] connect _hamaskFull_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 902:38] wire hamaskFull : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 902:30] connect hamaskFull, _hamaskFull_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 902:30] node _T = lt(selectedHartReg, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 924:27] when _T : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 924:44] connect hamaskFull[0], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 925:71] connect io.innerCtrl.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 928:24] wire _hamaskWrSel_WIRE : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 932:39] connect _hamaskWrSel_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 932:39] wire hamaskWrSel : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 932:31] connect hamaskWrSel, _hamaskWrSel_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 932:31] node _hamaskWrSel_0_T = eq(io.innerCtrl.bits.hartsel, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 934:61] node _hamaskWrSel_0_T_1 = or(_hamaskWrSel_0_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 934:78] connect hamaskWrSel[0], _hamaskWrSel_0_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 934:30] wire _hrReset_WIRE : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 944:38] connect _hrReset_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 944:38] wire hrReset : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 944:30] connect hrReset, _hrReset_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 944:30] wire hrDebugInt : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 945:26] regreset hrmaskReg : UInt<1>[1], clock, reset, hrReset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 946:29] wire hartIsInResetSync : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 947:33] inst hartIsInResetSync_0_debug_hartReset_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_16 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect hartIsInResetSync_0_debug_hartReset_0.clock, clock connect hartIsInResetSync_0_debug_hartReset_0.reset, reset connect hartIsInResetSync_0_debug_hartReset_0.io.d, io.hartIsInReset[0] @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _hartIsInResetSync_0_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _hartIsInResetSync_0_WIRE, hartIsInResetSync_0_debug_hartReset_0.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect hartIsInResetSync[0], _hartIsInResetSync_0_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 950:36] node _T_1 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 953:11] node _T_2 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 953:27] node _T_3 = or(_T_1, _T_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 953:24] when _T_3 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 953:45] connect hrmaskReg, hrReset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 954:17] else : node _T_4 = and(io.innerCtrl.ready, io.innerCtrl.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 955:35] connect hrmaskReg, io.innerCtrl.bits.hrmask @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 956:17] node _T_5 = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 959:21] wire _hrDebugIntReg_WIRE : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 960:42] connect _hrDebugIntReg_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 960:42] regreset hrDebugIntReg : UInt<1>[1], clock, _T_5, _hrDebugIntReg_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 960:34] node _T_6 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 961:13] node _T_7 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 961:29] node _T_8 = or(_T_6, _T_7) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 961:26] when _T_8 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 961:47] connect hrDebugIntReg, hrReset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 962:23] else : node _T_9 = bits(haltedBitRegs, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 966:44] node _T_10 = eq(_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 80:37] node _T_11 = and(hrDebugIntReg[0], _T_10) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 75:72] node _T_12 = or(hartIsInResetSync[0], _T_11) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 76:75] node _T_13 = and(hrmaskReg[0], _T_12) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 75:72] connect hrDebugIntReg[0], _T_13 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 964:23] connect hrDebugInt, hrDebugIntReg @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 968:18] wire _DMSTATUSRdData_WIRE : { reserved0 : UInt<9>, impebreak : UInt<1>, reserved1 : UInt<2>, allhavereset : UInt<1>, anyhavereset : UInt<1>, allresumeack : UInt<1>, anyresumeack : UInt<1>, allnonexistent : UInt<1>, anynonexistent : UInt<1>, allunavail : UInt<1>, anyunavail : UInt<1>, allrunning : UInt<1>, anyrunning : UInt<1>, allhalted : UInt<1>, anyhalted : UInt<1>, authenticated : UInt<1>, authbusy : UInt<1>, hasresethaltreq : UInt<1>, confstrptrvalid : UInt<1>, version : UInt<4>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.version, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.confstrptrvalid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.hasresethaltreq, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.authbusy, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.authenticated, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.anyhalted, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.allhalted, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.anyrunning, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.allrunning, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.anyunavail, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.allunavail, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.anynonexistent, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.allnonexistent, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.anyresumeack, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.allresumeack, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.anyhavereset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.allhavereset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.reserved1, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.impebreak, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] connect _DMSTATUSRdData_WIRE.reserved0, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:47] wire DMSTATUSRdData : { reserved0 : UInt<9>, impebreak : UInt<1>, reserved1 : UInt<2>, allhavereset : UInt<1>, anyhavereset : UInt<1>, allresumeack : UInt<1>, anyresumeack : UInt<1>, allnonexistent : UInt<1>, anynonexistent : UInt<1>, allunavail : UInt<1>, anyunavail : UInt<1>, allrunning : UInt<1>, anyrunning : UInt<1>, allhalted : UInt<1>, anyhalted : UInt<1>, authenticated : UInt<1>, authbusy : UInt<1>, hasresethaltreq : UInt<1>, confstrptrvalid : UInt<1>, version : UInt<4>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:34] connect DMSTATUSRdData, _DMSTATUSRdData_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 977:34] connect DMSTATUSRdData.authenticated, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 978:34] connect DMSTATUSRdData.version, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 979:34] node _resumereq_T = and(io.innerCtrl.ready, io.innerCtrl.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node resumereq = and(_resumereq_T, io.innerCtrl.bits.resumereq) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 982:39] when UInt<1>(0h1) : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 984:28] connect DMSTATUSRdData.hasresethaltreq, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 985:38] node _DMSTATUSRdData_anynonexistent_T = geq(selectedHartReg, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 987:57] connect DMSTATUSRdData.anynonexistent, _DMSTATUSRdData_anynonexistent_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 987:37] node _DMSTATUSRdData_allnonexistent_T = geq(selectedHartReg, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 990:57] node _DMSTATUSRdData_allnonexistent_T_1 = not(hamaskFull[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 990:78] node _DMSTATUSRdData_allnonexistent_T_2 = and(_DMSTATUSRdData_allnonexistent_T, _DMSTATUSRdData_allnonexistent_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 990:75] connect DMSTATUSRdData.allnonexistent, _DMSTATUSRdData_allnonexistent_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 990:37] node _T_14 = not(DMSTATUSRdData.allnonexistent) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 992:13] when _T_14 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 992:45] node _DMSTATUSRdData_anyunavail_T = and(io.debugUnavail[0], hamaskFull[0]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 75:72] connect DMSTATUSRdData.anyunavail, _DMSTATUSRdData_anyunavail_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 993:37] node _DMSTATUSRdData_anyhalted_T = eq(io.debugUnavail[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 80:37] node _DMSTATUSRdData_anyhalted_T_1 = bits(haltedBitRegs, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 994:77] node _DMSTATUSRdData_anyhalted_T_2 = and(_DMSTATUSRdData_anyhalted_T, _DMSTATUSRdData_anyhalted_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 75:72] node _DMSTATUSRdData_anyhalted_T_3 = and(_DMSTATUSRdData_anyhalted_T_2, hamaskFull[0]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 75:72] connect DMSTATUSRdData.anyhalted, _DMSTATUSRdData_anyhalted_T_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 994:37] node _DMSTATUSRdData_anyrunning_T = eq(io.debugUnavail[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 80:37] node _DMSTATUSRdData_anyrunning_T_1 = bits(haltedBitRegs, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 995:77] node _DMSTATUSRdData_anyrunning_T_2 = eq(_DMSTATUSRdData_anyrunning_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 80:37] node _DMSTATUSRdData_anyrunning_T_3 = and(_DMSTATUSRdData_anyrunning_T, _DMSTATUSRdData_anyrunning_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 75:72] node _DMSTATUSRdData_anyrunning_T_4 = and(_DMSTATUSRdData_anyrunning_T_3, hamaskFull[0]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 75:72] connect DMSTATUSRdData.anyrunning, _DMSTATUSRdData_anyrunning_T_4 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 995:37] node _DMSTATUSRdData_anyhavereset_T = bits(haveResetBitRegs, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 996:58] node _DMSTATUSRdData_anyhavereset_T_1 = and(_DMSTATUSRdData_anyhavereset_T, hamaskFull[0]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 75:72] connect DMSTATUSRdData.anyhavereset, _DMSTATUSRdData_anyhavereset_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 996:37] node _DMSTATUSRdData_anyresumeack_T = bits(resumeAcks, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 997:52] node _DMSTATUSRdData_anyresumeack_T_1 = and(_DMSTATUSRdData_anyresumeack_T, hamaskFull[0]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 75:72] connect DMSTATUSRdData.anyresumeack, _DMSTATUSRdData_anyresumeack_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 997:37] node _T_15 = not(DMSTATUSRdData.anynonexistent) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 998:15] when _T_15 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 998:47] node _DMSTATUSRdData_allunavail_T = eq(hamaskFull[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 80:37] node _DMSTATUSRdData_allunavail_T_1 = or(io.debugUnavail[0], _DMSTATUSRdData_allunavail_T) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 76:75] connect DMSTATUSRdData.allunavail, _DMSTATUSRdData_allunavail_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 999:39] node _DMSTATUSRdData_allhalted_T = eq(io.debugUnavail[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 80:37] node _DMSTATUSRdData_allhalted_T_1 = bits(haltedBitRegs, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1000:79] node _DMSTATUSRdData_allhalted_T_2 = and(_DMSTATUSRdData_allhalted_T, _DMSTATUSRdData_allhalted_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 75:72] node _DMSTATUSRdData_allhalted_T_3 = eq(hamaskFull[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 80:37] node _DMSTATUSRdData_allhalted_T_4 = or(_DMSTATUSRdData_allhalted_T_2, _DMSTATUSRdData_allhalted_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 76:75] connect DMSTATUSRdData.allhalted, _DMSTATUSRdData_allhalted_T_4 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1000:39] node _DMSTATUSRdData_allrunning_T = eq(io.debugUnavail[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 80:37] node _DMSTATUSRdData_allrunning_T_1 = bits(haltedBitRegs, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1001:79] node _DMSTATUSRdData_allrunning_T_2 = eq(_DMSTATUSRdData_allrunning_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 80:37] node _DMSTATUSRdData_allrunning_T_3 = and(_DMSTATUSRdData_allrunning_T, _DMSTATUSRdData_allrunning_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 75:72] node _DMSTATUSRdData_allrunning_T_4 = eq(hamaskFull[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 80:37] node _DMSTATUSRdData_allrunning_T_5 = or(_DMSTATUSRdData_allrunning_T_3, _DMSTATUSRdData_allrunning_T_4) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 76:75] connect DMSTATUSRdData.allrunning, _DMSTATUSRdData_allrunning_T_5 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1001:39] node _DMSTATUSRdData_allhavereset_T = bits(haveResetBitRegs, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1002:60] node _DMSTATUSRdData_allhavereset_T_1 = eq(hamaskFull[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 80:37] node _DMSTATUSRdData_allhavereset_T_2 = or(_DMSTATUSRdData_allhavereset_T, _DMSTATUSRdData_allhavereset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 76:75] connect DMSTATUSRdData.allhavereset, _DMSTATUSRdData_allhavereset_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1002:39] node _DMSTATUSRdData_allresumeack_T = bits(resumeAcks, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1003:54] node _DMSTATUSRdData_allresumeack_T_1 = eq(hamaskFull[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 80:37] node _DMSTATUSRdData_allresumeack_T_2 = or(_DMSTATUSRdData_allresumeack_T, _DMSTATUSRdData_allresumeack_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 76:75] connect DMSTATUSRdData.allresumeack, _DMSTATUSRdData_allresumeack_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1003:39] connect DMSTATUSRdData.confstrptrvalid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1008:38] connect DMSTATUSRdData.impebreak, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1009:32] node _T_16 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1012:10] node _T_17 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1012:26] node _T_18 = or(_T_16, _T_17) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1012:23] when _T_18 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1012:44] connect haveResetBitRegs, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1013:24] else : node _T_19 = and(io.innerCtrl.ready, io.innerCtrl.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _T_20 = and(_T_19, io.innerCtrl.bits.ackhavereset) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1015:31] when _T_20 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1015:66] node _haveResetBitRegs_T = not(hamaskWrSel[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1016:50] node _haveResetBitRegs_T_1 = and(haveResetBitRegs, _haveResetBitRegs_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1016:47] node _haveResetBitRegs_T_2 = or(_haveResetBitRegs_T_1, hartIsInResetSync[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1016:74] connect haveResetBitRegs, _haveResetBitRegs_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1016:26] else : node _haveResetBitRegs_T_3 = or(haveResetBitRegs, hartIsInResetSync[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1018:46] connect haveResetBitRegs, _haveResetBitRegs_T_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1018:26] wire _DMCS2RdData_WIRE : { reserved0 : UInt<21>, exttrigger : UInt<4>, haltgroup : UInt<5>, hgwrite : UInt<1>, hgselect : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1024:47] connect _DMCS2RdData_WIRE.hgselect, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1024:47] connect _DMCS2RdData_WIRE.hgwrite, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1024:47] connect _DMCS2RdData_WIRE.haltgroup, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1024:47] connect _DMCS2RdData_WIRE.exttrigger, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1024:47] connect _DMCS2RdData_WIRE.reserved0, UInt<21>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1024:47] wire DMCS2RdData : { reserved0 : UInt<21>, exttrigger : UInt<4>, haltgroup : UInt<5>, hgwrite : UInt<1>, hgselect : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1024:34] connect DMCS2RdData, _DMCS2RdData_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1024:34] wire _DMCS2WrData_WIRE : { reserved0 : UInt<21>, exttrigger : UInt<4>, haltgroup : UInt<5>, hgwrite : UInt<1>, hgselect : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1025:47] connect _DMCS2WrData_WIRE.hgselect, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1025:47] connect _DMCS2WrData_WIRE.hgwrite, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1025:47] connect _DMCS2WrData_WIRE.haltgroup, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1025:47] connect _DMCS2WrData_WIRE.exttrigger, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1025:47] connect _DMCS2WrData_WIRE.reserved0, UInt<21>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1025:47] wire DMCS2WrData : { reserved0 : UInt<21>, exttrigger : UInt<4>, haltgroup : UInt<5>, hgwrite : UInt<1>, hgselect : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1025:34] connect DMCS2WrData, _DMCS2WrData_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1025:34] wire hgselectWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1026:34] connect hgselectWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1026:34] wire hgwriteWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1027:34] connect hgwriteWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1027:34] wire haltgroupWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1028:34] connect haltgroupWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1028:34] wire exttriggerWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1029:34] connect exttriggerWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1029:34] wire _hgDebugInt_WIRE : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1030:42] connect _hgDebugInt_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1030:42] wire hgDebugInt : UInt<1>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1030:34] connect hgDebugInt, _hgDebugInt_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1030:34] node _T_21 = or(hgDebugInt[0], hrDebugInt[0]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 76:75] connect io.hgDebugInt[0], _T_21 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1153:19] wire haltedStatus : UInt<32>[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1158:30] when UInt<1>(0h1) : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1161:30] node _haltedStatus_0_T = shr(haltedBitRegs, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1162:43] connect haltedStatus[0], _haltedStatus_0_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1162:26] else : connect haltedStatus[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1164:26] node haltedSummary = orr(haltedStatus[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1168:48] wire HALTSUM1RdData : { haltsum1 : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1169:48] wire _HALTSUM1RdData_WIRE : UInt<32> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1169:48] connect _HALTSUM1RdData_WIRE, haltedSummary @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1169:48] node _HALTSUM1RdData_T = bits(_HALTSUM1RdData_WIRE, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1169:48] connect HALTSUM1RdData.haltsum1, _HALTSUM1RdData_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1169:48] node _selectedHaltedStatus_T = shr(selectedHartReg, 5) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1171:53] node _selectedHaltedStatus_T_1 = gt(_selectedHaltedStatus_T, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1171:59] node _selectedHaltedStatus_T_2 = shr(selectedHartReg, 5) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1171:114] wire _selectedHaltedStatus_WIRE : UInt connect _selectedHaltedStatus_WIRE, UInt<1>(0h0) node selectedHaltedStatus = mux(_selectedHaltedStatus_T_1, UInt<1>(0h0), haltedStatus[_selectedHaltedStatus_WIRE]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1171:35] wire HALTSUM0RdData : { haltsum0 : UInt<32>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1172:55] wire _HALTSUM0RdData_WIRE : UInt<32> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1172:55] connect _HALTSUM0RdData_WIRE, selectedHaltedStatus @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1172:55] node _HALTSUM0RdData_T = bits(_HALTSUM0RdData_WIRE, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1172:55] connect HALTSUM0RdData.haltsum0, _HALTSUM0RdData_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1172:55] wire _ABSTRACTCSReset_WIRE : { reserved0 : UInt<3>, progbufsize : UInt<5>, reserved1 : UInt<11>, busy : UInt<1>, reserved2 : UInt<1>, cmderr : UInt<3>, reserved3 : UInt<4>, datacount : UInt<4>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1178:48] connect _ABSTRACTCSReset_WIRE.datacount, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1178:48] connect _ABSTRACTCSReset_WIRE.reserved3, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1178:48] connect _ABSTRACTCSReset_WIRE.cmderr, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1178:48] connect _ABSTRACTCSReset_WIRE.reserved2, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1178:48] connect _ABSTRACTCSReset_WIRE.busy, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1178:48] connect _ABSTRACTCSReset_WIRE.reserved1, UInt<11>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1178:48] connect _ABSTRACTCSReset_WIRE.progbufsize, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1178:48] connect _ABSTRACTCSReset_WIRE.reserved0, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1178:48] wire ABSTRACTCSReset : { reserved0 : UInt<3>, progbufsize : UInt<5>, reserved1 : UInt<11>, busy : UInt<1>, reserved2 : UInt<1>, cmderr : UInt<3>, reserved3 : UInt<4>, datacount : UInt<4>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1178:35] connect ABSTRACTCSReset, _ABSTRACTCSReset_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1178:35] connect ABSTRACTCSReset.datacount, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1179:33] connect ABSTRACTCSReset.progbufsize, UInt<5>(0h10) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1180:33] reg ABSTRACTCSReg : { reserved0 : UInt<3>, progbufsize : UInt<5>, reserved1 : UInt<11>, busy : UInt<1>, reserved2 : UInt<1>, cmderr : UInt<3>, reserved3 : UInt<4>, datacount : UInt<4>}, clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1182:34] wire _ABSTRACTCSWrData_WIRE : { reserved0 : UInt<3>, progbufsize : UInt<5>, reserved1 : UInt<11>, busy : UInt<1>, reserved2 : UInt<1>, cmderr : UInt<3>, reserved3 : UInt<4>, datacount : UInt<4>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1183:52] connect _ABSTRACTCSWrData_WIRE.datacount, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1183:52] connect _ABSTRACTCSWrData_WIRE.reserved3, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1183:52] connect _ABSTRACTCSWrData_WIRE.cmderr, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1183:52] connect _ABSTRACTCSWrData_WIRE.reserved2, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1183:52] connect _ABSTRACTCSWrData_WIRE.busy, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1183:52] connect _ABSTRACTCSWrData_WIRE.reserved1, UInt<11>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1183:52] connect _ABSTRACTCSWrData_WIRE.progbufsize, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1183:52] connect _ABSTRACTCSWrData_WIRE.reserved0, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1183:52] wire ABSTRACTCSWrData : { reserved0 : UInt<3>, progbufsize : UInt<5>, reserved1 : UInt<11>, busy : UInt<1>, reserved2 : UInt<1>, cmderr : UInt<3>, reserved3 : UInt<4>, datacount : UInt<4>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1183:39] connect ABSTRACTCSWrData, _ABSTRACTCSWrData_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1183:39] wire ABSTRACTCSRdData : { reserved0 : UInt<3>, progbufsize : UInt<5>, reserved1 : UInt<11>, busy : UInt<1>, reserved2 : UInt<1>, cmderr : UInt<3>, reserved3 : UInt<4>, datacount : UInt<4>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1184:39] connect ABSTRACTCSRdData, ABSTRACTCSReg @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1184:39] wire ABSTRACTCSRdEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1186:34] connect ABSTRACTCSRdEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1186:34] wire ABSTRACTCSWrEnMaybe : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1187:39] connect ABSTRACTCSWrEnMaybe, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1187:39] wire ABSTRACTCSWrEnLegal : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1189:39] connect ABSTRACTCSWrEnLegal, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1189:39] node ABSTRACTCSWrEn = and(ABSTRACTCSWrEnMaybe, ABSTRACTCSWrEnLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1190:51] wire errorBusy : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1194:36] connect errorBusy, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1194:36] wire errorException : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1195:36] connect errorException, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1195:36] wire errorUnsupported : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1196:36] connect errorUnsupported, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1196:36] wire errorHaltResume : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1197:36] connect errorHaltResume, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1197:36] node _T_22 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1199:11] node _T_23 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1199:27] node _T_24 = or(_T_22, _T_23) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1199:24] when _T_24 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1199:45] connect ABSTRACTCSReg, ABSTRACTCSReset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1200:21] else : when errorBusy : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1202:23] connect ABSTRACTCSReg.cmderr, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1203:30] else : when errorException : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1204:35] connect ABSTRACTCSReg.cmderr, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1205:30] else : when errorUnsupported : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1206:37] connect ABSTRACTCSReg.cmderr, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1207:30] else : when errorHaltResume : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1208:36] connect ABSTRACTCSReg.cmderr, UInt<3>(0h4) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1209:30] else : when ABSTRACTCSWrEn : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1212:30] node _ABSTRACTCSReg_cmderr_T = not(ABSTRACTCSWrData.cmderr) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1213:58] node _ABSTRACTCSReg_cmderr_T_1 = and(ABSTRACTCSReg.cmderr, _ABSTRACTCSReg_cmderr_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1213:56] connect ABSTRACTCSReg.cmderr, _ABSTRACTCSReg_cmderr_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1213:32] wire abstractCommandBusy : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1219:39] connect abstractCommandBusy, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1219:39] connect ABSTRACTCSRdData.busy, abstractCommandBusy @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1220:27] node _T_25 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1221:11] when _T_25 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1221:29] connect ABSTRACTCSRdData.datacount, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1222:34] connect ABSTRACTCSRdData.progbufsize, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1223:36] wire _ABSTRACTAUTOReset_WIRE : { autoexecprogbuf : UInt<16>, reserved0 : UInt<4>, autoexecdata : UInt<12>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1233:54] connect _ABSTRACTAUTOReset_WIRE.autoexecdata, UInt<12>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1233:54] connect _ABSTRACTAUTOReset_WIRE.reserved0, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1233:54] connect _ABSTRACTAUTOReset_WIRE.autoexecprogbuf, UInt<16>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1233:54] wire ABSTRACTAUTOReset : { autoexecprogbuf : UInt<16>, reserved0 : UInt<4>, autoexecdata : UInt<12>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1233:41] connect ABSTRACTAUTOReset, _ABSTRACTAUTOReset_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1233:41] reg ABSTRACTAUTOReg : { autoexecprogbuf : UInt<16>, reserved0 : UInt<4>, autoexecdata : UInt<12>}, clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1234:36] wire _ABSTRACTAUTOWrData_WIRE : { autoexecprogbuf : UInt<16>, reserved0 : UInt<4>, autoexecdata : UInt<12>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1235:54] connect _ABSTRACTAUTOWrData_WIRE.autoexecdata, UInt<12>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1235:54] connect _ABSTRACTAUTOWrData_WIRE.reserved0, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1235:54] connect _ABSTRACTAUTOWrData_WIRE.autoexecprogbuf, UInt<16>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1235:54] wire ABSTRACTAUTOWrData : { autoexecprogbuf : UInt<16>, reserved0 : UInt<4>, autoexecdata : UInt<12>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1235:41] connect ABSTRACTAUTOWrData, _ABSTRACTAUTOWrData_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1235:41] wire ABSTRACTAUTORdData : { autoexecprogbuf : UInt<16>, reserved0 : UInt<4>, autoexecdata : UInt<12>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1236:41] connect ABSTRACTAUTORdData, ABSTRACTAUTOReg @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1236:41] wire ABSTRACTAUTORdEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1238:36] connect ABSTRACTAUTORdEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1238:36] wire autoexecdataWrEnMaybe : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1239:41] connect autoexecdataWrEnMaybe, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1239:41] wire autoexecprogbufWrEnMaybe : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1240:44] connect autoexecprogbufWrEnMaybe, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1240:44] wire ABSTRACTAUTOWrEnLegal : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1242:41] connect ABSTRACTAUTOWrEnLegal, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1242:41] node _T_26 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1244:11] node _T_27 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1244:27] node _T_28 = or(_T_26, _T_27) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1244:24] when _T_28 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1244:45] connect ABSTRACTAUTOReg, ABSTRACTAUTOReset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1245:23] else : node _T_29 = and(autoexecprogbufWrEnMaybe, ABSTRACTAUTOWrEnLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1247:38] when _T_29 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1247:64] node _ABSTRACTAUTOReg_autoexecprogbuf_T = and(ABSTRACTAUTOWrData.autoexecprogbuf, UInt<16>(0hffff)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1248:79] connect ABSTRACTAUTOReg.autoexecprogbuf, _ABSTRACTAUTOReg_autoexecprogbuf_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1248:41] node _T_30 = and(autoexecdataWrEnMaybe, ABSTRACTAUTOWrEnLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1250:35] when _T_30 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1250:61] node _ABSTRACTAUTOReg_autoexecdata_T = and(ABSTRACTAUTOWrData.autoexecdata, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1251:73] connect ABSTRACTAUTOReg.autoexecdata, _ABSTRACTAUTOReg_autoexecdata_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1251:38] wire _dmiAbstractDataAccessVec_WIRE : UInt<1>[8] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1256:53] connect _dmiAbstractDataAccessVec_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1256:53] connect _dmiAbstractDataAccessVec_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1256:53] connect _dmiAbstractDataAccessVec_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1256:53] connect _dmiAbstractDataAccessVec_WIRE[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1256:53] connect _dmiAbstractDataAccessVec_WIRE[4], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1256:53] connect _dmiAbstractDataAccessVec_WIRE[5], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1256:53] connect _dmiAbstractDataAccessVec_WIRE[6], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1256:53] connect _dmiAbstractDataAccessVec_WIRE[7], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1256:53] wire dmiAbstractDataAccessVec : UInt<1>[8] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1256:45] connect dmiAbstractDataAccessVec, _dmiAbstractDataAccessVec_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1256:45] node _T_31 = or(dmiAbstractDataWrEnMaybe[0], dmiAbstractDataRdEn[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1257:105] node _T_32 = or(dmiAbstractDataWrEnMaybe[1], dmiAbstractDataRdEn[1]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1257:105] node _T_33 = or(dmiAbstractDataWrEnMaybe[2], dmiAbstractDataRdEn[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1257:105] node _T_34 = or(dmiAbstractDataWrEnMaybe[3], dmiAbstractDataRdEn[3]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1257:105] node _T_35 = or(dmiAbstractDataWrEnMaybe[4], dmiAbstractDataRdEn[4]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1257:105] node _T_36 = or(dmiAbstractDataWrEnMaybe[5], dmiAbstractDataRdEn[5]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1257:105] node _T_37 = or(dmiAbstractDataWrEnMaybe[6], dmiAbstractDataRdEn[6]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1257:105] node _T_38 = or(dmiAbstractDataWrEnMaybe[7], dmiAbstractDataRdEn[7]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1257:105] connect dmiAbstractDataAccessVec[0], _T_31 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1257:30] connect dmiAbstractDataAccessVec[1], _T_32 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1257:30] connect dmiAbstractDataAccessVec[2], _T_33 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1257:30] connect dmiAbstractDataAccessVec[3], _T_34 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1257:30] connect dmiAbstractDataAccessVec[4], _T_35 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1257:30] connect dmiAbstractDataAccessVec[5], _T_36 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1257:30] connect dmiAbstractDataAccessVec[6], _T_37 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1257:30] connect dmiAbstractDataAccessVec[7], _T_38 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1257:30] wire _dmiProgramBufferAccessVec_WIRE : UInt<1>[64] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[4], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[5], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[6], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[7], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[8], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[9], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[10], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[11], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[12], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[13], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[14], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[15], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[16], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[17], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[18], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[19], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[20], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[21], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[22], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[23], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[24], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[25], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[26], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[27], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[28], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[29], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[30], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[31], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[32], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[33], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[34], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[35], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[36], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[37], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[38], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[39], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[40], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[41], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[42], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[43], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[44], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[45], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[46], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[47], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[48], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[49], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[50], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[51], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[52], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[53], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[54], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[55], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[56], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[57], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[58], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[59], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[60], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[61], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[62], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] connect _dmiProgramBufferAccessVec_WIRE[63], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:54] wire dmiProgramBufferAccessVec : UInt<1>[64] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:46] connect dmiProgramBufferAccessVec, _dmiProgramBufferAccessVec_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1259:46] node _T_39 = or(dmiProgramBufferWrEnMaybe[0], dmiProgramBufferRdEn[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_40 = or(dmiProgramBufferWrEnMaybe[1], dmiProgramBufferRdEn[1]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_41 = or(dmiProgramBufferWrEnMaybe[2], dmiProgramBufferRdEn[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_42 = or(dmiProgramBufferWrEnMaybe[3], dmiProgramBufferRdEn[3]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_43 = or(dmiProgramBufferWrEnMaybe[4], dmiProgramBufferRdEn[4]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_44 = or(dmiProgramBufferWrEnMaybe[5], dmiProgramBufferRdEn[5]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_45 = or(dmiProgramBufferWrEnMaybe[6], dmiProgramBufferRdEn[6]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_46 = or(dmiProgramBufferWrEnMaybe[7], dmiProgramBufferRdEn[7]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_47 = or(dmiProgramBufferWrEnMaybe[8], dmiProgramBufferRdEn[8]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_48 = or(dmiProgramBufferWrEnMaybe[9], dmiProgramBufferRdEn[9]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_49 = or(dmiProgramBufferWrEnMaybe[10], dmiProgramBufferRdEn[10]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_50 = or(dmiProgramBufferWrEnMaybe[11], dmiProgramBufferRdEn[11]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_51 = or(dmiProgramBufferWrEnMaybe[12], dmiProgramBufferRdEn[12]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_52 = or(dmiProgramBufferWrEnMaybe[13], dmiProgramBufferRdEn[13]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_53 = or(dmiProgramBufferWrEnMaybe[14], dmiProgramBufferRdEn[14]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_54 = or(dmiProgramBufferWrEnMaybe[15], dmiProgramBufferRdEn[15]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_55 = or(dmiProgramBufferWrEnMaybe[16], dmiProgramBufferRdEn[16]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_56 = or(dmiProgramBufferWrEnMaybe[17], dmiProgramBufferRdEn[17]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_57 = or(dmiProgramBufferWrEnMaybe[18], dmiProgramBufferRdEn[18]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_58 = or(dmiProgramBufferWrEnMaybe[19], dmiProgramBufferRdEn[19]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_59 = or(dmiProgramBufferWrEnMaybe[20], dmiProgramBufferRdEn[20]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_60 = or(dmiProgramBufferWrEnMaybe[21], dmiProgramBufferRdEn[21]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_61 = or(dmiProgramBufferWrEnMaybe[22], dmiProgramBufferRdEn[22]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_62 = or(dmiProgramBufferWrEnMaybe[23], dmiProgramBufferRdEn[23]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_63 = or(dmiProgramBufferWrEnMaybe[24], dmiProgramBufferRdEn[24]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_64 = or(dmiProgramBufferWrEnMaybe[25], dmiProgramBufferRdEn[25]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_65 = or(dmiProgramBufferWrEnMaybe[26], dmiProgramBufferRdEn[26]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_66 = or(dmiProgramBufferWrEnMaybe[27], dmiProgramBufferRdEn[27]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_67 = or(dmiProgramBufferWrEnMaybe[28], dmiProgramBufferRdEn[28]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_68 = or(dmiProgramBufferWrEnMaybe[29], dmiProgramBufferRdEn[29]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_69 = or(dmiProgramBufferWrEnMaybe[30], dmiProgramBufferRdEn[30]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_70 = or(dmiProgramBufferWrEnMaybe[31], dmiProgramBufferRdEn[31]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_71 = or(dmiProgramBufferWrEnMaybe[32], dmiProgramBufferRdEn[32]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_72 = or(dmiProgramBufferWrEnMaybe[33], dmiProgramBufferRdEn[33]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_73 = or(dmiProgramBufferWrEnMaybe[34], dmiProgramBufferRdEn[34]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_74 = or(dmiProgramBufferWrEnMaybe[35], dmiProgramBufferRdEn[35]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_75 = or(dmiProgramBufferWrEnMaybe[36], dmiProgramBufferRdEn[36]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_76 = or(dmiProgramBufferWrEnMaybe[37], dmiProgramBufferRdEn[37]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_77 = or(dmiProgramBufferWrEnMaybe[38], dmiProgramBufferRdEn[38]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_78 = or(dmiProgramBufferWrEnMaybe[39], dmiProgramBufferRdEn[39]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_79 = or(dmiProgramBufferWrEnMaybe[40], dmiProgramBufferRdEn[40]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_80 = or(dmiProgramBufferWrEnMaybe[41], dmiProgramBufferRdEn[41]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_81 = or(dmiProgramBufferWrEnMaybe[42], dmiProgramBufferRdEn[42]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_82 = or(dmiProgramBufferWrEnMaybe[43], dmiProgramBufferRdEn[43]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_83 = or(dmiProgramBufferWrEnMaybe[44], dmiProgramBufferRdEn[44]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_84 = or(dmiProgramBufferWrEnMaybe[45], dmiProgramBufferRdEn[45]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_85 = or(dmiProgramBufferWrEnMaybe[46], dmiProgramBufferRdEn[46]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_86 = or(dmiProgramBufferWrEnMaybe[47], dmiProgramBufferRdEn[47]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_87 = or(dmiProgramBufferWrEnMaybe[48], dmiProgramBufferRdEn[48]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_88 = or(dmiProgramBufferWrEnMaybe[49], dmiProgramBufferRdEn[49]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_89 = or(dmiProgramBufferWrEnMaybe[50], dmiProgramBufferRdEn[50]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_90 = or(dmiProgramBufferWrEnMaybe[51], dmiProgramBufferRdEn[51]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_91 = or(dmiProgramBufferWrEnMaybe[52], dmiProgramBufferRdEn[52]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_92 = or(dmiProgramBufferWrEnMaybe[53], dmiProgramBufferRdEn[53]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_93 = or(dmiProgramBufferWrEnMaybe[54], dmiProgramBufferRdEn[54]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_94 = or(dmiProgramBufferWrEnMaybe[55], dmiProgramBufferRdEn[55]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_95 = or(dmiProgramBufferWrEnMaybe[56], dmiProgramBufferRdEn[56]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_96 = or(dmiProgramBufferWrEnMaybe[57], dmiProgramBufferRdEn[57]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_97 = or(dmiProgramBufferWrEnMaybe[58], dmiProgramBufferRdEn[58]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_98 = or(dmiProgramBufferWrEnMaybe[59], dmiProgramBufferRdEn[59]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_99 = or(dmiProgramBufferWrEnMaybe[60], dmiProgramBufferRdEn[60]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_100 = or(dmiProgramBufferWrEnMaybe[61], dmiProgramBufferRdEn[61]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_101 = or(dmiProgramBufferWrEnMaybe[62], dmiProgramBufferRdEn[62]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] node _T_102 = or(dmiProgramBufferWrEnMaybe[63], dmiProgramBufferRdEn[63]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:108] connect dmiProgramBufferAccessVec[0], _T_39 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[1], _T_40 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[2], _T_41 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[3], _T_42 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[4], _T_43 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[5], _T_44 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[6], _T_45 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[7], _T_46 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[8], _T_47 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[9], _T_48 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[10], _T_49 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[11], _T_50 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[12], _T_51 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[13], _T_52 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[14], _T_53 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[15], _T_54 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[16], _T_55 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[17], _T_56 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[18], _T_57 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[19], _T_58 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[20], _T_59 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[21], _T_60 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[22], _T_61 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[23], _T_62 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[24], _T_63 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[25], _T_64 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[26], _T_65 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[27], _T_66 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[28], _T_67 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[29], _T_68 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[30], _T_69 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[31], _T_70 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[32], _T_71 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[33], _T_72 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[34], _T_73 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[35], _T_74 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[36], _T_75 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[37], _T_76 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[38], _T_77 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[39], _T_78 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[40], _T_79 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[41], _T_80 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[42], _T_81 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[43], _T_82 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[44], _T_83 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[45], _T_84 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[46], _T_85 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[47], _T_86 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[48], _T_87 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[49], _T_88 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[50], _T_89 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[51], _T_90 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[52], _T_91 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[53], _T_92 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[54], _T_93 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[55], _T_94 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[56], _T_95 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[57], _T_96 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[58], _T_97 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[59], _T_98 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[60], _T_99 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[61], _T_100 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[62], _T_101 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] connect dmiProgramBufferAccessVec[63], _T_102 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1260:31] node _dmiAbstractDataAccess_T = or(dmiAbstractDataAccessVec[0], dmiAbstractDataAccessVec[1]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1262:68] node _dmiAbstractDataAccess_T_1 = or(_dmiAbstractDataAccess_T, dmiAbstractDataAccessVec[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1262:68] node _dmiAbstractDataAccess_T_2 = or(_dmiAbstractDataAccess_T_1, dmiAbstractDataAccessVec[3]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1262:68] node _dmiAbstractDataAccess_T_3 = or(_dmiAbstractDataAccess_T_2, dmiAbstractDataAccessVec[4]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1262:68] node _dmiAbstractDataAccess_T_4 = or(_dmiAbstractDataAccess_T_3, dmiAbstractDataAccessVec[5]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1262:68] node _dmiAbstractDataAccess_T_5 = or(_dmiAbstractDataAccess_T_4, dmiAbstractDataAccessVec[6]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1262:68] node dmiAbstractDataAccess = or(_dmiAbstractDataAccess_T_5, dmiAbstractDataAccessVec[7]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1262:68] node _dmiProgramBufferAccess_T = or(dmiProgramBufferAccessVec[0], dmiProgramBufferAccessVec[1]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_1 = or(_dmiProgramBufferAccess_T, dmiProgramBufferAccessVec[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_2 = or(_dmiProgramBufferAccess_T_1, dmiProgramBufferAccessVec[3]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_3 = or(_dmiProgramBufferAccess_T_2, dmiProgramBufferAccessVec[4]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_4 = or(_dmiProgramBufferAccess_T_3, dmiProgramBufferAccessVec[5]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_5 = or(_dmiProgramBufferAccess_T_4, dmiProgramBufferAccessVec[6]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_6 = or(_dmiProgramBufferAccess_T_5, dmiProgramBufferAccessVec[7]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_7 = or(_dmiProgramBufferAccess_T_6, dmiProgramBufferAccessVec[8]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_8 = or(_dmiProgramBufferAccess_T_7, dmiProgramBufferAccessVec[9]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_9 = or(_dmiProgramBufferAccess_T_8, dmiProgramBufferAccessVec[10]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_10 = or(_dmiProgramBufferAccess_T_9, dmiProgramBufferAccessVec[11]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_11 = or(_dmiProgramBufferAccess_T_10, dmiProgramBufferAccessVec[12]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_12 = or(_dmiProgramBufferAccess_T_11, dmiProgramBufferAccessVec[13]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_13 = or(_dmiProgramBufferAccess_T_12, dmiProgramBufferAccessVec[14]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_14 = or(_dmiProgramBufferAccess_T_13, dmiProgramBufferAccessVec[15]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_15 = or(_dmiProgramBufferAccess_T_14, dmiProgramBufferAccessVec[16]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_16 = or(_dmiProgramBufferAccess_T_15, dmiProgramBufferAccessVec[17]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_17 = or(_dmiProgramBufferAccess_T_16, dmiProgramBufferAccessVec[18]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_18 = or(_dmiProgramBufferAccess_T_17, dmiProgramBufferAccessVec[19]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_19 = or(_dmiProgramBufferAccess_T_18, dmiProgramBufferAccessVec[20]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_20 = or(_dmiProgramBufferAccess_T_19, dmiProgramBufferAccessVec[21]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_21 = or(_dmiProgramBufferAccess_T_20, dmiProgramBufferAccessVec[22]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_22 = or(_dmiProgramBufferAccess_T_21, dmiProgramBufferAccessVec[23]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_23 = or(_dmiProgramBufferAccess_T_22, dmiProgramBufferAccessVec[24]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_24 = or(_dmiProgramBufferAccess_T_23, dmiProgramBufferAccessVec[25]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_25 = or(_dmiProgramBufferAccess_T_24, dmiProgramBufferAccessVec[26]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_26 = or(_dmiProgramBufferAccess_T_25, dmiProgramBufferAccessVec[27]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_27 = or(_dmiProgramBufferAccess_T_26, dmiProgramBufferAccessVec[28]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_28 = or(_dmiProgramBufferAccess_T_27, dmiProgramBufferAccessVec[29]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_29 = or(_dmiProgramBufferAccess_T_28, dmiProgramBufferAccessVec[30]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_30 = or(_dmiProgramBufferAccess_T_29, dmiProgramBufferAccessVec[31]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_31 = or(_dmiProgramBufferAccess_T_30, dmiProgramBufferAccessVec[32]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_32 = or(_dmiProgramBufferAccess_T_31, dmiProgramBufferAccessVec[33]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_33 = or(_dmiProgramBufferAccess_T_32, dmiProgramBufferAccessVec[34]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_34 = or(_dmiProgramBufferAccess_T_33, dmiProgramBufferAccessVec[35]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_35 = or(_dmiProgramBufferAccess_T_34, dmiProgramBufferAccessVec[36]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_36 = or(_dmiProgramBufferAccess_T_35, dmiProgramBufferAccessVec[37]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_37 = or(_dmiProgramBufferAccess_T_36, dmiProgramBufferAccessVec[38]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_38 = or(_dmiProgramBufferAccess_T_37, dmiProgramBufferAccessVec[39]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_39 = or(_dmiProgramBufferAccess_T_38, dmiProgramBufferAccessVec[40]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_40 = or(_dmiProgramBufferAccess_T_39, dmiProgramBufferAccessVec[41]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_41 = or(_dmiProgramBufferAccess_T_40, dmiProgramBufferAccessVec[42]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_42 = or(_dmiProgramBufferAccess_T_41, dmiProgramBufferAccessVec[43]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_43 = or(_dmiProgramBufferAccess_T_42, dmiProgramBufferAccessVec[44]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_44 = or(_dmiProgramBufferAccess_T_43, dmiProgramBufferAccessVec[45]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_45 = or(_dmiProgramBufferAccess_T_44, dmiProgramBufferAccessVec[46]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_46 = or(_dmiProgramBufferAccess_T_45, dmiProgramBufferAccessVec[47]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_47 = or(_dmiProgramBufferAccess_T_46, dmiProgramBufferAccessVec[48]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_48 = or(_dmiProgramBufferAccess_T_47, dmiProgramBufferAccessVec[49]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_49 = or(_dmiProgramBufferAccess_T_48, dmiProgramBufferAccessVec[50]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_50 = or(_dmiProgramBufferAccess_T_49, dmiProgramBufferAccessVec[51]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_51 = or(_dmiProgramBufferAccess_T_50, dmiProgramBufferAccessVec[52]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_52 = or(_dmiProgramBufferAccess_T_51, dmiProgramBufferAccessVec[53]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_53 = or(_dmiProgramBufferAccess_T_52, dmiProgramBufferAccessVec[54]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_54 = or(_dmiProgramBufferAccess_T_53, dmiProgramBufferAccessVec[55]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_55 = or(_dmiProgramBufferAccess_T_54, dmiProgramBufferAccessVec[56]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_56 = or(_dmiProgramBufferAccess_T_55, dmiProgramBufferAccessVec[57]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_57 = or(_dmiProgramBufferAccess_T_56, dmiProgramBufferAccessVec[58]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_58 = or(_dmiProgramBufferAccess_T_57, dmiProgramBufferAccessVec[59]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_59 = or(_dmiProgramBufferAccess_T_58, dmiProgramBufferAccessVec[60]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_60 = or(_dmiProgramBufferAccess_T_59, dmiProgramBufferAccessVec[61]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node _dmiProgramBufferAccess_T_61 = or(_dmiProgramBufferAccess_T_60, dmiProgramBufferAccessVec[62]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] node dmiProgramBufferAccess = or(_dmiProgramBufferAccess_T_61, dmiProgramBufferAccessVec[63]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1263:69] wire _autoexecData_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1266:41] connect _autoexecData_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1266:41] connect _autoexecData_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1266:41] wire autoexecData : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1266:33] connect autoexecData, _autoexecData_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1266:33] wire _autoexecProg_WIRE : UInt<1>[16] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:41] connect _autoexecProg_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:41] connect _autoexecProg_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:41] connect _autoexecProg_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:41] connect _autoexecProg_WIRE[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:41] connect _autoexecProg_WIRE[4], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:41] connect _autoexecProg_WIRE[5], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:41] connect _autoexecProg_WIRE[6], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:41] connect _autoexecProg_WIRE[7], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:41] connect _autoexecProg_WIRE[8], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:41] connect _autoexecProg_WIRE[9], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:41] connect _autoexecProg_WIRE[10], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:41] connect _autoexecProg_WIRE[11], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:41] connect _autoexecProg_WIRE[12], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:41] connect _autoexecProg_WIRE[13], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:41] connect _autoexecProg_WIRE[14], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:41] connect _autoexecProg_WIRE[15], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:41] wire autoexecProg : UInt<1>[16] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:33] connect autoexecProg, _autoexecProg_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1267:33] node _T_103 = bits(ABSTRACTAUTOReg.autoexecdata, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1268:54] node _T_104 = bits(ABSTRACTAUTOReg.autoexecdata, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1268:54] node _T_105 = bits(ABSTRACTAUTOReg.autoexecdata, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1268:54] node _T_106 = bits(ABSTRACTAUTOReg.autoexecdata, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1268:54] node _T_107 = bits(ABSTRACTAUTOReg.autoexecdata, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1268:54] node _T_108 = bits(ABSTRACTAUTOReg.autoexecdata, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1268:54] node _T_109 = bits(ABSTRACTAUTOReg.autoexecdata, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1268:54] node _T_110 = bits(ABSTRACTAUTOReg.autoexecdata, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1268:54] node _T_111 = bits(ABSTRACTAUTOReg.autoexecdata, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1268:54] node _T_112 = bits(ABSTRACTAUTOReg.autoexecdata, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1268:54] node _T_113 = bits(ABSTRACTAUTOReg.autoexecdata, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1268:54] node _T_114 = bits(ABSTRACTAUTOReg.autoexecdata, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1268:54] node _autoexecData_0_T = and(dmiAbstractDataAccessVec[0], _T_103) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1268:140] connect autoexecData[0], _autoexecData_0_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1268:105] node _autoexecData_1_T = and(dmiAbstractDataAccessVec[4], _T_104) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1268:140] connect autoexecData[1], _autoexecData_1_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1268:105] node _T_115 = bits(ABSTRACTAUTOReg.autoexecprogbuf, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:57] node _T_116 = bits(ABSTRACTAUTOReg.autoexecprogbuf, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:57] node _T_117 = bits(ABSTRACTAUTOReg.autoexecprogbuf, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:57] node _T_118 = bits(ABSTRACTAUTOReg.autoexecprogbuf, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:57] node _T_119 = bits(ABSTRACTAUTOReg.autoexecprogbuf, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:57] node _T_120 = bits(ABSTRACTAUTOReg.autoexecprogbuf, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:57] node _T_121 = bits(ABSTRACTAUTOReg.autoexecprogbuf, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:57] node _T_122 = bits(ABSTRACTAUTOReg.autoexecprogbuf, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:57] node _T_123 = bits(ABSTRACTAUTOReg.autoexecprogbuf, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:57] node _T_124 = bits(ABSTRACTAUTOReg.autoexecprogbuf, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:57] node _T_125 = bits(ABSTRACTAUTOReg.autoexecprogbuf, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:57] node _T_126 = bits(ABSTRACTAUTOReg.autoexecprogbuf, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:57] node _T_127 = bits(ABSTRACTAUTOReg.autoexecprogbuf, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:57] node _T_128 = bits(ABSTRACTAUTOReg.autoexecprogbuf, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:57] node _T_129 = bits(ABSTRACTAUTOReg.autoexecprogbuf, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:57] node _T_130 = bits(ABSTRACTAUTOReg.autoexecprogbuf, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:57] node _autoexecProg_0_T = and(dmiProgramBufferAccessVec[0], _T_115) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:144] connect autoexecProg[0], _autoexecProg_0_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:108] node _autoexecProg_1_T = and(dmiProgramBufferAccessVec[4], _T_116) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:144] connect autoexecProg[1], _autoexecProg_1_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:108] node _autoexecProg_2_T = and(dmiProgramBufferAccessVec[8], _T_117) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:144] connect autoexecProg[2], _autoexecProg_2_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:108] node _autoexecProg_3_T = and(dmiProgramBufferAccessVec[12], _T_118) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:144] connect autoexecProg[3], _autoexecProg_3_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:108] node _autoexecProg_4_T = and(dmiProgramBufferAccessVec[16], _T_119) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:144] connect autoexecProg[4], _autoexecProg_4_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:108] node _autoexecProg_5_T = and(dmiProgramBufferAccessVec[20], _T_120) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:144] connect autoexecProg[5], _autoexecProg_5_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:108] node _autoexecProg_6_T = and(dmiProgramBufferAccessVec[24], _T_121) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:144] connect autoexecProg[6], _autoexecProg_6_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:108] node _autoexecProg_7_T = and(dmiProgramBufferAccessVec[28], _T_122) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:144] connect autoexecProg[7], _autoexecProg_7_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:108] node _autoexecProg_8_T = and(dmiProgramBufferAccessVec[32], _T_123) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:144] connect autoexecProg[8], _autoexecProg_8_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:108] node _autoexecProg_9_T = and(dmiProgramBufferAccessVec[36], _T_124) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:144] connect autoexecProg[9], _autoexecProg_9_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:108] node _autoexecProg_10_T = and(dmiProgramBufferAccessVec[40], _T_125) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:144] connect autoexecProg[10], _autoexecProg_10_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:108] node _autoexecProg_11_T = and(dmiProgramBufferAccessVec[44], _T_126) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:144] connect autoexecProg[11], _autoexecProg_11_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:108] node _autoexecProg_12_T = and(dmiProgramBufferAccessVec[48], _T_127) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:144] connect autoexecProg[12], _autoexecProg_12_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:108] node _autoexecProg_13_T = and(dmiProgramBufferAccessVec[52], _T_128) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:144] connect autoexecProg[13], _autoexecProg_13_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:108] node _autoexecProg_14_T = and(dmiProgramBufferAccessVec[56], _T_129) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:144] connect autoexecProg[14], _autoexecProg_14_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:108] node _autoexecProg_15_T = and(dmiProgramBufferAccessVec[60], _T_130) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:144] connect autoexecProg[15], _autoexecProg_15_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1269:108] node _autoexec_T = or(autoexecData[0], autoexecData[1]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1271:42] node _autoexec_T_1 = or(autoexecProg[0], autoexecProg[1]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1271:73] node _autoexec_T_2 = or(_autoexec_T_1, autoexecProg[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1271:73] node _autoexec_T_3 = or(_autoexec_T_2, autoexecProg[3]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1271:73] node _autoexec_T_4 = or(_autoexec_T_3, autoexecProg[4]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1271:73] node _autoexec_T_5 = or(_autoexec_T_4, autoexecProg[5]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1271:73] node _autoexec_T_6 = or(_autoexec_T_5, autoexecProg[6]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1271:73] node _autoexec_T_7 = or(_autoexec_T_6, autoexecProg[7]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1271:73] node _autoexec_T_8 = or(_autoexec_T_7, autoexecProg[8]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1271:73] node _autoexec_T_9 = or(_autoexec_T_8, autoexecProg[9]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1271:73] node _autoexec_T_10 = or(_autoexec_T_9, autoexecProg[10]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1271:73] node _autoexec_T_11 = or(_autoexec_T_10, autoexecProg[11]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1271:73] node _autoexec_T_12 = or(_autoexec_T_11, autoexecProg[12]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1271:73] node _autoexec_T_13 = or(_autoexec_T_12, autoexecProg[13]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1271:73] node _autoexec_T_14 = or(_autoexec_T_13, autoexecProg[14]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1271:73] node _autoexec_T_15 = or(_autoexec_T_14, autoexecProg[15]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1271:73] node autoexec = or(_autoexec_T, _autoexec_T_15) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1271:48] wire _COMMANDReset_WIRE : { cmdtype : UInt<8>, control : UInt<24>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1275:45] connect _COMMANDReset_WIRE.control, UInt<24>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1275:45] connect _COMMANDReset_WIRE.cmdtype, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1275:45] wire COMMANDReset : { cmdtype : UInt<8>, control : UInt<24>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1275:32] connect COMMANDReset, _COMMANDReset_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1275:32] reg COMMANDReg : { cmdtype : UInt<8>, control : UInt<24>}, clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1276:25] wire COMMANDWrDataVal : UInt<32> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1278:39] connect COMMANDWrDataVal, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1278:39] wire _COMMANDWrData_WIRE : { cmdtype : UInt<8>, control : UInt<24>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1279:65] wire _COMMANDWrData_WIRE_1 : UInt<32> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1279:65] connect _COMMANDWrData_WIRE_1, COMMANDWrDataVal @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1279:65] node _COMMANDWrData_T = bits(_COMMANDWrData_WIRE_1, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1279:65] connect _COMMANDWrData_WIRE.control, _COMMANDWrData_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1279:65] node _COMMANDWrData_T_1 = bits(_COMMANDWrData_WIRE_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1279:65] connect _COMMANDWrData_WIRE.cmdtype, _COMMANDWrData_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1279:65] wire COMMANDWrData : { cmdtype : UInt<8>, control : UInt<24>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1279:39] connect COMMANDWrData, _COMMANDWrData_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1279:39] wire COMMANDWrEnMaybe : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1280:39] connect COMMANDWrEnMaybe, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1280:39] wire COMMANDWrEnLegal : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1281:39] connect COMMANDWrEnLegal, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1281:39] wire COMMANDRdEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1282:32] connect COMMANDRdEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1282:32] node COMMANDWrEn = and(COMMANDWrEnMaybe, COMMANDWrEnLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1284:40] node _T_131 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1287:11] node _T_132 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1287:27] node _T_133 = or(_T_131, _T_132) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1287:24] when _T_133 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1287:45] connect COMMANDReg, COMMANDReset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1288:18] else : when COMMANDWrEn : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1290:26] connect COMMANDReg, COMMANDWrData @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1291:20] reg abstractDataMem : UInt<8>[8], clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1299:36] wire abstractDataNxt : UInt<8>[8] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1300:41] connect abstractDataNxt, abstractDataMem @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1300:41] reg programBufferMem : UInt<8>[64], clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1305:34] wire programBufferNxt : UInt<8>[64] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1306:39] connect programBufferNxt, programBufferMem @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1306:39] node _T_134 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1314:11] node _T_135 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1314:27] node _T_136 = or(_T_134, _T_135) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1314:24] when _T_136 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1314:45] connect haltedBitRegs, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1315:23] connect resumeReqRegs, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1316:23] else : node _resumeReqRegs_T = not(hartIsInResetSync[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1319:42] node _resumeReqRegs_T_1 = and(resumeReqRegs, _resumeReqRegs_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1319:40] connect resumeReqRegs, _resumeReqRegs_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1319:23] node hartHaltedIdIndex = dshl(UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node hartResumingIdIndex = dshl(UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node hartselIndex = dshl(UInt<1>(0h1), io.innerCtrl.bits.hartsel) @[src/main/scala/chisel3/util/OneHot.scala 58:35] when hartHaltedWrEn : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1324:31] node _haltedBitRegs_T = or(haltedBitRegs, hartHaltedIdIndex) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1326:43] node _haltedBitRegs_T_1 = not(hartIsInResetSync[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1326:66] node _haltedBitRegs_T_2 = and(_haltedBitRegs_T, _haltedBitRegs_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1326:64] connect haltedBitRegs, _haltedBitRegs_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1326:25] else : when hartResumingWrEn : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1327:39] node _haltedBitRegs_T_3 = not(hartResumingIdIndex) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1329:45] node _haltedBitRegs_T_4 = and(haltedBitRegs, _haltedBitRegs_T_3) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1329:43] node _haltedBitRegs_T_5 = not(hartIsInResetSync[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1329:71] node _haltedBitRegs_T_6 = and(_haltedBitRegs_T_4, _haltedBitRegs_T_5) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1329:69] connect haltedBitRegs, _haltedBitRegs_T_6 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1329:25] else : node _haltedBitRegs_T_7 = not(hartIsInResetSync[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1332:44] node _haltedBitRegs_T_8 = and(haltedBitRegs, _haltedBitRegs_T_7) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1332:42] connect haltedBitRegs, _haltedBitRegs_T_8 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1332:25] when hartResumingWrEn : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1335:33] node _resumeReqRegs_T_2 = not(hartResumingIdIndex) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1337:45] node _resumeReqRegs_T_3 = and(resumeReqRegs, _resumeReqRegs_T_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1337:43] node _resumeReqRegs_T_4 = not(hartIsInResetSync[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1337:71] node _resumeReqRegs_T_5 = and(_resumeReqRegs_T_3, _resumeReqRegs_T_4) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1337:69] connect resumeReqRegs, _resumeReqRegs_T_5 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1337:25] when resumereq : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1339:26] node _resumeReqRegs_T_6 = or(resumeReqRegs, hamaskWrSel[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1341:43] node _resumeReqRegs_T_7 = not(hartIsInResetSync[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1341:67] node _resumeReqRegs_T_8 = and(_resumeReqRegs_T_6, _resumeReqRegs_T_7) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1341:65] connect resumeReqRegs, _resumeReqRegs_T_8 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1341:25] when resumereq : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1346:24] node _resumeAcks_T = not(resumeReqRegs) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1348:24] node _resumeAcks_T_1 = not(hamaskWrSel[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1348:41] node _resumeAcks_T_2 = and(_resumeAcks_T, _resumeAcks_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1348:39] connect resumeAcks, _resumeAcks_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1348:20] else : node _resumeAcks_T_3 = not(resumeReqRegs) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1350:23] connect resumeAcks, _resumeAcks_T_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1350:20] wire authRdEnMaybe : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1355:33] connect authRdEnMaybe, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1355:33] wire authWrEnMaybe : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1356:33] connect authWrEnMaybe, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1356:33] wire anyAddressWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 42:34] connect anyAddressWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 42:34] wire anyDataRdEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 43:34] connect anyDataRdEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 43:34] wire anyDataWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 44:34] connect anyDataWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 44:34] reg SBCSFieldsReg : { sbversion : UInt<3>, reserved0 : UInt<6>, sbbusyerror : UInt<1>, sbbusy : UInt<1>, sbreadonaddr : UInt<1>, sbaccess : UInt<3>, sbautoincrement : UInt<1>, sbreadondata : UInt<1>, sberror : UInt<3>, sbasize : UInt<7>, sbaccess128 : UInt<1>, sbaccess64 : UInt<1>, sbaccess32 : UInt<1>, sbaccess16 : UInt<1>, sbaccess8 : UInt<1>}, clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 47:28] wire _SBCSFieldsRegReset_WIRE : { sbversion : UInt<3>, reserved0 : UInt<6>, sbbusyerror : UInt<1>, sbbusy : UInt<1>, sbreadonaddr : UInt<1>, sbaccess : UInt<3>, sbautoincrement : UInt<1>, sbreadondata : UInt<1>, sberror : UInt<3>, sbasize : UInt<7>, sbaccess128 : UInt<1>, sbaccess64 : UInt<1>, sbaccess32 : UInt<1>, sbaccess16 : UInt<1>, sbaccess8 : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 49:51] connect _SBCSFieldsRegReset_WIRE.sbaccess8, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 49:51] connect _SBCSFieldsRegReset_WIRE.sbaccess16, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 49:51] connect _SBCSFieldsRegReset_WIRE.sbaccess32, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 49:51] connect _SBCSFieldsRegReset_WIRE.sbaccess64, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 49:51] connect _SBCSFieldsRegReset_WIRE.sbaccess128, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 49:51] connect _SBCSFieldsRegReset_WIRE.sbasize, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 49:51] connect _SBCSFieldsRegReset_WIRE.sberror, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 49:51] connect _SBCSFieldsRegReset_WIRE.sbreadondata, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 49:51] connect _SBCSFieldsRegReset_WIRE.sbautoincrement, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 49:51] connect _SBCSFieldsRegReset_WIRE.sbaccess, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 49:51] connect _SBCSFieldsRegReset_WIRE.sbreadonaddr, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 49:51] connect _SBCSFieldsRegReset_WIRE.sbbusy, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 49:51] connect _SBCSFieldsRegReset_WIRE.sbbusyerror, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 49:51] connect _SBCSFieldsRegReset_WIRE.reserved0, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 49:51] connect _SBCSFieldsRegReset_WIRE.sbversion, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 49:51] wire SBCSFieldsRegReset : { sbversion : UInt<3>, reserved0 : UInt<6>, sbbusyerror : UInt<1>, sbbusy : UInt<1>, sbreadonaddr : UInt<1>, sbaccess : UInt<3>, sbautoincrement : UInt<1>, sbreadondata : UInt<1>, sberror : UInt<3>, sbasize : UInt<7>, sbaccess128 : UInt<1>, sbaccess64 : UInt<1>, sbaccess32 : UInt<1>, sbaccess16 : UInt<1>, sbaccess8 : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 49:38] connect SBCSFieldsRegReset, _SBCSFieldsRegReset_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 49:38] connect SBCSFieldsRegReset.sbversion, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 50:36] node _SBCSFieldsRegReset_sbbusy_T = neq(sb2tlOpt.io.sbStateOut, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 51:67] connect SBCSFieldsRegReset.sbbusy, _SBCSFieldsRegReset_sbbusy_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 51:36] connect SBCSFieldsRegReset.sbaccess, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 52:36] connect SBCSFieldsRegReset.sbasize, UInt<6>(0h20) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 53:36] connect SBCSFieldsRegReset.sbaccess128, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 54:36] connect SBCSFieldsRegReset.sbaccess64, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 55:36] connect SBCSFieldsRegReset.sbaccess32, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 56:36] connect SBCSFieldsRegReset.sbaccess16, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 57:36] connect SBCSFieldsRegReset.sbaccess8, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 58:36] wire _SBCSRdData_WIRE : { sbversion : UInt<3>, reserved0 : UInt<6>, sbbusyerror : UInt<1>, sbbusy : UInt<1>, sbreadonaddr : UInt<1>, sbaccess : UInt<3>, sbautoincrement : UInt<1>, sbreadondata : UInt<1>, sberror : UInt<3>, sbasize : UInt<7>, sbaccess128 : UInt<1>, sbaccess64 : UInt<1>, sbaccess32 : UInt<1>, sbaccess16 : UInt<1>, sbaccess8 : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 60:51] connect _SBCSRdData_WIRE.sbaccess8, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 60:51] connect _SBCSRdData_WIRE.sbaccess16, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 60:51] connect _SBCSRdData_WIRE.sbaccess32, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 60:51] connect _SBCSRdData_WIRE.sbaccess64, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 60:51] connect _SBCSRdData_WIRE.sbaccess128, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 60:51] connect _SBCSRdData_WIRE.sbasize, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 60:51] connect _SBCSRdData_WIRE.sberror, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 60:51] connect _SBCSRdData_WIRE.sbreadondata, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 60:51] connect _SBCSRdData_WIRE.sbautoincrement, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 60:51] connect _SBCSRdData_WIRE.sbaccess, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 60:51] connect _SBCSRdData_WIRE.sbreadonaddr, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 60:51] connect _SBCSRdData_WIRE.sbbusy, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 60:51] connect _SBCSRdData_WIRE.sbbusyerror, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 60:51] connect _SBCSRdData_WIRE.reserved0, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 60:51] connect _SBCSRdData_WIRE.sbversion, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 60:51] wire SBCSRdData : { sbversion : UInt<3>, reserved0 : UInt<6>, sbbusyerror : UInt<1>, sbbusy : UInt<1>, sbreadonaddr : UInt<1>, sbaccess : UInt<3>, sbautoincrement : UInt<1>, sbreadondata : UInt<1>, sberror : UInt<3>, sbasize : UInt<7>, sbaccess128 : UInt<1>, sbaccess64 : UInt<1>, sbaccess32 : UInt<1>, sbaccess16 : UInt<1>, sbaccess8 : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 60:38] connect SBCSRdData, _SBCSRdData_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 60:38] wire SBCSWrDataVal : UInt<32> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 62:38] connect SBCSWrDataVal, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 62:38] wire _SBCSWrData_WIRE : { sbversion : UInt<3>, reserved0 : UInt<6>, sbbusyerror : UInt<1>, sbbusy : UInt<1>, sbreadonaddr : UInt<1>, sbaccess : UInt<3>, sbautoincrement : UInt<1>, sbreadondata : UInt<1>, sberror : UInt<3>, sbasize : UInt<7>, sbaccess128 : UInt<1>, sbaccess64 : UInt<1>, sbaccess32 : UInt<1>, sbaccess16 : UInt<1>, sbaccess8 : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] wire _SBCSWrData_WIRE_1 : UInt<32> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] connect _SBCSWrData_WIRE_1, SBCSWrDataVal @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] node _SBCSWrData_T = bits(_SBCSWrData_WIRE_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] connect _SBCSWrData_WIRE.sbaccess8, _SBCSWrData_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] node _SBCSWrData_T_1 = bits(_SBCSWrData_WIRE_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] connect _SBCSWrData_WIRE.sbaccess16, _SBCSWrData_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] node _SBCSWrData_T_2 = bits(_SBCSWrData_WIRE_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] connect _SBCSWrData_WIRE.sbaccess32, _SBCSWrData_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] node _SBCSWrData_T_3 = bits(_SBCSWrData_WIRE_1, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] connect _SBCSWrData_WIRE.sbaccess64, _SBCSWrData_T_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] node _SBCSWrData_T_4 = bits(_SBCSWrData_WIRE_1, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] connect _SBCSWrData_WIRE.sbaccess128, _SBCSWrData_T_4 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] node _SBCSWrData_T_5 = bits(_SBCSWrData_WIRE_1, 11, 5) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] connect _SBCSWrData_WIRE.sbasize, _SBCSWrData_T_5 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] node _SBCSWrData_T_6 = bits(_SBCSWrData_WIRE_1, 14, 12) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] connect _SBCSWrData_WIRE.sberror, _SBCSWrData_T_6 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] node _SBCSWrData_T_7 = bits(_SBCSWrData_WIRE_1, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] connect _SBCSWrData_WIRE.sbreadondata, _SBCSWrData_T_7 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] node _SBCSWrData_T_8 = bits(_SBCSWrData_WIRE_1, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] connect _SBCSWrData_WIRE.sbautoincrement, _SBCSWrData_T_8 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] node _SBCSWrData_T_9 = bits(_SBCSWrData_WIRE_1, 19, 17) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] connect _SBCSWrData_WIRE.sbaccess, _SBCSWrData_T_9 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] node _SBCSWrData_T_10 = bits(_SBCSWrData_WIRE_1, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] connect _SBCSWrData_WIRE.sbreadonaddr, _SBCSWrData_T_10 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] node _SBCSWrData_T_11 = bits(_SBCSWrData_WIRE_1, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] connect _SBCSWrData_WIRE.sbbusy, _SBCSWrData_T_11 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] node _SBCSWrData_T_12 = bits(_SBCSWrData_WIRE_1, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] connect _SBCSWrData_WIRE.sbbusyerror, _SBCSWrData_T_12 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] node _SBCSWrData_T_13 = bits(_SBCSWrData_WIRE_1, 28, 23) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] connect _SBCSWrData_WIRE.reserved0, _SBCSWrData_T_13 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] node _SBCSWrData_T_14 = bits(_SBCSWrData_WIRE_1, 31, 29) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] connect _SBCSWrData_WIRE.sbversion, _SBCSWrData_T_14 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:61] wire SBCSWrData : { sbversion : UInt<3>, reserved0 : UInt<6>, sbbusyerror : UInt<1>, sbbusy : UInt<1>, sbreadonaddr : UInt<1>, sbaccess : UInt<3>, sbautoincrement : UInt<1>, sbreadondata : UInt<1>, sberror : UInt<3>, sbasize : UInt<7>, sbaccess128 : UInt<1>, sbaccess64 : UInt<1>, sbaccess32 : UInt<1>, sbaccess16 : UInt<1>, sbaccess8 : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:38] connect SBCSWrData, _SBCSWrData_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 63:38] wire sberrorWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 65:38] connect sberrorWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 65:38] wire sbreadondataWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 66:38] connect sbreadondataWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 66:38] wire sbautoincrementWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 67:38] connect sbautoincrementWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 67:38] wire sbaccessWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 68:38] connect sbaccessWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 68:38] wire sbreadonaddrWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 69:38] connect sbreadonaddrWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 69:38] wire sbbusyerrorWrEn : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 70:38] connect sbbusyerrorWrEn, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 70:38] reg SBADDRESSFieldsReg : UInt<32>[4], clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 104:33] wire _SBADDRESSWrData_WIRE : UInt<32>[4] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 106:46] connect _SBADDRESSWrData_WIRE[0], UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 106:46] connect _SBADDRESSWrData_WIRE[1], UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 106:46] connect _SBADDRESSWrData_WIRE[2], UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 106:46] connect _SBADDRESSWrData_WIRE[3], UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 106:46] wire SBADDRESSWrData : UInt<32>[4] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 106:38] connect SBADDRESSWrData, _SBADDRESSWrData_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 106:38] wire _SBADDRESSRdEn_WIRE : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 107:46] connect _SBADDRESSRdEn_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 107:46] connect _SBADDRESSRdEn_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 107:46] connect _SBADDRESSRdEn_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 107:46] connect _SBADDRESSRdEn_WIRE[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 107:46] wire SBADDRESSRdEn : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 107:38] connect SBADDRESSRdEn, _SBADDRESSRdEn_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 107:38] wire _SBADDRESSWrEn_WIRE : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 108:46] connect _SBADDRESSWrEn_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 108:46] connect _SBADDRESSWrEn_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 108:46] connect _SBADDRESSWrEn_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 108:46] connect _SBADDRESSWrEn_WIRE[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 108:46] wire SBADDRESSWrEn : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 108:38] connect SBADDRESSWrEn, _SBADDRESSWrEn_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 108:38] wire autoIncrementedAddr : UInt<128> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 110:39] connect autoIncrementedAddr, UInt<128>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 110:39] node autoIncrementedAddr_lo = cat(SBADDRESSFieldsReg[1], SBADDRESSFieldsReg[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 111:31] node autoIncrementedAddr_hi = cat(SBADDRESSFieldsReg[3], SBADDRESSFieldsReg[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 111:31] node _autoIncrementedAddr_T = cat(autoIncrementedAddr_hi, autoIncrementedAddr_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 111:31] node _autoIncrementedAddr_T_1 = dshl(UInt<1>(0h1), SBCSFieldsReg.sbaccess) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 111:67] node _autoIncrementedAddr_T_2 = add(_autoIncrementedAddr_T, _autoIncrementedAddr_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 111:60] node _autoIncrementedAddr_T_3 = tail(_autoIncrementedAddr_T_2, 1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 111:60] connect autoIncrementedAddr, _autoIncrementedAddr_T_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 111:25] node _T_137 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 116:15] node _T_138 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 116:28] node _T_139 = or(_T_137, _T_138) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 116:25] when _T_139 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 116:46] connect SBADDRESSFieldsReg[0], UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 117:13] else : node _SBADDRESSFieldsReg_0_T = eq(SBCSRdData.sberror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 119:40] node _SBADDRESSFieldsReg_0_T_1 = and(SBADDRESSWrEn[0], _SBADDRESSFieldsReg_0_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 119:37] node _SBADDRESSFieldsReg_0_T_2 = eq(SBCSFieldsReg.sbbusy, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 119:63] node _SBADDRESSFieldsReg_0_T_3 = and(_SBADDRESSFieldsReg_0_T_1, _SBADDRESSFieldsReg_0_T_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 119:60] node _SBADDRESSFieldsReg_0_T_4 = eq(SBCSFieldsReg.sbbusyerror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 119:88] node _SBADDRESSFieldsReg_0_T_5 = and(_SBADDRESSFieldsReg_0_T_3, _SBADDRESSFieldsReg_0_T_4) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 119:85] node _SBADDRESSFieldsReg_0_T_6 = or(sb2tlOpt.io.rdDone, sb2tlOpt.io.wrDone) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 120:44] node _SBADDRESSFieldsReg_0_T_7 = and(_SBADDRESSFieldsReg_0_T_6, SBCSFieldsReg.sbautoincrement) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 120:71] node _SBADDRESSFieldsReg_0_T_8 = bits(autoIncrementedAddr, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 120:124] node _SBADDRESSFieldsReg_0_T_9 = mux(_SBADDRESSFieldsReg_0_T_7, _SBADDRESSFieldsReg_0_T_8, SBADDRESSFieldsReg[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 120:19] node _SBADDRESSFieldsReg_0_T_10 = mux(_SBADDRESSFieldsReg_0_T_5, SBADDRESSWrData[0], _SBADDRESSFieldsReg_0_T_9) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 119:19] connect SBADDRESSFieldsReg[0], _SBADDRESSFieldsReg_0_T_10 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 119:13] invalidate SBADDRESSFieldsReg[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 126:11] invalidate SBADDRESSFieldsReg[2] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 126:11] invalidate SBADDRESSFieldsReg[3] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 126:11] node sb2tlOpt_io_addrIn_hi = cat(SBADDRESSFieldsReg[3], SBADDRESSFieldsReg[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 132:14] node _sb2tlOpt_io_addrIn_T = cat(sb2tlOpt_io_addrIn_hi, SBADDRESSFieldsReg[1]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 132:14] node _sb2tlOpt_io_addrIn_T_1 = cat(_sb2tlOpt_io_addrIn_T, SBADDRESSWrData[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 132:10] node sb2tlOpt_io_addrIn_lo = cat(SBADDRESSFieldsReg[1], SBADDRESSFieldsReg[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 133:10] node sb2tlOpt_io_addrIn_hi_1 = cat(SBADDRESSFieldsReg[3], SBADDRESSFieldsReg[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 133:10] node _sb2tlOpt_io_addrIn_T_2 = cat(sb2tlOpt_io_addrIn_hi_1, sb2tlOpt_io_addrIn_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 133:10] node _sb2tlOpt_io_addrIn_T_3 = mux(SBADDRESSWrEn[0], _sb2tlOpt_io_addrIn_T_1, _sb2tlOpt_io_addrIn_T_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 131:34] connect sb2tlOpt.io.addrIn, _sb2tlOpt_io_addrIn_T_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 131:28] node _anyAddressWrEn_T = or(SBADDRESSWrEn[0], SBADDRESSWrEn[1]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 134:54] node _anyAddressWrEn_T_1 = or(_anyAddressWrEn_T, SBADDRESSWrEn[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 134:54] node _anyAddressWrEn_T_2 = or(_anyAddressWrEn_T_1, SBADDRESSWrEn[3]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 134:54] connect anyAddressWrEn, _anyAddressWrEn_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 134:28] reg SBDATAFieldsReg : UInt<8>[4][4], clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 143:30] wire _SBDATARdData_WIRE : UInt<32>[4] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 145:43] connect _SBDATARdData_WIRE[0], UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 145:43] connect _SBDATARdData_WIRE[1], UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 145:43] connect _SBDATARdData_WIRE[2], UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 145:43] connect _SBDATARdData_WIRE[3], UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 145:43] wire SBDATARdData : UInt<32>[4] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 145:35] connect SBDATARdData, _SBDATARdData_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 145:35] wire _SBDATAWrData_WIRE : UInt<32>[4] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 147:43] connect _SBDATAWrData_WIRE[0], UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 147:43] connect _SBDATAWrData_WIRE[1], UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 147:43] connect _SBDATAWrData_WIRE[2], UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 147:43] connect _SBDATAWrData_WIRE[3], UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 147:43] wire SBDATAWrData : UInt<32>[4] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 147:35] connect SBDATAWrData, _SBDATAWrData_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 147:35] wire _SBDATARdEn_WIRE : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 149:43] connect _SBDATARdEn_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 149:43] connect _SBDATARdEn_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 149:43] connect _SBDATARdEn_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 149:43] connect _SBDATARdEn_WIRE[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 149:43] wire SBDATARdEn : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 149:35] connect SBDATARdEn, _SBDATARdEn_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 149:35] wire _SBDATAWrEn_WIRE : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 150:43] connect _SBDATAWrEn_WIRE[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 150:43] connect _SBDATAWrEn_WIRE[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 150:43] connect _SBDATAWrEn_WIRE[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 150:43] connect _SBDATAWrEn_WIRE[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 150:43] wire SBDATAWrEn : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 150:35] connect SBDATAWrEn, _SBDATAWrEn_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 150:35] node _T_140 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:17] node _T_141 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:30] node _T_142 = or(_T_140, _T_141) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:27] when _T_142 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:48] connect SBDATAFieldsReg[0][0], UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 158:18] else : node _SBDATAFieldsReg_0_0_T = eq(SBCSFieldsReg.sbbusy, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:42] node _SBDATAFieldsReg_0_0_T_1 = and(SBDATAWrEn[0], _SBDATAFieldsReg_0_0_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:39] node _SBDATAFieldsReg_0_0_T_2 = eq(SBCSFieldsReg.sbbusyerror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:67] node _SBDATAFieldsReg_0_0_T_3 = and(_SBDATAFieldsReg_0_0_T_1, _SBDATAFieldsReg_0_0_T_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:64] node _SBDATAFieldsReg_0_0_T_4 = eq(SBCSRdData.sberror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:97] node _SBDATAFieldsReg_0_0_T_5 = and(_SBDATAFieldsReg_0_0_T_3, _SBDATAFieldsReg_0_0_T_4) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:94] node _SBDATAFieldsReg_0_0_T_6 = bits(SBDATAWrData[0], 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:133] node _SBDATAFieldsReg_0_0_T_7 = mux(sb2tlOpt.io.rdLoad[0], sb2tlOpt.io.dataOut, SBDATAFieldsReg[0][0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 161:24] node _SBDATAFieldsReg_0_0_T_8 = mux(_SBDATAFieldsReg_0_0_T_5, _SBDATAFieldsReg_0_0_T_6, _SBDATAFieldsReg_0_0_T_7) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:24] connect SBDATAFieldsReg[0][0], _SBDATAFieldsReg_0_0_T_8 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:18] node _T_143 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:17] node _T_144 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:30] node _T_145 = or(_T_143, _T_144) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:27] when _T_145 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:48] connect SBDATAFieldsReg[0][1], UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 158:18] else : node _SBDATAFieldsReg_0_1_T = eq(SBCSFieldsReg.sbbusy, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:42] node _SBDATAFieldsReg_0_1_T_1 = and(SBDATAWrEn[0], _SBDATAFieldsReg_0_1_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:39] node _SBDATAFieldsReg_0_1_T_2 = eq(SBCSFieldsReg.sbbusyerror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:67] node _SBDATAFieldsReg_0_1_T_3 = and(_SBDATAFieldsReg_0_1_T_1, _SBDATAFieldsReg_0_1_T_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:64] node _SBDATAFieldsReg_0_1_T_4 = eq(SBCSRdData.sberror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:97] node _SBDATAFieldsReg_0_1_T_5 = and(_SBDATAFieldsReg_0_1_T_3, _SBDATAFieldsReg_0_1_T_4) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:94] node _SBDATAFieldsReg_0_1_T_6 = bits(SBDATAWrData[0], 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:133] node _SBDATAFieldsReg_0_1_T_7 = mux(sb2tlOpt.io.rdLoad[1], sb2tlOpt.io.dataOut, SBDATAFieldsReg[0][1]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 161:24] node _SBDATAFieldsReg_0_1_T_8 = mux(_SBDATAFieldsReg_0_1_T_5, _SBDATAFieldsReg_0_1_T_6, _SBDATAFieldsReg_0_1_T_7) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:24] connect SBDATAFieldsReg[0][1], _SBDATAFieldsReg_0_1_T_8 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:18] node _T_146 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:17] node _T_147 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:30] node _T_148 = or(_T_146, _T_147) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:27] when _T_148 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:48] connect SBDATAFieldsReg[0][2], UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 158:18] else : node _SBDATAFieldsReg_0_2_T = eq(SBCSFieldsReg.sbbusy, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:42] node _SBDATAFieldsReg_0_2_T_1 = and(SBDATAWrEn[0], _SBDATAFieldsReg_0_2_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:39] node _SBDATAFieldsReg_0_2_T_2 = eq(SBCSFieldsReg.sbbusyerror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:67] node _SBDATAFieldsReg_0_2_T_3 = and(_SBDATAFieldsReg_0_2_T_1, _SBDATAFieldsReg_0_2_T_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:64] node _SBDATAFieldsReg_0_2_T_4 = eq(SBCSRdData.sberror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:97] node _SBDATAFieldsReg_0_2_T_5 = and(_SBDATAFieldsReg_0_2_T_3, _SBDATAFieldsReg_0_2_T_4) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:94] node _SBDATAFieldsReg_0_2_T_6 = bits(SBDATAWrData[0], 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:133] node _SBDATAFieldsReg_0_2_T_7 = mux(sb2tlOpt.io.rdLoad[2], sb2tlOpt.io.dataOut, SBDATAFieldsReg[0][2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 161:24] node _SBDATAFieldsReg_0_2_T_8 = mux(_SBDATAFieldsReg_0_2_T_5, _SBDATAFieldsReg_0_2_T_6, _SBDATAFieldsReg_0_2_T_7) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:24] connect SBDATAFieldsReg[0][2], _SBDATAFieldsReg_0_2_T_8 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:18] node _T_149 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:17] node _T_150 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:30] node _T_151 = or(_T_149, _T_150) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:27] when _T_151 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:48] connect SBDATAFieldsReg[0][3], UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 158:18] else : node _SBDATAFieldsReg_0_3_T = eq(SBCSFieldsReg.sbbusy, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:42] node _SBDATAFieldsReg_0_3_T_1 = and(SBDATAWrEn[0], _SBDATAFieldsReg_0_3_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:39] node _SBDATAFieldsReg_0_3_T_2 = eq(SBCSFieldsReg.sbbusyerror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:67] node _SBDATAFieldsReg_0_3_T_3 = and(_SBDATAFieldsReg_0_3_T_1, _SBDATAFieldsReg_0_3_T_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:64] node _SBDATAFieldsReg_0_3_T_4 = eq(SBCSRdData.sberror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:97] node _SBDATAFieldsReg_0_3_T_5 = and(_SBDATAFieldsReg_0_3_T_3, _SBDATAFieldsReg_0_3_T_4) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:94] node _SBDATAFieldsReg_0_3_T_6 = bits(SBDATAWrData[0], 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:133] node _SBDATAFieldsReg_0_3_T_7 = mux(sb2tlOpt.io.rdLoad[3], sb2tlOpt.io.dataOut, SBDATAFieldsReg[0][3]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 161:24] node _SBDATAFieldsReg_0_3_T_8 = mux(_SBDATAFieldsReg_0_3_T_5, _SBDATAFieldsReg_0_3_T_6, _SBDATAFieldsReg_0_3_T_7) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:24] connect SBDATAFieldsReg[0][3], _SBDATAFieldsReg_0_3_T_8 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:18] node SBDATARdData_0_lo = cat(SBDATAFieldsReg[0][1], SBDATAFieldsReg[0][0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 165:31] node SBDATARdData_0_hi = cat(SBDATAFieldsReg[0][3], SBDATAFieldsReg[0][2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 165:31] node _SBDATARdData_0_T = cat(SBDATARdData_0_hi, SBDATARdData_0_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 165:31] connect SBDATARdData[0], _SBDATARdData_0_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 165:25] node _T_152 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:17] node _T_153 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:30] node _T_154 = or(_T_152, _T_153) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:27] when _T_154 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:48] connect SBDATAFieldsReg[1][0], UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 158:18] else : node _SBDATAFieldsReg_1_0_T = eq(SBCSFieldsReg.sbbusy, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:42] node _SBDATAFieldsReg_1_0_T_1 = and(SBDATAWrEn[1], _SBDATAFieldsReg_1_0_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:39] node _SBDATAFieldsReg_1_0_T_2 = eq(SBCSFieldsReg.sbbusyerror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:67] node _SBDATAFieldsReg_1_0_T_3 = and(_SBDATAFieldsReg_1_0_T_1, _SBDATAFieldsReg_1_0_T_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:64] node _SBDATAFieldsReg_1_0_T_4 = eq(SBCSRdData.sberror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:97] node _SBDATAFieldsReg_1_0_T_5 = and(_SBDATAFieldsReg_1_0_T_3, _SBDATAFieldsReg_1_0_T_4) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:94] node _SBDATAFieldsReg_1_0_T_6 = bits(SBDATAWrData[1], 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:133] node _SBDATAFieldsReg_1_0_T_7 = mux(sb2tlOpt.io.rdLoad[4], sb2tlOpt.io.dataOut, SBDATAFieldsReg[1][0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 161:24] node _SBDATAFieldsReg_1_0_T_8 = mux(_SBDATAFieldsReg_1_0_T_5, _SBDATAFieldsReg_1_0_T_6, _SBDATAFieldsReg_1_0_T_7) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:24] connect SBDATAFieldsReg[1][0], _SBDATAFieldsReg_1_0_T_8 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:18] node _T_155 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:17] node _T_156 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:30] node _T_157 = or(_T_155, _T_156) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:27] when _T_157 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:48] connect SBDATAFieldsReg[1][1], UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 158:18] else : node _SBDATAFieldsReg_1_1_T = eq(SBCSFieldsReg.sbbusy, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:42] node _SBDATAFieldsReg_1_1_T_1 = and(SBDATAWrEn[1], _SBDATAFieldsReg_1_1_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:39] node _SBDATAFieldsReg_1_1_T_2 = eq(SBCSFieldsReg.sbbusyerror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:67] node _SBDATAFieldsReg_1_1_T_3 = and(_SBDATAFieldsReg_1_1_T_1, _SBDATAFieldsReg_1_1_T_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:64] node _SBDATAFieldsReg_1_1_T_4 = eq(SBCSRdData.sberror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:97] node _SBDATAFieldsReg_1_1_T_5 = and(_SBDATAFieldsReg_1_1_T_3, _SBDATAFieldsReg_1_1_T_4) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:94] node _SBDATAFieldsReg_1_1_T_6 = bits(SBDATAWrData[1], 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:133] node _SBDATAFieldsReg_1_1_T_7 = mux(sb2tlOpt.io.rdLoad[5], sb2tlOpt.io.dataOut, SBDATAFieldsReg[1][1]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 161:24] node _SBDATAFieldsReg_1_1_T_8 = mux(_SBDATAFieldsReg_1_1_T_5, _SBDATAFieldsReg_1_1_T_6, _SBDATAFieldsReg_1_1_T_7) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:24] connect SBDATAFieldsReg[1][1], _SBDATAFieldsReg_1_1_T_8 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:18] node _T_158 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:17] node _T_159 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:30] node _T_160 = or(_T_158, _T_159) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:27] when _T_160 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:48] connect SBDATAFieldsReg[1][2], UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 158:18] else : node _SBDATAFieldsReg_1_2_T = eq(SBCSFieldsReg.sbbusy, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:42] node _SBDATAFieldsReg_1_2_T_1 = and(SBDATAWrEn[1], _SBDATAFieldsReg_1_2_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:39] node _SBDATAFieldsReg_1_2_T_2 = eq(SBCSFieldsReg.sbbusyerror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:67] node _SBDATAFieldsReg_1_2_T_3 = and(_SBDATAFieldsReg_1_2_T_1, _SBDATAFieldsReg_1_2_T_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:64] node _SBDATAFieldsReg_1_2_T_4 = eq(SBCSRdData.sberror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:97] node _SBDATAFieldsReg_1_2_T_5 = and(_SBDATAFieldsReg_1_2_T_3, _SBDATAFieldsReg_1_2_T_4) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:94] node _SBDATAFieldsReg_1_2_T_6 = bits(SBDATAWrData[1], 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:133] node _SBDATAFieldsReg_1_2_T_7 = mux(sb2tlOpt.io.rdLoad[6], sb2tlOpt.io.dataOut, SBDATAFieldsReg[1][2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 161:24] node _SBDATAFieldsReg_1_2_T_8 = mux(_SBDATAFieldsReg_1_2_T_5, _SBDATAFieldsReg_1_2_T_6, _SBDATAFieldsReg_1_2_T_7) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:24] connect SBDATAFieldsReg[1][2], _SBDATAFieldsReg_1_2_T_8 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:18] node _T_161 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:17] node _T_162 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:30] node _T_163 = or(_T_161, _T_162) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:27] when _T_163 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 157:48] connect SBDATAFieldsReg[1][3], UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 158:18] else : node _SBDATAFieldsReg_1_3_T = eq(SBCSFieldsReg.sbbusy, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:42] node _SBDATAFieldsReg_1_3_T_1 = and(SBDATAWrEn[1], _SBDATAFieldsReg_1_3_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:39] node _SBDATAFieldsReg_1_3_T_2 = eq(SBCSFieldsReg.sbbusyerror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:67] node _SBDATAFieldsReg_1_3_T_3 = and(_SBDATAFieldsReg_1_3_T_1, _SBDATAFieldsReg_1_3_T_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:64] node _SBDATAFieldsReg_1_3_T_4 = eq(SBCSRdData.sberror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:97] node _SBDATAFieldsReg_1_3_T_5 = and(_SBDATAFieldsReg_1_3_T_3, _SBDATAFieldsReg_1_3_T_4) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:94] node _SBDATAFieldsReg_1_3_T_6 = bits(SBDATAWrData[1], 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:133] node _SBDATAFieldsReg_1_3_T_7 = mux(sb2tlOpt.io.rdLoad[7], sb2tlOpt.io.dataOut, SBDATAFieldsReg[1][3]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 161:24] node _SBDATAFieldsReg_1_3_T_8 = mux(_SBDATAFieldsReg_1_3_T_5, _SBDATAFieldsReg_1_3_T_6, _SBDATAFieldsReg_1_3_T_7) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:24] connect SBDATAFieldsReg[1][3], _SBDATAFieldsReg_1_3_T_8 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 160:18] node SBDATARdData_1_lo = cat(SBDATAFieldsReg[1][1], SBDATAFieldsReg[1][0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 165:31] node SBDATARdData_1_hi = cat(SBDATAFieldsReg[1][3], SBDATAFieldsReg[1][2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 165:31] node _SBDATARdData_1_T = cat(SBDATARdData_1_hi, SBDATARdData_1_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 165:31] connect SBDATARdData[1], _SBDATARdData_1_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 165:25] invalidate SBDATAFieldsReg[2][0] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 170:34] invalidate SBDATAFieldsReg[2][1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 170:34] invalidate SBDATAFieldsReg[2][2] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 170:34] invalidate SBDATAFieldsReg[2][3] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 170:34] invalidate SBDATAFieldsReg[3][0] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 170:34] invalidate SBDATAFieldsReg[3][1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 170:34] invalidate SBDATAFieldsReg[3][2] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 170:34] invalidate SBDATAFieldsReg[3][3] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 170:34] node sb2tlOpt_io_dataIn_lo = cat(SBDATAWrData[1], SBDATAWrData[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:59] node sb2tlOpt_io_dataIn_hi = cat(SBDATAWrData[3], SBDATAWrData[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:59] node _sb2tlOpt_io_dataIn_T = cat(sb2tlOpt_io_dataIn_hi, sb2tlOpt_io_dataIn_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:59] node sb2tlOpt_io_dataIn_lo_lo_lo = cat(SBDATAFieldsReg[0][1], SBDATAFieldsReg[0][0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:85] node sb2tlOpt_io_dataIn_lo_lo_hi = cat(SBDATAFieldsReg[0][3], SBDATAFieldsReg[0][2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:85] node sb2tlOpt_io_dataIn_lo_lo = cat(sb2tlOpt_io_dataIn_lo_lo_hi, sb2tlOpt_io_dataIn_lo_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:85] node sb2tlOpt_io_dataIn_lo_hi_lo = cat(SBDATAFieldsReg[1][1], SBDATAFieldsReg[1][0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:85] node sb2tlOpt_io_dataIn_lo_hi_hi = cat(SBDATAFieldsReg[1][3], SBDATAFieldsReg[1][2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:85] node sb2tlOpt_io_dataIn_lo_hi = cat(sb2tlOpt_io_dataIn_lo_hi_hi, sb2tlOpt_io_dataIn_lo_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:85] node sb2tlOpt_io_dataIn_lo_1 = cat(sb2tlOpt_io_dataIn_lo_hi, sb2tlOpt_io_dataIn_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:85] node sb2tlOpt_io_dataIn_hi_lo_lo = cat(SBDATAFieldsReg[2][1], SBDATAFieldsReg[2][0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:85] node sb2tlOpt_io_dataIn_hi_lo_hi = cat(SBDATAFieldsReg[2][3], SBDATAFieldsReg[2][2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:85] node sb2tlOpt_io_dataIn_hi_lo = cat(sb2tlOpt_io_dataIn_hi_lo_hi, sb2tlOpt_io_dataIn_hi_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:85] node sb2tlOpt_io_dataIn_hi_hi_lo = cat(SBDATAFieldsReg[3][1], SBDATAFieldsReg[3][0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:85] node sb2tlOpt_io_dataIn_hi_hi_hi = cat(SBDATAFieldsReg[3][3], SBDATAFieldsReg[3][2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:85] node sb2tlOpt_io_dataIn_hi_hi = cat(sb2tlOpt_io_dataIn_hi_hi_hi, sb2tlOpt_io_dataIn_hi_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:85] node sb2tlOpt_io_dataIn_hi_1 = cat(sb2tlOpt_io_dataIn_hi_hi, sb2tlOpt_io_dataIn_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:85] node _sb2tlOpt_io_dataIn_T_1 = cat(sb2tlOpt_io_dataIn_hi_1, sb2tlOpt_io_dataIn_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:85] node _sb2tlOpt_io_dataIn_T_2 = mux(sb2tlOpt.io.wrEn, _sb2tlOpt_io_dataIn_T, _sb2tlOpt_io_dataIn_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:34] connect sb2tlOpt.io.dataIn, _sb2tlOpt_io_dataIn_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 175:28] node _anyDataRdEn_T = or(SBDATARdEn[0], SBDATARdEn[1]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 176:51] node _anyDataRdEn_T_1 = or(_anyDataRdEn_T, SBDATARdEn[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 176:51] node _anyDataRdEn_T_2 = or(_anyDataRdEn_T_1, SBDATARdEn[3]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 176:51] connect anyDataRdEn, _anyDataRdEn_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 176:28] node _anyDataWrEn_T = or(SBDATAWrEn[0], SBDATAWrEn[1]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 177:51] node _anyDataWrEn_T_1 = or(_anyDataWrEn_T, SBDATAWrEn[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 177:51] node _anyDataWrEn_T_2 = or(_anyDataWrEn_T_1, SBDATAWrEn[3]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 177:51] connect anyDataWrEn, _anyDataWrEn_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 177:28] node _tryRdEn_T = and(SBADDRESSWrEn[0], SBCSFieldsReg.sbreadonaddr) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 180:37] node _tryRdEn_T_1 = and(SBDATARdEn[0], SBCSFieldsReg.sbreadondata) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 180:86] node tryRdEn = or(_tryRdEn_T, _tryRdEn_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 180:68] node _sbAccessError_T = eq(SBCSFieldsReg.sbaccess, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 182:49] node _sbAccessError_T_1 = neq(SBCSFieldsReg.sbaccess8, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 182:88] node _sbAccessError_T_2 = and(_sbAccessError_T, _sbAccessError_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 182:58] node _sbAccessError_T_3 = eq(SBCSFieldsReg.sbaccess, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 183:49] node _sbAccessError_T_4 = neq(SBCSFieldsReg.sbaccess16, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 183:88] node _sbAccessError_T_5 = and(_sbAccessError_T_3, _sbAccessError_T_4) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 183:58] node _sbAccessError_T_6 = or(_sbAccessError_T_2, _sbAccessError_T_5) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 182:97] node _sbAccessError_T_7 = eq(SBCSFieldsReg.sbaccess, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 184:49] node _sbAccessError_T_8 = neq(SBCSFieldsReg.sbaccess32, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 184:88] node _sbAccessError_T_9 = and(_sbAccessError_T_7, _sbAccessError_T_8) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 184:58] node _sbAccessError_T_10 = or(_sbAccessError_T_6, _sbAccessError_T_9) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 183:97] node _sbAccessError_T_11 = eq(SBCSFieldsReg.sbaccess, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 185:49] node _sbAccessError_T_12 = neq(SBCSFieldsReg.sbaccess64, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 185:88] node _sbAccessError_T_13 = and(_sbAccessError_T_11, _sbAccessError_T_12) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 185:58] node _sbAccessError_T_14 = or(_sbAccessError_T_10, _sbAccessError_T_13) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 184:97] node _sbAccessError_T_15 = eq(SBCSFieldsReg.sbaccess, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 186:49] node _sbAccessError_T_16 = neq(SBCSFieldsReg.sbaccess128, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 186:88] node _sbAccessError_T_17 = and(_sbAccessError_T_15, _sbAccessError_T_16) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 186:58] node _sbAccessError_T_18 = or(_sbAccessError_T_14, _sbAccessError_T_17) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 185:97] node _sbAccessError_T_19 = gt(SBCSFieldsReg.sbaccess, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 186:124] node sbAccessError = or(_sbAccessError_T_18, _sbAccessError_T_19) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 186:97] wire compareAddr : UInt<32> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 188:27] node _compareAddr_T = mux(SBADDRESSWrEn[0], SBADDRESSWrData[0], SBADDRESSFieldsReg[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 189:23] connect compareAddr, _compareAddr_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 189:17] node _sbAlignmentError_T = eq(SBCSFieldsReg.sbaccess, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 191:52] node _sbAlignmentError_T_1 = bits(compareAddr, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 191:76] node _sbAlignmentError_T_2 = neq(_sbAlignmentError_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 191:82] node _sbAlignmentError_T_3 = and(_sbAlignmentError_T, _sbAlignmentError_T_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 191:61] node _sbAlignmentError_T_4 = eq(SBCSFieldsReg.sbaccess, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 192:52] node _sbAlignmentError_T_5 = bits(compareAddr, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 192:76] node _sbAlignmentError_T_6 = neq(_sbAlignmentError_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 192:82] node _sbAlignmentError_T_7 = and(_sbAlignmentError_T_4, _sbAlignmentError_T_6) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 192:61] node _sbAlignmentError_T_8 = or(_sbAlignmentError_T_3, _sbAlignmentError_T_7) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 191:91] node _sbAlignmentError_T_9 = eq(SBCSFieldsReg.sbaccess, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 193:52] node _sbAlignmentError_T_10 = bits(compareAddr, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 193:76] node _sbAlignmentError_T_11 = neq(_sbAlignmentError_T_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 193:82] node _sbAlignmentError_T_12 = and(_sbAlignmentError_T_9, _sbAlignmentError_T_11) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 193:61] node _sbAlignmentError_T_13 = or(_sbAlignmentError_T_8, _sbAlignmentError_T_12) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 192:91] node _sbAlignmentError_T_14 = eq(SBCSFieldsReg.sbaccess, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 194:52] node _sbAlignmentError_T_15 = bits(compareAddr, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 194:76] node _sbAlignmentError_T_16 = neq(_sbAlignmentError_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 194:82] node _sbAlignmentError_T_17 = and(_sbAlignmentError_T_14, _sbAlignmentError_T_16) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 194:61] node sbAlignmentError = or(_sbAlignmentError_T_13, _sbAlignmentError_T_17) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 193:91] node _sb2tlOpt_io_wrEn_T = and(UInt<1>(0h1), SBDATAWrEn[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 199:49] node _sb2tlOpt_io_wrEn_T_1 = eq(SBCSFieldsReg.sbbusy, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 199:63] node _sb2tlOpt_io_wrEn_T_2 = and(_sb2tlOpt_io_wrEn_T, _sb2tlOpt_io_wrEn_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 199:60] node _sb2tlOpt_io_wrEn_T_3 = eq(SBCSFieldsReg.sbbusyerror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 199:88] node _sb2tlOpt_io_wrEn_T_4 = and(_sb2tlOpt_io_wrEn_T_2, _sb2tlOpt_io_wrEn_T_3) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 199:85] node _sb2tlOpt_io_wrEn_T_5 = eq(SBCSRdData.sberror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 199:118] node _sb2tlOpt_io_wrEn_T_6 = and(_sb2tlOpt_io_wrEn_T_4, _sb2tlOpt_io_wrEn_T_5) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 199:115] node _sb2tlOpt_io_wrEn_T_7 = eq(sbAccessError, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 199:141] node _sb2tlOpt_io_wrEn_T_8 = and(_sb2tlOpt_io_wrEn_T_6, _sb2tlOpt_io_wrEn_T_7) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 199:138] node _sb2tlOpt_io_wrEn_T_9 = eq(sbAlignmentError, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 199:159] node _sb2tlOpt_io_wrEn_T_10 = and(_sb2tlOpt_io_wrEn_T_8, _sb2tlOpt_io_wrEn_T_9) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 199:156] connect sb2tlOpt.io.wrEn, _sb2tlOpt_io_wrEn_T_10 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 199:30] node _sb2tlOpt_io_rdEn_T = and(UInt<1>(0h1), tryRdEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 200:49] node _sb2tlOpt_io_rdEn_T_1 = eq(SBCSFieldsReg.sbbusy, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 200:63] node _sb2tlOpt_io_rdEn_T_2 = and(_sb2tlOpt_io_rdEn_T, _sb2tlOpt_io_rdEn_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 200:60] node _sb2tlOpt_io_rdEn_T_3 = eq(SBCSFieldsReg.sbbusyerror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 200:88] node _sb2tlOpt_io_rdEn_T_4 = and(_sb2tlOpt_io_rdEn_T_2, _sb2tlOpt_io_rdEn_T_3) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 200:85] node _sb2tlOpt_io_rdEn_T_5 = eq(SBCSRdData.sberror, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 200:118] node _sb2tlOpt_io_rdEn_T_6 = and(_sb2tlOpt_io_rdEn_T_4, _sb2tlOpt_io_rdEn_T_5) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 200:115] node _sb2tlOpt_io_rdEn_T_7 = eq(sbAccessError, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 200:141] node _sb2tlOpt_io_rdEn_T_8 = and(_sb2tlOpt_io_rdEn_T_6, _sb2tlOpt_io_rdEn_T_7) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 200:138] node _sb2tlOpt_io_rdEn_T_9 = eq(sbAlignmentError, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 200:159] node _sb2tlOpt_io_rdEn_T_10 = and(_sb2tlOpt_io_rdEn_T_8, _sb2tlOpt_io_rdEn_T_9) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 200:156] connect sb2tlOpt.io.rdEn, _sb2tlOpt_io_rdEn_T_10 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 200:30] connect sb2tlOpt.io.sizeIn, SBCSFieldsReg.sbaccess @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 201:30] node sbBusy = neq(sb2tlOpt.io.sbStateOut, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 203:46] node _T_164 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 205:11] node _T_165 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 205:24] node _T_166 = or(_T_164, _T_165) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 205:21] when _T_166 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 205:42] connect SBCSFieldsReg, SBCSFieldsRegReset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 206:21] else : node _SBCSFieldsReg_sbbusyerror_T = and(sbbusyerrorWrEn, SBCSWrData.sbbusyerror) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 208:60] node _SBCSFieldsReg_sbbusyerror_T_1 = and(anyAddressWrEn, sbBusy) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 209:59] node _SBCSFieldsReg_sbbusyerror_T_2 = or(anyDataRdEn, anyDataWrEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 210:57] node _SBCSFieldsReg_sbbusyerror_T_3 = and(_SBCSFieldsReg_sbbusyerror_T_2, sbBusy) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 210:73] node _SBCSFieldsReg_sbbusyerror_T_4 = mux(_SBCSFieldsReg_sbbusyerror_T_3, UInt<1>(0h1), SBCSFieldsReg.sbbusyerror) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 210:43] node _SBCSFieldsReg_sbbusyerror_T_5 = mux(_SBCSFieldsReg_sbbusyerror_T_1, UInt<1>(0h1), _SBCSFieldsReg_sbbusyerror_T_4) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 209:43] node _SBCSFieldsReg_sbbusyerror_T_6 = mux(_SBCSFieldsReg_sbbusyerror_T, UInt<1>(0h0), _SBCSFieldsReg_sbbusyerror_T_5) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 208:43] connect SBCSFieldsReg.sbbusyerror, _SBCSFieldsReg_sbbusyerror_T_6 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 208:37] node _SBCSFieldsReg_sbreadonaddr_T = mux(sbreadonaddrWrEn, SBCSWrData.sbreadonaddr, SBCSFieldsReg.sbreadonaddr) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 211:43] connect SBCSFieldsReg.sbreadonaddr, _SBCSFieldsReg_sbreadonaddr_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 211:37] node _SBCSFieldsReg_sbautoincrement_T = mux(sbautoincrementWrEn, SBCSWrData.sbautoincrement, SBCSFieldsReg.sbautoincrement) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 212:43] connect SBCSFieldsReg.sbautoincrement, _SBCSFieldsReg_sbautoincrement_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 212:37] node _SBCSFieldsReg_sbreadondata_T = mux(sbreadondataWrEn, SBCSWrData.sbreadondata, SBCSFieldsReg.sbreadondata) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 213:43] connect SBCSFieldsReg.sbreadondata, _SBCSFieldsReg_sbreadondata_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 213:37] node _SBCSFieldsReg_sbaccess_T = mux(sbaccessWrEn, SBCSWrData.sbaccess, SBCSFieldsReg.sbaccess) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 214:43] connect SBCSFieldsReg.sbaccess, _SBCSFieldsReg_sbaccess_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 214:37] connect SBCSFieldsReg.sbversion, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 215:37] reg sbErrorReg : UInt<1>[4], clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 219:25] node _T_167 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 220:10] node _T_168 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 220:23] node _T_169 = or(_T_167, _T_168) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 220:20] when _T_169 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 220:41] connect sbErrorReg[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 222:23] connect sbErrorReg[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 222:23] connect sbErrorReg[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 222:23] else : node _sbErrorReg_0_T = bits(SBCSWrData.sberror, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 225:63] node _sbErrorReg_0_T_1 = eq(_sbErrorReg_0_T, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 225:67] node _sbErrorReg_0_T_2 = and(sberrorWrEn, _sbErrorReg_0_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 225:42] node _sbErrorReg_0_T_3 = eq(sb2tlOpt.io.wrLegal, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 226:55] node _sbErrorReg_0_T_4 = and(sb2tlOpt.io.wrEn, _sbErrorReg_0_T_3) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 226:52] node _sbErrorReg_0_T_5 = eq(sb2tlOpt.io.rdLegal, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 226:109] node _sbErrorReg_0_T_6 = and(sb2tlOpt.io.rdEn, _sbErrorReg_0_T_5) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 226:106] node _sbErrorReg_0_T_7 = or(_sbErrorReg_0_T_4, _sbErrorReg_0_T_6) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 226:81] node _sbErrorReg_0_T_8 = or(SBDATAWrEn[0], tryRdEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 227:39] node _sbErrorReg_0_T_9 = and(_sbErrorReg_0_T_8, sbAlignmentError) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 227:51] node _sbErrorReg_0_T_10 = or(SBDATAWrEn[0], tryRdEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 228:39] node _sbErrorReg_0_T_11 = and(_sbErrorReg_0_T_10, sbAccessError) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 228:51] node _sbErrorReg_0_T_12 = or(sb2tlOpt.io.rdDone, sb2tlOpt.io.wrDone) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 229:54] node _sbErrorReg_0_T_13 = and(_sbErrorReg_0_T_12, sb2tlOpt.io.respError) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 229:81] node _sbErrorReg_0_T_14 = mux(_sbErrorReg_0_T_13, UInt<1>(0h1), sbErrorReg[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 229:29] node _sbErrorReg_0_T_15 = mux(_sbErrorReg_0_T_11, UInt<1>(0h0), _sbErrorReg_0_T_14) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 228:29] node _sbErrorReg_0_T_16 = mux(_sbErrorReg_0_T_9, UInt<1>(0h1), _sbErrorReg_0_T_15) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 227:29] node _sbErrorReg_0_T_17 = mux(_sbErrorReg_0_T_7, UInt<1>(0h0), _sbErrorReg_0_T_16) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 226:29] node _sbErrorReg_0_T_18 = mux(_sbErrorReg_0_T_2, UInt<1>(0h0), _sbErrorReg_0_T_17) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 225:29] connect sbErrorReg[0], _sbErrorReg_0_T_18 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 225:23] node _sbErrorReg_1_T = bits(SBCSWrData.sberror, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 225:63] node _sbErrorReg_1_T_1 = eq(_sbErrorReg_1_T, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 225:67] node _sbErrorReg_1_T_2 = and(sberrorWrEn, _sbErrorReg_1_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 225:42] node _sbErrorReg_1_T_3 = eq(sb2tlOpt.io.wrLegal, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 226:55] node _sbErrorReg_1_T_4 = and(sb2tlOpt.io.wrEn, _sbErrorReg_1_T_3) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 226:52] node _sbErrorReg_1_T_5 = eq(sb2tlOpt.io.rdLegal, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 226:109] node _sbErrorReg_1_T_6 = and(sb2tlOpt.io.rdEn, _sbErrorReg_1_T_5) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 226:106] node _sbErrorReg_1_T_7 = or(_sbErrorReg_1_T_4, _sbErrorReg_1_T_6) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 226:81] node _sbErrorReg_1_T_8 = or(SBDATAWrEn[0], tryRdEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 227:39] node _sbErrorReg_1_T_9 = and(_sbErrorReg_1_T_8, sbAlignmentError) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 227:51] node _sbErrorReg_1_T_10 = or(SBDATAWrEn[0], tryRdEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 228:39] node _sbErrorReg_1_T_11 = and(_sbErrorReg_1_T_10, sbAccessError) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 228:51] node _sbErrorReg_1_T_12 = or(sb2tlOpt.io.rdDone, sb2tlOpt.io.wrDone) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 229:54] node _sbErrorReg_1_T_13 = and(_sbErrorReg_1_T_12, sb2tlOpt.io.respError) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 229:81] node _sbErrorReg_1_T_14 = mux(_sbErrorReg_1_T_13, UInt<1>(0h1), sbErrorReg[1]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 229:29] node _sbErrorReg_1_T_15 = mux(_sbErrorReg_1_T_11, UInt<1>(0h0), _sbErrorReg_1_T_14) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 228:29] node _sbErrorReg_1_T_16 = mux(_sbErrorReg_1_T_9, UInt<1>(0h1), _sbErrorReg_1_T_15) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 227:29] node _sbErrorReg_1_T_17 = mux(_sbErrorReg_1_T_7, UInt<1>(0h1), _sbErrorReg_1_T_16) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 226:29] node _sbErrorReg_1_T_18 = mux(_sbErrorReg_1_T_2, UInt<1>(0h0), _sbErrorReg_1_T_17) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 225:29] connect sbErrorReg[1], _sbErrorReg_1_T_18 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 225:23] node _sbErrorReg_2_T = bits(SBCSWrData.sberror, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 225:63] node _sbErrorReg_2_T_1 = eq(_sbErrorReg_2_T, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 225:67] node _sbErrorReg_2_T_2 = and(sberrorWrEn, _sbErrorReg_2_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 225:42] node _sbErrorReg_2_T_3 = eq(sb2tlOpt.io.wrLegal, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 226:55] node _sbErrorReg_2_T_4 = and(sb2tlOpt.io.wrEn, _sbErrorReg_2_T_3) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 226:52] node _sbErrorReg_2_T_5 = eq(sb2tlOpt.io.rdLegal, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 226:109] node _sbErrorReg_2_T_6 = and(sb2tlOpt.io.rdEn, _sbErrorReg_2_T_5) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 226:106] node _sbErrorReg_2_T_7 = or(_sbErrorReg_2_T_4, _sbErrorReg_2_T_6) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 226:81] node _sbErrorReg_2_T_8 = or(SBDATAWrEn[0], tryRdEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 227:39] node _sbErrorReg_2_T_9 = and(_sbErrorReg_2_T_8, sbAlignmentError) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 227:51] node _sbErrorReg_2_T_10 = or(SBDATAWrEn[0], tryRdEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 228:39] node _sbErrorReg_2_T_11 = and(_sbErrorReg_2_T_10, sbAccessError) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 228:51] node _sbErrorReg_2_T_12 = or(sb2tlOpt.io.rdDone, sb2tlOpt.io.wrDone) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 229:54] node _sbErrorReg_2_T_13 = and(_sbErrorReg_2_T_12, sb2tlOpt.io.respError) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 229:81] node _sbErrorReg_2_T_14 = mux(_sbErrorReg_2_T_13, UInt<1>(0h1), sbErrorReg[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 229:29] node _sbErrorReg_2_T_15 = mux(_sbErrorReg_2_T_11, UInt<1>(0h1), _sbErrorReg_2_T_14) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 228:29] node _sbErrorReg_2_T_16 = mux(_sbErrorReg_2_T_9, UInt<1>(0h0), _sbErrorReg_2_T_15) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 227:29] node _sbErrorReg_2_T_17 = mux(_sbErrorReg_2_T_7, UInt<1>(0h0), _sbErrorReg_2_T_16) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 226:29] node _sbErrorReg_2_T_18 = mux(_sbErrorReg_2_T_2, UInt<1>(0h0), _sbErrorReg_2_T_17) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 225:29] connect sbErrorReg[2], _sbErrorReg_2_T_18 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 225:23] connect SBCSRdData, SBCSFieldsReg @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 232:28] connect SBCSRdData.sbasize, UInt<6>(0h20) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 233:28] connect SBCSRdData.sbaccess128, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 234:28] connect SBCSRdData.sbaccess64, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 235:28] connect SBCSRdData.sbaccess32, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 236:28] connect SBCSRdData.sbaccess16, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 237:28] connect SBCSRdData.sbaccess8, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 238:28] connect SBCSRdData.sbbusy, sbBusy @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 239:28] node SBCSRdData_sberror_lo = cat(sbErrorReg[1], sbErrorReg[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 240:42] node SBCSRdData_sberror_hi = cat(sbErrorReg[3], sbErrorReg[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 240:42] node _SBCSRdData_sberror_T = cat(SBCSRdData_sberror_hi, SBCSRdData_sberror_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 240:42] connect SBCSRdData.sberror, _SBCSRdData_sberror_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 240:28] node _T_170 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 242:11] when _T_170 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 242:29] wire _SBCSRdData_WIRE_1 : { sbversion : UInt<3>, reserved0 : UInt<6>, sbbusyerror : UInt<1>, sbbusy : UInt<1>, sbreadonaddr : UInt<1>, sbaccess : UInt<3>, sbautoincrement : UInt<1>, sbreadondata : UInt<1>, sberror : UInt<3>, sbasize : UInt<7>, sbaccess128 : UInt<1>, sbaccess64 : UInt<1>, sbaccess32 : UInt<1>, sbaccess16 : UInt<1>, sbaccess8 : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 243:33] connect _SBCSRdData_WIRE_1.sbaccess8, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 243:33] connect _SBCSRdData_WIRE_1.sbaccess16, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 243:33] connect _SBCSRdData_WIRE_1.sbaccess32, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 243:33] connect _SBCSRdData_WIRE_1.sbaccess64, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 243:33] connect _SBCSRdData_WIRE_1.sbaccess128, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 243:33] connect _SBCSRdData_WIRE_1.sbasize, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 243:33] connect _SBCSRdData_WIRE_1.sberror, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 243:33] connect _SBCSRdData_WIRE_1.sbreadondata, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 243:33] connect _SBCSRdData_WIRE_1.sbautoincrement, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 243:33] connect _SBCSRdData_WIRE_1.sbaccess, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 243:33] connect _SBCSRdData_WIRE_1.sbreadonaddr, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 243:33] connect _SBCSRdData_WIRE_1.sbbusy, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 243:33] connect _SBCSRdData_WIRE_1.sbbusyerror, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 243:33] connect _SBCSRdData_WIRE_1.reserved0, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 243:33] connect _SBCSRdData_WIRE_1.sbversion, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 243:33] connect SBCSRdData, _SBCSRdData_WIRE_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 243:18] node _T_171 = eq(SBCSFieldsReg.sbbusy, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 247:41] node _T_172 = or(sb2tlOpt.io.wrEn, sb2tlOpt.io.rdEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 249:42] node _T_173 = eq(SBCSFieldsReg.sbaccess, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 249:93] node _T_174 = and(_T_172, _T_173) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 249:67] node _T_175 = eq(sbAccessError, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 249:104] node _T_176 = and(_T_174, _T_175) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 249:101] node _T_177 = eq(sbAlignmentError, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 249:122] node _T_178 = and(_T_176, _T_177) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 249:119] node _T_179 = or(sb2tlOpt.io.wrEn, sb2tlOpt.io.rdEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 250:42] node _T_180 = eq(SBCSFieldsReg.sbaccess, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 250:93] node _T_181 = and(_T_179, _T_180) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 250:67] node _T_182 = eq(sbAccessError, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 250:104] node _T_183 = and(_T_181, _T_182) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 250:101] node _T_184 = eq(sbAlignmentError, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 250:122] node _T_185 = and(_T_183, _T_184) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 250:119] node _T_186 = or(sb2tlOpt.io.wrEn, sb2tlOpt.io.rdEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 251:42] node _T_187 = eq(SBCSFieldsReg.sbaccess, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 251:93] node _T_188 = and(_T_186, _T_187) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 251:67] node _T_189 = eq(sbAccessError, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 251:104] node _T_190 = and(_T_188, _T_189) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 251:101] node _T_191 = eq(sbAlignmentError, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 251:122] node _T_192 = and(_T_190, _T_191) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 251:119] node _T_193 = or(sb2tlOpt.io.wrEn, sb2tlOpt.io.rdEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 252:42] node _T_194 = eq(SBCSFieldsReg.sbaccess, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 252:93] node _T_195 = and(_T_193, _T_194) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 252:67] node _T_196 = eq(sbAccessError, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 252:104] node _T_197 = and(_T_195, _T_196) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 252:101] node _T_198 = eq(sbAlignmentError, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 252:122] node _T_199 = and(_T_197, _T_198) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 252:119] node _T_200 = or(sb2tlOpt.io.wrEn, sb2tlOpt.io.rdEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 253:42] node _T_201 = eq(SBCSFieldsReg.sbaccess, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 253:93] node _T_202 = and(_T_200, _T_201) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 253:67] node _T_203 = eq(sbAccessError, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 253:104] node _T_204 = and(_T_202, _T_203) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 253:101] node _T_205 = eq(sbAlignmentError, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 253:122] node _T_206 = and(_T_204, _T_205) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 253:119] node _T_207 = and(SBCSFieldsReg.sbautoincrement, SBCSFieldsReg.sbbusy) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 255:50] node _T_208 = eq(SBCSFieldsReg.sbautoincrement, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 256:20] node _T_209 = and(_T_208, SBCSFieldsReg.sbbusy) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 256:51] node _T_210 = or(sb2tlOpt.io.wrEn, sb2tlOpt.io.rdEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 258:42] node _T_211 = gt(SBCSFieldsReg.sbaccess, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 258:93] node _T_212 = and(_T_210, _T_211) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/SBA.scala 258:67] node _T_213 = cat(COMMANDReg.cmdtype, COMMANDReg.control) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1434:40] node _T_214 = mux(UInt<1>(0h1), abstractDataMem[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1437:24] node _T_215 = mux(UInt<1>(0h1), abstractDataMem[1], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1437:24] node _T_216 = mux(UInt<1>(0h1), abstractDataMem[2], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1437:24] node _T_217 = mux(UInt<1>(0h1), abstractDataMem[3], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1437:24] node _T_218 = mux(UInt<1>(0h1), abstractDataMem[4], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1437:24] node _T_219 = mux(UInt<1>(0h1), abstractDataMem[5], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1437:24] node _T_220 = mux(UInt<1>(0h1), abstractDataMem[6], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1437:24] node _T_221 = mux(UInt<1>(0h1), abstractDataMem[7], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1437:24] node _T_222 = mux(UInt<1>(0h1), programBufferMem[0], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_223 = mux(UInt<1>(0h1), programBufferMem[1], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_224 = mux(UInt<1>(0h1), programBufferMem[2], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_225 = mux(UInt<1>(0h1), programBufferMem[3], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_226 = mux(UInt<1>(0h1), programBufferMem[4], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_227 = mux(UInt<1>(0h1), programBufferMem[5], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_228 = mux(UInt<1>(0h1), programBufferMem[6], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_229 = mux(UInt<1>(0h1), programBufferMem[7], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_230 = mux(UInt<1>(0h1), programBufferMem[8], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_231 = mux(UInt<1>(0h1), programBufferMem[9], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_232 = mux(UInt<1>(0h1), programBufferMem[10], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_233 = mux(UInt<1>(0h1), programBufferMem[11], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_234 = mux(UInt<1>(0h1), programBufferMem[12], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_235 = mux(UInt<1>(0h1), programBufferMem[13], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_236 = mux(UInt<1>(0h1), programBufferMem[14], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_237 = mux(UInt<1>(0h1), programBufferMem[15], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_238 = mux(UInt<1>(0h1), programBufferMem[16], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_239 = mux(UInt<1>(0h1), programBufferMem[17], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_240 = mux(UInt<1>(0h1), programBufferMem[18], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_241 = mux(UInt<1>(0h1), programBufferMem[19], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_242 = mux(UInt<1>(0h1), programBufferMem[20], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_243 = mux(UInt<1>(0h1), programBufferMem[21], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_244 = mux(UInt<1>(0h1), programBufferMem[22], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_245 = mux(UInt<1>(0h1), programBufferMem[23], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_246 = mux(UInt<1>(0h1), programBufferMem[24], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_247 = mux(UInt<1>(0h1), programBufferMem[25], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_248 = mux(UInt<1>(0h1), programBufferMem[26], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_249 = mux(UInt<1>(0h1), programBufferMem[27], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_250 = mux(UInt<1>(0h1), programBufferMem[28], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_251 = mux(UInt<1>(0h1), programBufferMem[29], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_252 = mux(UInt<1>(0h1), programBufferMem[30], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_253 = mux(UInt<1>(0h1), programBufferMem[31], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_254 = mux(UInt<1>(0h1), programBufferMem[32], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_255 = mux(UInt<1>(0h1), programBufferMem[33], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_256 = mux(UInt<1>(0h1), programBufferMem[34], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_257 = mux(UInt<1>(0h1), programBufferMem[35], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_258 = mux(UInt<1>(0h1), programBufferMem[36], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_259 = mux(UInt<1>(0h1), programBufferMem[37], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_260 = mux(UInt<1>(0h1), programBufferMem[38], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_261 = mux(UInt<1>(0h1), programBufferMem[39], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_262 = mux(UInt<1>(0h1), programBufferMem[40], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_263 = mux(UInt<1>(0h1), programBufferMem[41], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_264 = mux(UInt<1>(0h1), programBufferMem[42], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_265 = mux(UInt<1>(0h1), programBufferMem[43], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_266 = mux(UInt<1>(0h1), programBufferMem[44], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_267 = mux(UInt<1>(0h1), programBufferMem[45], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_268 = mux(UInt<1>(0h1), programBufferMem[46], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_269 = mux(UInt<1>(0h1), programBufferMem[47], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_270 = mux(UInt<1>(0h1), programBufferMem[48], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_271 = mux(UInt<1>(0h1), programBufferMem[49], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_272 = mux(UInt<1>(0h1), programBufferMem[50], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_273 = mux(UInt<1>(0h1), programBufferMem[51], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_274 = mux(UInt<1>(0h1), programBufferMem[52], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_275 = mux(UInt<1>(0h1), programBufferMem[53], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_276 = mux(UInt<1>(0h1), programBufferMem[54], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_277 = mux(UInt<1>(0h1), programBufferMem[55], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_278 = mux(UInt<1>(0h1), programBufferMem[56], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_279 = mux(UInt<1>(0h1), programBufferMem[57], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_280 = mux(UInt<1>(0h1), programBufferMem[58], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_281 = mux(UInt<1>(0h1), programBufferMem[59], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_282 = mux(UInt<1>(0h1), programBufferMem[60], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_283 = mux(UInt<1>(0h1), programBufferMem[61], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_284 = mux(UInt<1>(0h1), programBufferMem[62], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] node _T_285 = mux(UInt<1>(0h1), programBufferMem[63], UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1442:24] wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<7>, data : UInt<32>, mask : UInt<4>, extra : { tlrr_extra : { source : UInt<1>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 73:18] node _in_bits_read_T = eq(dmiNodeIn.a.bits.opcode, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 74:36] connect in.bits.read, _in_bits_read_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 74:19] node _in_bits_index_T = shr(dmiNodeIn.a.bits.address, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 192:34] connect in.bits.index, _in_bits_index_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 75:19] connect in.bits.data, dmiNodeIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 76:19] connect in.bits.mask, dmiNodeIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 77:19] connect in.bits.extra.tlrr_extra.source, dmiNodeIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 83:20] connect in.bits.extra.tlrr_extra.size, dmiNodeIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 84:20] wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<32>, extra : { tlrr_extra : { source : UInt<1>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<7>, data : UInt<32>, mask : UInt<4>, extra : { tlrr_extra : { source : UInt<1>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front.bits, in.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_maskMatch = not(UInt<7>(0h3f)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_findex = and(out_front.bits.index, out_maskMatch) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_bindex = and(out_front.bits.index, out_maskMatch) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_13 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_14 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_15 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_16 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_17 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_18 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_19 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_20 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_21 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_22 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_23 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_24 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_25 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_26 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_27 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_28 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_29 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_30 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_31 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_32 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_33 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_34 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_35 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_36 = eq(out_findex, UInt<7>(0h40)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_37 = eq(out_bindex, UInt<7>(0h40)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_38 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_39 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_40 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_41 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_42 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_43 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_44 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_45 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_46 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_47 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_48 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_49 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_50 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_51 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_52 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_53 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_54 = eq(out_findex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_55 = eq(out_bindex, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rivalid : UInt<1>[122] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wivalid : UInt<1>[122] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_roready : UInt<1>[122] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_woready : UInt<1>[122] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_4 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_5 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_6 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_7 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo = cat(_out_frontMask_T_5, _out_frontMask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi = cat(_out_frontMask_T_7, _out_frontMask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T = bits(out_front.bits.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_4 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_5 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_6 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_7 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo = cat(_out_backMask_T_5, _out_backMask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi = cat(_out_backMask_T_7, _out_backMask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask = cat(out_backMask_hi, out_backMask_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask = orr(_out_rimask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask = andr(_out_wimask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask = orr(_out_romask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask = andr(_out_womask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid = and(out_rivalid[0], out_rimask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready = and(out_roready[0], out_romask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid = and(out_wivalid[0], out_wimask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready = and(out_woready[0], out_womask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiAbstractDataRdEn[4], out_f_roready @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_56 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiAbstractDataWrEnMaybe[4], out_f_woready @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect abstractDataNxt[4], _out_T_56 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_57 = and(out_f_rivalid, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_58 = and(UInt<1>(0h1), out_f_roready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_59 = and(out_f_wivalid, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_60 = and(UInt<1>(0h1), out_f_woready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_61 = eq(out_rimask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_62 = eq(out_wimask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_63 = eq(out_romask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_64 = eq(out_womask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_65 = or(_T_218, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_66 = bits(_out_T_65, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1 = orr(_out_rimask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1 = andr(_out_wimask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1 = orr(_out_romask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1 = andr(_out_womask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1 = and(out_roready[1], out_romask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1 = and(out_woready[1], out_womask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiAbstractDataRdEn[5], out_f_roready_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_67 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiAbstractDataWrEnMaybe[5], out_f_woready_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_1 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect abstractDataNxt[5], _out_T_67 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_68 = and(out_f_rivalid_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_69 = and(UInt<1>(0h1), out_f_roready_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_70 = and(out_f_wivalid_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_71 = and(UInt<1>(0h1), out_f_woready_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_72 = eq(out_rimask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_73 = eq(out_wimask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_74 = eq(out_romask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_75 = eq(out_womask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T = or(_out_T_66, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend = cat(_T_219, _out_prepend_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_76 = or(out_prepend, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_77 = bits(_out_T_76, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_2 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_2 = orr(_out_rimask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_2 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_2 = andr(_out_wimask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_2 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_2 = orr(_out_romask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_2 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_2 = andr(_out_womask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_2 = and(out_roready[2], out_romask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_2 = and(out_woready[2], out_womask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiAbstractDataRdEn[6], out_f_roready_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_78 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiAbstractDataWrEnMaybe[6], out_f_woready_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_2 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect abstractDataNxt[6], _out_T_78 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_79 = and(out_f_rivalid_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_80 = and(UInt<1>(0h1), out_f_roready_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_81 = and(out_f_wivalid_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_82 = and(UInt<1>(0h1), out_f_woready_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_83 = eq(out_rimask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_84 = eq(out_wimask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_85 = eq(out_romask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_86 = eq(out_womask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1 = or(_out_T_77, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1 = cat(_T_220, _out_prepend_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_87 = or(out_prepend_1, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_88 = bits(_out_T_87, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_3 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_3 = orr(_out_rimask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_3 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_3 = andr(_out_wimask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_3 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_3 = orr(_out_romask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_3 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_3 = andr(_out_womask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_3 = and(out_roready[3], out_romask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_3 = and(out_woready[3], out_womask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiAbstractDataRdEn[7], out_f_roready_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_89 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiAbstractDataWrEnMaybe[7], out_f_woready_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_3 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect abstractDataNxt[7], _out_T_89 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_90 = and(out_f_rivalid_3, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_91 = and(UInt<1>(0h1), out_f_roready_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_92 = and(out_f_wivalid_3, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_93 = and(UInt<1>(0h1), out_f_woready_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_94 = eq(out_rimask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_95 = eq(out_wimask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_96 = eq(out_romask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_97 = eq(out_womask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_2 = or(_out_T_88, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_2 = cat(_T_221, _out_prepend_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_98 = or(out_prepend_2, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_99 = bits(_out_T_98, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_4 = bits(out_frontMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_4 = orr(_out_rimask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_4 = bits(out_frontMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_4 = andr(_out_wimask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_4 = bits(out_backMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_4 = orr(_out_romask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_4 = bits(out_backMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_4 = andr(_out_womask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_4 = and(out_roready[4], out_romask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_4 = and(out_woready[4], out_womask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_100 = bits(out_front.bits.data, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_101 = and(out_f_rivalid_4, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_102 = and(UInt<1>(0h1), out_f_roready_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_103 = eq(out_rimask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_104 = eq(out_wimask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_105 = eq(out_romask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_106 = eq(out_womask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_107 = or(SBCSRdData.sbaccess8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_108 = bits(_out_T_107, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_5 = bits(out_frontMask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_5 = orr(_out_rimask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_5 = bits(out_frontMask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_5 = andr(_out_wimask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_5 = bits(out_backMask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_5 = orr(_out_romask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_5 = bits(out_backMask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_5 = andr(_out_womask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_5 = and(out_roready[5], out_romask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_5 = and(out_woready[5], out_womask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_109 = bits(out_front.bits.data, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_110 = and(out_f_rivalid_5, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_111 = and(UInt<1>(0h1), out_f_roready_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_112 = eq(out_rimask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_113 = eq(out_wimask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_114 = eq(out_romask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_115 = eq(out_womask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_3 = or(_out_T_108, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_3 = cat(SBCSRdData.sbaccess16, _out_prepend_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_116 = or(out_prepend_3, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_117 = bits(_out_T_116, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_6 = bits(out_frontMask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_6 = orr(_out_rimask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_6 = bits(out_frontMask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_6 = andr(_out_wimask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_6 = bits(out_backMask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_6 = orr(_out_romask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_6 = bits(out_backMask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_6 = andr(_out_womask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_6 = and(out_roready[6], out_romask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_6 = and(out_woready[6], out_womask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_118 = bits(out_front.bits.data, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_119 = and(out_f_rivalid_6, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_120 = and(UInt<1>(0h1), out_f_roready_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_121 = eq(out_rimask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_122 = eq(out_wimask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_123 = eq(out_romask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_124 = eq(out_womask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_4 = or(_out_T_117, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_4 = cat(SBCSRdData.sbaccess32, _out_prepend_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_125 = or(out_prepend_4, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_126 = bits(_out_T_125, 2, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_7 = bits(out_frontMask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_7 = orr(_out_rimask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_7 = bits(out_frontMask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_7 = andr(_out_wimask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_7 = bits(out_backMask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_7 = orr(_out_romask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_7 = bits(out_backMask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_7 = andr(_out_womask_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_7 = and(out_roready[7], out_romask_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_7 = and(out_woready[7], out_womask_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_127 = bits(out_front.bits.data, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_128 = and(out_f_rivalid_7, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_129 = and(UInt<1>(0h1), out_f_roready_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_130 = eq(out_rimask_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_131 = eq(out_wimask_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_132 = eq(out_romask_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_133 = eq(out_womask_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_5 = or(_out_T_126, UInt<3>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_5 = cat(SBCSRdData.sbaccess64, _out_prepend_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_134 = or(out_prepend_5, UInt<4>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_135 = bits(_out_T_134, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_8 = bits(out_frontMask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_8 = orr(_out_rimask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_8 = bits(out_frontMask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_8 = andr(_out_wimask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_8 = bits(out_backMask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_8 = orr(_out_romask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_8 = bits(out_backMask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_8 = andr(_out_womask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_8 = and(out_roready[8], out_romask_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_8 = and(out_woready[8], out_womask_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_136 = bits(out_front.bits.data, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_137 = and(out_f_rivalid_8, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_138 = and(UInt<1>(0h1), out_f_roready_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_139 = eq(out_rimask_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_140 = eq(out_wimask_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_141 = eq(out_romask_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_142 = eq(out_womask_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_6 = or(_out_T_135, UInt<4>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_6 = cat(SBCSRdData.sbaccess128, _out_prepend_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_143 = or(out_prepend_6, UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_144 = bits(_out_T_143, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_9 = bits(out_frontMask, 11, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_9 = orr(_out_rimask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_9 = bits(out_frontMask, 11, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_9 = andr(_out_wimask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_9 = bits(out_backMask, 11, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_9 = orr(_out_romask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_9 = bits(out_backMask, 11, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_9 = andr(_out_womask_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_9 = and(out_roready[9], out_romask_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_9 = and(out_woready[9], out_womask_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_145 = bits(out_front.bits.data, 11, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_146 = and(out_f_rivalid_9, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_147 = and(UInt<1>(0h1), out_f_roready_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_148 = eq(out_rimask_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_149 = eq(out_wimask_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_150 = eq(out_romask_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_151 = eq(out_womask_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_7 = or(_out_T_144, UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_7 = cat(SBCSRdData.sbasize, _out_prepend_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_152 = or(out_prepend_7, UInt<12>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_153 = bits(_out_T_152, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_10 = bits(out_frontMask, 14, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_10 = orr(_out_rimask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_10 = bits(out_frontMask, 14, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_10 = andr(_out_wimask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_10 = bits(out_backMask, 14, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_10 = orr(_out_romask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_10 = bits(out_backMask, 14, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_10 = andr(_out_womask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_10 = and(out_roready[10], out_romask_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_10 = and(out_woready[10], out_womask_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_154 = bits(out_front.bits.data, 14, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect sberrorWrEn, out_f_woready_10 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 309:15] connect SBCSWrData.sberror, _out_T_154 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 310:12] node _out_T_155 = and(out_f_rivalid_10, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_156 = and(UInt<1>(0h1), out_f_roready_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_157 = and(out_f_wivalid_10, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_158 = and(UInt<1>(0h1), out_f_woready_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_159 = eq(out_rimask_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_160 = eq(out_wimask_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_161 = eq(out_romask_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_162 = eq(out_womask_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_8 = or(_out_T_153, UInt<12>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_8 = cat(SBCSRdData.sberror, _out_prepend_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_163 = or(out_prepend_8, UInt<15>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_164 = bits(_out_T_163, 14, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_11 = bits(out_frontMask, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_11 = orr(_out_rimask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_11 = bits(out_frontMask, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_11 = andr(_out_wimask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_11 = bits(out_backMask, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_11 = orr(_out_romask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_11 = bits(out_backMask, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_11 = andr(_out_womask_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_11 = and(out_roready[11], out_romask_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_11 = and(out_woready[11], out_womask_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_165 = bits(out_front.bits.data, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect sbreadondataWrEn, out_f_woready_11 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 309:15] connect SBCSWrData.sbreadondata, _out_T_165 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 310:12] node _out_T_166 = and(out_f_rivalid_11, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_167 = and(UInt<1>(0h1), out_f_roready_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_168 = and(out_f_wivalid_11, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_169 = and(UInt<1>(0h1), out_f_woready_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_170 = eq(out_rimask_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_171 = eq(out_wimask_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_172 = eq(out_romask_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_173 = eq(out_womask_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_9 = or(_out_T_164, UInt<15>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_9 = cat(SBCSRdData.sbreadondata, _out_prepend_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_174 = or(out_prepend_9, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_175 = bits(_out_T_174, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_12 = bits(out_frontMask, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_12 = orr(_out_rimask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_12 = bits(out_frontMask, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_12 = andr(_out_wimask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_12 = bits(out_backMask, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_12 = orr(_out_romask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_12 = bits(out_backMask, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_12 = andr(_out_womask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_12 = and(out_roready[12], out_romask_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_12 = and(out_woready[12], out_womask_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_176 = bits(out_front.bits.data, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect sbautoincrementWrEn, out_f_woready_12 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 309:15] connect SBCSWrData.sbautoincrement, _out_T_176 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 310:12] node _out_T_177 = and(out_f_rivalid_12, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_178 = and(UInt<1>(0h1), out_f_roready_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_179 = and(out_f_wivalid_12, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_180 = and(UInt<1>(0h1), out_f_woready_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_181 = eq(out_rimask_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_182 = eq(out_wimask_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_183 = eq(out_romask_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_184 = eq(out_womask_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_10 = or(_out_T_175, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_10 = cat(SBCSRdData.sbautoincrement, _out_prepend_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_185 = or(out_prepend_10, UInt<17>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_186 = bits(_out_T_185, 16, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_13 = bits(out_frontMask, 19, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_13 = orr(_out_rimask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_13 = bits(out_frontMask, 19, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_13 = andr(_out_wimask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_13 = bits(out_backMask, 19, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_13 = orr(_out_romask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_13 = bits(out_backMask, 19, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_13 = andr(_out_womask_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_13 = and(out_roready[13], out_romask_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_13 = and(out_woready[13], out_womask_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_187 = bits(out_front.bits.data, 19, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect sbaccessWrEn, out_f_woready_13 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 309:15] connect SBCSWrData.sbaccess, _out_T_187 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 310:12] node _out_T_188 = and(out_f_rivalid_13, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_189 = and(UInt<1>(0h1), out_f_roready_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_190 = and(out_f_wivalid_13, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_191 = and(UInt<1>(0h1), out_f_woready_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_192 = eq(out_rimask_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_193 = eq(out_wimask_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_194 = eq(out_romask_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_195 = eq(out_womask_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_11 = or(_out_T_186, UInt<17>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_11 = cat(SBCSRdData.sbaccess, _out_prepend_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_196 = or(out_prepend_11, UInt<20>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_197 = bits(_out_T_196, 19, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_14 = bits(out_frontMask, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_14 = orr(_out_rimask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_14 = bits(out_frontMask, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_14 = andr(_out_wimask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_14 = bits(out_backMask, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_14 = orr(_out_romask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_14 = bits(out_backMask, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_14 = andr(_out_womask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_14 = and(out_roready[14], out_romask_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_14 = and(out_woready[14], out_womask_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_198 = bits(out_front.bits.data, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect sbreadonaddrWrEn, out_f_woready_14 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 309:15] connect SBCSWrData.sbreadonaddr, _out_T_198 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 310:12] node _out_T_199 = and(out_f_rivalid_14, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_200 = and(UInt<1>(0h1), out_f_roready_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_201 = and(out_f_wivalid_14, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_202 = and(UInt<1>(0h1), out_f_woready_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_203 = eq(out_rimask_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_204 = eq(out_wimask_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_205 = eq(out_romask_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_206 = eq(out_womask_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_12 = or(_out_T_197, UInt<20>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_12 = cat(SBCSRdData.sbreadonaddr, _out_prepend_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_207 = or(out_prepend_12, UInt<21>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_208 = bits(_out_T_207, 20, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_15 = bits(out_frontMask, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_15 = orr(_out_rimask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_15 = bits(out_frontMask, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_15 = andr(_out_wimask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_15 = bits(out_backMask, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_15 = orr(_out_romask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_15 = bits(out_backMask, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_15 = andr(_out_womask_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_15 = and(out_roready[15], out_romask_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_15 = and(out_woready[15], out_womask_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_209 = bits(out_front.bits.data, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_210 = and(out_f_rivalid_15, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_211 = and(UInt<1>(0h1), out_f_roready_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_212 = eq(out_rimask_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_213 = eq(out_wimask_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_214 = eq(out_romask_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_215 = eq(out_womask_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_13 = or(_out_T_208, UInt<21>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_13 = cat(SBCSRdData.sbbusy, _out_prepend_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_216 = or(out_prepend_13, UInt<22>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_217 = bits(_out_T_216, 21, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_16 = bits(out_frontMask, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_16 = orr(_out_rimask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_16 = bits(out_frontMask, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_16 = andr(_out_wimask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_16 = bits(out_backMask, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_16 = orr(_out_romask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_16 = bits(out_backMask, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_16 = andr(_out_womask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_16 = and(out_rivalid[16], out_rimask_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_16 = and(out_roready[16], out_romask_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_16 = and(out_wivalid[16], out_wimask_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_16 = and(out_woready[16], out_womask_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_218 = bits(out_front.bits.data, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect sbbusyerrorWrEn, out_f_woready_16 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 309:15] connect SBCSWrData.sbbusyerror, _out_T_218 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 310:12] node _out_T_219 = and(out_f_rivalid_16, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_220 = and(UInt<1>(0h1), out_f_roready_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_221 = and(out_f_wivalid_16, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_222 = and(UInt<1>(0h1), out_f_woready_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_223 = eq(out_rimask_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_224 = eq(out_wimask_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_225 = eq(out_romask_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_226 = eq(out_womask_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_14 = or(_out_T_217, UInt<22>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_14 = cat(SBCSRdData.sbbusyerror, _out_prepend_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_227 = or(out_prepend_14, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_228 = bits(_out_T_227, 22, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_17 = bits(out_frontMask, 28, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_17 = orr(_out_rimask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_17 = bits(out_frontMask, 28, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_17 = andr(_out_wimask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_17 = bits(out_backMask, 28, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_17 = orr(_out_romask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_17 = bits(out_backMask, 28, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_17 = andr(_out_womask_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_17 = and(out_rivalid[17], out_rimask_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_17 = and(out_roready[17], out_romask_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_17 = and(out_wivalid[17], out_wimask_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_17 = and(out_woready[17], out_womask_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_229 = bits(out_front.bits.data, 28, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_230 = and(out_f_rivalid_17, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_231 = and(UInt<1>(0h1), out_f_roready_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_232 = eq(out_rimask_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_233 = eq(out_wimask_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_234 = eq(out_romask_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_235 = eq(out_womask_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_15 = or(_out_T_228, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_15 = cat(UInt<1>(0h0), _out_prepend_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_236 = or(out_prepend_15, UInt<29>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_237 = bits(_out_T_236, 28, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_18 = bits(out_frontMask, 31, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_18 = orr(_out_rimask_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_18 = bits(out_frontMask, 31, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_18 = andr(_out_wimask_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_18 = bits(out_backMask, 31, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_18 = orr(_out_romask_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_18 = bits(out_backMask, 31, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_18 = andr(_out_womask_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_18 = and(out_rivalid[18], out_rimask_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_18 = and(out_roready[18], out_romask_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_18 = and(out_wivalid[18], out_wimask_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_18 = and(out_woready[18], out_womask_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_238 = bits(out_front.bits.data, 31, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_239 = and(out_f_rivalid_18, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_240 = and(UInt<1>(0h1), out_f_roready_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_241 = eq(out_rimask_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_242 = eq(out_wimask_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_243 = eq(out_romask_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_244 = eq(out_womask_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_16 = or(_out_T_237, UInt<29>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_16 = cat(SBCSRdData.sbversion, _out_prepend_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_245 = or(out_prepend_16, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_246 = bits(_out_T_245, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_19 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_19 = orr(_out_rimask_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_19 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_19 = andr(_out_wimask_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_19 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_19 = orr(_out_romask_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_19 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_19 = andr(_out_womask_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_19 = and(out_rivalid[19], out_rimask_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_19 = and(out_roready[19], out_romask_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_19 = and(out_wivalid[19], out_wimask_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_19 = and(out_woready[19], out_womask_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect SBDATARdEn[1], out_f_roready_19 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_247 = bits(out_front.bits.data, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect SBDATAWrEn[1], out_f_woready_19 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_19 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect SBDATAWrData[1], _out_T_247 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_248 = and(out_f_rivalid_19, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_249 = and(UInt<1>(0h1), out_f_roready_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_250 = and(out_f_wivalid_19, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_251 = and(UInt<1>(0h1), out_f_woready_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_252 = eq(out_rimask_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_253 = eq(out_wimask_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_254 = eq(out_romask_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_255 = eq(out_womask_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_256 = or(SBDATARdData[1], UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_257 = bits(_out_T_256, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_20 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_20 = orr(_out_rimask_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_20 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_20 = andr(_out_wimask_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_20 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_20 = orr(_out_romask_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_20 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_20 = andr(_out_womask_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_20 = and(out_rivalid[20], out_rimask_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_20 = and(out_roready[20], out_romask_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_20 = and(out_wivalid[20], out_wimask_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_20 = and(out_woready[20], out_womask_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect SBDATARdEn[0], out_f_roready_20 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_258 = bits(out_front.bits.data, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect SBDATAWrEn[0], out_f_woready_20 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_20 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect SBDATAWrData[0], _out_T_258 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_259 = and(out_f_rivalid_20, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_260 = and(UInt<1>(0h1), out_f_roready_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_261 = and(out_f_wivalid_20, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_262 = and(UInt<1>(0h1), out_f_woready_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_263 = eq(out_rimask_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_264 = eq(out_wimask_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_265 = eq(out_romask_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_266 = eq(out_womask_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_267 = or(SBDATARdData[0], UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_268 = bits(_out_T_267, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_21 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_21 = orr(_out_rimask_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_21 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_21 = andr(_out_wimask_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_21 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_21 = orr(_out_romask_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_21 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_21 = andr(_out_womask_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_21 = and(out_rivalid[21], out_rimask_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_21 = and(out_roready[21], out_romask_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_21 = and(out_wivalid[21], out_wimask_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_21 = and(out_woready[21], out_womask_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[36], out_f_roready_21 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_269 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[36], out_f_woready_21 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_21 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[36], _out_T_269 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_270 = and(out_f_rivalid_21, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_271 = and(UInt<1>(0h1), out_f_roready_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_272 = and(out_f_wivalid_21, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_273 = and(UInt<1>(0h1), out_f_woready_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_274 = eq(out_rimask_21, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_275 = eq(out_wimask_21, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_276 = eq(out_romask_21, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_277 = eq(out_womask_21, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_278 = or(_T_258, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_279 = bits(_out_T_278, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_22 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_22 = orr(_out_rimask_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_22 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_22 = andr(_out_wimask_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_22 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_22 = orr(_out_romask_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_22 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_22 = andr(_out_womask_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_22 = and(out_rivalid[22], out_rimask_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_22 = and(out_roready[22], out_romask_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_22 = and(out_wivalid[22], out_wimask_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_22 = and(out_woready[22], out_womask_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[37], out_f_roready_22 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_280 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[37], out_f_woready_22 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_22 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[37], _out_T_280 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_281 = and(out_f_rivalid_22, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_282 = and(UInt<1>(0h1), out_f_roready_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_283 = and(out_f_wivalid_22, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_284 = and(UInt<1>(0h1), out_f_woready_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_285 = eq(out_rimask_22, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_286 = eq(out_wimask_22, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_287 = eq(out_romask_22, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_288 = eq(out_womask_22, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_17 = or(_out_T_279, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_17 = cat(_T_259, _out_prepend_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_289 = or(out_prepend_17, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_290 = bits(_out_T_289, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_23 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_23 = orr(_out_rimask_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_23 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_23 = andr(_out_wimask_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_23 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_23 = orr(_out_romask_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_23 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_23 = andr(_out_womask_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_23 = and(out_rivalid[23], out_rimask_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_23 = and(out_roready[23], out_romask_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_23 = and(out_wivalid[23], out_wimask_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_23 = and(out_woready[23], out_womask_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[38], out_f_roready_23 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_291 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[38], out_f_woready_23 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_23 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[38], _out_T_291 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_292 = and(out_f_rivalid_23, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_293 = and(UInt<1>(0h1), out_f_roready_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_294 = and(out_f_wivalid_23, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_295 = and(UInt<1>(0h1), out_f_woready_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_296 = eq(out_rimask_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_297 = eq(out_wimask_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_298 = eq(out_romask_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_299 = eq(out_womask_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_18 = or(_out_T_290, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_18 = cat(_T_260, _out_prepend_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_300 = or(out_prepend_18, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_301 = bits(_out_T_300, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_24 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_24 = orr(_out_rimask_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_24 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_24 = andr(_out_wimask_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_24 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_24 = orr(_out_romask_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_24 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_24 = andr(_out_womask_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_24 = and(out_rivalid[24], out_rimask_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_24 = and(out_roready[24], out_romask_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_24 = and(out_wivalid[24], out_wimask_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_24 = and(out_woready[24], out_womask_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[39], out_f_roready_24 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_302 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[39], out_f_woready_24 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_24 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[39], _out_T_302 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_303 = and(out_f_rivalid_24, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_304 = and(UInt<1>(0h1), out_f_roready_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_305 = and(out_f_wivalid_24, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_306 = and(UInt<1>(0h1), out_f_woready_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_307 = eq(out_rimask_24, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_308 = eq(out_wimask_24, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_309 = eq(out_romask_24, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_310 = eq(out_womask_24, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_19 = or(_out_T_301, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_19 = cat(_T_261, _out_prepend_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_311 = or(out_prepend_19, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_312 = bits(_out_T_311, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_25 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_25 = orr(_out_rimask_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_25 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_25 = andr(_out_wimask_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_25 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_25 = orr(_out_romask_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_25 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_25 = andr(_out_womask_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_25 = and(out_rivalid[25], out_rimask_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_25 = and(out_roready[25], out_romask_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_25 = and(out_wivalid[25], out_wimask_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_25 = and(out_woready[25], out_womask_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[28], out_f_roready_25 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_313 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[28], out_f_woready_25 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_25 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[28], _out_T_313 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_314 = and(out_f_rivalid_25, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_315 = and(UInt<1>(0h1), out_f_roready_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_316 = and(out_f_wivalid_25, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_317 = and(UInt<1>(0h1), out_f_woready_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_318 = eq(out_rimask_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_319 = eq(out_wimask_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_320 = eq(out_romask_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_321 = eq(out_womask_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_322 = or(_T_250, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_323 = bits(_out_T_322, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_26 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_26 = orr(_out_rimask_T_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_26 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_26 = andr(_out_wimask_T_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_26 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_26 = orr(_out_romask_T_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_26 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_26 = andr(_out_womask_T_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_26 = and(out_rivalid[26], out_rimask_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_26 = and(out_roready[26], out_romask_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_26 = and(out_wivalid[26], out_wimask_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_26 = and(out_woready[26], out_womask_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[29], out_f_roready_26 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_324 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[29], out_f_woready_26 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_26 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[29], _out_T_324 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_325 = and(out_f_rivalid_26, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_326 = and(UInt<1>(0h1), out_f_roready_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_327 = and(out_f_wivalid_26, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_328 = and(UInt<1>(0h1), out_f_woready_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_329 = eq(out_rimask_26, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_330 = eq(out_wimask_26, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_331 = eq(out_romask_26, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_332 = eq(out_womask_26, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_20 = or(_out_T_323, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_20 = cat(_T_251, _out_prepend_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_333 = or(out_prepend_20, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_334 = bits(_out_T_333, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_27 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_27 = orr(_out_rimask_T_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_27 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_27 = andr(_out_wimask_T_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_27 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_27 = orr(_out_romask_T_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_27 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_27 = andr(_out_womask_T_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_27 = and(out_rivalid[27], out_rimask_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_27 = and(out_roready[27], out_romask_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_27 = and(out_wivalid[27], out_wimask_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_27 = and(out_woready[27], out_womask_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[30], out_f_roready_27 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_335 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[30], out_f_woready_27 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_27 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[30], _out_T_335 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_336 = and(out_f_rivalid_27, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_337 = and(UInt<1>(0h1), out_f_roready_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_338 = and(out_f_wivalid_27, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_339 = and(UInt<1>(0h1), out_f_woready_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_340 = eq(out_rimask_27, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_341 = eq(out_wimask_27, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_342 = eq(out_romask_27, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_343 = eq(out_womask_27, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_21 = or(_out_T_334, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_21 = cat(_T_252, _out_prepend_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_344 = or(out_prepend_21, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_345 = bits(_out_T_344, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_28 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_28 = orr(_out_rimask_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_28 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_28 = andr(_out_wimask_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_28 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_28 = orr(_out_romask_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_28 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_28 = andr(_out_womask_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_28 = and(out_rivalid[28], out_rimask_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_28 = and(out_roready[28], out_romask_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_28 = and(out_wivalid[28], out_wimask_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_28 = and(out_woready[28], out_womask_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[31], out_f_roready_28 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_346 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[31], out_f_woready_28 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_28 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[31], _out_T_346 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_347 = and(out_f_rivalid_28, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_348 = and(UInt<1>(0h1), out_f_roready_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_349 = and(out_f_wivalid_28, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_350 = and(UInt<1>(0h1), out_f_woready_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_351 = eq(out_rimask_28, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_352 = eq(out_wimask_28, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_353 = eq(out_romask_28, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_354 = eq(out_womask_28, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_22 = or(_out_T_345, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_22 = cat(_T_253, _out_prepend_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_355 = or(out_prepend_22, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_356 = bits(_out_T_355, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_29 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_29 = orr(_out_rimask_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_29 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_29 = andr(_out_wimask_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_29 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_29 = orr(_out_romask_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_29 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_29 = andr(_out_womask_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_29 = and(out_rivalid[29], out_rimask_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_29 = and(out_roready[29], out_romask_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_29 = and(out_wivalid[29], out_wimask_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_29 = and(out_woready[29], out_womask_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[12], out_f_roready_29 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_357 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[12], out_f_woready_29 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_29 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[12], _out_T_357 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_358 = and(out_f_rivalid_29, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_359 = and(UInt<1>(0h1), out_f_roready_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_360 = and(out_f_wivalid_29, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_361 = and(UInt<1>(0h1), out_f_woready_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_362 = eq(out_rimask_29, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_363 = eq(out_wimask_29, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_364 = eq(out_romask_29, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_365 = eq(out_womask_29, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_366 = or(_T_234, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_367 = bits(_out_T_366, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_30 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_30 = orr(_out_rimask_T_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_30 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_30 = andr(_out_wimask_T_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_30 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_30 = orr(_out_romask_T_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_30 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_30 = andr(_out_womask_T_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_30 = and(out_rivalid[30], out_rimask_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_30 = and(out_roready[30], out_romask_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_30 = and(out_wivalid[30], out_wimask_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_30 = and(out_woready[30], out_womask_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[13], out_f_roready_30 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_368 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[13], out_f_woready_30 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_30 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[13], _out_T_368 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_369 = and(out_f_rivalid_30, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_370 = and(UInt<1>(0h1), out_f_roready_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_371 = and(out_f_wivalid_30, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_372 = and(UInt<1>(0h1), out_f_woready_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_373 = eq(out_rimask_30, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_374 = eq(out_wimask_30, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_375 = eq(out_romask_30, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_376 = eq(out_womask_30, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_23 = or(_out_T_367, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_23 = cat(_T_235, _out_prepend_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_377 = or(out_prepend_23, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_378 = bits(_out_T_377, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_31 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_31 = orr(_out_rimask_T_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_31 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_31 = andr(_out_wimask_T_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_31 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_31 = orr(_out_romask_T_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_31 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_31 = andr(_out_womask_T_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_31 = and(out_rivalid[31], out_rimask_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_31 = and(out_roready[31], out_romask_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_31 = and(out_wivalid[31], out_wimask_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_31 = and(out_woready[31], out_womask_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[14], out_f_roready_31 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_379 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[14], out_f_woready_31 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_31 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[14], _out_T_379 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_380 = and(out_f_rivalid_31, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_381 = and(UInt<1>(0h1), out_f_roready_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_382 = and(out_f_wivalid_31, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_383 = and(UInt<1>(0h1), out_f_woready_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_384 = eq(out_rimask_31, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_385 = eq(out_wimask_31, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_386 = eq(out_romask_31, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_387 = eq(out_womask_31, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_24 = or(_out_T_378, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_24 = cat(_T_236, _out_prepend_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_388 = or(out_prepend_24, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_389 = bits(_out_T_388, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_32 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_32 = orr(_out_rimask_T_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_32 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_32 = andr(_out_wimask_T_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_32 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_32 = orr(_out_romask_T_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_32 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_32 = andr(_out_womask_T_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_32 = and(out_rivalid[32], out_rimask_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_32 = and(out_roready[32], out_romask_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_32 = and(out_wivalid[32], out_wimask_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_32 = and(out_woready[32], out_womask_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[15], out_f_roready_32 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_390 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[15], out_f_woready_32 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_32 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[15], _out_T_390 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_391 = and(out_f_rivalid_32, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_392 = and(UInt<1>(0h1), out_f_roready_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_393 = and(out_f_wivalid_32, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_394 = and(UInt<1>(0h1), out_f_woready_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_395 = eq(out_rimask_32, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_396 = eq(out_wimask_32, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_397 = eq(out_romask_32, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_398 = eq(out_womask_32, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_25 = or(_out_T_389, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_25 = cat(_T_237, _out_prepend_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_399 = or(out_prepend_25, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_400 = bits(_out_T_399, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_33 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_33 = orr(_out_rimask_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_33 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_33 = andr(_out_wimask_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_33 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_33 = orr(_out_romask_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_33 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_33 = andr(_out_womask_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_33 = and(out_rivalid[33], out_rimask_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_33 = and(out_roready[33], out_romask_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_33 = and(out_wivalid[33], out_wimask_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_33 = and(out_woready[33], out_womask_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[44], out_f_roready_33 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_401 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[44], out_f_woready_33 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_33 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[44], _out_T_401 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_402 = and(out_f_rivalid_33, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_403 = and(UInt<1>(0h1), out_f_roready_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_404 = and(out_f_wivalid_33, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_405 = and(UInt<1>(0h1), out_f_woready_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_406 = eq(out_rimask_33, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_407 = eq(out_wimask_33, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_408 = eq(out_romask_33, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_409 = eq(out_womask_33, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_410 = or(_T_266, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_411 = bits(_out_T_410, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_34 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_34 = orr(_out_rimask_T_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_34 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_34 = andr(_out_wimask_T_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_34 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_34 = orr(_out_romask_T_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_34 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_34 = andr(_out_womask_T_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_34 = and(out_rivalid[34], out_rimask_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_34 = and(out_roready[34], out_romask_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_34 = and(out_wivalid[34], out_wimask_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_34 = and(out_woready[34], out_womask_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[45], out_f_roready_34 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_412 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[45], out_f_woready_34 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_34 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[45], _out_T_412 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_413 = and(out_f_rivalid_34, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_414 = and(UInt<1>(0h1), out_f_roready_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_415 = and(out_f_wivalid_34, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_416 = and(UInt<1>(0h1), out_f_woready_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_417 = eq(out_rimask_34, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_418 = eq(out_wimask_34, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_419 = eq(out_romask_34, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_420 = eq(out_womask_34, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_26 = or(_out_T_411, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_26 = cat(_T_267, _out_prepend_T_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_421 = or(out_prepend_26, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_422 = bits(_out_T_421, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_35 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_35 = orr(_out_rimask_T_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_35 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_35 = andr(_out_wimask_T_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_35 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_35 = orr(_out_romask_T_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_35 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_35 = andr(_out_womask_T_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_35 = and(out_rivalid[35], out_rimask_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_35 = and(out_roready[35], out_romask_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_35 = and(out_wivalid[35], out_wimask_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_35 = and(out_woready[35], out_womask_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[46], out_f_roready_35 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_423 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[46], out_f_woready_35 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_35 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[46], _out_T_423 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_424 = and(out_f_rivalid_35, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_425 = and(UInt<1>(0h1), out_f_roready_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_426 = and(out_f_wivalid_35, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_427 = and(UInt<1>(0h1), out_f_woready_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_428 = eq(out_rimask_35, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_429 = eq(out_wimask_35, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_430 = eq(out_romask_35, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_431 = eq(out_womask_35, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_27 = or(_out_T_422, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_27 = cat(_T_268, _out_prepend_T_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_432 = or(out_prepend_27, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_433 = bits(_out_T_432, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_36 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_36 = orr(_out_rimask_T_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_36 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_36 = andr(_out_wimask_T_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_36 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_36 = orr(_out_romask_T_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_36 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_36 = andr(_out_womask_T_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_36 = and(out_rivalid[36], out_rimask_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_36 = and(out_roready[36], out_romask_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_36 = and(out_wivalid[36], out_wimask_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_36 = and(out_woready[36], out_womask_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[47], out_f_roready_36 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_434 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[47], out_f_woready_36 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_36 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[47], _out_T_434 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_435 = and(out_f_rivalid_36, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_436 = and(UInt<1>(0h1), out_f_roready_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_437 = and(out_f_wivalid_36, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_438 = and(UInt<1>(0h1), out_f_woready_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_439 = eq(out_rimask_36, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_440 = eq(out_wimask_36, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_441 = eq(out_romask_36, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_442 = eq(out_womask_36, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_28 = or(_out_T_433, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_28 = cat(_T_269, _out_prepend_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_443 = or(out_prepend_28, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_444 = bits(_out_T_443, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_37 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_37 = orr(_out_rimask_T_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_37 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_37 = andr(_out_wimask_T_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_37 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_37 = orr(_out_romask_T_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_37 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_37 = andr(_out_womask_T_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_37 = and(out_rivalid[37], out_rimask_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_37 = and(out_roready[37], out_romask_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_37 = and(out_wivalid[37], out_wimask_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_37 = and(out_woready[37], out_womask_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiAbstractDataRdEn[0], out_f_roready_37 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_445 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiAbstractDataWrEnMaybe[0], out_f_woready_37 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_37 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect abstractDataNxt[0], _out_T_445 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_446 = and(out_f_rivalid_37, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_447 = and(UInt<1>(0h1), out_f_roready_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_448 = and(out_f_wivalid_37, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_449 = and(UInt<1>(0h1), out_f_woready_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_450 = eq(out_rimask_37, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_451 = eq(out_wimask_37, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_452 = eq(out_romask_37, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_453 = eq(out_womask_37, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_454 = or(_T_214, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_455 = bits(_out_T_454, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_38 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_38 = orr(_out_rimask_T_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_38 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_38 = andr(_out_wimask_T_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_38 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_38 = orr(_out_romask_T_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_38 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_38 = andr(_out_womask_T_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_38 = and(out_rivalid[38], out_rimask_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_38 = and(out_roready[38], out_romask_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_38 = and(out_wivalid[38], out_wimask_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_38 = and(out_woready[38], out_womask_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiAbstractDataRdEn[1], out_f_roready_38 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_456 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiAbstractDataWrEnMaybe[1], out_f_woready_38 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_38 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect abstractDataNxt[1], _out_T_456 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_457 = and(out_f_rivalid_38, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_458 = and(UInt<1>(0h1), out_f_roready_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_459 = and(out_f_wivalid_38, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_460 = and(UInt<1>(0h1), out_f_woready_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_461 = eq(out_rimask_38, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_462 = eq(out_wimask_38, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_463 = eq(out_romask_38, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_464 = eq(out_womask_38, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_29 = or(_out_T_455, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_29 = cat(_T_215, _out_prepend_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_465 = or(out_prepend_29, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_466 = bits(_out_T_465, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_39 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_39 = orr(_out_rimask_T_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_39 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_39 = andr(_out_wimask_T_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_39 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_39 = orr(_out_romask_T_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_39 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_39 = andr(_out_womask_T_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_39 = and(out_rivalid[39], out_rimask_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_39 = and(out_roready[39], out_romask_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_39 = and(out_wivalid[39], out_wimask_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_39 = and(out_woready[39], out_womask_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiAbstractDataRdEn[2], out_f_roready_39 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_467 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiAbstractDataWrEnMaybe[2], out_f_woready_39 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_39 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect abstractDataNxt[2], _out_T_467 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_468 = and(out_f_rivalid_39, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_469 = and(UInt<1>(0h1), out_f_roready_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_470 = and(out_f_wivalid_39, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_471 = and(UInt<1>(0h1), out_f_woready_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_472 = eq(out_rimask_39, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_473 = eq(out_wimask_39, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_474 = eq(out_romask_39, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_475 = eq(out_womask_39, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_30 = or(_out_T_466, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_30 = cat(_T_216, _out_prepend_T_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_476 = or(out_prepend_30, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_477 = bits(_out_T_476, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_40 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_40 = orr(_out_rimask_T_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_40 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_40 = andr(_out_wimask_T_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_40 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_40 = orr(_out_romask_T_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_40 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_40 = andr(_out_womask_T_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_40 = and(out_rivalid[40], out_rimask_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_40 = and(out_roready[40], out_romask_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_40 = and(out_wivalid[40], out_wimask_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_40 = and(out_woready[40], out_womask_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiAbstractDataRdEn[3], out_f_roready_40 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_478 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiAbstractDataWrEnMaybe[3], out_f_woready_40 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_40 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect abstractDataNxt[3], _out_T_478 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_479 = and(out_f_rivalid_40, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_480 = and(UInt<1>(0h1), out_f_roready_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_481 = and(out_f_wivalid_40, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_482 = and(UInt<1>(0h1), out_f_woready_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_483 = eq(out_rimask_40, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_484 = eq(out_wimask_40, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_485 = eq(out_romask_40, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_486 = eq(out_womask_40, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_31 = or(_out_T_477, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_31 = cat(_T_217, _out_prepend_T_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_487 = or(out_prepend_31, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_488 = bits(_out_T_487, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_41 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_41 = orr(_out_rimask_T_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_41 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_41 = andr(_out_wimask_T_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_41 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_41 = orr(_out_romask_T_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_41 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_41 = andr(_out_womask_T_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_41 = and(out_rivalid[41], out_rimask_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_41 = and(out_roready[41], out_romask_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_41 = and(out_wivalid[41], out_wimask_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_41 = and(out_woready[41], out_womask_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[60], out_f_roready_41 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_489 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[60], out_f_woready_41 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_41 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[60], _out_T_489 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_490 = and(out_f_rivalid_41, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_491 = and(UInt<1>(0h1), out_f_roready_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_492 = and(out_f_wivalid_41, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_493 = and(UInt<1>(0h1), out_f_woready_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_494 = eq(out_rimask_41, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_495 = eq(out_wimask_41, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_496 = eq(out_romask_41, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_497 = eq(out_womask_41, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_498 = or(_T_282, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_499 = bits(_out_T_498, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_42 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_42 = orr(_out_rimask_T_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_42 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_42 = andr(_out_wimask_T_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_42 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_42 = orr(_out_romask_T_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_42 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_42 = andr(_out_womask_T_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_42 = and(out_rivalid[42], out_rimask_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_42 = and(out_roready[42], out_romask_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_42 = and(out_wivalid[42], out_wimask_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_42 = and(out_woready[42], out_womask_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[61], out_f_roready_42 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_500 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[61], out_f_woready_42 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_42 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[61], _out_T_500 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_501 = and(out_f_rivalid_42, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_502 = and(UInt<1>(0h1), out_f_roready_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_503 = and(out_f_wivalid_42, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_504 = and(UInt<1>(0h1), out_f_woready_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_505 = eq(out_rimask_42, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_506 = eq(out_wimask_42, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_507 = eq(out_romask_42, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_508 = eq(out_womask_42, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_32 = or(_out_T_499, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_32 = cat(_T_283, _out_prepend_T_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_509 = or(out_prepend_32, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_510 = bits(_out_T_509, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_43 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_43 = orr(_out_rimask_T_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_43 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_43 = andr(_out_wimask_T_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_43 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_43 = orr(_out_romask_T_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_43 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_43 = andr(_out_womask_T_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_43 = and(out_rivalid[43], out_rimask_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_43 = and(out_roready[43], out_romask_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_43 = and(out_wivalid[43], out_wimask_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_43 = and(out_woready[43], out_womask_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[62], out_f_roready_43 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_511 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[62], out_f_woready_43 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_43 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[62], _out_T_511 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_512 = and(out_f_rivalid_43, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_513 = and(UInt<1>(0h1), out_f_roready_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_514 = and(out_f_wivalid_43, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_515 = and(UInt<1>(0h1), out_f_woready_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_516 = eq(out_rimask_43, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_517 = eq(out_wimask_43, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_518 = eq(out_romask_43, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_519 = eq(out_womask_43, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_33 = or(_out_T_510, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_33 = cat(_T_284, _out_prepend_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_520 = or(out_prepend_33, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_521 = bits(_out_T_520, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_44 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_44 = orr(_out_rimask_T_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_44 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_44 = andr(_out_wimask_T_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_44 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_44 = orr(_out_romask_T_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_44 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_44 = andr(_out_womask_T_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_44 = and(out_rivalid[44], out_rimask_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_44 = and(out_roready[44], out_romask_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_44 = and(out_wivalid[44], out_wimask_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_44 = and(out_woready[44], out_womask_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[63], out_f_roready_44 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_522 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[63], out_f_woready_44 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_44 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[63], _out_T_522 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_523 = and(out_f_rivalid_44, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_524 = and(UInt<1>(0h1), out_f_roready_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_525 = and(out_f_wivalid_44, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_526 = and(UInt<1>(0h1), out_f_woready_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_527 = eq(out_rimask_44, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_528 = eq(out_wimask_44, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_529 = eq(out_romask_44, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_530 = eq(out_womask_44, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_34 = or(_out_T_521, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_34 = cat(_T_285, _out_prepend_T_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_531 = or(out_prepend_34, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_532 = bits(_out_T_531, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_45 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_45 = orr(_out_rimask_T_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_45 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_45 = andr(_out_wimask_T_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_45 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_45 = orr(_out_romask_T_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_45 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_45 = andr(_out_womask_T_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_45 = and(out_rivalid[45], out_rimask_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_45 = and(out_roready[45], out_romask_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_45 = and(out_wivalid[45], out_wimask_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_45 = and(out_woready[45], out_womask_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[40], out_f_roready_45 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_533 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[40], out_f_woready_45 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_45 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[40], _out_T_533 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_534 = and(out_f_rivalid_45, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_535 = and(UInt<1>(0h1), out_f_roready_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_536 = and(out_f_wivalid_45, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_537 = and(UInt<1>(0h1), out_f_woready_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_538 = eq(out_rimask_45, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_539 = eq(out_wimask_45, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_540 = eq(out_romask_45, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_541 = eq(out_womask_45, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_542 = or(_T_262, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_543 = bits(_out_T_542, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_46 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_46 = orr(_out_rimask_T_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_46 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_46 = andr(_out_wimask_T_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_46 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_46 = orr(_out_romask_T_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_46 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_46 = andr(_out_womask_T_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_46 = and(out_rivalid[46], out_rimask_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_46 = and(out_roready[46], out_romask_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_46 = and(out_wivalid[46], out_wimask_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_46 = and(out_woready[46], out_womask_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[41], out_f_roready_46 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_544 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[41], out_f_woready_46 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_46 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[41], _out_T_544 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_545 = and(out_f_rivalid_46, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_546 = and(UInt<1>(0h1), out_f_roready_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_547 = and(out_f_wivalid_46, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_548 = and(UInt<1>(0h1), out_f_woready_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_549 = eq(out_rimask_46, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_550 = eq(out_wimask_46, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_551 = eq(out_romask_46, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_552 = eq(out_womask_46, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_35 = or(_out_T_543, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_35 = cat(_T_263, _out_prepend_T_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_553 = or(out_prepend_35, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_554 = bits(_out_T_553, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_47 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_47 = orr(_out_rimask_T_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_47 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_47 = andr(_out_wimask_T_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_47 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_47 = orr(_out_romask_T_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_47 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_47 = andr(_out_womask_T_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_47 = and(out_rivalid[47], out_rimask_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_47 = and(out_roready[47], out_romask_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_47 = and(out_wivalid[47], out_wimask_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_47 = and(out_woready[47], out_womask_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[42], out_f_roready_47 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_555 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[42], out_f_woready_47 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_47 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[42], _out_T_555 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_556 = and(out_f_rivalid_47, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_557 = and(UInt<1>(0h1), out_f_roready_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_558 = and(out_f_wivalid_47, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_559 = and(UInt<1>(0h1), out_f_woready_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_560 = eq(out_rimask_47, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_561 = eq(out_wimask_47, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_562 = eq(out_romask_47, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_563 = eq(out_womask_47, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_36 = or(_out_T_554, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_36 = cat(_T_264, _out_prepend_T_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_564 = or(out_prepend_36, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_565 = bits(_out_T_564, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_48 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_48 = orr(_out_rimask_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_48 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_48 = andr(_out_wimask_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_48 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_48 = orr(_out_romask_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_48 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_48 = andr(_out_womask_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_48 = and(out_rivalid[48], out_rimask_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_48 = and(out_roready[48], out_romask_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_48 = and(out_wivalid[48], out_wimask_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_48 = and(out_woready[48], out_womask_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[43], out_f_roready_48 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_566 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[43], out_f_woready_48 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_48 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[43], _out_T_566 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_567 = and(out_f_rivalid_48, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_568 = and(UInt<1>(0h1), out_f_roready_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_569 = and(out_f_wivalid_48, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_570 = and(UInt<1>(0h1), out_f_woready_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_571 = eq(out_rimask_48, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_572 = eq(out_wimask_48, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_573 = eq(out_romask_48, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_574 = eq(out_womask_48, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_37 = or(_out_T_565, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_37 = cat(_T_265, _out_prepend_T_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_575 = or(out_prepend_37, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_576 = bits(_out_T_575, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_49 = bits(out_frontMask, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_49 = orr(_out_rimask_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_49 = bits(out_frontMask, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_49 = andr(_out_wimask_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_49 = bits(out_backMask, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_49 = orr(_out_romask_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_49 = bits(out_backMask, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_49 = andr(_out_womask_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_49 = and(out_rivalid[49], out_rimask_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_49 = and(out_roready[49], out_romask_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_49 = and(out_wivalid[49], out_wimask_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_49 = and(out_woready[49], out_womask_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_577 = bits(out_front.bits.data, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect autoexecdataWrEnMaybe, out_f_woready_49 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 309:15] connect ABSTRACTAUTOWrData.autoexecdata, _out_T_577 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 310:12] node _out_T_578 = and(out_f_rivalid_49, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_579 = and(UInt<1>(0h1), out_f_roready_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_580 = and(out_f_wivalid_49, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_581 = and(UInt<1>(0h1), out_f_woready_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_582 = eq(out_rimask_49, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_583 = eq(out_wimask_49, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_584 = eq(out_romask_49, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_585 = eq(out_womask_49, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_586 = or(ABSTRACTAUTORdData.autoexecdata, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_587 = bits(_out_T_586, 1, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_50 = bits(out_frontMask, 15, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_50 = orr(_out_rimask_T_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_50 = bits(out_frontMask, 15, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_50 = andr(_out_wimask_T_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_50 = bits(out_backMask, 15, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_50 = orr(_out_romask_T_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_50 = bits(out_backMask, 15, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_50 = andr(_out_womask_T_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_50 = and(out_rivalid[50], out_rimask_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_50 = and(out_roready[50], out_romask_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_50 = and(out_wivalid[50], out_wimask_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_50 = and(out_woready[50], out_womask_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_588 = bits(out_front.bits.data, 15, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_589 = and(out_f_rivalid_50, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_590 = and(UInt<1>(0h1), out_f_roready_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_591 = eq(out_rimask_50, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_592 = eq(out_wimask_50, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_593 = eq(out_romask_50, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_594 = eq(out_womask_50, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_38 = or(_out_T_587, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_38 = cat(UInt<1>(0h0), _out_prepend_T_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_595 = or(out_prepend_38, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_596 = bits(_out_T_595, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_51 = bits(out_frontMask, 31, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_51 = orr(_out_rimask_T_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_51 = bits(out_frontMask, 31, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_51 = andr(_out_wimask_T_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_51 = bits(out_backMask, 31, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_51 = orr(_out_romask_T_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_51 = bits(out_backMask, 31, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_51 = andr(_out_womask_T_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_51 = and(out_rivalid[51], out_rimask_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_51 = and(out_roready[51], out_romask_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_51 = and(out_wivalid[51], out_wimask_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_51 = and(out_woready[51], out_womask_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_597 = bits(out_front.bits.data, 31, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect autoexecprogbufWrEnMaybe, out_f_woready_51 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 309:15] connect ABSTRACTAUTOWrData.autoexecprogbuf, _out_T_597 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 310:12] node _out_T_598 = and(out_f_rivalid_51, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_599 = and(UInt<1>(0h1), out_f_roready_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_600 = and(out_f_wivalid_51, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_601 = and(UInt<1>(0h1), out_f_woready_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_602 = eq(out_rimask_51, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_603 = eq(out_wimask_51, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_604 = eq(out_romask_51, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_605 = eq(out_womask_51, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_39 = or(_out_T_596, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_39 = cat(ABSTRACTAUTORdData.autoexecprogbuf, _out_prepend_T_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_606 = or(out_prepend_39, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_607 = bits(_out_T_606, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_52 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_52 = orr(_out_rimask_T_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_52 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_52 = andr(_out_wimask_T_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_52 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_52 = orr(_out_romask_T_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_52 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_52 = andr(_out_womask_T_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_52 = and(out_rivalid[52], out_rimask_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_52 = and(out_roready[52], out_romask_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_52 = and(out_wivalid[52], out_wimask_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_52 = and(out_woready[52], out_womask_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[20], out_f_roready_52 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_608 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[20], out_f_woready_52 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_52 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[20], _out_T_608 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_609 = and(out_f_rivalid_52, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_610 = and(UInt<1>(0h1), out_f_roready_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_611 = and(out_f_wivalid_52, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_612 = and(UInt<1>(0h1), out_f_woready_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_613 = eq(out_rimask_52, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_614 = eq(out_wimask_52, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_615 = eq(out_romask_52, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_616 = eq(out_womask_52, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_617 = or(_T_242, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_618 = bits(_out_T_617, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_53 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_53 = orr(_out_rimask_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_53 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_53 = andr(_out_wimask_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_53 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_53 = orr(_out_romask_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_53 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_53 = andr(_out_womask_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_53 = and(out_rivalid[53], out_rimask_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_53 = and(out_roready[53], out_romask_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_53 = and(out_wivalid[53], out_wimask_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_53 = and(out_woready[53], out_womask_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[21], out_f_roready_53 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_619 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[21], out_f_woready_53 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_53 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[21], _out_T_619 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_620 = and(out_f_rivalid_53, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_621 = and(UInt<1>(0h1), out_f_roready_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_622 = and(out_f_wivalid_53, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_623 = and(UInt<1>(0h1), out_f_woready_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_624 = eq(out_rimask_53, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_625 = eq(out_wimask_53, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_626 = eq(out_romask_53, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_627 = eq(out_womask_53, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_40 = or(_out_T_618, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_40 = cat(_T_243, _out_prepend_T_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_628 = or(out_prepend_40, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_629 = bits(_out_T_628, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_54 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_54 = orr(_out_rimask_T_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_54 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_54 = andr(_out_wimask_T_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_54 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_54 = orr(_out_romask_T_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_54 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_54 = andr(_out_womask_T_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_54 = and(out_rivalid[54], out_rimask_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_54 = and(out_roready[54], out_romask_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_54 = and(out_wivalid[54], out_wimask_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_54 = and(out_woready[54], out_womask_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[22], out_f_roready_54 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_630 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[22], out_f_woready_54 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_54 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[22], _out_T_630 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_631 = and(out_f_rivalid_54, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_632 = and(UInt<1>(0h1), out_f_roready_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_633 = and(out_f_wivalid_54, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_634 = and(UInt<1>(0h1), out_f_woready_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_635 = eq(out_rimask_54, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_636 = eq(out_wimask_54, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_637 = eq(out_romask_54, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_638 = eq(out_womask_54, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_41 = or(_out_T_629, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_41 = cat(_T_244, _out_prepend_T_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_639 = or(out_prepend_41, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_640 = bits(_out_T_639, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_55 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_55 = orr(_out_rimask_T_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_55 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_55 = andr(_out_wimask_T_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_55 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_55 = orr(_out_romask_T_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_55 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_55 = andr(_out_womask_T_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_55 = and(out_rivalid[55], out_rimask_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_55 = and(out_roready[55], out_romask_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_55 = and(out_wivalid[55], out_wimask_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_55 = and(out_woready[55], out_womask_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[23], out_f_roready_55 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_641 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[23], out_f_woready_55 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_55 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[23], _out_T_641 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_642 = and(out_f_rivalid_55, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_643 = and(UInt<1>(0h1), out_f_roready_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_644 = and(out_f_wivalid_55, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_645 = and(UInt<1>(0h1), out_f_woready_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_646 = eq(out_rimask_55, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_647 = eq(out_wimask_55, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_648 = eq(out_romask_55, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_649 = eq(out_womask_55, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_42 = or(_out_T_640, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_42 = cat(_T_245, _out_prepend_T_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_650 = or(out_prepend_42, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_651 = bits(_out_T_650, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_56 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_56 = orr(_out_rimask_T_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_56 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_56 = andr(_out_wimask_T_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_56 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_56 = orr(_out_romask_T_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_56 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_56 = andr(_out_womask_T_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_56 = and(out_rivalid[56], out_rimask_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_56 = and(out_roready[56], out_romask_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_56 = and(out_wivalid[56], out_wimask_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_56 = and(out_woready[56], out_womask_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[56], out_f_roready_56 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_652 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[56], out_f_woready_56 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_56 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[56], _out_T_652 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_653 = and(out_f_rivalid_56, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_654 = and(UInt<1>(0h1), out_f_roready_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_655 = and(out_f_wivalid_56, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_656 = and(UInt<1>(0h1), out_f_woready_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_657 = eq(out_rimask_56, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_658 = eq(out_wimask_56, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_659 = eq(out_romask_56, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_660 = eq(out_womask_56, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_661 = or(_T_278, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_662 = bits(_out_T_661, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_57 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_57 = orr(_out_rimask_T_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_57 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_57 = andr(_out_wimask_T_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_57 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_57 = orr(_out_romask_T_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_57 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_57 = andr(_out_womask_T_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_57 = and(out_rivalid[57], out_rimask_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_57 = and(out_roready[57], out_romask_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_57 = and(out_wivalid[57], out_wimask_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_57 = and(out_woready[57], out_womask_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[57], out_f_roready_57 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_663 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[57], out_f_woready_57 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_57 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[57], _out_T_663 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_664 = and(out_f_rivalid_57, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_665 = and(UInt<1>(0h1), out_f_roready_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_666 = and(out_f_wivalid_57, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_667 = and(UInt<1>(0h1), out_f_woready_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_668 = eq(out_rimask_57, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_669 = eq(out_wimask_57, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_670 = eq(out_romask_57, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_671 = eq(out_womask_57, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_43 = or(_out_T_662, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_43 = cat(_T_279, _out_prepend_T_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_672 = or(out_prepend_43, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_673 = bits(_out_T_672, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_58 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_58 = orr(_out_rimask_T_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_58 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_58 = andr(_out_wimask_T_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_58 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_58 = orr(_out_romask_T_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_58 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_58 = andr(_out_womask_T_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_58 = and(out_rivalid[58], out_rimask_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_58 = and(out_roready[58], out_romask_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_58 = and(out_wivalid[58], out_wimask_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_58 = and(out_woready[58], out_womask_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[58], out_f_roready_58 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_674 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[58], out_f_woready_58 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_58 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[58], _out_T_674 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_675 = and(out_f_rivalid_58, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_676 = and(UInt<1>(0h1), out_f_roready_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_677 = and(out_f_wivalid_58, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_678 = and(UInt<1>(0h1), out_f_woready_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_679 = eq(out_rimask_58, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_680 = eq(out_wimask_58, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_681 = eq(out_romask_58, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_682 = eq(out_womask_58, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_44 = or(_out_T_673, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_44 = cat(_T_280, _out_prepend_T_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_683 = or(out_prepend_44, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_684 = bits(_out_T_683, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_59 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_59 = orr(_out_rimask_T_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_59 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_59 = andr(_out_wimask_T_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_59 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_59 = orr(_out_romask_T_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_59 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_59 = andr(_out_womask_T_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_59 = and(out_rivalid[59], out_rimask_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_59 = and(out_roready[59], out_romask_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_59 = and(out_wivalid[59], out_wimask_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_59 = and(out_woready[59], out_womask_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[59], out_f_roready_59 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_685 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[59], out_f_woready_59 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_59 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[59], _out_T_685 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_686 = and(out_f_rivalid_59, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_687 = and(UInt<1>(0h1), out_f_roready_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_688 = and(out_f_wivalid_59, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_689 = and(UInt<1>(0h1), out_f_woready_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_690 = eq(out_rimask_59, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_691 = eq(out_wimask_59, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_692 = eq(out_romask_59, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_693 = eq(out_womask_59, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_45 = or(_out_T_684, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_45 = cat(_T_281, _out_prepend_T_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_694 = or(out_prepend_45, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_695 = bits(_out_T_694, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_60 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_60 = orr(_out_rimask_T_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_60 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_60 = andr(_out_wimask_T_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_60 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_60 = orr(_out_romask_T_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_60 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_60 = andr(_out_womask_T_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_60 = and(out_rivalid[60], out_rimask_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_60 = and(out_roready[60], out_romask_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_60 = and(out_wivalid[60], out_wimask_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_60 = and(out_woready[60], out_womask_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect SBADDRESSRdEn[0], out_f_roready_60 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_696 = bits(out_front.bits.data, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect SBADDRESSWrEn[0], out_f_woready_60 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_60 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect SBADDRESSWrData[0], _out_T_696 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_697 = and(out_f_rivalid_60, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_698 = and(UInt<1>(0h1), out_f_roready_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_699 = and(out_f_wivalid_60, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_700 = and(UInt<1>(0h1), out_f_woready_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_701 = eq(out_rimask_60, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_702 = eq(out_wimask_60, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_703 = eq(out_romask_60, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_704 = eq(out_womask_60, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_705 = or(SBADDRESSFieldsReg[0], UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_706 = bits(_out_T_705, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_61 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_61 = orr(_out_rimask_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_61 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_61 = andr(_out_wimask_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_61 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_61 = orr(_out_romask_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_61 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_61 = andr(_out_womask_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_61 = and(out_rivalid[61], out_rimask_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_61 = and(out_roready[61], out_romask_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_61 = and(out_wivalid[61], out_wimask_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_61 = and(out_woready[61], out_womask_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[24], out_f_roready_61 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_707 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[24], out_f_woready_61 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_61 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[24], _out_T_707 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_708 = and(out_f_rivalid_61, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_709 = and(UInt<1>(0h1), out_f_roready_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_710 = and(out_f_wivalid_61, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_711 = and(UInt<1>(0h1), out_f_woready_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_712 = eq(out_rimask_61, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_713 = eq(out_wimask_61, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_714 = eq(out_romask_61, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_715 = eq(out_womask_61, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_716 = or(_T_246, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_717 = bits(_out_T_716, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_62 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_62 = orr(_out_rimask_T_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_62 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_62 = andr(_out_wimask_T_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_62 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_62 = orr(_out_romask_T_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_62 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_62 = andr(_out_womask_T_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_62 = and(out_rivalid[62], out_rimask_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_62 = and(out_roready[62], out_romask_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_62 = and(out_wivalid[62], out_wimask_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_62 = and(out_woready[62], out_womask_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[25], out_f_roready_62 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_718 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[25], out_f_woready_62 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_62 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[25], _out_T_718 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_719 = and(out_f_rivalid_62, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_720 = and(UInt<1>(0h1), out_f_roready_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_721 = and(out_f_wivalid_62, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_722 = and(UInt<1>(0h1), out_f_woready_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_723 = eq(out_rimask_62, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_724 = eq(out_wimask_62, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_725 = eq(out_romask_62, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_726 = eq(out_womask_62, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_46 = or(_out_T_717, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_46 = cat(_T_247, _out_prepend_T_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_727 = or(out_prepend_46, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_728 = bits(_out_T_727, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_63 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_63 = orr(_out_rimask_T_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_63 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_63 = andr(_out_wimask_T_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_63 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_63 = orr(_out_romask_T_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_63 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_63 = andr(_out_womask_T_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_63 = and(out_rivalid[63], out_rimask_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_63 = and(out_roready[63], out_romask_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_63 = and(out_wivalid[63], out_wimask_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_63 = and(out_woready[63], out_womask_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[26], out_f_roready_63 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_729 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[26], out_f_woready_63 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_63 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[26], _out_T_729 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_730 = and(out_f_rivalid_63, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_731 = and(UInt<1>(0h1), out_f_roready_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_732 = and(out_f_wivalid_63, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_733 = and(UInt<1>(0h1), out_f_woready_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_734 = eq(out_rimask_63, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_735 = eq(out_wimask_63, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_736 = eq(out_romask_63, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_737 = eq(out_womask_63, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_47 = or(_out_T_728, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_47 = cat(_T_248, _out_prepend_T_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_738 = or(out_prepend_47, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_739 = bits(_out_T_738, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_64 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_64 = orr(_out_rimask_T_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_64 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_64 = andr(_out_wimask_T_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_64 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_64 = orr(_out_romask_T_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_64 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_64 = andr(_out_womask_T_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_64 = and(out_rivalid[64], out_rimask_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_64 = and(out_roready[64], out_romask_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_64 = and(out_wivalid[64], out_wimask_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_64 = and(out_woready[64], out_womask_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[27], out_f_roready_64 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_740 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[27], out_f_woready_64 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_64 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[27], _out_T_740 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_741 = and(out_f_rivalid_64, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_742 = and(UInt<1>(0h1), out_f_roready_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_743 = and(out_f_wivalid_64, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_744 = and(UInt<1>(0h1), out_f_woready_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_745 = eq(out_rimask_64, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_746 = eq(out_wimask_64, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_747 = eq(out_romask_64, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_748 = eq(out_womask_64, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_48 = or(_out_T_739, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_48 = cat(_T_249, _out_prepend_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_749 = or(out_prepend_48, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_750 = bits(_out_T_749, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_65 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_65 = orr(_out_rimask_T_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_65 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_65 = andr(_out_wimask_T_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_65 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_65 = orr(_out_romask_T_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_65 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_65 = andr(_out_womask_T_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_65 = and(out_rivalid[65], out_rimask_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_65 = and(out_roready[65], out_romask_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_65 = and(out_wivalid[65], out_wimask_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_65 = and(out_woready[65], out_womask_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[4], out_f_roready_65 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_751 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[4], out_f_woready_65 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_65 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[4], _out_T_751 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_752 = and(out_f_rivalid_65, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_753 = and(UInt<1>(0h1), out_f_roready_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_754 = and(out_f_wivalid_65, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_755 = and(UInt<1>(0h1), out_f_woready_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_756 = eq(out_rimask_65, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_757 = eq(out_wimask_65, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_758 = eq(out_romask_65, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_759 = eq(out_womask_65, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_760 = or(_T_226, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_761 = bits(_out_T_760, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_66 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_66 = orr(_out_rimask_T_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_66 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_66 = andr(_out_wimask_T_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_66 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_66 = orr(_out_romask_T_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_66 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_66 = andr(_out_womask_T_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_66 = and(out_rivalid[66], out_rimask_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_66 = and(out_roready[66], out_romask_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_66 = and(out_wivalid[66], out_wimask_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_66 = and(out_woready[66], out_womask_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[5], out_f_roready_66 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_762 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[5], out_f_woready_66 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_66 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[5], _out_T_762 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_763 = and(out_f_rivalid_66, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_764 = and(UInt<1>(0h1), out_f_roready_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_765 = and(out_f_wivalid_66, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_766 = and(UInt<1>(0h1), out_f_woready_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_767 = eq(out_rimask_66, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_768 = eq(out_wimask_66, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_769 = eq(out_romask_66, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_770 = eq(out_womask_66, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_49 = or(_out_T_761, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_49 = cat(_T_227, _out_prepend_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_771 = or(out_prepend_49, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_772 = bits(_out_T_771, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_67 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_67 = orr(_out_rimask_T_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_67 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_67 = andr(_out_wimask_T_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_67 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_67 = orr(_out_romask_T_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_67 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_67 = andr(_out_womask_T_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_67 = and(out_rivalid[67], out_rimask_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_67 = and(out_roready[67], out_romask_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_67 = and(out_wivalid[67], out_wimask_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_67 = and(out_woready[67], out_womask_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[6], out_f_roready_67 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_773 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[6], out_f_woready_67 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_67 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[6], _out_T_773 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_774 = and(out_f_rivalid_67, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_775 = and(UInt<1>(0h1), out_f_roready_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_776 = and(out_f_wivalid_67, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_777 = and(UInt<1>(0h1), out_f_woready_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_778 = eq(out_rimask_67, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_779 = eq(out_wimask_67, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_780 = eq(out_romask_67, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_781 = eq(out_womask_67, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_50 = or(_out_T_772, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_50 = cat(_T_228, _out_prepend_T_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_782 = or(out_prepend_50, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_783 = bits(_out_T_782, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_68 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_68 = orr(_out_rimask_T_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_68 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_68 = andr(_out_wimask_T_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_68 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_68 = orr(_out_romask_T_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_68 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_68 = andr(_out_womask_T_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_68 = and(out_rivalid[68], out_rimask_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_68 = and(out_roready[68], out_romask_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_68 = and(out_wivalid[68], out_wimask_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_68 = and(out_woready[68], out_womask_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[7], out_f_roready_68 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_784 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[7], out_f_woready_68 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_68 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[7], _out_T_784 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_785 = and(out_f_rivalid_68, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_786 = and(UInt<1>(0h1), out_f_roready_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_787 = and(out_f_wivalid_68, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_788 = and(UInt<1>(0h1), out_f_woready_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_789 = eq(out_rimask_68, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_790 = eq(out_wimask_68, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_791 = eq(out_romask_68, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_792 = eq(out_womask_68, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_51 = or(_out_T_783, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_51 = cat(_T_229, _out_prepend_T_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_793 = or(out_prepend_51, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_794 = bits(_out_T_793, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_69 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_69 = orr(_out_rimask_T_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_69 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_69 = andr(_out_wimask_T_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_69 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_69 = orr(_out_romask_T_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_69 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_69 = andr(_out_womask_T_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_69 = and(out_rivalid[69], out_rimask_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_69 = and(out_roready[69], out_romask_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_69 = and(out_wivalid[69], out_wimask_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_69 = and(out_woready[69], out_womask_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[52], out_f_roready_69 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_795 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[52], out_f_woready_69 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_69 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[52], _out_T_795 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_796 = and(out_f_rivalid_69, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_797 = and(UInt<1>(0h1), out_f_roready_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_798 = and(out_f_wivalid_69, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_799 = and(UInt<1>(0h1), out_f_woready_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_800 = eq(out_rimask_69, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_801 = eq(out_wimask_69, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_802 = eq(out_romask_69, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_803 = eq(out_womask_69, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_804 = or(_T_274, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_805 = bits(_out_T_804, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_70 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_70 = orr(_out_rimask_T_70) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_70 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_70 = andr(_out_wimask_T_70) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_70 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_70 = orr(_out_romask_T_70) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_70 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_70 = andr(_out_womask_T_70) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_70 = and(out_rivalid[70], out_rimask_70) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_70 = and(out_roready[70], out_romask_70) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_70 = and(out_wivalid[70], out_wimask_70) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_70 = and(out_woready[70], out_womask_70) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[53], out_f_roready_70 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_806 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[53], out_f_woready_70 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_70 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[53], _out_T_806 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_807 = and(out_f_rivalid_70, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_808 = and(UInt<1>(0h1), out_f_roready_70) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_809 = and(out_f_wivalid_70, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_810 = and(UInt<1>(0h1), out_f_woready_70) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_811 = eq(out_rimask_70, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_812 = eq(out_wimask_70, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_813 = eq(out_romask_70, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_814 = eq(out_womask_70, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_52 = or(_out_T_805, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_52 = cat(_T_275, _out_prepend_T_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_815 = or(out_prepend_52, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_816 = bits(_out_T_815, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_71 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_71 = orr(_out_rimask_T_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_71 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_71 = andr(_out_wimask_T_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_71 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_71 = orr(_out_romask_T_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_71 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_71 = andr(_out_womask_T_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_71 = and(out_rivalid[71], out_rimask_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_71 = and(out_roready[71], out_romask_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_71 = and(out_wivalid[71], out_wimask_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_71 = and(out_woready[71], out_womask_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[54], out_f_roready_71 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_817 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[54], out_f_woready_71 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_71 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[54], _out_T_817 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_818 = and(out_f_rivalid_71, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_819 = and(UInt<1>(0h1), out_f_roready_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_820 = and(out_f_wivalid_71, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_821 = and(UInt<1>(0h1), out_f_woready_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_822 = eq(out_rimask_71, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_823 = eq(out_wimask_71, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_824 = eq(out_romask_71, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_825 = eq(out_womask_71, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_53 = or(_out_T_816, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_53 = cat(_T_276, _out_prepend_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_826 = or(out_prepend_53, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_827 = bits(_out_T_826, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_72 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_72 = orr(_out_rimask_T_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_72 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_72 = andr(_out_wimask_T_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_72 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_72 = orr(_out_romask_T_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_72 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_72 = andr(_out_womask_T_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_72 = and(out_rivalid[72], out_rimask_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_72 = and(out_roready[72], out_romask_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_72 = and(out_wivalid[72], out_wimask_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_72 = and(out_woready[72], out_womask_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[55], out_f_roready_72 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_828 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[55], out_f_woready_72 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_72 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[55], _out_T_828 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_829 = and(out_f_rivalid_72, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_830 = and(UInt<1>(0h1), out_f_roready_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_831 = and(out_f_wivalid_72, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_832 = and(UInt<1>(0h1), out_f_woready_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_833 = eq(out_rimask_72, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_834 = eq(out_wimask_72, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_835 = eq(out_romask_72, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_836 = eq(out_womask_72, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_54 = or(_out_T_827, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_54 = cat(_T_277, _out_prepend_T_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_837 = or(out_prepend_54, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_838 = bits(_out_T_837, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_73 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_73 = orr(_out_rimask_T_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_73 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_73 = andr(_out_wimask_T_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_73 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_73 = orr(_out_romask_T_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_73 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_73 = andr(_out_womask_T_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_73 = and(out_rivalid[73], out_rimask_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_73 = and(out_roready[73], out_romask_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_73 = and(out_wivalid[73], out_wimask_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_73 = and(out_woready[73], out_womask_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_839 = bits(out_front.bits.data, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_840 = and(out_f_rivalid_73, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_841 = and(UInt<1>(0h1), out_f_roready_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_842 = eq(out_rimask_73, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_843 = eq(out_wimask_73, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_844 = eq(out_romask_73, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_845 = eq(out_womask_73, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_846 = or(HALTSUM0RdData.haltsum0, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_847 = bits(_out_T_846, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_74 = bits(out_frontMask, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_74 = orr(_out_rimask_T_74) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_74 = bits(out_frontMask, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_74 = andr(_out_wimask_T_74) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_74 = bits(out_backMask, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_74 = orr(_out_romask_T_74) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_74 = bits(out_backMask, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_74 = andr(_out_womask_T_74) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_74 = and(out_rivalid[74], out_rimask_74) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_74 = and(out_roready[74], out_romask_74) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_74 = and(out_wivalid[74], out_wimask_74) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_74 = and(out_woready[74], out_womask_74) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_848 = bits(out_front.bits.data, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_849 = and(out_f_rivalid_74, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_850 = and(UInt<1>(0h1), out_f_roready_74) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_851 = eq(out_rimask_74, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_852 = eq(out_wimask_74, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_853 = eq(out_romask_74, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_854 = eq(out_womask_74, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_855 = or(DMSTATUSRdData.version, UInt<4>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_856 = bits(_out_T_855, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_75 = bits(out_frontMask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_75 = orr(_out_rimask_T_75) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_75 = bits(out_frontMask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_75 = andr(_out_wimask_T_75) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_75 = bits(out_backMask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_75 = orr(_out_romask_T_75) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_75 = bits(out_backMask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_75 = andr(_out_womask_T_75) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_75 = and(out_rivalid[75], out_rimask_75) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_75 = and(out_roready[75], out_romask_75) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_75 = and(out_wivalid[75], out_wimask_75) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_75 = and(out_woready[75], out_womask_75) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_857 = bits(out_front.bits.data, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_858 = and(out_f_rivalid_75, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_859 = and(UInt<1>(0h1), out_f_roready_75) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_860 = eq(out_rimask_75, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_861 = eq(out_wimask_75, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_862 = eq(out_romask_75, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_863 = eq(out_womask_75, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_55 = or(_out_T_856, UInt<4>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_55 = cat(DMSTATUSRdData.confstrptrvalid, _out_prepend_T_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_864 = or(out_prepend_55, UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_865 = bits(_out_T_864, 4, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_76 = bits(out_frontMask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_76 = orr(_out_rimask_T_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_76 = bits(out_frontMask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_76 = andr(_out_wimask_T_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_76 = bits(out_backMask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_76 = orr(_out_romask_T_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_76 = bits(out_backMask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_76 = andr(_out_womask_T_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_76 = and(out_rivalid[76], out_rimask_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_76 = and(out_roready[76], out_romask_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_76 = and(out_wivalid[76], out_wimask_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_76 = and(out_woready[76], out_womask_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_866 = bits(out_front.bits.data, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_867 = and(out_f_rivalid_76, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_868 = and(UInt<1>(0h1), out_f_roready_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_869 = eq(out_rimask_76, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_870 = eq(out_wimask_76, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_871 = eq(out_romask_76, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_872 = eq(out_womask_76, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_56 = or(_out_T_865, UInt<5>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_56 = cat(DMSTATUSRdData.hasresethaltreq, _out_prepend_T_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_873 = or(out_prepend_56, UInt<6>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_874 = bits(_out_T_873, 5, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_77 = bits(out_frontMask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_77 = orr(_out_rimask_T_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_77 = bits(out_frontMask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_77 = andr(_out_wimask_T_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_77 = bits(out_backMask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_77 = orr(_out_romask_T_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_77 = bits(out_backMask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_77 = andr(_out_womask_T_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_77 = and(out_rivalid[77], out_rimask_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_77 = and(out_roready[77], out_romask_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_77 = and(out_wivalid[77], out_wimask_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_77 = and(out_woready[77], out_womask_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_875 = bits(out_front.bits.data, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_876 = and(out_f_rivalid_77, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_877 = and(UInt<1>(0h1), out_f_roready_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_878 = eq(out_rimask_77, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_879 = eq(out_wimask_77, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_880 = eq(out_romask_77, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_881 = eq(out_womask_77, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_57 = or(_out_T_874, UInt<6>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_57 = cat(DMSTATUSRdData.authbusy, _out_prepend_T_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_882 = or(out_prepend_57, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_883 = bits(_out_T_882, 6, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_78 = bits(out_frontMask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_78 = orr(_out_rimask_T_78) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_78 = bits(out_frontMask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_78 = andr(_out_wimask_T_78) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_78 = bits(out_backMask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_78 = orr(_out_romask_T_78) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_78 = bits(out_backMask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_78 = andr(_out_womask_T_78) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_78 = and(out_rivalid[78], out_rimask_78) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_78 = and(out_roready[78], out_romask_78) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_78 = and(out_wivalid[78], out_wimask_78) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_78 = and(out_woready[78], out_womask_78) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_884 = bits(out_front.bits.data, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_885 = and(out_f_rivalid_78, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_886 = and(UInt<1>(0h1), out_f_roready_78) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_887 = eq(out_rimask_78, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_888 = eq(out_wimask_78, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_889 = eq(out_romask_78, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_890 = eq(out_womask_78, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_58 = or(_out_T_883, UInt<7>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_58 = cat(DMSTATUSRdData.authenticated, _out_prepend_T_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_891 = or(out_prepend_58, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_892 = bits(_out_T_891, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_79 = bits(out_frontMask, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_79 = orr(_out_rimask_T_79) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_79 = bits(out_frontMask, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_79 = andr(_out_wimask_T_79) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_79 = bits(out_backMask, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_79 = orr(_out_romask_T_79) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_79 = bits(out_backMask, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_79 = andr(_out_womask_T_79) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_79 = and(out_rivalid[79], out_rimask_79) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_79 = and(out_roready[79], out_romask_79) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_79 = and(out_wivalid[79], out_wimask_79) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_79 = and(out_woready[79], out_womask_79) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_893 = bits(out_front.bits.data, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_894 = and(out_f_rivalid_79, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_895 = and(UInt<1>(0h1), out_f_roready_79) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_896 = eq(out_rimask_79, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_897 = eq(out_wimask_79, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_898 = eq(out_romask_79, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_899 = eq(out_womask_79, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_59 = or(_out_T_892, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_59 = cat(DMSTATUSRdData.anyhalted, _out_prepend_T_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_900 = or(out_prepend_59, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_901 = bits(_out_T_900, 8, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_80 = bits(out_frontMask, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_80 = orr(_out_rimask_T_80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_80 = bits(out_frontMask, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_80 = andr(_out_wimask_T_80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_80 = bits(out_backMask, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_80 = orr(_out_romask_T_80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_80 = bits(out_backMask, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_80 = andr(_out_womask_T_80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_80 = and(out_rivalid[80], out_rimask_80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_80 = and(out_roready[80], out_romask_80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_80 = and(out_wivalid[80], out_wimask_80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_80 = and(out_woready[80], out_womask_80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_902 = bits(out_front.bits.data, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_903 = and(out_f_rivalid_80, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_904 = and(UInt<1>(0h1), out_f_roready_80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_905 = eq(out_rimask_80, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_906 = eq(out_wimask_80, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_907 = eq(out_romask_80, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_908 = eq(out_womask_80, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_60 = or(_out_T_901, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_60 = cat(DMSTATUSRdData.allhalted, _out_prepend_T_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_909 = or(out_prepend_60, UInt<10>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_910 = bits(_out_T_909, 9, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_81 = bits(out_frontMask, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_81 = orr(_out_rimask_T_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_81 = bits(out_frontMask, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_81 = andr(_out_wimask_T_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_81 = bits(out_backMask, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_81 = orr(_out_romask_T_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_81 = bits(out_backMask, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_81 = andr(_out_womask_T_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_81 = and(out_rivalid[81], out_rimask_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_81 = and(out_roready[81], out_romask_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_81 = and(out_wivalid[81], out_wimask_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_81 = and(out_woready[81], out_womask_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_911 = bits(out_front.bits.data, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_912 = and(out_f_rivalid_81, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_913 = and(UInt<1>(0h1), out_f_roready_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_914 = eq(out_rimask_81, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_915 = eq(out_wimask_81, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_916 = eq(out_romask_81, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_917 = eq(out_womask_81, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_61 = or(_out_T_910, UInt<10>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_61 = cat(DMSTATUSRdData.anyrunning, _out_prepend_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_918 = or(out_prepend_61, UInt<11>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_919 = bits(_out_T_918, 10, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_82 = bits(out_frontMask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_82 = orr(_out_rimask_T_82) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_82 = bits(out_frontMask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_82 = andr(_out_wimask_T_82) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_82 = bits(out_backMask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_82 = orr(_out_romask_T_82) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_82 = bits(out_backMask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_82 = andr(_out_womask_T_82) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_82 = and(out_rivalid[82], out_rimask_82) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_82 = and(out_roready[82], out_romask_82) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_82 = and(out_wivalid[82], out_wimask_82) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_82 = and(out_woready[82], out_womask_82) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_920 = bits(out_front.bits.data, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_921 = and(out_f_rivalid_82, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_922 = and(UInt<1>(0h1), out_f_roready_82) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_923 = eq(out_rimask_82, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_924 = eq(out_wimask_82, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_925 = eq(out_romask_82, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_926 = eq(out_womask_82, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_62 = or(_out_T_919, UInt<11>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_62 = cat(DMSTATUSRdData.allrunning, _out_prepend_T_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_927 = or(out_prepend_62, UInt<12>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_928 = bits(_out_T_927, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_83 = bits(out_frontMask, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_83 = orr(_out_rimask_T_83) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_83 = bits(out_frontMask, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_83 = andr(_out_wimask_T_83) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_83 = bits(out_backMask, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_83 = orr(_out_romask_T_83) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_83 = bits(out_backMask, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_83 = andr(_out_womask_T_83) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_83 = and(out_rivalid[83], out_rimask_83) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_83 = and(out_roready[83], out_romask_83) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_83 = and(out_wivalid[83], out_wimask_83) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_83 = and(out_woready[83], out_womask_83) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_929 = bits(out_front.bits.data, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_930 = and(out_f_rivalid_83, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_931 = and(UInt<1>(0h1), out_f_roready_83) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_932 = eq(out_rimask_83, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_933 = eq(out_wimask_83, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_934 = eq(out_romask_83, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_935 = eq(out_womask_83, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_63 = or(_out_T_928, UInt<12>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_63 = cat(DMSTATUSRdData.anyunavail, _out_prepend_T_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_936 = or(out_prepend_63, UInt<13>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_937 = bits(_out_T_936, 12, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_84 = bits(out_frontMask, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_84 = orr(_out_rimask_T_84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_84 = bits(out_frontMask, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_84 = andr(_out_wimask_T_84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_84 = bits(out_backMask, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_84 = orr(_out_romask_T_84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_84 = bits(out_backMask, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_84 = andr(_out_womask_T_84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_84 = and(out_rivalid[84], out_rimask_84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_84 = and(out_roready[84], out_romask_84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_84 = and(out_wivalid[84], out_wimask_84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_84 = and(out_woready[84], out_womask_84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_938 = bits(out_front.bits.data, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_939 = and(out_f_rivalid_84, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_940 = and(UInt<1>(0h1), out_f_roready_84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_941 = eq(out_rimask_84, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_942 = eq(out_wimask_84, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_943 = eq(out_romask_84, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_944 = eq(out_womask_84, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_64 = or(_out_T_937, UInt<13>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_64 = cat(DMSTATUSRdData.allunavail, _out_prepend_T_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_945 = or(out_prepend_64, UInt<14>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_946 = bits(_out_T_945, 13, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_85 = bits(out_frontMask, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_85 = orr(_out_rimask_T_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_85 = bits(out_frontMask, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_85 = andr(_out_wimask_T_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_85 = bits(out_backMask, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_85 = orr(_out_romask_T_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_85 = bits(out_backMask, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_85 = andr(_out_womask_T_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_85 = and(out_rivalid[85], out_rimask_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_85 = and(out_roready[85], out_romask_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_85 = and(out_wivalid[85], out_wimask_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_85 = and(out_woready[85], out_womask_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_947 = bits(out_front.bits.data, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_948 = and(out_f_rivalid_85, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_949 = and(UInt<1>(0h1), out_f_roready_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_950 = eq(out_rimask_85, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_951 = eq(out_wimask_85, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_952 = eq(out_romask_85, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_953 = eq(out_womask_85, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_65 = or(_out_T_946, UInt<14>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_65 = cat(DMSTATUSRdData.anynonexistent, _out_prepend_T_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_954 = or(out_prepend_65, UInt<15>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_955 = bits(_out_T_954, 14, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_86 = bits(out_frontMask, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_86 = orr(_out_rimask_T_86) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_86 = bits(out_frontMask, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_86 = andr(_out_wimask_T_86) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_86 = bits(out_backMask, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_86 = orr(_out_romask_T_86) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_86 = bits(out_backMask, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_86 = andr(_out_womask_T_86) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_86 = and(out_rivalid[86], out_rimask_86) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_86 = and(out_roready[86], out_romask_86) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_86 = and(out_wivalid[86], out_wimask_86) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_86 = and(out_woready[86], out_womask_86) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_956 = bits(out_front.bits.data, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_957 = and(out_f_rivalid_86, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_958 = and(UInt<1>(0h1), out_f_roready_86) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_959 = eq(out_rimask_86, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_960 = eq(out_wimask_86, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_961 = eq(out_romask_86, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_962 = eq(out_womask_86, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_66 = or(_out_T_955, UInt<15>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_66 = cat(DMSTATUSRdData.allnonexistent, _out_prepend_T_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_963 = or(out_prepend_66, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_964 = bits(_out_T_963, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_87 = bits(out_frontMask, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_87 = orr(_out_rimask_T_87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_87 = bits(out_frontMask, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_87 = andr(_out_wimask_T_87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_87 = bits(out_backMask, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_87 = orr(_out_romask_T_87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_87 = bits(out_backMask, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_87 = andr(_out_womask_T_87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_87 = and(out_rivalid[87], out_rimask_87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_87 = and(out_roready[87], out_romask_87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_87 = and(out_wivalid[87], out_wimask_87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_87 = and(out_woready[87], out_womask_87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_965 = bits(out_front.bits.data, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_966 = and(out_f_rivalid_87, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_967 = and(UInt<1>(0h1), out_f_roready_87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_968 = eq(out_rimask_87, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_969 = eq(out_wimask_87, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_970 = eq(out_romask_87, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_971 = eq(out_womask_87, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_67 = or(_out_T_964, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_67 = cat(DMSTATUSRdData.anyresumeack, _out_prepend_T_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_972 = or(out_prepend_67, UInt<17>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_973 = bits(_out_T_972, 16, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_88 = bits(out_frontMask, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_88 = orr(_out_rimask_T_88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_88 = bits(out_frontMask, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_88 = andr(_out_wimask_T_88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_88 = bits(out_backMask, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_88 = orr(_out_romask_T_88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_88 = bits(out_backMask, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_88 = andr(_out_womask_T_88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_88 = and(out_rivalid[88], out_rimask_88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_88 = and(out_roready[88], out_romask_88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_88 = and(out_wivalid[88], out_wimask_88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_88 = and(out_woready[88], out_womask_88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_974 = bits(out_front.bits.data, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_975 = and(out_f_rivalid_88, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_976 = and(UInt<1>(0h1), out_f_roready_88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_977 = eq(out_rimask_88, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_978 = eq(out_wimask_88, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_979 = eq(out_romask_88, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_980 = eq(out_womask_88, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_68 = or(_out_T_973, UInt<17>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_68 = cat(DMSTATUSRdData.allresumeack, _out_prepend_T_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_981 = or(out_prepend_68, UInt<18>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_982 = bits(_out_T_981, 17, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_89 = bits(out_frontMask, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_89 = orr(_out_rimask_T_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_89 = bits(out_frontMask, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_89 = andr(_out_wimask_T_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_89 = bits(out_backMask, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_89 = orr(_out_romask_T_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_89 = bits(out_backMask, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_89 = andr(_out_womask_T_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_89 = and(out_rivalid[89], out_rimask_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_89 = and(out_roready[89], out_romask_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_89 = and(out_wivalid[89], out_wimask_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_89 = and(out_woready[89], out_womask_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_983 = bits(out_front.bits.data, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_984 = and(out_f_rivalid_89, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_985 = and(UInt<1>(0h1), out_f_roready_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_986 = eq(out_rimask_89, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_987 = eq(out_wimask_89, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_988 = eq(out_romask_89, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_989 = eq(out_womask_89, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_69 = or(_out_T_982, UInt<18>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_69 = cat(DMSTATUSRdData.anyhavereset, _out_prepend_T_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_990 = or(out_prepend_69, UInt<19>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_991 = bits(_out_T_990, 18, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_90 = bits(out_frontMask, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_90 = orr(_out_rimask_T_90) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_90 = bits(out_frontMask, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_90 = andr(_out_wimask_T_90) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_90 = bits(out_backMask, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_90 = orr(_out_romask_T_90) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_90 = bits(out_backMask, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_90 = andr(_out_womask_T_90) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_90 = and(out_rivalid[90], out_rimask_90) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_90 = and(out_roready[90], out_romask_90) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_90 = and(out_wivalid[90], out_wimask_90) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_90 = and(out_woready[90], out_womask_90) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_992 = bits(out_front.bits.data, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_993 = and(out_f_rivalid_90, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_994 = and(UInt<1>(0h1), out_f_roready_90) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_995 = eq(out_rimask_90, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_996 = eq(out_wimask_90, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_997 = eq(out_romask_90, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_998 = eq(out_womask_90, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_70 = or(_out_T_991, UInt<19>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_70 = cat(DMSTATUSRdData.allhavereset, _out_prepend_T_70) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_999 = or(out_prepend_70, UInt<20>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1000 = bits(_out_T_999, 19, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_91 = bits(out_frontMask, 21, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_91 = orr(_out_rimask_T_91) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_91 = bits(out_frontMask, 21, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_91 = andr(_out_wimask_T_91) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_91 = bits(out_backMask, 21, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_91 = orr(_out_romask_T_91) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_91 = bits(out_backMask, 21, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_91 = andr(_out_womask_T_91) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_91 = and(out_rivalid[91], out_rimask_91) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_91 = and(out_roready[91], out_romask_91) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_91 = and(out_wivalid[91], out_wimask_91) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_91 = and(out_woready[91], out_womask_91) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1001 = bits(out_front.bits.data, 21, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1002 = and(out_f_rivalid_91, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1003 = and(UInt<1>(0h1), out_f_roready_91) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1004 = eq(out_rimask_91, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1005 = eq(out_wimask_91, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1006 = eq(out_romask_91, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1007 = eq(out_womask_91, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_71 = or(_out_T_1000, UInt<20>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_71 = cat(UInt<1>(0h0), _out_prepend_T_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1008 = or(out_prepend_71, UInt<22>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1009 = bits(_out_T_1008, 21, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_92 = bits(out_frontMask, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_92 = orr(_out_rimask_T_92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_92 = bits(out_frontMask, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_92 = andr(_out_wimask_T_92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_92 = bits(out_backMask, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_92 = orr(_out_romask_T_92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_92 = bits(out_backMask, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_92 = andr(_out_womask_T_92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_92 = and(out_rivalid[92], out_rimask_92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_92 = and(out_roready[92], out_romask_92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_92 = and(out_wivalid[92], out_wimask_92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_92 = and(out_woready[92], out_womask_92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1010 = bits(out_front.bits.data, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1011 = and(out_f_rivalid_92, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1012 = and(UInt<1>(0h1), out_f_roready_92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1013 = eq(out_rimask_92, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1014 = eq(out_wimask_92, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1015 = eq(out_romask_92, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1016 = eq(out_womask_92, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_72 = or(_out_T_1009, UInt<22>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_72 = cat(DMSTATUSRdData.impebreak, _out_prepend_T_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1017 = or(out_prepend_72, UInt<23>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1018 = bits(_out_T_1017, 22, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_93 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_93 = orr(_out_rimask_T_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_93 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_93 = andr(_out_wimask_T_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_93 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_93 = orr(_out_romask_T_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_93 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_93 = andr(_out_womask_T_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_93 = and(out_rivalid[93], out_rimask_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_93 = and(out_roready[93], out_romask_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_93 = and(out_wivalid[93], out_wimask_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_93 = and(out_woready[93], out_womask_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[0], out_f_roready_93 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1019 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[0], out_f_woready_93 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_93 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[0], _out_T_1019 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1020 = and(out_f_rivalid_93, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1021 = and(UInt<1>(0h1), out_f_roready_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1022 = and(out_f_wivalid_93, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1023 = and(UInt<1>(0h1), out_f_woready_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1024 = eq(out_rimask_93, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1025 = eq(out_wimask_93, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1026 = eq(out_romask_93, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1027 = eq(out_womask_93, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1028 = or(_T_222, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1029 = bits(_out_T_1028, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_94 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_94 = orr(_out_rimask_T_94) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_94 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_94 = andr(_out_wimask_T_94) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_94 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_94 = orr(_out_romask_T_94) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_94 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_94 = andr(_out_womask_T_94) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_94 = and(out_rivalid[94], out_rimask_94) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_94 = and(out_roready[94], out_romask_94) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_94 = and(out_wivalid[94], out_wimask_94) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_94 = and(out_woready[94], out_womask_94) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[1], out_f_roready_94 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1030 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[1], out_f_woready_94 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_94 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[1], _out_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1031 = and(out_f_rivalid_94, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1032 = and(UInt<1>(0h1), out_f_roready_94) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1033 = and(out_f_wivalid_94, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1034 = and(UInt<1>(0h1), out_f_woready_94) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1035 = eq(out_rimask_94, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1036 = eq(out_wimask_94, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1037 = eq(out_romask_94, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1038 = eq(out_womask_94, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_73 = or(_out_T_1029, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_73 = cat(_T_223, _out_prepend_T_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1039 = or(out_prepend_73, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1040 = bits(_out_T_1039, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_95 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_95 = orr(_out_rimask_T_95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_95 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_95 = andr(_out_wimask_T_95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_95 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_95 = orr(_out_romask_T_95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_95 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_95 = andr(_out_womask_T_95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_95 = and(out_rivalid[95], out_rimask_95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_95 = and(out_roready[95], out_romask_95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_95 = and(out_wivalid[95], out_wimask_95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_95 = and(out_woready[95], out_womask_95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[2], out_f_roready_95 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1041 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[2], out_f_woready_95 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_95 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[2], _out_T_1041 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1042 = and(out_f_rivalid_95, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1043 = and(UInt<1>(0h1), out_f_roready_95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1044 = and(out_f_wivalid_95, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1045 = and(UInt<1>(0h1), out_f_woready_95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1046 = eq(out_rimask_95, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1047 = eq(out_wimask_95, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1048 = eq(out_romask_95, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1049 = eq(out_womask_95, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_74 = or(_out_T_1040, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_74 = cat(_T_224, _out_prepend_T_74) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1050 = or(out_prepend_74, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1051 = bits(_out_T_1050, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_96 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_96 = orr(_out_rimask_T_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_96 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_96 = andr(_out_wimask_T_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_96 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_96 = orr(_out_romask_T_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_96 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_96 = andr(_out_womask_T_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_96 = and(out_rivalid[96], out_rimask_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_96 = and(out_roready[96], out_romask_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_96 = and(out_wivalid[96], out_wimask_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_96 = and(out_woready[96], out_womask_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[3], out_f_roready_96 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1052 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[3], out_f_woready_96 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_96 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[3], _out_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1053 = and(out_f_rivalid_96, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1054 = and(UInt<1>(0h1), out_f_roready_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1055 = and(out_f_wivalid_96, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1056 = and(UInt<1>(0h1), out_f_woready_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1057 = eq(out_rimask_96, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1058 = eq(out_wimask_96, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1059 = eq(out_romask_96, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1060 = eq(out_womask_96, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_75 = or(_out_T_1051, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_75 = cat(_T_225, _out_prepend_T_75) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1061 = or(out_prepend_75, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1062 = bits(_out_T_1061, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_97 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_97 = orr(_out_rimask_T_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_97 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_97 = andr(_out_wimask_T_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_97 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_97 = orr(_out_romask_T_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_97 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_97 = andr(_out_womask_T_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_97 = and(out_rivalid[97], out_rimask_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_97 = and(out_roready[97], out_romask_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_97 = and(out_wivalid[97], out_wimask_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_97 = and(out_woready[97], out_womask_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[8], out_f_roready_97 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1063 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[8], out_f_woready_97 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_97 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[8], _out_T_1063 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1064 = and(out_f_rivalid_97, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1065 = and(UInt<1>(0h1), out_f_roready_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1066 = and(out_f_wivalid_97, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1067 = and(UInt<1>(0h1), out_f_woready_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1068 = eq(out_rimask_97, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1069 = eq(out_wimask_97, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1070 = eq(out_romask_97, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1071 = eq(out_womask_97, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1072 = or(_T_230, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1073 = bits(_out_T_1072, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_98 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_98 = orr(_out_rimask_T_98) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_98 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_98 = andr(_out_wimask_T_98) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_98 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_98 = orr(_out_romask_T_98) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_98 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_98 = andr(_out_womask_T_98) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_98 = and(out_rivalid[98], out_rimask_98) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_98 = and(out_roready[98], out_romask_98) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_98 = and(out_wivalid[98], out_wimask_98) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_98 = and(out_woready[98], out_womask_98) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[9], out_f_roready_98 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1074 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[9], out_f_woready_98 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_98 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[9], _out_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1075 = and(out_f_rivalid_98, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1076 = and(UInt<1>(0h1), out_f_roready_98) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1077 = and(out_f_wivalid_98, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1078 = and(UInt<1>(0h1), out_f_woready_98) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1079 = eq(out_rimask_98, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1080 = eq(out_wimask_98, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1081 = eq(out_romask_98, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1082 = eq(out_womask_98, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_76 = or(_out_T_1073, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_76 = cat(_T_231, _out_prepend_T_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1083 = or(out_prepend_76, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1084 = bits(_out_T_1083, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_99 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_99 = orr(_out_rimask_T_99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_99 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_99 = andr(_out_wimask_T_99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_99 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_99 = orr(_out_romask_T_99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_99 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_99 = andr(_out_womask_T_99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_99 = and(out_rivalid[99], out_rimask_99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_99 = and(out_roready[99], out_romask_99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_99 = and(out_wivalid[99], out_wimask_99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_99 = and(out_woready[99], out_womask_99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[10], out_f_roready_99 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1085 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[10], out_f_woready_99 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_99 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[10], _out_T_1085 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1086 = and(out_f_rivalid_99, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1087 = and(UInt<1>(0h1), out_f_roready_99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1088 = and(out_f_wivalid_99, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1089 = and(UInt<1>(0h1), out_f_woready_99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1090 = eq(out_rimask_99, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1091 = eq(out_wimask_99, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1092 = eq(out_romask_99, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1093 = eq(out_womask_99, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_77 = or(_out_T_1084, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_77 = cat(_T_232, _out_prepend_T_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1094 = or(out_prepend_77, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1095 = bits(_out_T_1094, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_100 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_100 = orr(_out_rimask_T_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_100 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_100 = andr(_out_wimask_T_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_100 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_100 = orr(_out_romask_T_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_100 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_100 = andr(_out_womask_T_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_100 = and(out_rivalid[100], out_rimask_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_100 = and(out_roready[100], out_romask_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_100 = and(out_wivalid[100], out_wimask_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_100 = and(out_woready[100], out_womask_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[11], out_f_roready_100 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1096 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[11], out_f_woready_100 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_100 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[11], _out_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1097 = and(out_f_rivalid_100, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1098 = and(UInt<1>(0h1), out_f_roready_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1099 = and(out_f_wivalid_100, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1100 = and(UInt<1>(0h1), out_f_woready_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1101 = eq(out_rimask_100, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1102 = eq(out_wimask_100, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1103 = eq(out_romask_100, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1104 = eq(out_womask_100, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_78 = or(_out_T_1095, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_78 = cat(_T_233, _out_prepend_T_78) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1105 = or(out_prepend_78, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1106 = bits(_out_T_1105, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_101 = bits(out_frontMask, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_101 = orr(_out_rimask_T_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_101 = bits(out_frontMask, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_101 = andr(_out_wimask_T_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_101 = bits(out_backMask, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_101 = orr(_out_romask_T_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_101 = bits(out_backMask, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_101 = andr(_out_womask_T_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_101 = and(out_rivalid[101], out_rimask_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_101 = and(out_roready[101], out_romask_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_101 = and(out_wivalid[101], out_wimask_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_101 = and(out_woready[101], out_womask_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1107 = bits(out_front.bits.data, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1108 = and(out_f_rivalid_101, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1109 = and(UInt<1>(0h1), out_f_roready_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1110 = eq(out_rimask_101, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1111 = eq(out_wimask_101, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1112 = eq(out_romask_101, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1113 = eq(out_womask_101, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1114 = or(ABSTRACTCSRdData.datacount, UInt<4>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1115 = bits(_out_T_1114, 3, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_102 = bits(out_frontMask, 7, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_102 = orr(_out_rimask_T_102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_102 = bits(out_frontMask, 7, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_102 = andr(_out_wimask_T_102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_102 = bits(out_backMask, 7, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_102 = orr(_out_romask_T_102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_102 = bits(out_backMask, 7, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_102 = andr(_out_womask_T_102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_102 = and(out_rivalid[102], out_rimask_102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_102 = and(out_roready[102], out_romask_102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_102 = and(out_wivalid[102], out_wimask_102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_102 = and(out_woready[102], out_womask_102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1116 = bits(out_front.bits.data, 7, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1117 = and(out_f_rivalid_102, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1118 = and(UInt<1>(0h1), out_f_roready_102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1119 = eq(out_rimask_102, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1120 = eq(out_wimask_102, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1121 = eq(out_romask_102, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1122 = eq(out_womask_102, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_79 = or(_out_T_1115, UInt<4>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_79 = cat(UInt<1>(0h0), _out_prepend_T_79) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1123 = or(out_prepend_79, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1124 = bits(_out_T_1123, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_103 = bits(out_frontMask, 10, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_103 = orr(_out_rimask_T_103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_103 = bits(out_frontMask, 10, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_103 = andr(_out_wimask_T_103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_103 = bits(out_backMask, 10, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_103 = orr(_out_romask_T_103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_103 = bits(out_backMask, 10, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_103 = andr(_out_womask_T_103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_103 = and(out_rivalid[103], out_rimask_103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_103 = and(out_roready[103], out_romask_103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_103 = and(out_wivalid[103], out_wimask_103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_103 = and(out_woready[103], out_womask_103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1125 = bits(out_front.bits.data, 10, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect ABSTRACTCSWrEnMaybe, out_f_woready_103 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 309:15] connect ABSTRACTCSWrData.cmderr, _out_T_1125 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 310:12] node _out_T_1126 = and(out_f_rivalid_103, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1127 = and(UInt<1>(0h1), out_f_roready_103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1128 = and(out_f_wivalid_103, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1129 = and(UInt<1>(0h1), out_f_woready_103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1130 = eq(out_rimask_103, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1131 = eq(out_wimask_103, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1132 = eq(out_romask_103, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1133 = eq(out_womask_103, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_80 = or(_out_T_1124, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_80 = cat(ABSTRACTCSRdData.cmderr, _out_prepend_T_80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1134 = or(out_prepend_80, UInt<11>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1135 = bits(_out_T_1134, 10, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_104 = bits(out_frontMask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_104 = orr(_out_rimask_T_104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_104 = bits(out_frontMask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_104 = andr(_out_wimask_T_104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_104 = bits(out_backMask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_104 = orr(_out_romask_T_104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_104 = bits(out_backMask, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_104 = andr(_out_womask_T_104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_104 = and(out_rivalid[104], out_rimask_104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_104 = and(out_roready[104], out_romask_104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_104 = and(out_wivalid[104], out_wimask_104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_104 = and(out_woready[104], out_womask_104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1136 = bits(out_front.bits.data, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1137 = and(out_f_rivalid_104, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1138 = and(UInt<1>(0h1), out_f_roready_104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1139 = eq(out_rimask_104, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1140 = eq(out_wimask_104, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1141 = eq(out_romask_104, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1142 = eq(out_womask_104, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_81 = or(_out_T_1135, UInt<11>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_81 = cat(UInt<1>(0h0), _out_prepend_T_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1143 = or(out_prepend_81, UInt<12>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1144 = bits(_out_T_1143, 11, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_105 = bits(out_frontMask, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_105 = orr(_out_rimask_T_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_105 = bits(out_frontMask, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_105 = andr(_out_wimask_T_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_105 = bits(out_backMask, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_105 = orr(_out_romask_T_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_105 = bits(out_backMask, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_105 = andr(_out_womask_T_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_105 = and(out_rivalid[105], out_rimask_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_105 = and(out_roready[105], out_romask_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_105 = and(out_wivalid[105], out_wimask_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_105 = and(out_woready[105], out_womask_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1145 = bits(out_front.bits.data, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1146 = and(out_f_rivalid_105, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1147 = and(UInt<1>(0h1), out_f_roready_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1148 = eq(out_rimask_105, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1149 = eq(out_wimask_105, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1150 = eq(out_romask_105, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1151 = eq(out_womask_105, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_82 = or(_out_T_1144, UInt<12>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_82 = cat(ABSTRACTCSRdData.busy, _out_prepend_T_82) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1152 = or(out_prepend_82, UInt<13>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1153 = bits(_out_T_1152, 12, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_106 = bits(out_frontMask, 23, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_106 = orr(_out_rimask_T_106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_106 = bits(out_frontMask, 23, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_106 = andr(_out_wimask_T_106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_106 = bits(out_backMask, 23, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_106 = orr(_out_romask_T_106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_106 = bits(out_backMask, 23, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_106 = andr(_out_womask_T_106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_106 = and(out_rivalid[106], out_rimask_106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_106 = and(out_roready[106], out_romask_106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_106 = and(out_wivalid[106], out_wimask_106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_106 = and(out_woready[106], out_womask_106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1154 = bits(out_front.bits.data, 23, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1155 = and(out_f_rivalid_106, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1156 = and(UInt<1>(0h1), out_f_roready_106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1157 = eq(out_rimask_106, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1158 = eq(out_wimask_106, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1159 = eq(out_romask_106, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1160 = eq(out_womask_106, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_83 = or(_out_T_1153, UInt<13>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_83 = cat(UInt<1>(0h0), _out_prepend_T_83) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1161 = or(out_prepend_83, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1162 = bits(_out_T_1161, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_107 = bits(out_frontMask, 28, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_107 = orr(_out_rimask_T_107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_107 = bits(out_frontMask, 28, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_107 = andr(_out_wimask_T_107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_107 = bits(out_backMask, 28, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_107 = orr(_out_romask_T_107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_107 = bits(out_backMask, 28, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_107 = andr(_out_womask_T_107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_107 = and(out_rivalid[107], out_rimask_107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_107 = and(out_roready[107], out_romask_107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_107 = and(out_wivalid[107], out_wimask_107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_107 = and(out_woready[107], out_womask_107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1163 = bits(out_front.bits.data, 28, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1164 = and(out_f_rivalid_107, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1165 = and(UInt<1>(0h1), out_f_roready_107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1166 = eq(out_rimask_107, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1167 = eq(out_wimask_107, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1168 = eq(out_romask_107, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1169 = eq(out_womask_107, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_84 = or(_out_T_1162, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_84 = cat(ABSTRACTCSRdData.progbufsize, _out_prepend_T_84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1170 = or(out_prepend_84, UInt<29>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1171 = bits(_out_T_1170, 28, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_108 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_108 = orr(_out_rimask_T_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_108 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_108 = andr(_out_wimask_T_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_108 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_108 = orr(_out_romask_T_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_108 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_108 = andr(_out_womask_T_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_108 = and(out_rivalid[108], out_rimask_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_108 = and(out_roready[108], out_romask_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_108 = and(out_wivalid[108], out_wimask_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_108 = and(out_woready[108], out_womask_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[48], out_f_roready_108 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1172 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[48], out_f_woready_108 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_108 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[48], _out_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1173 = and(out_f_rivalid_108, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1174 = and(UInt<1>(0h1), out_f_roready_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1175 = and(out_f_wivalid_108, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1176 = and(UInt<1>(0h1), out_f_woready_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1177 = eq(out_rimask_108, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1178 = eq(out_wimask_108, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1179 = eq(out_romask_108, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1180 = eq(out_womask_108, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1181 = or(_T_270, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1182 = bits(_out_T_1181, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_109 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_109 = orr(_out_rimask_T_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_109 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_109 = andr(_out_wimask_T_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_109 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_109 = orr(_out_romask_T_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_109 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_109 = andr(_out_womask_T_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_109 = and(out_rivalid[109], out_rimask_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_109 = and(out_roready[109], out_romask_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_109 = and(out_wivalid[109], out_wimask_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_109 = and(out_woready[109], out_womask_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[49], out_f_roready_109 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1183 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[49], out_f_woready_109 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_109 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[49], _out_T_1183 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1184 = and(out_f_rivalid_109, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1185 = and(UInt<1>(0h1), out_f_roready_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1186 = and(out_f_wivalid_109, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1187 = and(UInt<1>(0h1), out_f_woready_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1188 = eq(out_rimask_109, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1189 = eq(out_wimask_109, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1190 = eq(out_romask_109, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1191 = eq(out_womask_109, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_85 = or(_out_T_1182, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_85 = cat(_T_271, _out_prepend_T_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1192 = or(out_prepend_85, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1193 = bits(_out_T_1192, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_110 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_110 = orr(_out_rimask_T_110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_110 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_110 = andr(_out_wimask_T_110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_110 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_110 = orr(_out_romask_T_110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_110 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_110 = andr(_out_womask_T_110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_110 = and(out_rivalid[110], out_rimask_110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_110 = and(out_roready[110], out_romask_110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_110 = and(out_wivalid[110], out_wimask_110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_110 = and(out_woready[110], out_womask_110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[50], out_f_roready_110 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1194 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[50], out_f_woready_110 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_110 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[50], _out_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1195 = and(out_f_rivalid_110, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1196 = and(UInt<1>(0h1), out_f_roready_110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1197 = and(out_f_wivalid_110, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1198 = and(UInt<1>(0h1), out_f_woready_110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1199 = eq(out_rimask_110, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1200 = eq(out_wimask_110, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1201 = eq(out_romask_110, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1202 = eq(out_womask_110, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_86 = or(_out_T_1193, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_86 = cat(_T_272, _out_prepend_T_86) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1203 = or(out_prepend_86, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1204 = bits(_out_T_1203, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_111 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_111 = orr(_out_rimask_T_111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_111 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_111 = andr(_out_wimask_T_111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_111 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_111 = orr(_out_romask_T_111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_111 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_111 = andr(_out_womask_T_111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_111 = and(out_rivalid[111], out_rimask_111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_111 = and(out_roready[111], out_romask_111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_111 = and(out_wivalid[111], out_wimask_111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_111 = and(out_woready[111], out_womask_111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[51], out_f_roready_111 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1205 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[51], out_f_woready_111 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_111 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[51], _out_T_1205 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1206 = and(out_f_rivalid_111, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1207 = and(UInt<1>(0h1), out_f_roready_111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1208 = and(out_f_wivalid_111, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1209 = and(UInt<1>(0h1), out_f_woready_111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1210 = eq(out_rimask_111, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1211 = eq(out_wimask_111, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1212 = eq(out_romask_111, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1213 = eq(out_womask_111, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_87 = or(_out_T_1204, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_87 = cat(_T_273, _out_prepend_T_87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1214 = or(out_prepend_87, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1215 = bits(_out_T_1214, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_112 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_112 = orr(_out_rimask_T_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_112 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_112 = andr(_out_wimask_T_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_112 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_112 = orr(_out_romask_T_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_112 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_112 = andr(_out_womask_T_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_112 = and(out_rivalid[112], out_rimask_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_112 = and(out_roready[112], out_romask_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_112 = and(out_wivalid[112], out_wimask_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_112 = and(out_woready[112], out_womask_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[32], out_f_roready_112 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1216 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[32], out_f_woready_112 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_112 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[32], _out_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1217 = and(out_f_rivalid_112, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1218 = and(UInt<1>(0h1), out_f_roready_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1219 = and(out_f_wivalid_112, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1220 = and(UInt<1>(0h1), out_f_woready_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1221 = eq(out_rimask_112, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1222 = eq(out_wimask_112, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1223 = eq(out_romask_112, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1224 = eq(out_womask_112, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1225 = or(_T_254, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1226 = bits(_out_T_1225, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_113 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_113 = orr(_out_rimask_T_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_113 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_113 = andr(_out_wimask_T_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_113 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_113 = orr(_out_romask_T_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_113 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_113 = andr(_out_womask_T_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_113 = and(out_rivalid[113], out_rimask_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_113 = and(out_roready[113], out_romask_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_113 = and(out_wivalid[113], out_wimask_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_113 = and(out_woready[113], out_womask_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[33], out_f_roready_113 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1227 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[33], out_f_woready_113 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_113 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[33], _out_T_1227 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1228 = and(out_f_rivalid_113, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1229 = and(UInt<1>(0h1), out_f_roready_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1230 = and(out_f_wivalid_113, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1231 = and(UInt<1>(0h1), out_f_woready_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1232 = eq(out_rimask_113, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1233 = eq(out_wimask_113, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1234 = eq(out_romask_113, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1235 = eq(out_womask_113, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_88 = or(_out_T_1226, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_88 = cat(_T_255, _out_prepend_T_88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1236 = or(out_prepend_88, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1237 = bits(_out_T_1236, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_114 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_114 = orr(_out_rimask_T_114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_114 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_114 = andr(_out_wimask_T_114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_114 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_114 = orr(_out_romask_T_114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_114 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_114 = andr(_out_womask_T_114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_114 = and(out_rivalid[114], out_rimask_114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_114 = and(out_roready[114], out_romask_114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_114 = and(out_wivalid[114], out_wimask_114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_114 = and(out_woready[114], out_womask_114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[34], out_f_roready_114 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1238 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[34], out_f_woready_114 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_114 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[34], _out_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1239 = and(out_f_rivalid_114, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1240 = and(UInt<1>(0h1), out_f_roready_114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1241 = and(out_f_wivalid_114, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1242 = and(UInt<1>(0h1), out_f_woready_114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1243 = eq(out_rimask_114, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1244 = eq(out_wimask_114, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1245 = eq(out_romask_114, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1246 = eq(out_womask_114, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_89 = or(_out_T_1237, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_89 = cat(_T_256, _out_prepend_T_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1247 = or(out_prepend_89, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1248 = bits(_out_T_1247, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_115 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_115 = orr(_out_rimask_T_115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_115 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_115 = andr(_out_wimask_T_115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_115 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_115 = orr(_out_romask_T_115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_115 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_115 = andr(_out_womask_T_115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_115 = and(out_rivalid[115], out_rimask_115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_115 = and(out_roready[115], out_romask_115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_115 = and(out_wivalid[115], out_wimask_115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_115 = and(out_woready[115], out_womask_115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[35], out_f_roready_115 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1249 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[35], out_f_woready_115 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_115 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[35], _out_T_1249 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1250 = and(out_f_rivalid_115, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1251 = and(UInt<1>(0h1), out_f_roready_115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1252 = and(out_f_wivalid_115, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1253 = and(UInt<1>(0h1), out_f_woready_115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1254 = eq(out_rimask_115, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1255 = eq(out_wimask_115, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1256 = eq(out_romask_115, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1257 = eq(out_womask_115, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_90 = or(_out_T_1248, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_90 = cat(_T_257, _out_prepend_T_90) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1258 = or(out_prepend_90, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1259 = bits(_out_T_1258, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_116 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_116 = orr(_out_rimask_T_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_116 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_116 = andr(_out_wimask_T_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_116 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_116 = orr(_out_romask_T_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_116 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_116 = andr(_out_womask_T_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_116 = and(out_rivalid[116], out_rimask_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_116 = and(out_roready[116], out_romask_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_116 = and(out_wivalid[116], out_wimask_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_116 = and(out_woready[116], out_womask_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect COMMANDRdEn, out_f_roready_116 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1260 = bits(out_front.bits.data, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect COMMANDWrEnMaybe, out_f_woready_116 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_116 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect COMMANDWrDataVal, _out_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1261 = and(out_f_rivalid_116, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1262 = and(UInt<1>(0h1), out_f_roready_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1263 = and(out_f_wivalid_116, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1264 = and(UInt<1>(0h1), out_f_woready_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1265 = eq(out_rimask_116, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1266 = eq(out_wimask_116, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1267 = eq(out_romask_116, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1268 = eq(out_womask_116, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1269 = or(_T_213, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1270 = bits(_out_T_1269, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_117 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_117 = orr(_out_rimask_T_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_117 = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_117 = andr(_out_wimask_T_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_117 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_117 = orr(_out_romask_T_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_117 = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_117 = andr(_out_womask_T_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_117 = and(out_rivalid[117], out_rimask_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_117 = and(out_roready[117], out_romask_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_117 = and(out_wivalid[117], out_wimask_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_117 = and(out_woready[117], out_womask_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[16], out_f_roready_117 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1271 = bits(out_front.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[16], out_f_woready_117 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_117 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[16], _out_T_1271 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1272 = and(out_f_rivalid_117, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1273 = and(UInt<1>(0h1), out_f_roready_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1274 = and(out_f_wivalid_117, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1275 = and(UInt<1>(0h1), out_f_woready_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1276 = eq(out_rimask_117, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1277 = eq(out_wimask_117, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1278 = eq(out_romask_117, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1279 = eq(out_womask_117, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1280 = or(_T_238, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1281 = bits(_out_T_1280, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_118 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_118 = orr(_out_rimask_T_118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_118 = bits(out_frontMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_118 = andr(_out_wimask_T_118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_118 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_118 = orr(_out_romask_T_118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_118 = bits(out_backMask, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_118 = andr(_out_womask_T_118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_118 = and(out_rivalid[118], out_rimask_118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_118 = and(out_roready[118], out_romask_118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_118 = and(out_wivalid[118], out_wimask_118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_118 = and(out_woready[118], out_womask_118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[17], out_f_roready_118 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1282 = bits(out_front.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[17], out_f_woready_118 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_118 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[17], _out_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1283 = and(out_f_rivalid_118, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1284 = and(UInt<1>(0h1), out_f_roready_118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1285 = and(out_f_wivalid_118, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1286 = and(UInt<1>(0h1), out_f_woready_118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1287 = eq(out_rimask_118, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1288 = eq(out_wimask_118, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1289 = eq(out_romask_118, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1290 = eq(out_womask_118, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_91 = or(_out_T_1281, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_91 = cat(_T_239, _out_prepend_T_91) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1291 = or(out_prepend_91, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1292 = bits(_out_T_1291, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_119 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_119 = orr(_out_rimask_T_119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_119 = bits(out_frontMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_119 = andr(_out_wimask_T_119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_119 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_119 = orr(_out_romask_T_119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_119 = bits(out_backMask, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_119 = andr(_out_womask_T_119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_119 = and(out_rivalid[119], out_rimask_119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_119 = and(out_roready[119], out_romask_119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_119 = and(out_wivalid[119], out_wimask_119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_119 = and(out_woready[119], out_womask_119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[18], out_f_roready_119 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1293 = bits(out_front.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[18], out_f_woready_119 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_119 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[18], _out_T_1293 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1294 = and(out_f_rivalid_119, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1295 = and(UInt<1>(0h1), out_f_roready_119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1296 = and(out_f_wivalid_119, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1297 = and(UInt<1>(0h1), out_f_woready_119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1298 = eq(out_rimask_119, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1299 = eq(out_wimask_119, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1300 = eq(out_romask_119, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1301 = eq(out_womask_119, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_92 = or(_out_T_1292, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_92 = cat(_T_240, _out_prepend_T_92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1302 = or(out_prepend_92, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1303 = bits(_out_T_1302, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_120 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_120 = orr(_out_rimask_T_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_120 = bits(out_frontMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_120 = andr(_out_wimask_T_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_120 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_120 = orr(_out_romask_T_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_120 = bits(out_backMask, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_120 = andr(_out_womask_T_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_120 = and(out_rivalid[120], out_rimask_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_120 = and(out_roready[120], out_romask_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_120 = and(out_wivalid[120], out_wimask_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_120 = and(out_woready[120], out_womask_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferRdEn[19], out_f_roready_120 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 294:46] node _out_T_1304 = bits(out_front.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect dmiProgramBufferWrEnMaybe[19], out_f_woready_120 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 296:19] when out_f_woready_120 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:24] connect programBufferNxt[19], _out_T_1304 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 297:30] node _out_T_1305 = and(out_f_rivalid_120, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1306 = and(UInt<1>(0h1), out_f_roready_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1307 = and(out_f_wivalid_120, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1308 = and(UInt<1>(0h1), out_f_woready_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1309 = eq(out_rimask_120, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1310 = eq(out_wimask_120, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1311 = eq(out_romask_120, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1312 = eq(out_womask_120, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_93 = or(_out_T_1303, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_93 = cat(_T_241, _out_prepend_T_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1313 = or(out_prepend_93, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1314 = bits(_out_T_1313, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_121 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_121 = orr(_out_rimask_T_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_121 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_121 = andr(_out_wimask_T_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_121 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_121 = orr(_out_romask_T_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_121 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_121 = andr(_out_womask_T_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_121 = and(out_rivalid[121], out_rimask_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_121 = and(out_roready[121], out_romask_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_121 = and(out_wivalid[121], out_wimask_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_121 = and(out_woready[121], out_womask_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1315 = bits(out_front.bits.data, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1316 = and(out_f_rivalid_121, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1317 = and(UInt<1>(0h1), out_f_roready_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1318 = eq(out_rimask_121, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1319 = eq(out_wimask_121, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1320 = eq(out_romask_121, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1321 = eq(out_womask_121, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1322 = or(HALTSUM1RdData.haltsum1, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1323 = bits(_out_T_1322, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T = bits(out_front.bits.index, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex_lo_hi = cat(_out_iindex_T_2, _out_iindex_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex_lo = cat(out_iindex_lo_hi, _out_iindex_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex_hi_hi = cat(_out_iindex_T_5, _out_iindex_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex_hi = cat(out_iindex_hi_hi, _out_iindex_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex = cat(out_iindex_hi, out_iindex_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T = bits(out_front.bits.index, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex_lo_hi = cat(_out_oindex_T_2, _out_oindex_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex_lo = cat(out_oindex_lo_hi, _out_oindex_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex_hi_hi = cat(_out_oindex_T_5, _out_oindex_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex_hi = cat(out_oindex_hi_hi, _out_oindex_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex = cat(out_oindex_hi, out_oindex_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_4 = bits(_out_frontSel_T, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_5 = bits(_out_frontSel_T, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_6 = bits(_out_frontSel_T, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_7 = bits(_out_frontSel_T, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_8 = bits(_out_frontSel_T, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_9 = bits(_out_frontSel_T, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_10 = bits(_out_frontSel_T, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_11 = bits(_out_frontSel_T, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_12 = bits(_out_frontSel_T, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_13 = bits(_out_frontSel_T, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_14 = bits(_out_frontSel_T, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_15 = bits(_out_frontSel_T, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_16 = bits(_out_frontSel_T, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_17 = bits(_out_frontSel_T, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_18 = bits(_out_frontSel_T, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_19 = bits(_out_frontSel_T, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_20 = bits(_out_frontSel_T, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_21 = bits(_out_frontSel_T, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_22 = bits(_out_frontSel_T, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_23 = bits(_out_frontSel_T, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_24 = bits(_out_frontSel_T, 24, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_25 = bits(_out_frontSel_T, 25, 25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_26 = bits(_out_frontSel_T, 26, 26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_27 = bits(_out_frontSel_T, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_28 = bits(_out_frontSel_T, 28, 28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_29 = bits(_out_frontSel_T, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_30 = bits(_out_frontSel_T, 30, 30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_31 = bits(_out_frontSel_T, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_32 = bits(_out_frontSel_T, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_33 = bits(_out_frontSel_T, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_34 = bits(_out_frontSel_T, 34, 34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_35 = bits(_out_frontSel_T, 35, 35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_36 = bits(_out_frontSel_T, 36, 36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_37 = bits(_out_frontSel_T, 37, 37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_38 = bits(_out_frontSel_T, 38, 38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_39 = bits(_out_frontSel_T, 39, 39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_40 = bits(_out_frontSel_T, 40, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_41 = bits(_out_frontSel_T, 41, 41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_42 = bits(_out_frontSel_T, 42, 42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_43 = bits(_out_frontSel_T, 43, 43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_44 = bits(_out_frontSel_T, 44, 44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_45 = bits(_out_frontSel_T, 45, 45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_46 = bits(_out_frontSel_T, 46, 46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_47 = bits(_out_frontSel_T, 47, 47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_48 = bits(_out_frontSel_T, 48, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_49 = bits(_out_frontSel_T, 49, 49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_50 = bits(_out_frontSel_T, 50, 50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_51 = bits(_out_frontSel_T, 51, 51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_52 = bits(_out_frontSel_T, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_53 = bits(_out_frontSel_T, 53, 53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_54 = bits(_out_frontSel_T, 54, 54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_55 = bits(_out_frontSel_T, 55, 55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_56 = bits(_out_frontSel_T, 56, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_57 = bits(_out_frontSel_T, 57, 57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_58 = bits(_out_frontSel_T, 58, 58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_59 = bits(_out_frontSel_T, 59, 59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_60 = bits(_out_frontSel_T, 60, 60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_61 = bits(_out_frontSel_T, 61, 61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_62 = bits(_out_frontSel_T, 62, 62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_63 = bits(_out_frontSel_T, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node out_backSel_0 = bits(_out_backSel_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_1 = bits(_out_backSel_T, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_2 = bits(_out_backSel_T, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_3 = bits(_out_backSel_T, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_4 = bits(_out_backSel_T, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_5 = bits(_out_backSel_T, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_6 = bits(_out_backSel_T, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_7 = bits(_out_backSel_T, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_8 = bits(_out_backSel_T, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_9 = bits(_out_backSel_T, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_10 = bits(_out_backSel_T, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_11 = bits(_out_backSel_T, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_12 = bits(_out_backSel_T, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_13 = bits(_out_backSel_T, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_14 = bits(_out_backSel_T, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_15 = bits(_out_backSel_T, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_16 = bits(_out_backSel_T, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_17 = bits(_out_backSel_T, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_18 = bits(_out_backSel_T, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_19 = bits(_out_backSel_T, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_20 = bits(_out_backSel_T, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_21 = bits(_out_backSel_T, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_22 = bits(_out_backSel_T, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_23 = bits(_out_backSel_T, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_24 = bits(_out_backSel_T, 24, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_25 = bits(_out_backSel_T, 25, 25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_26 = bits(_out_backSel_T, 26, 26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_27 = bits(_out_backSel_T, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_28 = bits(_out_backSel_T, 28, 28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_29 = bits(_out_backSel_T, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_30 = bits(_out_backSel_T, 30, 30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_31 = bits(_out_backSel_T, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_32 = bits(_out_backSel_T, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_33 = bits(_out_backSel_T, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_34 = bits(_out_backSel_T, 34, 34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_35 = bits(_out_backSel_T, 35, 35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_36 = bits(_out_backSel_T, 36, 36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_37 = bits(_out_backSel_T, 37, 37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_38 = bits(_out_backSel_T, 38, 38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_39 = bits(_out_backSel_T, 39, 39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_40 = bits(_out_backSel_T, 40, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_41 = bits(_out_backSel_T, 41, 41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_42 = bits(_out_backSel_T, 42, 42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_43 = bits(_out_backSel_T, 43, 43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_44 = bits(_out_backSel_T, 44, 44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_45 = bits(_out_backSel_T, 45, 45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_46 = bits(_out_backSel_T, 46, 46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_47 = bits(_out_backSel_T, 47, 47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_48 = bits(_out_backSel_T, 48, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_49 = bits(_out_backSel_T, 49, 49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_50 = bits(_out_backSel_T, 50, 50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_51 = bits(_out_backSel_T, 51, 51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_52 = bits(_out_backSel_T, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_53 = bits(_out_backSel_T, 53, 53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_54 = bits(_out_backSel_T, 54, 54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_55 = bits(_out_backSel_T, 55, 55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_56 = bits(_out_backSel_T, 56, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_57 = bits(_out_backSel_T, 57, 57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_58 = bits(_out_backSel_T, 58, 58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_59 = bits(_out_backSel_T, 59, 59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_60 = bits(_out_backSel_T, 60, 60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_61 = bits(_out_backSel_T, 61, 61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_62 = bits(_out_backSel_T, 62, 62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_63 = bits(_out_backSel_T, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T = and(in.valid, out_front.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[73], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_4 = eq(_out_T_36, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_2 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_2, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_12 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_3 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_3, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_4 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_18 = and(_out_rifireMux_T_1, out_frontSel_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_19 = and(_out_rifireMux_T_18, _out_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_4, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[40], _out_rifireMux_T_19 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[39], _out_rifireMux_T_19 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[38], _out_rifireMux_T_19 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[37], _out_rifireMux_T_19 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_20 = eq(_out_T_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_21 = or(out_rifireMux_out_4, _out_rifireMux_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_5 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_22 = and(_out_rifireMux_T_1, out_frontSel_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_23 = and(_out_rifireMux_T_22, _out_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_5, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[3], _out_rifireMux_T_23 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[2], _out_rifireMux_T_23 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[1], _out_rifireMux_T_23 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[0], _out_rifireMux_T_23 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_24 = eq(_out_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_25 = or(out_rifireMux_out_5, _out_rifireMux_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_6 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_26 = and(_out_rifireMux_T_1, out_frontSel_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_27 = and(_out_rifireMux_T_26, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_6, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_28 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_29 = or(out_rifireMux_out_6, _out_rifireMux_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_7 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_30 = and(_out_rifireMux_T_1, out_frontSel_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_31 = and(_out_rifireMux_T_30, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_7, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_32 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_33 = or(out_rifireMux_out_7, _out_rifireMux_T_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_8 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_34 = and(_out_rifireMux_T_1, out_frontSel_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_35 = and(_out_rifireMux_T_34, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_8, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_36 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_37 = or(out_rifireMux_out_8, _out_rifireMux_T_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_9 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_38 = and(_out_rifireMux_T_1, out_frontSel_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_39 = and(_out_rifireMux_T_38, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_9, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_40 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_41 = or(out_rifireMux_out_9, _out_rifireMux_T_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_10 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_42 = and(_out_rifireMux_T_1, out_frontSel_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_43 = and(_out_rifireMux_T_42, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_10, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_44 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_45 = or(out_rifireMux_out_10, _out_rifireMux_T_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_11 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_46 = and(_out_rifireMux_T_1, out_frontSel_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_47 = and(_out_rifireMux_T_46, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_11, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_48 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_49 = or(out_rifireMux_out_11, _out_rifireMux_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_12 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_50 = and(_out_rifireMux_T_1, out_frontSel_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_51 = and(_out_rifireMux_T_50, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_12, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_52 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_53 = or(out_rifireMux_out_12, _out_rifireMux_T_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_13 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_54 = and(_out_rifireMux_T_1, out_frontSel_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_55 = and(_out_rifireMux_T_54, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_13, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_56 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_57 = or(out_rifireMux_out_13, _out_rifireMux_T_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_14 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_58 = and(_out_rifireMux_T_1, out_frontSel_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_59 = and(_out_rifireMux_T_58, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_14, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_60 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_61 = or(out_rifireMux_out_14, _out_rifireMux_T_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_15 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_62 = and(_out_rifireMux_T_1, out_frontSel_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_63 = and(_out_rifireMux_T_62, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_15, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_64 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_65 = or(out_rifireMux_out_15, _out_rifireMux_T_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_16 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_66 = and(_out_rifireMux_T_1, out_frontSel_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_67 = and(_out_rifireMux_T_66, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_16, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_68 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_69 = or(out_rifireMux_out_16, _out_rifireMux_T_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_17 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_70 = and(_out_rifireMux_T_1, out_frontSel_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_71 = and(_out_rifireMux_T_70, _out_T_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_17, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[92], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[91], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[90], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[89], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[88], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[87], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[86], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[85], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[84], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[83], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[82], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[81], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[80], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[79], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[78], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[77], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[76], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[75], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[74], _out_rifireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_72 = eq(_out_T_38, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_73 = or(out_rifireMux_out_17, _out_rifireMux_T_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_18 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_74 = and(_out_rifireMux_T_1, out_frontSel_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_75 = and(_out_rifireMux_T_74, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_18, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_76 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_77 = or(out_rifireMux_out_18, _out_rifireMux_T_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_19 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_78 = and(_out_rifireMux_T_1, out_frontSel_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_79 = and(_out_rifireMux_T_78, _out_T_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_19, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[121], _out_rifireMux_T_79 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_80 = eq(_out_T_54, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_81 = or(out_rifireMux_out_19, _out_rifireMux_T_80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_20 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_82 = and(_out_rifireMux_T_1, out_frontSel_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_83 = and(_out_rifireMux_T_82, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_20, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_84 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_85 = or(out_rifireMux_out_20, _out_rifireMux_T_84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_21 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_86 = and(_out_rifireMux_T_1, out_frontSel_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_87 = and(_out_rifireMux_T_86, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_21, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_88 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_89 = or(out_rifireMux_out_21, _out_rifireMux_T_88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_22 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_90 = and(_out_rifireMux_T_1, out_frontSel_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_91 = and(_out_rifireMux_T_90, _out_T_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_22, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[107], _out_rifireMux_T_91 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[106], _out_rifireMux_T_91 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[105], _out_rifireMux_T_91 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[104], _out_rifireMux_T_91 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[103], _out_rifireMux_T_91 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[102], _out_rifireMux_T_91 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[101], _out_rifireMux_T_91 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_92 = eq(_out_T_44, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_93 = or(out_rifireMux_out_22, _out_rifireMux_T_92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_23 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_94 = and(_out_rifireMux_T_1, out_frontSel_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_95 = and(_out_rifireMux_T_94, _out_T_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_23, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[116], _out_rifireMux_T_95 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_96 = eq(_out_T_50, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_97 = or(out_rifireMux_out_23, _out_rifireMux_T_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_24 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_98 = and(_out_rifireMux_T_1, out_frontSel_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_99 = and(_out_rifireMux_T_98, _out_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_24, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[51], _out_rifireMux_T_99 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[50], _out_rifireMux_T_99 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[49], _out_rifireMux_T_99 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_100 = eq(_out_T_22, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_101 = or(out_rifireMux_out_24, _out_rifireMux_T_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_25 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_102 = and(_out_rifireMux_T_1, out_frontSel_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_103 = and(_out_rifireMux_T_102, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_25, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_104 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_105 = or(out_rifireMux_out_25, _out_rifireMux_T_104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_26 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_106 = and(_out_rifireMux_T_1, out_frontSel_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_107 = and(_out_rifireMux_T_106, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_26, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_108 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_109 = or(out_rifireMux_out_26, _out_rifireMux_T_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_27 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_110 = and(_out_rifireMux_T_1, out_frontSel_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_111 = and(_out_rifireMux_T_110, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_27, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_112 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_113 = or(out_rifireMux_out_27, _out_rifireMux_T_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_28 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_114 = and(_out_rifireMux_T_1, out_frontSel_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_115 = and(_out_rifireMux_T_114, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_28, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_116 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_117 = or(out_rifireMux_out_28, _out_rifireMux_T_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_29 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_118 = and(_out_rifireMux_T_1, out_frontSel_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_119 = and(_out_rifireMux_T_118, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_29, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_120 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_121 = or(out_rifireMux_out_29, _out_rifireMux_T_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_30 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_122 = and(_out_rifireMux_T_1, out_frontSel_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_123 = and(_out_rifireMux_T_122, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_30, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_124 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_125 = or(out_rifireMux_out_30, _out_rifireMux_T_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_31 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_126 = and(_out_rifireMux_T_1, out_frontSel_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_127 = and(_out_rifireMux_T_126, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_31, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_128 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_129 = or(out_rifireMux_out_31, _out_rifireMux_T_128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_32 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_130 = and(_out_rifireMux_T_1, out_frontSel_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_131 = and(_out_rifireMux_T_130, _out_T_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_32, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[96], _out_rifireMux_T_131 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[95], _out_rifireMux_T_131 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[94], _out_rifireMux_T_131 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[93], _out_rifireMux_T_131 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_132 = eq(_out_T_40, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_133 = or(out_rifireMux_out_32, _out_rifireMux_T_132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_33 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_134 = and(_out_rifireMux_T_1, out_frontSel_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_135 = and(_out_rifireMux_T_134, _out_T_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_33, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[68], _out_rifireMux_T_135 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[67], _out_rifireMux_T_135 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[66], _out_rifireMux_T_135 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[65], _out_rifireMux_T_135 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_136 = eq(_out_T_32, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_137 = or(out_rifireMux_out_33, _out_rifireMux_T_136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_34 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_138 = and(_out_rifireMux_T_1, out_frontSel_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_139 = and(_out_rifireMux_T_138, _out_T_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_34, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[100], _out_rifireMux_T_139 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[99], _out_rifireMux_T_139 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[98], _out_rifireMux_T_139 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[97], _out_rifireMux_T_139 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_140 = eq(_out_T_42, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_141 = or(out_rifireMux_out_34, _out_rifireMux_T_140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_35 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_142 = and(_out_rifireMux_T_1, out_frontSel_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_143 = and(_out_rifireMux_T_142, _out_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_35, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[32], _out_rifireMux_T_143 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[31], _out_rifireMux_T_143 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[30], _out_rifireMux_T_143 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[29], _out_rifireMux_T_143 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_144 = eq(_out_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_145 = or(out_rifireMux_out_35, _out_rifireMux_T_144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_36 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_146 = and(_out_rifireMux_T_1, out_frontSel_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_147 = and(_out_rifireMux_T_146, _out_T_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_36, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[120], _out_rifireMux_T_147 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[119], _out_rifireMux_T_147 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[118], _out_rifireMux_T_147 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[117], _out_rifireMux_T_147 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_148 = eq(_out_T_52, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_149 = or(out_rifireMux_out_36, _out_rifireMux_T_148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_37 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_150 = and(_out_rifireMux_T_1, out_frontSel_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_151 = and(_out_rifireMux_T_150, _out_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_37, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[55], _out_rifireMux_T_151 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[54], _out_rifireMux_T_151 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[53], _out_rifireMux_T_151 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[52], _out_rifireMux_T_151 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_152 = eq(_out_T_24, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_153 = or(out_rifireMux_out_37, _out_rifireMux_T_152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_38 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_154 = and(_out_rifireMux_T_1, out_frontSel_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_155 = and(_out_rifireMux_T_154, _out_T_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_38, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[64], _out_rifireMux_T_155 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[63], _out_rifireMux_T_155 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[62], _out_rifireMux_T_155 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[61], _out_rifireMux_T_155 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_156 = eq(_out_T_30, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_157 = or(out_rifireMux_out_38, _out_rifireMux_T_156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_39 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_158 = and(_out_rifireMux_T_1, out_frontSel_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_159 = and(_out_rifireMux_T_158, _out_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_39, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[28], _out_rifireMux_T_159 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[27], _out_rifireMux_T_159 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[26], _out_rifireMux_T_159 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[25], _out_rifireMux_T_159 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_160 = eq(_out_T_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_161 = or(out_rifireMux_out_39, _out_rifireMux_T_160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_40 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_162 = and(_out_rifireMux_T_1, out_frontSel_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_163 = and(_out_rifireMux_T_162, _out_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_40, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[115], _out_rifireMux_T_163 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[114], _out_rifireMux_T_163 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[113], _out_rifireMux_T_163 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[112], _out_rifireMux_T_163 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_164 = eq(_out_T_48, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_165 = or(out_rifireMux_out_40, _out_rifireMux_T_164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_41 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_166 = and(_out_rifireMux_T_1, out_frontSel_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_167 = and(_out_rifireMux_T_166, _out_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_41, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[24], _out_rifireMux_T_167 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[23], _out_rifireMux_T_167 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[22], _out_rifireMux_T_167 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[21], _out_rifireMux_T_167 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_168 = eq(_out_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_169 = or(out_rifireMux_out_41, _out_rifireMux_T_168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_42 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_170 = and(_out_rifireMux_T_1, out_frontSel_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_171 = and(_out_rifireMux_T_170, _out_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_42, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[48], _out_rifireMux_T_171 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[47], _out_rifireMux_T_171 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[46], _out_rifireMux_T_171 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[45], _out_rifireMux_T_171 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_172 = eq(_out_T_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_173 = or(out_rifireMux_out_42, _out_rifireMux_T_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_43 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_174 = and(_out_rifireMux_T_1, out_frontSel_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_175 = and(_out_rifireMux_T_174, _out_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_43, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[36], _out_rifireMux_T_175 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[35], _out_rifireMux_T_175 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[34], _out_rifireMux_T_175 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[33], _out_rifireMux_T_175 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_176 = eq(_out_T_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_177 = or(out_rifireMux_out_43, _out_rifireMux_T_176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_44 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_178 = and(_out_rifireMux_T_1, out_frontSel_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_179 = and(_out_rifireMux_T_178, _out_T_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_44, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[111], _out_rifireMux_T_179 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[110], _out_rifireMux_T_179 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[109], _out_rifireMux_T_179 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[108], _out_rifireMux_T_179 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_180 = eq(_out_T_46, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_181 = or(out_rifireMux_out_44, _out_rifireMux_T_180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_45 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_182 = and(_out_rifireMux_T_1, out_frontSel_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_183 = and(_out_rifireMux_T_182, _out_T_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_45, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[72], _out_rifireMux_T_183 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[71], _out_rifireMux_T_183 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[70], _out_rifireMux_T_183 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[69], _out_rifireMux_T_183 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_184 = eq(_out_T_34, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_185 = or(out_rifireMux_out_45, _out_rifireMux_T_184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_46 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_186 = and(_out_rifireMux_T_1, out_frontSel_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_187 = and(_out_rifireMux_T_186, _out_T_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_46, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[59], _out_rifireMux_T_187 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[58], _out_rifireMux_T_187 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[57], _out_rifireMux_T_187 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[56], _out_rifireMux_T_187 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_188 = eq(_out_T_26, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_189 = or(out_rifireMux_out_46, _out_rifireMux_T_188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_47 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_190 = and(_out_rifireMux_T_1, out_frontSel_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_191 = and(_out_rifireMux_T_190, _out_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_47, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[44], _out_rifireMux_T_191 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[43], _out_rifireMux_T_191 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[42], _out_rifireMux_T_191 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[41], _out_rifireMux_T_191 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_192 = eq(_out_T_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_193 = or(out_rifireMux_out_47, _out_rifireMux_T_192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_48 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_194 = and(_out_rifireMux_T_1, out_frontSel_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_195 = and(_out_rifireMux_T_194, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_48, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_196 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_197 = or(out_rifireMux_out_48, _out_rifireMux_T_196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_49 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_198 = and(_out_rifireMux_T_1, out_frontSel_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_199 = and(_out_rifireMux_T_198, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_49, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_200 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_201 = or(out_rifireMux_out_49, _out_rifireMux_T_200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_50 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_202 = and(_out_rifireMux_T_1, out_frontSel_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_203 = and(_out_rifireMux_T_202, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_50, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_204 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_205 = or(out_rifireMux_out_50, _out_rifireMux_T_204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_51 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_206 = and(_out_rifireMux_T_1, out_frontSel_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_207 = and(_out_rifireMux_T_206, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_51, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_208 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_209 = or(out_rifireMux_out_51, _out_rifireMux_T_208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_52 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_210 = and(_out_rifireMux_T_1, out_frontSel_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_211 = and(_out_rifireMux_T_210, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_52, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_212 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_213 = or(out_rifireMux_out_52, _out_rifireMux_T_212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_53 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_214 = and(_out_rifireMux_T_1, out_frontSel_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_215 = and(_out_rifireMux_T_214, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_53, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_216 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_217 = or(out_rifireMux_out_53, _out_rifireMux_T_216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_54 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_218 = and(_out_rifireMux_T_1, out_frontSel_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_219 = and(_out_rifireMux_T_218, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_54, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_220 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_221 = or(out_rifireMux_out_54, _out_rifireMux_T_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_55 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_222 = and(_out_rifireMux_T_1, out_frontSel_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_223 = and(_out_rifireMux_T_222, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_55, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_224 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_225 = or(out_rifireMux_out_55, _out_rifireMux_T_224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_56 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_226 = and(_out_rifireMux_T_1, out_frontSel_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_227 = and(_out_rifireMux_T_226, _out_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_56, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[18], _out_rifireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[17], _out_rifireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[16], _out_rifireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[15], _out_rifireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[14], _out_rifireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[13], _out_rifireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[12], _out_rifireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[11], _out_rifireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[10], _out_rifireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[9], _out_rifireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[8], _out_rifireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[7], _out_rifireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[6], _out_rifireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[5], _out_rifireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[4], _out_rifireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_228 = eq(_out_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_229 = or(out_rifireMux_out_56, _out_rifireMux_T_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_57 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_230 = and(_out_rifireMux_T_1, out_frontSel_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_231 = and(_out_rifireMux_T_230, _out_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_57, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[60], _out_rifireMux_T_231 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_232 = eq(_out_T_28, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_233 = or(out_rifireMux_out_57, _out_rifireMux_T_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_58 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_234 = and(_out_rifireMux_T_1, out_frontSel_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_235 = and(_out_rifireMux_T_234, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_58, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_236 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_237 = or(out_rifireMux_out_58, _out_rifireMux_T_236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_59 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_238 = and(_out_rifireMux_T_1, out_frontSel_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_239 = and(_out_rifireMux_T_238, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_59, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_240 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_241 = or(out_rifireMux_out_59, _out_rifireMux_T_240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_60 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_242 = and(_out_rifireMux_T_1, out_frontSel_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_243 = and(_out_rifireMux_T_242, _out_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_60, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[20], _out_rifireMux_T_243 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_244 = eq(_out_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_245 = or(out_rifireMux_out_60, _out_rifireMux_T_244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_61 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_246 = and(_out_rifireMux_T_1, out_frontSel_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_247 = and(_out_rifireMux_T_246, _out_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_61, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[19], _out_rifireMux_T_247 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_248 = eq(_out_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_249 = or(out_rifireMux_out_61, _out_rifireMux_T_248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_62 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_250 = and(_out_rifireMux_T_1, out_frontSel_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_251 = and(_out_rifireMux_T_250, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_62, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_252 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_253 = or(out_rifireMux_out_62, _out_rifireMux_T_252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_63 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_254 = and(_out_rifireMux_T_1, out_frontSel_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_255 = and(_out_rifireMux_T_254, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_63, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_256 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_257 = or(out_rifireMux_out_63, _out_rifireMux_T_256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_258 = geq(out_iindex, UInt<7>(0h40)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_rifireMux_WIRE : UInt<1>[64] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[4], _out_rifireMux_T_21 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[5], _out_rifireMux_T_25 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[6], _out_rifireMux_T_29 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[7], _out_rifireMux_T_33 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[8], _out_rifireMux_T_37 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[9], _out_rifireMux_T_41 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[10], _out_rifireMux_T_45 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[11], _out_rifireMux_T_49 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[12], _out_rifireMux_T_53 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[13], _out_rifireMux_T_57 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[14], _out_rifireMux_T_61 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[15], _out_rifireMux_T_65 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[16], _out_rifireMux_T_69 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[17], _out_rifireMux_T_73 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[18], _out_rifireMux_T_77 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[19], _out_rifireMux_T_81 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[20], _out_rifireMux_T_85 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[21], _out_rifireMux_T_89 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[22], _out_rifireMux_T_93 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[23], _out_rifireMux_T_97 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[24], _out_rifireMux_T_101 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[25], _out_rifireMux_T_105 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[26], _out_rifireMux_T_109 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[27], _out_rifireMux_T_113 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[28], _out_rifireMux_T_117 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[29], _out_rifireMux_T_121 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[30], _out_rifireMux_T_125 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[31], _out_rifireMux_T_129 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[32], _out_rifireMux_T_133 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[33], _out_rifireMux_T_137 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[34], _out_rifireMux_T_141 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[35], _out_rifireMux_T_145 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[36], _out_rifireMux_T_149 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[37], _out_rifireMux_T_153 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[38], _out_rifireMux_T_157 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[39], _out_rifireMux_T_161 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[40], _out_rifireMux_T_165 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[41], _out_rifireMux_T_169 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[42], _out_rifireMux_T_173 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[43], _out_rifireMux_T_177 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[44], _out_rifireMux_T_181 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[45], _out_rifireMux_T_185 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[46], _out_rifireMux_T_189 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[47], _out_rifireMux_T_193 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[48], _out_rifireMux_T_197 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[49], _out_rifireMux_T_201 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[50], _out_rifireMux_T_205 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[51], _out_rifireMux_T_209 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[52], _out_rifireMux_T_213 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[53], _out_rifireMux_T_217 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[54], _out_rifireMux_T_221 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[55], _out_rifireMux_T_225 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[56], _out_rifireMux_T_229 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[57], _out_rifireMux_T_233 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[58], _out_rifireMux_T_237 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[59], _out_rifireMux_T_241 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[60], _out_rifireMux_T_245 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[61], _out_rifireMux_T_249 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[62], _out_rifireMux_T_253 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[63], _out_rifireMux_T_257 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_rifireMux = mux(_out_rifireMux_T_258, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_wifireMux_T = and(in.valid, out_front.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[73], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_5 = eq(_out_T_36, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_9 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_2 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_2, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_13 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_3 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_3, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_4 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_19 = and(_out_wifireMux_T_2, out_frontSel_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_20 = and(_out_wifireMux_T_19, _out_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_4, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[40], _out_wifireMux_T_20 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[39], _out_wifireMux_T_20 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[38], _out_wifireMux_T_20 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[37], _out_wifireMux_T_20 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_21 = eq(_out_T_16, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_22 = or(out_wifireMux_out_4, _out_wifireMux_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_5 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_23 = and(_out_wifireMux_T_2, out_frontSel_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_24 = and(_out_wifireMux_T_23, _out_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_5, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[3], _out_wifireMux_T_24 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[2], _out_wifireMux_T_24 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[1], _out_wifireMux_T_24 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[0], _out_wifireMux_T_24 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_25 = eq(_out_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_26 = or(out_wifireMux_out_5, _out_wifireMux_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_6 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_27 = and(_out_wifireMux_T_2, out_frontSel_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_28 = and(_out_wifireMux_T_27, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_6, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_29 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_30 = or(out_wifireMux_out_6, _out_wifireMux_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_7 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_31 = and(_out_wifireMux_T_2, out_frontSel_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_32 = and(_out_wifireMux_T_31, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_7, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_34 = or(out_wifireMux_out_7, _out_wifireMux_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_8 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_35 = and(_out_wifireMux_T_2, out_frontSel_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_36 = and(_out_wifireMux_T_35, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_8, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_37 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_38 = or(out_wifireMux_out_8, _out_wifireMux_T_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_9 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_39 = and(_out_wifireMux_T_2, out_frontSel_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_40 = and(_out_wifireMux_T_39, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_9, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_41 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_42 = or(out_wifireMux_out_9, _out_wifireMux_T_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_10 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_43 = and(_out_wifireMux_T_2, out_frontSel_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_44 = and(_out_wifireMux_T_43, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_10, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_45 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_46 = or(out_wifireMux_out_10, _out_wifireMux_T_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_11 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_47 = and(_out_wifireMux_T_2, out_frontSel_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_48 = and(_out_wifireMux_T_47, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_11, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_49 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_50 = or(out_wifireMux_out_11, _out_wifireMux_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_12 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_51 = and(_out_wifireMux_T_2, out_frontSel_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_52 = and(_out_wifireMux_T_51, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_12, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_53 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_54 = or(out_wifireMux_out_12, _out_wifireMux_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_13 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_55 = and(_out_wifireMux_T_2, out_frontSel_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_56 = and(_out_wifireMux_T_55, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_13, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_57 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_58 = or(out_wifireMux_out_13, _out_wifireMux_T_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_14 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_59 = and(_out_wifireMux_T_2, out_frontSel_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_60 = and(_out_wifireMux_T_59, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_14, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_61 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_62 = or(out_wifireMux_out_14, _out_wifireMux_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_15 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_63 = and(_out_wifireMux_T_2, out_frontSel_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_64 = and(_out_wifireMux_T_63, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_15, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_65 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_66 = or(out_wifireMux_out_15, _out_wifireMux_T_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_16 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_67 = and(_out_wifireMux_T_2, out_frontSel_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_68 = and(_out_wifireMux_T_67, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_16, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_69 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_70 = or(out_wifireMux_out_16, _out_wifireMux_T_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_17 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_71 = and(_out_wifireMux_T_2, out_frontSel_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_72 = and(_out_wifireMux_T_71, _out_T_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_17, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[92], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[91], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[90], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[89], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[88], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[87], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[86], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[85], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[84], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[83], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[82], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[81], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[80], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[79], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[78], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[77], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[76], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[75], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[74], _out_wifireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_73 = eq(_out_T_38, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_74 = or(out_wifireMux_out_17, _out_wifireMux_T_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_18 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_75 = and(_out_wifireMux_T_2, out_frontSel_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_76 = and(_out_wifireMux_T_75, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_18, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_77 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_78 = or(out_wifireMux_out_18, _out_wifireMux_T_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_19 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_79 = and(_out_wifireMux_T_2, out_frontSel_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_80 = and(_out_wifireMux_T_79, _out_T_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_19, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[121], _out_wifireMux_T_80 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_81 = eq(_out_T_54, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_82 = or(out_wifireMux_out_19, _out_wifireMux_T_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_20 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_83 = and(_out_wifireMux_T_2, out_frontSel_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_84 = and(_out_wifireMux_T_83, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_20, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_85 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_86 = or(out_wifireMux_out_20, _out_wifireMux_T_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_21 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_87 = and(_out_wifireMux_T_2, out_frontSel_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_88 = and(_out_wifireMux_T_87, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_21, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_89 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_90 = or(out_wifireMux_out_21, _out_wifireMux_T_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_22 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_91 = and(_out_wifireMux_T_2, out_frontSel_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_92 = and(_out_wifireMux_T_91, _out_T_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_22, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[107], _out_wifireMux_T_92 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[106], _out_wifireMux_T_92 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[105], _out_wifireMux_T_92 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[104], _out_wifireMux_T_92 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[103], _out_wifireMux_T_92 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[102], _out_wifireMux_T_92 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[101], _out_wifireMux_T_92 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_93 = eq(_out_T_44, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_94 = or(out_wifireMux_out_22, _out_wifireMux_T_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_23 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_95 = and(_out_wifireMux_T_2, out_frontSel_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_96 = and(_out_wifireMux_T_95, _out_T_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_23, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[116], _out_wifireMux_T_96 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_97 = eq(_out_T_50, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_98 = or(out_wifireMux_out_23, _out_wifireMux_T_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_24 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_99 = and(_out_wifireMux_T_2, out_frontSel_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_100 = and(_out_wifireMux_T_99, _out_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_24, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[51], _out_wifireMux_T_100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[50], _out_wifireMux_T_100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[49], _out_wifireMux_T_100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_101 = eq(_out_T_22, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_102 = or(out_wifireMux_out_24, _out_wifireMux_T_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_25 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_103 = and(_out_wifireMux_T_2, out_frontSel_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_104 = and(_out_wifireMux_T_103, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_25, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_105 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_106 = or(out_wifireMux_out_25, _out_wifireMux_T_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_26 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_107 = and(_out_wifireMux_T_2, out_frontSel_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_108 = and(_out_wifireMux_T_107, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_26, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_109 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_110 = or(out_wifireMux_out_26, _out_wifireMux_T_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_27 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_111 = and(_out_wifireMux_T_2, out_frontSel_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_112 = and(_out_wifireMux_T_111, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_27, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_113 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_114 = or(out_wifireMux_out_27, _out_wifireMux_T_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_28 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_115 = and(_out_wifireMux_T_2, out_frontSel_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_116 = and(_out_wifireMux_T_115, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_28, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_117 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_118 = or(out_wifireMux_out_28, _out_wifireMux_T_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_29 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_119 = and(_out_wifireMux_T_2, out_frontSel_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_120 = and(_out_wifireMux_T_119, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_29, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_121 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_122 = or(out_wifireMux_out_29, _out_wifireMux_T_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_30 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_123 = and(_out_wifireMux_T_2, out_frontSel_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_124 = and(_out_wifireMux_T_123, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_30, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_125 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_126 = or(out_wifireMux_out_30, _out_wifireMux_T_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_31 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_127 = and(_out_wifireMux_T_2, out_frontSel_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_128 = and(_out_wifireMux_T_127, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_31, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_129 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_130 = or(out_wifireMux_out_31, _out_wifireMux_T_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_32 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_131 = and(_out_wifireMux_T_2, out_frontSel_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_132 = and(_out_wifireMux_T_131, _out_T_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_32, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[96], _out_wifireMux_T_132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[95], _out_wifireMux_T_132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[94], _out_wifireMux_T_132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[93], _out_wifireMux_T_132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_133 = eq(_out_T_40, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_134 = or(out_wifireMux_out_32, _out_wifireMux_T_133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_33 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_135 = and(_out_wifireMux_T_2, out_frontSel_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_136 = and(_out_wifireMux_T_135, _out_T_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_33, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[68], _out_wifireMux_T_136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[67], _out_wifireMux_T_136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[66], _out_wifireMux_T_136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[65], _out_wifireMux_T_136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_137 = eq(_out_T_32, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_138 = or(out_wifireMux_out_33, _out_wifireMux_T_137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_34 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_139 = and(_out_wifireMux_T_2, out_frontSel_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_140 = and(_out_wifireMux_T_139, _out_T_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_34, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[100], _out_wifireMux_T_140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[99], _out_wifireMux_T_140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[98], _out_wifireMux_T_140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[97], _out_wifireMux_T_140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_141 = eq(_out_T_42, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_142 = or(out_wifireMux_out_34, _out_wifireMux_T_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_35 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_143 = and(_out_wifireMux_T_2, out_frontSel_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_144 = and(_out_wifireMux_T_143, _out_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_35, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[32], _out_wifireMux_T_144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[31], _out_wifireMux_T_144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[30], _out_wifireMux_T_144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[29], _out_wifireMux_T_144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_145 = eq(_out_T_12, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_146 = or(out_wifireMux_out_35, _out_wifireMux_T_145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_36 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_147 = and(_out_wifireMux_T_2, out_frontSel_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_148 = and(_out_wifireMux_T_147, _out_T_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_36, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[120], _out_wifireMux_T_148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[119], _out_wifireMux_T_148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[118], _out_wifireMux_T_148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[117], _out_wifireMux_T_148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_149 = eq(_out_T_52, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_150 = or(out_wifireMux_out_36, _out_wifireMux_T_149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_37 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_151 = and(_out_wifireMux_T_2, out_frontSel_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_152 = and(_out_wifireMux_T_151, _out_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_37, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[55], _out_wifireMux_T_152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[54], _out_wifireMux_T_152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[53], _out_wifireMux_T_152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[52], _out_wifireMux_T_152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_153 = eq(_out_T_24, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_154 = or(out_wifireMux_out_37, _out_wifireMux_T_153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_38 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_155 = and(_out_wifireMux_T_2, out_frontSel_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_156 = and(_out_wifireMux_T_155, _out_T_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_38, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[64], _out_wifireMux_T_156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[63], _out_wifireMux_T_156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[62], _out_wifireMux_T_156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[61], _out_wifireMux_T_156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_157 = eq(_out_T_30, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_158 = or(out_wifireMux_out_38, _out_wifireMux_T_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_39 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_159 = and(_out_wifireMux_T_2, out_frontSel_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_160 = and(_out_wifireMux_T_159, _out_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_39, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[28], _out_wifireMux_T_160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[27], _out_wifireMux_T_160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[26], _out_wifireMux_T_160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[25], _out_wifireMux_T_160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_161 = eq(_out_T_10, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_162 = or(out_wifireMux_out_39, _out_wifireMux_T_161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_40 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_163 = and(_out_wifireMux_T_2, out_frontSel_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_164 = and(_out_wifireMux_T_163, _out_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_40, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[115], _out_wifireMux_T_164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[114], _out_wifireMux_T_164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[113], _out_wifireMux_T_164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[112], _out_wifireMux_T_164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_165 = eq(_out_T_48, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_166 = or(out_wifireMux_out_40, _out_wifireMux_T_165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_41 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_167 = and(_out_wifireMux_T_2, out_frontSel_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_168 = and(_out_wifireMux_T_167, _out_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_41, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[24], _out_wifireMux_T_168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[23], _out_wifireMux_T_168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[22], _out_wifireMux_T_168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[21], _out_wifireMux_T_168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_169 = eq(_out_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_170 = or(out_wifireMux_out_41, _out_wifireMux_T_169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_42 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_171 = and(_out_wifireMux_T_2, out_frontSel_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_172 = and(_out_wifireMux_T_171, _out_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_42, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[48], _out_wifireMux_T_172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[47], _out_wifireMux_T_172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[46], _out_wifireMux_T_172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[45], _out_wifireMux_T_172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_173 = eq(_out_T_20, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_174 = or(out_wifireMux_out_42, _out_wifireMux_T_173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_43 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_175 = and(_out_wifireMux_T_2, out_frontSel_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_176 = and(_out_wifireMux_T_175, _out_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_43, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[36], _out_wifireMux_T_176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[35], _out_wifireMux_T_176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[34], _out_wifireMux_T_176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[33], _out_wifireMux_T_176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_177 = eq(_out_T_14, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_178 = or(out_wifireMux_out_43, _out_wifireMux_T_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_44 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_179 = and(_out_wifireMux_T_2, out_frontSel_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_180 = and(_out_wifireMux_T_179, _out_T_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_44, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[111], _out_wifireMux_T_180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[110], _out_wifireMux_T_180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[109], _out_wifireMux_T_180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[108], _out_wifireMux_T_180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_181 = eq(_out_T_46, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_182 = or(out_wifireMux_out_44, _out_wifireMux_T_181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_45 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_183 = and(_out_wifireMux_T_2, out_frontSel_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_184 = and(_out_wifireMux_T_183, _out_T_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_45, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[72], _out_wifireMux_T_184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[71], _out_wifireMux_T_184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[70], _out_wifireMux_T_184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[69], _out_wifireMux_T_184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_185 = eq(_out_T_34, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_186 = or(out_wifireMux_out_45, _out_wifireMux_T_185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_46 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_187 = and(_out_wifireMux_T_2, out_frontSel_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_188 = and(_out_wifireMux_T_187, _out_T_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_46, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[59], _out_wifireMux_T_188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[58], _out_wifireMux_T_188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[57], _out_wifireMux_T_188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[56], _out_wifireMux_T_188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_189 = eq(_out_T_26, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_190 = or(out_wifireMux_out_46, _out_wifireMux_T_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_47 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_191 = and(_out_wifireMux_T_2, out_frontSel_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_192 = and(_out_wifireMux_T_191, _out_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_47, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[44], _out_wifireMux_T_192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[43], _out_wifireMux_T_192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[42], _out_wifireMux_T_192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[41], _out_wifireMux_T_192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_193 = eq(_out_T_18, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_194 = or(out_wifireMux_out_47, _out_wifireMux_T_193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_48 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_195 = and(_out_wifireMux_T_2, out_frontSel_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_196 = and(_out_wifireMux_T_195, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_48, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_197 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_198 = or(out_wifireMux_out_48, _out_wifireMux_T_197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_49 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_199 = and(_out_wifireMux_T_2, out_frontSel_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_200 = and(_out_wifireMux_T_199, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_49, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_201 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_202 = or(out_wifireMux_out_49, _out_wifireMux_T_201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_50 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_203 = and(_out_wifireMux_T_2, out_frontSel_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_204 = and(_out_wifireMux_T_203, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_50, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_205 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_206 = or(out_wifireMux_out_50, _out_wifireMux_T_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_51 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_207 = and(_out_wifireMux_T_2, out_frontSel_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_208 = and(_out_wifireMux_T_207, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_51, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_209 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_210 = or(out_wifireMux_out_51, _out_wifireMux_T_209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_52 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_211 = and(_out_wifireMux_T_2, out_frontSel_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_212 = and(_out_wifireMux_T_211, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_52, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_213 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_214 = or(out_wifireMux_out_52, _out_wifireMux_T_213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_53 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_215 = and(_out_wifireMux_T_2, out_frontSel_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_216 = and(_out_wifireMux_T_215, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_53, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_217 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_218 = or(out_wifireMux_out_53, _out_wifireMux_T_217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_54 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_219 = and(_out_wifireMux_T_2, out_frontSel_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_220 = and(_out_wifireMux_T_219, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_54, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_221 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_222 = or(out_wifireMux_out_54, _out_wifireMux_T_221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_55 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_223 = and(_out_wifireMux_T_2, out_frontSel_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_224 = and(_out_wifireMux_T_223, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_55, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_225 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_226 = or(out_wifireMux_out_55, _out_wifireMux_T_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_56 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_227 = and(_out_wifireMux_T_2, out_frontSel_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_228 = and(_out_wifireMux_T_227, _out_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_56, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[18], _out_wifireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[17], _out_wifireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[16], _out_wifireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[15], _out_wifireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[14], _out_wifireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[13], _out_wifireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[12], _out_wifireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[11], _out_wifireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[10], _out_wifireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[9], _out_wifireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[8], _out_wifireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[7], _out_wifireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[6], _out_wifireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[5], _out_wifireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[4], _out_wifireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_229 = eq(_out_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_230 = or(out_wifireMux_out_56, _out_wifireMux_T_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_57 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_231 = and(_out_wifireMux_T_2, out_frontSel_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_232 = and(_out_wifireMux_T_231, _out_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_57, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[60], _out_wifireMux_T_232 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_233 = eq(_out_T_28, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_234 = or(out_wifireMux_out_57, _out_wifireMux_T_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_58 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_235 = and(_out_wifireMux_T_2, out_frontSel_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_236 = and(_out_wifireMux_T_235, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_58, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_237 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_238 = or(out_wifireMux_out_58, _out_wifireMux_T_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_59 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_239 = and(_out_wifireMux_T_2, out_frontSel_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_240 = and(_out_wifireMux_T_239, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_59, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_241 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_242 = or(out_wifireMux_out_59, _out_wifireMux_T_241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_60 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_243 = and(_out_wifireMux_T_2, out_frontSel_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_244 = and(_out_wifireMux_T_243, _out_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_60, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[20], _out_wifireMux_T_244 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_245 = eq(_out_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_246 = or(out_wifireMux_out_60, _out_wifireMux_T_245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_61 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_247 = and(_out_wifireMux_T_2, out_frontSel_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_248 = and(_out_wifireMux_T_247, _out_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_61, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[19], _out_wifireMux_T_248 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_249 = eq(_out_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_250 = or(out_wifireMux_out_61, _out_wifireMux_T_249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_62 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_251 = and(_out_wifireMux_T_2, out_frontSel_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_252 = and(_out_wifireMux_T_251, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_62, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_253 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_254 = or(out_wifireMux_out_62, _out_wifireMux_T_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_63 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_255 = and(_out_wifireMux_T_2, out_frontSel_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_256 = and(_out_wifireMux_T_255, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_63, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_257 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_258 = or(out_wifireMux_out_63, _out_wifireMux_T_257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_259 = geq(out_iindex, UInt<7>(0h40)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_wifireMux_WIRE : UInt<1>[64] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[4], _out_wifireMux_T_22 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[5], _out_wifireMux_T_26 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[6], _out_wifireMux_T_30 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[7], _out_wifireMux_T_34 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[8], _out_wifireMux_T_38 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[9], _out_wifireMux_T_42 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[10], _out_wifireMux_T_46 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[11], _out_wifireMux_T_50 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[12], _out_wifireMux_T_54 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[13], _out_wifireMux_T_58 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[14], _out_wifireMux_T_62 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[15], _out_wifireMux_T_66 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[16], _out_wifireMux_T_70 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[17], _out_wifireMux_T_74 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[18], _out_wifireMux_T_78 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[19], _out_wifireMux_T_82 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[20], _out_wifireMux_T_86 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[21], _out_wifireMux_T_90 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[22], _out_wifireMux_T_94 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[23], _out_wifireMux_T_98 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[24], _out_wifireMux_T_102 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[25], _out_wifireMux_T_106 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[26], _out_wifireMux_T_110 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[27], _out_wifireMux_T_114 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[28], _out_wifireMux_T_118 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[29], _out_wifireMux_T_122 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[30], _out_wifireMux_T_126 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[31], _out_wifireMux_T_130 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[32], _out_wifireMux_T_134 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[33], _out_wifireMux_T_138 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[34], _out_wifireMux_T_142 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[35], _out_wifireMux_T_146 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[36], _out_wifireMux_T_150 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[37], _out_wifireMux_T_154 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[38], _out_wifireMux_T_158 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[39], _out_wifireMux_T_162 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[40], _out_wifireMux_T_166 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[41], _out_wifireMux_T_170 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[42], _out_wifireMux_T_174 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[43], _out_wifireMux_T_178 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[44], _out_wifireMux_T_182 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[45], _out_wifireMux_T_186 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[46], _out_wifireMux_T_190 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[47], _out_wifireMux_T_194 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[48], _out_wifireMux_T_198 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[49], _out_wifireMux_T_202 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[50], _out_wifireMux_T_206 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[51], _out_wifireMux_T_210 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[52], _out_wifireMux_T_214 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[53], _out_wifireMux_T_218 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[54], _out_wifireMux_T_222 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[55], _out_wifireMux_T_226 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[56], _out_wifireMux_T_230 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[57], _out_wifireMux_T_234 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[58], _out_wifireMux_T_238 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[59], _out_wifireMux_T_242 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[60], _out_wifireMux_T_246 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[61], _out_wifireMux_T_250 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[62], _out_wifireMux_T_254 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[63], _out_wifireMux_T_258 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_wifireMux = mux(_out_wifireMux_T_259, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_rofireMux_T = and(out_front.valid, out.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[73], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_4 = eq(_out_T_37, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_2 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_2, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_12 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_3 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_3, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_4 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_18 = and(_out_rofireMux_T_1, out_backSel_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_19 = and(_out_rofireMux_T_18, _out_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_4, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[40], _out_rofireMux_T_19 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[39], _out_rofireMux_T_19 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[38], _out_rofireMux_T_19 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[37], _out_rofireMux_T_19 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_20 = eq(_out_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_21 = or(out_rofireMux_out_4, _out_rofireMux_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_5 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_22 = and(_out_rofireMux_T_1, out_backSel_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_23 = and(_out_rofireMux_T_22, _out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_5, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[3], _out_rofireMux_T_23 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[2], _out_rofireMux_T_23 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[1], _out_rofireMux_T_23 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[0], _out_rofireMux_T_23 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_24 = eq(_out_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_25 = or(out_rofireMux_out_5, _out_rofireMux_T_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_6 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_26 = and(_out_rofireMux_T_1, out_backSel_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_27 = and(_out_rofireMux_T_26, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_6, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_28 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_29 = or(out_rofireMux_out_6, _out_rofireMux_T_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_7 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_30 = and(_out_rofireMux_T_1, out_backSel_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_31 = and(_out_rofireMux_T_30, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_7, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_32 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_33 = or(out_rofireMux_out_7, _out_rofireMux_T_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_8 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_34 = and(_out_rofireMux_T_1, out_backSel_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_35 = and(_out_rofireMux_T_34, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_8, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_36 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_37 = or(out_rofireMux_out_8, _out_rofireMux_T_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_9 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_38 = and(_out_rofireMux_T_1, out_backSel_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_39 = and(_out_rofireMux_T_38, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_9, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_40 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_41 = or(out_rofireMux_out_9, _out_rofireMux_T_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_10 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_42 = and(_out_rofireMux_T_1, out_backSel_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_43 = and(_out_rofireMux_T_42, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_10, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_44 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_45 = or(out_rofireMux_out_10, _out_rofireMux_T_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_11 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_46 = and(_out_rofireMux_T_1, out_backSel_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_47 = and(_out_rofireMux_T_46, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_11, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_48 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_49 = or(out_rofireMux_out_11, _out_rofireMux_T_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_12 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_50 = and(_out_rofireMux_T_1, out_backSel_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_51 = and(_out_rofireMux_T_50, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_12, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_52 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_53 = or(out_rofireMux_out_12, _out_rofireMux_T_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_13 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_54 = and(_out_rofireMux_T_1, out_backSel_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_55 = and(_out_rofireMux_T_54, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_13, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_56 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_57 = or(out_rofireMux_out_13, _out_rofireMux_T_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_14 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_58 = and(_out_rofireMux_T_1, out_backSel_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_59 = and(_out_rofireMux_T_58, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_14, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_60 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_61 = or(out_rofireMux_out_14, _out_rofireMux_T_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_15 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_62 = and(_out_rofireMux_T_1, out_backSel_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_63 = and(_out_rofireMux_T_62, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_15, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_64 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_65 = or(out_rofireMux_out_15, _out_rofireMux_T_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_16 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_66 = and(_out_rofireMux_T_1, out_backSel_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_67 = and(_out_rofireMux_T_66, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_16, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_68 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_69 = or(out_rofireMux_out_16, _out_rofireMux_T_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_17 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_70 = and(_out_rofireMux_T_1, out_backSel_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_71 = and(_out_rofireMux_T_70, _out_T_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_17, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[92], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[91], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[90], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[89], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[88], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[87], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[86], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[85], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[84], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[83], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[82], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[81], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[80], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[79], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[78], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[77], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[76], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[75], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[74], _out_rofireMux_T_71 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_72 = eq(_out_T_39, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_73 = or(out_rofireMux_out_17, _out_rofireMux_T_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_18 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_74 = and(_out_rofireMux_T_1, out_backSel_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_75 = and(_out_rofireMux_T_74, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_18, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_76 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_77 = or(out_rofireMux_out_18, _out_rofireMux_T_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_19 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_78 = and(_out_rofireMux_T_1, out_backSel_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_79 = and(_out_rofireMux_T_78, _out_T_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_19, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[121], _out_rofireMux_T_79 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_80 = eq(_out_T_55, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_81 = or(out_rofireMux_out_19, _out_rofireMux_T_80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_20 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_82 = and(_out_rofireMux_T_1, out_backSel_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_83 = and(_out_rofireMux_T_82, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_20, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_84 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_85 = or(out_rofireMux_out_20, _out_rofireMux_T_84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_21 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_86 = and(_out_rofireMux_T_1, out_backSel_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_87 = and(_out_rofireMux_T_86, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_21, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_88 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_89 = or(out_rofireMux_out_21, _out_rofireMux_T_88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_22 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_90 = and(_out_rofireMux_T_1, out_backSel_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_91 = and(_out_rofireMux_T_90, _out_T_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_22, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[107], _out_rofireMux_T_91 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[106], _out_rofireMux_T_91 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[105], _out_rofireMux_T_91 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[104], _out_rofireMux_T_91 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[103], _out_rofireMux_T_91 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[102], _out_rofireMux_T_91 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[101], _out_rofireMux_T_91 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_92 = eq(_out_T_45, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_93 = or(out_rofireMux_out_22, _out_rofireMux_T_92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_23 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_94 = and(_out_rofireMux_T_1, out_backSel_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_95 = and(_out_rofireMux_T_94, _out_T_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_23, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[116], _out_rofireMux_T_95 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_96 = eq(_out_T_51, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_97 = or(out_rofireMux_out_23, _out_rofireMux_T_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_24 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_98 = and(_out_rofireMux_T_1, out_backSel_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_99 = and(_out_rofireMux_T_98, _out_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_24, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[51], _out_rofireMux_T_99 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[50], _out_rofireMux_T_99 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[49], _out_rofireMux_T_99 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_100 = eq(_out_T_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_101 = or(out_rofireMux_out_24, _out_rofireMux_T_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_25 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_102 = and(_out_rofireMux_T_1, out_backSel_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_103 = and(_out_rofireMux_T_102, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_25, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_104 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_105 = or(out_rofireMux_out_25, _out_rofireMux_T_104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_26 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_106 = and(_out_rofireMux_T_1, out_backSel_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_107 = and(_out_rofireMux_T_106, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_26, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_108 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_109 = or(out_rofireMux_out_26, _out_rofireMux_T_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_27 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_110 = and(_out_rofireMux_T_1, out_backSel_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_111 = and(_out_rofireMux_T_110, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_27, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_112 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_113 = or(out_rofireMux_out_27, _out_rofireMux_T_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_28 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_114 = and(_out_rofireMux_T_1, out_backSel_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_115 = and(_out_rofireMux_T_114, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_28, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_116 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_117 = or(out_rofireMux_out_28, _out_rofireMux_T_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_29 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_118 = and(_out_rofireMux_T_1, out_backSel_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_119 = and(_out_rofireMux_T_118, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_29, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_120 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_121 = or(out_rofireMux_out_29, _out_rofireMux_T_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_30 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_122 = and(_out_rofireMux_T_1, out_backSel_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_123 = and(_out_rofireMux_T_122, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_30, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_124 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_125 = or(out_rofireMux_out_30, _out_rofireMux_T_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_31 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_126 = and(_out_rofireMux_T_1, out_backSel_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_127 = and(_out_rofireMux_T_126, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_31, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_128 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_129 = or(out_rofireMux_out_31, _out_rofireMux_T_128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_32 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_130 = and(_out_rofireMux_T_1, out_backSel_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_131 = and(_out_rofireMux_T_130, _out_T_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_32, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[96], _out_rofireMux_T_131 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[95], _out_rofireMux_T_131 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[94], _out_rofireMux_T_131 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[93], _out_rofireMux_T_131 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_132 = eq(_out_T_41, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_133 = or(out_rofireMux_out_32, _out_rofireMux_T_132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_33 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_134 = and(_out_rofireMux_T_1, out_backSel_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_135 = and(_out_rofireMux_T_134, _out_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_33, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[68], _out_rofireMux_T_135 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[67], _out_rofireMux_T_135 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[66], _out_rofireMux_T_135 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[65], _out_rofireMux_T_135 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_136 = eq(_out_T_33, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_137 = or(out_rofireMux_out_33, _out_rofireMux_T_136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_34 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_138 = and(_out_rofireMux_T_1, out_backSel_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_139 = and(_out_rofireMux_T_138, _out_T_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_34, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[100], _out_rofireMux_T_139 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[99], _out_rofireMux_T_139 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[98], _out_rofireMux_T_139 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[97], _out_rofireMux_T_139 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_140 = eq(_out_T_43, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_141 = or(out_rofireMux_out_34, _out_rofireMux_T_140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_35 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_142 = and(_out_rofireMux_T_1, out_backSel_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_143 = and(_out_rofireMux_T_142, _out_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_35, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[32], _out_rofireMux_T_143 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[31], _out_rofireMux_T_143 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[30], _out_rofireMux_T_143 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[29], _out_rofireMux_T_143 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_144 = eq(_out_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_145 = or(out_rofireMux_out_35, _out_rofireMux_T_144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_36 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_146 = and(_out_rofireMux_T_1, out_backSel_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_147 = and(_out_rofireMux_T_146, _out_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_36, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[120], _out_rofireMux_T_147 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[119], _out_rofireMux_T_147 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[118], _out_rofireMux_T_147 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[117], _out_rofireMux_T_147 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_148 = eq(_out_T_53, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_149 = or(out_rofireMux_out_36, _out_rofireMux_T_148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_37 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_150 = and(_out_rofireMux_T_1, out_backSel_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_151 = and(_out_rofireMux_T_150, _out_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_37, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[55], _out_rofireMux_T_151 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[54], _out_rofireMux_T_151 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[53], _out_rofireMux_T_151 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[52], _out_rofireMux_T_151 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_152 = eq(_out_T_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_153 = or(out_rofireMux_out_37, _out_rofireMux_T_152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_38 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_154 = and(_out_rofireMux_T_1, out_backSel_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_155 = and(_out_rofireMux_T_154, _out_T_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_38, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[64], _out_rofireMux_T_155 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[63], _out_rofireMux_T_155 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[62], _out_rofireMux_T_155 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[61], _out_rofireMux_T_155 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_156 = eq(_out_T_31, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_157 = or(out_rofireMux_out_38, _out_rofireMux_T_156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_39 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_158 = and(_out_rofireMux_T_1, out_backSel_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_159 = and(_out_rofireMux_T_158, _out_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_39, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[28], _out_rofireMux_T_159 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[27], _out_rofireMux_T_159 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[26], _out_rofireMux_T_159 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[25], _out_rofireMux_T_159 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_160 = eq(_out_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_161 = or(out_rofireMux_out_39, _out_rofireMux_T_160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_40 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_162 = and(_out_rofireMux_T_1, out_backSel_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_163 = and(_out_rofireMux_T_162, _out_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_40, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[115], _out_rofireMux_T_163 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[114], _out_rofireMux_T_163 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[113], _out_rofireMux_T_163 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[112], _out_rofireMux_T_163 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_164 = eq(_out_T_49, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_165 = or(out_rofireMux_out_40, _out_rofireMux_T_164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_41 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_166 = and(_out_rofireMux_T_1, out_backSel_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_167 = and(_out_rofireMux_T_166, _out_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_41, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[24], _out_rofireMux_T_167 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[23], _out_rofireMux_T_167 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[22], _out_rofireMux_T_167 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[21], _out_rofireMux_T_167 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_168 = eq(_out_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_169 = or(out_rofireMux_out_41, _out_rofireMux_T_168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_42 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_170 = and(_out_rofireMux_T_1, out_backSel_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_171 = and(_out_rofireMux_T_170, _out_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_42, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[48], _out_rofireMux_T_171 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[47], _out_rofireMux_T_171 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[46], _out_rofireMux_T_171 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[45], _out_rofireMux_T_171 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_172 = eq(_out_T_21, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_173 = or(out_rofireMux_out_42, _out_rofireMux_T_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_43 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_174 = and(_out_rofireMux_T_1, out_backSel_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_175 = and(_out_rofireMux_T_174, _out_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_43, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[36], _out_rofireMux_T_175 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[35], _out_rofireMux_T_175 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[34], _out_rofireMux_T_175 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[33], _out_rofireMux_T_175 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_176 = eq(_out_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_177 = or(out_rofireMux_out_43, _out_rofireMux_T_176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_44 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_178 = and(_out_rofireMux_T_1, out_backSel_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_179 = and(_out_rofireMux_T_178, _out_T_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_44, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[111], _out_rofireMux_T_179 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[110], _out_rofireMux_T_179 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[109], _out_rofireMux_T_179 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[108], _out_rofireMux_T_179 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_180 = eq(_out_T_47, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_181 = or(out_rofireMux_out_44, _out_rofireMux_T_180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_45 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_182 = and(_out_rofireMux_T_1, out_backSel_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_183 = and(_out_rofireMux_T_182, _out_T_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_45, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[72], _out_rofireMux_T_183 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[71], _out_rofireMux_T_183 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[70], _out_rofireMux_T_183 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[69], _out_rofireMux_T_183 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_184 = eq(_out_T_35, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_185 = or(out_rofireMux_out_45, _out_rofireMux_T_184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_46 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_186 = and(_out_rofireMux_T_1, out_backSel_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_187 = and(_out_rofireMux_T_186, _out_T_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_46, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[59], _out_rofireMux_T_187 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[58], _out_rofireMux_T_187 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[57], _out_rofireMux_T_187 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[56], _out_rofireMux_T_187 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_188 = eq(_out_T_27, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_189 = or(out_rofireMux_out_46, _out_rofireMux_T_188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_47 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_190 = and(_out_rofireMux_T_1, out_backSel_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_191 = and(_out_rofireMux_T_190, _out_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_47, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[44], _out_rofireMux_T_191 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[43], _out_rofireMux_T_191 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[42], _out_rofireMux_T_191 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[41], _out_rofireMux_T_191 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_192 = eq(_out_T_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_193 = or(out_rofireMux_out_47, _out_rofireMux_T_192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_48 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_194 = and(_out_rofireMux_T_1, out_backSel_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_195 = and(_out_rofireMux_T_194, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_48, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_196 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_197 = or(out_rofireMux_out_48, _out_rofireMux_T_196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_49 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_198 = and(_out_rofireMux_T_1, out_backSel_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_199 = and(_out_rofireMux_T_198, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_49, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_200 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_201 = or(out_rofireMux_out_49, _out_rofireMux_T_200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_50 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_202 = and(_out_rofireMux_T_1, out_backSel_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_203 = and(_out_rofireMux_T_202, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_50, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_204 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_205 = or(out_rofireMux_out_50, _out_rofireMux_T_204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_51 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_206 = and(_out_rofireMux_T_1, out_backSel_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_207 = and(_out_rofireMux_T_206, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_51, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_208 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_209 = or(out_rofireMux_out_51, _out_rofireMux_T_208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_52 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_210 = and(_out_rofireMux_T_1, out_backSel_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_211 = and(_out_rofireMux_T_210, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_52, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_212 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_213 = or(out_rofireMux_out_52, _out_rofireMux_T_212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_53 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_214 = and(_out_rofireMux_T_1, out_backSel_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_215 = and(_out_rofireMux_T_214, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_53, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_216 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_217 = or(out_rofireMux_out_53, _out_rofireMux_T_216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_54 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_218 = and(_out_rofireMux_T_1, out_backSel_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_219 = and(_out_rofireMux_T_218, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_54, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_220 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_221 = or(out_rofireMux_out_54, _out_rofireMux_T_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_55 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_222 = and(_out_rofireMux_T_1, out_backSel_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_223 = and(_out_rofireMux_T_222, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_55, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_224 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_225 = or(out_rofireMux_out_55, _out_rofireMux_T_224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_56 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_226 = and(_out_rofireMux_T_1, out_backSel_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_227 = and(_out_rofireMux_T_226, _out_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_56, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[18], _out_rofireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[17], _out_rofireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[16], _out_rofireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[15], _out_rofireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[14], _out_rofireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[13], _out_rofireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[12], _out_rofireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[11], _out_rofireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[10], _out_rofireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[9], _out_rofireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[8], _out_rofireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[7], _out_rofireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[6], _out_rofireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[5], _out_rofireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[4], _out_rofireMux_T_227 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_228 = eq(_out_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_229 = or(out_rofireMux_out_56, _out_rofireMux_T_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_57 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_230 = and(_out_rofireMux_T_1, out_backSel_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_231 = and(_out_rofireMux_T_230, _out_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_57, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[60], _out_rofireMux_T_231 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_232 = eq(_out_T_29, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_233 = or(out_rofireMux_out_57, _out_rofireMux_T_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_58 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_234 = and(_out_rofireMux_T_1, out_backSel_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_235 = and(_out_rofireMux_T_234, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_58, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_236 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_237 = or(out_rofireMux_out_58, _out_rofireMux_T_236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_59 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_238 = and(_out_rofireMux_T_1, out_backSel_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_239 = and(_out_rofireMux_T_238, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_59, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_240 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_241 = or(out_rofireMux_out_59, _out_rofireMux_T_240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_60 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_242 = and(_out_rofireMux_T_1, out_backSel_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_243 = and(_out_rofireMux_T_242, _out_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_60, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[20], _out_rofireMux_T_243 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_244 = eq(_out_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_245 = or(out_rofireMux_out_60, _out_rofireMux_T_244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_61 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_246 = and(_out_rofireMux_T_1, out_backSel_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_247 = and(_out_rofireMux_T_246, _out_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_61, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[19], _out_rofireMux_T_247 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_248 = eq(_out_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_249 = or(out_rofireMux_out_61, _out_rofireMux_T_248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_62 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_250 = and(_out_rofireMux_T_1, out_backSel_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_251 = and(_out_rofireMux_T_250, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_62, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_252 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_253 = or(out_rofireMux_out_62, _out_rofireMux_T_252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_63 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_254 = and(_out_rofireMux_T_1, out_backSel_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_255 = and(_out_rofireMux_T_254, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_63, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_256 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_257 = or(out_rofireMux_out_63, _out_rofireMux_T_256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_258 = geq(out_oindex, UInt<7>(0h40)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_rofireMux_WIRE : UInt<1>[64] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[4], _out_rofireMux_T_21 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[5], _out_rofireMux_T_25 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[6], _out_rofireMux_T_29 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[7], _out_rofireMux_T_33 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[8], _out_rofireMux_T_37 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[9], _out_rofireMux_T_41 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[10], _out_rofireMux_T_45 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[11], _out_rofireMux_T_49 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[12], _out_rofireMux_T_53 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[13], _out_rofireMux_T_57 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[14], _out_rofireMux_T_61 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[15], _out_rofireMux_T_65 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[16], _out_rofireMux_T_69 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[17], _out_rofireMux_T_73 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[18], _out_rofireMux_T_77 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[19], _out_rofireMux_T_81 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[20], _out_rofireMux_T_85 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[21], _out_rofireMux_T_89 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[22], _out_rofireMux_T_93 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[23], _out_rofireMux_T_97 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[24], _out_rofireMux_T_101 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[25], _out_rofireMux_T_105 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[26], _out_rofireMux_T_109 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[27], _out_rofireMux_T_113 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[28], _out_rofireMux_T_117 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[29], _out_rofireMux_T_121 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[30], _out_rofireMux_T_125 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[31], _out_rofireMux_T_129 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[32], _out_rofireMux_T_133 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[33], _out_rofireMux_T_137 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[34], _out_rofireMux_T_141 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[35], _out_rofireMux_T_145 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[36], _out_rofireMux_T_149 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[37], _out_rofireMux_T_153 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[38], _out_rofireMux_T_157 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[39], _out_rofireMux_T_161 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[40], _out_rofireMux_T_165 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[41], _out_rofireMux_T_169 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[42], _out_rofireMux_T_173 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[43], _out_rofireMux_T_177 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[44], _out_rofireMux_T_181 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[45], _out_rofireMux_T_185 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[46], _out_rofireMux_T_189 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[47], _out_rofireMux_T_193 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[48], _out_rofireMux_T_197 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[49], _out_rofireMux_T_201 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[50], _out_rofireMux_T_205 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[51], _out_rofireMux_T_209 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[52], _out_rofireMux_T_213 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[53], _out_rofireMux_T_217 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[54], _out_rofireMux_T_221 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[55], _out_rofireMux_T_225 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[56], _out_rofireMux_T_229 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[57], _out_rofireMux_T_233 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[58], _out_rofireMux_T_237 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[59], _out_rofireMux_T_241 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[60], _out_rofireMux_T_245 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[61], _out_rofireMux_T_249 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[62], _out_rofireMux_T_253 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[63], _out_rofireMux_T_257 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_rofireMux = mux(_out_rofireMux_T_258, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_wofireMux_T = and(out_front.valid, out.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[73], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_5 = eq(_out_T_37, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_9 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_2 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_2, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_13 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_3 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_3, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_4 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_19 = and(_out_wofireMux_T_2, out_backSel_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_20 = and(_out_wofireMux_T_19, _out_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_4, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[40], _out_wofireMux_T_20 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[39], _out_wofireMux_T_20 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[38], _out_wofireMux_T_20 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[37], _out_wofireMux_T_20 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_21 = eq(_out_T_17, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_22 = or(out_wofireMux_out_4, _out_wofireMux_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_5 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_23 = and(_out_wofireMux_T_2, out_backSel_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_24 = and(_out_wofireMux_T_23, _out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_5, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[3], _out_wofireMux_T_24 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[2], _out_wofireMux_T_24 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[1], _out_wofireMux_T_24 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[0], _out_wofireMux_T_24 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_25 = eq(_out_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_26 = or(out_wofireMux_out_5, _out_wofireMux_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_6 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_27 = and(_out_wofireMux_T_2, out_backSel_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_28 = and(_out_wofireMux_T_27, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_6, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_29 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_30 = or(out_wofireMux_out_6, _out_wofireMux_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_7 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_31 = and(_out_wofireMux_T_2, out_backSel_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_32 = and(_out_wofireMux_T_31, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_7, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_33 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_34 = or(out_wofireMux_out_7, _out_wofireMux_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_8 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_35 = and(_out_wofireMux_T_2, out_backSel_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_36 = and(_out_wofireMux_T_35, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_8, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_37 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_38 = or(out_wofireMux_out_8, _out_wofireMux_T_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_9 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_39 = and(_out_wofireMux_T_2, out_backSel_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_40 = and(_out_wofireMux_T_39, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_9, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_41 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_42 = or(out_wofireMux_out_9, _out_wofireMux_T_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_10 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_43 = and(_out_wofireMux_T_2, out_backSel_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_44 = and(_out_wofireMux_T_43, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_10, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_45 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_46 = or(out_wofireMux_out_10, _out_wofireMux_T_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_11 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_47 = and(_out_wofireMux_T_2, out_backSel_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_48 = and(_out_wofireMux_T_47, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_11, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_49 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_50 = or(out_wofireMux_out_11, _out_wofireMux_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_12 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_51 = and(_out_wofireMux_T_2, out_backSel_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_52 = and(_out_wofireMux_T_51, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_12, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_53 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_54 = or(out_wofireMux_out_12, _out_wofireMux_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_13 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_55 = and(_out_wofireMux_T_2, out_backSel_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_56 = and(_out_wofireMux_T_55, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_13, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_57 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_58 = or(out_wofireMux_out_13, _out_wofireMux_T_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_14 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_59 = and(_out_wofireMux_T_2, out_backSel_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_60 = and(_out_wofireMux_T_59, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_14, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_61 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_62 = or(out_wofireMux_out_14, _out_wofireMux_T_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_15 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_63 = and(_out_wofireMux_T_2, out_backSel_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_64 = and(_out_wofireMux_T_63, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_15, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_65 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_66 = or(out_wofireMux_out_15, _out_wofireMux_T_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_16 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_67 = and(_out_wofireMux_T_2, out_backSel_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_68 = and(_out_wofireMux_T_67, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_16, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_69 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_70 = or(out_wofireMux_out_16, _out_wofireMux_T_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_17 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_71 = and(_out_wofireMux_T_2, out_backSel_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_72 = and(_out_wofireMux_T_71, _out_T_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_17, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[92], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[91], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[90], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[89], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[88], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[87], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[86], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[85], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[84], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[83], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[82], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[81], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[80], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[79], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[78], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[77], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[76], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[75], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[74], _out_wofireMux_T_72 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_73 = eq(_out_T_39, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_74 = or(out_wofireMux_out_17, _out_wofireMux_T_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_18 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_75 = and(_out_wofireMux_T_2, out_backSel_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_76 = and(_out_wofireMux_T_75, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_18, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_77 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_78 = or(out_wofireMux_out_18, _out_wofireMux_T_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_19 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_79 = and(_out_wofireMux_T_2, out_backSel_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_80 = and(_out_wofireMux_T_79, _out_T_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_19, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[121], _out_wofireMux_T_80 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_81 = eq(_out_T_55, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_82 = or(out_wofireMux_out_19, _out_wofireMux_T_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_20 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_83 = and(_out_wofireMux_T_2, out_backSel_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_84 = and(_out_wofireMux_T_83, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_20, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_85 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_86 = or(out_wofireMux_out_20, _out_wofireMux_T_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_21 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_87 = and(_out_wofireMux_T_2, out_backSel_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_88 = and(_out_wofireMux_T_87, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_21, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_89 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_90 = or(out_wofireMux_out_21, _out_wofireMux_T_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_22 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_91 = and(_out_wofireMux_T_2, out_backSel_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_92 = and(_out_wofireMux_T_91, _out_T_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_22, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[107], _out_wofireMux_T_92 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[106], _out_wofireMux_T_92 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[105], _out_wofireMux_T_92 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[104], _out_wofireMux_T_92 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[103], _out_wofireMux_T_92 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[102], _out_wofireMux_T_92 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[101], _out_wofireMux_T_92 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_93 = eq(_out_T_45, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_94 = or(out_wofireMux_out_22, _out_wofireMux_T_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_23 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_95 = and(_out_wofireMux_T_2, out_backSel_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_96 = and(_out_wofireMux_T_95, _out_T_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_23, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[116], _out_wofireMux_T_96 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_97 = eq(_out_T_51, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_98 = or(out_wofireMux_out_23, _out_wofireMux_T_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_24 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_99 = and(_out_wofireMux_T_2, out_backSel_24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_100 = and(_out_wofireMux_T_99, _out_T_23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_24, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[51], _out_wofireMux_T_100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[50], _out_wofireMux_T_100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[49], _out_wofireMux_T_100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_101 = eq(_out_T_23, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_102 = or(out_wofireMux_out_24, _out_wofireMux_T_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_25 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_103 = and(_out_wofireMux_T_2, out_backSel_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_104 = and(_out_wofireMux_T_103, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_25, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_105 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_106 = or(out_wofireMux_out_25, _out_wofireMux_T_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_26 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_107 = and(_out_wofireMux_T_2, out_backSel_26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_108 = and(_out_wofireMux_T_107, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_26, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_109 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_110 = or(out_wofireMux_out_26, _out_wofireMux_T_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_27 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_111 = and(_out_wofireMux_T_2, out_backSel_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_112 = and(_out_wofireMux_T_111, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_27, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_113 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_114 = or(out_wofireMux_out_27, _out_wofireMux_T_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_28 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_115 = and(_out_wofireMux_T_2, out_backSel_28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_116 = and(_out_wofireMux_T_115, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_28, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_117 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_118 = or(out_wofireMux_out_28, _out_wofireMux_T_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_29 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_119 = and(_out_wofireMux_T_2, out_backSel_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_120 = and(_out_wofireMux_T_119, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_29, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_121 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_122 = or(out_wofireMux_out_29, _out_wofireMux_T_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_30 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_123 = and(_out_wofireMux_T_2, out_backSel_30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_124 = and(_out_wofireMux_T_123, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_30, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_125 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_126 = or(out_wofireMux_out_30, _out_wofireMux_T_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_31 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_127 = and(_out_wofireMux_T_2, out_backSel_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_128 = and(_out_wofireMux_T_127, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_31, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_129 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_130 = or(out_wofireMux_out_31, _out_wofireMux_T_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_32 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_131 = and(_out_wofireMux_T_2, out_backSel_32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_132 = and(_out_wofireMux_T_131, _out_T_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_32, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[96], _out_wofireMux_T_132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[95], _out_wofireMux_T_132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[94], _out_wofireMux_T_132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[93], _out_wofireMux_T_132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_133 = eq(_out_T_41, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_134 = or(out_wofireMux_out_32, _out_wofireMux_T_133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_33 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_135 = and(_out_wofireMux_T_2, out_backSel_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_136 = and(_out_wofireMux_T_135, _out_T_33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_33, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[68], _out_wofireMux_T_136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[67], _out_wofireMux_T_136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[66], _out_wofireMux_T_136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[65], _out_wofireMux_T_136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_137 = eq(_out_T_33, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_138 = or(out_wofireMux_out_33, _out_wofireMux_T_137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_34 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_139 = and(_out_wofireMux_T_2, out_backSel_34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_140 = and(_out_wofireMux_T_139, _out_T_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_34, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[100], _out_wofireMux_T_140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[99], _out_wofireMux_T_140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[98], _out_wofireMux_T_140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[97], _out_wofireMux_T_140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_141 = eq(_out_T_43, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_142 = or(out_wofireMux_out_34, _out_wofireMux_T_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_35 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_143 = and(_out_wofireMux_T_2, out_backSel_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_144 = and(_out_wofireMux_T_143, _out_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_35, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[32], _out_wofireMux_T_144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[31], _out_wofireMux_T_144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[30], _out_wofireMux_T_144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[29], _out_wofireMux_T_144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_145 = eq(_out_T_13, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_146 = or(out_wofireMux_out_35, _out_wofireMux_T_145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_36 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_147 = and(_out_wofireMux_T_2, out_backSel_36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_148 = and(_out_wofireMux_T_147, _out_T_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_36, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[120], _out_wofireMux_T_148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[119], _out_wofireMux_T_148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[118], _out_wofireMux_T_148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[117], _out_wofireMux_T_148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_149 = eq(_out_T_53, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_150 = or(out_wofireMux_out_36, _out_wofireMux_T_149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_37 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_151 = and(_out_wofireMux_T_2, out_backSel_37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_152 = and(_out_wofireMux_T_151, _out_T_25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_37, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[55], _out_wofireMux_T_152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[54], _out_wofireMux_T_152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[53], _out_wofireMux_T_152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[52], _out_wofireMux_T_152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_153 = eq(_out_T_25, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_154 = or(out_wofireMux_out_37, _out_wofireMux_T_153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_38 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_155 = and(_out_wofireMux_T_2, out_backSel_38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_156 = and(_out_wofireMux_T_155, _out_T_31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_38, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[64], _out_wofireMux_T_156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[63], _out_wofireMux_T_156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[62], _out_wofireMux_T_156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[61], _out_wofireMux_T_156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_157 = eq(_out_T_31, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_158 = or(out_wofireMux_out_38, _out_wofireMux_T_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_39 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_159 = and(_out_wofireMux_T_2, out_backSel_39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_160 = and(_out_wofireMux_T_159, _out_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_39, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[28], _out_wofireMux_T_160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[27], _out_wofireMux_T_160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[26], _out_wofireMux_T_160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[25], _out_wofireMux_T_160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_161 = eq(_out_T_11, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_162 = or(out_wofireMux_out_39, _out_wofireMux_T_161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_40 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_163 = and(_out_wofireMux_T_2, out_backSel_40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_164 = and(_out_wofireMux_T_163, _out_T_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_40, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[115], _out_wofireMux_T_164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[114], _out_wofireMux_T_164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[113], _out_wofireMux_T_164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[112], _out_wofireMux_T_164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_165 = eq(_out_T_49, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_166 = or(out_wofireMux_out_40, _out_wofireMux_T_165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_41 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_167 = and(_out_wofireMux_T_2, out_backSel_41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_168 = and(_out_wofireMux_T_167, _out_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_41, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[24], _out_wofireMux_T_168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[23], _out_wofireMux_T_168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[22], _out_wofireMux_T_168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[21], _out_wofireMux_T_168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_169 = eq(_out_T_9, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_170 = or(out_wofireMux_out_41, _out_wofireMux_T_169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_42 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_171 = and(_out_wofireMux_T_2, out_backSel_42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_172 = and(_out_wofireMux_T_171, _out_T_21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_42, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[48], _out_wofireMux_T_172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[47], _out_wofireMux_T_172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[46], _out_wofireMux_T_172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[45], _out_wofireMux_T_172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_173 = eq(_out_T_21, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_174 = or(out_wofireMux_out_42, _out_wofireMux_T_173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_43 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_175 = and(_out_wofireMux_T_2, out_backSel_43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_176 = and(_out_wofireMux_T_175, _out_T_15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_43, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[36], _out_wofireMux_T_176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[35], _out_wofireMux_T_176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[34], _out_wofireMux_T_176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[33], _out_wofireMux_T_176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_177 = eq(_out_T_15, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_178 = or(out_wofireMux_out_43, _out_wofireMux_T_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_44 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_179 = and(_out_wofireMux_T_2, out_backSel_44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_180 = and(_out_wofireMux_T_179, _out_T_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_44, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[111], _out_wofireMux_T_180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[110], _out_wofireMux_T_180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[109], _out_wofireMux_T_180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[108], _out_wofireMux_T_180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_181 = eq(_out_T_47, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_182 = or(out_wofireMux_out_44, _out_wofireMux_T_181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_45 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_183 = and(_out_wofireMux_T_2, out_backSel_45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_184 = and(_out_wofireMux_T_183, _out_T_35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_45, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[72], _out_wofireMux_T_184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[71], _out_wofireMux_T_184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[70], _out_wofireMux_T_184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[69], _out_wofireMux_T_184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_185 = eq(_out_T_35, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_186 = or(out_wofireMux_out_45, _out_wofireMux_T_185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_46 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_187 = and(_out_wofireMux_T_2, out_backSel_46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_188 = and(_out_wofireMux_T_187, _out_T_27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_46, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[59], _out_wofireMux_T_188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[58], _out_wofireMux_T_188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[57], _out_wofireMux_T_188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[56], _out_wofireMux_T_188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_189 = eq(_out_T_27, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_190 = or(out_wofireMux_out_46, _out_wofireMux_T_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_47 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_191 = and(_out_wofireMux_T_2, out_backSel_47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_192 = and(_out_wofireMux_T_191, _out_T_19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_47, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[44], _out_wofireMux_T_192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[43], _out_wofireMux_T_192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[42], _out_wofireMux_T_192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[41], _out_wofireMux_T_192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_193 = eq(_out_T_19, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_194 = or(out_wofireMux_out_47, _out_wofireMux_T_193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_48 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_195 = and(_out_wofireMux_T_2, out_backSel_48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_196 = and(_out_wofireMux_T_195, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_48, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_197 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_198 = or(out_wofireMux_out_48, _out_wofireMux_T_197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_49 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_199 = and(_out_wofireMux_T_2, out_backSel_49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_200 = and(_out_wofireMux_T_199, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_49, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_201 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_202 = or(out_wofireMux_out_49, _out_wofireMux_T_201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_50 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_203 = and(_out_wofireMux_T_2, out_backSel_50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_204 = and(_out_wofireMux_T_203, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_50, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_205 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_206 = or(out_wofireMux_out_50, _out_wofireMux_T_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_51 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_207 = and(_out_wofireMux_T_2, out_backSel_51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_208 = and(_out_wofireMux_T_207, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_51, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_209 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_210 = or(out_wofireMux_out_51, _out_wofireMux_T_209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_52 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_211 = and(_out_wofireMux_T_2, out_backSel_52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_212 = and(_out_wofireMux_T_211, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_52, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_213 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_214 = or(out_wofireMux_out_52, _out_wofireMux_T_213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_53 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_215 = and(_out_wofireMux_T_2, out_backSel_53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_216 = and(_out_wofireMux_T_215, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_53, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_217 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_218 = or(out_wofireMux_out_53, _out_wofireMux_T_217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_54 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_219 = and(_out_wofireMux_T_2, out_backSel_54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_220 = and(_out_wofireMux_T_219, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_54, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_221 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_222 = or(out_wofireMux_out_54, _out_wofireMux_T_221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_55 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_223 = and(_out_wofireMux_T_2, out_backSel_55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_224 = and(_out_wofireMux_T_223, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_55, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_225 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_226 = or(out_wofireMux_out_55, _out_wofireMux_T_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_56 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_227 = and(_out_wofireMux_T_2, out_backSel_56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_228 = and(_out_wofireMux_T_227, _out_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_56, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[18], _out_wofireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[17], _out_wofireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[16], _out_wofireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[15], _out_wofireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[14], _out_wofireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[13], _out_wofireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[12], _out_wofireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[11], _out_wofireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[10], _out_wofireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[9], _out_wofireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[8], _out_wofireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[7], _out_wofireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[6], _out_wofireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[5], _out_wofireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[4], _out_wofireMux_T_228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_229 = eq(_out_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_230 = or(out_wofireMux_out_56, _out_wofireMux_T_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_57 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_231 = and(_out_wofireMux_T_2, out_backSel_57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_232 = and(_out_wofireMux_T_231, _out_T_29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_57, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[60], _out_wofireMux_T_232 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_233 = eq(_out_T_29, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_234 = or(out_wofireMux_out_57, _out_wofireMux_T_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_58 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_235 = and(_out_wofireMux_T_2, out_backSel_58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_236 = and(_out_wofireMux_T_235, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_58, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_237 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_238 = or(out_wofireMux_out_58, _out_wofireMux_T_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_59 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_239 = and(_out_wofireMux_T_2, out_backSel_59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_240 = and(_out_wofireMux_T_239, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_59, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_241 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_242 = or(out_wofireMux_out_59, _out_wofireMux_T_241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_60 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_243 = and(_out_wofireMux_T_2, out_backSel_60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_244 = and(_out_wofireMux_T_243, _out_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_60, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[20], _out_wofireMux_T_244 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_245 = eq(_out_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_246 = or(out_wofireMux_out_60, _out_wofireMux_T_245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_61 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_247 = and(_out_wofireMux_T_2, out_backSel_61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_248 = and(_out_wofireMux_T_247, _out_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_61, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[19], _out_wofireMux_T_248 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_249 = eq(_out_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_250 = or(out_wofireMux_out_61, _out_wofireMux_T_249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_62 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_251 = and(_out_wofireMux_T_2, out_backSel_62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_252 = and(_out_wofireMux_T_251, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_62, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_253 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_254 = or(out_wofireMux_out_62, _out_wofireMux_T_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_63 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_255 = and(_out_wofireMux_T_2, out_backSel_63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_256 = and(_out_wofireMux_T_255, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_63, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_257 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_258 = or(out_wofireMux_out_63, _out_wofireMux_T_257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_259 = geq(out_oindex, UInt<7>(0h40)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_wofireMux_WIRE : UInt<1>[64] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[4], _out_wofireMux_T_22 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[5], _out_wofireMux_T_26 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[6], _out_wofireMux_T_30 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[7], _out_wofireMux_T_34 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[8], _out_wofireMux_T_38 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[9], _out_wofireMux_T_42 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[10], _out_wofireMux_T_46 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[11], _out_wofireMux_T_50 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[12], _out_wofireMux_T_54 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[13], _out_wofireMux_T_58 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[14], _out_wofireMux_T_62 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[15], _out_wofireMux_T_66 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[16], _out_wofireMux_T_70 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[17], _out_wofireMux_T_74 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[18], _out_wofireMux_T_78 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[19], _out_wofireMux_T_82 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[20], _out_wofireMux_T_86 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[21], _out_wofireMux_T_90 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[22], _out_wofireMux_T_94 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[23], _out_wofireMux_T_98 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[24], _out_wofireMux_T_102 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[25], _out_wofireMux_T_106 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[26], _out_wofireMux_T_110 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[27], _out_wofireMux_T_114 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[28], _out_wofireMux_T_118 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[29], _out_wofireMux_T_122 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[30], _out_wofireMux_T_126 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[31], _out_wofireMux_T_130 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[32], _out_wofireMux_T_134 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[33], _out_wofireMux_T_138 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[34], _out_wofireMux_T_142 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[35], _out_wofireMux_T_146 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[36], _out_wofireMux_T_150 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[37], _out_wofireMux_T_154 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[38], _out_wofireMux_T_158 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[39], _out_wofireMux_T_162 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[40], _out_wofireMux_T_166 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[41], _out_wofireMux_T_170 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[42], _out_wofireMux_T_174 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[43], _out_wofireMux_T_178 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[44], _out_wofireMux_T_182 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[45], _out_wofireMux_T_186 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[46], _out_wofireMux_T_190 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[47], _out_wofireMux_T_194 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[48], _out_wofireMux_T_198 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[49], _out_wofireMux_T_202 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[50], _out_wofireMux_T_206 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[51], _out_wofireMux_T_210 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[52], _out_wofireMux_T_214 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[53], _out_wofireMux_T_218 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[54], _out_wofireMux_T_222 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[55], _out_wofireMux_T_226 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[56], _out_wofireMux_T_230 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[57], _out_wofireMux_T_234 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[58], _out_wofireMux_T_238 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[59], _out_wofireMux_T_242 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[60], _out_wofireMux_T_246 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[61], _out_wofireMux_T_250 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[62], _out_wofireMux_T_254 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[63], _out_wofireMux_T_258 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_wofireMux = mux(_out_wofireMux_T_259, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_in_ready_T = and(out_front.ready, out_iready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect in.ready, _out_in_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_front_valid_T = and(in.valid, out_iready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front.valid, _out_front_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_front_ready_T = and(out.ready, out_oready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front.ready, _out_front_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_out_valid_T = and(out_front.valid, out_oready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.valid, _out_out_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.read, out_front.bits.read @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_out_bits_data_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 52:28] connect out_out_bits_data_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 52:28] node _out_out_bits_data_T = eq(UInt<1>(0h0), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_37 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_1 = eq(UInt<3>(0h4), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_17 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_2 = eq(UInt<3>(0h5), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_2 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_3 = eq(UInt<5>(0h11), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_3 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_39 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_4 = eq(UInt<5>(0h13), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_4 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_55 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_5 = eq(UInt<5>(0h16), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_5 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_45 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_6 = eq(UInt<5>(0h17), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_6 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_51 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_7 = eq(UInt<5>(0h18), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_7 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_23 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_8 = eq(UInt<6>(0h20), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_8 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_41 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_9 = eq(UInt<6>(0h21), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_9 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_33 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_10 = eq(UInt<6>(0h22), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_10 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_43 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_11 = eq(UInt<6>(0h23), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_11 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_13 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_12 = eq(UInt<6>(0h24), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_12 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_53 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_13 = eq(UInt<6>(0h25), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_13 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_25 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_14 = eq(UInt<6>(0h26), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_14 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_31 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_15 = eq(UInt<6>(0h27), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_15 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_16 = eq(UInt<6>(0h28), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_16 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_49 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_17 = eq(UInt<6>(0h29), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_17 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_9 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_18 = eq(UInt<6>(0h2a), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_18 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_21 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_19 = eq(UInt<6>(0h2b), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_19 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_15 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_20 = eq(UInt<6>(0h2c), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_20 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_47 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_21 = eq(UInt<6>(0h2d), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_21 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_35 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_22 = eq(UInt<6>(0h2e), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_22 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_27 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_23 = eq(UInt<6>(0h2f), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_23 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_19 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_24 = eq(UInt<6>(0h38), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_24 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_25 = eq(UInt<6>(0h39), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_25 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_29 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_26 = eq(UInt<6>(0h3c), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_26 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_27 = eq(UInt<6>(0h3d), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_27 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out, _out_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] wire out_out_bits_data_out_1 : UInt @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 52:28] connect out_out_bits_data_out_1, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 52:28] node _out_out_bits_data_T_28 = eq(UInt<1>(0h0), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_28 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_847 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_29 = eq(UInt<3>(0h4), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_29 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_488 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_30 = eq(UInt<3>(0h5), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_30 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_99 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_31 = eq(UInt<5>(0h11), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_31 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_32 = eq(UInt<5>(0h13), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_32 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_1323 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_33 = eq(UInt<5>(0h16), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_33 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_1171 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_34 = eq(UInt<5>(0h17), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_34 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_35 = eq(UInt<5>(0h18), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_35 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_607 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_36 = eq(UInt<6>(0h20), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_36 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_37 = eq(UInt<6>(0h21), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_37 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_38 = eq(UInt<6>(0h22), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_38 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_39 = eq(UInt<6>(0h23), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_39 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_400 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_40 = eq(UInt<6>(0h24), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_40 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_1314 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_41 = eq(UInt<6>(0h25), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_41 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_651 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_42 = eq(UInt<6>(0h26), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_42 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_750 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_43 = eq(UInt<6>(0h27), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_43 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_356 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_44 = eq(UInt<6>(0h28), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_44 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_1259 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_45 = eq(UInt<6>(0h29), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_45 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_312 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_46 = eq(UInt<6>(0h2a), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_46 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_576 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_47 = eq(UInt<6>(0h2b), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_47 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_444 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_48 = eq(UInt<6>(0h2c), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_48 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_1215 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_49 = eq(UInt<6>(0h2d), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_49 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_50 = eq(UInt<6>(0h2e), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_50 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_695 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_51 = eq(UInt<6>(0h2f), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_51 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_532 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_52 = eq(UInt<6>(0h38), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_52 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_246 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_53 = eq(UInt<6>(0h39), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_53 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_54 = eq(UInt<6>(0h3c), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_54 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] else : node _out_out_bits_data_T_55 = eq(UInt<6>(0h3d), out_oindex) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] when _out_out_bits_data_T_55 : @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:22] connect out_out_bits_data_out_1, _out_T_257 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 54:28] node _out_out_bits_data_T_56 = mux(out_out_bits_data_out, out_out_bits_data_out_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.data, _out_out_bits_data_T_56 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.extra, out_front.bits.extra @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect in.valid, dmiNodeIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 90:15] connect dmiNodeIn.a.ready, in.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 91:15] connect dmiNodeIn.d.valid, out.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 92:15] connect out.ready, dmiNodeIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 93:15] wire dmiNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 792:17] connect dmiNodeIn_d_bits_d.opcode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 793:15] connect dmiNodeIn_d_bits_d.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 794:15] connect dmiNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 795:15] connect dmiNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 796:15] connect dmiNodeIn_d_bits_d.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 797:15] connect dmiNodeIn_d_bits_d.denied, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 798:15] invalidate dmiNodeIn_d_bits_d.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 801:15] connect dmiNodeIn_d_bits_d.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 802:15] connect dmiNodeIn.d.bits.corrupt, dmiNodeIn_d_bits_d.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect dmiNodeIn.d.bits.data, dmiNodeIn_d_bits_d.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect dmiNodeIn.d.bits.denied, dmiNodeIn_d_bits_d.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect dmiNodeIn.d.bits.sink, dmiNodeIn_d_bits_d.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect dmiNodeIn.d.bits.source, dmiNodeIn_d_bits_d.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect dmiNodeIn.d.bits.size, dmiNodeIn_d_bits_d.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect dmiNodeIn.d.bits.param, dmiNodeIn_d_bits_d.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect dmiNodeIn.d.bits.opcode, dmiNodeIn_d_bits_d.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect dmiNodeIn.d.bits.data, out.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 100:17] node _dmiNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 105:25] connect dmiNodeIn.d.bits.opcode, _dmiNodeIn_d_bits_opcode_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 105:19] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 108:22] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 109:22] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 110:22] node _T_286 = and(UInt<1>(0h1), dmiAbstractDataWrEnMaybe[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:29] node _T_287 = and(_T_286, dmiAbstractDataAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:60] when _T_287 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:91] connect abstractDataMem[0], abstractDataNxt[0] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1463:11] node _T_288 = and(UInt<1>(0h1), dmiAbstractDataWrEnMaybe[1]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:29] node _T_289 = and(_T_288, dmiAbstractDataAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:60] when _T_289 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:91] connect abstractDataMem[1], abstractDataNxt[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1463:11] node _T_290 = and(UInt<1>(0h1), dmiAbstractDataWrEnMaybe[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:29] node _T_291 = and(_T_290, dmiAbstractDataAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:60] when _T_291 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:91] connect abstractDataMem[2], abstractDataNxt[2] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1463:11] node _T_292 = and(UInt<1>(0h1), dmiAbstractDataWrEnMaybe[3]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:29] node _T_293 = and(_T_292, dmiAbstractDataAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:60] when _T_293 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:91] connect abstractDataMem[3], abstractDataNxt[3] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1463:11] node _T_294 = and(UInt<1>(0h1), dmiAbstractDataWrEnMaybe[4]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:29] node _T_295 = and(_T_294, dmiAbstractDataAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:60] when _T_295 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:91] connect abstractDataMem[4], abstractDataNxt[4] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1463:11] node _T_296 = and(UInt<1>(0h1), dmiAbstractDataWrEnMaybe[5]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:29] node _T_297 = and(_T_296, dmiAbstractDataAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:60] when _T_297 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:91] connect abstractDataMem[5], abstractDataNxt[5] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1463:11] node _T_298 = and(UInt<1>(0h1), dmiAbstractDataWrEnMaybe[6]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:29] node _T_299 = and(_T_298, dmiAbstractDataAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:60] when _T_299 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:91] connect abstractDataMem[6], abstractDataNxt[6] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1463:11] node _T_300 = and(UInt<1>(0h1), dmiAbstractDataWrEnMaybe[7]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:29] node _T_301 = and(_T_300, dmiAbstractDataAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:60] when _T_301 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1462:91] connect abstractDataMem[7], abstractDataNxt[7] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1463:11] node _T_302 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[0]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_303 = and(_T_302, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_303 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[0], programBufferNxt[0] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_304 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[1]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_305 = and(_T_304, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_305 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[1], programBufferNxt[1] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_306 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[2]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_307 = and(_T_306, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_307 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[2], programBufferNxt[2] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_308 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[3]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_309 = and(_T_308, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_309 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[3], programBufferNxt[3] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_310 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[4]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_311 = and(_T_310, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_311 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[4], programBufferNxt[4] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_312 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[5]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_313 = and(_T_312, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_313 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[5], programBufferNxt[5] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_314 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[6]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_315 = and(_T_314, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_315 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[6], programBufferNxt[6] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_316 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[7]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_317 = and(_T_316, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_317 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[7], programBufferNxt[7] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_318 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[8]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_319 = and(_T_318, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_319 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[8], programBufferNxt[8] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_320 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[9]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_321 = and(_T_320, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_321 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[9], programBufferNxt[9] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_322 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[10]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_323 = and(_T_322, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_323 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[10], programBufferNxt[10] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_324 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[11]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_325 = and(_T_324, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_325 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[11], programBufferNxt[11] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_326 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[12]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_327 = and(_T_326, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_327 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[12], programBufferNxt[12] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_328 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[13]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_329 = and(_T_328, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_329 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[13], programBufferNxt[13] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_330 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[14]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_331 = and(_T_330, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_331 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[14], programBufferNxt[14] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_332 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[15]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_333 = and(_T_332, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_333 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[15], programBufferNxt[15] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_334 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[16]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_335 = and(_T_334, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_335 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[16], programBufferNxt[16] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_336 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[17]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_337 = and(_T_336, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_337 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[17], programBufferNxt[17] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_338 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[18]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_339 = and(_T_338, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_339 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[18], programBufferNxt[18] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_340 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[19]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_341 = and(_T_340, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_341 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[19], programBufferNxt[19] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_342 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[20]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_343 = and(_T_342, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_343 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[20], programBufferNxt[20] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_344 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[21]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_345 = and(_T_344, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_345 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[21], programBufferNxt[21] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_346 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[22]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_347 = and(_T_346, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_347 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[22], programBufferNxt[22] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_348 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[23]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_349 = and(_T_348, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_349 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[23], programBufferNxt[23] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_350 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[24]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_351 = and(_T_350, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_351 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[24], programBufferNxt[24] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_352 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[25]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_353 = and(_T_352, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_353 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[25], programBufferNxt[25] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_354 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[26]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_355 = and(_T_354, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_355 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[26], programBufferNxt[26] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_356 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[27]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_357 = and(_T_356, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_357 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[27], programBufferNxt[27] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_358 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[28]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_359 = and(_T_358, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_359 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[28], programBufferNxt[28] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_360 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[29]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_361 = and(_T_360, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_361 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[29], programBufferNxt[29] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_362 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[30]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_363 = and(_T_362, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_363 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[30], programBufferNxt[30] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_364 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[31]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_365 = and(_T_364, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_365 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[31], programBufferNxt[31] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_366 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[32]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_367 = and(_T_366, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_367 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[32], programBufferNxt[32] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_368 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[33]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_369 = and(_T_368, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_369 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[33], programBufferNxt[33] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_370 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[34]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_371 = and(_T_370, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_371 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[34], programBufferNxt[34] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_372 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[35]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_373 = and(_T_372, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_373 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[35], programBufferNxt[35] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_374 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[36]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_375 = and(_T_374, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_375 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[36], programBufferNxt[36] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_376 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[37]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_377 = and(_T_376, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_377 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[37], programBufferNxt[37] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_378 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[38]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_379 = and(_T_378, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_379 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[38], programBufferNxt[38] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_380 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[39]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_381 = and(_T_380, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_381 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[39], programBufferNxt[39] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_382 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[40]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_383 = and(_T_382, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_383 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[40], programBufferNxt[40] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_384 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[41]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_385 = and(_T_384, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_385 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[41], programBufferNxt[41] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_386 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[42]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_387 = and(_T_386, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_387 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[42], programBufferNxt[42] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_388 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[43]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_389 = and(_T_388, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_389 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[43], programBufferNxt[43] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_390 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[44]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_391 = and(_T_390, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_391 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[44], programBufferNxt[44] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_392 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[45]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_393 = and(_T_392, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_393 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[45], programBufferNxt[45] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_394 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[46]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_395 = and(_T_394, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_395 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[46], programBufferNxt[46] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_396 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[47]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_397 = and(_T_396, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_397 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[47], programBufferNxt[47] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_398 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[48]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_399 = and(_T_398, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_399 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[48], programBufferNxt[48] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_400 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[49]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_401 = and(_T_400, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_401 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[49], programBufferNxt[49] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_402 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[50]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_403 = and(_T_402, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_403 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[50], programBufferNxt[50] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_404 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[51]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_405 = and(_T_404, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_405 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[51], programBufferNxt[51] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_406 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[52]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_407 = and(_T_406, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_407 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[52], programBufferNxt[52] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_408 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[53]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_409 = and(_T_408, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_409 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[53], programBufferNxt[53] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_410 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[54]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_411 = and(_T_410, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_411 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[54], programBufferNxt[54] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_412 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[55]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_413 = and(_T_412, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_413 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[55], programBufferNxt[55] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_414 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[56]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_415 = and(_T_414, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_415 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[56], programBufferNxt[56] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_416 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[57]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_417 = and(_T_416, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_417 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[57], programBufferNxt[57] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_418 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[58]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_419 = and(_T_418, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_419 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[58], programBufferNxt[58] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_420 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[59]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_421 = and(_T_420, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_421 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[59], programBufferNxt[59] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_422 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[60]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_423 = and(_T_422, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_423 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[60], programBufferNxt[60] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_424 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[61]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_425 = and(_T_424, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_425 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[61], programBufferNxt[61] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_426 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[62]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_427 = and(_T_426, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_427 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[62], programBufferNxt[62] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] node _T_428 = and(UInt<1>(0h1), dmiProgramBufferWrEnMaybe[63]) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:29] node _T_429 = and(_T_428, dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:61] when _T_429 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1484:93] connect programBufferMem[63], programBufferNxt[63] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1485:11] reg goReg : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1493:27] wire goAbstract : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1494:32] connect goAbstract, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1494:32] wire goCustom : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1495:32] connect goCustom, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1495:32] wire _jalAbstract_WIRE : { imm3 : UInt<1>, imm0 : UInt<10>, imm1 : UInt<1>, imm2 : UInt<8>, rd : UInt<5>, opcode : UInt<7>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1496:66] connect _jalAbstract_WIRE.opcode, UInt<7>(0h6f) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1496:66] connect _jalAbstract_WIRE.rd, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1496:66] connect _jalAbstract_WIRE.imm2, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1496:66] connect _jalAbstract_WIRE.imm1, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1496:66] connect _jalAbstract_WIRE.imm0, UInt<10>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1496:66] connect _jalAbstract_WIRE.imm3, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1496:66] wire jalAbstract : { imm3 : UInt<1>, imm0 : UInt<10>, imm1 : UInt<1>, imm2 : UInt<8>, rd : UInt<5>, opcode : UInt<7>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1496:32] connect jalAbstract, _jalAbstract_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1496:32] wire immWire : SInt<21> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1573:31] connect immWire, asSInt(UInt<21>(0h38)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1573:31] node _immBits_T = bits(immWire, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_1 = bits(immWire, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_2 = bits(immWire, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_3 = bits(immWire, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_4 = bits(immWire, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_5 = bits(immWire, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_6 = bits(immWire, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_7 = bits(immWire, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_8 = bits(immWire, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_9 = bits(immWire, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_10 = bits(immWire, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_11 = bits(immWire, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_12 = bits(immWire, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_13 = bits(immWire, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_14 = bits(immWire, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_15 = bits(immWire, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_16 = bits(immWire, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_17 = bits(immWire, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_18 = bits(immWire, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_19 = bits(immWire, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] node _immBits_T_20 = bits(immWire, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:48] wire _immBits_WIRE : UInt<1>[21] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[0], _immBits_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[1], _immBits_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[2], _immBits_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[3], _immBits_T_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[4], _immBits_T_4 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[5], _immBits_T_5 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[6], _immBits_T_6 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[7], _immBits_T_7 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[8], _immBits_T_8 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[9], _immBits_T_9 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[10], _immBits_T_10 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[11], _immBits_T_11 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[12], _immBits_T_12 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[13], _immBits_T_13 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[14], _immBits_T_14 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[15], _immBits_T_15 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[16], _immBits_T_16 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[17], _immBits_T_17 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[18], _immBits_T_18 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[19], _immBits_T_19 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] connect _immBits_WIRE[20], _immBits_T_20 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:39] wire immBits : UInt<1>[21] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:31] connect immBits, _immBits_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1574:31] node jalAbstract_imm0_lo_lo = cat(immBits[2], immBits[1]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm0_lo_hi_hi = cat(immBits[5], immBits[4]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm0_lo_hi = cat(jalAbstract_imm0_lo_hi_hi, immBits[3]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm0_lo = cat(jalAbstract_imm0_lo_hi, jalAbstract_imm0_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm0_hi_lo = cat(immBits[7], immBits[6]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm0_hi_hi_hi = cat(immBits[10], immBits[9]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm0_hi_hi = cat(jalAbstract_imm0_hi_hi_hi, immBits[8]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm0_hi = cat(jalAbstract_imm0_hi_hi, jalAbstract_imm0_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _jalAbstract_imm0_T = cat(jalAbstract_imm0_hi, jalAbstract_imm0_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] connect jalAbstract.imm0, _jalAbstract_imm0_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1576:14] node jalAbstract_imm1_lo_lo = cat(immBits[12], immBits[11]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm1_lo_hi_hi = cat(immBits[15], immBits[14]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm1_lo_hi = cat(jalAbstract_imm1_lo_hi_hi, immBits[13]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm1_lo = cat(jalAbstract_imm1_lo_hi, jalAbstract_imm1_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm1_hi_lo = cat(immBits[17], immBits[16]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm1_hi_hi_hi = cat(immBits[20], immBits[19]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm1_hi_hi = cat(jalAbstract_imm1_hi_hi_hi, immBits[18]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm1_hi = cat(jalAbstract_imm1_hi_hi, jalAbstract_imm1_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _jalAbstract_imm1_T = cat(jalAbstract_imm1_hi, jalAbstract_imm1_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] connect jalAbstract.imm1, _jalAbstract_imm1_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1577:14] node jalAbstract_imm2_lo_lo = cat(immBits[13], immBits[12]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm2_lo_hi = cat(immBits[15], immBits[14]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm2_lo = cat(jalAbstract_imm2_lo_hi, jalAbstract_imm2_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm2_hi_lo = cat(immBits[17], immBits[16]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm2_hi_hi = cat(immBits[19], immBits[18]) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node jalAbstract_imm2_hi = cat(jalAbstract_imm2_hi_hi, jalAbstract_imm2_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] node _jalAbstract_imm2_T = cat(jalAbstract_imm2_hi, jalAbstract_imm2_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/package.scala 46:27] connect jalAbstract.imm2, _jalAbstract_imm2_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1578:14] connect jalAbstract.imm3, immBits[20] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1579:14] node _T_430 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1499:11] when _T_430 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1499:24] connect goReg, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1500:13] else : when goAbstract : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1502:25] connect goReg, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1503:15] else : when hartGoingWrEn : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1504:33] node _T_431 = eq(hartGoingId, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1505:28] node _T_432 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1505:15] node _T_433 = eq(_T_432, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1505:15] when _T_433 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1505:15] node _T_434 = eq(_T_431, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1505:15] when _T_434 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1505:15] printf(clock, UInt<1>(0h1), "Assertion failed: Unexpected 'GOING' hart.\n at Debug.scala:1505 assert(hartGoingId === 0.U, \"Unexpected 'GOING' hart.\")//Chisel3 #540 %%%%x, expected %%%%x\", hartGoingId, 0.U)\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1505:15] assert(clock, _T_431, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1505:15] connect goReg, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1506:15] wire _flags_WIRE : { reserved : UInt<6>, resume : UInt<1>, go : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1516:87] connect _flags_WIRE.go, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1516:87] connect _flags_WIRE.resume, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1516:87] connect _flags_WIRE.reserved, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1516:87] wire _flags_WIRE_1 : { reserved : UInt<6>, resume : UInt<1>, go : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1516:87] connect _flags_WIRE_1.go, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1516:87] connect _flags_WIRE_1.resume, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1516:87] connect _flags_WIRE_1.reserved, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1516:87] wire _flags_WIRE_2 : { reserved : UInt<6>, resume : UInt<1>, go : UInt<1>}[2] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1516:33] connect _flags_WIRE_2[0].go, _flags_WIRE.go @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1516:33] connect _flags_WIRE_2[0].resume, _flags_WIRE.resume @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1516:33] connect _flags_WIRE_2[0].reserved, _flags_WIRE.reserved @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1516:33] connect _flags_WIRE_2[1].go, _flags_WIRE_1.go @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1516:33] connect _flags_WIRE_2[1].resume, _flags_WIRE_1.resume @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1516:33] connect _flags_WIRE_2[1].reserved, _flags_WIRE_1.reserved @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1516:33] wire flags : { reserved : UInt<6>, resume : UInt<1>, go : UInt<1>}[2] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1516:25] connect flags, _flags_WIRE_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1516:25] node _T_435 = lt(selectedHartReg, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1517:60] node _T_436 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1517:12] node _T_437 = eq(_T_436, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1517:12] when _T_437 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1517:12] node _T_438 = eq(_T_435, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1517:12] when _T_438 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1517:12] printf(clock, UInt<1>(0h1), "Assertion failed: HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < 2 for it to work.\n at Debug.scala:1517 assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U),\n") : printf_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1517:12] assert(clock, _T_435, UInt<1>(0h1), "") : assert_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1517:12] connect flags[selectedHartReg].go, goReg @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1519:61] wire componentSel : UInt @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1522:34] connect componentSel, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1522:34] node _T_439 = or(componentSel, UInt<1>(0h0)) node _T_440 = bits(_T_439, 0, 0) node _flags_resume_T = bits(resumeReqRegs, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1523:80] connect flags[_T_440].resume, _flags_resume_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1523:64] node _accessRegisterCommandWr_T = cat(COMMANDWrData.cmdtype, COMMANDWrData.control) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:59] wire _accessRegisterCommandWr_WIRE : { cmdtype : UInt<8>, reserved0 : UInt<1>, size : UInt<3>, reserved1 : UInt<1>, postexec : UInt<1>, transfer : UInt<1>, write : UInt<1>, regno : UInt<16>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] wire _accessRegisterCommandWr_WIRE_1 : UInt<32> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] connect _accessRegisterCommandWr_WIRE_1, _accessRegisterCommandWr_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] node _accessRegisterCommandWr_T_1 = bits(_accessRegisterCommandWr_WIRE_1, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] connect _accessRegisterCommandWr_WIRE.regno, _accessRegisterCommandWr_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] node _accessRegisterCommandWr_T_2 = bits(_accessRegisterCommandWr_WIRE_1, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] connect _accessRegisterCommandWr_WIRE.write, _accessRegisterCommandWr_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] node _accessRegisterCommandWr_T_3 = bits(_accessRegisterCommandWr_WIRE_1, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] connect _accessRegisterCommandWr_WIRE.transfer, _accessRegisterCommandWr_T_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] node _accessRegisterCommandWr_T_4 = bits(_accessRegisterCommandWr_WIRE_1, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] connect _accessRegisterCommandWr_WIRE.postexec, _accessRegisterCommandWr_T_4 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] node _accessRegisterCommandWr_T_5 = bits(_accessRegisterCommandWr_WIRE_1, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] connect _accessRegisterCommandWr_WIRE.reserved1, _accessRegisterCommandWr_T_5 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] node _accessRegisterCommandWr_T_6 = bits(_accessRegisterCommandWr_WIRE_1, 22, 20) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] connect _accessRegisterCommandWr_WIRE.size, _accessRegisterCommandWr_T_6 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] node _accessRegisterCommandWr_T_7 = bits(_accessRegisterCommandWr_WIRE_1, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] connect _accessRegisterCommandWr_WIRE.reserved0, _accessRegisterCommandWr_T_7 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] node _accessRegisterCommandWr_T_8 = bits(_accessRegisterCommandWr_WIRE_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] connect _accessRegisterCommandWr_WIRE.cmdtype, _accessRegisterCommandWr_T_8 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:74] wire accessRegisterCommandWr : { cmdtype : UInt<8>, reserved0 : UInt<1>, size : UInt<3>, reserved1 : UInt<1>, postexec : UInt<1>, transfer : UInt<1>, write : UInt<1>, regno : UInt<16>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:44] connect accessRegisterCommandWr, _accessRegisterCommandWr_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1530:44] node _accessRegisterCommandReg_T = cat(COMMANDReg.cmdtype, COMMANDReg.control) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:56] wire _accessRegisterCommandReg_WIRE : { cmdtype : UInt<8>, reserved0 : UInt<1>, size : UInt<3>, reserved1 : UInt<1>, postexec : UInt<1>, transfer : UInt<1>, write : UInt<1>, regno : UInt<16>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] wire _accessRegisterCommandReg_WIRE_1 : UInt<32> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] connect _accessRegisterCommandReg_WIRE_1, _accessRegisterCommandReg_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] node _accessRegisterCommandReg_T_1 = bits(_accessRegisterCommandReg_WIRE_1, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] connect _accessRegisterCommandReg_WIRE.regno, _accessRegisterCommandReg_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] node _accessRegisterCommandReg_T_2 = bits(_accessRegisterCommandReg_WIRE_1, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] connect _accessRegisterCommandReg_WIRE.write, _accessRegisterCommandReg_T_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] node _accessRegisterCommandReg_T_3 = bits(_accessRegisterCommandReg_WIRE_1, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] connect _accessRegisterCommandReg_WIRE.transfer, _accessRegisterCommandReg_T_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] node _accessRegisterCommandReg_T_4 = bits(_accessRegisterCommandReg_WIRE_1, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] connect _accessRegisterCommandReg_WIRE.postexec, _accessRegisterCommandReg_T_4 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] node _accessRegisterCommandReg_T_5 = bits(_accessRegisterCommandReg_WIRE_1, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] connect _accessRegisterCommandReg_WIRE.reserved1, _accessRegisterCommandReg_T_5 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] node _accessRegisterCommandReg_T_6 = bits(_accessRegisterCommandReg_WIRE_1, 22, 20) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] connect _accessRegisterCommandReg_WIRE.size, _accessRegisterCommandReg_T_6 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] node _accessRegisterCommandReg_T_7 = bits(_accessRegisterCommandReg_WIRE_1, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] connect _accessRegisterCommandReg_WIRE.reserved0, _accessRegisterCommandReg_T_7 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] node _accessRegisterCommandReg_T_8 = bits(_accessRegisterCommandReg_WIRE_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] connect _accessRegisterCommandReg_WIRE.cmdtype, _accessRegisterCommandReg_T_8 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:71] wire accessRegisterCommandReg : { cmdtype : UInt<8>, reserved0 : UInt<1>, size : UInt<3>, reserved1 : UInt<1>, postexec : UInt<1>, transfer : UInt<1>, write : UInt<1>, regno : UInt<16>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:44] connect accessRegisterCommandReg, _accessRegisterCommandReg_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1532:44] reg abstractGeneratedMem : UInt<32>[2], clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1585:35] wire nop : { imm : UInt<12>, rs1 : UInt<5>, funct3 : UInt<3>, rd : UInt<5>, opcode : UInt<7>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1622:19] wire _nop_WIRE : { imm : UInt<12>, rs1 : UInt<5>, funct3 : UInt<3>, rd : UInt<5>, opcode : UInt<7>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1623:46] connect _nop_WIRE.opcode, UInt<7>(0h13) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1623:46] connect _nop_WIRE.rd, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1623:46] connect _nop_WIRE.funct3, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1623:46] connect _nop_WIRE.rs1, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1623:46] connect _nop_WIRE.imm, UInt<12>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1623:46] connect nop, _nop_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1623:9] connect nop.rd, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1624:14] connect nop.rs1, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1625:14] connect nop.imm, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1626:14] wire isa : { imm : UInt<12>, rs1 : UInt<5>, funct3 : UInt<3>, rd : UInt<5>, opcode : UInt<7>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1628:19] wire _isa_WIRE : { imm : UInt<12>, rs1 : UInt<5>, funct3 : UInt<3>, rd : UInt<5>, opcode : UInt<7>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1629:47] connect _isa_WIRE.opcode, UInt<7>(0h1b) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1629:47] connect _isa_WIRE.rd, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1629:47] connect _isa_WIRE.funct3, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1629:47] connect _isa_WIRE.rs1, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1629:47] connect _isa_WIRE.imm, UInt<12>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1629:47] connect isa, _isa_WIRE @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1629:9] connect isa.rd, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1630:14] connect isa.rs1, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1631:14] connect isa.imm, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1632:14] when goAbstract : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1635:23] wire abstractGeneratedMem_0_inst : { imm : UInt<12>, rs1 : UInt<5>, funct3 : UInt<3>, rd : UInt<5>, opcode : UInt<7>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1588:22] wire _abstractGeneratedMem_0_inst_opcode_WIRE : { imm : UInt<12>, rs1 : UInt<5>, funct3 : UInt<3>, rd : UInt<5>, opcode : UInt<7>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1591:55] connect _abstractGeneratedMem_0_inst_opcode_WIRE.opcode, UInt<7>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1591:55] connect _abstractGeneratedMem_0_inst_opcode_WIRE.rd, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1591:55] connect _abstractGeneratedMem_0_inst_opcode_WIRE.funct3, UInt<3>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1591:55] connect _abstractGeneratedMem_0_inst_opcode_WIRE.rs1, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1591:55] connect _abstractGeneratedMem_0_inst_opcode_WIRE.imm, UInt<12>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1591:55] connect abstractGeneratedMem_0_inst.opcode, _abstractGeneratedMem_0_inst_opcode_WIRE.opcode @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1591:19] node _abstractGeneratedMem_0_inst_rd_T = and(accessRegisterCommandReg.regno, UInt<5>(0h1f)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1592:54] connect abstractGeneratedMem_0_inst.rd, _abstractGeneratedMem_0_inst_rd_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1592:19] connect abstractGeneratedMem_0_inst.funct3, accessRegisterCommandReg.size @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1593:19] connect abstractGeneratedMem_0_inst.rs1, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1594:19] connect abstractGeneratedMem_0_inst.imm, UInt<10>(0h380) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1595:19] node abstractGeneratedMem_0_lo = cat(abstractGeneratedMem_0_inst.rd, abstractGeneratedMem_0_inst.opcode) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1596:12] node abstractGeneratedMem_0_hi_hi = cat(abstractGeneratedMem_0_inst.imm, abstractGeneratedMem_0_inst.rs1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1596:12] node abstractGeneratedMem_0_hi = cat(abstractGeneratedMem_0_hi_hi, abstractGeneratedMem_0_inst.funct3) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1596:12] node _abstractGeneratedMem_0_T = cat(abstractGeneratedMem_0_hi, abstractGeneratedMem_0_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1596:12] wire abstractGeneratedMem_0_inst_1 : { immhi : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, funct3 : UInt<3>, immlo : UInt<5>, opcode : UInt<7>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1600:22] wire _abstractGeneratedMem_0_inst_opcode_WIRE_1 : { immhi : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, funct3 : UInt<3>, immlo : UInt<5>, opcode : UInt<7>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1603:55] connect _abstractGeneratedMem_0_inst_opcode_WIRE_1.opcode, UInt<7>(0h23) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1603:55] connect _abstractGeneratedMem_0_inst_opcode_WIRE_1.immlo, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1603:55] connect _abstractGeneratedMem_0_inst_opcode_WIRE_1.funct3, UInt<3>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1603:55] connect _abstractGeneratedMem_0_inst_opcode_WIRE_1.rs1, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1603:55] connect _abstractGeneratedMem_0_inst_opcode_WIRE_1.rs2, UInt<5>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1603:55] connect _abstractGeneratedMem_0_inst_opcode_WIRE_1.immhi, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1603:55] connect abstractGeneratedMem_0_inst_1.opcode, _abstractGeneratedMem_0_inst_opcode_WIRE_1.opcode @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1603:19] connect abstractGeneratedMem_0_inst_1.immlo, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1604:19] connect abstractGeneratedMem_0_inst_1.funct3, accessRegisterCommandReg.size @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1605:19] connect abstractGeneratedMem_0_inst_1.rs1, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1606:19] node _abstractGeneratedMem_0_inst_rs2_T = and(accessRegisterCommandReg.regno, UInt<5>(0h1f)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1607:54] connect abstractGeneratedMem_0_inst_1.rs2, _abstractGeneratedMem_0_inst_rs2_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1607:19] connect abstractGeneratedMem_0_inst_1.immhi, UInt<5>(0h1c) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1608:19] node abstractGeneratedMem_0_lo_hi = cat(abstractGeneratedMem_0_inst_1.funct3, abstractGeneratedMem_0_inst_1.immlo) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1609:12] node abstractGeneratedMem_0_lo_1 = cat(abstractGeneratedMem_0_lo_hi, abstractGeneratedMem_0_inst_1.opcode) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1609:12] node abstractGeneratedMem_0_hi_hi_1 = cat(abstractGeneratedMem_0_inst_1.immhi, abstractGeneratedMem_0_inst_1.rs2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1609:12] node abstractGeneratedMem_0_hi_1 = cat(abstractGeneratedMem_0_hi_hi_1, abstractGeneratedMem_0_inst_1.rs1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1609:12] node _abstractGeneratedMem_0_T_1 = cat(abstractGeneratedMem_0_hi_1, abstractGeneratedMem_0_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1609:12] node _abstractGeneratedMem_0_T_2 = mux(accessRegisterCommandReg.write, _abstractGeneratedMem_0_T, _abstractGeneratedMem_0_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1640:14] node abstractGeneratedMem_0_lo_2 = cat(nop.rd, nop.opcode) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1641:15] node abstractGeneratedMem_0_hi_hi_2 = cat(nop.imm, nop.rs1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1641:15] node abstractGeneratedMem_0_hi_2 = cat(abstractGeneratedMem_0_hi_hi_2, nop.funct3) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1641:15] node _abstractGeneratedMem_0_T_3 = cat(abstractGeneratedMem_0_hi_2, abstractGeneratedMem_0_lo_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1641:15] node _abstractGeneratedMem_0_T_4 = mux(accessRegisterCommandReg.transfer, _abstractGeneratedMem_0_T_2, _abstractGeneratedMem_0_T_3) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1639:39] connect abstractGeneratedMem[0], _abstractGeneratedMem_0_T_4 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1639:33] node abstractGeneratedMem_1_lo = cat(nop.rd, nop.opcode) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1644:15] node abstractGeneratedMem_1_hi_hi = cat(nop.imm, nop.rs1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1644:15] node abstractGeneratedMem_1_hi = cat(abstractGeneratedMem_1_hi_hi, nop.funct3) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1644:15] node _abstractGeneratedMem_1_T = cat(abstractGeneratedMem_1_hi, abstractGeneratedMem_1_lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1644:15] node _abstractGeneratedMem_1_T_1 = mux(accessRegisterCommandReg.postexec, _abstractGeneratedMem_1_T, UInt<21>(0h100073)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1643:39] connect abstractGeneratedMem[1], _abstractGeneratedMem_1_T_1 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1643:33] node lo_hi = cat(jalAbstract.imm2, jalAbstract.rd) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1696:55] node lo = cat(lo_hi, jalAbstract.opcode) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1696:55] node hi_hi = cat(jalAbstract.imm3, jalAbstract.imm0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1696:55] node hi = cat(hi_hi, jalAbstract.imm1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1696:55] node _T_441 = cat(hi, lo) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1696:55] node hi_1 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_442 = cat(hi_1, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_2 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_443 = cat(hi_2, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_3 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_444 = cat(hi_3, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_4 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_445 = cat(hi_4, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_5 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_446 = cat(hi_5, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_6 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_447 = cat(hi_6, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_7 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_448 = cat(hi_7, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_8 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_449 = cat(hi_8, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_9 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_450 = cat(hi_9, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_10 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_451 = cat(hi_10, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_11 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_452 = cat(hi_11, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_12 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_453 = cat(hi_12, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_13 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_454 = cat(hi_13, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_14 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_455 = cat(hi_14, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_15 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_456 = cat(hi_15, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_16 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_457 = cat(hi_16, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_17 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_458 = cat(hi_17, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_18 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_459 = cat(hi_18, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_19 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_460 = cat(hi_19, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_20 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_461 = cat(hi_20, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_21 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_462 = cat(hi_21, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_22 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_463 = cat(hi_22, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_23 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_464 = cat(hi_23, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_24 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_465 = cat(hi_24, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_25 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_466 = cat(hi_25, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_26 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_467 = cat(hi_26, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_27 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_468 = cat(hi_27, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_28 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_469 = cat(hi_28, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_29 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_470 = cat(hi_29, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_30 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_471 = cat(hi_30, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_31 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_472 = cat(hi_31, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_32 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_473 = cat(hi_32, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_33 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_474 = cat(hi_33, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_34 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_475 = cat(hi_34, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_35 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_476 = cat(hi_35, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_36 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_477 = cat(hi_36, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_37 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_478 = cat(hi_37, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_38 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_479 = cat(hi_38, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_39 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_480 = cat(hi_39, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_40 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_481 = cat(hi_40, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_41 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_482 = cat(hi_41, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_42 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_483 = cat(hi_42, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_43 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_484 = cat(hi_43, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_44 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_485 = cat(hi_44, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_45 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_486 = cat(hi_45, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_46 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_487 = cat(hi_46, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_47 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_488 = cat(hi_47, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_48 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_489 = cat(hi_48, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_49 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_490 = cat(hi_49, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_50 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_491 = cat(hi_50, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_51 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_492 = cat(hi_51, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_52 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_493 = cat(hi_52, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_53 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_494 = cat(hi_53, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_54 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_495 = cat(hi_54, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_55 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_496 = cat(hi_55, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_56 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_497 = cat(hi_56, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_57 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_498 = cat(hi_57, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_58 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_499 = cat(hi_58, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_59 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_500 = cat(hi_59, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_60 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_501 = cat(hi_60, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_61 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_502 = cat(hi_61, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_62 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_503 = cat(hi_62, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_63 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_504 = cat(hi_63, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_64 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_505 = cat(hi_64, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_65 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_506 = cat(hi_65, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_66 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_507 = cat(hi_66, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_67 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_508 = cat(hi_67, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_68 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_509 = cat(hi_68, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_69 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_510 = cat(hi_69, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_70 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_511 = cat(hi_70, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_71 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_512 = cat(hi_71, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_72 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_513 = cat(hi_72, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_73 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_514 = cat(hi_73, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_74 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_515 = cat(hi_74, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_75 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_516 = cat(hi_75, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_76 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_517 = cat(hi_76, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_77 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_518 = cat(hi_77, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_78 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_519 = cat(hi_78, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_79 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_520 = cat(hi_79, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_80 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_521 = cat(hi_80, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_81 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_522 = cat(hi_81, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_82 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_523 = cat(hi_82, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_83 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_524 = cat(hi_83, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_84 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_525 = cat(hi_84, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_85 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_526 = cat(hi_85, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_86 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_527 = cat(hi_86, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_87 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_528 = cat(hi_87, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_88 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_529 = cat(hi_88, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_89 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_530 = cat(hi_89, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_90 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_531 = cat(hi_90, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_91 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_532 = cat(hi_91, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_92 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_533 = cat(hi_92, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_93 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_534 = cat(hi_93, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_94 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_535 = cat(hi_94, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_95 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_536 = cat(hi_95, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_96 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_537 = cat(hi_96, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_97 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_538 = cat(hi_97, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_98 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_539 = cat(hi_98, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_99 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_540 = cat(hi_99, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_100 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_541 = cat(hi_100, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_101 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_542 = cat(hi_101, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_102 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_543 = cat(hi_102, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_103 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_544 = cat(hi_103, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_104 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_545 = cat(hi_104, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_105 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_546 = cat(hi_105, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_106 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_547 = cat(hi_106, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_107 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_548 = cat(hi_107, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_108 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_549 = cat(hi_108, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_109 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_550 = cat(hi_109, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_110 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_551 = cat(hi_110, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_111 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_552 = cat(hi_111, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_112 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_553 = cat(hi_112, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_113 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_554 = cat(hi_113, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_114 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_555 = cat(hi_114, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_115 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_556 = cat(hi_115, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_116 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_557 = cat(hi_116, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_117 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_558 = cat(hi_117, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_118 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_559 = cat(hi_118, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_119 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_560 = cat(hi_119, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_120 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_561 = cat(hi_120, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_121 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_562 = cat(hi_121, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_122 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_563 = cat(hi_122, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_123 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_564 = cat(hi_123, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_124 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_565 = cat(hi_124, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_125 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_566 = cat(hi_125, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_126 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_567 = cat(hi_126, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_127 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_568 = cat(hi_127, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_128 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_569 = cat(hi_128, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_129 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_570 = cat(hi_129, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_130 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_571 = cat(hi_130, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_131 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_572 = cat(hi_131, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_132 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_573 = cat(hi_132, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_133 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_574 = cat(hi_133, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_134 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_575 = cat(hi_134, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_135 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_576 = cat(hi_135, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_136 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_577 = cat(hi_136, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_137 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_578 = cat(hi_137, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_138 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_579 = cat(hi_138, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_139 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_580 = cat(hi_139, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_140 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_581 = cat(hi_140, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_141 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_582 = cat(hi_141, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_142 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_583 = cat(hi_142, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_143 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_584 = cat(hi_143, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_144 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_585 = cat(hi_144, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_145 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_586 = cat(hi_145, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_146 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_587 = cat(hi_146, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_147 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_588 = cat(hi_147, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_148 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_589 = cat(hi_148, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_149 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_590 = cat(hi_149, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_150 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_591 = cat(hi_150, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_151 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_592 = cat(hi_151, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_152 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_593 = cat(hi_152, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_153 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_594 = cat(hi_153, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_154 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_595 = cat(hi_154, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_155 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_596 = cat(hi_155, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_156 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_597 = cat(hi_156, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_157 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_598 = cat(hi_157, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_158 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_599 = cat(hi_158, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_159 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_600 = cat(hi_159, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_160 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_601 = cat(hi_160, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_161 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_602 = cat(hi_161, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_162 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_603 = cat(hi_162, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_163 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_604 = cat(hi_163, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_164 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_605 = cat(hi_164, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_165 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_606 = cat(hi_165, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_166 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_607 = cat(hi_166, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_167 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_608 = cat(hi_167, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_168 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_609 = cat(hi_168, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_169 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_610 = cat(hi_169, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_170 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_611 = cat(hi_170, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_171 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_612 = cat(hi_171, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_172 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_613 = cat(hi_172, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_173 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_614 = cat(hi_173, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_174 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_615 = cat(hi_174, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_175 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_616 = cat(hi_175, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_176 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_617 = cat(hi_176, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_177 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_618 = cat(hi_177, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_178 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_619 = cat(hi_178, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_179 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_620 = cat(hi_179, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_180 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_621 = cat(hi_180, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_181 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_622 = cat(hi_181, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_182 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_623 = cat(hi_182, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_183 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_624 = cat(hi_183, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_184 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_625 = cat(hi_184, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_185 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_626 = cat(hi_185, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_186 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_627 = cat(hi_186, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_187 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_628 = cat(hi_187, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_188 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_629 = cat(hi_188, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_189 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_630 = cat(hi_189, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_190 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_631 = cat(hi_190, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_191 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_632 = cat(hi_191, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_192 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_633 = cat(hi_192, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_193 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_634 = cat(hi_193, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_194 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_635 = cat(hi_194, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_195 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_636 = cat(hi_195, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_196 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_637 = cat(hi_196, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_197 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_638 = cat(hi_197, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_198 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_639 = cat(hi_198, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_199 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_640 = cat(hi_199, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_200 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_641 = cat(hi_200, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_201 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_642 = cat(hi_201, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_202 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_643 = cat(hi_202, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_203 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_644 = cat(hi_203, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_204 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_645 = cat(hi_204, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_205 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_646 = cat(hi_205, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_206 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_647 = cat(hi_206, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_207 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_648 = cat(hi_207, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_208 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_649 = cat(hi_208, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_209 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_650 = cat(hi_209, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_210 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_651 = cat(hi_210, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_211 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_652 = cat(hi_211, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_212 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_653 = cat(hi_212, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_213 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_654 = cat(hi_213, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_214 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_655 = cat(hi_214, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_215 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_656 = cat(hi_215, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_216 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_657 = cat(hi_216, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_217 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_658 = cat(hi_217, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_218 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_659 = cat(hi_218, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_219 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_660 = cat(hi_219, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_220 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_661 = cat(hi_220, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_221 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_662 = cat(hi_221, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_222 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_663 = cat(hi_222, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_223 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_664 = cat(hi_223, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_224 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_665 = cat(hi_224, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_225 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_666 = cat(hi_225, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_226 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_667 = cat(hi_226, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_227 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_668 = cat(hi_227, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_228 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_669 = cat(hi_228, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_229 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_670 = cat(hi_229, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_230 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_671 = cat(hi_230, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_231 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_672 = cat(hi_231, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_232 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_673 = cat(hi_232, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_233 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_674 = cat(hi_233, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_234 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_675 = cat(hi_234, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_235 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_676 = cat(hi_235, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_236 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_677 = cat(hi_236, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_237 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_678 = cat(hi_237, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_238 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_679 = cat(hi_238, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_239 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_680 = cat(hi_239, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_240 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_681 = cat(hi_240, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_241 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_682 = cat(hi_241, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_242 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_683 = cat(hi_242, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_243 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_684 = cat(hi_243, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_244 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_685 = cat(hi_244, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_245 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_686 = cat(hi_245, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_246 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_687 = cat(hi_246, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_247 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_688 = cat(hi_247, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_248 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_689 = cat(hi_248, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_249 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_690 = cat(hi_249, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_250 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_691 = cat(hi_250, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_251 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_692 = cat(hi_251, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_252 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_693 = cat(hi_252, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_253 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_694 = cat(hi_253, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_254 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_695 = cat(hi_254, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_255 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_696 = cat(hi_255, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_256 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_697 = cat(hi_256, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_257 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_698 = cat(hi_257, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_258 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_699 = cat(hi_258, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_259 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_700 = cat(hi_259, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_260 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_701 = cat(hi_260, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_261 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_702 = cat(hi_261, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_262 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_703 = cat(hi_262, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_263 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_704 = cat(hi_263, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_264 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_705 = cat(hi_264, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_265 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_706 = cat(hi_265, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_266 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_707 = cat(hi_266, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_267 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_708 = cat(hi_267, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_268 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_709 = cat(hi_268, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_269 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_710 = cat(hi_269, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_270 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_711 = cat(hi_270, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_271 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_712 = cat(hi_271, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_272 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_713 = cat(hi_272, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_273 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_714 = cat(hi_273, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_274 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_715 = cat(hi_274, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_275 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_716 = cat(hi_275, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_276 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_717 = cat(hi_276, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_277 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_718 = cat(hi_277, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_278 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_719 = cat(hi_278, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_279 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_720 = cat(hi_279, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_280 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_721 = cat(hi_280, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_281 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_722 = cat(hi_281, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_282 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_723 = cat(hi_282, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_283 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_724 = cat(hi_283, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_284 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_725 = cat(hi_284, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_285 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_726 = cat(hi_285, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_286 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_727 = cat(hi_286, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_287 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_728 = cat(hi_287, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_288 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_729 = cat(hi_288, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_289 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_730 = cat(hi_289, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_290 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_731 = cat(hi_290, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_291 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_732 = cat(hi_291, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_292 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_733 = cat(hi_292, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_293 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_734 = cat(hi_293, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_294 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_735 = cat(hi_294, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_295 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_736 = cat(hi_295, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_296 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_737 = cat(hi_296, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_297 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_738 = cat(hi_297, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_298 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_739 = cat(hi_298, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_299 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_740 = cat(hi_299, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_300 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_741 = cat(hi_300, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_301 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_742 = cat(hi_301, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_302 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_743 = cat(hi_302, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_303 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_744 = cat(hi_303, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_304 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_745 = cat(hi_304, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_305 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_746 = cat(hi_305, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_306 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_747 = cat(hi_306, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_307 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_748 = cat(hi_307, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_308 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_749 = cat(hi_308, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_309 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_750 = cat(hi_309, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_310 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_751 = cat(hi_310, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_311 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_752 = cat(hi_311, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_312 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_753 = cat(hi_312, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_313 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_754 = cat(hi_313, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_314 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_755 = cat(hi_314, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_315 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_756 = cat(hi_315, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_316 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_757 = cat(hi_316, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_317 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_758 = cat(hi_317, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_318 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_759 = cat(hi_318, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_319 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_760 = cat(hi_319, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_320 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_761 = cat(hi_320, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_321 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_762 = cat(hi_321, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_322 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_763 = cat(hi_322, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_323 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_764 = cat(hi_323, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_324 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_765 = cat(hi_324, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_325 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_766 = cat(hi_325, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_326 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_767 = cat(hi_326, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_327 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_768 = cat(hi_327, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_328 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_769 = cat(hi_328, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_329 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_770 = cat(hi_329, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_330 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_771 = cat(hi_330, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_331 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_772 = cat(hi_331, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_332 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_773 = cat(hi_332, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_333 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_774 = cat(hi_333, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_334 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_775 = cat(hi_334, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_335 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_776 = cat(hi_335, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_336 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_777 = cat(hi_336, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_337 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_778 = cat(hi_337, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_338 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_779 = cat(hi_338, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_339 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_780 = cat(hi_339, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_340 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_781 = cat(hi_340, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_341 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_782 = cat(hi_341, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_342 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_783 = cat(hi_342, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_343 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_784 = cat(hi_343, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_344 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_785 = cat(hi_344, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_345 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_786 = cat(hi_345, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_346 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_787 = cat(hi_346, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_347 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_788 = cat(hi_347, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_348 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_789 = cat(hi_348, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_349 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_790 = cat(hi_349, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_350 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_791 = cat(hi_350, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_351 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_792 = cat(hi_351, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_352 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_793 = cat(hi_352, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_353 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_794 = cat(hi_353, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_354 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_795 = cat(hi_354, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_355 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_796 = cat(hi_355, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_356 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_797 = cat(hi_356, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_357 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_798 = cat(hi_357, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_358 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_799 = cat(hi_358, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_359 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_800 = cat(hi_359, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_360 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_801 = cat(hi_360, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_361 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_802 = cat(hi_361, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_362 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_803 = cat(hi_362, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_363 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_804 = cat(hi_363, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_364 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_805 = cat(hi_364, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_365 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_806 = cat(hi_365, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_366 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_807 = cat(hi_366, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_367 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_808 = cat(hi_367, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_368 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_809 = cat(hi_368, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_369 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_810 = cat(hi_369, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_370 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_811 = cat(hi_370, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_371 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_812 = cat(hi_371, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_372 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_813 = cat(hi_372, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_373 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_814 = cat(hi_373, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_374 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_815 = cat(hi_374, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_375 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_816 = cat(hi_375, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_376 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_817 = cat(hi_376, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_377 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_818 = cat(hi_377, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_378 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_819 = cat(hi_378, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_379 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_820 = cat(hi_379, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_380 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_821 = cat(hi_380, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_381 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_822 = cat(hi_381, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_382 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_823 = cat(hi_382, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_383 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_824 = cat(hi_383, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_384 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_825 = cat(hi_384, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_385 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_826 = cat(hi_385, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_386 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_827 = cat(hi_386, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_387 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_828 = cat(hi_387, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_388 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_829 = cat(hi_388, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_389 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_830 = cat(hi_389, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_390 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_831 = cat(hi_390, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_391 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_832 = cat(hi_391, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_392 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_833 = cat(hi_392, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_393 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_834 = cat(hi_393, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_394 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_835 = cat(hi_394, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_395 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_836 = cat(hi_395, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_396 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_837 = cat(hi_396, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_397 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_838 = cat(hi_397, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_398 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_839 = cat(hi_398, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_399 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_840 = cat(hi_399, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_400 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_841 = cat(hi_400, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_401 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_842 = cat(hi_401, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_402 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_843 = cat(hi_402, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_403 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_844 = cat(hi_403, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_404 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_845 = cat(hi_404, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_405 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_846 = cat(hi_405, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_406 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_847 = cat(hi_406, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_407 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_848 = cat(hi_407, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_408 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_849 = cat(hi_408, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_409 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_850 = cat(hi_409, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_410 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_851 = cat(hi_410, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_411 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_852 = cat(hi_411, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_412 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_853 = cat(hi_412, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_413 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_854 = cat(hi_413, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_414 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_855 = cat(hi_414, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_415 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_856 = cat(hi_415, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_416 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_857 = cat(hi_416, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_417 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_858 = cat(hi_417, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_418 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_859 = cat(hi_418, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_419 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_860 = cat(hi_419, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_420 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_861 = cat(hi_420, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_421 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_862 = cat(hi_421, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_422 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_863 = cat(hi_422, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_423 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_864 = cat(hi_423, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_424 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_865 = cat(hi_424, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_425 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_866 = cat(hi_425, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_426 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_867 = cat(hi_426, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_427 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_868 = cat(hi_427, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_428 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_869 = cat(hi_428, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_429 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_870 = cat(hi_429, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_430 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_871 = cat(hi_430, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_431 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_872 = cat(hi_431, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_432 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_873 = cat(hi_432, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_433 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_874 = cat(hi_433, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_434 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_875 = cat(hi_434, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_435 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_876 = cat(hi_435, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_436 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_877 = cat(hi_436, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_437 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_878 = cat(hi_437, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_438 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_879 = cat(hi_438, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_439 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_880 = cat(hi_439, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_440 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_881 = cat(hi_440, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_441 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_882 = cat(hi_441, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_442 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_883 = cat(hi_442, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_443 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_884 = cat(hi_443, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_444 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_885 = cat(hi_444, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_445 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_886 = cat(hi_445, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_446 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_887 = cat(hi_446, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_447 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_888 = cat(hi_447, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_448 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_889 = cat(hi_448, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_449 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_890 = cat(hi_449, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_450 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_891 = cat(hi_450, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_451 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_892 = cat(hi_451, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_452 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_893 = cat(hi_452, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_453 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_894 = cat(hi_453, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_454 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_895 = cat(hi_454, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_455 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_896 = cat(hi_455, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_456 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_897 = cat(hi_456, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_457 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_898 = cat(hi_457, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_458 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_899 = cat(hi_458, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_459 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_900 = cat(hi_459, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_460 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_901 = cat(hi_460, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_461 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_902 = cat(hi_461, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_462 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_903 = cat(hi_462, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_463 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_904 = cat(hi_463, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_464 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_905 = cat(hi_464, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_465 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_906 = cat(hi_465, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_466 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_907 = cat(hi_466, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_467 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_908 = cat(hi_467, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_468 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_909 = cat(hi_468, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_469 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_910 = cat(hi_469, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_470 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_911 = cat(hi_470, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_471 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_912 = cat(hi_471, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_472 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_913 = cat(hi_472, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_473 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_914 = cat(hi_473, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_474 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_915 = cat(hi_474, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_475 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_916 = cat(hi_475, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_476 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_917 = cat(hi_476, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_477 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_918 = cat(hi_477, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_478 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_919 = cat(hi_478, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_479 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_920 = cat(hi_479, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_480 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_921 = cat(hi_480, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_481 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_922 = cat(hi_481, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_482 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_923 = cat(hi_482, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_483 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_924 = cat(hi_483, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_484 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_925 = cat(hi_484, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_485 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_926 = cat(hi_485, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_486 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_927 = cat(hi_486, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_487 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_928 = cat(hi_487, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_488 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_929 = cat(hi_488, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_489 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_930 = cat(hi_489, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_490 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_931 = cat(hi_490, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_491 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_932 = cat(hi_491, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_492 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_933 = cat(hi_492, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_493 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_934 = cat(hi_493, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_494 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_935 = cat(hi_494, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_495 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_936 = cat(hi_495, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_496 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_937 = cat(hi_496, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_497 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_938 = cat(hi_497, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_498 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_939 = cat(hi_498, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_499 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_940 = cat(hi_499, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_500 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_941 = cat(hi_500, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_501 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_942 = cat(hi_501, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_502 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_943 = cat(hi_502, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_503 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_944 = cat(hi_503, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_504 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_945 = cat(hi_504, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_505 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_946 = cat(hi_505, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_506 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_947 = cat(hi_506, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_507 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_948 = cat(hi_507, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_508 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_949 = cat(hi_508, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_509 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_950 = cat(hi_509, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_510 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_951 = cat(hi_510, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_511 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_952 = cat(hi_511, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_512 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_953 = cat(hi_512, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_513 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_954 = cat(hi_513, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_514 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_955 = cat(hi_514, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_515 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_956 = cat(hi_515, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_516 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_957 = cat(hi_516, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_517 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_958 = cat(hi_517, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_518 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_959 = cat(hi_518, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_519 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_960 = cat(hi_519, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_520 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_961 = cat(hi_520, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_521 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_962 = cat(hi_521, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_522 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_963 = cat(hi_522, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_523 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_964 = cat(hi_523, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_524 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_965 = cat(hi_524, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_525 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_966 = cat(hi_525, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_526 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_967 = cat(hi_526, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_527 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_968 = cat(hi_527, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_528 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_969 = cat(hi_528, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_529 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_970 = cat(hi_529, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_530 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_971 = cat(hi_530, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_531 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_972 = cat(hi_531, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_532 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_973 = cat(hi_532, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_533 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_974 = cat(hi_533, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_534 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_975 = cat(hi_534, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_535 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_976 = cat(hi_535, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_536 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_977 = cat(hi_536, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_537 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_978 = cat(hi_537, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_538 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_979 = cat(hi_538, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_539 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_980 = cat(hi_539, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_540 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_981 = cat(hi_540, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_541 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_982 = cat(hi_541, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_542 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_983 = cat(hi_542, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_543 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_984 = cat(hi_543, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_544 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_985 = cat(hi_544, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_545 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_986 = cat(hi_545, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_546 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_987 = cat(hi_546, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_547 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_988 = cat(hi_547, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_548 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_989 = cat(hi_548, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_549 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_990 = cat(hi_549, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_550 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_991 = cat(hi_550, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_551 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_992 = cat(hi_551, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_552 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_993 = cat(hi_552, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_553 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_994 = cat(hi_553, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_554 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_995 = cat(hi_554, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_555 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_996 = cat(hi_555, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_556 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_997 = cat(hi_556, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_557 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_998 = cat(hi_557, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_558 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_999 = cat(hi_558, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_559 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1000 = cat(hi_559, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_560 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1001 = cat(hi_560, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_561 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1002 = cat(hi_561, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_562 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1003 = cat(hi_562, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_563 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1004 = cat(hi_563, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_564 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1005 = cat(hi_564, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_565 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1006 = cat(hi_565, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_566 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1007 = cat(hi_566, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_567 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1008 = cat(hi_567, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_568 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1009 = cat(hi_568, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_569 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1010 = cat(hi_569, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_570 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1011 = cat(hi_570, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_571 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1012 = cat(hi_571, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_572 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1013 = cat(hi_572, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_573 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1014 = cat(hi_573, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_574 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1015 = cat(hi_574, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_575 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1016 = cat(hi_575, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_576 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1017 = cat(hi_576, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_577 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1018 = cat(hi_577, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_578 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1019 = cat(hi_578, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_579 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1020 = cat(hi_579, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_580 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1021 = cat(hi_580, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_581 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1022 = cat(hi_581, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_582 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1023 = cat(hi_582, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_583 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1024 = cat(hi_583, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_584 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1025 = cat(hi_584, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_585 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1026 = cat(hi_585, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_586 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1027 = cat(hi_586, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_587 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1028 = cat(hi_587, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_588 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1029 = cat(hi_588, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_589 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1030 = cat(hi_589, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_590 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1031 = cat(hi_590, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_591 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1032 = cat(hi_591, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_592 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1033 = cat(hi_592, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_593 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1034 = cat(hi_593, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_594 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1035 = cat(hi_594, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_595 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1036 = cat(hi_595, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_596 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1037 = cat(hi_596, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_597 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1038 = cat(hi_597, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_598 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1039 = cat(hi_598, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_599 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1040 = cat(hi_599, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_600 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1041 = cat(hi_600, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_601 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1042 = cat(hi_601, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_602 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1043 = cat(hi_602, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_603 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1044 = cat(hi_603, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_604 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1045 = cat(hi_604, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_605 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1046 = cat(hi_605, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_606 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1047 = cat(hi_606, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_607 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1048 = cat(hi_607, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_608 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1049 = cat(hi_608, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_609 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1050 = cat(hi_609, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_610 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1051 = cat(hi_610, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_611 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1052 = cat(hi_611, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_612 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1053 = cat(hi_612, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_613 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1054 = cat(hi_613, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_614 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1055 = cat(hi_614, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_615 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1056 = cat(hi_615, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_616 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1057 = cat(hi_616, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_617 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1058 = cat(hi_617, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_618 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1059 = cat(hi_618, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_619 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1060 = cat(hi_619, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_620 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1061 = cat(hi_620, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_621 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1062 = cat(hi_621, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_622 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1063 = cat(hi_622, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_623 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1064 = cat(hi_623, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_624 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1065 = cat(hi_624, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_625 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1066 = cat(hi_625, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_626 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1067 = cat(hi_626, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_627 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1068 = cat(hi_627, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_628 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1069 = cat(hi_628, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_629 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1070 = cat(hi_629, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_630 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1071 = cat(hi_630, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_631 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1072 = cat(hi_631, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_632 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1073 = cat(hi_632, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_633 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1074 = cat(hi_633, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_634 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1075 = cat(hi_634, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_635 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1076 = cat(hi_635, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_636 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1077 = cat(hi_636, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_637 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1078 = cat(hi_637, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_638 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1079 = cat(hi_638, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_639 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1080 = cat(hi_639, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_640 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1081 = cat(hi_640, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_641 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1082 = cat(hi_641, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_642 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1083 = cat(hi_642, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_643 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1084 = cat(hi_643, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_644 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1085 = cat(hi_644, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_645 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1086 = cat(hi_645, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_646 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1087 = cat(hi_646, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_647 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1088 = cat(hi_647, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_648 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1089 = cat(hi_648, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_649 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1090 = cat(hi_649, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_650 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1091 = cat(hi_650, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_651 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1092 = cat(hi_651, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_652 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1093 = cat(hi_652, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_653 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1094 = cat(hi_653, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_654 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1095 = cat(hi_654, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_655 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1096 = cat(hi_655, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_656 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1097 = cat(hi_656, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_657 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1098 = cat(hi_657, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_658 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1099 = cat(hi_658, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_659 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1100 = cat(hi_659, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_660 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1101 = cat(hi_660, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_661 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1102 = cat(hi_661, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_662 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1103 = cat(hi_662, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_663 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1104 = cat(hi_663, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_664 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1105 = cat(hi_664, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_665 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1106 = cat(hi_665, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_666 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1107 = cat(hi_666, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_667 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1108 = cat(hi_667, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_668 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1109 = cat(hi_668, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_669 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1110 = cat(hi_669, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_670 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1111 = cat(hi_670, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_671 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1112 = cat(hi_671, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_672 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1113 = cat(hi_672, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_673 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1114 = cat(hi_673, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_674 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1115 = cat(hi_674, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_675 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1116 = cat(hi_675, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_676 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1117 = cat(hi_676, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_677 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1118 = cat(hi_677, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_678 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1119 = cat(hi_678, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_679 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1120 = cat(hi_679, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_680 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1121 = cat(hi_680, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_681 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1122 = cat(hi_681, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_682 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1123 = cat(hi_682, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_683 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1124 = cat(hi_683, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_684 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1125 = cat(hi_684, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_685 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1126 = cat(hi_685, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_686 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1127 = cat(hi_686, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_687 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1128 = cat(hi_687, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_688 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1129 = cat(hi_688, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_689 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1130 = cat(hi_689, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_690 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1131 = cat(hi_690, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_691 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1132 = cat(hi_691, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_692 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1133 = cat(hi_692, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_693 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1134 = cat(hi_693, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_694 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1135 = cat(hi_694, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_695 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1136 = cat(hi_695, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_696 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1137 = cat(hi_696, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_697 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1138 = cat(hi_697, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_698 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1139 = cat(hi_698, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_699 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1140 = cat(hi_699, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_700 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1141 = cat(hi_700, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_701 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1142 = cat(hi_701, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_702 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1143 = cat(hi_702, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_703 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1144 = cat(hi_703, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_704 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1145 = cat(hi_704, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_705 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1146 = cat(hi_705, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_706 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1147 = cat(hi_706, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_707 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1148 = cat(hi_707, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_708 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1149 = cat(hi_708, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_709 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1150 = cat(hi_709, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_710 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1151 = cat(hi_710, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_711 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1152 = cat(hi_711, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_712 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1153 = cat(hi_712, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_713 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1154 = cat(hi_713, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_714 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1155 = cat(hi_714, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_715 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1156 = cat(hi_715, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_716 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1157 = cat(hi_716, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_717 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1158 = cat(hi_717, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_718 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1159 = cat(hi_718, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_719 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1160 = cat(hi_719, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_720 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1161 = cat(hi_720, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_721 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1162 = cat(hi_721, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_722 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1163 = cat(hi_722, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_723 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1164 = cat(hi_723, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_724 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1165 = cat(hi_724, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_725 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1166 = cat(hi_725, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_726 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1167 = cat(hi_726, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_727 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1168 = cat(hi_727, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_728 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1169 = cat(hi_728, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_729 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1170 = cat(hi_729, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_730 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1171 = cat(hi_730, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_731 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1172 = cat(hi_731, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_732 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1173 = cat(hi_732, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_733 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1174 = cat(hi_733, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_734 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1175 = cat(hi_734, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_735 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1176 = cat(hi_735, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_736 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1177 = cat(hi_736, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_737 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1178 = cat(hi_737, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_738 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1179 = cat(hi_738, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_739 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1180 = cat(hi_739, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_740 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1181 = cat(hi_740, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_741 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1182 = cat(hi_741, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_742 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1183 = cat(hi_742, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_743 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1184 = cat(hi_743, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_744 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1185 = cat(hi_744, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_745 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1186 = cat(hi_745, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_746 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1187 = cat(hi_746, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_747 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1188 = cat(hi_747, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_748 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1189 = cat(hi_748, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_749 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1190 = cat(hi_749, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_750 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1191 = cat(hi_750, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_751 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1192 = cat(hi_751, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_752 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1193 = cat(hi_752, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_753 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1194 = cat(hi_753, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_754 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1195 = cat(hi_754, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_755 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1196 = cat(hi_755, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_756 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1197 = cat(hi_756, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_757 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1198 = cat(hi_757, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_758 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1199 = cat(hi_758, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_759 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1200 = cat(hi_759, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_760 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1201 = cat(hi_760, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_761 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1202 = cat(hi_761, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_762 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1203 = cat(hi_762, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_763 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1204 = cat(hi_763, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_764 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1205 = cat(hi_764, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_765 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1206 = cat(hi_765, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_766 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1207 = cat(hi_766, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_767 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1208 = cat(hi_767, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_768 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1209 = cat(hi_768, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_769 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1210 = cat(hi_769, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_770 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1211 = cat(hi_770, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_771 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1212 = cat(hi_771, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_772 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1213 = cat(hi_772, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_773 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1214 = cat(hi_773, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_774 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1215 = cat(hi_774, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_775 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1216 = cat(hi_775, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_776 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1217 = cat(hi_776, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_777 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1218 = cat(hi_777, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_778 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1219 = cat(hi_778, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_779 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1220 = cat(hi_779, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_780 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1221 = cat(hi_780, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_781 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1222 = cat(hi_781, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_782 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1223 = cat(hi_782, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_783 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1224 = cat(hi_783, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_784 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1225 = cat(hi_784, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_785 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1226 = cat(hi_785, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_786 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1227 = cat(hi_786, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_787 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1228 = cat(hi_787, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_788 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1229 = cat(hi_788, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_789 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1230 = cat(hi_789, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_790 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1231 = cat(hi_790, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_791 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1232 = cat(hi_791, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_792 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1233 = cat(hi_792, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_793 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1234 = cat(hi_793, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_794 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1235 = cat(hi_794, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_795 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1236 = cat(hi_795, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_796 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1237 = cat(hi_796, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_797 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1238 = cat(hi_797, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_798 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1239 = cat(hi_798, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_799 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1240 = cat(hi_799, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_800 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1241 = cat(hi_800, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_801 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1242 = cat(hi_801, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_802 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1243 = cat(hi_802, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_803 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1244 = cat(hi_803, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_804 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1245 = cat(hi_804, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_805 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1246 = cat(hi_805, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_806 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1247 = cat(hi_806, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_807 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1248 = cat(hi_807, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_808 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1249 = cat(hi_808, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_809 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1250 = cat(hi_809, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_810 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1251 = cat(hi_810, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_811 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1252 = cat(hi_811, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_812 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1253 = cat(hi_812, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_813 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1254 = cat(hi_813, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_814 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1255 = cat(hi_814, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_815 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1256 = cat(hi_815, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_816 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1257 = cat(hi_816, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_817 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1258 = cat(hi_817, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_818 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1259 = cat(hi_818, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_819 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1260 = cat(hi_819, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_820 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1261 = cat(hi_820, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_821 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1262 = cat(hi_821, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_822 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1263 = cat(hi_822, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_823 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1264 = cat(hi_823, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_824 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1265 = cat(hi_824, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_825 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1266 = cat(hi_825, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_826 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1267 = cat(hi_826, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_827 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1268 = cat(hi_827, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_828 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1269 = cat(hi_828, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_829 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1270 = cat(hi_829, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_830 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1271 = cat(hi_830, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_831 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1272 = cat(hi_831, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_832 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1273 = cat(hi_832, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_833 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1274 = cat(hi_833, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_834 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1275 = cat(hi_834, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_835 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1276 = cat(hi_835, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_836 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1277 = cat(hi_836, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_837 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1278 = cat(hi_837, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_838 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1279 = cat(hi_838, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_839 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1280 = cat(hi_839, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_840 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1281 = cat(hi_840, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_841 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1282 = cat(hi_841, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_842 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1283 = cat(hi_842, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_843 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1284 = cat(hi_843, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_844 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1285 = cat(hi_844, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_845 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1286 = cat(hi_845, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_846 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1287 = cat(hi_846, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_847 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1288 = cat(hi_847, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_848 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1289 = cat(hi_848, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_849 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1290 = cat(hi_849, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_850 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1291 = cat(hi_850, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_851 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1292 = cat(hi_851, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_852 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1293 = cat(hi_852, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_853 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1294 = cat(hi_853, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_854 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1295 = cat(hi_854, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_855 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1296 = cat(hi_855, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_856 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1297 = cat(hi_856, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_857 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1298 = cat(hi_857, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_858 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1299 = cat(hi_858, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_859 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1300 = cat(hi_859, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_860 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1301 = cat(hi_860, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_861 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1302 = cat(hi_861, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_862 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1303 = cat(hi_862, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_863 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1304 = cat(hi_863, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_864 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1305 = cat(hi_864, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_865 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1306 = cat(hi_865, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_866 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1307 = cat(hi_866, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_867 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1308 = cat(hi_867, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_868 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1309 = cat(hi_868, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_869 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1310 = cat(hi_869, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_870 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1311 = cat(hi_870, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_871 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1312 = cat(hi_871, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_872 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1313 = cat(hi_872, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_873 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1314 = cat(hi_873, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_874 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1315 = cat(hi_874, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_875 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1316 = cat(hi_875, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_876 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1317 = cat(hi_876, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_877 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1318 = cat(hi_877, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_878 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1319 = cat(hi_878, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_879 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1320 = cat(hi_879, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_880 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1321 = cat(hi_880, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_881 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1322 = cat(hi_881, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_882 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1323 = cat(hi_882, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_883 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1324 = cat(hi_883, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_884 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1325 = cat(hi_884, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_885 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1326 = cat(hi_885, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_886 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1327 = cat(hi_886, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_887 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1328 = cat(hi_887, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_888 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1329 = cat(hi_888, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_889 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1330 = cat(hi_889, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_890 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1331 = cat(hi_890, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_891 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1332 = cat(hi_891, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_892 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1333 = cat(hi_892, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_893 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1334 = cat(hi_893, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_894 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1335 = cat(hi_894, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_895 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1336 = cat(hi_895, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_896 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1337 = cat(hi_896, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_897 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1338 = cat(hi_897, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_898 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1339 = cat(hi_898, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_899 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1340 = cat(hi_899, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_900 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1341 = cat(hi_900, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_901 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1342 = cat(hi_901, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_902 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1343 = cat(hi_902, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_903 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1344 = cat(hi_903, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_904 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1345 = cat(hi_904, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_905 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1346 = cat(hi_905, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_906 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1347 = cat(hi_906, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_907 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1348 = cat(hi_907, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_908 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1349 = cat(hi_908, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_909 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1350 = cat(hi_909, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_910 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1351 = cat(hi_910, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_911 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1352 = cat(hi_911, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_912 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1353 = cat(hi_912, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_913 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1354 = cat(hi_913, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_914 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1355 = cat(hi_914, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_915 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1356 = cat(hi_915, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_916 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1357 = cat(hi_916, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_917 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1358 = cat(hi_917, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_918 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1359 = cat(hi_918, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_919 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1360 = cat(hi_919, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_920 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1361 = cat(hi_920, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_921 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1362 = cat(hi_921, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_922 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1363 = cat(hi_922, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_923 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1364 = cat(hi_923, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_924 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1365 = cat(hi_924, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_925 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1366 = cat(hi_925, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_926 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1367 = cat(hi_926, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_927 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1368 = cat(hi_927, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_928 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1369 = cat(hi_928, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_929 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1370 = cat(hi_929, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_930 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1371 = cat(hi_930, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_931 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1372 = cat(hi_931, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_932 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1373 = cat(hi_932, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_933 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1374 = cat(hi_933, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_934 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1375 = cat(hi_934, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_935 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1376 = cat(hi_935, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_936 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1377 = cat(hi_936, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_937 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1378 = cat(hi_937, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_938 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1379 = cat(hi_938, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_939 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1380 = cat(hi_939, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_940 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1381 = cat(hi_940, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_941 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1382 = cat(hi_941, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_942 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1383 = cat(hi_942, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_943 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1384 = cat(hi_943, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_944 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1385 = cat(hi_944, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_945 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1386 = cat(hi_945, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_946 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1387 = cat(hi_946, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_947 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1388 = cat(hi_947, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_948 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1389 = cat(hi_948, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_949 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1390 = cat(hi_949, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_950 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1391 = cat(hi_950, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_951 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1392 = cat(hi_951, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_952 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1393 = cat(hi_952, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_953 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1394 = cat(hi_953, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_954 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1395 = cat(hi_954, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_955 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1396 = cat(hi_955, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_956 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1397 = cat(hi_956, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_957 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1398 = cat(hi_957, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_958 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1399 = cat(hi_958, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_959 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1400 = cat(hi_959, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_960 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1401 = cat(hi_960, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_961 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1402 = cat(hi_961, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_962 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1403 = cat(hi_962, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_963 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1404 = cat(hi_963, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_964 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1405 = cat(hi_964, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_965 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1406 = cat(hi_965, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_966 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1407 = cat(hi_966, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_967 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1408 = cat(hi_967, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_968 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1409 = cat(hi_968, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_969 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1410 = cat(hi_969, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_970 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1411 = cat(hi_970, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_971 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1412 = cat(hi_971, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_972 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1413 = cat(hi_972, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_973 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1414 = cat(hi_973, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_974 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1415 = cat(hi_974, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_975 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1416 = cat(hi_975, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_976 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1417 = cat(hi_976, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_977 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1418 = cat(hi_977, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_978 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1419 = cat(hi_978, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_979 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1420 = cat(hi_979, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_980 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1421 = cat(hi_980, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_981 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1422 = cat(hi_981, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_982 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1423 = cat(hi_982, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_983 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1424 = cat(hi_983, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_984 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1425 = cat(hi_984, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_985 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1426 = cat(hi_985, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_986 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1427 = cat(hi_986, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_987 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1428 = cat(hi_987, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_988 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1429 = cat(hi_988, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_989 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1430 = cat(hi_989, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_990 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1431 = cat(hi_990, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_991 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1432 = cat(hi_991, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_992 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1433 = cat(hi_992, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_993 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1434 = cat(hi_993, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_994 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1435 = cat(hi_994, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_995 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1436 = cat(hi_995, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_996 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1437 = cat(hi_996, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_997 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1438 = cat(hi_997, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_998 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1439 = cat(hi_998, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_999 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1440 = cat(hi_999, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1000 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1441 = cat(hi_1000, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1001 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1442 = cat(hi_1001, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1002 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1443 = cat(hi_1002, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1003 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1444 = cat(hi_1003, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1004 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1445 = cat(hi_1004, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1005 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1446 = cat(hi_1005, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1006 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1447 = cat(hi_1006, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1007 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1448 = cat(hi_1007, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1008 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1449 = cat(hi_1008, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1009 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1450 = cat(hi_1009, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1010 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1451 = cat(hi_1010, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1011 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1452 = cat(hi_1011, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1012 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1453 = cat(hi_1012, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1013 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1454 = cat(hi_1013, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1014 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1455 = cat(hi_1014, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1015 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1456 = cat(hi_1015, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1016 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1457 = cat(hi_1016, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1017 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1458 = cat(hi_1017, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1018 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1459 = cat(hi_1018, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1019 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1460 = cat(hi_1019, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1020 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1461 = cat(hi_1020, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1021 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1462 = cat(hi_1021, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1022 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1463 = cat(hi_1022, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1023 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1464 = cat(hi_1023, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node hi_1024 = cat(flags[0].reserved, flags[0].resume) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] node _T_1465 = cat(hi_1024, flags[0].go) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1701:60] wire in_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 73:18] node _in_bits_read_T_1 = eq(tlNodeIn.a.bits.opcode, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 74:36] connect in_1.bits.read, _in_bits_read_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 74:19] node _in_bits_index_T_1 = shr(tlNodeIn.a.bits.address, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 192:34] connect in_1.bits.index, _in_bits_index_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 75:19] connect in_1.bits.data, tlNodeIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 76:19] connect in_1.bits.mask, tlNodeIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 77:19] connect in_1.bits.extra.tlrr_extra.source, tlNodeIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 83:20] connect in_1.bits.extra.tlrr_extra.size, tlNodeIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 84:20] wire out_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_front_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front_1.bits, in_1.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_maskMatch_1 = not(UInt<9>(0hff)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_findex_1 = and(out_front_1.bits.index, out_maskMatch_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_bindex_1 = and(out_front_1.bits.index, out_maskMatch_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1324 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1325 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1326 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1327 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1328 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1329 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1330 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1331 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1332 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1333 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1334 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1335 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1336 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1337 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1338 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1339 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1340 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1341 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1342 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1343 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1344 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1345 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1346 = eq(out_findex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1347 = eq(out_bindex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1348 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1349 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1350 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1351 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1352 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1353 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1354 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1355 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1356 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1357 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1358 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1359 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1360 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1361 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1362 = eq(out_findex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1363 = eq(out_bindex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1364 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1365 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1366 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1367 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1368 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1369 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1370 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1371 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1372 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1373 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1374 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1375 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1376 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1377 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1378 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1379 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1380 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1381 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1382 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1383 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1384 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1385 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1386 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1387 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1388 = eq(out_findex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1389 = eq(out_bindex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1390 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1391 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1392 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1393 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1394 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1395 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1396 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1397 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1398 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1399 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1400 = eq(out_findex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1401 = eq(out_bindex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1402 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1403 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1404 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1405 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1406 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1407 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1408 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1409 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1410 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1411 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1412 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1413 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1414 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1415 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1416 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1417 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1418 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1419 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1420 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1421 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1422 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1423 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1424 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1425 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1426 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1427 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1428 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1429 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1430 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1431 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1432 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1433 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1434 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1435 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1436 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1437 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1438 = eq(out_findex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1439 = eq(out_bindex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1440 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1441 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1442 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1443 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1444 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1445 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1446 = eq(out_findex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1447 = eq(out_bindex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1448 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1449 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1450 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1451 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1452 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1453 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1454 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1455 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1456 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1457 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1458 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1459 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1460 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1461 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1462 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1463 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1464 = eq(out_findex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1465 = eq(out_bindex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1466 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1467 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1468 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1469 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1470 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1471 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1472 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1473 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1474 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1475 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1476 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1477 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1478 = eq(out_findex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1479 = eq(out_bindex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1480 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1481 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1482 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1483 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1484 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1485 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1486 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1487 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1488 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1489 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1490 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1491 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1492 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1493 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1494 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1495 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1496 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1497 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1498 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1499 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1500 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1501 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1502 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1503 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1504 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1505 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1506 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1507 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1508 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1509 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1510 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1511 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1512 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1513 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1514 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1515 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1516 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1517 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1518 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1519 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1520 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1521 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1522 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1523 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1524 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1525 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1526 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1527 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1528 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1529 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1530 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1531 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1532 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1533 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1534 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1535 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1536 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1537 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1538 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1539 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1540 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1541 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1542 = eq(out_findex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1543 = eq(out_bindex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1544 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1545 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1546 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1547 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1548 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1549 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1550 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1551 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1552 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1553 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1554 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1555 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1556 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1557 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1558 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1559 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1560 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1561 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1562 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1563 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1564 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1565 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1566 = eq(out_findex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1567 = eq(out_bindex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1568 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1569 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1570 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1571 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1572 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1573 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1574 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1575 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1576 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1577 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1578 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1579 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1580 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1581 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1582 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1583 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1584 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1585 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1586 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1587 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1588 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1589 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1590 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1591 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1592 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1593 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1594 = eq(out_findex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1595 = eq(out_bindex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1596 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1597 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1598 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1599 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1600 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1601 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1602 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1603 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1604 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1605 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1606 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1607 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1608 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1609 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1610 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1611 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1612 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1613 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1614 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1615 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1616 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1617 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1618 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1619 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1620 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1621 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1622 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1623 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1624 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1625 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1626 = eq(out_findex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1627 = eq(out_bindex_1, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rivalid_1 : UInt<1>[1187] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wivalid_1 : UInt<1>[1187] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_roready_1 : UInt<1>[1187] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_woready_1 : UInt<1>[1187] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_8 = bits(out_front_1.bits.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_9 = bits(out_front_1.bits.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_10 = bits(out_front_1.bits.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_11 = bits(out_front_1.bits.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_12 = bits(out_front_1.bits.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_13 = bits(out_front_1.bits.mask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_14 = bits(out_front_1.bits.mask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_15 = bits(out_front_1.bits.mask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_16 = mux(_out_frontMask_T_8, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_17 = mux(_out_frontMask_T_9, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_18 = mux(_out_frontMask_T_10, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_19 = mux(_out_frontMask_T_11, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_20 = mux(_out_frontMask_T_12, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_21 = mux(_out_frontMask_T_13, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_22 = mux(_out_frontMask_T_14, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_23 = mux(_out_frontMask_T_15, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo_lo = cat(_out_frontMask_T_17, _out_frontMask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo_hi = cat(_out_frontMask_T_19, _out_frontMask_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo_1 = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi_lo = cat(_out_frontMask_T_21, _out_frontMask_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi_hi = cat(_out_frontMask_T_23, _out_frontMask_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi_1 = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_1 = cat(out_frontMask_hi_1, out_frontMask_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_8 = bits(out_front_1.bits.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_9 = bits(out_front_1.bits.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_10 = bits(out_front_1.bits.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_11 = bits(out_front_1.bits.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_12 = bits(out_front_1.bits.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_13 = bits(out_front_1.bits.mask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_14 = bits(out_front_1.bits.mask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_15 = bits(out_front_1.bits.mask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_16 = mux(_out_backMask_T_8, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_17 = mux(_out_backMask_T_9, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_18 = mux(_out_backMask_T_10, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_19 = mux(_out_backMask_T_11, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_20 = mux(_out_backMask_T_12, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_21 = mux(_out_backMask_T_13, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_22 = mux(_out_backMask_T_14, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_23 = mux(_out_backMask_T_15, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo_lo = cat(_out_backMask_T_17, _out_backMask_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo_hi = cat(_out_backMask_T_19, _out_backMask_T_18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo_1 = cat(out_backMask_lo_hi, out_backMask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi_lo = cat(_out_backMask_T_21, _out_backMask_T_20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi_hi = cat(_out_backMask_T_23, _out_backMask_T_22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi_1 = cat(out_backMask_hi_hi, out_backMask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_1 = cat(out_backMask_hi_1, out_backMask_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_122 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_122 = orr(_out_rimask_T_122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_122 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_122 = andr(_out_wimask_T_122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_122 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_122 = orr(_out_romask_T_122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_122 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_122 = andr(_out_womask_T_122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_122 = and(out_rivalid_1[0], out_rimask_122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_122 = and(out_roready_1[0], out_romask_122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_122 = and(out_wivalid_1[0], out_wimask_122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_122 = and(out_woready_1[0], out_womask_122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1628 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1629 = and(out_f_rivalid_122, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1630 = and(UInt<1>(0h1), out_f_roready_122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1631 = eq(out_rimask_122, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1632 = eq(out_wimask_122, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1633 = eq(out_romask_122, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1634 = eq(out_womask_122, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1635 = or(_T_522, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1636 = bits(_out_T_1635, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_123 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_123 = orr(_out_rimask_T_123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_123 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_123 = andr(_out_wimask_T_123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_123 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_123 = orr(_out_romask_T_123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_123 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_123 = andr(_out_womask_T_123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_123 = and(out_rivalid_1[1], out_rimask_123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_123 = and(out_roready_1[1], out_romask_123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_123 = and(out_wivalid_1[1], out_wimask_123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_123 = and(out_woready_1[1], out_womask_123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1637 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1638 = and(out_f_rivalid_123, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1639 = and(UInt<1>(0h1), out_f_roready_123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1640 = eq(out_rimask_123, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1641 = eq(out_wimask_123, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1642 = eq(out_romask_123, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1643 = eq(out_womask_123, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_94 = or(_out_T_1636, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_94 = cat(_T_523, _out_prepend_T_94) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1644 = or(out_prepend_94, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1645 = bits(_out_T_1644, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_124 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_124 = orr(_out_rimask_T_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_124 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_124 = andr(_out_wimask_T_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_124 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_124 = orr(_out_romask_T_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_124 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_124 = andr(_out_womask_T_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_124 = and(out_rivalid_1[2], out_rimask_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_124 = and(out_roready_1[2], out_romask_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_124 = and(out_wivalid_1[2], out_wimask_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_124 = and(out_woready_1[2], out_womask_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1646 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1647 = and(out_f_rivalid_124, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1648 = and(UInt<1>(0h1), out_f_roready_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1649 = eq(out_rimask_124, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1650 = eq(out_wimask_124, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1651 = eq(out_romask_124, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1652 = eq(out_womask_124, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_95 = or(_out_T_1645, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_95 = cat(_T_524, _out_prepend_T_95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1653 = or(out_prepend_95, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1654 = bits(_out_T_1653, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_125 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_125 = orr(_out_rimask_T_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_125 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_125 = andr(_out_wimask_T_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_125 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_125 = orr(_out_romask_T_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_125 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_125 = andr(_out_womask_T_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_125 = and(out_rivalid_1[3], out_rimask_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_125 = and(out_roready_1[3], out_romask_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_125 = and(out_wivalid_1[3], out_wimask_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_125 = and(out_woready_1[3], out_womask_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1655 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1656 = and(out_f_rivalid_125, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1657 = and(UInt<1>(0h1), out_f_roready_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1658 = eq(out_rimask_125, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1659 = eq(out_wimask_125, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1660 = eq(out_romask_125, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1661 = eq(out_womask_125, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_96 = or(_out_T_1654, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_96 = cat(_T_525, _out_prepend_T_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1662 = or(out_prepend_96, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1663 = bits(_out_T_1662, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_126 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_126 = orr(_out_rimask_T_126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_126 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_126 = andr(_out_wimask_T_126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_126 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_126 = orr(_out_romask_T_126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_126 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_126 = andr(_out_womask_T_126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_126 = and(out_rivalid_1[4], out_rimask_126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_126 = and(out_roready_1[4], out_romask_126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_126 = and(out_wivalid_1[4], out_wimask_126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_126 = and(out_woready_1[4], out_womask_126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1664 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1665 = and(out_f_rivalid_126, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1666 = and(UInt<1>(0h1), out_f_roready_126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1667 = eq(out_rimask_126, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1668 = eq(out_wimask_126, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1669 = eq(out_romask_126, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1670 = eq(out_womask_126, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_97 = or(_out_T_1663, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_97 = cat(_T_526, _out_prepend_T_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1671 = or(out_prepend_97, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1672 = bits(_out_T_1671, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_127 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_127 = orr(_out_rimask_T_127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_127 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_127 = andr(_out_wimask_T_127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_127 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_127 = orr(_out_romask_T_127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_127 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_127 = andr(_out_womask_T_127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_127 = and(out_rivalid_1[5], out_rimask_127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_127 = and(out_roready_1[5], out_romask_127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_127 = and(out_wivalid_1[5], out_wimask_127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_127 = and(out_woready_1[5], out_womask_127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1673 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1674 = and(out_f_rivalid_127, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1675 = and(UInt<1>(0h1), out_f_roready_127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1676 = eq(out_rimask_127, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1677 = eq(out_wimask_127, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1678 = eq(out_romask_127, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1679 = eq(out_womask_127, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_98 = or(_out_T_1672, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_98 = cat(_T_527, _out_prepend_T_98) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1680 = or(out_prepend_98, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1681 = bits(_out_T_1680, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_128 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_128 = orr(_out_rimask_T_128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_128 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_128 = andr(_out_wimask_T_128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_128 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_128 = orr(_out_romask_T_128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_128 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_128 = andr(_out_womask_T_128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_128 = and(out_rivalid_1[6], out_rimask_128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_128 = and(out_roready_1[6], out_romask_128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_128 = and(out_wivalid_1[6], out_wimask_128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_128 = and(out_woready_1[6], out_womask_128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1682 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1683 = and(out_f_rivalid_128, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1684 = and(UInt<1>(0h1), out_f_roready_128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1685 = eq(out_rimask_128, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1686 = eq(out_wimask_128, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1687 = eq(out_romask_128, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1688 = eq(out_womask_128, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_99 = or(_out_T_1681, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_99 = cat(_T_528, _out_prepend_T_99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1689 = or(out_prepend_99, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1690 = bits(_out_T_1689, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_129 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_129 = orr(_out_rimask_T_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_129 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_129 = andr(_out_wimask_T_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_129 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_129 = orr(_out_romask_T_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_129 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_129 = andr(_out_womask_T_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_129 = and(out_rivalid_1[7], out_rimask_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_129 = and(out_roready_1[7], out_romask_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_129 = and(out_wivalid_1[7], out_wimask_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_129 = and(out_woready_1[7], out_womask_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1691 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1692 = and(out_f_rivalid_129, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1693 = and(UInt<1>(0h1), out_f_roready_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1694 = eq(out_rimask_129, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1695 = eq(out_wimask_129, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1696 = eq(out_romask_129, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1697 = eq(out_womask_129, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_100 = or(_out_T_1690, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_100 = cat(_T_529, _out_prepend_T_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1698 = or(out_prepend_100, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1699 = bits(_out_T_1698, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_130 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_130 = orr(_out_rimask_T_130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_130 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_130 = andr(_out_wimask_T_130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_130 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_130 = orr(_out_romask_T_130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_130 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_130 = andr(_out_womask_T_130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_130 = and(out_rivalid_1[8], out_rimask_130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_130 = and(out_roready_1[8], out_romask_130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_130 = and(out_wivalid_1[8], out_wimask_130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_130 = and(out_woready_1[8], out_womask_130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1700 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1701 = and(out_f_rivalid_130, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1702 = and(UInt<1>(0h1), out_f_roready_130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1703 = eq(out_rimask_130, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1704 = eq(out_wimask_130, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1705 = eq(out_romask_130, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1706 = eq(out_womask_130, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1707 = or(_T_1410, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1708 = bits(_out_T_1707, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_131 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_131 = orr(_out_rimask_T_131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_131 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_131 = andr(_out_wimask_T_131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_131 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_131 = orr(_out_romask_T_131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_131 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_131 = andr(_out_womask_T_131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_131 = and(out_rivalid_1[9], out_rimask_131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_131 = and(out_roready_1[9], out_romask_131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_131 = and(out_wivalid_1[9], out_wimask_131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_131 = and(out_woready_1[9], out_womask_131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1709 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1710 = and(out_f_rivalid_131, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1711 = and(UInt<1>(0h1), out_f_roready_131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1712 = eq(out_rimask_131, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1713 = eq(out_wimask_131, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1714 = eq(out_romask_131, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1715 = eq(out_womask_131, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_101 = or(_out_T_1708, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_101 = cat(_T_1411, _out_prepend_T_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1716 = or(out_prepend_101, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1717 = bits(_out_T_1716, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_132 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_132 = orr(_out_rimask_T_132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_132 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_132 = andr(_out_wimask_T_132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_132 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_132 = orr(_out_romask_T_132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_132 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_132 = andr(_out_womask_T_132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_132 = and(out_rivalid_1[10], out_rimask_132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_132 = and(out_roready_1[10], out_romask_132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_132 = and(out_wivalid_1[10], out_wimask_132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_132 = and(out_woready_1[10], out_womask_132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1718 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1719 = and(out_f_rivalid_132, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1720 = and(UInt<1>(0h1), out_f_roready_132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1721 = eq(out_rimask_132, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1722 = eq(out_wimask_132, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1723 = eq(out_romask_132, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1724 = eq(out_womask_132, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_102 = or(_out_T_1717, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_102 = cat(_T_1412, _out_prepend_T_102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1725 = or(out_prepend_102, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1726 = bits(_out_T_1725, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_133 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_133 = orr(_out_rimask_T_133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_133 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_133 = andr(_out_wimask_T_133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_133 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_133 = orr(_out_romask_T_133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_133 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_133 = andr(_out_womask_T_133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_133 = and(out_rivalid_1[11], out_rimask_133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_133 = and(out_roready_1[11], out_romask_133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_133 = and(out_wivalid_1[11], out_wimask_133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_133 = and(out_woready_1[11], out_womask_133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1727 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1728 = and(out_f_rivalid_133, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1729 = and(UInt<1>(0h1), out_f_roready_133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1730 = eq(out_rimask_133, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1731 = eq(out_wimask_133, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1732 = eq(out_romask_133, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1733 = eq(out_womask_133, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_103 = or(_out_T_1726, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_103 = cat(_T_1413, _out_prepend_T_103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1734 = or(out_prepend_103, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1735 = bits(_out_T_1734, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_134 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_134 = orr(_out_rimask_T_134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_134 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_134 = andr(_out_wimask_T_134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_134 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_134 = orr(_out_romask_T_134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_134 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_134 = andr(_out_womask_T_134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_134 = and(out_rivalid_1[12], out_rimask_134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_134 = and(out_roready_1[12], out_romask_134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_134 = and(out_wivalid_1[12], out_wimask_134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_134 = and(out_woready_1[12], out_womask_134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1736 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1737 = and(out_f_rivalid_134, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1738 = and(UInt<1>(0h1), out_f_roready_134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1739 = eq(out_rimask_134, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1740 = eq(out_wimask_134, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1741 = eq(out_romask_134, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1742 = eq(out_womask_134, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_104 = or(_out_T_1735, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_104 = cat(_T_1414, _out_prepend_T_104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1743 = or(out_prepend_104, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1744 = bits(_out_T_1743, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_135 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_135 = orr(_out_rimask_T_135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_135 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_135 = andr(_out_wimask_T_135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_135 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_135 = orr(_out_romask_T_135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_135 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_135 = andr(_out_womask_T_135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_135 = and(out_rivalid_1[13], out_rimask_135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_135 = and(out_roready_1[13], out_romask_135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_135 = and(out_wivalid_1[13], out_wimask_135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_135 = and(out_woready_1[13], out_womask_135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1745 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1746 = and(out_f_rivalid_135, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1747 = and(UInt<1>(0h1), out_f_roready_135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1748 = eq(out_rimask_135, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1749 = eq(out_wimask_135, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1750 = eq(out_romask_135, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1751 = eq(out_womask_135, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_105 = or(_out_T_1744, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_105 = cat(_T_1415, _out_prepend_T_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1752 = or(out_prepend_105, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1753 = bits(_out_T_1752, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_136 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_136 = orr(_out_rimask_T_136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_136 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_136 = andr(_out_wimask_T_136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_136 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_136 = orr(_out_romask_T_136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_136 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_136 = andr(_out_womask_T_136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_136 = and(out_rivalid_1[14], out_rimask_136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_136 = and(out_roready_1[14], out_romask_136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_136 = and(out_wivalid_1[14], out_wimask_136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_136 = and(out_woready_1[14], out_womask_136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1754 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1755 = and(out_f_rivalid_136, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1756 = and(UInt<1>(0h1), out_f_roready_136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1757 = eq(out_rimask_136, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1758 = eq(out_wimask_136, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1759 = eq(out_romask_136, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1760 = eq(out_womask_136, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_106 = or(_out_T_1753, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_106 = cat(_T_1416, _out_prepend_T_106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1761 = or(out_prepend_106, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1762 = bits(_out_T_1761, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_137 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_137 = orr(_out_rimask_T_137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_137 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_137 = andr(_out_wimask_T_137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_137 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_137 = orr(_out_romask_T_137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_137 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_137 = andr(_out_womask_T_137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_137 = and(out_rivalid_1[15], out_rimask_137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_137 = and(out_roready_1[15], out_romask_137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_137 = and(out_wivalid_1[15], out_wimask_137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_137 = and(out_woready_1[15], out_womask_137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1763 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1764 = and(out_f_rivalid_137, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1765 = and(UInt<1>(0h1), out_f_roready_137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1766 = eq(out_rimask_137, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1767 = eq(out_wimask_137, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1768 = eq(out_romask_137, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1769 = eq(out_womask_137, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_107 = or(_out_T_1762, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_107 = cat(_T_1417, _out_prepend_T_107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1770 = or(out_prepend_107, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1771 = bits(_out_T_1770, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_138 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_138 = orr(_out_rimask_T_138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_138 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_138 = andr(_out_wimask_T_138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_138 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_138 = orr(_out_romask_T_138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_138 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_138 = andr(_out_womask_T_138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_138 = and(out_rivalid_1[16], out_rimask_138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_138 = and(out_roready_1[16], out_romask_138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_138 = and(out_wivalid_1[16], out_wimask_138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_138 = and(out_woready_1[16], out_womask_138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1772 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1773 = and(out_f_rivalid_138, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1774 = and(UInt<1>(0h1), out_f_roready_138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1775 = eq(out_rimask_138, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1776 = eq(out_wimask_138, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1777 = eq(out_romask_138, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1778 = eq(out_womask_138, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1779 = or(_T_1290, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1780 = bits(_out_T_1779, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_139 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_139 = orr(_out_rimask_T_139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_139 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_139 = andr(_out_wimask_T_139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_139 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_139 = orr(_out_romask_T_139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_139 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_139 = andr(_out_womask_T_139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_139 = and(out_rivalid_1[17], out_rimask_139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_139 = and(out_roready_1[17], out_romask_139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_139 = and(out_wivalid_1[17], out_wimask_139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_139 = and(out_woready_1[17], out_womask_139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1781 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1782 = and(out_f_rivalid_139, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1783 = and(UInt<1>(0h1), out_f_roready_139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1784 = eq(out_rimask_139, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1785 = eq(out_wimask_139, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1786 = eq(out_romask_139, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1787 = eq(out_womask_139, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_108 = or(_out_T_1780, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_108 = cat(_T_1291, _out_prepend_T_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1788 = or(out_prepend_108, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1789 = bits(_out_T_1788, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_140 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_140 = orr(_out_rimask_T_140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_140 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_140 = andr(_out_wimask_T_140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_140 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_140 = orr(_out_romask_T_140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_140 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_140 = andr(_out_womask_T_140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_140 = and(out_rivalid_1[18], out_rimask_140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_140 = and(out_roready_1[18], out_romask_140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_140 = and(out_wivalid_1[18], out_wimask_140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_140 = and(out_woready_1[18], out_womask_140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1790 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1791 = and(out_f_rivalid_140, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1792 = and(UInt<1>(0h1), out_f_roready_140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1793 = eq(out_rimask_140, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1794 = eq(out_wimask_140, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1795 = eq(out_romask_140, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1796 = eq(out_womask_140, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_109 = or(_out_T_1789, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_109 = cat(_T_1292, _out_prepend_T_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1797 = or(out_prepend_109, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1798 = bits(_out_T_1797, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_141 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_141 = orr(_out_rimask_T_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_141 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_141 = andr(_out_wimask_T_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_141 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_141 = orr(_out_romask_T_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_141 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_141 = andr(_out_womask_T_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_141 = and(out_rivalid_1[19], out_rimask_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_141 = and(out_roready_1[19], out_romask_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_141 = and(out_wivalid_1[19], out_wimask_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_141 = and(out_woready_1[19], out_womask_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1799 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1800 = and(out_f_rivalid_141, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1801 = and(UInt<1>(0h1), out_f_roready_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1802 = eq(out_rimask_141, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1803 = eq(out_wimask_141, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1804 = eq(out_romask_141, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1805 = eq(out_womask_141, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_110 = or(_out_T_1798, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_110 = cat(_T_1293, _out_prepend_T_110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1806 = or(out_prepend_110, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1807 = bits(_out_T_1806, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_142 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_142 = orr(_out_rimask_T_142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_142 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_142 = andr(_out_wimask_T_142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_142 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_142 = orr(_out_romask_T_142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_142 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_142 = andr(_out_womask_T_142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_142 = and(out_rivalid_1[20], out_rimask_142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_142 = and(out_roready_1[20], out_romask_142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_142 = and(out_wivalid_1[20], out_wimask_142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_142 = and(out_woready_1[20], out_womask_142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1808 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1809 = and(out_f_rivalid_142, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1810 = and(UInt<1>(0h1), out_f_roready_142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1811 = eq(out_rimask_142, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1812 = eq(out_wimask_142, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1813 = eq(out_romask_142, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1814 = eq(out_womask_142, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_111 = or(_out_T_1807, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_111 = cat(_T_1294, _out_prepend_T_111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1815 = or(out_prepend_111, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1816 = bits(_out_T_1815, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_143 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_143 = orr(_out_rimask_T_143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_143 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_143 = andr(_out_wimask_T_143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_143 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_143 = orr(_out_romask_T_143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_143 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_143 = andr(_out_womask_T_143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_143 = and(out_rivalid_1[21], out_rimask_143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_143 = and(out_roready_1[21], out_romask_143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_143 = and(out_wivalid_1[21], out_wimask_143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_143 = and(out_woready_1[21], out_womask_143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1817 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1818 = and(out_f_rivalid_143, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1819 = and(UInt<1>(0h1), out_f_roready_143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1820 = eq(out_rimask_143, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1821 = eq(out_wimask_143, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1822 = eq(out_romask_143, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1823 = eq(out_womask_143, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_112 = or(_out_T_1816, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_112 = cat(_T_1295, _out_prepend_T_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1824 = or(out_prepend_112, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1825 = bits(_out_T_1824, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_144 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_144 = orr(_out_rimask_T_144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_144 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_144 = andr(_out_wimask_T_144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_144 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_144 = orr(_out_romask_T_144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_144 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_144 = andr(_out_womask_T_144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_144 = and(out_rivalid_1[22], out_rimask_144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_144 = and(out_roready_1[22], out_romask_144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_144 = and(out_wivalid_1[22], out_wimask_144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_144 = and(out_woready_1[22], out_womask_144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1826 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1827 = and(out_f_rivalid_144, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1828 = and(UInt<1>(0h1), out_f_roready_144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1829 = eq(out_rimask_144, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1830 = eq(out_wimask_144, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1831 = eq(out_romask_144, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1832 = eq(out_womask_144, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_113 = or(_out_T_1825, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_113 = cat(_T_1296, _out_prepend_T_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1833 = or(out_prepend_113, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1834 = bits(_out_T_1833, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_145 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_145 = orr(_out_rimask_T_145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_145 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_145 = andr(_out_wimask_T_145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_145 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_145 = orr(_out_romask_T_145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_145 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_145 = andr(_out_womask_T_145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_145 = and(out_rivalid_1[23], out_rimask_145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_145 = and(out_roready_1[23], out_romask_145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_145 = and(out_wivalid_1[23], out_wimask_145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_145 = and(out_woready_1[23], out_womask_145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1835 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1836 = and(out_f_rivalid_145, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1837 = and(UInt<1>(0h1), out_f_roready_145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1838 = eq(out_rimask_145, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1839 = eq(out_wimask_145, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1840 = eq(out_romask_145, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1841 = eq(out_womask_145, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_114 = or(_out_T_1834, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_114 = cat(_T_1297, _out_prepend_T_114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1842 = or(out_prepend_114, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1843 = bits(_out_T_1842, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_146 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_146 = orr(_out_rimask_T_146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_146 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_146 = andr(_out_wimask_T_146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_146 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_146 = orr(_out_romask_T_146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_146 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_146 = andr(_out_womask_T_146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_146 = and(out_rivalid_1[24], out_rimask_146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_146 = and(out_roready_1[24], out_romask_146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_146 = and(out_wivalid_1[24], out_wimask_146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_146 = and(out_woready_1[24], out_womask_146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1844 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1845 = and(out_f_rivalid_146, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1846 = and(UInt<1>(0h1), out_f_roready_146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1847 = eq(out_rimask_146, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1848 = eq(out_wimask_146, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1849 = eq(out_romask_146, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1850 = eq(out_womask_146, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1851 = or(_T_778, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1852 = bits(_out_T_1851, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_147 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_147 = orr(_out_rimask_T_147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_147 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_147 = andr(_out_wimask_T_147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_147 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_147 = orr(_out_romask_T_147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_147 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_147 = andr(_out_womask_T_147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_147 = and(out_rivalid_1[25], out_rimask_147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_147 = and(out_roready_1[25], out_romask_147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_147 = and(out_wivalid_1[25], out_wimask_147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_147 = and(out_woready_1[25], out_womask_147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1853 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1854 = and(out_f_rivalid_147, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1855 = and(UInt<1>(0h1), out_f_roready_147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1856 = eq(out_rimask_147, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1857 = eq(out_wimask_147, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1858 = eq(out_romask_147, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1859 = eq(out_womask_147, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_115 = or(_out_T_1852, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_115 = cat(_T_779, _out_prepend_T_115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1860 = or(out_prepend_115, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1861 = bits(_out_T_1860, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_148 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_148 = orr(_out_rimask_T_148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_148 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_148 = andr(_out_wimask_T_148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_148 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_148 = orr(_out_romask_T_148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_148 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_148 = andr(_out_womask_T_148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_148 = and(out_rivalid_1[26], out_rimask_148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_148 = and(out_roready_1[26], out_romask_148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_148 = and(out_wivalid_1[26], out_wimask_148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_148 = and(out_woready_1[26], out_womask_148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1862 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1863 = and(out_f_rivalid_148, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1864 = and(UInt<1>(0h1), out_f_roready_148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1865 = eq(out_rimask_148, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1866 = eq(out_wimask_148, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1867 = eq(out_romask_148, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1868 = eq(out_womask_148, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_116 = or(_out_T_1861, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_116 = cat(_T_780, _out_prepend_T_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1869 = or(out_prepend_116, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1870 = bits(_out_T_1869, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_149 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_149 = orr(_out_rimask_T_149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_149 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_149 = andr(_out_wimask_T_149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_149 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_149 = orr(_out_romask_T_149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_149 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_149 = andr(_out_womask_T_149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_149 = and(out_rivalid_1[27], out_rimask_149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_149 = and(out_roready_1[27], out_romask_149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_149 = and(out_wivalid_1[27], out_wimask_149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_149 = and(out_woready_1[27], out_womask_149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1871 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1872 = and(out_f_rivalid_149, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1873 = and(UInt<1>(0h1), out_f_roready_149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1874 = eq(out_rimask_149, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1875 = eq(out_wimask_149, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1876 = eq(out_romask_149, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1877 = eq(out_womask_149, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_117 = or(_out_T_1870, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_117 = cat(_T_781, _out_prepend_T_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1878 = or(out_prepend_117, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1879 = bits(_out_T_1878, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_150 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_150 = orr(_out_rimask_T_150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_150 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_150 = andr(_out_wimask_T_150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_150 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_150 = orr(_out_romask_T_150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_150 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_150 = andr(_out_womask_T_150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_150 = and(out_rivalid_1[28], out_rimask_150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_150 = and(out_roready_1[28], out_romask_150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_150 = and(out_wivalid_1[28], out_wimask_150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_150 = and(out_woready_1[28], out_womask_150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1880 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1881 = and(out_f_rivalid_150, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1882 = and(UInt<1>(0h1), out_f_roready_150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1883 = eq(out_rimask_150, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1884 = eq(out_wimask_150, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1885 = eq(out_romask_150, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1886 = eq(out_womask_150, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_118 = or(_out_T_1879, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_118 = cat(_T_782, _out_prepend_T_118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1887 = or(out_prepend_118, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1888 = bits(_out_T_1887, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_151 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_151 = orr(_out_rimask_T_151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_151 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_151 = andr(_out_wimask_T_151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_151 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_151 = orr(_out_romask_T_151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_151 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_151 = andr(_out_womask_T_151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_151 = and(out_rivalid_1[29], out_rimask_151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_151 = and(out_roready_1[29], out_romask_151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_151 = and(out_wivalid_1[29], out_wimask_151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_151 = and(out_woready_1[29], out_womask_151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1889 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1890 = and(out_f_rivalid_151, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1891 = and(UInt<1>(0h1), out_f_roready_151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1892 = eq(out_rimask_151, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1893 = eq(out_wimask_151, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1894 = eq(out_romask_151, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1895 = eq(out_womask_151, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_119 = or(_out_T_1888, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_119 = cat(_T_783, _out_prepend_T_119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1896 = or(out_prepend_119, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1897 = bits(_out_T_1896, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_152 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_152 = orr(_out_rimask_T_152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_152 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_152 = andr(_out_wimask_T_152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_152 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_152 = orr(_out_romask_T_152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_152 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_152 = andr(_out_womask_T_152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_152 = and(out_rivalid_1[30], out_rimask_152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_152 = and(out_roready_1[30], out_romask_152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_152 = and(out_wivalid_1[30], out_wimask_152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_152 = and(out_woready_1[30], out_womask_152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1898 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1899 = and(out_f_rivalid_152, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1900 = and(UInt<1>(0h1), out_f_roready_152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1901 = eq(out_rimask_152, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1902 = eq(out_wimask_152, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1903 = eq(out_romask_152, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1904 = eq(out_womask_152, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_120 = or(_out_T_1897, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_120 = cat(_T_784, _out_prepend_T_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1905 = or(out_prepend_120, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1906 = bits(_out_T_1905, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_153 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_153 = orr(_out_rimask_T_153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_153 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_153 = andr(_out_wimask_T_153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_153 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_153 = orr(_out_romask_T_153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_153 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_153 = andr(_out_womask_T_153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_153 = and(out_rivalid_1[31], out_rimask_153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_153 = and(out_roready_1[31], out_romask_153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_153 = and(out_wivalid_1[31], out_wimask_153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_153 = and(out_woready_1[31], out_womask_153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1907 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1908 = and(out_f_rivalid_153, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1909 = and(UInt<1>(0h1), out_f_roready_153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1910 = eq(out_rimask_153, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1911 = eq(out_wimask_153, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1912 = eq(out_romask_153, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1913 = eq(out_womask_153, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_121 = or(_out_T_1906, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_121 = cat(_T_785, _out_prepend_T_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1914 = or(out_prepend_121, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1915 = bits(_out_T_1914, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_154 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_154 = orr(_out_rimask_T_154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_154 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_154 = andr(_out_wimask_T_154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_154 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_154 = orr(_out_romask_T_154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_154 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_154 = andr(_out_womask_T_154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_154 = and(out_rivalid_1[32], out_rimask_154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_154 = and(out_roready_1[32], out_romask_154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_154 = and(out_wivalid_1[32], out_wimask_154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_154 = and(out_woready_1[32], out_womask_154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1916 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1917 = and(out_f_rivalid_154, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1918 = and(UInt<1>(0h1), out_f_roready_154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1919 = eq(out_rimask_154, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1920 = eq(out_wimask_154, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1921 = eq(out_romask_154, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1922 = eq(out_womask_154, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1923 = or(_T_1154, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1924 = bits(_out_T_1923, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_155 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_155 = orr(_out_rimask_T_155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_155 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_155 = andr(_out_wimask_T_155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_155 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_155 = orr(_out_romask_T_155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_155 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_155 = andr(_out_womask_T_155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_155 = and(out_rivalid_1[33], out_rimask_155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_155 = and(out_roready_1[33], out_romask_155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_155 = and(out_wivalid_1[33], out_wimask_155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_155 = and(out_woready_1[33], out_womask_155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1925 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1926 = and(out_f_rivalid_155, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1927 = and(UInt<1>(0h1), out_f_roready_155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1928 = eq(out_rimask_155, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1929 = eq(out_wimask_155, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1930 = eq(out_romask_155, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1931 = eq(out_womask_155, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_122 = or(_out_T_1924, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_122 = cat(_T_1155, _out_prepend_T_122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1932 = or(out_prepend_122, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1933 = bits(_out_T_1932, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_156 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_156 = orr(_out_rimask_T_156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_156 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_156 = andr(_out_wimask_T_156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_156 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_156 = orr(_out_romask_T_156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_156 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_156 = andr(_out_womask_T_156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_156 = and(out_rivalid_1[34], out_rimask_156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_156 = and(out_roready_1[34], out_romask_156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_156 = and(out_wivalid_1[34], out_wimask_156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_156 = and(out_woready_1[34], out_womask_156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1934 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1935 = and(out_f_rivalid_156, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1936 = and(UInt<1>(0h1), out_f_roready_156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1937 = eq(out_rimask_156, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1938 = eq(out_wimask_156, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1939 = eq(out_romask_156, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1940 = eq(out_womask_156, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_123 = or(_out_T_1933, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_123 = cat(_T_1156, _out_prepend_T_123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1941 = or(out_prepend_123, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1942 = bits(_out_T_1941, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_157 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_157 = orr(_out_rimask_T_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_157 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_157 = andr(_out_wimask_T_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_157 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_157 = orr(_out_romask_T_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_157 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_157 = andr(_out_womask_T_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_157 = and(out_rivalid_1[35], out_rimask_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_157 = and(out_roready_1[35], out_romask_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_157 = and(out_wivalid_1[35], out_wimask_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_157 = and(out_woready_1[35], out_womask_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1943 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1944 = and(out_f_rivalid_157, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1945 = and(UInt<1>(0h1), out_f_roready_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1946 = eq(out_rimask_157, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1947 = eq(out_wimask_157, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1948 = eq(out_romask_157, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1949 = eq(out_womask_157, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_124 = or(_out_T_1942, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_124 = cat(_T_1157, _out_prepend_T_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1950 = or(out_prepend_124, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1951 = bits(_out_T_1950, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_158 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_158 = orr(_out_rimask_T_158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_158 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_158 = andr(_out_wimask_T_158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_158 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_158 = orr(_out_romask_T_158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_158 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_158 = andr(_out_womask_T_158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_158 = and(out_rivalid_1[36], out_rimask_158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_158 = and(out_roready_1[36], out_romask_158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_158 = and(out_wivalid_1[36], out_wimask_158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_158 = and(out_woready_1[36], out_womask_158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1952 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1953 = and(out_f_rivalid_158, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1954 = and(UInt<1>(0h1), out_f_roready_158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1955 = eq(out_rimask_158, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1956 = eq(out_wimask_158, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1957 = eq(out_romask_158, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1958 = eq(out_womask_158, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_125 = or(_out_T_1951, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_125 = cat(_T_1158, _out_prepend_T_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1959 = or(out_prepend_125, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1960 = bits(_out_T_1959, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_159 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_159 = orr(_out_rimask_T_159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_159 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_159 = andr(_out_wimask_T_159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_159 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_159 = orr(_out_romask_T_159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_159 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_159 = andr(_out_womask_T_159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_159 = and(out_rivalid_1[37], out_rimask_159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_159 = and(out_roready_1[37], out_romask_159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_159 = and(out_wivalid_1[37], out_wimask_159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_159 = and(out_woready_1[37], out_womask_159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1961 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1962 = and(out_f_rivalid_159, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1963 = and(UInt<1>(0h1), out_f_roready_159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1964 = eq(out_rimask_159, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1965 = eq(out_wimask_159, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1966 = eq(out_romask_159, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1967 = eq(out_womask_159, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_126 = or(_out_T_1960, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_126 = cat(_T_1159, _out_prepend_T_126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1968 = or(out_prepend_126, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1969 = bits(_out_T_1968, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_160 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_160 = orr(_out_rimask_T_160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_160 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_160 = andr(_out_wimask_T_160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_160 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_160 = orr(_out_romask_T_160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_160 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_160 = andr(_out_womask_T_160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_160 = and(out_rivalid_1[38], out_rimask_160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_160 = and(out_roready_1[38], out_romask_160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_160 = and(out_wivalid_1[38], out_wimask_160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_160 = and(out_woready_1[38], out_womask_160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1970 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1971 = and(out_f_rivalid_160, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1972 = and(UInt<1>(0h1), out_f_roready_160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1973 = eq(out_rimask_160, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1974 = eq(out_wimask_160, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1975 = eq(out_romask_160, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1976 = eq(out_womask_160, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_127 = or(_out_T_1969, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_127 = cat(_T_1160, _out_prepend_T_127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1977 = or(out_prepend_127, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1978 = bits(_out_T_1977, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_161 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_161 = orr(_out_rimask_T_161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_161 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_161 = andr(_out_wimask_T_161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_161 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_161 = orr(_out_romask_T_161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_161 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_161 = andr(_out_womask_T_161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_161 = and(out_rivalid_1[39], out_rimask_161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_161 = and(out_roready_1[39], out_romask_161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_161 = and(out_wivalid_1[39], out_wimask_161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_161 = and(out_woready_1[39], out_womask_161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1979 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1980 = and(out_f_rivalid_161, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1981 = and(UInt<1>(0h1), out_f_roready_161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1982 = eq(out_rimask_161, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1983 = eq(out_wimask_161, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1984 = eq(out_romask_161, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1985 = eq(out_womask_161, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_128 = or(_out_T_1978, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_128 = cat(_T_1161, _out_prepend_T_128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1986 = or(out_prepend_128, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1987 = bits(_out_T_1986, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_162 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_162 = orr(_out_rimask_T_162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_162 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_162 = andr(_out_wimask_T_162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_162 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_162 = orr(_out_romask_T_162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_162 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_162 = andr(_out_womask_T_162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_162 = and(out_rivalid_1[40], out_rimask_162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_162 = and(out_roready_1[40], out_romask_162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_162 = and(out_wivalid_1[40], out_wimask_162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_162 = and(out_woready_1[40], out_womask_162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1988 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1989 = and(out_f_rivalid_162, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1990 = and(UInt<1>(0h1), out_f_roready_162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1991 = eq(out_rimask_162, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1992 = eq(out_wimask_162, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1993 = eq(out_romask_162, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1994 = eq(out_womask_162, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1995 = or(_T_1394, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1996 = bits(_out_T_1995, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_163 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_163 = orr(_out_rimask_T_163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_163 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_163 = andr(_out_wimask_T_163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_163 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_163 = orr(_out_romask_T_163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_163 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_163 = andr(_out_womask_T_163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_163 = and(out_rivalid_1[41], out_rimask_163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_163 = and(out_roready_1[41], out_romask_163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_163 = and(out_wivalid_1[41], out_wimask_163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_163 = and(out_woready_1[41], out_womask_163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1997 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1998 = and(out_f_rivalid_163, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1999 = and(UInt<1>(0h1), out_f_roready_163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2000 = eq(out_rimask_163, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2001 = eq(out_wimask_163, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2002 = eq(out_romask_163, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2003 = eq(out_womask_163, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_129 = or(_out_T_1996, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_129 = cat(_T_1395, _out_prepend_T_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2004 = or(out_prepend_129, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2005 = bits(_out_T_2004, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_164 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_164 = orr(_out_rimask_T_164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_164 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_164 = andr(_out_wimask_T_164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_164 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_164 = orr(_out_romask_T_164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_164 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_164 = andr(_out_womask_T_164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_164 = and(out_rivalid_1[42], out_rimask_164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_164 = and(out_roready_1[42], out_romask_164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_164 = and(out_wivalid_1[42], out_wimask_164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_164 = and(out_woready_1[42], out_womask_164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2006 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2007 = and(out_f_rivalid_164, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2008 = and(UInt<1>(0h1), out_f_roready_164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2009 = eq(out_rimask_164, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2010 = eq(out_wimask_164, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2011 = eq(out_romask_164, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2012 = eq(out_womask_164, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_130 = or(_out_T_2005, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_130 = cat(_T_1396, _out_prepend_T_130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2013 = or(out_prepend_130, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2014 = bits(_out_T_2013, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_165 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_165 = orr(_out_rimask_T_165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_165 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_165 = andr(_out_wimask_T_165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_165 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_165 = orr(_out_romask_T_165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_165 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_165 = andr(_out_womask_T_165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_165 = and(out_rivalid_1[43], out_rimask_165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_165 = and(out_roready_1[43], out_romask_165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_165 = and(out_wivalid_1[43], out_wimask_165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_165 = and(out_woready_1[43], out_womask_165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2015 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2016 = and(out_f_rivalid_165, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2017 = and(UInt<1>(0h1), out_f_roready_165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2018 = eq(out_rimask_165, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2019 = eq(out_wimask_165, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2020 = eq(out_romask_165, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2021 = eq(out_womask_165, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_131 = or(_out_T_2014, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_131 = cat(_T_1397, _out_prepend_T_131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2022 = or(out_prepend_131, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2023 = bits(_out_T_2022, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_166 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_166 = orr(_out_rimask_T_166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_166 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_166 = andr(_out_wimask_T_166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_166 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_166 = orr(_out_romask_T_166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_166 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_166 = andr(_out_womask_T_166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_166 = and(out_rivalid_1[44], out_rimask_166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_166 = and(out_roready_1[44], out_romask_166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_166 = and(out_wivalid_1[44], out_wimask_166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_166 = and(out_woready_1[44], out_womask_166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2024 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2025 = and(out_f_rivalid_166, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2026 = and(UInt<1>(0h1), out_f_roready_166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2027 = eq(out_rimask_166, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2028 = eq(out_wimask_166, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2029 = eq(out_romask_166, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2030 = eq(out_womask_166, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_132 = or(_out_T_2023, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_132 = cat(_T_1398, _out_prepend_T_132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2031 = or(out_prepend_132, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2032 = bits(_out_T_2031, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_167 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_167 = orr(_out_rimask_T_167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_167 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_167 = andr(_out_wimask_T_167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_167 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_167 = orr(_out_romask_T_167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_167 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_167 = andr(_out_womask_T_167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_167 = and(out_rivalid_1[45], out_rimask_167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_167 = and(out_roready_1[45], out_romask_167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_167 = and(out_wivalid_1[45], out_wimask_167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_167 = and(out_woready_1[45], out_womask_167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2033 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2034 = and(out_f_rivalid_167, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2035 = and(UInt<1>(0h1), out_f_roready_167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2036 = eq(out_rimask_167, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2037 = eq(out_wimask_167, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2038 = eq(out_romask_167, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2039 = eq(out_womask_167, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_133 = or(_out_T_2032, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_133 = cat(_T_1399, _out_prepend_T_133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2040 = or(out_prepend_133, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2041 = bits(_out_T_2040, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_168 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_168 = orr(_out_rimask_T_168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_168 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_168 = andr(_out_wimask_T_168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_168 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_168 = orr(_out_romask_T_168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_168 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_168 = andr(_out_womask_T_168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_168 = and(out_rivalid_1[46], out_rimask_168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_168 = and(out_roready_1[46], out_romask_168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_168 = and(out_wivalid_1[46], out_wimask_168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_168 = and(out_woready_1[46], out_womask_168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2042 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2043 = and(out_f_rivalid_168, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2044 = and(UInt<1>(0h1), out_f_roready_168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2045 = eq(out_rimask_168, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2046 = eq(out_wimask_168, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2047 = eq(out_romask_168, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2048 = eq(out_womask_168, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_134 = or(_out_T_2041, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_134 = cat(_T_1400, _out_prepend_T_134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2049 = or(out_prepend_134, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2050 = bits(_out_T_2049, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_169 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_169 = orr(_out_rimask_T_169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_169 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_169 = andr(_out_wimask_T_169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_169 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_169 = orr(_out_romask_T_169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_169 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_169 = andr(_out_womask_T_169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_169 = and(out_rivalid_1[47], out_rimask_169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_169 = and(out_roready_1[47], out_romask_169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_169 = and(out_wivalid_1[47], out_wimask_169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_169 = and(out_woready_1[47], out_womask_169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2051 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2052 = and(out_f_rivalid_169, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2053 = and(UInt<1>(0h1), out_f_roready_169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2054 = eq(out_rimask_169, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2055 = eq(out_wimask_169, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2056 = eq(out_romask_169, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2057 = eq(out_womask_169, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_135 = or(_out_T_2050, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_135 = cat(_T_1401, _out_prepend_T_135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2058 = or(out_prepend_135, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2059 = bits(_out_T_2058, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_170 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_170 = orr(_out_rimask_T_170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_170 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_170 = andr(_out_wimask_T_170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_170 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_170 = orr(_out_romask_T_170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_170 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_170 = andr(_out_womask_T_170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_170 = and(out_rivalid_1[48], out_rimask_170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_170 = and(out_roready_1[48], out_romask_170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_170 = and(out_wivalid_1[48], out_wimask_170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_170 = and(out_woready_1[48], out_womask_170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2060 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2061 = and(out_f_rivalid_170, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2062 = and(UInt<1>(0h1), out_f_roready_170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2063 = eq(out_rimask_170, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2064 = eq(out_wimask_170, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2065 = eq(out_romask_170, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2066 = eq(out_womask_170, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2067 = or(_T_1034, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2068 = bits(_out_T_2067, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_171 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_171 = orr(_out_rimask_T_171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_171 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_171 = andr(_out_wimask_T_171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_171 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_171 = orr(_out_romask_T_171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_171 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_171 = andr(_out_womask_T_171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_171 = and(out_rivalid_1[49], out_rimask_171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_171 = and(out_roready_1[49], out_romask_171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_171 = and(out_wivalid_1[49], out_wimask_171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_171 = and(out_woready_1[49], out_womask_171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2069 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2070 = and(out_f_rivalid_171, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2071 = and(UInt<1>(0h1), out_f_roready_171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2072 = eq(out_rimask_171, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2073 = eq(out_wimask_171, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2074 = eq(out_romask_171, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2075 = eq(out_womask_171, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_136 = or(_out_T_2068, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_136 = cat(_T_1035, _out_prepend_T_136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2076 = or(out_prepend_136, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2077 = bits(_out_T_2076, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_172 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_172 = orr(_out_rimask_T_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_172 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_172 = andr(_out_wimask_T_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_172 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_172 = orr(_out_romask_T_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_172 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_172 = andr(_out_womask_T_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_172 = and(out_rivalid_1[50], out_rimask_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_172 = and(out_roready_1[50], out_romask_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_172 = and(out_wivalid_1[50], out_wimask_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_172 = and(out_woready_1[50], out_womask_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2078 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2079 = and(out_f_rivalid_172, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2080 = and(UInt<1>(0h1), out_f_roready_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2081 = eq(out_rimask_172, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2082 = eq(out_wimask_172, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2083 = eq(out_romask_172, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2084 = eq(out_womask_172, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_137 = or(_out_T_2077, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_137 = cat(_T_1036, _out_prepend_T_137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2085 = or(out_prepend_137, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2086 = bits(_out_T_2085, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_173 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_173 = orr(_out_rimask_T_173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_173 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_173 = andr(_out_wimask_T_173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_173 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_173 = orr(_out_romask_T_173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_173 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_173 = andr(_out_womask_T_173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_173 = and(out_rivalid_1[51], out_rimask_173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_173 = and(out_roready_1[51], out_romask_173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_173 = and(out_wivalid_1[51], out_wimask_173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_173 = and(out_woready_1[51], out_womask_173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2087 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2088 = and(out_f_rivalid_173, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2089 = and(UInt<1>(0h1), out_f_roready_173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2090 = eq(out_rimask_173, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2091 = eq(out_wimask_173, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2092 = eq(out_romask_173, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2093 = eq(out_womask_173, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_138 = or(_out_T_2086, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_138 = cat(_T_1037, _out_prepend_T_138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2094 = or(out_prepend_138, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2095 = bits(_out_T_2094, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_174 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_174 = orr(_out_rimask_T_174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_174 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_174 = andr(_out_wimask_T_174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_174 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_174 = orr(_out_romask_T_174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_174 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_174 = andr(_out_womask_T_174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_174 = and(out_rivalid_1[52], out_rimask_174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_174 = and(out_roready_1[52], out_romask_174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_174 = and(out_wivalid_1[52], out_wimask_174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_174 = and(out_woready_1[52], out_womask_174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2096 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2097 = and(out_f_rivalid_174, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2098 = and(UInt<1>(0h1), out_f_roready_174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2099 = eq(out_rimask_174, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2100 = eq(out_wimask_174, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2101 = eq(out_romask_174, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2102 = eq(out_womask_174, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_139 = or(_out_T_2095, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_139 = cat(_T_1038, _out_prepend_T_139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2103 = or(out_prepend_139, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2104 = bits(_out_T_2103, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_175 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_175 = orr(_out_rimask_T_175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_175 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_175 = andr(_out_wimask_T_175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_175 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_175 = orr(_out_romask_T_175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_175 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_175 = andr(_out_womask_T_175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_175 = and(out_rivalid_1[53], out_rimask_175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_175 = and(out_roready_1[53], out_romask_175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_175 = and(out_wivalid_1[53], out_wimask_175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_175 = and(out_woready_1[53], out_womask_175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2105 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2106 = and(out_f_rivalid_175, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2107 = and(UInt<1>(0h1), out_f_roready_175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2108 = eq(out_rimask_175, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2109 = eq(out_wimask_175, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2110 = eq(out_romask_175, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2111 = eq(out_womask_175, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_140 = or(_out_T_2104, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_140 = cat(_T_1039, _out_prepend_T_140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2112 = or(out_prepend_140, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2113 = bits(_out_T_2112, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_176 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_176 = orr(_out_rimask_T_176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_176 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_176 = andr(_out_wimask_T_176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_176 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_176 = orr(_out_romask_T_176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_176 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_176 = andr(_out_womask_T_176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_176 = and(out_rivalid_1[54], out_rimask_176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_176 = and(out_roready_1[54], out_romask_176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_176 = and(out_wivalid_1[54], out_wimask_176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_176 = and(out_woready_1[54], out_womask_176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2114 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2115 = and(out_f_rivalid_176, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2116 = and(UInt<1>(0h1), out_f_roready_176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2117 = eq(out_rimask_176, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2118 = eq(out_wimask_176, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2119 = eq(out_romask_176, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2120 = eq(out_womask_176, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_141 = or(_out_T_2113, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_141 = cat(_T_1040, _out_prepend_T_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2121 = or(out_prepend_141, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2122 = bits(_out_T_2121, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_177 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_177 = orr(_out_rimask_T_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_177 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_177 = andr(_out_wimask_T_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_177 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_177 = orr(_out_romask_T_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_177 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_177 = andr(_out_womask_T_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_177 = and(out_rivalid_1[55], out_rimask_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_177 = and(out_roready_1[55], out_romask_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_177 = and(out_wivalid_1[55], out_wimask_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_177 = and(out_woready_1[55], out_womask_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2123 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2124 = and(out_f_rivalid_177, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2125 = and(UInt<1>(0h1), out_f_roready_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2126 = eq(out_rimask_177, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2127 = eq(out_wimask_177, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2128 = eq(out_romask_177, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2129 = eq(out_womask_177, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_142 = or(_out_T_2122, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_142 = cat(_T_1041, _out_prepend_T_142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2130 = or(out_prepend_142, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2131 = bits(_out_T_2130, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_178 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_178 = orr(_out_rimask_T_178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_178 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_178 = andr(_out_wimask_T_178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_178 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_178 = orr(_out_romask_T_178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_178 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_178 = andr(_out_womask_T_178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_178 = and(out_rivalid_1[56], out_rimask_178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_178 = and(out_roready_1[56], out_romask_178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_178 = and(out_wivalid_1[56], out_wimask_178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_178 = and(out_woready_1[56], out_womask_178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2132 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2133 = and(out_f_rivalid_178, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2134 = and(UInt<1>(0h1), out_f_roready_178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2135 = eq(out_rimask_178, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2136 = eq(out_wimask_178, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2137 = eq(out_romask_178, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2138 = eq(out_womask_178, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2139 = or(_T_554, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2140 = bits(_out_T_2139, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_179 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_179 = orr(_out_rimask_T_179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_179 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_179 = andr(_out_wimask_T_179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_179 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_179 = orr(_out_romask_T_179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_179 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_179 = andr(_out_womask_T_179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_179 = and(out_rivalid_1[57], out_rimask_179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_179 = and(out_roready_1[57], out_romask_179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_179 = and(out_wivalid_1[57], out_wimask_179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_179 = and(out_woready_1[57], out_womask_179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2141 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2142 = and(out_f_rivalid_179, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2143 = and(UInt<1>(0h1), out_f_roready_179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2144 = eq(out_rimask_179, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2145 = eq(out_wimask_179, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2146 = eq(out_romask_179, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2147 = eq(out_womask_179, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_143 = or(_out_T_2140, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_143 = cat(_T_555, _out_prepend_T_143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2148 = or(out_prepend_143, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2149 = bits(_out_T_2148, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_180 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_180 = orr(_out_rimask_T_180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_180 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_180 = andr(_out_wimask_T_180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_180 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_180 = orr(_out_romask_T_180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_180 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_180 = andr(_out_womask_T_180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_180 = and(out_rivalid_1[58], out_rimask_180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_180 = and(out_roready_1[58], out_romask_180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_180 = and(out_wivalid_1[58], out_wimask_180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_180 = and(out_woready_1[58], out_womask_180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2150 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2151 = and(out_f_rivalid_180, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2152 = and(UInt<1>(0h1), out_f_roready_180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2153 = eq(out_rimask_180, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2154 = eq(out_wimask_180, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2155 = eq(out_romask_180, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2156 = eq(out_womask_180, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_144 = or(_out_T_2149, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_144 = cat(_T_556, _out_prepend_T_144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2157 = or(out_prepend_144, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2158 = bits(_out_T_2157, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_181 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_181 = orr(_out_rimask_T_181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_181 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_181 = andr(_out_wimask_T_181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_181 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_181 = orr(_out_romask_T_181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_181 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_181 = andr(_out_womask_T_181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_181 = and(out_rivalid_1[59], out_rimask_181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_181 = and(out_roready_1[59], out_romask_181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_181 = and(out_wivalid_1[59], out_wimask_181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_181 = and(out_woready_1[59], out_womask_181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2159 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2160 = and(out_f_rivalid_181, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2161 = and(UInt<1>(0h1), out_f_roready_181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2162 = eq(out_rimask_181, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2163 = eq(out_wimask_181, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2164 = eq(out_romask_181, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2165 = eq(out_womask_181, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_145 = or(_out_T_2158, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_145 = cat(_T_557, _out_prepend_T_145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2166 = or(out_prepend_145, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2167 = bits(_out_T_2166, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_182 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_182 = orr(_out_rimask_T_182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_182 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_182 = andr(_out_wimask_T_182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_182 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_182 = orr(_out_romask_T_182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_182 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_182 = andr(_out_womask_T_182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_182 = and(out_rivalid_1[60], out_rimask_182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_182 = and(out_roready_1[60], out_romask_182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_182 = and(out_wivalid_1[60], out_wimask_182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_182 = and(out_woready_1[60], out_womask_182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2168 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2169 = and(out_f_rivalid_182, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2170 = and(UInt<1>(0h1), out_f_roready_182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2171 = eq(out_rimask_182, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2172 = eq(out_wimask_182, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2173 = eq(out_romask_182, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2174 = eq(out_womask_182, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_146 = or(_out_T_2167, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_146 = cat(_T_558, _out_prepend_T_146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2175 = or(out_prepend_146, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2176 = bits(_out_T_2175, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_183 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_183 = orr(_out_rimask_T_183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_183 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_183 = andr(_out_wimask_T_183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_183 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_183 = orr(_out_romask_T_183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_183 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_183 = andr(_out_womask_T_183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_183 = and(out_rivalid_1[61], out_rimask_183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_183 = and(out_roready_1[61], out_romask_183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_183 = and(out_wivalid_1[61], out_wimask_183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_183 = and(out_woready_1[61], out_womask_183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2177 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2178 = and(out_f_rivalid_183, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2179 = and(UInt<1>(0h1), out_f_roready_183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2180 = eq(out_rimask_183, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2181 = eq(out_wimask_183, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2182 = eq(out_romask_183, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2183 = eq(out_womask_183, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_147 = or(_out_T_2176, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_147 = cat(_T_559, _out_prepend_T_147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2184 = or(out_prepend_147, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2185 = bits(_out_T_2184, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_184 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_184 = orr(_out_rimask_T_184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_184 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_184 = andr(_out_wimask_T_184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_184 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_184 = orr(_out_romask_T_184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_184 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_184 = andr(_out_womask_T_184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_184 = and(out_rivalid_1[62], out_rimask_184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_184 = and(out_roready_1[62], out_romask_184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_184 = and(out_wivalid_1[62], out_wimask_184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_184 = and(out_woready_1[62], out_womask_184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2186 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2187 = and(out_f_rivalid_184, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2188 = and(UInt<1>(0h1), out_f_roready_184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2189 = eq(out_rimask_184, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2190 = eq(out_wimask_184, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2191 = eq(out_romask_184, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2192 = eq(out_womask_184, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_148 = or(_out_T_2185, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_148 = cat(_T_560, _out_prepend_T_148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2193 = or(out_prepend_148, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2194 = bits(_out_T_2193, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_185 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_185 = orr(_out_rimask_T_185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_185 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_185 = andr(_out_wimask_T_185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_185 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_185 = orr(_out_romask_T_185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_185 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_185 = andr(_out_womask_T_185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_185 = and(out_rivalid_1[63], out_rimask_185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_185 = and(out_roready_1[63], out_romask_185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_185 = and(out_wivalid_1[63], out_wimask_185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_185 = and(out_woready_1[63], out_womask_185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2195 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2196 = and(out_f_rivalid_185, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2197 = and(UInt<1>(0h1), out_f_roready_185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2198 = eq(out_rimask_185, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2199 = eq(out_wimask_185, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2200 = eq(out_romask_185, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2201 = eq(out_womask_185, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_149 = or(_out_T_2194, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_149 = cat(_T_561, _out_prepend_T_149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2202 = or(out_prepend_149, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2203 = bits(_out_T_2202, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_186 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_186 = orr(_out_rimask_T_186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_186 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_186 = andr(_out_wimask_T_186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_186 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_186 = orr(_out_romask_T_186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_186 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_186 = andr(_out_womask_T_186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_186 = and(out_rivalid_1[64], out_rimask_186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_186 = and(out_roready_1[64], out_romask_186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_186 = and(out_wivalid_1[64], out_wimask_186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_186 = and(out_woready_1[64], out_womask_186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2204 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2205 = and(out_f_rivalid_186, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2206 = and(UInt<1>(0h1), out_f_roready_186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2207 = eq(out_rimask_186, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2208 = eq(out_wimask_186, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2209 = eq(out_romask_186, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2210 = eq(out_womask_186, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2211 = or(_T_642, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2212 = bits(_out_T_2211, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_187 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_187 = orr(_out_rimask_T_187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_187 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_187 = andr(_out_wimask_T_187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_187 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_187 = orr(_out_romask_T_187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_187 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_187 = andr(_out_womask_T_187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_187 = and(out_rivalid_1[65], out_rimask_187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_187 = and(out_roready_1[65], out_romask_187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_187 = and(out_wivalid_1[65], out_wimask_187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_187 = and(out_woready_1[65], out_womask_187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2213 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2214 = and(out_f_rivalid_187, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2215 = and(UInt<1>(0h1), out_f_roready_187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2216 = eq(out_rimask_187, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2217 = eq(out_wimask_187, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2218 = eq(out_romask_187, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2219 = eq(out_womask_187, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_150 = or(_out_T_2212, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_150 = cat(_T_643, _out_prepend_T_150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2220 = or(out_prepend_150, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2221 = bits(_out_T_2220, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_188 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_188 = orr(_out_rimask_T_188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_188 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_188 = andr(_out_wimask_T_188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_188 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_188 = orr(_out_romask_T_188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_188 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_188 = andr(_out_womask_T_188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_188 = and(out_rivalid_1[66], out_rimask_188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_188 = and(out_roready_1[66], out_romask_188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_188 = and(out_wivalid_1[66], out_wimask_188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_188 = and(out_woready_1[66], out_womask_188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2222 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2223 = and(out_f_rivalid_188, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2224 = and(UInt<1>(0h1), out_f_roready_188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2225 = eq(out_rimask_188, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2226 = eq(out_wimask_188, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2227 = eq(out_romask_188, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2228 = eq(out_womask_188, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_151 = or(_out_T_2221, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_151 = cat(_T_644, _out_prepend_T_151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2229 = or(out_prepend_151, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2230 = bits(_out_T_2229, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_189 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_189 = orr(_out_rimask_T_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_189 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_189 = andr(_out_wimask_T_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_189 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_189 = orr(_out_romask_T_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_189 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_189 = andr(_out_womask_T_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_189 = and(out_rivalid_1[67], out_rimask_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_189 = and(out_roready_1[67], out_romask_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_189 = and(out_wivalid_1[67], out_wimask_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_189 = and(out_woready_1[67], out_womask_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2231 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2232 = and(out_f_rivalid_189, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2233 = and(UInt<1>(0h1), out_f_roready_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2234 = eq(out_rimask_189, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2235 = eq(out_wimask_189, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2236 = eq(out_romask_189, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2237 = eq(out_womask_189, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_152 = or(_out_T_2230, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_152 = cat(_T_645, _out_prepend_T_152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2238 = or(out_prepend_152, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2239 = bits(_out_T_2238, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_190 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_190 = orr(_out_rimask_T_190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_190 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_190 = andr(_out_wimask_T_190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_190 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_190 = orr(_out_romask_T_190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_190 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_190 = andr(_out_womask_T_190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_190 = and(out_rivalid_1[68], out_rimask_190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_190 = and(out_roready_1[68], out_romask_190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_190 = and(out_wivalid_1[68], out_wimask_190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_190 = and(out_woready_1[68], out_womask_190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2240 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2241 = and(out_f_rivalid_190, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2242 = and(UInt<1>(0h1), out_f_roready_190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2243 = eq(out_rimask_190, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2244 = eq(out_wimask_190, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2245 = eq(out_romask_190, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2246 = eq(out_womask_190, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_153 = or(_out_T_2239, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_153 = cat(_T_646, _out_prepend_T_153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2247 = or(out_prepend_153, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2248 = bits(_out_T_2247, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_191 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_191 = orr(_out_rimask_T_191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_191 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_191 = andr(_out_wimask_T_191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_191 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_191 = orr(_out_romask_T_191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_191 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_191 = andr(_out_womask_T_191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_191 = and(out_rivalid_1[69], out_rimask_191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_191 = and(out_roready_1[69], out_romask_191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_191 = and(out_wivalid_1[69], out_wimask_191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_191 = and(out_woready_1[69], out_womask_191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2249 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2250 = and(out_f_rivalid_191, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2251 = and(UInt<1>(0h1), out_f_roready_191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2252 = eq(out_rimask_191, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2253 = eq(out_wimask_191, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2254 = eq(out_romask_191, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2255 = eq(out_womask_191, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_154 = or(_out_T_2248, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_154 = cat(_T_647, _out_prepend_T_154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2256 = or(out_prepend_154, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2257 = bits(_out_T_2256, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_192 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_192 = orr(_out_rimask_T_192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_192 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_192 = andr(_out_wimask_T_192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_192 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_192 = orr(_out_romask_T_192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_192 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_192 = andr(_out_womask_T_192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_192 = and(out_rivalid_1[70], out_rimask_192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_192 = and(out_roready_1[70], out_romask_192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_192 = and(out_wivalid_1[70], out_wimask_192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_192 = and(out_woready_1[70], out_womask_192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2258 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2259 = and(out_f_rivalid_192, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2260 = and(UInt<1>(0h1), out_f_roready_192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2261 = eq(out_rimask_192, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2262 = eq(out_wimask_192, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2263 = eq(out_romask_192, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2264 = eq(out_womask_192, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_155 = or(_out_T_2257, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_155 = cat(_T_648, _out_prepend_T_155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2265 = or(out_prepend_155, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2266 = bits(_out_T_2265, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_193 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_193 = orr(_out_rimask_T_193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_193 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_193 = andr(_out_wimask_T_193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_193 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_193 = orr(_out_romask_T_193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_193 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_193 = andr(_out_womask_T_193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_193 = and(out_rivalid_1[71], out_rimask_193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_193 = and(out_roready_1[71], out_romask_193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_193 = and(out_wivalid_1[71], out_wimask_193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_193 = and(out_woready_1[71], out_womask_193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2267 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2268 = and(out_f_rivalid_193, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2269 = and(UInt<1>(0h1), out_f_roready_193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2270 = eq(out_rimask_193, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2271 = eq(out_wimask_193, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2272 = eq(out_romask_193, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2273 = eq(out_womask_193, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_156 = or(_out_T_2266, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_156 = cat(_T_649, _out_prepend_T_156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2274 = or(out_prepend_156, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2275 = bits(_out_T_2274, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_194 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_194 = orr(_out_rimask_T_194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_194 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_194 = andr(_out_wimask_T_194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_194 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_194 = orr(_out_romask_T_194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_194 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_194 = andr(_out_womask_T_194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_194 = and(out_rivalid_1[72], out_rimask_194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_194 = and(out_roready_1[72], out_romask_194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_194 = and(out_wivalid_1[72], out_wimask_194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_194 = and(out_woready_1[72], out_womask_194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2276 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2277 = and(out_f_rivalid_194, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2278 = and(UInt<1>(0h1), out_f_roready_194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2279 = eq(out_rimask_194, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2280 = eq(out_wimask_194, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2281 = eq(out_romask_194, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2282 = eq(out_womask_194, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2283 = or(_T_810, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2284 = bits(_out_T_2283, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_195 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_195 = orr(_out_rimask_T_195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_195 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_195 = andr(_out_wimask_T_195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_195 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_195 = orr(_out_romask_T_195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_195 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_195 = andr(_out_womask_T_195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_195 = and(out_rivalid_1[73], out_rimask_195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_195 = and(out_roready_1[73], out_romask_195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_195 = and(out_wivalid_1[73], out_wimask_195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_195 = and(out_woready_1[73], out_womask_195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2285 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2286 = and(out_f_rivalid_195, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2287 = and(UInt<1>(0h1), out_f_roready_195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2288 = eq(out_rimask_195, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2289 = eq(out_wimask_195, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2290 = eq(out_romask_195, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2291 = eq(out_womask_195, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_157 = or(_out_T_2284, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_157 = cat(_T_811, _out_prepend_T_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2292 = or(out_prepend_157, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2293 = bits(_out_T_2292, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_196 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_196 = orr(_out_rimask_T_196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_196 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_196 = andr(_out_wimask_T_196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_196 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_196 = orr(_out_romask_T_196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_196 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_196 = andr(_out_womask_T_196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_196 = and(out_rivalid_1[74], out_rimask_196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_196 = and(out_roready_1[74], out_romask_196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_196 = and(out_wivalid_1[74], out_wimask_196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_196 = and(out_woready_1[74], out_womask_196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2294 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2295 = and(out_f_rivalid_196, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2296 = and(UInt<1>(0h1), out_f_roready_196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2297 = eq(out_rimask_196, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2298 = eq(out_wimask_196, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2299 = eq(out_romask_196, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2300 = eq(out_womask_196, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_158 = or(_out_T_2293, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_158 = cat(_T_812, _out_prepend_T_158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2301 = or(out_prepend_158, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2302 = bits(_out_T_2301, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_197 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_197 = orr(_out_rimask_T_197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_197 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_197 = andr(_out_wimask_T_197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_197 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_197 = orr(_out_romask_T_197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_197 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_197 = andr(_out_womask_T_197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_197 = and(out_rivalid_1[75], out_rimask_197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_197 = and(out_roready_1[75], out_romask_197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_197 = and(out_wivalid_1[75], out_wimask_197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_197 = and(out_woready_1[75], out_womask_197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2303 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2304 = and(out_f_rivalid_197, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2305 = and(UInt<1>(0h1), out_f_roready_197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2306 = eq(out_rimask_197, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2307 = eq(out_wimask_197, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2308 = eq(out_romask_197, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2309 = eq(out_womask_197, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_159 = or(_out_T_2302, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_159 = cat(_T_813, _out_prepend_T_159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2310 = or(out_prepend_159, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2311 = bits(_out_T_2310, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_198 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_198 = orr(_out_rimask_T_198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_198 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_198 = andr(_out_wimask_T_198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_198 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_198 = orr(_out_romask_T_198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_198 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_198 = andr(_out_womask_T_198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_198 = and(out_rivalid_1[76], out_rimask_198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_198 = and(out_roready_1[76], out_romask_198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_198 = and(out_wivalid_1[76], out_wimask_198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_198 = and(out_woready_1[76], out_womask_198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2312 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2313 = and(out_f_rivalid_198, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2314 = and(UInt<1>(0h1), out_f_roready_198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2315 = eq(out_rimask_198, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2316 = eq(out_wimask_198, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2317 = eq(out_romask_198, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2318 = eq(out_womask_198, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_160 = or(_out_T_2311, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_160 = cat(_T_814, _out_prepend_T_160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2319 = or(out_prepend_160, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2320 = bits(_out_T_2319, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_199 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_199 = orr(_out_rimask_T_199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_199 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_199 = andr(_out_wimask_T_199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_199 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_199 = orr(_out_romask_T_199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_199 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_199 = andr(_out_womask_T_199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_199 = and(out_rivalid_1[77], out_rimask_199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_199 = and(out_roready_1[77], out_romask_199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_199 = and(out_wivalid_1[77], out_wimask_199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_199 = and(out_woready_1[77], out_womask_199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2321 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2322 = and(out_f_rivalid_199, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2323 = and(UInt<1>(0h1), out_f_roready_199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2324 = eq(out_rimask_199, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2325 = eq(out_wimask_199, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2326 = eq(out_romask_199, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2327 = eq(out_womask_199, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_161 = or(_out_T_2320, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_161 = cat(_T_815, _out_prepend_T_161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2328 = or(out_prepend_161, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2329 = bits(_out_T_2328, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_200 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_200 = orr(_out_rimask_T_200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_200 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_200 = andr(_out_wimask_T_200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_200 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_200 = orr(_out_romask_T_200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_200 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_200 = andr(_out_womask_T_200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_200 = and(out_rivalid_1[78], out_rimask_200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_200 = and(out_roready_1[78], out_romask_200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_200 = and(out_wivalid_1[78], out_wimask_200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_200 = and(out_woready_1[78], out_womask_200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2330 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2331 = and(out_f_rivalid_200, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2332 = and(UInt<1>(0h1), out_f_roready_200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2333 = eq(out_rimask_200, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2334 = eq(out_wimask_200, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2335 = eq(out_romask_200, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2336 = eq(out_womask_200, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_162 = or(_out_T_2329, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_162 = cat(_T_816, _out_prepend_T_162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2337 = or(out_prepend_162, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2338 = bits(_out_T_2337, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_201 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_201 = orr(_out_rimask_T_201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_201 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_201 = andr(_out_wimask_T_201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_201 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_201 = orr(_out_romask_T_201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_201 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_201 = andr(_out_womask_T_201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_201 = and(out_rivalid_1[79], out_rimask_201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_201 = and(out_roready_1[79], out_romask_201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_201 = and(out_wivalid_1[79], out_wimask_201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_201 = and(out_woready_1[79], out_womask_201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2339 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2340 = and(out_f_rivalid_201, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2341 = and(UInt<1>(0h1), out_f_roready_201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2342 = eq(out_rimask_201, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2343 = eq(out_wimask_201, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2344 = eq(out_romask_201, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2345 = eq(out_womask_201, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_163 = or(_out_T_2338, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_163 = cat(_T_817, _out_prepend_T_163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2346 = or(out_prepend_163, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2347 = bits(_out_T_2346, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_202 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_202 = orr(_out_rimask_T_202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_202 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_202 = andr(_out_wimask_T_202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_202 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_202 = orr(_out_romask_T_202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_202 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_202 = andr(_out_womask_T_202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_202 = and(out_rivalid_1[80], out_rimask_202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_202 = and(out_roready_1[80], out_romask_202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_202 = and(out_wivalid_1[80], out_wimask_202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_202 = and(out_woready_1[80], out_womask_202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2348 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2349 = and(out_f_rivalid_202, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2350 = and(UInt<1>(0h1), out_f_roready_202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2351 = eq(out_rimask_202, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2352 = eq(out_wimask_202, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2353 = eq(out_romask_202, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2354 = eq(out_womask_202, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2355 = or(_T_898, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2356 = bits(_out_T_2355, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_203 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_203 = orr(_out_rimask_T_203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_203 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_203 = andr(_out_wimask_T_203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_203 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_203 = orr(_out_romask_T_203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_203 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_203 = andr(_out_womask_T_203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_203 = and(out_rivalid_1[81], out_rimask_203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_203 = and(out_roready_1[81], out_romask_203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_203 = and(out_wivalid_1[81], out_wimask_203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_203 = and(out_woready_1[81], out_womask_203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2357 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2358 = and(out_f_rivalid_203, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2359 = and(UInt<1>(0h1), out_f_roready_203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2360 = eq(out_rimask_203, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2361 = eq(out_wimask_203, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2362 = eq(out_romask_203, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2363 = eq(out_womask_203, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_164 = or(_out_T_2356, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_164 = cat(_T_899, _out_prepend_T_164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2364 = or(out_prepend_164, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2365 = bits(_out_T_2364, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_204 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_204 = orr(_out_rimask_T_204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_204 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_204 = andr(_out_wimask_T_204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_204 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_204 = orr(_out_romask_T_204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_204 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_204 = andr(_out_womask_T_204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_204 = and(out_rivalid_1[82], out_rimask_204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_204 = and(out_roready_1[82], out_romask_204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_204 = and(out_wivalid_1[82], out_wimask_204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_204 = and(out_woready_1[82], out_womask_204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2366 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2367 = and(out_f_rivalid_204, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2368 = and(UInt<1>(0h1), out_f_roready_204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2369 = eq(out_rimask_204, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2370 = eq(out_wimask_204, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2371 = eq(out_romask_204, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2372 = eq(out_womask_204, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_165 = or(_out_T_2365, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_165 = cat(_T_900, _out_prepend_T_165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2373 = or(out_prepend_165, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2374 = bits(_out_T_2373, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_205 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_205 = orr(_out_rimask_T_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_205 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_205 = andr(_out_wimask_T_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_205 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_205 = orr(_out_romask_T_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_205 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_205 = andr(_out_womask_T_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_205 = and(out_rivalid_1[83], out_rimask_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_205 = and(out_roready_1[83], out_romask_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_205 = and(out_wivalid_1[83], out_wimask_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_205 = and(out_woready_1[83], out_womask_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2375 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2376 = and(out_f_rivalid_205, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2377 = and(UInt<1>(0h1), out_f_roready_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2378 = eq(out_rimask_205, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2379 = eq(out_wimask_205, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2380 = eq(out_romask_205, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2381 = eq(out_womask_205, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_166 = or(_out_T_2374, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_166 = cat(_T_901, _out_prepend_T_166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2382 = or(out_prepend_166, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2383 = bits(_out_T_2382, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_206 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_206 = orr(_out_rimask_T_206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_206 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_206 = andr(_out_wimask_T_206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_206 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_206 = orr(_out_romask_T_206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_206 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_206 = andr(_out_womask_T_206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_206 = and(out_rivalid_1[84], out_rimask_206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_206 = and(out_roready_1[84], out_romask_206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_206 = and(out_wivalid_1[84], out_wimask_206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_206 = and(out_woready_1[84], out_womask_206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2384 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2385 = and(out_f_rivalid_206, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2386 = and(UInt<1>(0h1), out_f_roready_206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2387 = eq(out_rimask_206, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2388 = eq(out_wimask_206, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2389 = eq(out_romask_206, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2390 = eq(out_womask_206, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_167 = or(_out_T_2383, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_167 = cat(_T_902, _out_prepend_T_167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2391 = or(out_prepend_167, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2392 = bits(_out_T_2391, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_207 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_207 = orr(_out_rimask_T_207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_207 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_207 = andr(_out_wimask_T_207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_207 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_207 = orr(_out_romask_T_207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_207 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_207 = andr(_out_womask_T_207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_207 = and(out_rivalid_1[85], out_rimask_207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_207 = and(out_roready_1[85], out_romask_207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_207 = and(out_wivalid_1[85], out_wimask_207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_207 = and(out_woready_1[85], out_womask_207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2393 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2394 = and(out_f_rivalid_207, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2395 = and(UInt<1>(0h1), out_f_roready_207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2396 = eq(out_rimask_207, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2397 = eq(out_wimask_207, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2398 = eq(out_romask_207, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2399 = eq(out_womask_207, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_168 = or(_out_T_2392, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_168 = cat(_T_903, _out_prepend_T_168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2400 = or(out_prepend_168, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2401 = bits(_out_T_2400, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_208 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_208 = orr(_out_rimask_T_208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_208 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_208 = andr(_out_wimask_T_208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_208 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_208 = orr(_out_romask_T_208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_208 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_208 = andr(_out_womask_T_208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_208 = and(out_rivalid_1[86], out_rimask_208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_208 = and(out_roready_1[86], out_romask_208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_208 = and(out_wivalid_1[86], out_wimask_208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_208 = and(out_woready_1[86], out_womask_208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2402 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2403 = and(out_f_rivalid_208, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2404 = and(UInt<1>(0h1), out_f_roready_208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2405 = eq(out_rimask_208, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2406 = eq(out_wimask_208, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2407 = eq(out_romask_208, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2408 = eq(out_womask_208, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_169 = or(_out_T_2401, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_169 = cat(_T_904, _out_prepend_T_169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2409 = or(out_prepend_169, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2410 = bits(_out_T_2409, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_209 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_209 = orr(_out_rimask_T_209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_209 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_209 = andr(_out_wimask_T_209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_209 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_209 = orr(_out_romask_T_209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_209 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_209 = andr(_out_womask_T_209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_209 = and(out_rivalid_1[87], out_rimask_209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_209 = and(out_roready_1[87], out_romask_209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_209 = and(out_wivalid_1[87], out_wimask_209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_209 = and(out_woready_1[87], out_womask_209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2411 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2412 = and(out_f_rivalid_209, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2413 = and(UInt<1>(0h1), out_f_roready_209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2414 = eq(out_rimask_209, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2415 = eq(out_wimask_209, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2416 = eq(out_romask_209, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2417 = eq(out_womask_209, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_170 = or(_out_T_2410, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_170 = cat(_T_905, _out_prepend_T_170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2418 = or(out_prepend_170, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2419 = bits(_out_T_2418, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_210 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_210 = orr(_out_rimask_T_210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_210 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_210 = andr(_out_wimask_T_210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_210 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_210 = orr(_out_romask_T_210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_210 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_210 = andr(_out_womask_T_210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_210 = and(out_rivalid_1[88], out_rimask_210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_210 = and(out_roready_1[88], out_romask_210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_210 = and(out_wivalid_1[88], out_wimask_210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_210 = and(out_woready_1[88], out_womask_210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2420 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2421 = and(out_f_rivalid_210, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2422 = and(UInt<1>(0h1), out_f_roready_210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2423 = eq(out_rimask_210, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2424 = eq(out_wimask_210, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2425 = eq(out_romask_210, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2426 = eq(out_womask_210, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2427 = or(UInt<8>(0h6f), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2428 = bits(_out_T_2427, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_211 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_211 = orr(_out_rimask_T_211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_211 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_211 = andr(_out_wimask_T_211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_211 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_211 = orr(_out_romask_T_211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_211 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_211 = andr(_out_womask_T_211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_211 = and(out_rivalid_1[89], out_rimask_211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_211 = and(out_roready_1[89], out_romask_211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_211 = and(out_wivalid_1[89], out_wimask_211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_211 = and(out_woready_1[89], out_womask_211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2429 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2430 = and(out_f_rivalid_211, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2431 = and(UInt<1>(0h1), out_f_roready_211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2432 = eq(out_rimask_211, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2433 = eq(out_wimask_211, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2434 = eq(out_romask_211, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2435 = eq(out_womask_211, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_171 = or(_out_T_2428, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_171 = cat(UInt<8>(0h0), _out_prepend_T_171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2436 = or(out_prepend_171, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2437 = bits(_out_T_2436, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_212 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_212 = orr(_out_rimask_T_212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_212 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_212 = andr(_out_wimask_T_212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_212 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_212 = orr(_out_romask_T_212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_212 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_212 = andr(_out_womask_T_212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_212 = and(out_rivalid_1[90], out_rimask_212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_212 = and(out_roready_1[90], out_romask_212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_212 = and(out_wivalid_1[90], out_wimask_212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_212 = and(out_woready_1[90], out_womask_212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2438 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2439 = and(out_f_rivalid_212, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2440 = and(UInt<1>(0h1), out_f_roready_212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2441 = eq(out_rimask_212, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2442 = eq(out_wimask_212, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2443 = eq(out_romask_212, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2444 = eq(out_womask_212, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_172 = or(_out_T_2437, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_172 = cat(UInt<8>(0h40), _out_prepend_T_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2445 = or(out_prepend_172, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2446 = bits(_out_T_2445, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_213 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_213 = orr(_out_rimask_T_213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_213 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_213 = andr(_out_wimask_T_213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_213 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_213 = orr(_out_romask_T_213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_213 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_213 = andr(_out_womask_T_213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_213 = and(out_rivalid_1[91], out_rimask_213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_213 = and(out_roready_1[91], out_romask_213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_213 = and(out_wivalid_1[91], out_wimask_213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_213 = and(out_woready_1[91], out_womask_213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2447 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2448 = and(out_f_rivalid_213, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2449 = and(UInt<1>(0h1), out_f_roready_213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2450 = eq(out_rimask_213, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2451 = eq(out_wimask_213, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2452 = eq(out_romask_213, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2453 = eq(out_womask_213, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_173 = or(_out_T_2446, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_173 = cat(UInt<8>(0h4), _out_prepend_T_173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2454 = or(out_prepend_173, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2455 = bits(_out_T_2454, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_214 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_214 = orr(_out_rimask_T_214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_214 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_214 = andr(_out_wimask_T_214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_214 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_214 = orr(_out_romask_T_214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_214 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_214 = andr(_out_womask_T_214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_214 = and(out_rivalid_1[92], out_rimask_214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_214 = and(out_roready_1[92], out_romask_214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_214 = and(out_wivalid_1[92], out_wimask_214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_214 = and(out_woready_1[92], out_womask_214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2456 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2457 = and(out_f_rivalid_214, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2458 = and(UInt<1>(0h1), out_f_roready_214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2459 = eq(out_rimask_214, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2460 = eq(out_wimask_214, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2461 = eq(out_romask_214, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2462 = eq(out_womask_214, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_174 = or(_out_T_2455, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_174 = cat(UInt<8>(0hf), _out_prepend_T_174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2463 = or(out_prepend_174, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2464 = bits(_out_T_2463, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_215 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_215 = orr(_out_rimask_T_215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_215 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_215 = andr(_out_wimask_T_215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_215 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_215 = orr(_out_romask_T_215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_215 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_215 = andr(_out_womask_T_215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_215 = and(out_rivalid_1[93], out_rimask_215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_215 = and(out_roready_1[93], out_romask_215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_215 = and(out_wivalid_1[93], out_wimask_215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_215 = and(out_woready_1[93], out_womask_215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2465 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2466 = and(out_f_rivalid_215, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2467 = and(UInt<1>(0h1), out_f_roready_215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2468 = eq(out_rimask_215, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2469 = eq(out_wimask_215, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2470 = eq(out_romask_215, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2471 = eq(out_womask_215, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_175 = or(_out_T_2464, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_175 = cat(UInt<8>(0h0), _out_prepend_T_175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2472 = or(out_prepend_175, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2473 = bits(_out_T_2472, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_216 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_216 = orr(_out_rimask_T_216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_216 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_216 = andr(_out_wimask_T_216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_216 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_216 = orr(_out_romask_T_216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_216 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_216 = andr(_out_womask_T_216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_216 = and(out_rivalid_1[94], out_rimask_216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_216 = and(out_roready_1[94], out_romask_216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_216 = and(out_wivalid_1[94], out_wimask_216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_216 = and(out_woready_1[94], out_womask_216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2474 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2475 = and(out_f_rivalid_216, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2476 = and(UInt<1>(0h1), out_f_roready_216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2477 = eq(out_rimask_216, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2478 = eq(out_wimask_216, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2479 = eq(out_romask_216, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2480 = eq(out_womask_216, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_176 = or(_out_T_2473, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_176 = cat(UInt<8>(0hf0), _out_prepend_T_176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2481 = or(out_prepend_176, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2482 = bits(_out_T_2481, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_217 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_217 = orr(_out_rimask_T_217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_217 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_217 = andr(_out_wimask_T_217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_217 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_217 = orr(_out_romask_T_217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_217 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_217 = andr(_out_womask_T_217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_217 = and(out_rivalid_1[95], out_rimask_217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_217 = and(out_roready_1[95], out_romask_217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_217 = and(out_wivalid_1[95], out_wimask_217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_217 = and(out_woready_1[95], out_womask_217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2483 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2484 = and(out_f_rivalid_217, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2485 = and(UInt<1>(0h1), out_f_roready_217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2486 = eq(out_rimask_217, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2487 = eq(out_wimask_217, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2488 = eq(out_romask_217, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2489 = eq(out_womask_217, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_177 = or(_out_T_2482, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_177 = cat(UInt<8>(0hf), _out_prepend_T_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2490 = or(out_prepend_177, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2491 = bits(_out_T_2490, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_218 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_218 = orr(_out_rimask_T_218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_218 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_218 = andr(_out_wimask_T_218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_218 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_218 = orr(_out_romask_T_218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_218 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_218 = andr(_out_womask_T_218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_218 = and(out_rivalid_1[96], out_rimask_218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_218 = and(out_roready_1[96], out_romask_218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_218 = and(out_wivalid_1[96], out_wimask_218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_218 = and(out_woready_1[96], out_womask_218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2492 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2493 = and(out_f_rivalid_218, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2494 = and(UInt<1>(0h1), out_f_roready_218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2495 = eq(out_rimask_218, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2496 = eq(out_wimask_218, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2497 = eq(out_romask_218, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2498 = eq(out_womask_218, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2499 = or(_T_890, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2500 = bits(_out_T_2499, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_219 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_219 = orr(_out_rimask_T_219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_219 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_219 = andr(_out_wimask_T_219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_219 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_219 = orr(_out_romask_T_219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_219 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_219 = andr(_out_womask_T_219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_219 = and(out_rivalid_1[97], out_rimask_219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_219 = and(out_roready_1[97], out_romask_219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_219 = and(out_wivalid_1[97], out_wimask_219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_219 = and(out_woready_1[97], out_womask_219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2501 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2502 = and(out_f_rivalid_219, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2503 = and(UInt<1>(0h1), out_f_roready_219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2504 = eq(out_rimask_219, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2505 = eq(out_wimask_219, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2506 = eq(out_romask_219, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2507 = eq(out_womask_219, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_178 = or(_out_T_2500, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_178 = cat(_T_891, _out_prepend_T_178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2508 = or(out_prepend_178, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2509 = bits(_out_T_2508, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_220 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_220 = orr(_out_rimask_T_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_220 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_220 = andr(_out_wimask_T_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_220 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_220 = orr(_out_romask_T_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_220 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_220 = andr(_out_womask_T_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_220 = and(out_rivalid_1[98], out_rimask_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_220 = and(out_roready_1[98], out_romask_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_220 = and(out_wivalid_1[98], out_wimask_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_220 = and(out_woready_1[98], out_womask_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2510 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2511 = and(out_f_rivalid_220, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2512 = and(UInt<1>(0h1), out_f_roready_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2513 = eq(out_rimask_220, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2514 = eq(out_wimask_220, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2515 = eq(out_romask_220, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2516 = eq(out_womask_220, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_179 = or(_out_T_2509, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_179 = cat(_T_892, _out_prepend_T_179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2517 = or(out_prepend_179, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2518 = bits(_out_T_2517, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_221 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_221 = orr(_out_rimask_T_221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_221 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_221 = andr(_out_wimask_T_221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_221 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_221 = orr(_out_romask_T_221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_221 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_221 = andr(_out_womask_T_221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_221 = and(out_rivalid_1[99], out_rimask_221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_221 = and(out_roready_1[99], out_romask_221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_221 = and(out_wivalid_1[99], out_wimask_221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_221 = and(out_woready_1[99], out_womask_221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2519 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2520 = and(out_f_rivalid_221, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2521 = and(UInt<1>(0h1), out_f_roready_221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2522 = eq(out_rimask_221, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2523 = eq(out_wimask_221, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2524 = eq(out_romask_221, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2525 = eq(out_womask_221, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_180 = or(_out_T_2518, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_180 = cat(_T_893, _out_prepend_T_180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2526 = or(out_prepend_180, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2527 = bits(_out_T_2526, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_222 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_222 = orr(_out_rimask_T_222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_222 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_222 = andr(_out_wimask_T_222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_222 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_222 = orr(_out_romask_T_222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_222 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_222 = andr(_out_womask_T_222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_222 = and(out_rivalid_1[100], out_rimask_222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_222 = and(out_roready_1[100], out_romask_222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_222 = and(out_wivalid_1[100], out_wimask_222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_222 = and(out_woready_1[100], out_womask_222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2528 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2529 = and(out_f_rivalid_222, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2530 = and(UInt<1>(0h1), out_f_roready_222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2531 = eq(out_rimask_222, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2532 = eq(out_wimask_222, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2533 = eq(out_romask_222, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2534 = eq(out_womask_222, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_181 = or(_out_T_2527, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_181 = cat(_T_894, _out_prepend_T_181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2535 = or(out_prepend_181, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2536 = bits(_out_T_2535, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_223 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_223 = orr(_out_rimask_T_223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_223 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_223 = andr(_out_wimask_T_223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_223 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_223 = orr(_out_romask_T_223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_223 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_223 = andr(_out_womask_T_223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_223 = and(out_rivalid_1[101], out_rimask_223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_223 = and(out_roready_1[101], out_romask_223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_223 = and(out_wivalid_1[101], out_wimask_223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_223 = and(out_woready_1[101], out_womask_223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2537 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2538 = and(out_f_rivalid_223, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2539 = and(UInt<1>(0h1), out_f_roready_223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2540 = eq(out_rimask_223, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2541 = eq(out_wimask_223, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2542 = eq(out_romask_223, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2543 = eq(out_womask_223, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_182 = or(_out_T_2536, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_182 = cat(_T_895, _out_prepend_T_182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2544 = or(out_prepend_182, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2545 = bits(_out_T_2544, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_224 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_224 = orr(_out_rimask_T_224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_224 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_224 = andr(_out_wimask_T_224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_224 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_224 = orr(_out_romask_T_224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_224 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_224 = andr(_out_womask_T_224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_224 = and(out_rivalid_1[102], out_rimask_224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_224 = and(out_roready_1[102], out_romask_224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_224 = and(out_wivalid_1[102], out_wimask_224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_224 = and(out_woready_1[102], out_womask_224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2546 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2547 = and(out_f_rivalid_224, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2548 = and(UInt<1>(0h1), out_f_roready_224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2549 = eq(out_rimask_224, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2550 = eq(out_wimask_224, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2551 = eq(out_romask_224, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2552 = eq(out_womask_224, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_183 = or(_out_T_2545, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_183 = cat(_T_896, _out_prepend_T_183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2553 = or(out_prepend_183, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2554 = bits(_out_T_2553, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_225 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_225 = orr(_out_rimask_T_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_225 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_225 = andr(_out_wimask_T_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_225 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_225 = orr(_out_romask_T_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_225 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_225 = andr(_out_womask_T_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_225 = and(out_rivalid_1[103], out_rimask_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_225 = and(out_roready_1[103], out_romask_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_225 = and(out_wivalid_1[103], out_wimask_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_225 = and(out_woready_1[103], out_womask_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2555 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2556 = and(out_f_rivalid_225, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2557 = and(UInt<1>(0h1), out_f_roready_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2558 = eq(out_rimask_225, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2559 = eq(out_wimask_225, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2560 = eq(out_romask_225, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2561 = eq(out_womask_225, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_184 = or(_out_T_2554, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_184 = cat(_T_897, _out_prepend_T_184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2562 = or(out_prepend_184, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2563 = bits(_out_T_2562, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_226 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_226 = orr(_out_rimask_T_226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_226 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_226 = andr(_out_wimask_T_226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_226 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_226 = orr(_out_romask_T_226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_226 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_226 = andr(_out_womask_T_226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_226 = and(out_rivalid_1[104], out_rimask_226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_226 = and(out_roready_1[104], out_romask_226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_226 = and(out_wivalid_1[104], out_wimask_226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_226 = and(out_woready_1[104], out_womask_226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2564 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_226 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[48], _out_T_2564 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_2565 = and(out_f_rivalid_226, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2566 = and(UInt<1>(0h1), out_f_roready_226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2567 = and(out_f_wivalid_226, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2568 = and(UInt<1>(0h1), out_f_woready_226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2569 = eq(out_rimask_226, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2570 = eq(out_wimask_226, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2571 = eq(out_romask_226, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2572 = eq(out_womask_226, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2573 = or(programBufferMem[48], UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2574 = bits(_out_T_2573, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_227 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_227 = orr(_out_rimask_T_227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_227 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_227 = andr(_out_wimask_T_227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_227 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_227 = orr(_out_romask_T_227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_227 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_227 = andr(_out_womask_T_227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_227 = and(out_rivalid_1[105], out_rimask_227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_227 = and(out_roready_1[105], out_romask_227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_227 = and(out_wivalid_1[105], out_wimask_227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_227 = and(out_woready_1[105], out_womask_227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2575 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_227 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[49], _out_T_2575 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_2576 = and(out_f_rivalid_227, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2577 = and(UInt<1>(0h1), out_f_roready_227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2578 = and(out_f_wivalid_227, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2579 = and(UInt<1>(0h1), out_f_woready_227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2580 = eq(out_rimask_227, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2581 = eq(out_wimask_227, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2582 = eq(out_romask_227, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2583 = eq(out_womask_227, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_185 = or(_out_T_2574, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_185 = cat(programBufferMem[49], _out_prepend_T_185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2584 = or(out_prepend_185, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2585 = bits(_out_T_2584, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_228 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_228 = orr(_out_rimask_T_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_228 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_228 = andr(_out_wimask_T_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_228 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_228 = orr(_out_romask_T_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_228 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_228 = andr(_out_womask_T_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_228 = and(out_rivalid_1[106], out_rimask_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_228 = and(out_roready_1[106], out_romask_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_228 = and(out_wivalid_1[106], out_wimask_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_228 = and(out_woready_1[106], out_womask_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2586 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_228 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[50], _out_T_2586 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_2587 = and(out_f_rivalid_228, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2588 = and(UInt<1>(0h1), out_f_roready_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2589 = and(out_f_wivalid_228, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2590 = and(UInt<1>(0h1), out_f_woready_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2591 = eq(out_rimask_228, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2592 = eq(out_wimask_228, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2593 = eq(out_romask_228, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2594 = eq(out_womask_228, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_186 = or(_out_T_2585, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_186 = cat(programBufferMem[50], _out_prepend_T_186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2595 = or(out_prepend_186, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2596 = bits(_out_T_2595, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_229 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_229 = orr(_out_rimask_T_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_229 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_229 = andr(_out_wimask_T_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_229 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_229 = orr(_out_romask_T_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_229 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_229 = andr(_out_womask_T_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_229 = and(out_rivalid_1[107], out_rimask_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_229 = and(out_roready_1[107], out_romask_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_229 = and(out_wivalid_1[107], out_wimask_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_229 = and(out_woready_1[107], out_womask_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2597 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_229 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[51], _out_T_2597 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_2598 = and(out_f_rivalid_229, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2599 = and(UInt<1>(0h1), out_f_roready_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2600 = and(out_f_wivalid_229, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2601 = and(UInt<1>(0h1), out_f_woready_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2602 = eq(out_rimask_229, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2603 = eq(out_wimask_229, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2604 = eq(out_romask_229, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2605 = eq(out_womask_229, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_187 = or(_out_T_2596, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_187 = cat(programBufferMem[51], _out_prepend_T_187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2606 = or(out_prepend_187, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2607 = bits(_out_T_2606, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_230 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_230 = orr(_out_rimask_T_230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_230 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_230 = andr(_out_wimask_T_230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_230 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_230 = orr(_out_romask_T_230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_230 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_230 = andr(_out_womask_T_230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_230 = and(out_rivalid_1[108], out_rimask_230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_230 = and(out_roready_1[108], out_romask_230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_230 = and(out_wivalid_1[108], out_wimask_230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_230 = and(out_woready_1[108], out_womask_230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2608 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_230 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[52], _out_T_2608 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_2609 = and(out_f_rivalid_230, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2610 = and(UInt<1>(0h1), out_f_roready_230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2611 = and(out_f_wivalid_230, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2612 = and(UInt<1>(0h1), out_f_woready_230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2613 = eq(out_rimask_230, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2614 = eq(out_wimask_230, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2615 = eq(out_romask_230, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2616 = eq(out_womask_230, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_188 = or(_out_T_2607, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_188 = cat(programBufferMem[52], _out_prepend_T_188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2617 = or(out_prepend_188, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2618 = bits(_out_T_2617, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_231 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_231 = orr(_out_rimask_T_231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_231 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_231 = andr(_out_wimask_T_231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_231 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_231 = orr(_out_romask_T_231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_231 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_231 = andr(_out_womask_T_231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_231 = and(out_rivalid_1[109], out_rimask_231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_231 = and(out_roready_1[109], out_romask_231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_231 = and(out_wivalid_1[109], out_wimask_231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_231 = and(out_woready_1[109], out_womask_231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2619 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_231 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[53], _out_T_2619 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_2620 = and(out_f_rivalid_231, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2621 = and(UInt<1>(0h1), out_f_roready_231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2622 = and(out_f_wivalid_231, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2623 = and(UInt<1>(0h1), out_f_woready_231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2624 = eq(out_rimask_231, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2625 = eq(out_wimask_231, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2626 = eq(out_romask_231, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2627 = eq(out_womask_231, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_189 = or(_out_T_2618, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_189 = cat(programBufferMem[53], _out_prepend_T_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2628 = or(out_prepend_189, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2629 = bits(_out_T_2628, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_232 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_232 = orr(_out_rimask_T_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_232 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_232 = andr(_out_wimask_T_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_232 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_232 = orr(_out_romask_T_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_232 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_232 = andr(_out_womask_T_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_232 = and(out_rivalid_1[110], out_rimask_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_232 = and(out_roready_1[110], out_romask_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_232 = and(out_wivalid_1[110], out_wimask_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_232 = and(out_woready_1[110], out_womask_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2630 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_232 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[54], _out_T_2630 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_2631 = and(out_f_rivalid_232, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2632 = and(UInt<1>(0h1), out_f_roready_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2633 = and(out_f_wivalid_232, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2634 = and(UInt<1>(0h1), out_f_woready_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2635 = eq(out_rimask_232, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2636 = eq(out_wimask_232, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2637 = eq(out_romask_232, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2638 = eq(out_womask_232, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_190 = or(_out_T_2629, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_190 = cat(programBufferMem[54], _out_prepend_T_190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2639 = or(out_prepend_190, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2640 = bits(_out_T_2639, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_233 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_233 = orr(_out_rimask_T_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_233 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_233 = andr(_out_wimask_T_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_233 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_233 = orr(_out_romask_T_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_233 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_233 = andr(_out_womask_T_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_233 = and(out_rivalid_1[111], out_rimask_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_233 = and(out_roready_1[111], out_romask_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_233 = and(out_wivalid_1[111], out_wimask_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_233 = and(out_woready_1[111], out_womask_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2641 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_233 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[55], _out_T_2641 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_2642 = and(out_f_rivalid_233, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2643 = and(UInt<1>(0h1), out_f_roready_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2644 = and(out_f_wivalid_233, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2645 = and(UInt<1>(0h1), out_f_woready_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2646 = eq(out_rimask_233, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2647 = eq(out_wimask_233, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2648 = eq(out_romask_233, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2649 = eq(out_womask_233, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_191 = or(_out_T_2640, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_191 = cat(programBufferMem[55], _out_prepend_T_191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2650 = or(out_prepend_191, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2651 = bits(_out_T_2650, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_234 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_234 = orr(_out_rimask_T_234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_234 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_234 = andr(_out_wimask_T_234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_234 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_234 = orr(_out_romask_T_234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_234 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_234 = andr(_out_womask_T_234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_234 = and(out_rivalid_1[112], out_rimask_234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_234 = and(out_roready_1[112], out_romask_234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_234 = and(out_wivalid_1[112], out_wimask_234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_234 = and(out_woready_1[112], out_womask_234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2652 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2653 = and(out_f_rivalid_234, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2654 = and(UInt<1>(0h1), out_f_roready_234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2655 = eq(out_rimask_234, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2656 = eq(out_wimask_234, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2657 = eq(out_romask_234, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2658 = eq(out_womask_234, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2659 = or(_T_986, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2660 = bits(_out_T_2659, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_235 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_235 = orr(_out_rimask_T_235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_235 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_235 = andr(_out_wimask_T_235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_235 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_235 = orr(_out_romask_T_235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_235 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_235 = andr(_out_womask_T_235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_235 = and(out_rivalid_1[113], out_rimask_235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_235 = and(out_roready_1[113], out_romask_235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_235 = and(out_wivalid_1[113], out_wimask_235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_235 = and(out_woready_1[113], out_womask_235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2661 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2662 = and(out_f_rivalid_235, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2663 = and(UInt<1>(0h1), out_f_roready_235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2664 = eq(out_rimask_235, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2665 = eq(out_wimask_235, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2666 = eq(out_romask_235, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2667 = eq(out_womask_235, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_192 = or(_out_T_2660, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_192 = cat(_T_987, _out_prepend_T_192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2668 = or(out_prepend_192, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2669 = bits(_out_T_2668, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_236 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_236 = orr(_out_rimask_T_236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_236 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_236 = andr(_out_wimask_T_236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_236 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_236 = orr(_out_romask_T_236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_236 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_236 = andr(_out_womask_T_236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_236 = and(out_rivalid_1[114], out_rimask_236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_236 = and(out_roready_1[114], out_romask_236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_236 = and(out_wivalid_1[114], out_wimask_236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_236 = and(out_woready_1[114], out_womask_236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2670 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2671 = and(out_f_rivalid_236, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2672 = and(UInt<1>(0h1), out_f_roready_236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2673 = eq(out_rimask_236, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2674 = eq(out_wimask_236, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2675 = eq(out_romask_236, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2676 = eq(out_womask_236, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_193 = or(_out_T_2669, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_193 = cat(_T_988, _out_prepend_T_193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2677 = or(out_prepend_193, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2678 = bits(_out_T_2677, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_237 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_237 = orr(_out_rimask_T_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_237 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_237 = andr(_out_wimask_T_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_237 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_237 = orr(_out_romask_T_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_237 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_237 = andr(_out_womask_T_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_237 = and(out_rivalid_1[115], out_rimask_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_237 = and(out_roready_1[115], out_romask_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_237 = and(out_wivalid_1[115], out_wimask_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_237 = and(out_woready_1[115], out_womask_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2679 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2680 = and(out_f_rivalid_237, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2681 = and(UInt<1>(0h1), out_f_roready_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2682 = eq(out_rimask_237, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2683 = eq(out_wimask_237, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2684 = eq(out_romask_237, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2685 = eq(out_womask_237, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_194 = or(_out_T_2678, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_194 = cat(_T_989, _out_prepend_T_194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2686 = or(out_prepend_194, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2687 = bits(_out_T_2686, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_238 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_238 = orr(_out_rimask_T_238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_238 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_238 = andr(_out_wimask_T_238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_238 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_238 = orr(_out_romask_T_238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_238 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_238 = andr(_out_womask_T_238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_238 = and(out_rivalid_1[116], out_rimask_238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_238 = and(out_roready_1[116], out_romask_238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_238 = and(out_wivalid_1[116], out_wimask_238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_238 = and(out_woready_1[116], out_womask_238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2688 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2689 = and(out_f_rivalid_238, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2690 = and(UInt<1>(0h1), out_f_roready_238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2691 = eq(out_rimask_238, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2692 = eq(out_wimask_238, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2693 = eq(out_romask_238, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2694 = eq(out_womask_238, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_195 = or(_out_T_2687, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_195 = cat(_T_990, _out_prepend_T_195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2695 = or(out_prepend_195, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2696 = bits(_out_T_2695, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_239 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_239 = orr(_out_rimask_T_239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_239 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_239 = andr(_out_wimask_T_239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_239 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_239 = orr(_out_romask_T_239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_239 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_239 = andr(_out_womask_T_239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_239 = and(out_rivalid_1[117], out_rimask_239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_239 = and(out_roready_1[117], out_romask_239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_239 = and(out_wivalid_1[117], out_wimask_239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_239 = and(out_woready_1[117], out_womask_239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2697 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2698 = and(out_f_rivalid_239, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2699 = and(UInt<1>(0h1), out_f_roready_239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2700 = eq(out_rimask_239, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2701 = eq(out_wimask_239, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2702 = eq(out_romask_239, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2703 = eq(out_womask_239, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_196 = or(_out_T_2696, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_196 = cat(_T_991, _out_prepend_T_196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2704 = or(out_prepend_196, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2705 = bits(_out_T_2704, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_240 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_240 = orr(_out_rimask_T_240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_240 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_240 = andr(_out_wimask_T_240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_240 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_240 = orr(_out_romask_T_240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_240 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_240 = andr(_out_womask_T_240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_240 = and(out_rivalid_1[118], out_rimask_240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_240 = and(out_roready_1[118], out_romask_240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_240 = and(out_wivalid_1[118], out_wimask_240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_240 = and(out_woready_1[118], out_womask_240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2706 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2707 = and(out_f_rivalid_240, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2708 = and(UInt<1>(0h1), out_f_roready_240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2709 = eq(out_rimask_240, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2710 = eq(out_wimask_240, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2711 = eq(out_romask_240, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2712 = eq(out_womask_240, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_197 = or(_out_T_2705, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_197 = cat(_T_992, _out_prepend_T_197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2713 = or(out_prepend_197, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2714 = bits(_out_T_2713, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_241 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_241 = orr(_out_rimask_T_241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_241 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_241 = andr(_out_wimask_T_241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_241 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_241 = orr(_out_romask_T_241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_241 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_241 = andr(_out_womask_T_241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_241 = and(out_rivalid_1[119], out_rimask_241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_241 = and(out_roready_1[119], out_romask_241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_241 = and(out_wivalid_1[119], out_wimask_241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_241 = and(out_woready_1[119], out_womask_241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2715 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2716 = and(out_f_rivalid_241, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2717 = and(UInt<1>(0h1), out_f_roready_241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2718 = eq(out_rimask_241, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2719 = eq(out_wimask_241, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2720 = eq(out_romask_241, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2721 = eq(out_womask_241, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_198 = or(_out_T_2714, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_198 = cat(_T_993, _out_prepend_T_198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2722 = or(out_prepend_198, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2723 = bits(_out_T_2722, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_242 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_242 = orr(_out_rimask_T_242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_242 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_242 = andr(_out_wimask_T_242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_242 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_242 = orr(_out_romask_T_242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_242 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_242 = andr(_out_womask_T_242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_242 = and(out_rivalid_1[120], out_rimask_242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_242 = and(out_roready_1[120], out_romask_242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_242 = and(out_wivalid_1[120], out_wimask_242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_242 = and(out_woready_1[120], out_womask_242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2724 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2725 = and(out_f_rivalid_242, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2726 = and(UInt<1>(0h1), out_f_roready_242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2727 = eq(out_rimask_242, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2728 = eq(out_wimask_242, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2729 = eq(out_romask_242, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2730 = eq(out_womask_242, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2731 = or(_T_674, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2732 = bits(_out_T_2731, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_243 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_243 = orr(_out_rimask_T_243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_243 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_243 = andr(_out_wimask_T_243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_243 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_243 = orr(_out_romask_T_243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_243 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_243 = andr(_out_womask_T_243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_243 = and(out_rivalid_1[121], out_rimask_243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_243 = and(out_roready_1[121], out_romask_243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_243 = and(out_wivalid_1[121], out_wimask_243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_243 = and(out_woready_1[121], out_womask_243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2733 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2734 = and(out_f_rivalid_243, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2735 = and(UInt<1>(0h1), out_f_roready_243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2736 = eq(out_rimask_243, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2737 = eq(out_wimask_243, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2738 = eq(out_romask_243, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2739 = eq(out_womask_243, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_199 = or(_out_T_2732, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_199 = cat(_T_675, _out_prepend_T_199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2740 = or(out_prepend_199, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2741 = bits(_out_T_2740, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_244 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_244 = orr(_out_rimask_T_244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_244 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_244 = andr(_out_wimask_T_244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_244 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_244 = orr(_out_romask_T_244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_244 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_244 = andr(_out_womask_T_244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_244 = and(out_rivalid_1[122], out_rimask_244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_244 = and(out_roready_1[122], out_romask_244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_244 = and(out_wivalid_1[122], out_wimask_244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_244 = and(out_woready_1[122], out_womask_244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2742 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2743 = and(out_f_rivalid_244, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2744 = and(UInt<1>(0h1), out_f_roready_244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2745 = eq(out_rimask_244, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2746 = eq(out_wimask_244, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2747 = eq(out_romask_244, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2748 = eq(out_womask_244, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_200 = or(_out_T_2741, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_200 = cat(_T_676, _out_prepend_T_200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2749 = or(out_prepend_200, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2750 = bits(_out_T_2749, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_245 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_245 = orr(_out_rimask_T_245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_245 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_245 = andr(_out_wimask_T_245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_245 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_245 = orr(_out_romask_T_245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_245 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_245 = andr(_out_womask_T_245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_245 = and(out_rivalid_1[123], out_rimask_245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_245 = and(out_roready_1[123], out_romask_245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_245 = and(out_wivalid_1[123], out_wimask_245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_245 = and(out_woready_1[123], out_womask_245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2751 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2752 = and(out_f_rivalid_245, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2753 = and(UInt<1>(0h1), out_f_roready_245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2754 = eq(out_rimask_245, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2755 = eq(out_wimask_245, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2756 = eq(out_romask_245, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2757 = eq(out_womask_245, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_201 = or(_out_T_2750, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_201 = cat(_T_677, _out_prepend_T_201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2758 = or(out_prepend_201, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2759 = bits(_out_T_2758, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_246 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_246 = orr(_out_rimask_T_246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_246 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_246 = andr(_out_wimask_T_246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_246 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_246 = orr(_out_romask_T_246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_246 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_246 = andr(_out_womask_T_246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_246 = and(out_rivalid_1[124], out_rimask_246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_246 = and(out_roready_1[124], out_romask_246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_246 = and(out_wivalid_1[124], out_wimask_246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_246 = and(out_woready_1[124], out_womask_246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2760 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2761 = and(out_f_rivalid_246, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2762 = and(UInt<1>(0h1), out_f_roready_246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2763 = eq(out_rimask_246, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2764 = eq(out_wimask_246, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2765 = eq(out_romask_246, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2766 = eq(out_womask_246, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_202 = or(_out_T_2759, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_202 = cat(_T_678, _out_prepend_T_202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2767 = or(out_prepend_202, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2768 = bits(_out_T_2767, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_247 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_247 = orr(_out_rimask_T_247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_247 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_247 = andr(_out_wimask_T_247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_247 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_247 = orr(_out_romask_T_247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_247 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_247 = andr(_out_womask_T_247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_247 = and(out_rivalid_1[125], out_rimask_247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_247 = and(out_roready_1[125], out_romask_247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_247 = and(out_wivalid_1[125], out_wimask_247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_247 = and(out_woready_1[125], out_womask_247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2769 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2770 = and(out_f_rivalid_247, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2771 = and(UInt<1>(0h1), out_f_roready_247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2772 = eq(out_rimask_247, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2773 = eq(out_wimask_247, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2774 = eq(out_romask_247, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2775 = eq(out_womask_247, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_203 = or(_out_T_2768, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_203 = cat(_T_679, _out_prepend_T_203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2776 = or(out_prepend_203, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2777 = bits(_out_T_2776, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_248 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_248 = orr(_out_rimask_T_248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_248 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_248 = andr(_out_wimask_T_248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_248 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_248 = orr(_out_romask_T_248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_248 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_248 = andr(_out_womask_T_248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_248 = and(out_rivalid_1[126], out_rimask_248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_248 = and(out_roready_1[126], out_romask_248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_248 = and(out_wivalid_1[126], out_wimask_248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_248 = and(out_woready_1[126], out_womask_248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2778 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2779 = and(out_f_rivalid_248, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2780 = and(UInt<1>(0h1), out_f_roready_248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2781 = eq(out_rimask_248, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2782 = eq(out_wimask_248, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2783 = eq(out_romask_248, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2784 = eq(out_womask_248, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_204 = or(_out_T_2777, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_204 = cat(_T_680, _out_prepend_T_204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2785 = or(out_prepend_204, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2786 = bits(_out_T_2785, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_249 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_249 = orr(_out_rimask_T_249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_249 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_249 = andr(_out_wimask_T_249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_249 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_249 = orr(_out_romask_T_249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_249 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_249 = andr(_out_womask_T_249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_249 = and(out_rivalid_1[127], out_rimask_249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_249 = and(out_roready_1[127], out_romask_249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_249 = and(out_wivalid_1[127], out_wimask_249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_249 = and(out_woready_1[127], out_womask_249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2787 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2788 = and(out_f_rivalid_249, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2789 = and(UInt<1>(0h1), out_f_roready_249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2790 = eq(out_rimask_249, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2791 = eq(out_wimask_249, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2792 = eq(out_romask_249, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2793 = eq(out_womask_249, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_205 = or(_out_T_2786, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_205 = cat(_T_681, _out_prepend_T_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2794 = or(out_prepend_205, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2795 = bits(_out_T_2794, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_250 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_250 = orr(_out_rimask_T_250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_250 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_250 = andr(_out_wimask_T_250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_250 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_250 = orr(_out_romask_T_250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_250 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_250 = andr(_out_womask_T_250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_250 = and(out_rivalid_1[128], out_rimask_250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_250 = and(out_roready_1[128], out_romask_250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_250 = and(out_wivalid_1[128], out_wimask_250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_250 = and(out_woready_1[128], out_womask_250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2796 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2797 = and(out_f_rivalid_250, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2798 = and(UInt<1>(0h1), out_f_roready_250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2799 = eq(out_rimask_250, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2800 = eq(out_wimask_250, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2801 = eq(out_romask_250, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2802 = eq(out_womask_250, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2803 = or(_T_930, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2804 = bits(_out_T_2803, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_251 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_251 = orr(_out_rimask_T_251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_251 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_251 = andr(_out_wimask_T_251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_251 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_251 = orr(_out_romask_T_251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_251 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_251 = andr(_out_womask_T_251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_251 = and(out_rivalid_1[129], out_rimask_251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_251 = and(out_roready_1[129], out_romask_251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_251 = and(out_wivalid_1[129], out_wimask_251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_251 = and(out_woready_1[129], out_womask_251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2805 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2806 = and(out_f_rivalid_251, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2807 = and(UInt<1>(0h1), out_f_roready_251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2808 = eq(out_rimask_251, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2809 = eq(out_wimask_251, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2810 = eq(out_romask_251, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2811 = eq(out_womask_251, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_206 = or(_out_T_2804, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_206 = cat(_T_931, _out_prepend_T_206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2812 = or(out_prepend_206, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2813 = bits(_out_T_2812, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_252 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_252 = orr(_out_rimask_T_252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_252 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_252 = andr(_out_wimask_T_252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_252 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_252 = orr(_out_romask_T_252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_252 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_252 = andr(_out_womask_T_252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_252 = and(out_rivalid_1[130], out_rimask_252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_252 = and(out_roready_1[130], out_romask_252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_252 = and(out_wivalid_1[130], out_wimask_252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_252 = and(out_woready_1[130], out_womask_252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2814 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2815 = and(out_f_rivalid_252, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2816 = and(UInt<1>(0h1), out_f_roready_252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2817 = eq(out_rimask_252, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2818 = eq(out_wimask_252, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2819 = eq(out_romask_252, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2820 = eq(out_womask_252, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_207 = or(_out_T_2813, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_207 = cat(_T_932, _out_prepend_T_207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2821 = or(out_prepend_207, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2822 = bits(_out_T_2821, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_253 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_253 = orr(_out_rimask_T_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_253 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_253 = andr(_out_wimask_T_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_253 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_253 = orr(_out_romask_T_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_253 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_253 = andr(_out_womask_T_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_253 = and(out_rivalid_1[131], out_rimask_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_253 = and(out_roready_1[131], out_romask_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_253 = and(out_wivalid_1[131], out_wimask_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_253 = and(out_woready_1[131], out_womask_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2823 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2824 = and(out_f_rivalid_253, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2825 = and(UInt<1>(0h1), out_f_roready_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2826 = eq(out_rimask_253, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2827 = eq(out_wimask_253, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2828 = eq(out_romask_253, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2829 = eq(out_womask_253, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_208 = or(_out_T_2822, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_208 = cat(_T_933, _out_prepend_T_208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2830 = or(out_prepend_208, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2831 = bits(_out_T_2830, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_254 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_254 = orr(_out_rimask_T_254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_254 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_254 = andr(_out_wimask_T_254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_254 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_254 = orr(_out_romask_T_254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_254 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_254 = andr(_out_womask_T_254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_254 = and(out_rivalid_1[132], out_rimask_254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_254 = and(out_roready_1[132], out_romask_254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_254 = and(out_wivalid_1[132], out_wimask_254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_254 = and(out_woready_1[132], out_womask_254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2832 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2833 = and(out_f_rivalid_254, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2834 = and(UInt<1>(0h1), out_f_roready_254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2835 = eq(out_rimask_254, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2836 = eq(out_wimask_254, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2837 = eq(out_romask_254, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2838 = eq(out_womask_254, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_209 = or(_out_T_2831, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_209 = cat(_T_934, _out_prepend_T_209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2839 = or(out_prepend_209, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2840 = bits(_out_T_2839, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_255 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_255 = orr(_out_rimask_T_255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_255 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_255 = andr(_out_wimask_T_255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_255 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_255 = orr(_out_romask_T_255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_255 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_255 = andr(_out_womask_T_255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_255 = and(out_rivalid_1[133], out_rimask_255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_255 = and(out_roready_1[133], out_romask_255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_255 = and(out_wivalid_1[133], out_wimask_255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_255 = and(out_woready_1[133], out_womask_255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2841 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2842 = and(out_f_rivalid_255, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2843 = and(UInt<1>(0h1), out_f_roready_255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2844 = eq(out_rimask_255, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2845 = eq(out_wimask_255, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2846 = eq(out_romask_255, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2847 = eq(out_womask_255, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_210 = or(_out_T_2840, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_210 = cat(_T_935, _out_prepend_T_210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2848 = or(out_prepend_210, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2849 = bits(_out_T_2848, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_256 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_256 = orr(_out_rimask_T_256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_256 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_256 = andr(_out_wimask_T_256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_256 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_256 = orr(_out_romask_T_256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_256 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_256 = andr(_out_womask_T_256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_256 = and(out_rivalid_1[134], out_rimask_256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_256 = and(out_roready_1[134], out_romask_256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_256 = and(out_wivalid_1[134], out_wimask_256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_256 = and(out_woready_1[134], out_womask_256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2850 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2851 = and(out_f_rivalid_256, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2852 = and(UInt<1>(0h1), out_f_roready_256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2853 = eq(out_rimask_256, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2854 = eq(out_wimask_256, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2855 = eq(out_romask_256, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2856 = eq(out_womask_256, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_211 = or(_out_T_2849, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_211 = cat(_T_936, _out_prepend_T_211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2857 = or(out_prepend_211, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2858 = bits(_out_T_2857, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_257 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_257 = orr(_out_rimask_T_257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_257 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_257 = andr(_out_wimask_T_257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_257 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_257 = orr(_out_romask_T_257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_257 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_257 = andr(_out_womask_T_257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_257 = and(out_rivalid_1[135], out_rimask_257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_257 = and(out_roready_1[135], out_romask_257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_257 = and(out_wivalid_1[135], out_wimask_257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_257 = and(out_woready_1[135], out_womask_257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2859 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2860 = and(out_f_rivalid_257, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2861 = and(UInt<1>(0h1), out_f_roready_257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2862 = eq(out_rimask_257, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2863 = eq(out_wimask_257, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2864 = eq(out_romask_257, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2865 = eq(out_womask_257, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_212 = or(_out_T_2858, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_212 = cat(_T_937, _out_prepend_T_212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2866 = or(out_prepend_212, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2867 = bits(_out_T_2866, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_258 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_258 = orr(_out_rimask_T_258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_258 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_258 = andr(_out_wimask_T_258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_258 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_258 = orr(_out_romask_T_258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_258 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_258 = andr(_out_womask_T_258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_258 = and(out_rivalid_1[136], out_rimask_258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_258 = and(out_roready_1[136], out_romask_258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_258 = and(out_wivalid_1[136], out_wimask_258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_258 = and(out_woready_1[136], out_womask_258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2868 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2869 = and(out_f_rivalid_258, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2870 = and(UInt<1>(0h1), out_f_roready_258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2871 = eq(out_rimask_258, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2872 = eq(out_wimask_258, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2873 = eq(out_romask_258, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2874 = eq(out_womask_258, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2875 = or(_T_634, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2876 = bits(_out_T_2875, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_259 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_259 = orr(_out_rimask_T_259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_259 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_259 = andr(_out_wimask_T_259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_259 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_259 = orr(_out_romask_T_259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_259 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_259 = andr(_out_womask_T_259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_259 = and(out_rivalid_1[137], out_rimask_259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_259 = and(out_roready_1[137], out_romask_259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_259 = and(out_wivalid_1[137], out_wimask_259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_259 = and(out_woready_1[137], out_womask_259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2877 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2878 = and(out_f_rivalid_259, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2879 = and(UInt<1>(0h1), out_f_roready_259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2880 = eq(out_rimask_259, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2881 = eq(out_wimask_259, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2882 = eq(out_romask_259, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2883 = eq(out_womask_259, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_213 = or(_out_T_2876, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_213 = cat(_T_635, _out_prepend_T_213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2884 = or(out_prepend_213, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2885 = bits(_out_T_2884, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_260 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_260 = orr(_out_rimask_T_260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_260 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_260 = andr(_out_wimask_T_260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_260 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_260 = orr(_out_romask_T_260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_260 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_260 = andr(_out_womask_T_260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_260 = and(out_rivalid_1[138], out_rimask_260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_260 = and(out_roready_1[138], out_romask_260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_260 = and(out_wivalid_1[138], out_wimask_260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_260 = and(out_woready_1[138], out_womask_260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2886 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2887 = and(out_f_rivalid_260, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2888 = and(UInt<1>(0h1), out_f_roready_260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2889 = eq(out_rimask_260, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2890 = eq(out_wimask_260, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2891 = eq(out_romask_260, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2892 = eq(out_womask_260, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_214 = or(_out_T_2885, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_214 = cat(_T_636, _out_prepend_T_214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2893 = or(out_prepend_214, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2894 = bits(_out_T_2893, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_261 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_261 = orr(_out_rimask_T_261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_261 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_261 = andr(_out_wimask_T_261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_261 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_261 = orr(_out_romask_T_261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_261 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_261 = andr(_out_womask_T_261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_261 = and(out_rivalid_1[139], out_rimask_261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_261 = and(out_roready_1[139], out_romask_261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_261 = and(out_wivalid_1[139], out_wimask_261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_261 = and(out_woready_1[139], out_womask_261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2895 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2896 = and(out_f_rivalid_261, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2897 = and(UInt<1>(0h1), out_f_roready_261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2898 = eq(out_rimask_261, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2899 = eq(out_wimask_261, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2900 = eq(out_romask_261, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2901 = eq(out_womask_261, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_215 = or(_out_T_2894, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_215 = cat(_T_637, _out_prepend_T_215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2902 = or(out_prepend_215, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2903 = bits(_out_T_2902, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_262 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_262 = orr(_out_rimask_T_262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_262 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_262 = andr(_out_wimask_T_262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_262 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_262 = orr(_out_romask_T_262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_262 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_262 = andr(_out_womask_T_262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_262 = and(out_rivalid_1[140], out_rimask_262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_262 = and(out_roready_1[140], out_romask_262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_262 = and(out_wivalid_1[140], out_wimask_262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_262 = and(out_woready_1[140], out_womask_262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2904 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2905 = and(out_f_rivalid_262, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2906 = and(UInt<1>(0h1), out_f_roready_262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2907 = eq(out_rimask_262, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2908 = eq(out_wimask_262, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2909 = eq(out_romask_262, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2910 = eq(out_womask_262, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_216 = or(_out_T_2903, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_216 = cat(_T_638, _out_prepend_T_216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2911 = or(out_prepend_216, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2912 = bits(_out_T_2911, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_263 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_263 = orr(_out_rimask_T_263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_263 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_263 = andr(_out_wimask_T_263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_263 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_263 = orr(_out_romask_T_263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_263 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_263 = andr(_out_womask_T_263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_263 = and(out_rivalid_1[141], out_rimask_263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_263 = and(out_roready_1[141], out_romask_263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_263 = and(out_wivalid_1[141], out_wimask_263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_263 = and(out_woready_1[141], out_womask_263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2913 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2914 = and(out_f_rivalid_263, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2915 = and(UInt<1>(0h1), out_f_roready_263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2916 = eq(out_rimask_263, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2917 = eq(out_wimask_263, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2918 = eq(out_romask_263, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2919 = eq(out_womask_263, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_217 = or(_out_T_2912, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_217 = cat(_T_639, _out_prepend_T_217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2920 = or(out_prepend_217, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2921 = bits(_out_T_2920, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_264 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_264 = orr(_out_rimask_T_264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_264 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_264 = andr(_out_wimask_T_264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_264 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_264 = orr(_out_romask_T_264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_264 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_264 = andr(_out_womask_T_264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_264 = and(out_rivalid_1[142], out_rimask_264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_264 = and(out_roready_1[142], out_romask_264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_264 = and(out_wivalid_1[142], out_wimask_264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_264 = and(out_woready_1[142], out_womask_264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2922 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2923 = and(out_f_rivalid_264, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2924 = and(UInt<1>(0h1), out_f_roready_264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2925 = eq(out_rimask_264, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2926 = eq(out_wimask_264, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2927 = eq(out_romask_264, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2928 = eq(out_womask_264, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_218 = or(_out_T_2921, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_218 = cat(_T_640, _out_prepend_T_218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2929 = or(out_prepend_218, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2930 = bits(_out_T_2929, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_265 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_265 = orr(_out_rimask_T_265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_265 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_265 = andr(_out_wimask_T_265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_265 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_265 = orr(_out_romask_T_265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_265 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_265 = andr(_out_womask_T_265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_265 = and(out_rivalid_1[143], out_rimask_265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_265 = and(out_roready_1[143], out_romask_265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_265 = and(out_wivalid_1[143], out_wimask_265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_265 = and(out_woready_1[143], out_womask_265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2931 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2932 = and(out_f_rivalid_265, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2933 = and(UInt<1>(0h1), out_f_roready_265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2934 = eq(out_rimask_265, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2935 = eq(out_wimask_265, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2936 = eq(out_romask_265, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2937 = eq(out_womask_265, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_219 = or(_out_T_2930, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_219 = cat(_T_641, _out_prepend_T_219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2938 = or(out_prepend_219, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2939 = bits(_out_T_2938, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_266 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_266 = orr(_out_rimask_T_266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_266 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_266 = andr(_out_wimask_T_266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_266 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_266 = orr(_out_romask_T_266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_266 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_266 = andr(_out_womask_T_266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_266 = and(out_rivalid_1[144], out_rimask_266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_266 = and(out_roready_1[144], out_romask_266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_266 = and(out_wivalid_1[144], out_wimask_266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_266 = and(out_woready_1[144], out_womask_266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2940 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2941 = and(out_f_rivalid_266, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2942 = and(UInt<1>(0h1), out_f_roready_266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2943 = eq(out_rimask_266, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2944 = eq(out_wimask_266, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2945 = eq(out_romask_266, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2946 = eq(out_womask_266, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2947 = or(_T_1242, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2948 = bits(_out_T_2947, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_267 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_267 = orr(_out_rimask_T_267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_267 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_267 = andr(_out_wimask_T_267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_267 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_267 = orr(_out_romask_T_267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_267 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_267 = andr(_out_womask_T_267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_267 = and(out_rivalid_1[145], out_rimask_267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_267 = and(out_roready_1[145], out_romask_267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_267 = and(out_wivalid_1[145], out_wimask_267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_267 = and(out_woready_1[145], out_womask_267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2949 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2950 = and(out_f_rivalid_267, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2951 = and(UInt<1>(0h1), out_f_roready_267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2952 = eq(out_rimask_267, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2953 = eq(out_wimask_267, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2954 = eq(out_romask_267, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2955 = eq(out_womask_267, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_220 = or(_out_T_2948, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_220 = cat(_T_1243, _out_prepend_T_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2956 = or(out_prepend_220, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2957 = bits(_out_T_2956, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_268 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_268 = orr(_out_rimask_T_268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_268 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_268 = andr(_out_wimask_T_268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_268 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_268 = orr(_out_romask_T_268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_268 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_268 = andr(_out_womask_T_268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_268 = and(out_rivalid_1[146], out_rimask_268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_268 = and(out_roready_1[146], out_romask_268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_268 = and(out_wivalid_1[146], out_wimask_268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_268 = and(out_woready_1[146], out_womask_268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2958 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2959 = and(out_f_rivalid_268, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2960 = and(UInt<1>(0h1), out_f_roready_268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2961 = eq(out_rimask_268, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2962 = eq(out_wimask_268, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2963 = eq(out_romask_268, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2964 = eq(out_womask_268, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_221 = or(_out_T_2957, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_221 = cat(_T_1244, _out_prepend_T_221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2965 = or(out_prepend_221, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2966 = bits(_out_T_2965, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_269 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_269 = orr(_out_rimask_T_269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_269 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_269 = andr(_out_wimask_T_269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_269 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_269 = orr(_out_romask_T_269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_269 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_269 = andr(_out_womask_T_269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_269 = and(out_rivalid_1[147], out_rimask_269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_269 = and(out_roready_1[147], out_romask_269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_269 = and(out_wivalid_1[147], out_wimask_269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_269 = and(out_woready_1[147], out_womask_269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2967 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2968 = and(out_f_rivalid_269, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2969 = and(UInt<1>(0h1), out_f_roready_269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2970 = eq(out_rimask_269, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2971 = eq(out_wimask_269, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2972 = eq(out_romask_269, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2973 = eq(out_womask_269, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_222 = or(_out_T_2966, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_222 = cat(_T_1245, _out_prepend_T_222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2974 = or(out_prepend_222, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2975 = bits(_out_T_2974, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_270 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_270 = orr(_out_rimask_T_270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_270 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_270 = andr(_out_wimask_T_270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_270 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_270 = orr(_out_romask_T_270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_270 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_270 = andr(_out_womask_T_270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_270 = and(out_rivalid_1[148], out_rimask_270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_270 = and(out_roready_1[148], out_romask_270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_270 = and(out_wivalid_1[148], out_wimask_270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_270 = and(out_woready_1[148], out_womask_270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2976 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2977 = and(out_f_rivalid_270, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2978 = and(UInt<1>(0h1), out_f_roready_270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2979 = eq(out_rimask_270, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2980 = eq(out_wimask_270, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2981 = eq(out_romask_270, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2982 = eq(out_womask_270, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_223 = or(_out_T_2975, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_223 = cat(_T_1246, _out_prepend_T_223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2983 = or(out_prepend_223, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2984 = bits(_out_T_2983, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_271 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_271 = orr(_out_rimask_T_271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_271 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_271 = andr(_out_wimask_T_271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_271 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_271 = orr(_out_romask_T_271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_271 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_271 = andr(_out_womask_T_271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_271 = and(out_rivalid_1[149], out_rimask_271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_271 = and(out_roready_1[149], out_romask_271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_271 = and(out_wivalid_1[149], out_wimask_271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_271 = and(out_woready_1[149], out_womask_271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2985 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2986 = and(out_f_rivalid_271, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2987 = and(UInt<1>(0h1), out_f_roready_271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2988 = eq(out_rimask_271, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2989 = eq(out_wimask_271, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2990 = eq(out_romask_271, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2991 = eq(out_womask_271, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_224 = or(_out_T_2984, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_224 = cat(_T_1247, _out_prepend_T_224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2992 = or(out_prepend_224, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2993 = bits(_out_T_2992, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_272 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_272 = orr(_out_rimask_T_272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_272 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_272 = andr(_out_wimask_T_272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_272 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_272 = orr(_out_romask_T_272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_272 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_272 = andr(_out_womask_T_272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_272 = and(out_rivalid_1[150], out_rimask_272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_272 = and(out_roready_1[150], out_romask_272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_272 = and(out_wivalid_1[150], out_wimask_272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_272 = and(out_woready_1[150], out_womask_272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2994 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2995 = and(out_f_rivalid_272, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2996 = and(UInt<1>(0h1), out_f_roready_272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2997 = eq(out_rimask_272, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2998 = eq(out_wimask_272, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2999 = eq(out_romask_272, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3000 = eq(out_womask_272, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_225 = or(_out_T_2993, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_225 = cat(_T_1248, _out_prepend_T_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3001 = or(out_prepend_225, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3002 = bits(_out_T_3001, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_273 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_273 = orr(_out_rimask_T_273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_273 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_273 = andr(_out_wimask_T_273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_273 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_273 = orr(_out_romask_T_273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_273 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_273 = andr(_out_womask_T_273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_273 = and(out_rivalid_1[151], out_rimask_273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_273 = and(out_roready_1[151], out_romask_273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_273 = and(out_wivalid_1[151], out_wimask_273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_273 = and(out_woready_1[151], out_womask_273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3003 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3004 = and(out_f_rivalid_273, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3005 = and(UInt<1>(0h1), out_f_roready_273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3006 = eq(out_rimask_273, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3007 = eq(out_wimask_273, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3008 = eq(out_romask_273, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3009 = eq(out_womask_273, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_226 = or(_out_T_3002, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_226 = cat(_T_1249, _out_prepend_T_226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3010 = or(out_prepend_226, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3011 = bits(_out_T_3010, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_274 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_274 = orr(_out_rimask_T_274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_274 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_274 = andr(_out_wimask_T_274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_274 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_274 = orr(_out_romask_T_274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_274 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_274 = andr(_out_womask_T_274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_274 = and(out_rivalid_1[152], out_rimask_274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_274 = and(out_roready_1[152], out_romask_274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_274 = and(out_wivalid_1[152], out_wimask_274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_274 = and(out_woready_1[152], out_womask_274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3012 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3013 = and(out_f_rivalid_274, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3014 = and(UInt<1>(0h1), out_f_roready_274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3015 = eq(out_rimask_274, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3016 = eq(out_wimask_274, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3017 = eq(out_romask_274, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3018 = eq(out_womask_274, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3019 = or(UInt<8>(0h13), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3020 = bits(_out_T_3019, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_275 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_275 = orr(_out_rimask_T_275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_275 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_275 = andr(_out_wimask_T_275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_275 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_275 = orr(_out_romask_T_275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_275 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_275 = andr(_out_womask_T_275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_275 = and(out_rivalid_1[153], out_rimask_275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_275 = and(out_roready_1[153], out_romask_275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_275 = and(out_wivalid_1[153], out_wimask_275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_275 = and(out_woready_1[153], out_womask_275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3021 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3022 = and(out_f_rivalid_275, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3023 = and(UInt<1>(0h1), out_f_roready_275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3024 = eq(out_rimask_275, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3025 = eq(out_wimask_275, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3026 = eq(out_romask_275, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3027 = eq(out_womask_275, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_227 = or(_out_T_3020, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_227 = cat(UInt<8>(0h74), _out_prepend_T_227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3028 = or(out_prepend_227, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3029 = bits(_out_T_3028, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_276 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_276 = orr(_out_rimask_T_276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_276 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_276 = andr(_out_wimask_T_276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_276 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_276 = orr(_out_romask_T_276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_276 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_276 = andr(_out_womask_T_276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_276 = and(out_rivalid_1[154], out_rimask_276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_276 = and(out_roready_1[154], out_romask_276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_276 = and(out_wivalid_1[154], out_wimask_276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_276 = and(out_woready_1[154], out_womask_276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3030 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3031 = and(out_f_rivalid_276, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3032 = and(UInt<1>(0h1), out_f_roready_276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3033 = eq(out_rimask_276, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3034 = eq(out_wimask_276, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3035 = eq(out_romask_276, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3036 = eq(out_womask_276, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_228 = or(_out_T_3029, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_228 = cat(UInt<8>(0h14), _out_prepend_T_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3037 = or(out_prepend_228, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3038 = bits(_out_T_3037, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_277 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_277 = orr(_out_rimask_T_277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_277 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_277 = andr(_out_wimask_T_277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_277 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_277 = orr(_out_romask_T_277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_277 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_277 = andr(_out_womask_T_277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_277 = and(out_rivalid_1[155], out_rimask_277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_277 = and(out_roready_1[155], out_romask_277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_277 = and(out_wivalid_1[155], out_wimask_277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_277 = and(out_woready_1[155], out_womask_277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3039 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3040 = and(out_f_rivalid_277, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3041 = and(UInt<1>(0h1), out_f_roready_277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3042 = eq(out_rimask_277, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3043 = eq(out_wimask_277, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3044 = eq(out_romask_277, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3045 = eq(out_womask_277, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_229 = or(_out_T_3038, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_229 = cat(UInt<8>(0h0), _out_prepend_T_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3046 = or(out_prepend_229, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3047 = bits(_out_T_3046, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_278 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_278 = orr(_out_rimask_T_278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_278 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_278 = andr(_out_wimask_T_278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_278 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_278 = orr(_out_romask_T_278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_278 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_278 = andr(_out_womask_T_278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_278 = and(out_rivalid_1[156], out_rimask_278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_278 = and(out_roready_1[156], out_romask_278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_278 = and(out_wivalid_1[156], out_wimask_278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_278 = and(out_woready_1[156], out_womask_278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3048 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3049 = and(out_f_rivalid_278, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3050 = and(UInt<1>(0h1), out_f_roready_278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3051 = eq(out_rimask_278, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3052 = eq(out_wimask_278, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3053 = eq(out_romask_278, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3054 = eq(out_womask_278, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_230 = or(_out_T_3047, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_230 = cat(UInt<8>(0h63), _out_prepend_T_230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3055 = or(out_prepend_230, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3056 = bits(_out_T_3055, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_279 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_279 = orr(_out_rimask_T_279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_279 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_279 = andr(_out_wimask_T_279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_279 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_279 = orr(_out_romask_T_279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_279 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_279 = andr(_out_womask_T_279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_279 = and(out_rivalid_1[157], out_rimask_279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_279 = and(out_roready_1[157], out_romask_279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_279 = and(out_wivalid_1[157], out_wimask_279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_279 = and(out_woready_1[157], out_womask_279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3057 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3058 = and(out_f_rivalid_279, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3059 = and(UInt<1>(0h1), out_f_roready_279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3060 = eq(out_rimask_279, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3061 = eq(out_wimask_279, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3062 = eq(out_romask_279, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3063 = eq(out_womask_279, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_231 = or(_out_T_3056, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_231 = cat(UInt<8>(0h8), _out_prepend_T_231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3064 = or(out_prepend_231, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3065 = bits(_out_T_3064, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_280 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_280 = orr(_out_rimask_T_280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_280 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_280 = andr(_out_wimask_T_280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_280 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_280 = orr(_out_romask_T_280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_280 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_280 = andr(_out_womask_T_280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_280 = and(out_rivalid_1[158], out_rimask_280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_280 = and(out_roready_1[158], out_romask_280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_280 = and(out_wivalid_1[158], out_wimask_280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_280 = and(out_woready_1[158], out_womask_280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3066 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3067 = and(out_f_rivalid_280, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3068 = and(UInt<1>(0h1), out_f_roready_280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3069 = eq(out_rimask_280, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3070 = eq(out_wimask_280, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3071 = eq(out_romask_280, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3072 = eq(out_womask_280, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_232 = or(_out_T_3065, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_232 = cat(UInt<8>(0h4), _out_prepend_T_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3073 = or(out_prepend_232, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3074 = bits(_out_T_3073, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_281 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_281 = orr(_out_rimask_T_281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_281 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_281 = andr(_out_wimask_T_281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_281 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_281 = orr(_out_romask_T_281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_281 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_281 = andr(_out_womask_T_281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_281 = and(out_rivalid_1[159], out_rimask_281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_281 = and(out_roready_1[159], out_romask_281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_281 = and(out_wivalid_1[159], out_wimask_281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_281 = and(out_woready_1[159], out_womask_281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3075 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3076 = and(out_f_rivalid_281, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3077 = and(UInt<1>(0h1), out_f_roready_281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3078 = eq(out_rimask_281, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3079 = eq(out_wimask_281, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3080 = eq(out_romask_281, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3081 = eq(out_womask_281, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_233 = or(_out_T_3074, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_233 = cat(UInt<8>(0h0), _out_prepend_T_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3082 = or(out_prepend_233, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3083 = bits(_out_T_3082, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_282 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_282 = orr(_out_rimask_T_282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_282 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_282 = andr(_out_wimask_T_282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_282 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_282 = orr(_out_romask_T_282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_282 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_282 = andr(_out_womask_T_282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_282 = and(out_rivalid_1[160], out_rimask_282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_282 = and(out_roready_1[160], out_romask_282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_282 = and(out_wivalid_1[160], out_wimask_282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_282 = and(out_woready_1[160], out_womask_282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3084 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3085 = and(out_f_rivalid_282, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3086 = and(UInt<1>(0h1), out_f_roready_282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3087 = eq(out_rimask_282, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3088 = eq(out_wimask_282, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3089 = eq(out_romask_282, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3090 = eq(out_womask_282, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3091 = or(_T_1146, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3092 = bits(_out_T_3091, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_283 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_283 = orr(_out_rimask_T_283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_283 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_283 = andr(_out_wimask_T_283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_283 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_283 = orr(_out_romask_T_283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_283 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_283 = andr(_out_womask_T_283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_283 = and(out_rivalid_1[161], out_rimask_283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_283 = and(out_roready_1[161], out_romask_283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_283 = and(out_wivalid_1[161], out_wimask_283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_283 = and(out_woready_1[161], out_womask_283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3093 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3094 = and(out_f_rivalid_283, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3095 = and(UInt<1>(0h1), out_f_roready_283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3096 = eq(out_rimask_283, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3097 = eq(out_wimask_283, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3098 = eq(out_romask_283, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3099 = eq(out_womask_283, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_234 = or(_out_T_3092, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_234 = cat(_T_1147, _out_prepend_T_234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3100 = or(out_prepend_234, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3101 = bits(_out_T_3100, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_284 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_284 = orr(_out_rimask_T_284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_284 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_284 = andr(_out_wimask_T_284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_284 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_284 = orr(_out_romask_T_284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_284 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_284 = andr(_out_womask_T_284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_284 = and(out_rivalid_1[162], out_rimask_284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_284 = and(out_roready_1[162], out_romask_284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_284 = and(out_wivalid_1[162], out_wimask_284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_284 = and(out_woready_1[162], out_womask_284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3102 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3103 = and(out_f_rivalid_284, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3104 = and(UInt<1>(0h1), out_f_roready_284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3105 = eq(out_rimask_284, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3106 = eq(out_wimask_284, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3107 = eq(out_romask_284, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3108 = eq(out_womask_284, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_235 = or(_out_T_3101, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_235 = cat(_T_1148, _out_prepend_T_235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3109 = or(out_prepend_235, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3110 = bits(_out_T_3109, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_285 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_285 = orr(_out_rimask_T_285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_285 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_285 = andr(_out_wimask_T_285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_285 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_285 = orr(_out_romask_T_285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_285 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_285 = andr(_out_womask_T_285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_285 = and(out_rivalid_1[163], out_rimask_285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_285 = and(out_roready_1[163], out_romask_285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_285 = and(out_wivalid_1[163], out_wimask_285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_285 = and(out_woready_1[163], out_womask_285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3111 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3112 = and(out_f_rivalid_285, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3113 = and(UInt<1>(0h1), out_f_roready_285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3114 = eq(out_rimask_285, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3115 = eq(out_wimask_285, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3116 = eq(out_romask_285, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3117 = eq(out_womask_285, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_236 = or(_out_T_3110, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_236 = cat(_T_1149, _out_prepend_T_236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3118 = or(out_prepend_236, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3119 = bits(_out_T_3118, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_286 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_286 = orr(_out_rimask_T_286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_286 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_286 = andr(_out_wimask_T_286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_286 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_286 = orr(_out_romask_T_286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_286 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_286 = andr(_out_womask_T_286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_286 = and(out_rivalid_1[164], out_rimask_286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_286 = and(out_roready_1[164], out_romask_286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_286 = and(out_wivalid_1[164], out_wimask_286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_286 = and(out_woready_1[164], out_womask_286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3120 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3121 = and(out_f_rivalid_286, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3122 = and(UInt<1>(0h1), out_f_roready_286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3123 = eq(out_rimask_286, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3124 = eq(out_wimask_286, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3125 = eq(out_romask_286, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3126 = eq(out_womask_286, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_237 = or(_out_T_3119, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_237 = cat(_T_1150, _out_prepend_T_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3127 = or(out_prepend_237, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3128 = bits(_out_T_3127, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_287 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_287 = orr(_out_rimask_T_287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_287 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_287 = andr(_out_wimask_T_287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_287 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_287 = orr(_out_romask_T_287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_287 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_287 = andr(_out_womask_T_287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_287 = and(out_rivalid_1[165], out_rimask_287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_287 = and(out_roready_1[165], out_romask_287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_287 = and(out_wivalid_1[165], out_wimask_287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_287 = and(out_woready_1[165], out_womask_287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3129 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3130 = and(out_f_rivalid_287, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3131 = and(UInt<1>(0h1), out_f_roready_287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3132 = eq(out_rimask_287, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3133 = eq(out_wimask_287, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3134 = eq(out_romask_287, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3135 = eq(out_womask_287, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_238 = or(_out_T_3128, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_238 = cat(_T_1151, _out_prepend_T_238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3136 = or(out_prepend_238, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3137 = bits(_out_T_3136, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_288 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_288 = orr(_out_rimask_T_288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_288 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_288 = andr(_out_wimask_T_288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_288 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_288 = orr(_out_romask_T_288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_288 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_288 = andr(_out_womask_T_288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_288 = and(out_rivalid_1[166], out_rimask_288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_288 = and(out_roready_1[166], out_romask_288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_288 = and(out_wivalid_1[166], out_wimask_288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_288 = and(out_woready_1[166], out_womask_288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3138 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3139 = and(out_f_rivalid_288, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3140 = and(UInt<1>(0h1), out_f_roready_288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3141 = eq(out_rimask_288, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3142 = eq(out_wimask_288, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3143 = eq(out_romask_288, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3144 = eq(out_womask_288, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_239 = or(_out_T_3137, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_239 = cat(_T_1152, _out_prepend_T_239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3145 = or(out_prepend_239, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3146 = bits(_out_T_3145, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_289 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_289 = orr(_out_rimask_T_289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_289 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_289 = andr(_out_wimask_T_289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_289 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_289 = orr(_out_romask_T_289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_289 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_289 = andr(_out_womask_T_289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_289 = and(out_rivalid_1[167], out_rimask_289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_289 = and(out_roready_1[167], out_romask_289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_289 = and(out_wivalid_1[167], out_wimask_289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_289 = and(out_woready_1[167], out_womask_289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3147 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3148 = and(out_f_rivalid_289, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3149 = and(UInt<1>(0h1), out_f_roready_289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3150 = eq(out_rimask_289, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3151 = eq(out_wimask_289, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3152 = eq(out_romask_289, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3153 = eq(out_womask_289, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_240 = or(_out_T_3146, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_240 = cat(_T_1153, _out_prepend_T_240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3154 = or(out_prepend_240, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3155 = bits(_out_T_3154, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_290 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_290 = orr(_out_rimask_T_290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_290 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_290 = andr(_out_wimask_T_290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_290 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_290 = orr(_out_romask_T_290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_290 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_290 = andr(_out_womask_T_290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_290 = and(out_rivalid_1[168], out_rimask_290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_290 = and(out_roready_1[168], out_romask_290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_290 = and(out_wivalid_1[168], out_wimask_290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_290 = and(out_woready_1[168], out_womask_290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3156 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3157 = and(out_f_rivalid_290, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3158 = and(UInt<1>(0h1), out_f_roready_290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3159 = eq(out_rimask_290, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3160 = eq(out_wimask_290, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3161 = eq(out_romask_290, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3162 = eq(out_womask_290, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3163 = or(_T_730, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3164 = bits(_out_T_3163, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_291 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_291 = orr(_out_rimask_T_291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_291 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_291 = andr(_out_wimask_T_291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_291 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_291 = orr(_out_romask_T_291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_291 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_291 = andr(_out_womask_T_291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_291 = and(out_rivalid_1[169], out_rimask_291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_291 = and(out_roready_1[169], out_romask_291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_291 = and(out_wivalid_1[169], out_wimask_291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_291 = and(out_woready_1[169], out_womask_291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3165 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3166 = and(out_f_rivalid_291, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3167 = and(UInt<1>(0h1), out_f_roready_291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3168 = eq(out_rimask_291, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3169 = eq(out_wimask_291, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3170 = eq(out_romask_291, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3171 = eq(out_womask_291, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_241 = or(_out_T_3164, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_241 = cat(_T_731, _out_prepend_T_241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3172 = or(out_prepend_241, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3173 = bits(_out_T_3172, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_292 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_292 = orr(_out_rimask_T_292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_292 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_292 = andr(_out_wimask_T_292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_292 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_292 = orr(_out_romask_T_292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_292 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_292 = andr(_out_womask_T_292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_292 = and(out_rivalid_1[170], out_rimask_292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_292 = and(out_roready_1[170], out_romask_292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_292 = and(out_wivalid_1[170], out_wimask_292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_292 = and(out_woready_1[170], out_womask_292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3174 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3175 = and(out_f_rivalid_292, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3176 = and(UInt<1>(0h1), out_f_roready_292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3177 = eq(out_rimask_292, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3178 = eq(out_wimask_292, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3179 = eq(out_romask_292, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3180 = eq(out_womask_292, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_242 = or(_out_T_3173, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_242 = cat(_T_732, _out_prepend_T_242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3181 = or(out_prepend_242, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3182 = bits(_out_T_3181, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_293 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_293 = orr(_out_rimask_T_293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_293 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_293 = andr(_out_wimask_T_293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_293 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_293 = orr(_out_romask_T_293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_293 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_293 = andr(_out_womask_T_293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_293 = and(out_rivalid_1[171], out_rimask_293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_293 = and(out_roready_1[171], out_romask_293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_293 = and(out_wivalid_1[171], out_wimask_293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_293 = and(out_woready_1[171], out_womask_293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3183 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3184 = and(out_f_rivalid_293, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3185 = and(UInt<1>(0h1), out_f_roready_293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3186 = eq(out_rimask_293, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3187 = eq(out_wimask_293, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3188 = eq(out_romask_293, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3189 = eq(out_womask_293, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_243 = or(_out_T_3182, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_243 = cat(_T_733, _out_prepend_T_243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3190 = or(out_prepend_243, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3191 = bits(_out_T_3190, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_294 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_294 = orr(_out_rimask_T_294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_294 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_294 = andr(_out_wimask_T_294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_294 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_294 = orr(_out_romask_T_294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_294 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_294 = andr(_out_womask_T_294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_294 = and(out_rivalid_1[172], out_rimask_294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_294 = and(out_roready_1[172], out_romask_294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_294 = and(out_wivalid_1[172], out_wimask_294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_294 = and(out_woready_1[172], out_womask_294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3192 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3193 = and(out_f_rivalid_294, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3194 = and(UInt<1>(0h1), out_f_roready_294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3195 = eq(out_rimask_294, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3196 = eq(out_wimask_294, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3197 = eq(out_romask_294, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3198 = eq(out_womask_294, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_244 = or(_out_T_3191, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_244 = cat(_T_734, _out_prepend_T_244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3199 = or(out_prepend_244, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3200 = bits(_out_T_3199, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_295 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_295 = orr(_out_rimask_T_295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_295 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_295 = andr(_out_wimask_T_295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_295 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_295 = orr(_out_romask_T_295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_295 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_295 = andr(_out_womask_T_295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_295 = and(out_rivalid_1[173], out_rimask_295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_295 = and(out_roready_1[173], out_romask_295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_295 = and(out_wivalid_1[173], out_wimask_295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_295 = and(out_woready_1[173], out_womask_295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3201 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3202 = and(out_f_rivalid_295, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3203 = and(UInt<1>(0h1), out_f_roready_295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3204 = eq(out_rimask_295, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3205 = eq(out_wimask_295, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3206 = eq(out_romask_295, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3207 = eq(out_womask_295, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_245 = or(_out_T_3200, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_245 = cat(_T_735, _out_prepend_T_245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3208 = or(out_prepend_245, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3209 = bits(_out_T_3208, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_296 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_296 = orr(_out_rimask_T_296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_296 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_296 = andr(_out_wimask_T_296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_296 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_296 = orr(_out_romask_T_296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_296 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_296 = andr(_out_womask_T_296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_296 = and(out_rivalid_1[174], out_rimask_296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_296 = and(out_roready_1[174], out_romask_296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_296 = and(out_wivalid_1[174], out_wimask_296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_296 = and(out_woready_1[174], out_womask_296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3210 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3211 = and(out_f_rivalid_296, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3212 = and(UInt<1>(0h1), out_f_roready_296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3213 = eq(out_rimask_296, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3214 = eq(out_wimask_296, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3215 = eq(out_romask_296, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3216 = eq(out_womask_296, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_246 = or(_out_T_3209, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_246 = cat(_T_736, _out_prepend_T_246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3217 = or(out_prepend_246, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3218 = bits(_out_T_3217, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_297 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_297 = orr(_out_rimask_T_297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_297 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_297 = andr(_out_wimask_T_297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_297 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_297 = orr(_out_romask_T_297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_297 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_297 = andr(_out_womask_T_297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_297 = and(out_rivalid_1[175], out_rimask_297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_297 = and(out_roready_1[175], out_romask_297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_297 = and(out_wivalid_1[175], out_wimask_297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_297 = and(out_woready_1[175], out_womask_297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3219 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3220 = and(out_f_rivalid_297, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3221 = and(UInt<1>(0h1), out_f_roready_297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3222 = eq(out_rimask_297, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3223 = eq(out_wimask_297, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3224 = eq(out_romask_297, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3225 = eq(out_womask_297, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_247 = or(_out_T_3218, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_247 = cat(_T_737, _out_prepend_T_247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3226 = or(out_prepend_247, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3227 = bits(_out_T_3226, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_298 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_298 = orr(_out_rimask_T_298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_298 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_298 = andr(_out_wimask_T_298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_298 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_298 = orr(_out_romask_T_298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_298 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_298 = andr(_out_womask_T_298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_298 = and(out_rivalid_1[176], out_rimask_298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_298 = and(out_roready_1[176], out_romask_298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_298 = and(out_wivalid_1[176], out_wimask_298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_298 = and(out_woready_1[176], out_womask_298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3228 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3229 = and(out_f_rivalid_298, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3230 = and(UInt<1>(0h1), out_f_roready_298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3231 = eq(out_rimask_298, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3232 = eq(out_wimask_298, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3233 = eq(out_romask_298, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3234 = eq(out_womask_298, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3235 = or(_T_850, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3236 = bits(_out_T_3235, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_299 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_299 = orr(_out_rimask_T_299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_299 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_299 = andr(_out_wimask_T_299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_299 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_299 = orr(_out_romask_T_299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_299 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_299 = andr(_out_womask_T_299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_299 = and(out_rivalid_1[177], out_rimask_299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_299 = and(out_roready_1[177], out_romask_299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_299 = and(out_wivalid_1[177], out_wimask_299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_299 = and(out_woready_1[177], out_womask_299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3237 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3238 = and(out_f_rivalid_299, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3239 = and(UInt<1>(0h1), out_f_roready_299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3240 = eq(out_rimask_299, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3241 = eq(out_wimask_299, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3242 = eq(out_romask_299, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3243 = eq(out_womask_299, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_248 = or(_out_T_3236, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_248 = cat(_T_851, _out_prepend_T_248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3244 = or(out_prepend_248, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3245 = bits(_out_T_3244, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_300 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_300 = orr(_out_rimask_T_300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_300 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_300 = andr(_out_wimask_T_300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_300 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_300 = orr(_out_romask_T_300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_300 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_300 = andr(_out_womask_T_300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_300 = and(out_rivalid_1[178], out_rimask_300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_300 = and(out_roready_1[178], out_romask_300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_300 = and(out_wivalid_1[178], out_wimask_300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_300 = and(out_woready_1[178], out_womask_300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3246 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3247 = and(out_f_rivalid_300, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3248 = and(UInt<1>(0h1), out_f_roready_300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3249 = eq(out_rimask_300, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3250 = eq(out_wimask_300, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3251 = eq(out_romask_300, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3252 = eq(out_womask_300, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_249 = or(_out_T_3245, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_249 = cat(_T_852, _out_prepend_T_249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3253 = or(out_prepend_249, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3254 = bits(_out_T_3253, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_301 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_301 = orr(_out_rimask_T_301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_301 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_301 = andr(_out_wimask_T_301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_301 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_301 = orr(_out_romask_T_301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_301 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_301 = andr(_out_womask_T_301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_301 = and(out_rivalid_1[179], out_rimask_301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_301 = and(out_roready_1[179], out_romask_301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_301 = and(out_wivalid_1[179], out_wimask_301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_301 = and(out_woready_1[179], out_womask_301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3255 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3256 = and(out_f_rivalid_301, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3257 = and(UInt<1>(0h1), out_f_roready_301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3258 = eq(out_rimask_301, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3259 = eq(out_wimask_301, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3260 = eq(out_romask_301, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3261 = eq(out_womask_301, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_250 = or(_out_T_3254, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_250 = cat(_T_853, _out_prepend_T_250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3262 = or(out_prepend_250, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3263 = bits(_out_T_3262, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_302 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_302 = orr(_out_rimask_T_302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_302 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_302 = andr(_out_wimask_T_302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_302 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_302 = orr(_out_romask_T_302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_302 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_302 = andr(_out_womask_T_302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_302 = and(out_rivalid_1[180], out_rimask_302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_302 = and(out_roready_1[180], out_romask_302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_302 = and(out_wivalid_1[180], out_wimask_302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_302 = and(out_woready_1[180], out_womask_302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3264 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3265 = and(out_f_rivalid_302, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3266 = and(UInt<1>(0h1), out_f_roready_302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3267 = eq(out_rimask_302, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3268 = eq(out_wimask_302, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3269 = eq(out_romask_302, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3270 = eq(out_womask_302, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_251 = or(_out_T_3263, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_251 = cat(_T_854, _out_prepend_T_251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3271 = or(out_prepend_251, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3272 = bits(_out_T_3271, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_303 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_303 = orr(_out_rimask_T_303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_303 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_303 = andr(_out_wimask_T_303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_303 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_303 = orr(_out_romask_T_303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_303 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_303 = andr(_out_womask_T_303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_303 = and(out_rivalid_1[181], out_rimask_303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_303 = and(out_roready_1[181], out_romask_303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_303 = and(out_wivalid_1[181], out_wimask_303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_303 = and(out_woready_1[181], out_womask_303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3273 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3274 = and(out_f_rivalid_303, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3275 = and(UInt<1>(0h1), out_f_roready_303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3276 = eq(out_rimask_303, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3277 = eq(out_wimask_303, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3278 = eq(out_romask_303, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3279 = eq(out_womask_303, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_252 = or(_out_T_3272, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_252 = cat(_T_855, _out_prepend_T_252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3280 = or(out_prepend_252, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3281 = bits(_out_T_3280, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_304 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_304 = orr(_out_rimask_T_304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_304 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_304 = andr(_out_wimask_T_304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_304 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_304 = orr(_out_romask_T_304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_304 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_304 = andr(_out_womask_T_304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_304 = and(out_rivalid_1[182], out_rimask_304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_304 = and(out_roready_1[182], out_romask_304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_304 = and(out_wivalid_1[182], out_wimask_304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_304 = and(out_woready_1[182], out_womask_304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3282 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3283 = and(out_f_rivalid_304, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3284 = and(UInt<1>(0h1), out_f_roready_304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3285 = eq(out_rimask_304, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3286 = eq(out_wimask_304, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3287 = eq(out_romask_304, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3288 = eq(out_womask_304, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_253 = or(_out_T_3281, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_253 = cat(_T_856, _out_prepend_T_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3289 = or(out_prepend_253, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3290 = bits(_out_T_3289, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_305 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_305 = orr(_out_rimask_T_305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_305 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_305 = andr(_out_wimask_T_305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_305 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_305 = orr(_out_romask_T_305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_305 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_305 = andr(_out_womask_T_305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_305 = and(out_rivalid_1[183], out_rimask_305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_305 = and(out_roready_1[183], out_romask_305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_305 = and(out_wivalid_1[183], out_wimask_305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_305 = and(out_woready_1[183], out_womask_305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3291 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3292 = and(out_f_rivalid_305, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3293 = and(UInt<1>(0h1), out_f_roready_305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3294 = eq(out_rimask_305, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3295 = eq(out_wimask_305, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3296 = eq(out_romask_305, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3297 = eq(out_womask_305, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_254 = or(_out_T_3290, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_254 = cat(_T_857, _out_prepend_T_254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3298 = or(out_prepend_254, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3299 = bits(_out_T_3298, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_306 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_306 = orr(_out_rimask_T_306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_306 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_306 = andr(_out_wimask_T_306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_306 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_306 = orr(_out_romask_T_306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_306 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_306 = andr(_out_womask_T_306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_306 = and(out_rivalid_1[184], out_rimask_306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_306 = and(out_roready_1[184], out_romask_306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_306 = and(out_wivalid_1[184], out_wimask_306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_306 = and(out_woready_1[184], out_womask_306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3300 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_306 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[16], _out_T_3300 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_3301 = and(out_f_rivalid_306, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3302 = and(UInt<1>(0h1), out_f_roready_306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3303 = and(out_f_wivalid_306, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3304 = and(UInt<1>(0h1), out_f_woready_306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3305 = eq(out_rimask_306, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3306 = eq(out_wimask_306, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3307 = eq(out_romask_306, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3308 = eq(out_womask_306, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3309 = or(programBufferMem[16], UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3310 = bits(_out_T_3309, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_307 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_307 = orr(_out_rimask_T_307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_307 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_307 = andr(_out_wimask_T_307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_307 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_307 = orr(_out_romask_T_307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_307 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_307 = andr(_out_womask_T_307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_307 = and(out_rivalid_1[185], out_rimask_307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_307 = and(out_roready_1[185], out_romask_307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_307 = and(out_wivalid_1[185], out_wimask_307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_307 = and(out_woready_1[185], out_womask_307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3311 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_307 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[17], _out_T_3311 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_3312 = and(out_f_rivalid_307, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3313 = and(UInt<1>(0h1), out_f_roready_307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3314 = and(out_f_wivalid_307, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3315 = and(UInt<1>(0h1), out_f_woready_307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3316 = eq(out_rimask_307, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3317 = eq(out_wimask_307, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3318 = eq(out_romask_307, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3319 = eq(out_womask_307, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_255 = or(_out_T_3310, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_255 = cat(programBufferMem[17], _out_prepend_T_255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3320 = or(out_prepend_255, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3321 = bits(_out_T_3320, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_308 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_308 = orr(_out_rimask_T_308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_308 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_308 = andr(_out_wimask_T_308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_308 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_308 = orr(_out_romask_T_308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_308 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_308 = andr(_out_womask_T_308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_308 = and(out_rivalid_1[186], out_rimask_308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_308 = and(out_roready_1[186], out_romask_308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_308 = and(out_wivalid_1[186], out_wimask_308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_308 = and(out_woready_1[186], out_womask_308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3322 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_308 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[18], _out_T_3322 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_3323 = and(out_f_rivalid_308, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3324 = and(UInt<1>(0h1), out_f_roready_308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3325 = and(out_f_wivalid_308, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3326 = and(UInt<1>(0h1), out_f_woready_308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3327 = eq(out_rimask_308, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3328 = eq(out_wimask_308, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3329 = eq(out_romask_308, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3330 = eq(out_womask_308, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_256 = or(_out_T_3321, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_256 = cat(programBufferMem[18], _out_prepend_T_256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3331 = or(out_prepend_256, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3332 = bits(_out_T_3331, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_309 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_309 = orr(_out_rimask_T_309) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_309 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_309 = andr(_out_wimask_T_309) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_309 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_309 = orr(_out_romask_T_309) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_309 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_309 = andr(_out_womask_T_309) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_309 = and(out_rivalid_1[187], out_rimask_309) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_309 = and(out_roready_1[187], out_romask_309) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_309 = and(out_wivalid_1[187], out_wimask_309) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_309 = and(out_woready_1[187], out_womask_309) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3333 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_309 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[19], _out_T_3333 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_3334 = and(out_f_rivalid_309, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3335 = and(UInt<1>(0h1), out_f_roready_309) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3336 = and(out_f_wivalid_309, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3337 = and(UInt<1>(0h1), out_f_woready_309) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3338 = eq(out_rimask_309, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3339 = eq(out_wimask_309, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3340 = eq(out_romask_309, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3341 = eq(out_womask_309, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_257 = or(_out_T_3332, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_257 = cat(programBufferMem[19], _out_prepend_T_257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3342 = or(out_prepend_257, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3343 = bits(_out_T_3342, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_310 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_310 = orr(_out_rimask_T_310) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_310 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_310 = andr(_out_wimask_T_310) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_310 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_310 = orr(_out_romask_T_310) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_310 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_310 = andr(_out_womask_T_310) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_310 = and(out_rivalid_1[188], out_rimask_310) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_310 = and(out_roready_1[188], out_romask_310) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_310 = and(out_wivalid_1[188], out_wimask_310) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_310 = and(out_woready_1[188], out_womask_310) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3344 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_310 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[20], _out_T_3344 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_3345 = and(out_f_rivalid_310, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3346 = and(UInt<1>(0h1), out_f_roready_310) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3347 = and(out_f_wivalid_310, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3348 = and(UInt<1>(0h1), out_f_woready_310) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3349 = eq(out_rimask_310, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3350 = eq(out_wimask_310, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3351 = eq(out_romask_310, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3352 = eq(out_womask_310, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_258 = or(_out_T_3343, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_258 = cat(programBufferMem[20], _out_prepend_T_258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3353 = or(out_prepend_258, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3354 = bits(_out_T_3353, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_311 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_311 = orr(_out_rimask_T_311) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_311 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_311 = andr(_out_wimask_T_311) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_311 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_311 = orr(_out_romask_T_311) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_311 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_311 = andr(_out_womask_T_311) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_311 = and(out_rivalid_1[189], out_rimask_311) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_311 = and(out_roready_1[189], out_romask_311) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_311 = and(out_wivalid_1[189], out_wimask_311) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_311 = and(out_woready_1[189], out_womask_311) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3355 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_311 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[21], _out_T_3355 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_3356 = and(out_f_rivalid_311, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3357 = and(UInt<1>(0h1), out_f_roready_311) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3358 = and(out_f_wivalid_311, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3359 = and(UInt<1>(0h1), out_f_woready_311) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3360 = eq(out_rimask_311, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3361 = eq(out_wimask_311, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3362 = eq(out_romask_311, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3363 = eq(out_womask_311, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_259 = or(_out_T_3354, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_259 = cat(programBufferMem[21], _out_prepend_T_259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3364 = or(out_prepend_259, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3365 = bits(_out_T_3364, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_312 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_312 = orr(_out_rimask_T_312) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_312 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_312 = andr(_out_wimask_T_312) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_312 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_312 = orr(_out_romask_T_312) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_312 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_312 = andr(_out_womask_T_312) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_312 = and(out_rivalid_1[190], out_rimask_312) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_312 = and(out_roready_1[190], out_romask_312) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_312 = and(out_wivalid_1[190], out_wimask_312) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_312 = and(out_woready_1[190], out_womask_312) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3366 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_312 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[22], _out_T_3366 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_3367 = and(out_f_rivalid_312, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3368 = and(UInt<1>(0h1), out_f_roready_312) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3369 = and(out_f_wivalid_312, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3370 = and(UInt<1>(0h1), out_f_woready_312) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3371 = eq(out_rimask_312, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3372 = eq(out_wimask_312, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3373 = eq(out_romask_312, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3374 = eq(out_womask_312, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_260 = or(_out_T_3365, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_260 = cat(programBufferMem[22], _out_prepend_T_260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3375 = or(out_prepend_260, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3376 = bits(_out_T_3375, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_313 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_313 = orr(_out_rimask_T_313) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_313 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_313 = andr(_out_wimask_T_313) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_313 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_313 = orr(_out_romask_T_313) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_313 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_313 = andr(_out_womask_T_313) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_313 = and(out_rivalid_1[191], out_rimask_313) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_313 = and(out_roready_1[191], out_romask_313) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_313 = and(out_wivalid_1[191], out_wimask_313) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_313 = and(out_woready_1[191], out_womask_313) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3377 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_313 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[23], _out_T_3377 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_3378 = and(out_f_rivalid_313, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3379 = and(UInt<1>(0h1), out_f_roready_313) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3380 = and(out_f_wivalid_313, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3381 = and(UInt<1>(0h1), out_f_woready_313) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3382 = eq(out_rimask_313, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3383 = eq(out_wimask_313, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3384 = eq(out_romask_313, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3385 = eq(out_womask_313, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_261 = or(_out_T_3376, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_261 = cat(programBufferMem[23], _out_prepend_T_261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3386 = or(out_prepend_261, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3387 = bits(_out_T_3386, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_314 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_314 = orr(_out_rimask_T_314) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_314 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_314 = andr(_out_wimask_T_314) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_314 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_314 = orr(_out_romask_T_314) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_314 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_314 = andr(_out_womask_T_314) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_314 = and(out_rivalid_1[192], out_rimask_314) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_314 = and(out_roready_1[192], out_romask_314) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_314 = and(out_wivalid_1[192], out_wimask_314) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_314 = and(out_woready_1[192], out_womask_314) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3388 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3389 = and(out_f_rivalid_314, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3390 = and(UInt<1>(0h1), out_f_roready_314) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3391 = eq(out_rimask_314, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3392 = eq(out_wimask_314, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3393 = eq(out_romask_314, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3394 = eq(out_womask_314, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3395 = or(_T_1322, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3396 = bits(_out_T_3395, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_315 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_315 = orr(_out_rimask_T_315) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_315 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_315 = andr(_out_wimask_T_315) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_315 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_315 = orr(_out_romask_T_315) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_315 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_315 = andr(_out_womask_T_315) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_315 = and(out_rivalid_1[193], out_rimask_315) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_315 = and(out_roready_1[193], out_romask_315) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_315 = and(out_wivalid_1[193], out_wimask_315) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_315 = and(out_woready_1[193], out_womask_315) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3397 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3398 = and(out_f_rivalid_315, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3399 = and(UInt<1>(0h1), out_f_roready_315) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3400 = eq(out_rimask_315, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3401 = eq(out_wimask_315, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3402 = eq(out_romask_315, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3403 = eq(out_womask_315, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_262 = or(_out_T_3396, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_262 = cat(_T_1323, _out_prepend_T_262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3404 = or(out_prepend_262, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3405 = bits(_out_T_3404, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_316 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_316 = orr(_out_rimask_T_316) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_316 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_316 = andr(_out_wimask_T_316) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_316 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_316 = orr(_out_romask_T_316) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_316 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_316 = andr(_out_womask_T_316) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_316 = and(out_rivalid_1[194], out_rimask_316) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_316 = and(out_roready_1[194], out_romask_316) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_316 = and(out_wivalid_1[194], out_wimask_316) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_316 = and(out_woready_1[194], out_womask_316) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3406 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3407 = and(out_f_rivalid_316, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3408 = and(UInt<1>(0h1), out_f_roready_316) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3409 = eq(out_rimask_316, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3410 = eq(out_wimask_316, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3411 = eq(out_romask_316, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3412 = eq(out_womask_316, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_263 = or(_out_T_3405, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_263 = cat(_T_1324, _out_prepend_T_263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3413 = or(out_prepend_263, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3414 = bits(_out_T_3413, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_317 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_317 = orr(_out_rimask_T_317) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_317 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_317 = andr(_out_wimask_T_317) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_317 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_317 = orr(_out_romask_T_317) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_317 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_317 = andr(_out_womask_T_317) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_317 = and(out_rivalid_1[195], out_rimask_317) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_317 = and(out_roready_1[195], out_romask_317) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_317 = and(out_wivalid_1[195], out_wimask_317) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_317 = and(out_woready_1[195], out_womask_317) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3415 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3416 = and(out_f_rivalid_317, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3417 = and(UInt<1>(0h1), out_f_roready_317) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3418 = eq(out_rimask_317, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3419 = eq(out_wimask_317, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3420 = eq(out_romask_317, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3421 = eq(out_womask_317, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_264 = or(_out_T_3414, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_264 = cat(_T_1325, _out_prepend_T_264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3422 = or(out_prepend_264, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3423 = bits(_out_T_3422, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_318 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_318 = orr(_out_rimask_T_318) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_318 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_318 = andr(_out_wimask_T_318) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_318 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_318 = orr(_out_romask_T_318) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_318 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_318 = andr(_out_womask_T_318) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_318 = and(out_rivalid_1[196], out_rimask_318) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_318 = and(out_roready_1[196], out_romask_318) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_318 = and(out_wivalid_1[196], out_wimask_318) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_318 = and(out_woready_1[196], out_womask_318) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3424 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3425 = and(out_f_rivalid_318, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3426 = and(UInt<1>(0h1), out_f_roready_318) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3427 = eq(out_rimask_318, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3428 = eq(out_wimask_318, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3429 = eq(out_romask_318, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3430 = eq(out_womask_318, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_265 = or(_out_T_3423, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_265 = cat(_T_1326, _out_prepend_T_265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3431 = or(out_prepend_265, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3432 = bits(_out_T_3431, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_319 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_319 = orr(_out_rimask_T_319) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_319 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_319 = andr(_out_wimask_T_319) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_319 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_319 = orr(_out_romask_T_319) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_319 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_319 = andr(_out_womask_T_319) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_319 = and(out_rivalid_1[197], out_rimask_319) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_319 = and(out_roready_1[197], out_romask_319) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_319 = and(out_wivalid_1[197], out_wimask_319) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_319 = and(out_woready_1[197], out_womask_319) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3433 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3434 = and(out_f_rivalid_319, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3435 = and(UInt<1>(0h1), out_f_roready_319) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3436 = eq(out_rimask_319, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3437 = eq(out_wimask_319, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3438 = eq(out_romask_319, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3439 = eq(out_womask_319, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_266 = or(_out_T_3432, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_266 = cat(_T_1327, _out_prepend_T_266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3440 = or(out_prepend_266, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3441 = bits(_out_T_3440, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_320 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_320 = orr(_out_rimask_T_320) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_320 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_320 = andr(_out_wimask_T_320) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_320 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_320 = orr(_out_romask_T_320) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_320 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_320 = andr(_out_womask_T_320) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_320 = and(out_rivalid_1[198], out_rimask_320) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_320 = and(out_roready_1[198], out_romask_320) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_320 = and(out_wivalid_1[198], out_wimask_320) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_320 = and(out_woready_1[198], out_womask_320) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3442 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3443 = and(out_f_rivalid_320, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3444 = and(UInt<1>(0h1), out_f_roready_320) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3445 = eq(out_rimask_320, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3446 = eq(out_wimask_320, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3447 = eq(out_romask_320, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3448 = eq(out_womask_320, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_267 = or(_out_T_3441, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_267 = cat(_T_1328, _out_prepend_T_267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3449 = or(out_prepend_267, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3450 = bits(_out_T_3449, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_321 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_321 = orr(_out_rimask_T_321) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_321 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_321 = andr(_out_wimask_T_321) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_321 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_321 = orr(_out_romask_T_321) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_321 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_321 = andr(_out_womask_T_321) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_321 = and(out_rivalid_1[199], out_rimask_321) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_321 = and(out_roready_1[199], out_romask_321) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_321 = and(out_wivalid_1[199], out_wimask_321) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_321 = and(out_woready_1[199], out_womask_321) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3451 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3452 = and(out_f_rivalid_321, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3453 = and(UInt<1>(0h1), out_f_roready_321) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3454 = eq(out_rimask_321, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3455 = eq(out_wimask_321, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3456 = eq(out_romask_321, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3457 = eq(out_womask_321, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_268 = or(_out_T_3450, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_268 = cat(_T_1329, _out_prepend_T_268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3458 = or(out_prepend_268, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3459 = bits(_out_T_3458, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_322 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_322 = orr(_out_rimask_T_322) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_322 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_322 = andr(_out_wimask_T_322) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_322 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_322 = orr(_out_romask_T_322) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_322 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_322 = andr(_out_womask_T_322) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_322 = and(out_rivalid_1[200], out_rimask_322) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_322 = and(out_roready_1[200], out_romask_322) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_322 = and(out_wivalid_1[200], out_wimask_322) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_322 = and(out_woready_1[200], out_womask_322) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3460 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3461 = and(out_f_rivalid_322, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3462 = and(UInt<1>(0h1), out_f_roready_322) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3463 = eq(out_rimask_322, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3464 = eq(out_wimask_322, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3465 = eq(out_romask_322, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3466 = eq(out_womask_322, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3467 = or(_T_1106, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3468 = bits(_out_T_3467, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_323 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_323 = orr(_out_rimask_T_323) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_323 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_323 = andr(_out_wimask_T_323) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_323 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_323 = orr(_out_romask_T_323) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_323 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_323 = andr(_out_womask_T_323) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_323 = and(out_rivalid_1[201], out_rimask_323) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_323 = and(out_roready_1[201], out_romask_323) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_323 = and(out_wivalid_1[201], out_wimask_323) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_323 = and(out_woready_1[201], out_womask_323) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3469 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3470 = and(out_f_rivalid_323, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3471 = and(UInt<1>(0h1), out_f_roready_323) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3472 = eq(out_rimask_323, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3473 = eq(out_wimask_323, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3474 = eq(out_romask_323, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3475 = eq(out_womask_323, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_269 = or(_out_T_3468, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_269 = cat(_T_1107, _out_prepend_T_269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3476 = or(out_prepend_269, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3477 = bits(_out_T_3476, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_324 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_324 = orr(_out_rimask_T_324) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_324 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_324 = andr(_out_wimask_T_324) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_324 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_324 = orr(_out_romask_T_324) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_324 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_324 = andr(_out_womask_T_324) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_324 = and(out_rivalid_1[202], out_rimask_324) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_324 = and(out_roready_1[202], out_romask_324) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_324 = and(out_wivalid_1[202], out_wimask_324) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_324 = and(out_woready_1[202], out_womask_324) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3478 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3479 = and(out_f_rivalid_324, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3480 = and(UInt<1>(0h1), out_f_roready_324) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3481 = eq(out_rimask_324, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3482 = eq(out_wimask_324, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3483 = eq(out_romask_324, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3484 = eq(out_womask_324, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_270 = or(_out_T_3477, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_270 = cat(_T_1108, _out_prepend_T_270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3485 = or(out_prepend_270, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3486 = bits(_out_T_3485, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_325 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_325 = orr(_out_rimask_T_325) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_325 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_325 = andr(_out_wimask_T_325) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_325 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_325 = orr(_out_romask_T_325) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_325 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_325 = andr(_out_womask_T_325) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_325 = and(out_rivalid_1[203], out_rimask_325) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_325 = and(out_roready_1[203], out_romask_325) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_325 = and(out_wivalid_1[203], out_wimask_325) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_325 = and(out_woready_1[203], out_womask_325) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3487 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3488 = and(out_f_rivalid_325, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3489 = and(UInt<1>(0h1), out_f_roready_325) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3490 = eq(out_rimask_325, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3491 = eq(out_wimask_325, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3492 = eq(out_romask_325, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3493 = eq(out_womask_325, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_271 = or(_out_T_3486, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_271 = cat(_T_1109, _out_prepend_T_271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3494 = or(out_prepend_271, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3495 = bits(_out_T_3494, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_326 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_326 = orr(_out_rimask_T_326) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_326 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_326 = andr(_out_wimask_T_326) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_326 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_326 = orr(_out_romask_T_326) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_326 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_326 = andr(_out_womask_T_326) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_326 = and(out_rivalid_1[204], out_rimask_326) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_326 = and(out_roready_1[204], out_romask_326) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_326 = and(out_wivalid_1[204], out_wimask_326) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_326 = and(out_woready_1[204], out_womask_326) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3496 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3497 = and(out_f_rivalid_326, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3498 = and(UInt<1>(0h1), out_f_roready_326) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3499 = eq(out_rimask_326, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3500 = eq(out_wimask_326, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3501 = eq(out_romask_326, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3502 = eq(out_womask_326, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_272 = or(_out_T_3495, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_272 = cat(_T_1110, _out_prepend_T_272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3503 = or(out_prepend_272, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3504 = bits(_out_T_3503, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_327 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_327 = orr(_out_rimask_T_327) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_327 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_327 = andr(_out_wimask_T_327) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_327 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_327 = orr(_out_romask_T_327) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_327 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_327 = andr(_out_womask_T_327) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_327 = and(out_rivalid_1[205], out_rimask_327) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_327 = and(out_roready_1[205], out_romask_327) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_327 = and(out_wivalid_1[205], out_wimask_327) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_327 = and(out_woready_1[205], out_womask_327) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3505 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3506 = and(out_f_rivalid_327, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3507 = and(UInt<1>(0h1), out_f_roready_327) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3508 = eq(out_rimask_327, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3509 = eq(out_wimask_327, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3510 = eq(out_romask_327, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3511 = eq(out_womask_327, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_273 = or(_out_T_3504, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_273 = cat(_T_1111, _out_prepend_T_273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3512 = or(out_prepend_273, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3513 = bits(_out_T_3512, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_328 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_328 = orr(_out_rimask_T_328) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_328 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_328 = andr(_out_wimask_T_328) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_328 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_328 = orr(_out_romask_T_328) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_328 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_328 = andr(_out_womask_T_328) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_328 = and(out_rivalid_1[206], out_rimask_328) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_328 = and(out_roready_1[206], out_romask_328) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_328 = and(out_wivalid_1[206], out_wimask_328) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_328 = and(out_woready_1[206], out_womask_328) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3514 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3515 = and(out_f_rivalid_328, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3516 = and(UInt<1>(0h1), out_f_roready_328) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3517 = eq(out_rimask_328, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3518 = eq(out_wimask_328, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3519 = eq(out_romask_328, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3520 = eq(out_womask_328, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_274 = or(_out_T_3513, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_274 = cat(_T_1112, _out_prepend_T_274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3521 = or(out_prepend_274, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3522 = bits(_out_T_3521, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_329 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_329 = orr(_out_rimask_T_329) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_329 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_329 = andr(_out_wimask_T_329) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_329 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_329 = orr(_out_romask_T_329) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_329 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_329 = andr(_out_womask_T_329) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_329 = and(out_rivalid_1[207], out_rimask_329) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_329 = and(out_roready_1[207], out_romask_329) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_329 = and(out_wivalid_1[207], out_wimask_329) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_329 = and(out_woready_1[207], out_womask_329) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3523 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3524 = and(out_f_rivalid_329, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3525 = and(UInt<1>(0h1), out_f_roready_329) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3526 = eq(out_rimask_329, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3527 = eq(out_wimask_329, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3528 = eq(out_romask_329, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3529 = eq(out_womask_329, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_275 = or(_out_T_3522, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_275 = cat(_T_1113, _out_prepend_T_275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3530 = or(out_prepend_275, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3531 = bits(_out_T_3530, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_330 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_330 = orr(_out_rimask_T_330) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_330 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_330 = andr(_out_wimask_T_330) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_330 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_330 = orr(_out_romask_T_330) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_330 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_330 = andr(_out_womask_T_330) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_330 = and(out_rivalid_1[208], out_rimask_330) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_330 = and(out_roready_1[208], out_romask_330) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_330 = and(out_wivalid_1[208], out_wimask_330) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_330 = and(out_woready_1[208], out_womask_330) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3532 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3533 = and(out_f_rivalid_330, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3534 = and(UInt<1>(0h1), out_f_roready_330) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3535 = eq(out_rimask_330, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3536 = eq(out_wimask_330, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3537 = eq(out_romask_330, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3538 = eq(out_womask_330, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3539 = or(_T_1442, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3540 = bits(_out_T_3539, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_331 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_331 = orr(_out_rimask_T_331) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_331 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_331 = andr(_out_wimask_T_331) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_331 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_331 = orr(_out_romask_T_331) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_331 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_331 = andr(_out_womask_T_331) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_331 = and(out_rivalid_1[209], out_rimask_331) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_331 = and(out_roready_1[209], out_romask_331) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_331 = and(out_wivalid_1[209], out_wimask_331) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_331 = and(out_woready_1[209], out_womask_331) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3541 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3542 = and(out_f_rivalid_331, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3543 = and(UInt<1>(0h1), out_f_roready_331) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3544 = eq(out_rimask_331, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3545 = eq(out_wimask_331, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3546 = eq(out_romask_331, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3547 = eq(out_womask_331, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_276 = or(_out_T_3540, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_276 = cat(_T_1443, _out_prepend_T_276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3548 = or(out_prepend_276, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3549 = bits(_out_T_3548, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_332 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_332 = orr(_out_rimask_T_332) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_332 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_332 = andr(_out_wimask_T_332) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_332 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_332 = orr(_out_romask_T_332) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_332 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_332 = andr(_out_womask_T_332) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_332 = and(out_rivalid_1[210], out_rimask_332) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_332 = and(out_roready_1[210], out_romask_332) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_332 = and(out_wivalid_1[210], out_wimask_332) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_332 = and(out_woready_1[210], out_womask_332) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3550 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3551 = and(out_f_rivalid_332, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3552 = and(UInt<1>(0h1), out_f_roready_332) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3553 = eq(out_rimask_332, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3554 = eq(out_wimask_332, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3555 = eq(out_romask_332, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3556 = eq(out_womask_332, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_277 = or(_out_T_3549, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_277 = cat(_T_1444, _out_prepend_T_277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3557 = or(out_prepend_277, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3558 = bits(_out_T_3557, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_333 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_333 = orr(_out_rimask_T_333) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_333 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_333 = andr(_out_wimask_T_333) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_333 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_333 = orr(_out_romask_T_333) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_333 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_333 = andr(_out_womask_T_333) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_333 = and(out_rivalid_1[211], out_rimask_333) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_333 = and(out_roready_1[211], out_romask_333) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_333 = and(out_wivalid_1[211], out_wimask_333) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_333 = and(out_woready_1[211], out_womask_333) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3559 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3560 = and(out_f_rivalid_333, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3561 = and(UInt<1>(0h1), out_f_roready_333) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3562 = eq(out_rimask_333, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3563 = eq(out_wimask_333, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3564 = eq(out_romask_333, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3565 = eq(out_womask_333, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_278 = or(_out_T_3558, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_278 = cat(_T_1445, _out_prepend_T_278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3566 = or(out_prepend_278, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3567 = bits(_out_T_3566, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_334 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_334 = orr(_out_rimask_T_334) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_334 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_334 = andr(_out_wimask_T_334) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_334 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_334 = orr(_out_romask_T_334) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_334 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_334 = andr(_out_womask_T_334) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_334 = and(out_rivalid_1[212], out_rimask_334) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_334 = and(out_roready_1[212], out_romask_334) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_334 = and(out_wivalid_1[212], out_wimask_334) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_334 = and(out_woready_1[212], out_womask_334) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3568 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3569 = and(out_f_rivalid_334, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3570 = and(UInt<1>(0h1), out_f_roready_334) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3571 = eq(out_rimask_334, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3572 = eq(out_wimask_334, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3573 = eq(out_romask_334, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3574 = eq(out_womask_334, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_279 = or(_out_T_3567, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_279 = cat(_T_1446, _out_prepend_T_279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3575 = or(out_prepend_279, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3576 = bits(_out_T_3575, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_335 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_335 = orr(_out_rimask_T_335) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_335 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_335 = andr(_out_wimask_T_335) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_335 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_335 = orr(_out_romask_T_335) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_335 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_335 = andr(_out_womask_T_335) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_335 = and(out_rivalid_1[213], out_rimask_335) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_335 = and(out_roready_1[213], out_romask_335) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_335 = and(out_wivalid_1[213], out_wimask_335) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_335 = and(out_woready_1[213], out_womask_335) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3577 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3578 = and(out_f_rivalid_335, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3579 = and(UInt<1>(0h1), out_f_roready_335) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3580 = eq(out_rimask_335, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3581 = eq(out_wimask_335, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3582 = eq(out_romask_335, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3583 = eq(out_womask_335, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_280 = or(_out_T_3576, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_280 = cat(_T_1447, _out_prepend_T_280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3584 = or(out_prepend_280, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3585 = bits(_out_T_3584, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_336 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_336 = orr(_out_rimask_T_336) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_336 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_336 = andr(_out_wimask_T_336) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_336 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_336 = orr(_out_romask_T_336) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_336 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_336 = andr(_out_womask_T_336) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_336 = and(out_rivalid_1[214], out_rimask_336) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_336 = and(out_roready_1[214], out_romask_336) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_336 = and(out_wivalid_1[214], out_wimask_336) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_336 = and(out_woready_1[214], out_womask_336) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3586 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3587 = and(out_f_rivalid_336, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3588 = and(UInt<1>(0h1), out_f_roready_336) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3589 = eq(out_rimask_336, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3590 = eq(out_wimask_336, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3591 = eq(out_romask_336, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3592 = eq(out_womask_336, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_281 = or(_out_T_3585, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_281 = cat(_T_1448, _out_prepend_T_281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3593 = or(out_prepend_281, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3594 = bits(_out_T_3593, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_337 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_337 = orr(_out_rimask_T_337) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_337 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_337 = andr(_out_wimask_T_337) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_337 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_337 = orr(_out_romask_T_337) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_337 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_337 = andr(_out_womask_T_337) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_337 = and(out_rivalid_1[215], out_rimask_337) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_337 = and(out_roready_1[215], out_romask_337) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_337 = and(out_wivalid_1[215], out_wimask_337) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_337 = and(out_woready_1[215], out_womask_337) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3595 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3596 = and(out_f_rivalid_337, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3597 = and(UInt<1>(0h1), out_f_roready_337) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3598 = eq(out_rimask_337, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3599 = eq(out_wimask_337, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3600 = eq(out_romask_337, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3601 = eq(out_womask_337, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_282 = or(_out_T_3594, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_282 = cat(_T_1449, _out_prepend_T_282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3602 = or(out_prepend_282, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3603 = bits(_out_T_3602, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_338 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_338 = orr(_out_rimask_T_338) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_338 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_338 = andr(_out_wimask_T_338) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_338 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_338 = orr(_out_romask_T_338) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_338 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_338 = andr(_out_womask_T_338) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_338 = and(out_rivalid_1[216], out_rimask_338) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_338 = and(out_roready_1[216], out_romask_338) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_338 = and(out_wivalid_1[216], out_wimask_338) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_338 = and(out_woready_1[216], out_womask_338) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3604 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3605 = and(out_f_rivalid_338, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3606 = and(UInt<1>(0h1), out_f_roready_338) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3607 = eq(out_rimask_338, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3608 = eq(out_wimask_338, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3609 = eq(out_romask_338, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3610 = eq(out_womask_338, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3611 = or(_T_594, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3612 = bits(_out_T_3611, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_339 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_339 = orr(_out_rimask_T_339) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_339 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_339 = andr(_out_wimask_T_339) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_339 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_339 = orr(_out_romask_T_339) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_339 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_339 = andr(_out_womask_T_339) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_339 = and(out_rivalid_1[217], out_rimask_339) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_339 = and(out_roready_1[217], out_romask_339) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_339 = and(out_wivalid_1[217], out_wimask_339) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_339 = and(out_woready_1[217], out_womask_339) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3613 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3614 = and(out_f_rivalid_339, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3615 = and(UInt<1>(0h1), out_f_roready_339) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3616 = eq(out_rimask_339, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3617 = eq(out_wimask_339, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3618 = eq(out_romask_339, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3619 = eq(out_womask_339, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_283 = or(_out_T_3612, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_283 = cat(_T_595, _out_prepend_T_283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3620 = or(out_prepend_283, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3621 = bits(_out_T_3620, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_340 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_340 = orr(_out_rimask_T_340) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_340 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_340 = andr(_out_wimask_T_340) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_340 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_340 = orr(_out_romask_T_340) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_340 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_340 = andr(_out_womask_T_340) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_340 = and(out_rivalid_1[218], out_rimask_340) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_340 = and(out_roready_1[218], out_romask_340) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_340 = and(out_wivalid_1[218], out_wimask_340) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_340 = and(out_woready_1[218], out_womask_340) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3622 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3623 = and(out_f_rivalid_340, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3624 = and(UInt<1>(0h1), out_f_roready_340) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3625 = eq(out_rimask_340, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3626 = eq(out_wimask_340, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3627 = eq(out_romask_340, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3628 = eq(out_womask_340, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_284 = or(_out_T_3621, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_284 = cat(_T_596, _out_prepend_T_284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3629 = or(out_prepend_284, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3630 = bits(_out_T_3629, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_341 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_341 = orr(_out_rimask_T_341) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_341 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_341 = andr(_out_wimask_T_341) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_341 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_341 = orr(_out_romask_T_341) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_341 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_341 = andr(_out_womask_T_341) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_341 = and(out_rivalid_1[219], out_rimask_341) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_341 = and(out_roready_1[219], out_romask_341) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_341 = and(out_wivalid_1[219], out_wimask_341) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_341 = and(out_woready_1[219], out_womask_341) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3631 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3632 = and(out_f_rivalid_341, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3633 = and(UInt<1>(0h1), out_f_roready_341) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3634 = eq(out_rimask_341, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3635 = eq(out_wimask_341, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3636 = eq(out_romask_341, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3637 = eq(out_womask_341, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_285 = or(_out_T_3630, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_285 = cat(_T_597, _out_prepend_T_285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3638 = or(out_prepend_285, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3639 = bits(_out_T_3638, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_342 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_342 = orr(_out_rimask_T_342) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_342 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_342 = andr(_out_wimask_T_342) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_342 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_342 = orr(_out_romask_T_342) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_342 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_342 = andr(_out_womask_T_342) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_342 = and(out_rivalid_1[220], out_rimask_342) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_342 = and(out_roready_1[220], out_romask_342) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_342 = and(out_wivalid_1[220], out_wimask_342) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_342 = and(out_woready_1[220], out_womask_342) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3640 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3641 = and(out_f_rivalid_342, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3642 = and(UInt<1>(0h1), out_f_roready_342) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3643 = eq(out_rimask_342, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3644 = eq(out_wimask_342, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3645 = eq(out_romask_342, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3646 = eq(out_womask_342, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_286 = or(_out_T_3639, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_286 = cat(_T_598, _out_prepend_T_286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3647 = or(out_prepend_286, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3648 = bits(_out_T_3647, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_343 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_343 = orr(_out_rimask_T_343) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_343 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_343 = andr(_out_wimask_T_343) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_343 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_343 = orr(_out_romask_T_343) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_343 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_343 = andr(_out_womask_T_343) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_343 = and(out_rivalid_1[221], out_rimask_343) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_343 = and(out_roready_1[221], out_romask_343) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_343 = and(out_wivalid_1[221], out_wimask_343) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_343 = and(out_woready_1[221], out_womask_343) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3649 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3650 = and(out_f_rivalid_343, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3651 = and(UInt<1>(0h1), out_f_roready_343) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3652 = eq(out_rimask_343, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3653 = eq(out_wimask_343, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3654 = eq(out_romask_343, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3655 = eq(out_womask_343, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_287 = or(_out_T_3648, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_287 = cat(_T_599, _out_prepend_T_287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3656 = or(out_prepend_287, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3657 = bits(_out_T_3656, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_344 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_344 = orr(_out_rimask_T_344) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_344 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_344 = andr(_out_wimask_T_344) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_344 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_344 = orr(_out_romask_T_344) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_344 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_344 = andr(_out_womask_T_344) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_344 = and(out_rivalid_1[222], out_rimask_344) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_344 = and(out_roready_1[222], out_romask_344) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_344 = and(out_wivalid_1[222], out_wimask_344) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_344 = and(out_woready_1[222], out_womask_344) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3658 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3659 = and(out_f_rivalid_344, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3660 = and(UInt<1>(0h1), out_f_roready_344) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3661 = eq(out_rimask_344, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3662 = eq(out_wimask_344, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3663 = eq(out_romask_344, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3664 = eq(out_womask_344, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_288 = or(_out_T_3657, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_288 = cat(_T_600, _out_prepend_T_288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3665 = or(out_prepend_288, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3666 = bits(_out_T_3665, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_345 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_345 = orr(_out_rimask_T_345) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_345 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_345 = andr(_out_wimask_T_345) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_345 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_345 = orr(_out_romask_T_345) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_345 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_345 = andr(_out_womask_T_345) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_345 = and(out_rivalid_1[223], out_rimask_345) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_345 = and(out_roready_1[223], out_romask_345) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_345 = and(out_wivalid_1[223], out_wimask_345) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_345 = and(out_woready_1[223], out_womask_345) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3667 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3668 = and(out_f_rivalid_345, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3669 = and(UInt<1>(0h1), out_f_roready_345) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3670 = eq(out_rimask_345, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3671 = eq(out_wimask_345, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3672 = eq(out_romask_345, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3673 = eq(out_womask_345, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_289 = or(_out_T_3666, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_289 = cat(_T_601, _out_prepend_T_289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3674 = or(out_prepend_289, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3675 = bits(_out_T_3674, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_346 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_346 = orr(_out_rimask_T_346) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_346 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_346 = andr(_out_wimask_T_346) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_346 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_346 = orr(_out_romask_T_346) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_346 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_346 = andr(_out_womask_T_346) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_346 = and(out_rivalid_1[224], out_rimask_346) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_346 = and(out_roready_1[224], out_romask_346) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_346 = and(out_wivalid_1[224], out_wimask_346) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_346 = and(out_woready_1[224], out_womask_346) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3676 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3677 = and(out_f_rivalid_346, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3678 = and(UInt<1>(0h1), out_f_roready_346) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3679 = eq(out_rimask_346, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3680 = eq(out_wimask_346, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3681 = eq(out_romask_346, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3682 = eq(out_womask_346, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3683 = or(_T_1186, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3684 = bits(_out_T_3683, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_347 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_347 = orr(_out_rimask_T_347) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_347 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_347 = andr(_out_wimask_T_347) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_347 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_347 = orr(_out_romask_T_347) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_347 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_347 = andr(_out_womask_T_347) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_347 = and(out_rivalid_1[225], out_rimask_347) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_347 = and(out_roready_1[225], out_romask_347) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_347 = and(out_wivalid_1[225], out_wimask_347) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_347 = and(out_woready_1[225], out_womask_347) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3685 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3686 = and(out_f_rivalid_347, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3687 = and(UInt<1>(0h1), out_f_roready_347) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3688 = eq(out_rimask_347, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3689 = eq(out_wimask_347, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3690 = eq(out_romask_347, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3691 = eq(out_womask_347, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_290 = or(_out_T_3684, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_290 = cat(_T_1187, _out_prepend_T_290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3692 = or(out_prepend_290, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3693 = bits(_out_T_3692, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_348 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_348 = orr(_out_rimask_T_348) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_348 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_348 = andr(_out_wimask_T_348) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_348 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_348 = orr(_out_romask_T_348) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_348 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_348 = andr(_out_womask_T_348) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_348 = and(out_rivalid_1[226], out_rimask_348) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_348 = and(out_roready_1[226], out_romask_348) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_348 = and(out_wivalid_1[226], out_wimask_348) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_348 = and(out_woready_1[226], out_womask_348) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3694 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3695 = and(out_f_rivalid_348, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3696 = and(UInt<1>(0h1), out_f_roready_348) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3697 = eq(out_rimask_348, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3698 = eq(out_wimask_348, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3699 = eq(out_romask_348, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3700 = eq(out_womask_348, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_291 = or(_out_T_3693, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_291 = cat(_T_1188, _out_prepend_T_291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3701 = or(out_prepend_291, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3702 = bits(_out_T_3701, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_349 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_349 = orr(_out_rimask_T_349) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_349 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_349 = andr(_out_wimask_T_349) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_349 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_349 = orr(_out_romask_T_349) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_349 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_349 = andr(_out_womask_T_349) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_349 = and(out_rivalid_1[227], out_rimask_349) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_349 = and(out_roready_1[227], out_romask_349) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_349 = and(out_wivalid_1[227], out_wimask_349) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_349 = and(out_woready_1[227], out_womask_349) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3703 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3704 = and(out_f_rivalid_349, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3705 = and(UInt<1>(0h1), out_f_roready_349) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3706 = eq(out_rimask_349, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3707 = eq(out_wimask_349, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3708 = eq(out_romask_349, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3709 = eq(out_womask_349, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_292 = or(_out_T_3702, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_292 = cat(_T_1189, _out_prepend_T_292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3710 = or(out_prepend_292, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3711 = bits(_out_T_3710, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_350 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_350 = orr(_out_rimask_T_350) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_350 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_350 = andr(_out_wimask_T_350) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_350 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_350 = orr(_out_romask_T_350) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_350 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_350 = andr(_out_womask_T_350) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_350 = and(out_rivalid_1[228], out_rimask_350) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_350 = and(out_roready_1[228], out_romask_350) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_350 = and(out_wivalid_1[228], out_wimask_350) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_350 = and(out_woready_1[228], out_womask_350) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3712 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3713 = and(out_f_rivalid_350, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3714 = and(UInt<1>(0h1), out_f_roready_350) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3715 = eq(out_rimask_350, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3716 = eq(out_wimask_350, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3717 = eq(out_romask_350, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3718 = eq(out_womask_350, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_293 = or(_out_T_3711, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_293 = cat(_T_1190, _out_prepend_T_293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3719 = or(out_prepend_293, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3720 = bits(_out_T_3719, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_351 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_351 = orr(_out_rimask_T_351) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_351 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_351 = andr(_out_wimask_T_351) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_351 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_351 = orr(_out_romask_T_351) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_351 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_351 = andr(_out_womask_T_351) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_351 = and(out_rivalid_1[229], out_rimask_351) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_351 = and(out_roready_1[229], out_romask_351) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_351 = and(out_wivalid_1[229], out_wimask_351) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_351 = and(out_woready_1[229], out_womask_351) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3721 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3722 = and(out_f_rivalid_351, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3723 = and(UInt<1>(0h1), out_f_roready_351) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3724 = eq(out_rimask_351, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3725 = eq(out_wimask_351, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3726 = eq(out_romask_351, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3727 = eq(out_womask_351, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_294 = or(_out_T_3720, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_294 = cat(_T_1191, _out_prepend_T_294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3728 = or(out_prepend_294, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3729 = bits(_out_T_3728, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_352 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_352 = orr(_out_rimask_T_352) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_352 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_352 = andr(_out_wimask_T_352) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_352 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_352 = orr(_out_romask_T_352) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_352 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_352 = andr(_out_womask_T_352) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_352 = and(out_rivalid_1[230], out_rimask_352) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_352 = and(out_roready_1[230], out_romask_352) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_352 = and(out_wivalid_1[230], out_wimask_352) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_352 = and(out_woready_1[230], out_womask_352) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3730 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3731 = and(out_f_rivalid_352, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3732 = and(UInt<1>(0h1), out_f_roready_352) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3733 = eq(out_rimask_352, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3734 = eq(out_wimask_352, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3735 = eq(out_romask_352, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3736 = eq(out_womask_352, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_295 = or(_out_T_3729, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_295 = cat(_T_1192, _out_prepend_T_295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3737 = or(out_prepend_295, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3738 = bits(_out_T_3737, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_353 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_353 = orr(_out_rimask_T_353) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_353 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_353 = andr(_out_wimask_T_353) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_353 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_353 = orr(_out_romask_T_353) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_353 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_353 = andr(_out_womask_T_353) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_353 = and(out_rivalid_1[231], out_rimask_353) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_353 = and(out_roready_1[231], out_romask_353) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_353 = and(out_wivalid_1[231], out_wimask_353) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_353 = and(out_woready_1[231], out_womask_353) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3739 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3740 = and(out_f_rivalid_353, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3741 = and(UInt<1>(0h1), out_f_roready_353) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3742 = eq(out_rimask_353, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3743 = eq(out_wimask_353, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3744 = eq(out_romask_353, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3745 = eq(out_womask_353, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_296 = or(_out_T_3738, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_296 = cat(_T_1193, _out_prepend_T_296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3746 = or(out_prepend_296, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3747 = bits(_out_T_3746, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_354 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_354 = orr(_out_rimask_T_354) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_354 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_354 = andr(_out_wimask_T_354) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_354 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_354 = orr(_out_romask_T_354) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_354 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_354 = andr(_out_womask_T_354) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_354 = and(out_rivalid_1[232], out_rimask_354) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_354 = and(out_roready_1[232], out_romask_354) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_354 = and(out_wivalid_1[232], out_wimask_354) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_354 = and(out_woready_1[232], out_womask_354) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3748 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3749 = and(out_f_rivalid_354, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3750 = and(UInt<1>(0h1), out_f_roready_354) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3751 = eq(out_rimask_354, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3752 = eq(out_wimask_354, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3753 = eq(out_romask_354, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3754 = eq(out_womask_354, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3755 = or(_T_474, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3756 = bits(_out_T_3755, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_355 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_355 = orr(_out_rimask_T_355) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_355 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_355 = andr(_out_wimask_T_355) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_355 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_355 = orr(_out_romask_T_355) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_355 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_355 = andr(_out_womask_T_355) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_355 = and(out_rivalid_1[233], out_rimask_355) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_355 = and(out_roready_1[233], out_romask_355) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_355 = and(out_wivalid_1[233], out_wimask_355) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_355 = and(out_woready_1[233], out_womask_355) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3757 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3758 = and(out_f_rivalid_355, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3759 = and(UInt<1>(0h1), out_f_roready_355) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3760 = eq(out_rimask_355, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3761 = eq(out_wimask_355, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3762 = eq(out_romask_355, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3763 = eq(out_womask_355, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_297 = or(_out_T_3756, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_297 = cat(_T_475, _out_prepend_T_297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3764 = or(out_prepend_297, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3765 = bits(_out_T_3764, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_356 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_356 = orr(_out_rimask_T_356) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_356 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_356 = andr(_out_wimask_T_356) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_356 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_356 = orr(_out_romask_T_356) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_356 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_356 = andr(_out_womask_T_356) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_356 = and(out_rivalid_1[234], out_rimask_356) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_356 = and(out_roready_1[234], out_romask_356) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_356 = and(out_wivalid_1[234], out_wimask_356) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_356 = and(out_woready_1[234], out_womask_356) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3766 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3767 = and(out_f_rivalid_356, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3768 = and(UInt<1>(0h1), out_f_roready_356) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3769 = eq(out_rimask_356, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3770 = eq(out_wimask_356, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3771 = eq(out_romask_356, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3772 = eq(out_womask_356, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_298 = or(_out_T_3765, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_298 = cat(_T_476, _out_prepend_T_298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3773 = or(out_prepend_298, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3774 = bits(_out_T_3773, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_357 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_357 = orr(_out_rimask_T_357) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_357 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_357 = andr(_out_wimask_T_357) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_357 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_357 = orr(_out_romask_T_357) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_357 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_357 = andr(_out_womask_T_357) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_357 = and(out_rivalid_1[235], out_rimask_357) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_357 = and(out_roready_1[235], out_romask_357) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_357 = and(out_wivalid_1[235], out_wimask_357) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_357 = and(out_woready_1[235], out_womask_357) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3775 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3776 = and(out_f_rivalid_357, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3777 = and(UInt<1>(0h1), out_f_roready_357) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3778 = eq(out_rimask_357, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3779 = eq(out_wimask_357, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3780 = eq(out_romask_357, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3781 = eq(out_womask_357, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_299 = or(_out_T_3774, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_299 = cat(_T_477, _out_prepend_T_299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3782 = or(out_prepend_299, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3783 = bits(_out_T_3782, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_358 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_358 = orr(_out_rimask_T_358) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_358 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_358 = andr(_out_wimask_T_358) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_358 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_358 = orr(_out_romask_T_358) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_358 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_358 = andr(_out_womask_T_358) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_358 = and(out_rivalid_1[236], out_rimask_358) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_358 = and(out_roready_1[236], out_romask_358) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_358 = and(out_wivalid_1[236], out_wimask_358) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_358 = and(out_woready_1[236], out_womask_358) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3784 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3785 = and(out_f_rivalid_358, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3786 = and(UInt<1>(0h1), out_f_roready_358) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3787 = eq(out_rimask_358, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3788 = eq(out_wimask_358, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3789 = eq(out_romask_358, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3790 = eq(out_womask_358, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_300 = or(_out_T_3783, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_300 = cat(_T_478, _out_prepend_T_300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3791 = or(out_prepend_300, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3792 = bits(_out_T_3791, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_359 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_359 = orr(_out_rimask_T_359) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_359 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_359 = andr(_out_wimask_T_359) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_359 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_359 = orr(_out_romask_T_359) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_359 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_359 = andr(_out_womask_T_359) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_359 = and(out_rivalid_1[237], out_rimask_359) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_359 = and(out_roready_1[237], out_romask_359) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_359 = and(out_wivalid_1[237], out_wimask_359) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_359 = and(out_woready_1[237], out_womask_359) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3793 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3794 = and(out_f_rivalid_359, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3795 = and(UInt<1>(0h1), out_f_roready_359) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3796 = eq(out_rimask_359, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3797 = eq(out_wimask_359, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3798 = eq(out_romask_359, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3799 = eq(out_womask_359, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_301 = or(_out_T_3792, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_301 = cat(_T_479, _out_prepend_T_301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3800 = or(out_prepend_301, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3801 = bits(_out_T_3800, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_360 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_360 = orr(_out_rimask_T_360) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_360 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_360 = andr(_out_wimask_T_360) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_360 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_360 = orr(_out_romask_T_360) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_360 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_360 = andr(_out_womask_T_360) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_360 = and(out_rivalid_1[238], out_rimask_360) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_360 = and(out_roready_1[238], out_romask_360) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_360 = and(out_wivalid_1[238], out_wimask_360) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_360 = and(out_woready_1[238], out_womask_360) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3802 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3803 = and(out_f_rivalid_360, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3804 = and(UInt<1>(0h1), out_f_roready_360) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3805 = eq(out_rimask_360, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3806 = eq(out_wimask_360, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3807 = eq(out_romask_360, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3808 = eq(out_womask_360, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_302 = or(_out_T_3801, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_302 = cat(_T_480, _out_prepend_T_302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3809 = or(out_prepend_302, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3810 = bits(_out_T_3809, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_361 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_361 = orr(_out_rimask_T_361) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_361 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_361 = andr(_out_wimask_T_361) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_361 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_361 = orr(_out_romask_T_361) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_361 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_361 = andr(_out_womask_T_361) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_361 = and(out_rivalid_1[239], out_rimask_361) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_361 = and(out_roready_1[239], out_romask_361) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_361 = and(out_wivalid_1[239], out_wimask_361) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_361 = and(out_woready_1[239], out_womask_361) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3811 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3812 = and(out_f_rivalid_361, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3813 = and(UInt<1>(0h1), out_f_roready_361) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3814 = eq(out_rimask_361, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3815 = eq(out_wimask_361, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3816 = eq(out_romask_361, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3817 = eq(out_womask_361, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_303 = or(_out_T_3810, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_303 = cat(_T_481, _out_prepend_T_303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3818 = or(out_prepend_303, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3819 = bits(_out_T_3818, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_362 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_362 = orr(_out_rimask_T_362) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_362 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_362 = andr(_out_wimask_T_362) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_362 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_362 = orr(_out_romask_T_362) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_362 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_362 = andr(_out_womask_T_362) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_362 = and(out_rivalid_1[240], out_rimask_362) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_362 = and(out_roready_1[240], out_romask_362) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_362 = and(out_wivalid_1[240], out_wimask_362) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_362 = and(out_woready_1[240], out_womask_362) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3820 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3821 = and(out_f_rivalid_362, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3822 = and(UInt<1>(0h1), out_f_roready_362) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3823 = eq(out_rimask_362, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3824 = eq(out_wimask_362, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3825 = eq(out_romask_362, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3826 = eq(out_womask_362, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3827 = or(_T_482, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3828 = bits(_out_T_3827, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_363 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_363 = orr(_out_rimask_T_363) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_363 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_363 = andr(_out_wimask_T_363) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_363 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_363 = orr(_out_romask_T_363) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_363 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_363 = andr(_out_womask_T_363) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_363 = and(out_rivalid_1[241], out_rimask_363) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_363 = and(out_roready_1[241], out_romask_363) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_363 = and(out_wivalid_1[241], out_wimask_363) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_363 = and(out_woready_1[241], out_womask_363) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3829 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3830 = and(out_f_rivalid_363, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3831 = and(UInt<1>(0h1), out_f_roready_363) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3832 = eq(out_rimask_363, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3833 = eq(out_wimask_363, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3834 = eq(out_romask_363, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3835 = eq(out_womask_363, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_304 = or(_out_T_3828, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_304 = cat(_T_483, _out_prepend_T_304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3836 = or(out_prepend_304, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3837 = bits(_out_T_3836, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_364 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_364 = orr(_out_rimask_T_364) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_364 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_364 = andr(_out_wimask_T_364) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_364 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_364 = orr(_out_romask_T_364) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_364 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_364 = andr(_out_womask_T_364) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_364 = and(out_rivalid_1[242], out_rimask_364) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_364 = and(out_roready_1[242], out_romask_364) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_364 = and(out_wivalid_1[242], out_wimask_364) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_364 = and(out_woready_1[242], out_womask_364) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3838 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3839 = and(out_f_rivalid_364, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3840 = and(UInt<1>(0h1), out_f_roready_364) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3841 = eq(out_rimask_364, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3842 = eq(out_wimask_364, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3843 = eq(out_romask_364, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3844 = eq(out_womask_364, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_305 = or(_out_T_3837, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_305 = cat(_T_484, _out_prepend_T_305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3845 = or(out_prepend_305, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3846 = bits(_out_T_3845, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_365 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_365 = orr(_out_rimask_T_365) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_365 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_365 = andr(_out_wimask_T_365) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_365 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_365 = orr(_out_romask_T_365) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_365 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_365 = andr(_out_womask_T_365) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_365 = and(out_rivalid_1[243], out_rimask_365) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_365 = and(out_roready_1[243], out_romask_365) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_365 = and(out_wivalid_1[243], out_wimask_365) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_365 = and(out_woready_1[243], out_womask_365) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3847 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3848 = and(out_f_rivalid_365, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3849 = and(UInt<1>(0h1), out_f_roready_365) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3850 = eq(out_rimask_365, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3851 = eq(out_wimask_365, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3852 = eq(out_romask_365, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3853 = eq(out_womask_365, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_306 = or(_out_T_3846, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_306 = cat(_T_485, _out_prepend_T_306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3854 = or(out_prepend_306, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3855 = bits(_out_T_3854, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_366 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_366 = orr(_out_rimask_T_366) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_366 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_366 = andr(_out_wimask_T_366) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_366 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_366 = orr(_out_romask_T_366) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_366 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_366 = andr(_out_womask_T_366) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_366 = and(out_rivalid_1[244], out_rimask_366) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_366 = and(out_roready_1[244], out_romask_366) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_366 = and(out_wivalid_1[244], out_wimask_366) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_366 = and(out_woready_1[244], out_womask_366) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3856 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3857 = and(out_f_rivalid_366, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3858 = and(UInt<1>(0h1), out_f_roready_366) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3859 = eq(out_rimask_366, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3860 = eq(out_wimask_366, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3861 = eq(out_romask_366, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3862 = eq(out_womask_366, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_307 = or(_out_T_3855, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_307 = cat(_T_486, _out_prepend_T_307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3863 = or(out_prepend_307, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3864 = bits(_out_T_3863, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_367 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_367 = orr(_out_rimask_T_367) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_367 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_367 = andr(_out_wimask_T_367) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_367 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_367 = orr(_out_romask_T_367) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_367 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_367 = andr(_out_womask_T_367) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_367 = and(out_rivalid_1[245], out_rimask_367) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_367 = and(out_roready_1[245], out_romask_367) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_367 = and(out_wivalid_1[245], out_wimask_367) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_367 = and(out_woready_1[245], out_womask_367) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3865 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3866 = and(out_f_rivalid_367, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3867 = and(UInt<1>(0h1), out_f_roready_367) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3868 = eq(out_rimask_367, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3869 = eq(out_wimask_367, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3870 = eq(out_romask_367, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3871 = eq(out_womask_367, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_308 = or(_out_T_3864, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_308 = cat(_T_487, _out_prepend_T_308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3872 = or(out_prepend_308, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3873 = bits(_out_T_3872, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_368 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_368 = orr(_out_rimask_T_368) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_368 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_368 = andr(_out_wimask_T_368) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_368 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_368 = orr(_out_romask_T_368) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_368 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_368 = andr(_out_womask_T_368) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_368 = and(out_rivalid_1[246], out_rimask_368) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_368 = and(out_roready_1[246], out_romask_368) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_368 = and(out_wivalid_1[246], out_wimask_368) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_368 = and(out_woready_1[246], out_womask_368) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3874 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3875 = and(out_f_rivalid_368, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3876 = and(UInt<1>(0h1), out_f_roready_368) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3877 = eq(out_rimask_368, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3878 = eq(out_wimask_368, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3879 = eq(out_romask_368, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3880 = eq(out_womask_368, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_309 = or(_out_T_3873, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_309 = cat(_T_488, _out_prepend_T_309) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3881 = or(out_prepend_309, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3882 = bits(_out_T_3881, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_369 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_369 = orr(_out_rimask_T_369) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_369 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_369 = andr(_out_wimask_T_369) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_369 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_369 = orr(_out_romask_T_369) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_369 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_369 = andr(_out_womask_T_369) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_369 = and(out_rivalid_1[247], out_rimask_369) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_369 = and(out_roready_1[247], out_romask_369) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_369 = and(out_wivalid_1[247], out_wimask_369) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_369 = and(out_woready_1[247], out_womask_369) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3883 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3884 = and(out_f_rivalid_369, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3885 = and(UInt<1>(0h1), out_f_roready_369) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3886 = eq(out_rimask_369, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3887 = eq(out_wimask_369, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3888 = eq(out_romask_369, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3889 = eq(out_womask_369, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_310 = or(_out_T_3882, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_310 = cat(_T_489, _out_prepend_T_310) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3890 = or(out_prepend_310, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3891 = bits(_out_T_3890, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_370 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_370 = orr(_out_rimask_T_370) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_370 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_370 = andr(_out_wimask_T_370) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_370 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_370 = orr(_out_romask_T_370) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_370 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_370 = andr(_out_womask_T_370) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_370 = and(out_rivalid_1[248], out_rimask_370) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_370 = and(out_roready_1[248], out_romask_370) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_370 = and(out_wivalid_1[248], out_wimask_370) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_370 = and(out_woready_1[248], out_womask_370) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3892 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3893 = and(out_f_rivalid_370, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3894 = and(UInt<1>(0h1), out_f_roready_370) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3895 = eq(out_rimask_370, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3896 = eq(out_wimask_370, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3897 = eq(out_romask_370, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3898 = eq(out_womask_370, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3899 = or(_T_1362, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3900 = bits(_out_T_3899, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_371 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_371 = orr(_out_rimask_T_371) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_371 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_371 = andr(_out_wimask_T_371) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_371 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_371 = orr(_out_romask_T_371) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_371 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_371 = andr(_out_womask_T_371) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_371 = and(out_rivalid_1[249], out_rimask_371) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_371 = and(out_roready_1[249], out_romask_371) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_371 = and(out_wivalid_1[249], out_wimask_371) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_371 = and(out_woready_1[249], out_womask_371) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3901 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3902 = and(out_f_rivalid_371, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3903 = and(UInt<1>(0h1), out_f_roready_371) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3904 = eq(out_rimask_371, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3905 = eq(out_wimask_371, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3906 = eq(out_romask_371, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3907 = eq(out_womask_371, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_311 = or(_out_T_3900, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_311 = cat(_T_1363, _out_prepend_T_311) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3908 = or(out_prepend_311, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3909 = bits(_out_T_3908, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_372 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_372 = orr(_out_rimask_T_372) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_372 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_372 = andr(_out_wimask_T_372) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_372 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_372 = orr(_out_romask_T_372) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_372 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_372 = andr(_out_womask_T_372) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_372 = and(out_rivalid_1[250], out_rimask_372) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_372 = and(out_roready_1[250], out_romask_372) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_372 = and(out_wivalid_1[250], out_wimask_372) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_372 = and(out_woready_1[250], out_womask_372) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3910 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3911 = and(out_f_rivalid_372, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3912 = and(UInt<1>(0h1), out_f_roready_372) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3913 = eq(out_rimask_372, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3914 = eq(out_wimask_372, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3915 = eq(out_romask_372, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3916 = eq(out_womask_372, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_312 = or(_out_T_3909, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_312 = cat(_T_1364, _out_prepend_T_312) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3917 = or(out_prepend_312, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3918 = bits(_out_T_3917, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_373 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_373 = orr(_out_rimask_T_373) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_373 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_373 = andr(_out_wimask_T_373) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_373 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_373 = orr(_out_romask_T_373) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_373 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_373 = andr(_out_womask_T_373) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_373 = and(out_rivalid_1[251], out_rimask_373) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_373 = and(out_roready_1[251], out_romask_373) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_373 = and(out_wivalid_1[251], out_wimask_373) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_373 = and(out_woready_1[251], out_womask_373) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3919 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3920 = and(out_f_rivalid_373, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3921 = and(UInt<1>(0h1), out_f_roready_373) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3922 = eq(out_rimask_373, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3923 = eq(out_wimask_373, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3924 = eq(out_romask_373, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3925 = eq(out_womask_373, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_313 = or(_out_T_3918, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_313 = cat(_T_1365, _out_prepend_T_313) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3926 = or(out_prepend_313, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3927 = bits(_out_T_3926, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_374 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_374 = orr(_out_rimask_T_374) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_374 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_374 = andr(_out_wimask_T_374) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_374 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_374 = orr(_out_romask_T_374) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_374 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_374 = andr(_out_womask_T_374) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_374 = and(out_rivalid_1[252], out_rimask_374) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_374 = and(out_roready_1[252], out_romask_374) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_374 = and(out_wivalid_1[252], out_wimask_374) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_374 = and(out_woready_1[252], out_womask_374) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3928 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3929 = and(out_f_rivalid_374, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3930 = and(UInt<1>(0h1), out_f_roready_374) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3931 = eq(out_rimask_374, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3932 = eq(out_wimask_374, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3933 = eq(out_romask_374, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3934 = eq(out_womask_374, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_314 = or(_out_T_3927, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_314 = cat(_T_1366, _out_prepend_T_314) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3935 = or(out_prepend_314, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3936 = bits(_out_T_3935, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_375 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_375 = orr(_out_rimask_T_375) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_375 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_375 = andr(_out_wimask_T_375) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_375 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_375 = orr(_out_romask_T_375) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_375 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_375 = andr(_out_womask_T_375) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_375 = and(out_rivalid_1[253], out_rimask_375) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_375 = and(out_roready_1[253], out_romask_375) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_375 = and(out_wivalid_1[253], out_wimask_375) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_375 = and(out_woready_1[253], out_womask_375) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3937 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3938 = and(out_f_rivalid_375, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3939 = and(UInt<1>(0h1), out_f_roready_375) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3940 = eq(out_rimask_375, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3941 = eq(out_wimask_375, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3942 = eq(out_romask_375, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3943 = eq(out_womask_375, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_315 = or(_out_T_3936, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_315 = cat(_T_1367, _out_prepend_T_315) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3944 = or(out_prepend_315, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3945 = bits(_out_T_3944, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_376 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_376 = orr(_out_rimask_T_376) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_376 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_376 = andr(_out_wimask_T_376) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_376 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_376 = orr(_out_romask_T_376) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_376 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_376 = andr(_out_womask_T_376) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_376 = and(out_rivalid_1[254], out_rimask_376) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_376 = and(out_roready_1[254], out_romask_376) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_376 = and(out_wivalid_1[254], out_wimask_376) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_376 = and(out_woready_1[254], out_womask_376) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3946 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3947 = and(out_f_rivalid_376, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3948 = and(UInt<1>(0h1), out_f_roready_376) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3949 = eq(out_rimask_376, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3950 = eq(out_wimask_376, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3951 = eq(out_romask_376, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3952 = eq(out_womask_376, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_316 = or(_out_T_3945, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_316 = cat(_T_1368, _out_prepend_T_316) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3953 = or(out_prepend_316, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3954 = bits(_out_T_3953, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_377 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_377 = orr(_out_rimask_T_377) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_377 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_377 = andr(_out_wimask_T_377) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_377 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_377 = orr(_out_romask_T_377) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_377 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_377 = andr(_out_womask_T_377) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_377 = and(out_rivalid_1[255], out_rimask_377) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_377 = and(out_roready_1[255], out_romask_377) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_377 = and(out_wivalid_1[255], out_wimask_377) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_377 = and(out_woready_1[255], out_womask_377) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3955 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3956 = and(out_f_rivalid_377, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3957 = and(UInt<1>(0h1), out_f_roready_377) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3958 = eq(out_rimask_377, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3959 = eq(out_wimask_377, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3960 = eq(out_romask_377, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3961 = eq(out_womask_377, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_317 = or(_out_T_3954, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_317 = cat(_T_1369, _out_prepend_T_317) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3962 = or(out_prepend_317, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3963 = bits(_out_T_3962, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_378 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_378 = orr(_out_rimask_T_378) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_378 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_378 = andr(_out_wimask_T_378) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_378 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_378 = orr(_out_romask_T_378) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_378 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_378 = andr(_out_womask_T_378) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_378 = and(out_rivalid_1[256], out_rimask_378) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_378 = and(out_roready_1[256], out_romask_378) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_378 = and(out_wivalid_1[256], out_wimask_378) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_378 = and(out_woready_1[256], out_womask_378) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3964 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3965 = and(out_f_rivalid_378, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3966 = and(UInt<1>(0h1), out_f_roready_378) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3967 = eq(out_rimask_378, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3968 = eq(out_wimask_378, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3969 = eq(out_romask_378, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3970 = eq(out_womask_378, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3971 = or(UInt<8>(0h73), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3972 = bits(_out_T_3971, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_379 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_379 = orr(_out_rimask_T_379) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_379 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_379 = andr(_out_wimask_T_379) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_379 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_379 = orr(_out_romask_T_379) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_379 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_379 = andr(_out_womask_T_379) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_379 = and(out_rivalid_1[257], out_rimask_379) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_379 = and(out_roready_1[257], out_romask_379) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_379 = and(out_wivalid_1[257], out_wimask_379) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_379 = and(out_woready_1[257], out_womask_379) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3973 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3974 = and(out_f_rivalid_379, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3975 = and(UInt<1>(0h1), out_f_roready_379) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3976 = eq(out_rimask_379, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3977 = eq(out_wimask_379, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3978 = eq(out_romask_379, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3979 = eq(out_womask_379, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_318 = or(_out_T_3972, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_318 = cat(UInt<8>(0h0), _out_prepend_T_318) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3980 = or(out_prepend_318, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3981 = bits(_out_T_3980, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_380 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_380 = orr(_out_rimask_T_380) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_380 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_380 = andr(_out_wimask_T_380) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_380 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_380 = orr(_out_romask_T_380) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_380 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_380 = andr(_out_womask_T_380) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_380 = and(out_rivalid_1[258], out_rimask_380) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_380 = and(out_roready_1[258], out_romask_380) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_380 = and(out_wivalid_1[258], out_wimask_380) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_380 = and(out_woready_1[258], out_womask_380) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3982 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3983 = and(out_f_rivalid_380, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3984 = and(UInt<1>(0h1), out_f_roready_380) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3985 = eq(out_rimask_380, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3986 = eq(out_wimask_380, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3987 = eq(out_romask_380, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3988 = eq(out_womask_380, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_319 = or(_out_T_3981, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_319 = cat(UInt<8>(0h20), _out_prepend_T_319) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3989 = or(out_prepend_319, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3990 = bits(_out_T_3989, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_381 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_381 = orr(_out_rimask_T_381) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_381 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_381 = andr(_out_wimask_T_381) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_381 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_381 = orr(_out_romask_T_381) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_381 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_381 = andr(_out_womask_T_381) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_381 = and(out_rivalid_1[259], out_rimask_381) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_381 = and(out_roready_1[259], out_romask_381) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_381 = and(out_wivalid_1[259], out_wimask_381) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_381 = and(out_woready_1[259], out_womask_381) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3991 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3992 = and(out_f_rivalid_381, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3993 = and(UInt<1>(0h1), out_f_roready_381) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3994 = eq(out_rimask_381, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3995 = eq(out_wimask_381, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3996 = eq(out_romask_381, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3997 = eq(out_womask_381, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_320 = or(_out_T_3990, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_320 = cat(UInt<8>(0h7b), _out_prepend_T_320) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3998 = or(out_prepend_320, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3999 = bits(_out_T_3998, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_382 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_382 = orr(_out_rimask_T_382) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_382 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_382 = andr(_out_wimask_T_382) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_382 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_382 = orr(_out_romask_T_382) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_382 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_382 = andr(_out_womask_T_382) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_382 = and(out_rivalid_1[260], out_rimask_382) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_382 = and(out_roready_1[260], out_romask_382) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_382 = and(out_wivalid_1[260], out_wimask_382) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_382 = and(out_woready_1[260], out_womask_382) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4000 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4001 = and(out_f_rivalid_382, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4002 = and(UInt<1>(0h1), out_f_roready_382) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4003 = eq(out_rimask_382, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4004 = eq(out_wimask_382, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4005 = eq(out_romask_382, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4006 = eq(out_womask_382, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_321 = or(_out_T_3999, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_321 = cat(UInt<8>(0h23), _out_prepend_T_321) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4007 = or(out_prepend_321, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4008 = bits(_out_T_4007, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_383 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_383 = orr(_out_rimask_T_383) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_383 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_383 = andr(_out_wimask_T_383) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_383 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_383 = orr(_out_romask_T_383) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_383 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_383 = andr(_out_womask_T_383) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_383 = and(out_rivalid_1[261], out_rimask_383) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_383 = and(out_roready_1[261], out_romask_383) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_383 = and(out_wivalid_1[261], out_wimask_383) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_383 = and(out_woready_1[261], out_womask_383) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4009 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4010 = and(out_f_rivalid_383, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4011 = and(UInt<1>(0h1), out_f_roready_383) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4012 = eq(out_rimask_383, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4013 = eq(out_wimask_383, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4014 = eq(out_romask_383, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4015 = eq(out_womask_383, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_322 = or(_out_T_4008, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_322 = cat(UInt<8>(0h26), _out_prepend_T_322) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4016 = or(out_prepend_322, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4017 = bits(_out_T_4016, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_384 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_384 = orr(_out_rimask_T_384) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_384 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_384 = andr(_out_wimask_T_384) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_384 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_384 = orr(_out_romask_T_384) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_384 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_384 = andr(_out_womask_T_384) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_384 = and(out_rivalid_1[262], out_rimask_384) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_384 = and(out_roready_1[262], out_romask_384) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_384 = and(out_wivalid_1[262], out_wimask_384) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_384 = and(out_woready_1[262], out_womask_384) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4018 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4019 = and(out_f_rivalid_384, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4020 = and(UInt<1>(0h1), out_f_roready_384) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4021 = eq(out_rimask_384, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4022 = eq(out_wimask_384, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4023 = eq(out_romask_384, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4024 = eq(out_womask_384, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_323 = or(_out_T_4017, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_323 = cat(UInt<8>(0h0), _out_prepend_T_323) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4025 = or(out_prepend_323, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4026 = bits(_out_T_4025, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_385 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_385 = orr(_out_rimask_T_385) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_385 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_385 = andr(_out_wimask_T_385) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_385 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_385 = orr(_out_romask_T_385) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_385 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_385 = andr(_out_womask_T_385) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_385 = and(out_rivalid_1[263], out_rimask_385) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_385 = and(out_roready_1[263], out_romask_385) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_385 = and(out_wivalid_1[263], out_wimask_385) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_385 = and(out_woready_1[263], out_womask_385) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4027 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4028 = and(out_f_rivalid_385, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4029 = and(UInt<1>(0h1), out_f_roready_385) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4030 = eq(out_rimask_385, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4031 = eq(out_wimask_385, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4032 = eq(out_romask_385, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4033 = eq(out_womask_385, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_324 = or(_out_T_4026, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_324 = cat(UInt<8>(0h10), _out_prepend_T_324) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4034 = or(out_prepend_324, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4035 = bits(_out_T_4034, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_386 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_386 = orr(_out_rimask_T_386) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_386 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_386 = andr(_out_wimask_T_386) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_386 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_386 = orr(_out_romask_T_386) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_386 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_386 = andr(_out_womask_T_386) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_386 = and(out_rivalid_1[264], out_rimask_386) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_386 = and(out_roready_1[264], out_romask_386) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_386 = and(out_wivalid_1[264], out_wimask_386) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_386 = and(out_woready_1[264], out_womask_386) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4036 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4037 = and(out_f_rivalid_386, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4038 = and(UInt<1>(0h1), out_f_roready_386) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4039 = eq(out_rimask_386, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4040 = eq(out_wimask_386, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4041 = eq(out_romask_386, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4042 = eq(out_womask_386, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4043 = or(_T_1066, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4044 = bits(_out_T_4043, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_387 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_387 = orr(_out_rimask_T_387) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_387 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_387 = andr(_out_wimask_T_387) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_387 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_387 = orr(_out_romask_T_387) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_387 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_387 = andr(_out_womask_T_387) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_387 = and(out_rivalid_1[265], out_rimask_387) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_387 = and(out_roready_1[265], out_romask_387) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_387 = and(out_wivalid_1[265], out_wimask_387) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_387 = and(out_woready_1[265], out_womask_387) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4045 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4046 = and(out_f_rivalid_387, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4047 = and(UInt<1>(0h1), out_f_roready_387) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4048 = eq(out_rimask_387, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4049 = eq(out_wimask_387, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4050 = eq(out_romask_387, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4051 = eq(out_womask_387, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_325 = or(_out_T_4044, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_325 = cat(_T_1067, _out_prepend_T_325) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4052 = or(out_prepend_325, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4053 = bits(_out_T_4052, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_388 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_388 = orr(_out_rimask_T_388) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_388 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_388 = andr(_out_wimask_T_388) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_388 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_388 = orr(_out_romask_T_388) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_388 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_388 = andr(_out_womask_T_388) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_388 = and(out_rivalid_1[266], out_rimask_388) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_388 = and(out_roready_1[266], out_romask_388) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_388 = and(out_wivalid_1[266], out_wimask_388) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_388 = and(out_woready_1[266], out_womask_388) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4054 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4055 = and(out_f_rivalid_388, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4056 = and(UInt<1>(0h1), out_f_roready_388) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4057 = eq(out_rimask_388, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4058 = eq(out_wimask_388, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4059 = eq(out_romask_388, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4060 = eq(out_womask_388, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_326 = or(_out_T_4053, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_326 = cat(_T_1068, _out_prepend_T_326) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4061 = or(out_prepend_326, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4062 = bits(_out_T_4061, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_389 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_389 = orr(_out_rimask_T_389) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_389 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_389 = andr(_out_wimask_T_389) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_389 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_389 = orr(_out_romask_T_389) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_389 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_389 = andr(_out_womask_T_389) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_389 = and(out_rivalid_1[267], out_rimask_389) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_389 = and(out_roready_1[267], out_romask_389) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_389 = and(out_wivalid_1[267], out_wimask_389) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_389 = and(out_woready_1[267], out_womask_389) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4063 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4064 = and(out_f_rivalid_389, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4065 = and(UInt<1>(0h1), out_f_roready_389) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4066 = eq(out_rimask_389, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4067 = eq(out_wimask_389, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4068 = eq(out_romask_389, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4069 = eq(out_womask_389, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_327 = or(_out_T_4062, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_327 = cat(_T_1069, _out_prepend_T_327) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4070 = or(out_prepend_327, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4071 = bits(_out_T_4070, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_390 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_390 = orr(_out_rimask_T_390) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_390 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_390 = andr(_out_wimask_T_390) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_390 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_390 = orr(_out_romask_T_390) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_390 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_390 = andr(_out_womask_T_390) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_390 = and(out_rivalid_1[268], out_rimask_390) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_390 = and(out_roready_1[268], out_romask_390) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_390 = and(out_wivalid_1[268], out_wimask_390) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_390 = and(out_woready_1[268], out_womask_390) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4072 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4073 = and(out_f_rivalid_390, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4074 = and(UInt<1>(0h1), out_f_roready_390) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4075 = eq(out_rimask_390, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4076 = eq(out_wimask_390, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4077 = eq(out_romask_390, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4078 = eq(out_womask_390, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_328 = or(_out_T_4071, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_328 = cat(_T_1070, _out_prepend_T_328) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4079 = or(out_prepend_328, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4080 = bits(_out_T_4079, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_391 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_391 = orr(_out_rimask_T_391) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_391 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_391 = andr(_out_wimask_T_391) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_391 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_391 = orr(_out_romask_T_391) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_391 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_391 = andr(_out_womask_T_391) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_391 = and(out_rivalid_1[269], out_rimask_391) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_391 = and(out_roready_1[269], out_romask_391) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_391 = and(out_wivalid_1[269], out_wimask_391) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_391 = and(out_woready_1[269], out_womask_391) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4081 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4082 = and(out_f_rivalid_391, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4083 = and(UInt<1>(0h1), out_f_roready_391) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4084 = eq(out_rimask_391, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4085 = eq(out_wimask_391, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4086 = eq(out_romask_391, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4087 = eq(out_womask_391, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_329 = or(_out_T_4080, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_329 = cat(_T_1071, _out_prepend_T_329) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4088 = or(out_prepend_329, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4089 = bits(_out_T_4088, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_392 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_392 = orr(_out_rimask_T_392) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_392 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_392 = andr(_out_wimask_T_392) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_392 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_392 = orr(_out_romask_T_392) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_392 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_392 = andr(_out_womask_T_392) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_392 = and(out_rivalid_1[270], out_rimask_392) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_392 = and(out_roready_1[270], out_romask_392) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_392 = and(out_wivalid_1[270], out_wimask_392) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_392 = and(out_woready_1[270], out_womask_392) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4090 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4091 = and(out_f_rivalid_392, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4092 = and(UInt<1>(0h1), out_f_roready_392) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4093 = eq(out_rimask_392, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4094 = eq(out_wimask_392, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4095 = eq(out_romask_392, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4096 = eq(out_womask_392, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_330 = or(_out_T_4089, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_330 = cat(_T_1072, _out_prepend_T_330) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4097 = or(out_prepend_330, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4098 = bits(_out_T_4097, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_393 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_393 = orr(_out_rimask_T_393) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_393 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_393 = andr(_out_wimask_T_393) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_393 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_393 = orr(_out_romask_T_393) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_393 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_393 = andr(_out_womask_T_393) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_393 = and(out_rivalid_1[271], out_rimask_393) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_393 = and(out_roready_1[271], out_romask_393) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_393 = and(out_wivalid_1[271], out_wimask_393) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_393 = and(out_woready_1[271], out_womask_393) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4099 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4100 = and(out_f_rivalid_393, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4101 = and(UInt<1>(0h1), out_f_roready_393) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4102 = eq(out_rimask_393, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4103 = eq(out_wimask_393, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4104 = eq(out_romask_393, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4105 = eq(out_womask_393, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_331 = or(_out_T_4098, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_331 = cat(_T_1073, _out_prepend_T_331) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4106 = or(out_prepend_331, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4107 = bits(_out_T_4106, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_394 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_394 = orr(_out_rimask_T_394) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_394 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_394 = andr(_out_wimask_T_394) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_394 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_394 = orr(_out_romask_T_394) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_394 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_394 = andr(_out_womask_T_394) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_394 = and(out_rivalid_1[272], out_rimask_394) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_394 = and(out_roready_1[272], out_romask_394) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_394 = and(out_wivalid_1[272], out_wimask_394) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_394 = and(out_woready_1[272], out_womask_394) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4108 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4109 = and(out_f_rivalid_394, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4110 = and(UInt<1>(0h1), out_f_roready_394) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4111 = eq(out_rimask_394, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4112 = eq(out_wimask_394, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4113 = eq(out_romask_394, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4114 = eq(out_womask_394, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4115 = or(_T_1282, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4116 = bits(_out_T_4115, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_395 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_395 = orr(_out_rimask_T_395) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_395 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_395 = andr(_out_wimask_T_395) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_395 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_395 = orr(_out_romask_T_395) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_395 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_395 = andr(_out_womask_T_395) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_395 = and(out_rivalid_1[273], out_rimask_395) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_395 = and(out_roready_1[273], out_romask_395) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_395 = and(out_wivalid_1[273], out_wimask_395) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_395 = and(out_woready_1[273], out_womask_395) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4117 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4118 = and(out_f_rivalid_395, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4119 = and(UInt<1>(0h1), out_f_roready_395) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4120 = eq(out_rimask_395, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4121 = eq(out_wimask_395, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4122 = eq(out_romask_395, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4123 = eq(out_womask_395, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_332 = or(_out_T_4116, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_332 = cat(_T_1283, _out_prepend_T_332) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4124 = or(out_prepend_332, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4125 = bits(_out_T_4124, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_396 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_396 = orr(_out_rimask_T_396) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_396 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_396 = andr(_out_wimask_T_396) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_396 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_396 = orr(_out_romask_T_396) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_396 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_396 = andr(_out_womask_T_396) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_396 = and(out_rivalid_1[274], out_rimask_396) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_396 = and(out_roready_1[274], out_romask_396) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_396 = and(out_wivalid_1[274], out_wimask_396) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_396 = and(out_woready_1[274], out_womask_396) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4126 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4127 = and(out_f_rivalid_396, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4128 = and(UInt<1>(0h1), out_f_roready_396) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4129 = eq(out_rimask_396, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4130 = eq(out_wimask_396, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4131 = eq(out_romask_396, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4132 = eq(out_womask_396, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_333 = or(_out_T_4125, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_333 = cat(_T_1284, _out_prepend_T_333) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4133 = or(out_prepend_333, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4134 = bits(_out_T_4133, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_397 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_397 = orr(_out_rimask_T_397) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_397 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_397 = andr(_out_wimask_T_397) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_397 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_397 = orr(_out_romask_T_397) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_397 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_397 = andr(_out_womask_T_397) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_397 = and(out_rivalid_1[275], out_rimask_397) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_397 = and(out_roready_1[275], out_romask_397) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_397 = and(out_wivalid_1[275], out_wimask_397) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_397 = and(out_woready_1[275], out_womask_397) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4135 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4136 = and(out_f_rivalid_397, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4137 = and(UInt<1>(0h1), out_f_roready_397) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4138 = eq(out_rimask_397, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4139 = eq(out_wimask_397, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4140 = eq(out_romask_397, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4141 = eq(out_womask_397, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_334 = or(_out_T_4134, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_334 = cat(_T_1285, _out_prepend_T_334) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4142 = or(out_prepend_334, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4143 = bits(_out_T_4142, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_398 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_398 = orr(_out_rimask_T_398) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_398 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_398 = andr(_out_wimask_T_398) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_398 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_398 = orr(_out_romask_T_398) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_398 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_398 = andr(_out_womask_T_398) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_398 = and(out_rivalid_1[276], out_rimask_398) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_398 = and(out_roready_1[276], out_romask_398) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_398 = and(out_wivalid_1[276], out_wimask_398) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_398 = and(out_woready_1[276], out_womask_398) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4144 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4145 = and(out_f_rivalid_398, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4146 = and(UInt<1>(0h1), out_f_roready_398) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4147 = eq(out_rimask_398, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4148 = eq(out_wimask_398, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4149 = eq(out_romask_398, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4150 = eq(out_womask_398, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_335 = or(_out_T_4143, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_335 = cat(_T_1286, _out_prepend_T_335) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4151 = or(out_prepend_335, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4152 = bits(_out_T_4151, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_399 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_399 = orr(_out_rimask_T_399) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_399 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_399 = andr(_out_wimask_T_399) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_399 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_399 = orr(_out_romask_T_399) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_399 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_399 = andr(_out_womask_T_399) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_399 = and(out_rivalid_1[277], out_rimask_399) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_399 = and(out_roready_1[277], out_romask_399) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_399 = and(out_wivalid_1[277], out_wimask_399) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_399 = and(out_woready_1[277], out_womask_399) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4153 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4154 = and(out_f_rivalid_399, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4155 = and(UInt<1>(0h1), out_f_roready_399) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4156 = eq(out_rimask_399, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4157 = eq(out_wimask_399, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4158 = eq(out_romask_399, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4159 = eq(out_womask_399, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_336 = or(_out_T_4152, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_336 = cat(_T_1287, _out_prepend_T_336) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4160 = or(out_prepend_336, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4161 = bits(_out_T_4160, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_400 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_400 = orr(_out_rimask_T_400) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_400 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_400 = andr(_out_wimask_T_400) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_400 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_400 = orr(_out_romask_T_400) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_400 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_400 = andr(_out_womask_T_400) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_400 = and(out_rivalid_1[278], out_rimask_400) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_400 = and(out_roready_1[278], out_romask_400) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_400 = and(out_wivalid_1[278], out_wimask_400) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_400 = and(out_woready_1[278], out_womask_400) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4162 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4163 = and(out_f_rivalid_400, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4164 = and(UInt<1>(0h1), out_f_roready_400) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4165 = eq(out_rimask_400, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4166 = eq(out_wimask_400, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4167 = eq(out_romask_400, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4168 = eq(out_womask_400, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_337 = or(_out_T_4161, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_337 = cat(_T_1288, _out_prepend_T_337) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4169 = or(out_prepend_337, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4170 = bits(_out_T_4169, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_401 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_401 = orr(_out_rimask_T_401) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_401 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_401 = andr(_out_wimask_T_401) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_401 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_401 = orr(_out_romask_T_401) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_401 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_401 = andr(_out_womask_T_401) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_401 = and(out_rivalid_1[279], out_rimask_401) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_401 = and(out_roready_1[279], out_romask_401) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_401 = and(out_wivalid_1[279], out_wimask_401) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_401 = and(out_woready_1[279], out_womask_401) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4171 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4172 = and(out_f_rivalid_401, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4173 = and(UInt<1>(0h1), out_f_roready_401) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4174 = eq(out_rimask_401, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4175 = eq(out_wimask_401, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4176 = eq(out_romask_401, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4177 = eq(out_womask_401, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_338 = or(_out_T_4170, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_338 = cat(_T_1289, _out_prepend_T_338) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4178 = or(out_prepend_338, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4179 = bits(_out_T_4178, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_402 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_402 = orr(_out_rimask_T_402) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_402 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_402 = andr(_out_wimask_T_402) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_402 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_402 = orr(_out_romask_T_402) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_402 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_402 = andr(_out_womask_T_402) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_402 = and(out_rivalid_1[280], out_rimask_402) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_402 = and(out_roready_1[280], out_romask_402) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_402 = and(out_wivalid_1[280], out_wimask_402) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_402 = and(out_woready_1[280], out_womask_402) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4180 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4181 = and(out_f_rivalid_402, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4182 = and(UInt<1>(0h1), out_f_roready_402) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4183 = eq(out_rimask_402, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4184 = eq(out_wimask_402, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4185 = eq(out_romask_402, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4186 = eq(out_womask_402, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4187 = or(_T_1402, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4188 = bits(_out_T_4187, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_403 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_403 = orr(_out_rimask_T_403) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_403 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_403 = andr(_out_wimask_T_403) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_403 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_403 = orr(_out_romask_T_403) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_403 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_403 = andr(_out_womask_T_403) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_403 = and(out_rivalid_1[281], out_rimask_403) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_403 = and(out_roready_1[281], out_romask_403) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_403 = and(out_wivalid_1[281], out_wimask_403) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_403 = and(out_woready_1[281], out_womask_403) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4189 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4190 = and(out_f_rivalid_403, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4191 = and(UInt<1>(0h1), out_f_roready_403) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4192 = eq(out_rimask_403, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4193 = eq(out_wimask_403, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4194 = eq(out_romask_403, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4195 = eq(out_womask_403, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_339 = or(_out_T_4188, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_339 = cat(_T_1403, _out_prepend_T_339) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4196 = or(out_prepend_339, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4197 = bits(_out_T_4196, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_404 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_404 = orr(_out_rimask_T_404) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_404 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_404 = andr(_out_wimask_T_404) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_404 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_404 = orr(_out_romask_T_404) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_404 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_404 = andr(_out_womask_T_404) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_404 = and(out_rivalid_1[282], out_rimask_404) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_404 = and(out_roready_1[282], out_romask_404) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_404 = and(out_wivalid_1[282], out_wimask_404) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_404 = and(out_woready_1[282], out_womask_404) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4198 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4199 = and(out_f_rivalid_404, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4200 = and(UInt<1>(0h1), out_f_roready_404) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4201 = eq(out_rimask_404, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4202 = eq(out_wimask_404, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4203 = eq(out_romask_404, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4204 = eq(out_womask_404, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_340 = or(_out_T_4197, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_340 = cat(_T_1404, _out_prepend_T_340) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4205 = or(out_prepend_340, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4206 = bits(_out_T_4205, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_405 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_405 = orr(_out_rimask_T_405) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_405 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_405 = andr(_out_wimask_T_405) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_405 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_405 = orr(_out_romask_T_405) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_405 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_405 = andr(_out_womask_T_405) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_405 = and(out_rivalid_1[283], out_rimask_405) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_405 = and(out_roready_1[283], out_romask_405) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_405 = and(out_wivalid_1[283], out_wimask_405) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_405 = and(out_woready_1[283], out_womask_405) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4207 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4208 = and(out_f_rivalid_405, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4209 = and(UInt<1>(0h1), out_f_roready_405) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4210 = eq(out_rimask_405, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4211 = eq(out_wimask_405, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4212 = eq(out_romask_405, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4213 = eq(out_womask_405, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_341 = or(_out_T_4206, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_341 = cat(_T_1405, _out_prepend_T_341) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4214 = or(out_prepend_341, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4215 = bits(_out_T_4214, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_406 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_406 = orr(_out_rimask_T_406) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_406 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_406 = andr(_out_wimask_T_406) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_406 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_406 = orr(_out_romask_T_406) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_406 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_406 = andr(_out_womask_T_406) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_406 = and(out_rivalid_1[284], out_rimask_406) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_406 = and(out_roready_1[284], out_romask_406) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_406 = and(out_wivalid_1[284], out_wimask_406) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_406 = and(out_woready_1[284], out_womask_406) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4216 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4217 = and(out_f_rivalid_406, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4218 = and(UInt<1>(0h1), out_f_roready_406) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4219 = eq(out_rimask_406, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4220 = eq(out_wimask_406, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4221 = eq(out_romask_406, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4222 = eq(out_womask_406, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_342 = or(_out_T_4215, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_342 = cat(_T_1406, _out_prepend_T_342) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4223 = or(out_prepend_342, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4224 = bits(_out_T_4223, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_407 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_407 = orr(_out_rimask_T_407) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_407 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_407 = andr(_out_wimask_T_407) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_407 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_407 = orr(_out_romask_T_407) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_407 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_407 = andr(_out_womask_T_407) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_407 = and(out_rivalid_1[285], out_rimask_407) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_407 = and(out_roready_1[285], out_romask_407) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_407 = and(out_wivalid_1[285], out_wimask_407) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_407 = and(out_woready_1[285], out_womask_407) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4225 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4226 = and(out_f_rivalid_407, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4227 = and(UInt<1>(0h1), out_f_roready_407) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4228 = eq(out_rimask_407, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4229 = eq(out_wimask_407, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4230 = eq(out_romask_407, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4231 = eq(out_womask_407, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_343 = or(_out_T_4224, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_343 = cat(_T_1407, _out_prepend_T_343) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4232 = or(out_prepend_343, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4233 = bits(_out_T_4232, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_408 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_408 = orr(_out_rimask_T_408) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_408 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_408 = andr(_out_wimask_T_408) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_408 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_408 = orr(_out_romask_T_408) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_408 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_408 = andr(_out_womask_T_408) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_408 = and(out_rivalid_1[286], out_rimask_408) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_408 = and(out_roready_1[286], out_romask_408) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_408 = and(out_wivalid_1[286], out_wimask_408) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_408 = and(out_woready_1[286], out_womask_408) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4234 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4235 = and(out_f_rivalid_408, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4236 = and(UInt<1>(0h1), out_f_roready_408) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4237 = eq(out_rimask_408, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4238 = eq(out_wimask_408, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4239 = eq(out_romask_408, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4240 = eq(out_womask_408, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_344 = or(_out_T_4233, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_344 = cat(_T_1408, _out_prepend_T_344) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4241 = or(out_prepend_344, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4242 = bits(_out_T_4241, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_409 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_409 = orr(_out_rimask_T_409) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_409 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_409 = andr(_out_wimask_T_409) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_409 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_409 = orr(_out_romask_T_409) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_409 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_409 = andr(_out_womask_T_409) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_409 = and(out_rivalid_1[287], out_rimask_409) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_409 = and(out_roready_1[287], out_romask_409) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_409 = and(out_wivalid_1[287], out_wimask_409) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_409 = and(out_woready_1[287], out_womask_409) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4243 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4244 = and(out_f_rivalid_409, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4245 = and(UInt<1>(0h1), out_f_roready_409) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4246 = eq(out_rimask_409, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4247 = eq(out_wimask_409, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4248 = eq(out_romask_409, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4249 = eq(out_womask_409, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_345 = or(_out_T_4242, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_345 = cat(_T_1409, _out_prepend_T_345) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4250 = or(out_prepend_345, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4251 = bits(_out_T_4250, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_410 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_410 = orr(_out_rimask_T_410) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_410 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_410 = andr(_out_wimask_T_410) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_410 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_410 = orr(_out_romask_T_410) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_410 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_410 = andr(_out_womask_T_410) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_410 = and(out_rivalid_1[288], out_rimask_410) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_410 = and(out_roready_1[288], out_romask_410) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_410 = and(out_wivalid_1[288], out_wimask_410) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_410 = and(out_woready_1[288], out_womask_410) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4252 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4253 = and(out_f_rivalid_410, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4254 = and(UInt<1>(0h1), out_f_roready_410) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4255 = eq(out_rimask_410, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4256 = eq(out_wimask_410, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4257 = eq(out_romask_410, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4258 = eq(out_womask_410, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4259 = or(_T_1026, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4260 = bits(_out_T_4259, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_411 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_411 = orr(_out_rimask_T_411) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_411 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_411 = andr(_out_wimask_T_411) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_411 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_411 = orr(_out_romask_T_411) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_411 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_411 = andr(_out_womask_T_411) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_411 = and(out_rivalid_1[289], out_rimask_411) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_411 = and(out_roready_1[289], out_romask_411) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_411 = and(out_wivalid_1[289], out_wimask_411) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_411 = and(out_woready_1[289], out_womask_411) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4261 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4262 = and(out_f_rivalid_411, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4263 = and(UInt<1>(0h1), out_f_roready_411) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4264 = eq(out_rimask_411, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4265 = eq(out_wimask_411, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4266 = eq(out_romask_411, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4267 = eq(out_womask_411, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_346 = or(_out_T_4260, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_346 = cat(_T_1027, _out_prepend_T_346) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4268 = or(out_prepend_346, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4269 = bits(_out_T_4268, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_412 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_412 = orr(_out_rimask_T_412) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_412 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_412 = andr(_out_wimask_T_412) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_412 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_412 = orr(_out_romask_T_412) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_412 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_412 = andr(_out_womask_T_412) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_412 = and(out_rivalid_1[290], out_rimask_412) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_412 = and(out_roready_1[290], out_romask_412) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_412 = and(out_wivalid_1[290], out_wimask_412) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_412 = and(out_woready_1[290], out_womask_412) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4270 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4271 = and(out_f_rivalid_412, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4272 = and(UInt<1>(0h1), out_f_roready_412) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4273 = eq(out_rimask_412, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4274 = eq(out_wimask_412, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4275 = eq(out_romask_412, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4276 = eq(out_womask_412, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_347 = or(_out_T_4269, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_347 = cat(_T_1028, _out_prepend_T_347) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4277 = or(out_prepend_347, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4278 = bits(_out_T_4277, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_413 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_413 = orr(_out_rimask_T_413) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_413 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_413 = andr(_out_wimask_T_413) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_413 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_413 = orr(_out_romask_T_413) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_413 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_413 = andr(_out_womask_T_413) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_413 = and(out_rivalid_1[291], out_rimask_413) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_413 = and(out_roready_1[291], out_romask_413) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_413 = and(out_wivalid_1[291], out_wimask_413) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_413 = and(out_woready_1[291], out_womask_413) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4279 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4280 = and(out_f_rivalid_413, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4281 = and(UInt<1>(0h1), out_f_roready_413) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4282 = eq(out_rimask_413, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4283 = eq(out_wimask_413, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4284 = eq(out_romask_413, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4285 = eq(out_womask_413, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_348 = or(_out_T_4278, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_348 = cat(_T_1029, _out_prepend_T_348) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4286 = or(out_prepend_348, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4287 = bits(_out_T_4286, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_414 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_414 = orr(_out_rimask_T_414) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_414 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_414 = andr(_out_wimask_T_414) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_414 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_414 = orr(_out_romask_T_414) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_414 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_414 = andr(_out_womask_T_414) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_414 = and(out_rivalid_1[292], out_rimask_414) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_414 = and(out_roready_1[292], out_romask_414) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_414 = and(out_wivalid_1[292], out_wimask_414) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_414 = and(out_woready_1[292], out_womask_414) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4288 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4289 = and(out_f_rivalid_414, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4290 = and(UInt<1>(0h1), out_f_roready_414) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4291 = eq(out_rimask_414, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4292 = eq(out_wimask_414, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4293 = eq(out_romask_414, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4294 = eq(out_womask_414, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_349 = or(_out_T_4287, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_349 = cat(_T_1030, _out_prepend_T_349) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4295 = or(out_prepend_349, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4296 = bits(_out_T_4295, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_415 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_415 = orr(_out_rimask_T_415) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_415 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_415 = andr(_out_wimask_T_415) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_415 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_415 = orr(_out_romask_T_415) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_415 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_415 = andr(_out_womask_T_415) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_415 = and(out_rivalid_1[293], out_rimask_415) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_415 = and(out_roready_1[293], out_romask_415) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_415 = and(out_wivalid_1[293], out_wimask_415) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_415 = and(out_woready_1[293], out_womask_415) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4297 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4298 = and(out_f_rivalid_415, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4299 = and(UInt<1>(0h1), out_f_roready_415) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4300 = eq(out_rimask_415, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4301 = eq(out_wimask_415, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4302 = eq(out_romask_415, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4303 = eq(out_womask_415, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_350 = or(_out_T_4296, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_350 = cat(_T_1031, _out_prepend_T_350) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4304 = or(out_prepend_350, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4305 = bits(_out_T_4304, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_416 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_416 = orr(_out_rimask_T_416) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_416 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_416 = andr(_out_wimask_T_416) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_416 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_416 = orr(_out_romask_T_416) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_416 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_416 = andr(_out_womask_T_416) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_416 = and(out_rivalid_1[294], out_rimask_416) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_416 = and(out_roready_1[294], out_romask_416) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_416 = and(out_wivalid_1[294], out_wimask_416) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_416 = and(out_woready_1[294], out_womask_416) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4306 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4307 = and(out_f_rivalid_416, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4308 = and(UInt<1>(0h1), out_f_roready_416) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4309 = eq(out_rimask_416, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4310 = eq(out_wimask_416, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4311 = eq(out_romask_416, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4312 = eq(out_womask_416, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_351 = or(_out_T_4305, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_351 = cat(_T_1032, _out_prepend_T_351) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4313 = or(out_prepend_351, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4314 = bits(_out_T_4313, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_417 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_417 = orr(_out_rimask_T_417) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_417 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_417 = andr(_out_wimask_T_417) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_417 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_417 = orr(_out_romask_T_417) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_417 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_417 = andr(_out_womask_T_417) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_417 = and(out_rivalid_1[295], out_rimask_417) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_417 = and(out_roready_1[295], out_romask_417) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_417 = and(out_wivalid_1[295], out_wimask_417) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_417 = and(out_woready_1[295], out_womask_417) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4315 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4316 = and(out_f_rivalid_417, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4317 = and(UInt<1>(0h1), out_f_roready_417) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4318 = eq(out_rimask_417, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4319 = eq(out_wimask_417, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4320 = eq(out_romask_417, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4321 = eq(out_womask_417, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_352 = or(_out_T_4314, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_352 = cat(_T_1033, _out_prepend_T_352) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4322 = or(out_prepend_352, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4323 = bits(_out_T_4322, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_418 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_418 = orr(_out_rimask_T_418) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_418 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_418 = andr(_out_wimask_T_418) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_418 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_418 = orr(_out_romask_T_418) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_418 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_418 = andr(_out_womask_T_418) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_418 = and(out_rivalid_1[296], out_rimask_418) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_418 = and(out_roready_1[296], out_romask_418) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_418 = and(out_wivalid_1[296], out_wimask_418) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_418 = and(out_woready_1[296], out_womask_418) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4324 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4325 = and(out_f_rivalid_418, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4326 = and(UInt<1>(0h1), out_f_roready_418) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4327 = eq(out_rimask_418, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4328 = eq(out_wimask_418, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4329 = eq(out_romask_418, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4330 = eq(out_womask_418, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4331 = or(_T_1178, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4332 = bits(_out_T_4331, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_419 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_419 = orr(_out_rimask_T_419) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_419 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_419 = andr(_out_wimask_T_419) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_419 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_419 = orr(_out_romask_T_419) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_419 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_419 = andr(_out_womask_T_419) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_419 = and(out_rivalid_1[297], out_rimask_419) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_419 = and(out_roready_1[297], out_romask_419) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_419 = and(out_wivalid_1[297], out_wimask_419) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_419 = and(out_woready_1[297], out_womask_419) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4333 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4334 = and(out_f_rivalid_419, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4335 = and(UInt<1>(0h1), out_f_roready_419) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4336 = eq(out_rimask_419, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4337 = eq(out_wimask_419, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4338 = eq(out_romask_419, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4339 = eq(out_womask_419, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_353 = or(_out_T_4332, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_353 = cat(_T_1179, _out_prepend_T_353) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4340 = or(out_prepend_353, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4341 = bits(_out_T_4340, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_420 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_420 = orr(_out_rimask_T_420) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_420 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_420 = andr(_out_wimask_T_420) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_420 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_420 = orr(_out_romask_T_420) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_420 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_420 = andr(_out_womask_T_420) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_420 = and(out_rivalid_1[298], out_rimask_420) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_420 = and(out_roready_1[298], out_romask_420) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_420 = and(out_wivalid_1[298], out_wimask_420) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_420 = and(out_woready_1[298], out_womask_420) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4342 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4343 = and(out_f_rivalid_420, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4344 = and(UInt<1>(0h1), out_f_roready_420) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4345 = eq(out_rimask_420, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4346 = eq(out_wimask_420, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4347 = eq(out_romask_420, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4348 = eq(out_womask_420, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_354 = or(_out_T_4341, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_354 = cat(_T_1180, _out_prepend_T_354) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4349 = or(out_prepend_354, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4350 = bits(_out_T_4349, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_421 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_421 = orr(_out_rimask_T_421) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_421 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_421 = andr(_out_wimask_T_421) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_421 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_421 = orr(_out_romask_T_421) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_421 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_421 = andr(_out_womask_T_421) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_421 = and(out_rivalid_1[299], out_rimask_421) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_421 = and(out_roready_1[299], out_romask_421) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_421 = and(out_wivalid_1[299], out_wimask_421) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_421 = and(out_woready_1[299], out_womask_421) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4351 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4352 = and(out_f_rivalid_421, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4353 = and(UInt<1>(0h1), out_f_roready_421) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4354 = eq(out_rimask_421, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4355 = eq(out_wimask_421, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4356 = eq(out_romask_421, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4357 = eq(out_womask_421, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_355 = or(_out_T_4350, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_355 = cat(_T_1181, _out_prepend_T_355) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4358 = or(out_prepend_355, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4359 = bits(_out_T_4358, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_422 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_422 = orr(_out_rimask_T_422) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_422 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_422 = andr(_out_wimask_T_422) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_422 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_422 = orr(_out_romask_T_422) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_422 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_422 = andr(_out_womask_T_422) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_422 = and(out_rivalid_1[300], out_rimask_422) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_422 = and(out_roready_1[300], out_romask_422) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_422 = and(out_wivalid_1[300], out_wimask_422) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_422 = and(out_woready_1[300], out_womask_422) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4360 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4361 = and(out_f_rivalid_422, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4362 = and(UInt<1>(0h1), out_f_roready_422) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4363 = eq(out_rimask_422, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4364 = eq(out_wimask_422, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4365 = eq(out_romask_422, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4366 = eq(out_womask_422, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_356 = or(_out_T_4359, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_356 = cat(_T_1182, _out_prepend_T_356) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4367 = or(out_prepend_356, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4368 = bits(_out_T_4367, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_423 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_423 = orr(_out_rimask_T_423) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_423 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_423 = andr(_out_wimask_T_423) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_423 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_423 = orr(_out_romask_T_423) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_423 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_423 = andr(_out_womask_T_423) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_423 = and(out_rivalid_1[301], out_rimask_423) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_423 = and(out_roready_1[301], out_romask_423) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_423 = and(out_wivalid_1[301], out_wimask_423) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_423 = and(out_woready_1[301], out_womask_423) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4369 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4370 = and(out_f_rivalid_423, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4371 = and(UInt<1>(0h1), out_f_roready_423) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4372 = eq(out_rimask_423, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4373 = eq(out_wimask_423, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4374 = eq(out_romask_423, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4375 = eq(out_womask_423, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_357 = or(_out_T_4368, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_357 = cat(_T_1183, _out_prepend_T_357) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4376 = or(out_prepend_357, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4377 = bits(_out_T_4376, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_424 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_424 = orr(_out_rimask_T_424) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_424 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_424 = andr(_out_wimask_T_424) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_424 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_424 = orr(_out_romask_T_424) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_424 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_424 = andr(_out_womask_T_424) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_424 = and(out_rivalid_1[302], out_rimask_424) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_424 = and(out_roready_1[302], out_romask_424) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_424 = and(out_wivalid_1[302], out_wimask_424) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_424 = and(out_woready_1[302], out_womask_424) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4378 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4379 = and(out_f_rivalid_424, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4380 = and(UInt<1>(0h1), out_f_roready_424) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4381 = eq(out_rimask_424, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4382 = eq(out_wimask_424, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4383 = eq(out_romask_424, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4384 = eq(out_womask_424, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_358 = or(_out_T_4377, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_358 = cat(_T_1184, _out_prepend_T_358) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4385 = or(out_prepend_358, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4386 = bits(_out_T_4385, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_425 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_425 = orr(_out_rimask_T_425) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_425 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_425 = andr(_out_wimask_T_425) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_425 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_425 = orr(_out_romask_T_425) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_425 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_425 = andr(_out_womask_T_425) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_425 = and(out_rivalid_1[303], out_rimask_425) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_425 = and(out_roready_1[303], out_romask_425) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_425 = and(out_wivalid_1[303], out_wimask_425) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_425 = and(out_woready_1[303], out_womask_425) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4387 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4388 = and(out_f_rivalid_425, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4389 = and(UInt<1>(0h1), out_f_roready_425) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4390 = eq(out_rimask_425, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4391 = eq(out_wimask_425, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4392 = eq(out_romask_425, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4393 = eq(out_womask_425, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_359 = or(_out_T_4386, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_359 = cat(_T_1185, _out_prepend_T_359) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4394 = or(out_prepend_359, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4395 = bits(_out_T_4394, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_426 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_426 = orr(_out_rimask_T_426) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_426 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_426 = andr(_out_wimask_T_426) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_426 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_426 = orr(_out_romask_T_426) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_426 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_426 = andr(_out_womask_T_426) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_426 = and(out_rivalid_1[304], out_rimask_426) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_426 = and(out_roready_1[304], out_romask_426) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_426 = and(out_wivalid_1[304], out_wimask_426) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_426 = and(out_woready_1[304], out_womask_426) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4396 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4397 = and(out_f_rivalid_426, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4398 = and(UInt<1>(0h1), out_f_roready_426) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4399 = eq(out_rimask_426, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4400 = eq(out_wimask_426, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4401 = eq(out_romask_426, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4402 = eq(out_womask_426, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4403 = or(UInt<8>(0h13), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4404 = bits(_out_T_4403, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_427 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_427 = orr(_out_rimask_T_427) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_427 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_427 = andr(_out_wimask_T_427) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_427 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_427 = orr(_out_romask_T_427) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_427 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_427 = andr(_out_womask_T_427) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_427 = and(out_rivalid_1[305], out_rimask_427) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_427 = and(out_roready_1[305], out_romask_427) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_427 = and(out_wivalid_1[305], out_wimask_427) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_427 = and(out_woready_1[305], out_womask_427) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4405 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4406 = and(out_f_rivalid_427, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4407 = and(UInt<1>(0h1), out_f_roready_427) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4408 = eq(out_rimask_427, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4409 = eq(out_wimask_427, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4410 = eq(out_romask_427, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4411 = eq(out_womask_427, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_360 = or(_out_T_4404, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_360 = cat(UInt<8>(0h74), _out_prepend_T_360) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4412 = or(out_prepend_360, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4413 = bits(_out_T_4412, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_428 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_428 = orr(_out_rimask_T_428) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_428 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_428 = andr(_out_wimask_T_428) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_428 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_428 = orr(_out_romask_T_428) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_428 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_428 = andr(_out_womask_T_428) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_428 = and(out_rivalid_1[306], out_rimask_428) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_428 = and(out_roready_1[306], out_romask_428) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_428 = and(out_wivalid_1[306], out_wimask_428) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_428 = and(out_woready_1[306], out_womask_428) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4414 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4415 = and(out_f_rivalid_428, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4416 = and(UInt<1>(0h1), out_f_roready_428) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4417 = eq(out_rimask_428, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4418 = eq(out_wimask_428, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4419 = eq(out_romask_428, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4420 = eq(out_womask_428, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_361 = or(_out_T_4413, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_361 = cat(UInt<8>(0h34), _out_prepend_T_361) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4421 = or(out_prepend_361, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4422 = bits(_out_T_4421, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_429 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_429 = orr(_out_rimask_T_429) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_429 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_429 = andr(_out_wimask_T_429) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_429 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_429 = orr(_out_romask_T_429) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_429 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_429 = andr(_out_womask_T_429) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_429 = and(out_rivalid_1[307], out_rimask_429) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_429 = and(out_roready_1[307], out_romask_429) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_429 = and(out_wivalid_1[307], out_wimask_429) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_429 = and(out_woready_1[307], out_womask_429) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4423 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4424 = and(out_f_rivalid_429, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4425 = and(UInt<1>(0h1), out_f_roready_429) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4426 = eq(out_rimask_429, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4427 = eq(out_wimask_429, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4428 = eq(out_romask_429, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4429 = eq(out_womask_429, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_362 = or(_out_T_4422, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_362 = cat(UInt<8>(0h0), _out_prepend_T_362) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4430 = or(out_prepend_362, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4431 = bits(_out_T_4430, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_430 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_430 = orr(_out_rimask_T_430) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_430 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_430 = andr(_out_wimask_T_430) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_430 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_430 = orr(_out_romask_T_430) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_430 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_430 = andr(_out_womask_T_430) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_430 = and(out_rivalid_1[308], out_rimask_430) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_430 = and(out_roready_1[308], out_romask_430) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_430 = and(out_wivalid_1[308], out_wimask_430) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_430 = and(out_woready_1[308], out_womask_430) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4432 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4433 = and(out_f_rivalid_430, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4434 = and(UInt<1>(0h1), out_f_roready_430) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4435 = eq(out_rimask_430, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4436 = eq(out_wimask_430, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4437 = eq(out_romask_430, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4438 = eq(out_womask_430, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_363 = or(_out_T_4431, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_363 = cat(UInt<8>(0he3), _out_prepend_T_363) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4439 = or(out_prepend_363, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4440 = bits(_out_T_4439, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_431 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_431 = orr(_out_rimask_T_431) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_431 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_431 = andr(_out_wimask_T_431) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_431 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_431 = orr(_out_romask_T_431) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_431 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_431 = andr(_out_womask_T_431) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_431 = and(out_rivalid_1[309], out_rimask_431) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_431 = and(out_roready_1[309], out_romask_431) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_431 = and(out_wivalid_1[309], out_wimask_431) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_431 = and(out_woready_1[309], out_womask_431) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4441 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4442 = and(out_f_rivalid_431, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4443 = and(UInt<1>(0h1), out_f_roready_431) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4444 = eq(out_rimask_431, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4445 = eq(out_wimask_431, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4446 = eq(out_romask_431, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4447 = eq(out_womask_431, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_364 = or(_out_T_4440, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_364 = cat(UInt<8>(0h8), _out_prepend_T_364) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4448 = or(out_prepend_364, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4449 = bits(_out_T_4448, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_432 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_432 = orr(_out_rimask_T_432) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_432 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_432 = andr(_out_wimask_T_432) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_432 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_432 = orr(_out_romask_T_432) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_432 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_432 = andr(_out_womask_T_432) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_432 = and(out_rivalid_1[310], out_rimask_432) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_432 = and(out_roready_1[310], out_romask_432) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_432 = and(out_wivalid_1[310], out_wimask_432) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_432 = and(out_woready_1[310], out_womask_432) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4450 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4451 = and(out_f_rivalid_432, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4452 = and(UInt<1>(0h1), out_f_roready_432) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4453 = eq(out_rimask_432, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4454 = eq(out_wimask_432, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4455 = eq(out_romask_432, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4456 = eq(out_womask_432, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_365 = or(_out_T_4449, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_365 = cat(UInt<8>(0h4), _out_prepend_T_365) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4457 = or(out_prepend_365, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4458 = bits(_out_T_4457, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_433 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_433 = orr(_out_rimask_T_433) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_433 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_433 = andr(_out_wimask_T_433) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_433 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_433 = orr(_out_romask_T_433) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_433 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_433 = andr(_out_womask_T_433) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_433 = and(out_rivalid_1[311], out_rimask_433) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_433 = and(out_roready_1[311], out_romask_433) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_433 = and(out_wivalid_1[311], out_wimask_433) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_433 = and(out_woready_1[311], out_womask_433) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4459 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4460 = and(out_f_rivalid_433, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4461 = and(UInt<1>(0h1), out_f_roready_433) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4462 = eq(out_rimask_433, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4463 = eq(out_wimask_433, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4464 = eq(out_romask_433, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4465 = eq(out_womask_433, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_366 = or(_out_T_4458, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_366 = cat(UInt<8>(0hfe), _out_prepend_T_366) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4466 = or(out_prepend_366, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4467 = bits(_out_T_4466, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_434 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_434 = orr(_out_rimask_T_434) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_434 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_434 = andr(_out_wimask_T_434) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_434 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_434 = orr(_out_romask_T_434) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_434 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_434 = andr(_out_womask_T_434) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_434 = and(out_rivalid_1[312], out_rimask_434) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_434 = and(out_roready_1[312], out_romask_434) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_434 = and(out_wivalid_1[312], out_wimask_434) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_434 = and(out_woready_1[312], out_womask_434) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4468 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4469 = and(out_f_rivalid_434, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4470 = and(UInt<1>(0h1), out_f_roready_434) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4471 = eq(out_rimask_434, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4472 = eq(out_wimask_434, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4473 = eq(out_romask_434, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4474 = eq(out_womask_434, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4475 = or(_T_698, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4476 = bits(_out_T_4475, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_435 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_435 = orr(_out_rimask_T_435) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_435 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_435 = andr(_out_wimask_T_435) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_435 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_435 = orr(_out_romask_T_435) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_435 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_435 = andr(_out_womask_T_435) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_435 = and(out_rivalid_1[313], out_rimask_435) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_435 = and(out_roready_1[313], out_romask_435) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_435 = and(out_wivalid_1[313], out_wimask_435) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_435 = and(out_woready_1[313], out_womask_435) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4477 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4478 = and(out_f_rivalid_435, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4479 = and(UInt<1>(0h1), out_f_roready_435) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4480 = eq(out_rimask_435, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4481 = eq(out_wimask_435, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4482 = eq(out_romask_435, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4483 = eq(out_womask_435, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_367 = or(_out_T_4476, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_367 = cat(_T_699, _out_prepend_T_367) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4484 = or(out_prepend_367, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4485 = bits(_out_T_4484, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_436 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_436 = orr(_out_rimask_T_436) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_436 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_436 = andr(_out_wimask_T_436) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_436 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_436 = orr(_out_romask_T_436) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_436 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_436 = andr(_out_womask_T_436) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_436 = and(out_rivalid_1[314], out_rimask_436) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_436 = and(out_roready_1[314], out_romask_436) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_436 = and(out_wivalid_1[314], out_wimask_436) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_436 = and(out_woready_1[314], out_womask_436) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4486 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4487 = and(out_f_rivalid_436, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4488 = and(UInt<1>(0h1), out_f_roready_436) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4489 = eq(out_rimask_436, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4490 = eq(out_wimask_436, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4491 = eq(out_romask_436, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4492 = eq(out_womask_436, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_368 = or(_out_T_4485, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_368 = cat(_T_700, _out_prepend_T_368) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4493 = or(out_prepend_368, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4494 = bits(_out_T_4493, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_437 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_437 = orr(_out_rimask_T_437) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_437 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_437 = andr(_out_wimask_T_437) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_437 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_437 = orr(_out_romask_T_437) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_437 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_437 = andr(_out_womask_T_437) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_437 = and(out_rivalid_1[315], out_rimask_437) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_437 = and(out_roready_1[315], out_romask_437) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_437 = and(out_wivalid_1[315], out_wimask_437) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_437 = and(out_woready_1[315], out_womask_437) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4495 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4496 = and(out_f_rivalid_437, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4497 = and(UInt<1>(0h1), out_f_roready_437) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4498 = eq(out_rimask_437, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4499 = eq(out_wimask_437, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4500 = eq(out_romask_437, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4501 = eq(out_womask_437, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_369 = or(_out_T_4494, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_369 = cat(_T_701, _out_prepend_T_369) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4502 = or(out_prepend_369, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4503 = bits(_out_T_4502, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_438 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_438 = orr(_out_rimask_T_438) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_438 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_438 = andr(_out_wimask_T_438) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_438 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_438 = orr(_out_romask_T_438) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_438 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_438 = andr(_out_womask_T_438) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_438 = and(out_rivalid_1[316], out_rimask_438) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_438 = and(out_roready_1[316], out_romask_438) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_438 = and(out_wivalid_1[316], out_wimask_438) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_438 = and(out_woready_1[316], out_womask_438) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4504 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4505 = and(out_f_rivalid_438, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4506 = and(UInt<1>(0h1), out_f_roready_438) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4507 = eq(out_rimask_438, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4508 = eq(out_wimask_438, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4509 = eq(out_romask_438, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4510 = eq(out_womask_438, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_370 = or(_out_T_4503, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_370 = cat(_T_702, _out_prepend_T_370) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4511 = or(out_prepend_370, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4512 = bits(_out_T_4511, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_439 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_439 = orr(_out_rimask_T_439) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_439 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_439 = andr(_out_wimask_T_439) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_439 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_439 = orr(_out_romask_T_439) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_439 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_439 = andr(_out_womask_T_439) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_439 = and(out_rivalid_1[317], out_rimask_439) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_439 = and(out_roready_1[317], out_romask_439) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_439 = and(out_wivalid_1[317], out_wimask_439) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_439 = and(out_woready_1[317], out_womask_439) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4513 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4514 = and(out_f_rivalid_439, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4515 = and(UInt<1>(0h1), out_f_roready_439) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4516 = eq(out_rimask_439, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4517 = eq(out_wimask_439, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4518 = eq(out_romask_439, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4519 = eq(out_womask_439, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_371 = or(_out_T_4512, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_371 = cat(_T_703, _out_prepend_T_371) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4520 = or(out_prepend_371, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4521 = bits(_out_T_4520, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_440 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_440 = orr(_out_rimask_T_440) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_440 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_440 = andr(_out_wimask_T_440) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_440 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_440 = orr(_out_romask_T_440) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_440 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_440 = andr(_out_womask_T_440) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_440 = and(out_rivalid_1[318], out_rimask_440) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_440 = and(out_roready_1[318], out_romask_440) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_440 = and(out_wivalid_1[318], out_wimask_440) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_440 = and(out_woready_1[318], out_womask_440) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4522 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4523 = and(out_f_rivalid_440, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4524 = and(UInt<1>(0h1), out_f_roready_440) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4525 = eq(out_rimask_440, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4526 = eq(out_wimask_440, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4527 = eq(out_romask_440, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4528 = eq(out_womask_440, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_372 = or(_out_T_4521, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_372 = cat(_T_704, _out_prepend_T_372) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4529 = or(out_prepend_372, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4530 = bits(_out_T_4529, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_441 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_441 = orr(_out_rimask_T_441) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_441 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_441 = andr(_out_wimask_T_441) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_441 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_441 = orr(_out_romask_T_441) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_441 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_441 = andr(_out_womask_T_441) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_441 = and(out_rivalid_1[319], out_rimask_441) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_441 = and(out_roready_1[319], out_romask_441) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_441 = and(out_wivalid_1[319], out_wimask_441) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_441 = and(out_woready_1[319], out_womask_441) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4531 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4532 = and(out_f_rivalid_441, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4533 = and(UInt<1>(0h1), out_f_roready_441) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4534 = eq(out_rimask_441, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4535 = eq(out_wimask_441, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4536 = eq(out_romask_441, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4537 = eq(out_womask_441, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_373 = or(_out_T_4530, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_373 = cat(_T_705, _out_prepend_T_373) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4538 = or(out_prepend_373, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4539 = bits(_out_T_4538, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_442 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_442 = orr(_out_rimask_T_442) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_442 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_442 = andr(_out_wimask_T_442) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_442 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_442 = orr(_out_romask_T_442) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_442 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_442 = andr(_out_womask_T_442) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_442 = and(out_rivalid_1[320], out_rimask_442) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_442 = and(out_roready_1[320], out_romask_442) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_442 = and(out_wivalid_1[320], out_wimask_442) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_442 = and(out_woready_1[320], out_womask_442) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4540 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4541 = and(out_f_rivalid_442, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4542 = and(UInt<1>(0h1), out_f_roready_442) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4543 = eq(out_rimask_442, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4544 = eq(out_wimask_442, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4545 = eq(out_romask_442, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4546 = eq(out_womask_442, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4547 = or(_T_954, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4548 = bits(_out_T_4547, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_443 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_443 = orr(_out_rimask_T_443) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_443 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_443 = andr(_out_wimask_T_443) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_443 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_443 = orr(_out_romask_T_443) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_443 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_443 = andr(_out_womask_T_443) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_443 = and(out_rivalid_1[321], out_rimask_443) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_443 = and(out_roready_1[321], out_romask_443) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_443 = and(out_wivalid_1[321], out_wimask_443) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_443 = and(out_woready_1[321], out_womask_443) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4549 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4550 = and(out_f_rivalid_443, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4551 = and(UInt<1>(0h1), out_f_roready_443) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4552 = eq(out_rimask_443, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4553 = eq(out_wimask_443, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4554 = eq(out_romask_443, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4555 = eq(out_womask_443, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_374 = or(_out_T_4548, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_374 = cat(_T_955, _out_prepend_T_374) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4556 = or(out_prepend_374, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4557 = bits(_out_T_4556, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_444 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_444 = orr(_out_rimask_T_444) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_444 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_444 = andr(_out_wimask_T_444) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_444 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_444 = orr(_out_romask_T_444) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_444 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_444 = andr(_out_womask_T_444) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_444 = and(out_rivalid_1[322], out_rimask_444) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_444 = and(out_roready_1[322], out_romask_444) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_444 = and(out_wivalid_1[322], out_wimask_444) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_444 = and(out_woready_1[322], out_womask_444) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4558 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4559 = and(out_f_rivalid_444, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4560 = and(UInt<1>(0h1), out_f_roready_444) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4561 = eq(out_rimask_444, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4562 = eq(out_wimask_444, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4563 = eq(out_romask_444, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4564 = eq(out_womask_444, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_375 = or(_out_T_4557, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_375 = cat(_T_956, _out_prepend_T_375) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4565 = or(out_prepend_375, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4566 = bits(_out_T_4565, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_445 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_445 = orr(_out_rimask_T_445) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_445 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_445 = andr(_out_wimask_T_445) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_445 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_445 = orr(_out_romask_T_445) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_445 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_445 = andr(_out_womask_T_445) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_445 = and(out_rivalid_1[323], out_rimask_445) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_445 = and(out_roready_1[323], out_romask_445) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_445 = and(out_wivalid_1[323], out_wimask_445) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_445 = and(out_woready_1[323], out_womask_445) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4567 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4568 = and(out_f_rivalid_445, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4569 = and(UInt<1>(0h1), out_f_roready_445) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4570 = eq(out_rimask_445, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4571 = eq(out_wimask_445, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4572 = eq(out_romask_445, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4573 = eq(out_womask_445, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_376 = or(_out_T_4566, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_376 = cat(_T_957, _out_prepend_T_376) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4574 = or(out_prepend_376, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4575 = bits(_out_T_4574, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_446 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_446 = orr(_out_rimask_T_446) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_446 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_446 = andr(_out_wimask_T_446) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_446 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_446 = orr(_out_romask_T_446) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_446 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_446 = andr(_out_womask_T_446) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_446 = and(out_rivalid_1[324], out_rimask_446) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_446 = and(out_roready_1[324], out_romask_446) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_446 = and(out_wivalid_1[324], out_wimask_446) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_446 = and(out_woready_1[324], out_womask_446) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4576 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4577 = and(out_f_rivalid_446, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4578 = and(UInt<1>(0h1), out_f_roready_446) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4579 = eq(out_rimask_446, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4580 = eq(out_wimask_446, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4581 = eq(out_romask_446, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4582 = eq(out_womask_446, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_377 = or(_out_T_4575, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_377 = cat(_T_958, _out_prepend_T_377) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4583 = or(out_prepend_377, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4584 = bits(_out_T_4583, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_447 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_447 = orr(_out_rimask_T_447) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_447 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_447 = andr(_out_wimask_T_447) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_447 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_447 = orr(_out_romask_T_447) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_447 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_447 = andr(_out_womask_T_447) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_447 = and(out_rivalid_1[325], out_rimask_447) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_447 = and(out_roready_1[325], out_romask_447) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_447 = and(out_wivalid_1[325], out_wimask_447) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_447 = and(out_woready_1[325], out_womask_447) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4585 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4586 = and(out_f_rivalid_447, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4587 = and(UInt<1>(0h1), out_f_roready_447) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4588 = eq(out_rimask_447, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4589 = eq(out_wimask_447, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4590 = eq(out_romask_447, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4591 = eq(out_womask_447, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_378 = or(_out_T_4584, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_378 = cat(_T_959, _out_prepend_T_378) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4592 = or(out_prepend_378, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4593 = bits(_out_T_4592, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_448 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_448 = orr(_out_rimask_T_448) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_448 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_448 = andr(_out_wimask_T_448) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_448 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_448 = orr(_out_romask_T_448) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_448 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_448 = andr(_out_womask_T_448) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_448 = and(out_rivalid_1[326], out_rimask_448) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_448 = and(out_roready_1[326], out_romask_448) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_448 = and(out_wivalid_1[326], out_wimask_448) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_448 = and(out_woready_1[326], out_womask_448) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4594 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4595 = and(out_f_rivalid_448, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4596 = and(UInt<1>(0h1), out_f_roready_448) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4597 = eq(out_rimask_448, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4598 = eq(out_wimask_448, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4599 = eq(out_romask_448, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4600 = eq(out_womask_448, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_379 = or(_out_T_4593, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_379 = cat(_T_960, _out_prepend_T_379) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4601 = or(out_prepend_379, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4602 = bits(_out_T_4601, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_449 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_449 = orr(_out_rimask_T_449) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_449 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_449 = andr(_out_wimask_T_449) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_449 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_449 = orr(_out_romask_T_449) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_449 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_449 = andr(_out_womask_T_449) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_449 = and(out_rivalid_1[327], out_rimask_449) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_449 = and(out_roready_1[327], out_romask_449) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_449 = and(out_wivalid_1[327], out_wimask_449) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_449 = and(out_woready_1[327], out_womask_449) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4603 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4604 = and(out_f_rivalid_449, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4605 = and(UInt<1>(0h1), out_f_roready_449) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4606 = eq(out_rimask_449, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4607 = eq(out_wimask_449, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4608 = eq(out_romask_449, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4609 = eq(out_womask_449, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_380 = or(_out_T_4602, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_380 = cat(_T_961, _out_prepend_T_380) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4610 = or(out_prepend_380, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4611 = bits(_out_T_4610, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_450 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_450 = orr(_out_rimask_T_450) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_450 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_450 = andr(_out_wimask_T_450) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_450 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_450 = orr(_out_romask_T_450) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_450 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_450 = andr(_out_womask_T_450) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_450 = and(out_rivalid_1[328], out_rimask_450) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_450 = and(out_roready_1[328], out_romask_450) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_450 = and(out_wivalid_1[328], out_wimask_450) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_450 = and(out_woready_1[328], out_womask_450) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4612 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4613 = and(out_f_rivalid_450, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4614 = and(UInt<1>(0h1), out_f_roready_450) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4615 = eq(out_rimask_450, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4616 = eq(out_wimask_450, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4617 = eq(out_romask_450, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4618 = eq(out_womask_450, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4619 = or(_T_514, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4620 = bits(_out_T_4619, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_451 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_451 = orr(_out_rimask_T_451) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_451 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_451 = andr(_out_wimask_T_451) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_451 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_451 = orr(_out_romask_T_451) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_451 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_451 = andr(_out_womask_T_451) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_451 = and(out_rivalid_1[329], out_rimask_451) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_451 = and(out_roready_1[329], out_romask_451) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_451 = and(out_wivalid_1[329], out_wimask_451) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_451 = and(out_woready_1[329], out_womask_451) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4621 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4622 = and(out_f_rivalid_451, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4623 = and(UInt<1>(0h1), out_f_roready_451) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4624 = eq(out_rimask_451, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4625 = eq(out_wimask_451, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4626 = eq(out_romask_451, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4627 = eq(out_womask_451, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_381 = or(_out_T_4620, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_381 = cat(_T_515, _out_prepend_T_381) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4628 = or(out_prepend_381, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4629 = bits(_out_T_4628, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_452 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_452 = orr(_out_rimask_T_452) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_452 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_452 = andr(_out_wimask_T_452) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_452 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_452 = orr(_out_romask_T_452) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_452 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_452 = andr(_out_womask_T_452) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_452 = and(out_rivalid_1[330], out_rimask_452) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_452 = and(out_roready_1[330], out_romask_452) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_452 = and(out_wivalid_1[330], out_wimask_452) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_452 = and(out_woready_1[330], out_womask_452) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4630 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4631 = and(out_f_rivalid_452, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4632 = and(UInt<1>(0h1), out_f_roready_452) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4633 = eq(out_rimask_452, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4634 = eq(out_wimask_452, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4635 = eq(out_romask_452, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4636 = eq(out_womask_452, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_382 = or(_out_T_4629, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_382 = cat(_T_516, _out_prepend_T_382) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4637 = or(out_prepend_382, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4638 = bits(_out_T_4637, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_453 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_453 = orr(_out_rimask_T_453) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_453 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_453 = andr(_out_wimask_T_453) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_453 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_453 = orr(_out_romask_T_453) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_453 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_453 = andr(_out_womask_T_453) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_453 = and(out_rivalid_1[331], out_rimask_453) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_453 = and(out_roready_1[331], out_romask_453) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_453 = and(out_wivalid_1[331], out_wimask_453) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_453 = and(out_woready_1[331], out_womask_453) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4639 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4640 = and(out_f_rivalid_453, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4641 = and(UInt<1>(0h1), out_f_roready_453) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4642 = eq(out_rimask_453, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4643 = eq(out_wimask_453, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4644 = eq(out_romask_453, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4645 = eq(out_womask_453, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_383 = or(_out_T_4638, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_383 = cat(_T_517, _out_prepend_T_383) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4646 = or(out_prepend_383, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4647 = bits(_out_T_4646, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_454 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_454 = orr(_out_rimask_T_454) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_454 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_454 = andr(_out_wimask_T_454) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_454 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_454 = orr(_out_romask_T_454) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_454 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_454 = andr(_out_womask_T_454) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_454 = and(out_rivalid_1[332], out_rimask_454) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_454 = and(out_roready_1[332], out_romask_454) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_454 = and(out_wivalid_1[332], out_wimask_454) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_454 = and(out_woready_1[332], out_womask_454) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4648 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4649 = and(out_f_rivalid_454, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4650 = and(UInt<1>(0h1), out_f_roready_454) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4651 = eq(out_rimask_454, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4652 = eq(out_wimask_454, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4653 = eq(out_romask_454, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4654 = eq(out_womask_454, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_384 = or(_out_T_4647, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_384 = cat(_T_518, _out_prepend_T_384) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4655 = or(out_prepend_384, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4656 = bits(_out_T_4655, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_455 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_455 = orr(_out_rimask_T_455) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_455 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_455 = andr(_out_wimask_T_455) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_455 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_455 = orr(_out_romask_T_455) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_455 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_455 = andr(_out_womask_T_455) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_455 = and(out_rivalid_1[333], out_rimask_455) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_455 = and(out_roready_1[333], out_romask_455) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_455 = and(out_wivalid_1[333], out_wimask_455) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_455 = and(out_woready_1[333], out_womask_455) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4657 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4658 = and(out_f_rivalid_455, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4659 = and(UInt<1>(0h1), out_f_roready_455) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4660 = eq(out_rimask_455, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4661 = eq(out_wimask_455, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4662 = eq(out_romask_455, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4663 = eq(out_womask_455, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_385 = or(_out_T_4656, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_385 = cat(_T_519, _out_prepend_T_385) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4664 = or(out_prepend_385, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4665 = bits(_out_T_4664, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_456 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_456 = orr(_out_rimask_T_456) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_456 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_456 = andr(_out_wimask_T_456) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_456 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_456 = orr(_out_romask_T_456) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_456 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_456 = andr(_out_womask_T_456) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_456 = and(out_rivalid_1[334], out_rimask_456) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_456 = and(out_roready_1[334], out_romask_456) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_456 = and(out_wivalid_1[334], out_wimask_456) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_456 = and(out_woready_1[334], out_womask_456) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4666 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4667 = and(out_f_rivalid_456, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4668 = and(UInt<1>(0h1), out_f_roready_456) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4669 = eq(out_rimask_456, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4670 = eq(out_wimask_456, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4671 = eq(out_romask_456, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4672 = eq(out_womask_456, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_386 = or(_out_T_4665, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_386 = cat(_T_520, _out_prepend_T_386) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4673 = or(out_prepend_386, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4674 = bits(_out_T_4673, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_457 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_457 = orr(_out_rimask_T_457) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_457 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_457 = andr(_out_wimask_T_457) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_457 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_457 = orr(_out_romask_T_457) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_457 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_457 = andr(_out_womask_T_457) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_457 = and(out_rivalid_1[335], out_rimask_457) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_457 = and(out_roready_1[335], out_romask_457) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_457 = and(out_wivalid_1[335], out_wimask_457) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_457 = and(out_woready_1[335], out_womask_457) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4675 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4676 = and(out_f_rivalid_457, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4677 = and(UInt<1>(0h1), out_f_roready_457) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4678 = eq(out_rimask_457, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4679 = eq(out_wimask_457, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4680 = eq(out_romask_457, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4681 = eq(out_womask_457, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_387 = or(_out_T_4674, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_387 = cat(_T_521, _out_prepend_T_387) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4682 = or(out_prepend_387, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4683 = bits(_out_T_4682, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_458 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_458 = orr(_out_rimask_T_458) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_458 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_458 = andr(_out_wimask_T_458) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_458 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_458 = orr(_out_romask_T_458) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_458 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_458 = andr(_out_womask_T_458) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_458 = and(out_rivalid_1[336], out_rimask_458) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_458 = and(out_roready_1[336], out_romask_458) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_458 = and(out_wivalid_1[336], out_wimask_458) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_458 = and(out_woready_1[336], out_womask_458) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4684 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4685 = and(out_f_rivalid_458, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4686 = and(UInt<1>(0h1), out_f_roready_458) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4687 = eq(out_rimask_458, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4688 = eq(out_wimask_458, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4689 = eq(out_romask_458, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4690 = eq(out_womask_458, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4691 = or(_T_738, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4692 = bits(_out_T_4691, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_459 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_459 = orr(_out_rimask_T_459) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_459 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_459 = andr(_out_wimask_T_459) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_459 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_459 = orr(_out_romask_T_459) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_459 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_459 = andr(_out_womask_T_459) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_459 = and(out_rivalid_1[337], out_rimask_459) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_459 = and(out_roready_1[337], out_romask_459) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_459 = and(out_wivalid_1[337], out_wimask_459) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_459 = and(out_woready_1[337], out_womask_459) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4693 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4694 = and(out_f_rivalid_459, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4695 = and(UInt<1>(0h1), out_f_roready_459) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4696 = eq(out_rimask_459, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4697 = eq(out_wimask_459, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4698 = eq(out_romask_459, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4699 = eq(out_womask_459, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_388 = or(_out_T_4692, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_388 = cat(_T_739, _out_prepend_T_388) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4700 = or(out_prepend_388, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4701 = bits(_out_T_4700, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_460 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_460 = orr(_out_rimask_T_460) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_460 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_460 = andr(_out_wimask_T_460) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_460 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_460 = orr(_out_romask_T_460) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_460 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_460 = andr(_out_womask_T_460) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_460 = and(out_rivalid_1[338], out_rimask_460) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_460 = and(out_roready_1[338], out_romask_460) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_460 = and(out_wivalid_1[338], out_wimask_460) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_460 = and(out_woready_1[338], out_womask_460) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4702 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4703 = and(out_f_rivalid_460, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4704 = and(UInt<1>(0h1), out_f_roready_460) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4705 = eq(out_rimask_460, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4706 = eq(out_wimask_460, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4707 = eq(out_romask_460, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4708 = eq(out_womask_460, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_389 = or(_out_T_4701, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_389 = cat(_T_740, _out_prepend_T_389) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4709 = or(out_prepend_389, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4710 = bits(_out_T_4709, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_461 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_461 = orr(_out_rimask_T_461) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_461 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_461 = andr(_out_wimask_T_461) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_461 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_461 = orr(_out_romask_T_461) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_461 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_461 = andr(_out_womask_T_461) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_461 = and(out_rivalid_1[339], out_rimask_461) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_461 = and(out_roready_1[339], out_romask_461) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_461 = and(out_wivalid_1[339], out_wimask_461) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_461 = and(out_woready_1[339], out_womask_461) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4711 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4712 = and(out_f_rivalid_461, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4713 = and(UInt<1>(0h1), out_f_roready_461) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4714 = eq(out_rimask_461, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4715 = eq(out_wimask_461, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4716 = eq(out_romask_461, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4717 = eq(out_womask_461, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_390 = or(_out_T_4710, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_390 = cat(_T_741, _out_prepend_T_390) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4718 = or(out_prepend_390, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4719 = bits(_out_T_4718, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_462 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_462 = orr(_out_rimask_T_462) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_462 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_462 = andr(_out_wimask_T_462) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_462 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_462 = orr(_out_romask_T_462) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_462 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_462 = andr(_out_womask_T_462) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_462 = and(out_rivalid_1[340], out_rimask_462) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_462 = and(out_roready_1[340], out_romask_462) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_462 = and(out_wivalid_1[340], out_wimask_462) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_462 = and(out_woready_1[340], out_womask_462) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4720 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4721 = and(out_f_rivalid_462, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4722 = and(UInt<1>(0h1), out_f_roready_462) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4723 = eq(out_rimask_462, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4724 = eq(out_wimask_462, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4725 = eq(out_romask_462, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4726 = eq(out_womask_462, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_391 = or(_out_T_4719, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_391 = cat(_T_742, _out_prepend_T_391) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4727 = or(out_prepend_391, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4728 = bits(_out_T_4727, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_463 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_463 = orr(_out_rimask_T_463) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_463 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_463 = andr(_out_wimask_T_463) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_463 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_463 = orr(_out_romask_T_463) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_463 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_463 = andr(_out_womask_T_463) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_463 = and(out_rivalid_1[341], out_rimask_463) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_463 = and(out_roready_1[341], out_romask_463) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_463 = and(out_wivalid_1[341], out_wimask_463) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_463 = and(out_woready_1[341], out_womask_463) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4729 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4730 = and(out_f_rivalid_463, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4731 = and(UInt<1>(0h1), out_f_roready_463) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4732 = eq(out_rimask_463, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4733 = eq(out_wimask_463, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4734 = eq(out_romask_463, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4735 = eq(out_womask_463, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_392 = or(_out_T_4728, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_392 = cat(_T_743, _out_prepend_T_392) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4736 = or(out_prepend_392, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4737 = bits(_out_T_4736, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_464 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_464 = orr(_out_rimask_T_464) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_464 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_464 = andr(_out_wimask_T_464) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_464 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_464 = orr(_out_romask_T_464) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_464 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_464 = andr(_out_womask_T_464) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_464 = and(out_rivalid_1[342], out_rimask_464) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_464 = and(out_roready_1[342], out_romask_464) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_464 = and(out_wivalid_1[342], out_wimask_464) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_464 = and(out_woready_1[342], out_womask_464) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4738 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4739 = and(out_f_rivalid_464, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4740 = and(UInt<1>(0h1), out_f_roready_464) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4741 = eq(out_rimask_464, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4742 = eq(out_wimask_464, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4743 = eq(out_romask_464, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4744 = eq(out_womask_464, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_393 = or(_out_T_4737, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_393 = cat(_T_744, _out_prepend_T_393) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4745 = or(out_prepend_393, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4746 = bits(_out_T_4745, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_465 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_465 = orr(_out_rimask_T_465) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_465 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_465 = andr(_out_wimask_T_465) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_465 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_465 = orr(_out_romask_T_465) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_465 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_465 = andr(_out_womask_T_465) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_465 = and(out_rivalid_1[343], out_rimask_465) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_465 = and(out_roready_1[343], out_romask_465) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_465 = and(out_wivalid_1[343], out_wimask_465) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_465 = and(out_woready_1[343], out_womask_465) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4747 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4748 = and(out_f_rivalid_465, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4749 = and(UInt<1>(0h1), out_f_roready_465) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4750 = eq(out_rimask_465, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4751 = eq(out_wimask_465, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4752 = eq(out_romask_465, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4753 = eq(out_womask_465, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_394 = or(_out_T_4746, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_394 = cat(_T_745, _out_prepend_T_394) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4754 = or(out_prepend_394, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4755 = bits(_out_T_4754, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_466 = bits(out_frontMask_1, 9, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_466 = orr(_out_rimask_T_466) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_466 = bits(out_frontMask_1, 9, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_466 = andr(_out_wimask_T_466) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_466 = bits(out_backMask_1, 9, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_466 = orr(_out_romask_T_466) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_466 = bits(out_backMask_1, 9, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_466 = andr(_out_womask_T_466) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_466 = and(out_rivalid_1[344], out_rimask_466) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_466 = and(out_roready_1[344], out_romask_466) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_466 = and(out_wivalid_1[344], out_wimask_466) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_466 = and(out_woready_1[344], out_womask_466) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4756 = bits(out_front_1.bits.data, 9, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect hartResumingWrEn, out_f_woready_466 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 282:11] connect hartResumingId, _out_T_4756 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 283:13] node _out_T_4757 = and(out_f_wivalid_466, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4758 = and(UInt<1>(0h1), out_f_woready_466) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4759 = eq(out_rimask_466, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4760 = eq(out_wimask_466, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4761 = eq(out_romask_466, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4762 = eq(out_womask_466, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4763 = or(UInt<1>(0h0), UInt<10>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4764 = bits(_out_T_4763, 9, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_467 = bits(out_frontMask_1, 41, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_467 = orr(_out_rimask_T_467) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_467 = bits(out_frontMask_1, 41, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_467 = andr(_out_wimask_T_467) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_467 = bits(out_backMask_1, 41, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_467 = orr(_out_romask_T_467) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_467 = bits(out_backMask_1, 41, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_467 = andr(_out_womask_T_467) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_467 = and(out_rivalid_1[345], out_rimask_467) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_467 = and(out_roready_1[345], out_romask_467) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_467 = and(out_wivalid_1[345], out_wimask_467) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_467 = and(out_woready_1[345], out_womask_467) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4765 = bits(out_front_1.bits.data, 41, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect hartExceptionWrEn, out_f_woready_467 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 282:11] connect hartExceptionId, _out_T_4765 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 283:13] node _out_T_4766 = and(out_f_wivalid_467, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4767 = and(UInt<1>(0h1), out_f_woready_467) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4768 = eq(out_rimask_467, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4769 = eq(out_wimask_467, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4770 = eq(out_romask_467, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4771 = eq(out_womask_467, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_395 = or(_out_T_4764, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_395 = cat(UInt<1>(0h0), _out_prepend_T_395) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4772 = or(out_prepend_395, UInt<42>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4773 = bits(_out_T_4772, 41, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_468 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_468 = orr(_out_rimask_T_468) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_468 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_468 = andr(_out_wimask_T_468) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_468 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_468 = orr(_out_romask_T_468) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_468 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_468 = andr(_out_womask_T_468) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_468 = and(out_rivalid_1[346], out_rimask_468) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_468 = and(out_roready_1[346], out_romask_468) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_468 = and(out_wivalid_1[346], out_wimask_468) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_468 = and(out_woready_1[346], out_womask_468) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4774 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4775 = and(out_f_rivalid_468, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4776 = and(UInt<1>(0h1), out_f_roready_468) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4777 = eq(out_rimask_468, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4778 = eq(out_wimask_468, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4779 = eq(out_romask_468, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4780 = eq(out_womask_468, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4781 = or(_T_1250, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4782 = bits(_out_T_4781, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_469 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_469 = orr(_out_rimask_T_469) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_469 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_469 = andr(_out_wimask_T_469) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_469 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_469 = orr(_out_romask_T_469) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_469 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_469 = andr(_out_womask_T_469) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_469 = and(out_rivalid_1[347], out_rimask_469) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_469 = and(out_roready_1[347], out_romask_469) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_469 = and(out_wivalid_1[347], out_wimask_469) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_469 = and(out_woready_1[347], out_womask_469) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4783 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4784 = and(out_f_rivalid_469, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4785 = and(UInt<1>(0h1), out_f_roready_469) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4786 = eq(out_rimask_469, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4787 = eq(out_wimask_469, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4788 = eq(out_romask_469, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4789 = eq(out_womask_469, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_396 = or(_out_T_4782, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_396 = cat(_T_1251, _out_prepend_T_396) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4790 = or(out_prepend_396, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4791 = bits(_out_T_4790, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_470 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_470 = orr(_out_rimask_T_470) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_470 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_470 = andr(_out_wimask_T_470) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_470 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_470 = orr(_out_romask_T_470) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_470 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_470 = andr(_out_womask_T_470) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_470 = and(out_rivalid_1[348], out_rimask_470) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_470 = and(out_roready_1[348], out_romask_470) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_470 = and(out_wivalid_1[348], out_wimask_470) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_470 = and(out_woready_1[348], out_womask_470) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4792 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4793 = and(out_f_rivalid_470, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4794 = and(UInt<1>(0h1), out_f_roready_470) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4795 = eq(out_rimask_470, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4796 = eq(out_wimask_470, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4797 = eq(out_romask_470, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4798 = eq(out_womask_470, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_397 = or(_out_T_4791, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_397 = cat(_T_1252, _out_prepend_T_397) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4799 = or(out_prepend_397, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4800 = bits(_out_T_4799, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_471 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_471 = orr(_out_rimask_T_471) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_471 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_471 = andr(_out_wimask_T_471) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_471 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_471 = orr(_out_romask_T_471) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_471 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_471 = andr(_out_womask_T_471) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_471 = and(out_rivalid_1[349], out_rimask_471) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_471 = and(out_roready_1[349], out_romask_471) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_471 = and(out_wivalid_1[349], out_wimask_471) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_471 = and(out_woready_1[349], out_womask_471) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4801 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4802 = and(out_f_rivalid_471, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4803 = and(UInt<1>(0h1), out_f_roready_471) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4804 = eq(out_rimask_471, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4805 = eq(out_wimask_471, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4806 = eq(out_romask_471, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4807 = eq(out_womask_471, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_398 = or(_out_T_4800, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_398 = cat(_T_1253, _out_prepend_T_398) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4808 = or(out_prepend_398, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4809 = bits(_out_T_4808, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_472 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_472 = orr(_out_rimask_T_472) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_472 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_472 = andr(_out_wimask_T_472) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_472 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_472 = orr(_out_romask_T_472) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_472 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_472 = andr(_out_womask_T_472) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_472 = and(out_rivalid_1[350], out_rimask_472) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_472 = and(out_roready_1[350], out_romask_472) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_472 = and(out_wivalid_1[350], out_wimask_472) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_472 = and(out_woready_1[350], out_womask_472) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4810 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4811 = and(out_f_rivalid_472, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4812 = and(UInt<1>(0h1), out_f_roready_472) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4813 = eq(out_rimask_472, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4814 = eq(out_wimask_472, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4815 = eq(out_romask_472, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4816 = eq(out_womask_472, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_399 = or(_out_T_4809, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_399 = cat(_T_1254, _out_prepend_T_399) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4817 = or(out_prepend_399, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4818 = bits(_out_T_4817, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_473 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_473 = orr(_out_rimask_T_473) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_473 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_473 = andr(_out_wimask_T_473) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_473 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_473 = orr(_out_romask_T_473) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_473 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_473 = andr(_out_womask_T_473) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_473 = and(out_rivalid_1[351], out_rimask_473) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_473 = and(out_roready_1[351], out_romask_473) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_473 = and(out_wivalid_1[351], out_wimask_473) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_473 = and(out_woready_1[351], out_womask_473) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4819 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4820 = and(out_f_rivalid_473, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4821 = and(UInt<1>(0h1), out_f_roready_473) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4822 = eq(out_rimask_473, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4823 = eq(out_wimask_473, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4824 = eq(out_romask_473, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4825 = eq(out_womask_473, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_400 = or(_out_T_4818, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_400 = cat(_T_1255, _out_prepend_T_400) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4826 = or(out_prepend_400, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4827 = bits(_out_T_4826, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_474 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_474 = orr(_out_rimask_T_474) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_474 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_474 = andr(_out_wimask_T_474) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_474 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_474 = orr(_out_romask_T_474) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_474 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_474 = andr(_out_womask_T_474) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_474 = and(out_rivalid_1[352], out_rimask_474) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_474 = and(out_roready_1[352], out_romask_474) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_474 = and(out_wivalid_1[352], out_wimask_474) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_474 = and(out_woready_1[352], out_womask_474) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4828 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4829 = and(out_f_rivalid_474, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4830 = and(UInt<1>(0h1), out_f_roready_474) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4831 = eq(out_rimask_474, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4832 = eq(out_wimask_474, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4833 = eq(out_romask_474, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4834 = eq(out_womask_474, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_401 = or(_out_T_4827, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_401 = cat(_T_1256, _out_prepend_T_401) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4835 = or(out_prepend_401, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4836 = bits(_out_T_4835, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_475 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_475 = orr(_out_rimask_T_475) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_475 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_475 = andr(_out_wimask_T_475) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_475 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_475 = orr(_out_romask_T_475) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_475 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_475 = andr(_out_womask_T_475) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_475 = and(out_rivalid_1[353], out_rimask_475) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_475 = and(out_roready_1[353], out_romask_475) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_475 = and(out_wivalid_1[353], out_wimask_475) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_475 = and(out_woready_1[353], out_womask_475) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4837 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4838 = and(out_f_rivalid_475, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4839 = and(UInt<1>(0h1), out_f_roready_475) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4840 = eq(out_rimask_475, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4841 = eq(out_wimask_475, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4842 = eq(out_romask_475, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4843 = eq(out_womask_475, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_402 = or(_out_T_4836, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_402 = cat(_T_1257, _out_prepend_T_402) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4844 = or(out_prepend_402, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4845 = bits(_out_T_4844, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_476 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_476 = orr(_out_rimask_T_476) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_476 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_476 = andr(_out_wimask_T_476) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_476 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_476 = orr(_out_romask_T_476) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_476 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_476 = andr(_out_womask_T_476) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_476 = and(out_rivalid_1[354], out_rimask_476) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_476 = and(out_roready_1[354], out_romask_476) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_476 = and(out_wivalid_1[354], out_wimask_476) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_476 = and(out_woready_1[354], out_womask_476) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4846 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4847 = and(out_f_rivalid_476, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4848 = and(UInt<1>(0h1), out_f_roready_476) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4849 = eq(out_rimask_476, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4850 = eq(out_wimask_476, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4851 = eq(out_romask_476, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4852 = eq(out_womask_476, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4853 = or(_T_1434, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4854 = bits(_out_T_4853, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_477 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_477 = orr(_out_rimask_T_477) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_477 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_477 = andr(_out_wimask_T_477) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_477 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_477 = orr(_out_romask_T_477) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_477 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_477 = andr(_out_womask_T_477) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_477 = and(out_rivalid_1[355], out_rimask_477) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_477 = and(out_roready_1[355], out_romask_477) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_477 = and(out_wivalid_1[355], out_wimask_477) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_477 = and(out_woready_1[355], out_womask_477) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4855 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4856 = and(out_f_rivalid_477, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4857 = and(UInt<1>(0h1), out_f_roready_477) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4858 = eq(out_rimask_477, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4859 = eq(out_wimask_477, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4860 = eq(out_romask_477, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4861 = eq(out_womask_477, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_403 = or(_out_T_4854, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_403 = cat(_T_1435, _out_prepend_T_403) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4862 = or(out_prepend_403, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4863 = bits(_out_T_4862, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_478 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_478 = orr(_out_rimask_T_478) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_478 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_478 = andr(_out_wimask_T_478) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_478 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_478 = orr(_out_romask_T_478) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_478 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_478 = andr(_out_womask_T_478) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_478 = and(out_rivalid_1[356], out_rimask_478) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_478 = and(out_roready_1[356], out_romask_478) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_478 = and(out_wivalid_1[356], out_wimask_478) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_478 = and(out_woready_1[356], out_womask_478) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4864 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4865 = and(out_f_rivalid_478, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4866 = and(UInt<1>(0h1), out_f_roready_478) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4867 = eq(out_rimask_478, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4868 = eq(out_wimask_478, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4869 = eq(out_romask_478, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4870 = eq(out_womask_478, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_404 = or(_out_T_4863, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_404 = cat(_T_1436, _out_prepend_T_404) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4871 = or(out_prepend_404, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4872 = bits(_out_T_4871, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_479 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_479 = orr(_out_rimask_T_479) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_479 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_479 = andr(_out_wimask_T_479) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_479 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_479 = orr(_out_romask_T_479) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_479 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_479 = andr(_out_womask_T_479) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_479 = and(out_rivalid_1[357], out_rimask_479) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_479 = and(out_roready_1[357], out_romask_479) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_479 = and(out_wivalid_1[357], out_wimask_479) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_479 = and(out_woready_1[357], out_womask_479) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4873 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4874 = and(out_f_rivalid_479, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4875 = and(UInt<1>(0h1), out_f_roready_479) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4876 = eq(out_rimask_479, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4877 = eq(out_wimask_479, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4878 = eq(out_romask_479, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4879 = eq(out_womask_479, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_405 = or(_out_T_4872, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_405 = cat(_T_1437, _out_prepend_T_405) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4880 = or(out_prepend_405, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4881 = bits(_out_T_4880, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_480 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_480 = orr(_out_rimask_T_480) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_480 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_480 = andr(_out_wimask_T_480) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_480 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_480 = orr(_out_romask_T_480) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_480 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_480 = andr(_out_womask_T_480) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_480 = and(out_rivalid_1[358], out_rimask_480) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_480 = and(out_roready_1[358], out_romask_480) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_480 = and(out_wivalid_1[358], out_wimask_480) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_480 = and(out_woready_1[358], out_womask_480) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4882 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4883 = and(out_f_rivalid_480, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4884 = and(UInt<1>(0h1), out_f_roready_480) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4885 = eq(out_rimask_480, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4886 = eq(out_wimask_480, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4887 = eq(out_romask_480, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4888 = eq(out_womask_480, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_406 = or(_out_T_4881, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_406 = cat(_T_1438, _out_prepend_T_406) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4889 = or(out_prepend_406, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4890 = bits(_out_T_4889, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_481 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_481 = orr(_out_rimask_T_481) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_481 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_481 = andr(_out_wimask_T_481) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_481 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_481 = orr(_out_romask_T_481) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_481 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_481 = andr(_out_womask_T_481) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_481 = and(out_rivalid_1[359], out_rimask_481) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_481 = and(out_roready_1[359], out_romask_481) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_481 = and(out_wivalid_1[359], out_wimask_481) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_481 = and(out_woready_1[359], out_womask_481) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4891 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4892 = and(out_f_rivalid_481, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4893 = and(UInt<1>(0h1), out_f_roready_481) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4894 = eq(out_rimask_481, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4895 = eq(out_wimask_481, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4896 = eq(out_romask_481, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4897 = eq(out_womask_481, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_407 = or(_out_T_4890, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_407 = cat(_T_1439, _out_prepend_T_407) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4898 = or(out_prepend_407, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4899 = bits(_out_T_4898, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_482 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_482 = orr(_out_rimask_T_482) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_482 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_482 = andr(_out_wimask_T_482) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_482 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_482 = orr(_out_romask_T_482) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_482 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_482 = andr(_out_womask_T_482) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_482 = and(out_rivalid_1[360], out_rimask_482) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_482 = and(out_roready_1[360], out_romask_482) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_482 = and(out_wivalid_1[360], out_wimask_482) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_482 = and(out_woready_1[360], out_womask_482) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4900 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4901 = and(out_f_rivalid_482, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4902 = and(UInt<1>(0h1), out_f_roready_482) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4903 = eq(out_rimask_482, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4904 = eq(out_wimask_482, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4905 = eq(out_romask_482, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4906 = eq(out_womask_482, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_408 = or(_out_T_4899, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_408 = cat(_T_1440, _out_prepend_T_408) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4907 = or(out_prepend_408, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4908 = bits(_out_T_4907, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_483 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_483 = orr(_out_rimask_T_483) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_483 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_483 = andr(_out_wimask_T_483) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_483 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_483 = orr(_out_romask_T_483) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_483 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_483 = andr(_out_womask_T_483) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_483 = and(out_rivalid_1[361], out_rimask_483) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_483 = and(out_roready_1[361], out_romask_483) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_483 = and(out_wivalid_1[361], out_wimask_483) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_483 = and(out_woready_1[361], out_womask_483) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4909 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4910 = and(out_f_rivalid_483, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4911 = and(UInt<1>(0h1), out_f_roready_483) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4912 = eq(out_rimask_483, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4913 = eq(out_wimask_483, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4914 = eq(out_romask_483, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4915 = eq(out_womask_483, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_409 = or(_out_T_4908, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_409 = cat(_T_1441, _out_prepend_T_409) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4916 = or(out_prepend_409, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4917 = bits(_out_T_4916, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_484 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_484 = orr(_out_rimask_T_484) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_484 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_484 = andr(_out_wimask_T_484) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_484 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_484 = orr(_out_romask_T_484) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_484 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_484 = andr(_out_womask_T_484) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_484 = and(out_rivalid_1[362], out_rimask_484) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_484 = and(out_roready_1[362], out_romask_484) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_484 = and(out_wivalid_1[362], out_wimask_484) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_484 = and(out_woready_1[362], out_womask_484) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4918 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4919 = and(out_f_rivalid_484, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4920 = and(UInt<1>(0h1), out_f_roready_484) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4921 = eq(out_rimask_484, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4922 = eq(out_wimask_484, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4923 = eq(out_romask_484, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4924 = eq(out_womask_484, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4925 = or(_T_994, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4926 = bits(_out_T_4925, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_485 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_485 = orr(_out_rimask_T_485) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_485 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_485 = andr(_out_wimask_T_485) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_485 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_485 = orr(_out_romask_T_485) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_485 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_485 = andr(_out_womask_T_485) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_485 = and(out_rivalid_1[363], out_rimask_485) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_485 = and(out_roready_1[363], out_romask_485) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_485 = and(out_wivalid_1[363], out_wimask_485) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_485 = and(out_woready_1[363], out_womask_485) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4927 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4928 = and(out_f_rivalid_485, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4929 = and(UInt<1>(0h1), out_f_roready_485) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4930 = eq(out_rimask_485, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4931 = eq(out_wimask_485, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4932 = eq(out_romask_485, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4933 = eq(out_womask_485, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_410 = or(_out_T_4926, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_410 = cat(_T_995, _out_prepend_T_410) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4934 = or(out_prepend_410, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4935 = bits(_out_T_4934, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_486 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_486 = orr(_out_rimask_T_486) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_486 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_486 = andr(_out_wimask_T_486) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_486 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_486 = orr(_out_romask_T_486) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_486 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_486 = andr(_out_womask_T_486) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_486 = and(out_rivalid_1[364], out_rimask_486) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_486 = and(out_roready_1[364], out_romask_486) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_486 = and(out_wivalid_1[364], out_wimask_486) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_486 = and(out_woready_1[364], out_womask_486) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4936 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4937 = and(out_f_rivalid_486, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4938 = and(UInt<1>(0h1), out_f_roready_486) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4939 = eq(out_rimask_486, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4940 = eq(out_wimask_486, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4941 = eq(out_romask_486, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4942 = eq(out_womask_486, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_411 = or(_out_T_4935, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_411 = cat(_T_996, _out_prepend_T_411) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4943 = or(out_prepend_411, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4944 = bits(_out_T_4943, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_487 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_487 = orr(_out_rimask_T_487) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_487 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_487 = andr(_out_wimask_T_487) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_487 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_487 = orr(_out_romask_T_487) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_487 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_487 = andr(_out_womask_T_487) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_487 = and(out_rivalid_1[365], out_rimask_487) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_487 = and(out_roready_1[365], out_romask_487) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_487 = and(out_wivalid_1[365], out_wimask_487) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_487 = and(out_woready_1[365], out_womask_487) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4945 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4946 = and(out_f_rivalid_487, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4947 = and(UInt<1>(0h1), out_f_roready_487) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4948 = eq(out_rimask_487, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4949 = eq(out_wimask_487, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4950 = eq(out_romask_487, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4951 = eq(out_womask_487, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_412 = or(_out_T_4944, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_412 = cat(_T_997, _out_prepend_T_412) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4952 = or(out_prepend_412, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4953 = bits(_out_T_4952, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_488 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_488 = orr(_out_rimask_T_488) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_488 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_488 = andr(_out_wimask_T_488) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_488 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_488 = orr(_out_romask_T_488) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_488 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_488 = andr(_out_womask_T_488) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_488 = and(out_rivalid_1[366], out_rimask_488) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_488 = and(out_roready_1[366], out_romask_488) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_488 = and(out_wivalid_1[366], out_wimask_488) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_488 = and(out_woready_1[366], out_womask_488) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4954 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4955 = and(out_f_rivalid_488, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4956 = and(UInt<1>(0h1), out_f_roready_488) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4957 = eq(out_rimask_488, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4958 = eq(out_wimask_488, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4959 = eq(out_romask_488, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4960 = eq(out_womask_488, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_413 = or(_out_T_4953, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_413 = cat(_T_998, _out_prepend_T_413) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4961 = or(out_prepend_413, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4962 = bits(_out_T_4961, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_489 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_489 = orr(_out_rimask_T_489) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_489 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_489 = andr(_out_wimask_T_489) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_489 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_489 = orr(_out_romask_T_489) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_489 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_489 = andr(_out_womask_T_489) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_489 = and(out_rivalid_1[367], out_rimask_489) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_489 = and(out_roready_1[367], out_romask_489) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_489 = and(out_wivalid_1[367], out_wimask_489) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_489 = and(out_woready_1[367], out_womask_489) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4963 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4964 = and(out_f_rivalid_489, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4965 = and(UInt<1>(0h1), out_f_roready_489) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4966 = eq(out_rimask_489, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4967 = eq(out_wimask_489, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4968 = eq(out_romask_489, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4969 = eq(out_womask_489, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_414 = or(_out_T_4962, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_414 = cat(_T_999, _out_prepend_T_414) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4970 = or(out_prepend_414, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4971 = bits(_out_T_4970, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_490 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_490 = orr(_out_rimask_T_490) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_490 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_490 = andr(_out_wimask_T_490) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_490 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_490 = orr(_out_romask_T_490) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_490 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_490 = andr(_out_womask_T_490) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_490 = and(out_rivalid_1[368], out_rimask_490) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_490 = and(out_roready_1[368], out_romask_490) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_490 = and(out_wivalid_1[368], out_wimask_490) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_490 = and(out_woready_1[368], out_womask_490) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4972 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4973 = and(out_f_rivalid_490, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4974 = and(UInt<1>(0h1), out_f_roready_490) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4975 = eq(out_rimask_490, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4976 = eq(out_wimask_490, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4977 = eq(out_romask_490, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4978 = eq(out_womask_490, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_415 = or(_out_T_4971, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_415 = cat(_T_1000, _out_prepend_T_415) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4979 = or(out_prepend_415, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4980 = bits(_out_T_4979, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_491 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_491 = orr(_out_rimask_T_491) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_491 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_491 = andr(_out_wimask_T_491) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_491 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_491 = orr(_out_romask_T_491) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_491 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_491 = andr(_out_womask_T_491) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_491 = and(out_rivalid_1[369], out_rimask_491) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_491 = and(out_roready_1[369], out_romask_491) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_491 = and(out_wivalid_1[369], out_wimask_491) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_491 = and(out_woready_1[369], out_womask_491) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4981 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4982 = and(out_f_rivalid_491, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4983 = and(UInt<1>(0h1), out_f_roready_491) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4984 = eq(out_rimask_491, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4985 = eq(out_wimask_491, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4986 = eq(out_romask_491, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4987 = eq(out_womask_491, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_416 = or(_out_T_4980, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_416 = cat(_T_1001, _out_prepend_T_416) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4988 = or(out_prepend_416, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4989 = bits(_out_T_4988, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_492 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_492 = orr(_out_rimask_T_492) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_492 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_492 = andr(_out_wimask_T_492) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_492 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_492 = orr(_out_romask_T_492) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_492 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_492 = andr(_out_womask_T_492) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_492 = and(out_rivalid_1[370], out_rimask_492) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_492 = and(out_roready_1[370], out_romask_492) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_492 = and(out_wivalid_1[370], out_wimask_492) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_492 = and(out_woready_1[370], out_womask_492) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4990 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4991 = and(out_f_rivalid_492, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4992 = and(UInt<1>(0h1), out_f_roready_492) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4993 = eq(out_rimask_492, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4994 = eq(out_wimask_492, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4995 = eq(out_romask_492, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4996 = eq(out_womask_492, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4997 = or(_T_1210, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4998 = bits(_out_T_4997, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_493 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_493 = orr(_out_rimask_T_493) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_493 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_493 = andr(_out_wimask_T_493) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_493 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_493 = orr(_out_romask_T_493) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_493 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_493 = andr(_out_womask_T_493) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_493 = and(out_rivalid_1[371], out_rimask_493) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_493 = and(out_roready_1[371], out_romask_493) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_493 = and(out_wivalid_1[371], out_wimask_493) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_493 = and(out_woready_1[371], out_womask_493) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4999 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5000 = and(out_f_rivalid_493, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5001 = and(UInt<1>(0h1), out_f_roready_493) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5002 = eq(out_rimask_493, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5003 = eq(out_wimask_493, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5004 = eq(out_romask_493, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5005 = eq(out_womask_493, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_417 = or(_out_T_4998, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_417 = cat(_T_1211, _out_prepend_T_417) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5006 = or(out_prepend_417, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5007 = bits(_out_T_5006, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_494 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_494 = orr(_out_rimask_T_494) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_494 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_494 = andr(_out_wimask_T_494) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_494 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_494 = orr(_out_romask_T_494) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_494 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_494 = andr(_out_womask_T_494) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_494 = and(out_rivalid_1[372], out_rimask_494) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_494 = and(out_roready_1[372], out_romask_494) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_494 = and(out_wivalid_1[372], out_wimask_494) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_494 = and(out_woready_1[372], out_womask_494) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5008 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5009 = and(out_f_rivalid_494, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5010 = and(UInt<1>(0h1), out_f_roready_494) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5011 = eq(out_rimask_494, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5012 = eq(out_wimask_494, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5013 = eq(out_romask_494, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5014 = eq(out_womask_494, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_418 = or(_out_T_5007, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_418 = cat(_T_1212, _out_prepend_T_418) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5015 = or(out_prepend_418, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5016 = bits(_out_T_5015, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_495 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_495 = orr(_out_rimask_T_495) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_495 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_495 = andr(_out_wimask_T_495) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_495 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_495 = orr(_out_romask_T_495) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_495 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_495 = andr(_out_womask_T_495) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_495 = and(out_rivalid_1[373], out_rimask_495) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_495 = and(out_roready_1[373], out_romask_495) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_495 = and(out_wivalid_1[373], out_wimask_495) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_495 = and(out_woready_1[373], out_womask_495) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5017 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5018 = and(out_f_rivalid_495, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5019 = and(UInt<1>(0h1), out_f_roready_495) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5020 = eq(out_rimask_495, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5021 = eq(out_wimask_495, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5022 = eq(out_romask_495, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5023 = eq(out_womask_495, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_419 = or(_out_T_5016, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_419 = cat(_T_1213, _out_prepend_T_419) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5024 = or(out_prepend_419, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5025 = bits(_out_T_5024, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_496 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_496 = orr(_out_rimask_T_496) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_496 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_496 = andr(_out_wimask_T_496) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_496 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_496 = orr(_out_romask_T_496) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_496 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_496 = andr(_out_womask_T_496) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_496 = and(out_rivalid_1[374], out_rimask_496) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_496 = and(out_roready_1[374], out_romask_496) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_496 = and(out_wivalid_1[374], out_wimask_496) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_496 = and(out_woready_1[374], out_womask_496) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5026 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5027 = and(out_f_rivalid_496, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5028 = and(UInt<1>(0h1), out_f_roready_496) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5029 = eq(out_rimask_496, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5030 = eq(out_wimask_496, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5031 = eq(out_romask_496, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5032 = eq(out_womask_496, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_420 = or(_out_T_5025, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_420 = cat(_T_1214, _out_prepend_T_420) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5033 = or(out_prepend_420, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5034 = bits(_out_T_5033, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_497 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_497 = orr(_out_rimask_T_497) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_497 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_497 = andr(_out_wimask_T_497) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_497 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_497 = orr(_out_romask_T_497) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_497 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_497 = andr(_out_womask_T_497) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_497 = and(out_rivalid_1[375], out_rimask_497) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_497 = and(out_roready_1[375], out_romask_497) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_497 = and(out_wivalid_1[375], out_wimask_497) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_497 = and(out_woready_1[375], out_womask_497) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5035 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5036 = and(out_f_rivalid_497, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5037 = and(UInt<1>(0h1), out_f_roready_497) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5038 = eq(out_rimask_497, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5039 = eq(out_wimask_497, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5040 = eq(out_romask_497, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5041 = eq(out_womask_497, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_421 = or(_out_T_5034, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_421 = cat(_T_1215, _out_prepend_T_421) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5042 = or(out_prepend_421, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5043 = bits(_out_T_5042, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_498 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_498 = orr(_out_rimask_T_498) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_498 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_498 = andr(_out_wimask_T_498) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_498 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_498 = orr(_out_romask_T_498) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_498 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_498 = andr(_out_womask_T_498) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_498 = and(out_rivalid_1[376], out_rimask_498) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_498 = and(out_roready_1[376], out_romask_498) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_498 = and(out_wivalid_1[376], out_wimask_498) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_498 = and(out_woready_1[376], out_womask_498) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5044 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5045 = and(out_f_rivalid_498, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5046 = and(UInt<1>(0h1), out_f_roready_498) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5047 = eq(out_rimask_498, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5048 = eq(out_wimask_498, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5049 = eq(out_romask_498, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5050 = eq(out_womask_498, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_422 = or(_out_T_5043, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_422 = cat(_T_1216, _out_prepend_T_422) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5051 = or(out_prepend_422, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5052 = bits(_out_T_5051, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_499 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_499 = orr(_out_rimask_T_499) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_499 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_499 = andr(_out_wimask_T_499) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_499 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_499 = orr(_out_romask_T_499) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_499 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_499 = andr(_out_womask_T_499) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_499 = and(out_rivalid_1[377], out_rimask_499) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_499 = and(out_roready_1[377], out_romask_499) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_499 = and(out_wivalid_1[377], out_wimask_499) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_499 = and(out_woready_1[377], out_womask_499) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5053 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5054 = and(out_f_rivalid_499, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5055 = and(UInt<1>(0h1), out_f_roready_499) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5056 = eq(out_rimask_499, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5057 = eq(out_wimask_499, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5058 = eq(out_romask_499, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5059 = eq(out_womask_499, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_423 = or(_out_T_5052, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_423 = cat(_T_1217, _out_prepend_T_423) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5060 = or(out_prepend_423, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5061 = bits(_out_T_5060, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_500 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_500 = orr(_out_rimask_T_500) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_500 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_500 = andr(_out_wimask_T_500) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_500 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_500 = orr(_out_romask_T_500) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_500 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_500 = andr(_out_womask_T_500) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_500 = and(out_rivalid_1[378], out_rimask_500) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_500 = and(out_roready_1[378], out_romask_500) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_500 = and(out_wivalid_1[378], out_wimask_500) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_500 = and(out_woready_1[378], out_womask_500) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5062 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5063 = and(out_f_rivalid_500, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5064 = and(UInt<1>(0h1), out_f_roready_500) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5065 = eq(out_rimask_500, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5066 = eq(out_wimask_500, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5067 = eq(out_romask_500, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5068 = eq(out_womask_500, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5069 = or(_T_666, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5070 = bits(_out_T_5069, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_501 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_501 = orr(_out_rimask_T_501) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_501 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_501 = andr(_out_wimask_T_501) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_501 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_501 = orr(_out_romask_T_501) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_501 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_501 = andr(_out_womask_T_501) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_501 = and(out_rivalid_1[379], out_rimask_501) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_501 = and(out_roready_1[379], out_romask_501) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_501 = and(out_wivalid_1[379], out_wimask_501) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_501 = and(out_woready_1[379], out_womask_501) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5071 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5072 = and(out_f_rivalid_501, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5073 = and(UInt<1>(0h1), out_f_roready_501) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5074 = eq(out_rimask_501, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5075 = eq(out_wimask_501, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5076 = eq(out_romask_501, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5077 = eq(out_womask_501, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_424 = or(_out_T_5070, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_424 = cat(_T_667, _out_prepend_T_424) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5078 = or(out_prepend_424, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5079 = bits(_out_T_5078, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_502 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_502 = orr(_out_rimask_T_502) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_502 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_502 = andr(_out_wimask_T_502) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_502 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_502 = orr(_out_romask_T_502) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_502 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_502 = andr(_out_womask_T_502) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_502 = and(out_rivalid_1[380], out_rimask_502) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_502 = and(out_roready_1[380], out_romask_502) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_502 = and(out_wivalid_1[380], out_wimask_502) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_502 = and(out_woready_1[380], out_womask_502) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5080 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5081 = and(out_f_rivalid_502, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5082 = and(UInt<1>(0h1), out_f_roready_502) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5083 = eq(out_rimask_502, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5084 = eq(out_wimask_502, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5085 = eq(out_romask_502, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5086 = eq(out_womask_502, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_425 = or(_out_T_5079, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_425 = cat(_T_668, _out_prepend_T_425) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5087 = or(out_prepend_425, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5088 = bits(_out_T_5087, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_503 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_503 = orr(_out_rimask_T_503) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_503 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_503 = andr(_out_wimask_T_503) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_503 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_503 = orr(_out_romask_T_503) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_503 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_503 = andr(_out_womask_T_503) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_503 = and(out_rivalid_1[381], out_rimask_503) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_503 = and(out_roready_1[381], out_romask_503) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_503 = and(out_wivalid_1[381], out_wimask_503) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_503 = and(out_woready_1[381], out_womask_503) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5089 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5090 = and(out_f_rivalid_503, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5091 = and(UInt<1>(0h1), out_f_roready_503) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5092 = eq(out_rimask_503, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5093 = eq(out_wimask_503, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5094 = eq(out_romask_503, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5095 = eq(out_womask_503, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_426 = or(_out_T_5088, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_426 = cat(_T_669, _out_prepend_T_426) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5096 = or(out_prepend_426, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5097 = bits(_out_T_5096, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_504 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_504 = orr(_out_rimask_T_504) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_504 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_504 = andr(_out_wimask_T_504) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_504 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_504 = orr(_out_romask_T_504) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_504 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_504 = andr(_out_womask_T_504) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_504 = and(out_rivalid_1[382], out_rimask_504) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_504 = and(out_roready_1[382], out_romask_504) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_504 = and(out_wivalid_1[382], out_wimask_504) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_504 = and(out_woready_1[382], out_womask_504) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5098 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5099 = and(out_f_rivalid_504, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5100 = and(UInt<1>(0h1), out_f_roready_504) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5101 = eq(out_rimask_504, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5102 = eq(out_wimask_504, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5103 = eq(out_romask_504, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5104 = eq(out_womask_504, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_427 = or(_out_T_5097, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_427 = cat(_T_670, _out_prepend_T_427) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5105 = or(out_prepend_427, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5106 = bits(_out_T_5105, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_505 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_505 = orr(_out_rimask_T_505) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_505 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_505 = andr(_out_wimask_T_505) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_505 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_505 = orr(_out_romask_T_505) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_505 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_505 = andr(_out_womask_T_505) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_505 = and(out_rivalid_1[383], out_rimask_505) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_505 = and(out_roready_1[383], out_romask_505) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_505 = and(out_wivalid_1[383], out_wimask_505) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_505 = and(out_woready_1[383], out_womask_505) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5107 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5108 = and(out_f_rivalid_505, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5109 = and(UInt<1>(0h1), out_f_roready_505) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5110 = eq(out_rimask_505, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5111 = eq(out_wimask_505, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5112 = eq(out_romask_505, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5113 = eq(out_womask_505, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_428 = or(_out_T_5106, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_428 = cat(_T_671, _out_prepend_T_428) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5114 = or(out_prepend_428, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5115 = bits(_out_T_5114, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_506 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_506 = orr(_out_rimask_T_506) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_506 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_506 = andr(_out_wimask_T_506) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_506 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_506 = orr(_out_romask_T_506) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_506 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_506 = andr(_out_womask_T_506) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_506 = and(out_rivalid_1[384], out_rimask_506) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_506 = and(out_roready_1[384], out_romask_506) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_506 = and(out_wivalid_1[384], out_wimask_506) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_506 = and(out_woready_1[384], out_womask_506) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5116 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5117 = and(out_f_rivalid_506, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5118 = and(UInt<1>(0h1), out_f_roready_506) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5119 = eq(out_rimask_506, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5120 = eq(out_wimask_506, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5121 = eq(out_romask_506, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5122 = eq(out_womask_506, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_429 = or(_out_T_5115, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_429 = cat(_T_672, _out_prepend_T_429) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5123 = or(out_prepend_429, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5124 = bits(_out_T_5123, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_507 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_507 = orr(_out_rimask_T_507) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_507 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_507 = andr(_out_wimask_T_507) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_507 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_507 = orr(_out_romask_T_507) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_507 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_507 = andr(_out_womask_T_507) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_507 = and(out_rivalid_1[385], out_rimask_507) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_507 = and(out_roready_1[385], out_romask_507) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_507 = and(out_wivalid_1[385], out_wimask_507) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_507 = and(out_woready_1[385], out_womask_507) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5125 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5126 = and(out_f_rivalid_507, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5127 = and(UInt<1>(0h1), out_f_roready_507) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5128 = eq(out_rimask_507, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5129 = eq(out_wimask_507, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5130 = eq(out_romask_507, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5131 = eq(out_womask_507, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_430 = or(_out_T_5124, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_430 = cat(_T_673, _out_prepend_T_430) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5132 = or(out_prepend_430, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5133 = bits(_out_T_5132, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_508 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_508 = orr(_out_rimask_T_508) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_508 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_508 = andr(_out_wimask_T_508) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_508 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_508 = orr(_out_romask_T_508) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_508 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_508 = andr(_out_womask_T_508) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_508 = and(out_rivalid_1[386], out_rimask_508) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_508 = and(out_roready_1[386], out_romask_508) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_508 = and(out_wivalid_1[386], out_wimask_508) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_508 = and(out_woready_1[386], out_womask_508) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5134 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5135 = and(out_f_rivalid_508, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5136 = and(UInt<1>(0h1), out_f_roready_508) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5137 = eq(out_rimask_508, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5138 = eq(out_wimask_508, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5139 = eq(out_romask_508, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5140 = eq(out_womask_508, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5141 = or(_T_922, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5142 = bits(_out_T_5141, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_509 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_509 = orr(_out_rimask_T_509) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_509 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_509 = andr(_out_wimask_T_509) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_509 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_509 = orr(_out_romask_T_509) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_509 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_509 = andr(_out_womask_T_509) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_509 = and(out_rivalid_1[387], out_rimask_509) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_509 = and(out_roready_1[387], out_romask_509) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_509 = and(out_wivalid_1[387], out_wimask_509) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_509 = and(out_woready_1[387], out_womask_509) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5143 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5144 = and(out_f_rivalid_509, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5145 = and(UInt<1>(0h1), out_f_roready_509) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5146 = eq(out_rimask_509, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5147 = eq(out_wimask_509, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5148 = eq(out_romask_509, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5149 = eq(out_womask_509, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_431 = or(_out_T_5142, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_431 = cat(_T_923, _out_prepend_T_431) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5150 = or(out_prepend_431, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5151 = bits(_out_T_5150, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_510 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_510 = orr(_out_rimask_T_510) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_510 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_510 = andr(_out_wimask_T_510) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_510 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_510 = orr(_out_romask_T_510) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_510 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_510 = andr(_out_womask_T_510) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_510 = and(out_rivalid_1[388], out_rimask_510) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_510 = and(out_roready_1[388], out_romask_510) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_510 = and(out_wivalid_1[388], out_wimask_510) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_510 = and(out_woready_1[388], out_womask_510) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5152 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5153 = and(out_f_rivalid_510, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5154 = and(UInt<1>(0h1), out_f_roready_510) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5155 = eq(out_rimask_510, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5156 = eq(out_wimask_510, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5157 = eq(out_romask_510, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5158 = eq(out_womask_510, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_432 = or(_out_T_5151, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_432 = cat(_T_924, _out_prepend_T_432) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5159 = or(out_prepend_432, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5160 = bits(_out_T_5159, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_511 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_511 = orr(_out_rimask_T_511) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_511 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_511 = andr(_out_wimask_T_511) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_511 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_511 = orr(_out_romask_T_511) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_511 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_511 = andr(_out_womask_T_511) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_511 = and(out_rivalid_1[389], out_rimask_511) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_511 = and(out_roready_1[389], out_romask_511) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_511 = and(out_wivalid_1[389], out_wimask_511) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_511 = and(out_woready_1[389], out_womask_511) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5161 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5162 = and(out_f_rivalid_511, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5163 = and(UInt<1>(0h1), out_f_roready_511) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5164 = eq(out_rimask_511, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5165 = eq(out_wimask_511, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5166 = eq(out_romask_511, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5167 = eq(out_womask_511, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_433 = or(_out_T_5160, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_433 = cat(_T_925, _out_prepend_T_433) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5168 = or(out_prepend_433, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5169 = bits(_out_T_5168, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_512 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_512 = orr(_out_rimask_T_512) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_512 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_512 = andr(_out_wimask_T_512) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_512 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_512 = orr(_out_romask_T_512) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_512 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_512 = andr(_out_womask_T_512) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_512 = and(out_rivalid_1[390], out_rimask_512) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_512 = and(out_roready_1[390], out_romask_512) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_512 = and(out_wivalid_1[390], out_wimask_512) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_512 = and(out_woready_1[390], out_womask_512) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5170 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5171 = and(out_f_rivalid_512, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5172 = and(UInt<1>(0h1), out_f_roready_512) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5173 = eq(out_rimask_512, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5174 = eq(out_wimask_512, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5175 = eq(out_romask_512, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5176 = eq(out_womask_512, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_434 = or(_out_T_5169, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_434 = cat(_T_926, _out_prepend_T_434) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5177 = or(out_prepend_434, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5178 = bits(_out_T_5177, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_513 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_513 = orr(_out_rimask_T_513) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_513 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_513 = andr(_out_wimask_T_513) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_513 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_513 = orr(_out_romask_T_513) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_513 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_513 = andr(_out_womask_T_513) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_513 = and(out_rivalid_1[391], out_rimask_513) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_513 = and(out_roready_1[391], out_romask_513) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_513 = and(out_wivalid_1[391], out_wimask_513) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_513 = and(out_woready_1[391], out_womask_513) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5179 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5180 = and(out_f_rivalid_513, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5181 = and(UInt<1>(0h1), out_f_roready_513) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5182 = eq(out_rimask_513, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5183 = eq(out_wimask_513, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5184 = eq(out_romask_513, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5185 = eq(out_womask_513, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_435 = or(_out_T_5178, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_435 = cat(_T_927, _out_prepend_T_435) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5186 = or(out_prepend_435, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5187 = bits(_out_T_5186, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_514 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_514 = orr(_out_rimask_T_514) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_514 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_514 = andr(_out_wimask_T_514) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_514 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_514 = orr(_out_romask_T_514) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_514 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_514 = andr(_out_womask_T_514) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_514 = and(out_rivalid_1[392], out_rimask_514) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_514 = and(out_roready_1[392], out_romask_514) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_514 = and(out_wivalid_1[392], out_wimask_514) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_514 = and(out_woready_1[392], out_womask_514) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5188 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5189 = and(out_f_rivalid_514, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5190 = and(UInt<1>(0h1), out_f_roready_514) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5191 = eq(out_rimask_514, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5192 = eq(out_wimask_514, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5193 = eq(out_romask_514, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5194 = eq(out_womask_514, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_436 = or(_out_T_5187, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_436 = cat(_T_928, _out_prepend_T_436) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5195 = or(out_prepend_436, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5196 = bits(_out_T_5195, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_515 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_515 = orr(_out_rimask_T_515) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_515 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_515 = andr(_out_wimask_T_515) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_515 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_515 = orr(_out_romask_T_515) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_515 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_515 = andr(_out_womask_T_515) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_515 = and(out_rivalid_1[393], out_rimask_515) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_515 = and(out_roready_1[393], out_romask_515) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_515 = and(out_wivalid_1[393], out_wimask_515) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_515 = and(out_woready_1[393], out_womask_515) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5197 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5198 = and(out_f_rivalid_515, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5199 = and(UInt<1>(0h1), out_f_roready_515) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5200 = eq(out_rimask_515, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5201 = eq(out_wimask_515, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5202 = eq(out_romask_515, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5203 = eq(out_womask_515, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_437 = or(_out_T_5196, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_437 = cat(_T_929, _out_prepend_T_437) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5204 = or(out_prepend_437, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5205 = bits(_out_T_5204, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_516 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_516 = orr(_out_rimask_T_516) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_516 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_516 = andr(_out_wimask_T_516) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_516 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_516 = orr(_out_romask_T_516) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_516 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_516 = andr(_out_womask_T_516) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_516 = and(out_rivalid_1[394], out_rimask_516) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_516 = and(out_roready_1[394], out_romask_516) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_516 = and(out_wivalid_1[394], out_wimask_516) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_516 = and(out_woready_1[394], out_womask_516) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5206 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5207 = and(out_f_rivalid_516, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5208 = and(UInt<1>(0h1), out_f_roready_516) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5209 = eq(out_rimask_516, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5210 = eq(out_wimask_516, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5211 = eq(out_romask_516, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5212 = eq(out_womask_516, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5213 = or(_T_770, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5214 = bits(_out_T_5213, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_517 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_517 = orr(_out_rimask_T_517) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_517 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_517 = andr(_out_wimask_T_517) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_517 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_517 = orr(_out_romask_T_517) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_517 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_517 = andr(_out_womask_T_517) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_517 = and(out_rivalid_1[395], out_rimask_517) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_517 = and(out_roready_1[395], out_romask_517) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_517 = and(out_wivalid_1[395], out_wimask_517) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_517 = and(out_woready_1[395], out_womask_517) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5215 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5216 = and(out_f_rivalid_517, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5217 = and(UInt<1>(0h1), out_f_roready_517) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5218 = eq(out_rimask_517, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5219 = eq(out_wimask_517, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5220 = eq(out_romask_517, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5221 = eq(out_womask_517, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_438 = or(_out_T_5214, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_438 = cat(_T_771, _out_prepend_T_438) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5222 = or(out_prepend_438, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5223 = bits(_out_T_5222, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_518 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_518 = orr(_out_rimask_T_518) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_518 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_518 = andr(_out_wimask_T_518) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_518 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_518 = orr(_out_romask_T_518) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_518 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_518 = andr(_out_womask_T_518) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_518 = and(out_rivalid_1[396], out_rimask_518) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_518 = and(out_roready_1[396], out_romask_518) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_518 = and(out_wivalid_1[396], out_wimask_518) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_518 = and(out_woready_1[396], out_womask_518) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5224 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5225 = and(out_f_rivalid_518, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5226 = and(UInt<1>(0h1), out_f_roready_518) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5227 = eq(out_rimask_518, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5228 = eq(out_wimask_518, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5229 = eq(out_romask_518, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5230 = eq(out_womask_518, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_439 = or(_out_T_5223, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_439 = cat(_T_772, _out_prepend_T_439) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5231 = or(out_prepend_439, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5232 = bits(_out_T_5231, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_519 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_519 = orr(_out_rimask_T_519) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_519 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_519 = andr(_out_wimask_T_519) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_519 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_519 = orr(_out_romask_T_519) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_519 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_519 = andr(_out_womask_T_519) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_519 = and(out_rivalid_1[397], out_rimask_519) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_519 = and(out_roready_1[397], out_romask_519) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_519 = and(out_wivalid_1[397], out_wimask_519) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_519 = and(out_woready_1[397], out_womask_519) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5233 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5234 = and(out_f_rivalid_519, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5235 = and(UInt<1>(0h1), out_f_roready_519) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5236 = eq(out_rimask_519, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5237 = eq(out_wimask_519, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5238 = eq(out_romask_519, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5239 = eq(out_womask_519, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_440 = or(_out_T_5232, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_440 = cat(_T_773, _out_prepend_T_440) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5240 = or(out_prepend_440, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5241 = bits(_out_T_5240, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_520 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_520 = orr(_out_rimask_T_520) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_520 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_520 = andr(_out_wimask_T_520) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_520 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_520 = orr(_out_romask_T_520) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_520 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_520 = andr(_out_womask_T_520) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_520 = and(out_rivalid_1[398], out_rimask_520) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_520 = and(out_roready_1[398], out_romask_520) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_520 = and(out_wivalid_1[398], out_wimask_520) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_520 = and(out_woready_1[398], out_womask_520) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5242 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5243 = and(out_f_rivalid_520, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5244 = and(UInt<1>(0h1), out_f_roready_520) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5245 = eq(out_rimask_520, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5246 = eq(out_wimask_520, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5247 = eq(out_romask_520, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5248 = eq(out_womask_520, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_441 = or(_out_T_5241, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_441 = cat(_T_774, _out_prepend_T_441) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5249 = or(out_prepend_441, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5250 = bits(_out_T_5249, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_521 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_521 = orr(_out_rimask_T_521) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_521 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_521 = andr(_out_wimask_T_521) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_521 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_521 = orr(_out_romask_T_521) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_521 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_521 = andr(_out_womask_T_521) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_521 = and(out_rivalid_1[399], out_rimask_521) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_521 = and(out_roready_1[399], out_romask_521) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_521 = and(out_wivalid_1[399], out_wimask_521) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_521 = and(out_woready_1[399], out_womask_521) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5251 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5252 = and(out_f_rivalid_521, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5253 = and(UInt<1>(0h1), out_f_roready_521) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5254 = eq(out_rimask_521, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5255 = eq(out_wimask_521, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5256 = eq(out_romask_521, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5257 = eq(out_womask_521, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_442 = or(_out_T_5250, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_442 = cat(_T_775, _out_prepend_T_442) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5258 = or(out_prepend_442, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5259 = bits(_out_T_5258, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_522 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_522 = orr(_out_rimask_T_522) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_522 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_522 = andr(_out_wimask_T_522) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_522 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_522 = orr(_out_romask_T_522) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_522 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_522 = andr(_out_womask_T_522) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_522 = and(out_rivalid_1[400], out_rimask_522) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_522 = and(out_roready_1[400], out_romask_522) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_522 = and(out_wivalid_1[400], out_wimask_522) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_522 = and(out_woready_1[400], out_womask_522) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5260 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5261 = and(out_f_rivalid_522, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5262 = and(UInt<1>(0h1), out_f_roready_522) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5263 = eq(out_rimask_522, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5264 = eq(out_wimask_522, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5265 = eq(out_romask_522, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5266 = eq(out_womask_522, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_443 = or(_out_T_5259, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_443 = cat(_T_776, _out_prepend_T_443) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5267 = or(out_prepend_443, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5268 = bits(_out_T_5267, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_523 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_523 = orr(_out_rimask_T_523) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_523 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_523 = andr(_out_wimask_T_523) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_523 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_523 = orr(_out_romask_T_523) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_523 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_523 = andr(_out_womask_T_523) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_523 = and(out_rivalid_1[401], out_rimask_523) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_523 = and(out_roready_1[401], out_romask_523) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_523 = and(out_wivalid_1[401], out_wimask_523) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_523 = and(out_woready_1[401], out_womask_523) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5269 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5270 = and(out_f_rivalid_523, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5271 = and(UInt<1>(0h1), out_f_roready_523) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5272 = eq(out_rimask_523, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5273 = eq(out_wimask_523, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5274 = eq(out_romask_523, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5275 = eq(out_womask_523, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_444 = or(_out_T_5268, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_444 = cat(_T_777, _out_prepend_T_444) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5276 = or(out_prepend_444, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5277 = bits(_out_T_5276, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_524 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_524 = orr(_out_rimask_T_524) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_524 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_524 = andr(_out_wimask_T_524) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_524 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_524 = orr(_out_romask_T_524) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_524 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_524 = andr(_out_womask_T_524) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_524 = and(out_rivalid_1[402], out_rimask_524) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_524 = and(out_roready_1[402], out_romask_524) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_524 = and(out_wivalid_1[402], out_wimask_524) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_524 = and(out_woready_1[402], out_womask_524) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5278 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5279 = and(out_f_rivalid_524, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5280 = and(UInt<1>(0h1), out_f_roready_524) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5281 = eq(out_rimask_524, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5282 = eq(out_wimask_524, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5283 = eq(out_romask_524, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5284 = eq(out_womask_524, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5285 = or(_T_546, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5286 = bits(_out_T_5285, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_525 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_525 = orr(_out_rimask_T_525) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_525 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_525 = andr(_out_wimask_T_525) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_525 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_525 = orr(_out_romask_T_525) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_525 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_525 = andr(_out_womask_T_525) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_525 = and(out_rivalid_1[403], out_rimask_525) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_525 = and(out_roready_1[403], out_romask_525) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_525 = and(out_wivalid_1[403], out_wimask_525) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_525 = and(out_woready_1[403], out_womask_525) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5287 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5288 = and(out_f_rivalid_525, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5289 = and(UInt<1>(0h1), out_f_roready_525) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5290 = eq(out_rimask_525, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5291 = eq(out_wimask_525, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5292 = eq(out_romask_525, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5293 = eq(out_womask_525, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_445 = or(_out_T_5286, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_445 = cat(_T_547, _out_prepend_T_445) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5294 = or(out_prepend_445, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5295 = bits(_out_T_5294, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_526 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_526 = orr(_out_rimask_T_526) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_526 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_526 = andr(_out_wimask_T_526) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_526 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_526 = orr(_out_romask_T_526) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_526 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_526 = andr(_out_womask_T_526) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_526 = and(out_rivalid_1[404], out_rimask_526) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_526 = and(out_roready_1[404], out_romask_526) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_526 = and(out_wivalid_1[404], out_wimask_526) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_526 = and(out_woready_1[404], out_womask_526) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5296 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5297 = and(out_f_rivalid_526, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5298 = and(UInt<1>(0h1), out_f_roready_526) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5299 = eq(out_rimask_526, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5300 = eq(out_wimask_526, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5301 = eq(out_romask_526, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5302 = eq(out_womask_526, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_446 = or(_out_T_5295, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_446 = cat(_T_548, _out_prepend_T_446) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5303 = or(out_prepend_446, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5304 = bits(_out_T_5303, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_527 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_527 = orr(_out_rimask_T_527) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_527 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_527 = andr(_out_wimask_T_527) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_527 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_527 = orr(_out_romask_T_527) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_527 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_527 = andr(_out_womask_T_527) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_527 = and(out_rivalid_1[405], out_rimask_527) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_527 = and(out_roready_1[405], out_romask_527) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_527 = and(out_wivalid_1[405], out_wimask_527) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_527 = and(out_woready_1[405], out_womask_527) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5305 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5306 = and(out_f_rivalid_527, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5307 = and(UInt<1>(0h1), out_f_roready_527) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5308 = eq(out_rimask_527, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5309 = eq(out_wimask_527, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5310 = eq(out_romask_527, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5311 = eq(out_womask_527, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_447 = or(_out_T_5304, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_447 = cat(_T_549, _out_prepend_T_447) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5312 = or(out_prepend_447, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5313 = bits(_out_T_5312, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_528 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_528 = orr(_out_rimask_T_528) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_528 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_528 = andr(_out_wimask_T_528) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_528 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_528 = orr(_out_romask_T_528) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_528 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_528 = andr(_out_womask_T_528) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_528 = and(out_rivalid_1[406], out_rimask_528) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_528 = and(out_roready_1[406], out_romask_528) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_528 = and(out_wivalid_1[406], out_wimask_528) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_528 = and(out_woready_1[406], out_womask_528) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5314 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5315 = and(out_f_rivalid_528, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5316 = and(UInt<1>(0h1), out_f_roready_528) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5317 = eq(out_rimask_528, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5318 = eq(out_wimask_528, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5319 = eq(out_romask_528, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5320 = eq(out_womask_528, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_448 = or(_out_T_5313, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_448 = cat(_T_550, _out_prepend_T_448) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5321 = or(out_prepend_448, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5322 = bits(_out_T_5321, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_529 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_529 = orr(_out_rimask_T_529) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_529 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_529 = andr(_out_wimask_T_529) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_529 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_529 = orr(_out_romask_T_529) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_529 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_529 = andr(_out_womask_T_529) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_529 = and(out_rivalid_1[407], out_rimask_529) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_529 = and(out_roready_1[407], out_romask_529) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_529 = and(out_wivalid_1[407], out_wimask_529) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_529 = and(out_woready_1[407], out_womask_529) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5323 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5324 = and(out_f_rivalid_529, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5325 = and(UInt<1>(0h1), out_f_roready_529) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5326 = eq(out_rimask_529, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5327 = eq(out_wimask_529, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5328 = eq(out_romask_529, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5329 = eq(out_womask_529, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_449 = or(_out_T_5322, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_449 = cat(_T_551, _out_prepend_T_449) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5330 = or(out_prepend_449, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5331 = bits(_out_T_5330, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_530 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_530 = orr(_out_rimask_T_530) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_530 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_530 = andr(_out_wimask_T_530) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_530 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_530 = orr(_out_romask_T_530) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_530 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_530 = andr(_out_womask_T_530) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_530 = and(out_rivalid_1[408], out_rimask_530) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_530 = and(out_roready_1[408], out_romask_530) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_530 = and(out_wivalid_1[408], out_wimask_530) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_530 = and(out_woready_1[408], out_womask_530) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5332 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5333 = and(out_f_rivalid_530, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5334 = and(UInt<1>(0h1), out_f_roready_530) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5335 = eq(out_rimask_530, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5336 = eq(out_wimask_530, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5337 = eq(out_romask_530, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5338 = eq(out_womask_530, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_450 = or(_out_T_5331, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_450 = cat(_T_552, _out_prepend_T_450) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5339 = or(out_prepend_450, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5340 = bits(_out_T_5339, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_531 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_531 = orr(_out_rimask_T_531) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_531 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_531 = andr(_out_wimask_T_531) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_531 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_531 = orr(_out_romask_T_531) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_531 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_531 = andr(_out_womask_T_531) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_531 = and(out_rivalid_1[409], out_rimask_531) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_531 = and(out_roready_1[409], out_romask_531) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_531 = and(out_wivalid_1[409], out_wimask_531) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_531 = and(out_woready_1[409], out_womask_531) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5341 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5342 = and(out_f_rivalid_531, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5343 = and(UInt<1>(0h1), out_f_roready_531) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5344 = eq(out_rimask_531, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5345 = eq(out_wimask_531, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5346 = eq(out_romask_531, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5347 = eq(out_womask_531, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_451 = or(_out_T_5340, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_451 = cat(_T_553, _out_prepend_T_451) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5348 = or(out_prepend_451, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5349 = bits(_out_T_5348, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_532 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_532 = orr(_out_rimask_T_532) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_532 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_532 = andr(_out_wimask_T_532) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_532 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_532 = orr(_out_romask_T_532) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_532 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_532 = andr(_out_womask_T_532) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_532 = and(out_rivalid_1[410], out_rimask_532) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_532 = and(out_roready_1[410], out_romask_532) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_532 = and(out_wivalid_1[410], out_wimask_532) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_532 = and(out_woready_1[410], out_womask_532) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5350 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5351 = and(out_f_rivalid_532, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5352 = and(UInt<1>(0h1), out_f_roready_532) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5353 = eq(out_rimask_532, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5354 = eq(out_wimask_532, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5355 = eq(out_romask_532, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5356 = eq(out_womask_532, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5357 = or(_T_1218, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5358 = bits(_out_T_5357, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_533 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_533 = orr(_out_rimask_T_533) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_533 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_533 = andr(_out_wimask_T_533) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_533 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_533 = orr(_out_romask_T_533) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_533 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_533 = andr(_out_womask_T_533) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_533 = and(out_rivalid_1[411], out_rimask_533) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_533 = and(out_roready_1[411], out_romask_533) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_533 = and(out_wivalid_1[411], out_wimask_533) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_533 = and(out_woready_1[411], out_womask_533) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5359 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5360 = and(out_f_rivalid_533, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5361 = and(UInt<1>(0h1), out_f_roready_533) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5362 = eq(out_rimask_533, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5363 = eq(out_wimask_533, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5364 = eq(out_romask_533, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5365 = eq(out_womask_533, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_452 = or(_out_T_5358, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_452 = cat(_T_1219, _out_prepend_T_452) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5366 = or(out_prepend_452, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5367 = bits(_out_T_5366, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_534 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_534 = orr(_out_rimask_T_534) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_534 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_534 = andr(_out_wimask_T_534) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_534 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_534 = orr(_out_romask_T_534) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_534 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_534 = andr(_out_womask_T_534) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_534 = and(out_rivalid_1[412], out_rimask_534) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_534 = and(out_roready_1[412], out_romask_534) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_534 = and(out_wivalid_1[412], out_wimask_534) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_534 = and(out_woready_1[412], out_womask_534) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5368 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5369 = and(out_f_rivalid_534, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5370 = and(UInt<1>(0h1), out_f_roready_534) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5371 = eq(out_rimask_534, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5372 = eq(out_wimask_534, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5373 = eq(out_romask_534, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5374 = eq(out_womask_534, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_453 = or(_out_T_5367, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_453 = cat(_T_1220, _out_prepend_T_453) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5375 = or(out_prepend_453, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5376 = bits(_out_T_5375, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_535 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_535 = orr(_out_rimask_T_535) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_535 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_535 = andr(_out_wimask_T_535) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_535 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_535 = orr(_out_romask_T_535) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_535 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_535 = andr(_out_womask_T_535) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_535 = and(out_rivalid_1[413], out_rimask_535) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_535 = and(out_roready_1[413], out_romask_535) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_535 = and(out_wivalid_1[413], out_wimask_535) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_535 = and(out_woready_1[413], out_womask_535) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5377 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5378 = and(out_f_rivalid_535, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5379 = and(UInt<1>(0h1), out_f_roready_535) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5380 = eq(out_rimask_535, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5381 = eq(out_wimask_535, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5382 = eq(out_romask_535, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5383 = eq(out_womask_535, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_454 = or(_out_T_5376, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_454 = cat(_T_1221, _out_prepend_T_454) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5384 = or(out_prepend_454, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5385 = bits(_out_T_5384, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_536 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_536 = orr(_out_rimask_T_536) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_536 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_536 = andr(_out_wimask_T_536) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_536 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_536 = orr(_out_romask_T_536) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_536 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_536 = andr(_out_womask_T_536) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_536 = and(out_rivalid_1[414], out_rimask_536) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_536 = and(out_roready_1[414], out_romask_536) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_536 = and(out_wivalid_1[414], out_wimask_536) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_536 = and(out_woready_1[414], out_womask_536) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5386 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5387 = and(out_f_rivalid_536, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5388 = and(UInt<1>(0h1), out_f_roready_536) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5389 = eq(out_rimask_536, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5390 = eq(out_wimask_536, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5391 = eq(out_romask_536, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5392 = eq(out_womask_536, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_455 = or(_out_T_5385, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_455 = cat(_T_1222, _out_prepend_T_455) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5393 = or(out_prepend_455, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5394 = bits(_out_T_5393, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_537 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_537 = orr(_out_rimask_T_537) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_537 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_537 = andr(_out_wimask_T_537) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_537 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_537 = orr(_out_romask_T_537) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_537 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_537 = andr(_out_womask_T_537) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_537 = and(out_rivalid_1[415], out_rimask_537) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_537 = and(out_roready_1[415], out_romask_537) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_537 = and(out_wivalid_1[415], out_wimask_537) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_537 = and(out_woready_1[415], out_womask_537) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5395 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5396 = and(out_f_rivalid_537, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5397 = and(UInt<1>(0h1), out_f_roready_537) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5398 = eq(out_rimask_537, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5399 = eq(out_wimask_537, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5400 = eq(out_romask_537, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5401 = eq(out_womask_537, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_456 = or(_out_T_5394, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_456 = cat(_T_1223, _out_prepend_T_456) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5402 = or(out_prepend_456, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5403 = bits(_out_T_5402, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_538 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_538 = orr(_out_rimask_T_538) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_538 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_538 = andr(_out_wimask_T_538) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_538 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_538 = orr(_out_romask_T_538) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_538 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_538 = andr(_out_womask_T_538) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_538 = and(out_rivalid_1[416], out_rimask_538) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_538 = and(out_roready_1[416], out_romask_538) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_538 = and(out_wivalid_1[416], out_wimask_538) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_538 = and(out_woready_1[416], out_womask_538) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5404 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5405 = and(out_f_rivalid_538, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5406 = and(UInt<1>(0h1), out_f_roready_538) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5407 = eq(out_rimask_538, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5408 = eq(out_wimask_538, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5409 = eq(out_romask_538, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5410 = eq(out_womask_538, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_457 = or(_out_T_5403, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_457 = cat(_T_1224, _out_prepend_T_457) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5411 = or(out_prepend_457, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5412 = bits(_out_T_5411, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_539 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_539 = orr(_out_rimask_T_539) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_539 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_539 = andr(_out_wimask_T_539) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_539 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_539 = orr(_out_romask_T_539) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_539 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_539 = andr(_out_womask_T_539) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_539 = and(out_rivalid_1[417], out_rimask_539) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_539 = and(out_roready_1[417], out_romask_539) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_539 = and(out_wivalid_1[417], out_wimask_539) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_539 = and(out_woready_1[417], out_womask_539) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5413 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5414 = and(out_f_rivalid_539, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5415 = and(UInt<1>(0h1), out_f_roready_539) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5416 = eq(out_rimask_539, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5417 = eq(out_wimask_539, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5418 = eq(out_romask_539, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5419 = eq(out_womask_539, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_458 = or(_out_T_5412, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_458 = cat(_T_1225, _out_prepend_T_458) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5420 = or(out_prepend_458, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5421 = bits(_out_T_5420, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_540 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_540 = orr(_out_rimask_T_540) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_540 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_540 = andr(_out_wimask_T_540) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_540 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_540 = orr(_out_romask_T_540) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_540 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_540 = andr(_out_womask_T_540) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_540 = and(out_rivalid_1[418], out_rimask_540) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_540 = and(out_roready_1[418], out_romask_540) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_540 = and(out_wivalid_1[418], out_wimask_540) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_540 = and(out_woready_1[418], out_womask_540) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5422 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5423 = and(out_f_rivalid_540, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5424 = and(UInt<1>(0h1), out_f_roready_540) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5425 = eq(out_rimask_540, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5426 = eq(out_wimask_540, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5427 = eq(out_romask_540, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5428 = eq(out_womask_540, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5429 = or(_T_962, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5430 = bits(_out_T_5429, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_541 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_541 = orr(_out_rimask_T_541) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_541 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_541 = andr(_out_wimask_T_541) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_541 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_541 = orr(_out_romask_T_541) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_541 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_541 = andr(_out_womask_T_541) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_541 = and(out_rivalid_1[419], out_rimask_541) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_541 = and(out_roready_1[419], out_romask_541) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_541 = and(out_wivalid_1[419], out_wimask_541) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_541 = and(out_woready_1[419], out_womask_541) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5431 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5432 = and(out_f_rivalid_541, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5433 = and(UInt<1>(0h1), out_f_roready_541) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5434 = eq(out_rimask_541, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5435 = eq(out_wimask_541, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5436 = eq(out_romask_541, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5437 = eq(out_womask_541, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_459 = or(_out_T_5430, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_459 = cat(_T_963, _out_prepend_T_459) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5438 = or(out_prepend_459, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5439 = bits(_out_T_5438, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_542 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_542 = orr(_out_rimask_T_542) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_542 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_542 = andr(_out_wimask_T_542) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_542 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_542 = orr(_out_romask_T_542) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_542 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_542 = andr(_out_womask_T_542) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_542 = and(out_rivalid_1[420], out_rimask_542) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_542 = and(out_roready_1[420], out_romask_542) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_542 = and(out_wivalid_1[420], out_wimask_542) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_542 = and(out_woready_1[420], out_womask_542) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5440 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5441 = and(out_f_rivalid_542, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5442 = and(UInt<1>(0h1), out_f_roready_542) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5443 = eq(out_rimask_542, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5444 = eq(out_wimask_542, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5445 = eq(out_romask_542, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5446 = eq(out_womask_542, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_460 = or(_out_T_5439, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_460 = cat(_T_964, _out_prepend_T_460) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5447 = or(out_prepend_460, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5448 = bits(_out_T_5447, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_543 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_543 = orr(_out_rimask_T_543) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_543 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_543 = andr(_out_wimask_T_543) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_543 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_543 = orr(_out_romask_T_543) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_543 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_543 = andr(_out_womask_T_543) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_543 = and(out_rivalid_1[421], out_rimask_543) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_543 = and(out_roready_1[421], out_romask_543) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_543 = and(out_wivalid_1[421], out_wimask_543) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_543 = and(out_woready_1[421], out_womask_543) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5449 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5450 = and(out_f_rivalid_543, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5451 = and(UInt<1>(0h1), out_f_roready_543) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5452 = eq(out_rimask_543, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5453 = eq(out_wimask_543, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5454 = eq(out_romask_543, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5455 = eq(out_womask_543, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_461 = or(_out_T_5448, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_461 = cat(_T_965, _out_prepend_T_461) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5456 = or(out_prepend_461, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5457 = bits(_out_T_5456, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_544 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_544 = orr(_out_rimask_T_544) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_544 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_544 = andr(_out_wimask_T_544) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_544 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_544 = orr(_out_romask_T_544) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_544 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_544 = andr(_out_womask_T_544) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_544 = and(out_rivalid_1[422], out_rimask_544) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_544 = and(out_roready_1[422], out_romask_544) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_544 = and(out_wivalid_1[422], out_wimask_544) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_544 = and(out_woready_1[422], out_womask_544) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5458 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5459 = and(out_f_rivalid_544, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5460 = and(UInt<1>(0h1), out_f_roready_544) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5461 = eq(out_rimask_544, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5462 = eq(out_wimask_544, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5463 = eq(out_romask_544, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5464 = eq(out_womask_544, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_462 = or(_out_T_5457, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_462 = cat(_T_966, _out_prepend_T_462) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5465 = or(out_prepend_462, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5466 = bits(_out_T_5465, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_545 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_545 = orr(_out_rimask_T_545) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_545 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_545 = andr(_out_wimask_T_545) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_545 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_545 = orr(_out_romask_T_545) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_545 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_545 = andr(_out_womask_T_545) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_545 = and(out_rivalid_1[423], out_rimask_545) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_545 = and(out_roready_1[423], out_romask_545) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_545 = and(out_wivalid_1[423], out_wimask_545) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_545 = and(out_woready_1[423], out_womask_545) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5467 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5468 = and(out_f_rivalid_545, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5469 = and(UInt<1>(0h1), out_f_roready_545) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5470 = eq(out_rimask_545, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5471 = eq(out_wimask_545, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5472 = eq(out_romask_545, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5473 = eq(out_womask_545, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_463 = or(_out_T_5466, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_463 = cat(_T_967, _out_prepend_T_463) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5474 = or(out_prepend_463, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5475 = bits(_out_T_5474, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_546 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_546 = orr(_out_rimask_T_546) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_546 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_546 = andr(_out_wimask_T_546) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_546 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_546 = orr(_out_romask_T_546) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_546 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_546 = andr(_out_womask_T_546) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_546 = and(out_rivalid_1[424], out_rimask_546) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_546 = and(out_roready_1[424], out_romask_546) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_546 = and(out_wivalid_1[424], out_wimask_546) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_546 = and(out_woready_1[424], out_womask_546) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5476 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5477 = and(out_f_rivalid_546, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5478 = and(UInt<1>(0h1), out_f_roready_546) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5479 = eq(out_rimask_546, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5480 = eq(out_wimask_546, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5481 = eq(out_romask_546, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5482 = eq(out_womask_546, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_464 = or(_out_T_5475, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_464 = cat(_T_968, _out_prepend_T_464) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5483 = or(out_prepend_464, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5484 = bits(_out_T_5483, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_547 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_547 = orr(_out_rimask_T_547) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_547 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_547 = andr(_out_wimask_T_547) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_547 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_547 = orr(_out_romask_T_547) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_547 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_547 = andr(_out_womask_T_547) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_547 = and(out_rivalid_1[425], out_rimask_547) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_547 = and(out_roready_1[425], out_romask_547) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_547 = and(out_wivalid_1[425], out_wimask_547) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_547 = and(out_woready_1[425], out_womask_547) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5485 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5486 = and(out_f_rivalid_547, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5487 = and(UInt<1>(0h1), out_f_roready_547) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5488 = eq(out_rimask_547, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5489 = eq(out_wimask_547, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5490 = eq(out_romask_547, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5491 = eq(out_womask_547, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_465 = or(_out_T_5484, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_465 = cat(_T_969, _out_prepend_T_465) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5492 = or(out_prepend_465, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5493 = bits(_out_T_5492, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_548 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_548 = orr(_out_rimask_T_548) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_548 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_548 = andr(_out_wimask_T_548) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_548 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_548 = orr(_out_romask_T_548) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_548 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_548 = andr(_out_womask_T_548) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_548 = and(out_rivalid_1[426], out_rimask_548) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_548 = and(out_roready_1[426], out_romask_548) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_548 = and(out_wivalid_1[426], out_wimask_548) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_548 = and(out_woready_1[426], out_womask_548) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5494 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5495 = and(out_f_rivalid_548, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5496 = and(UInt<1>(0h1), out_f_roready_548) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5497 = eq(out_rimask_548, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5498 = eq(out_wimask_548, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5499 = eq(out_romask_548, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5500 = eq(out_womask_548, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5501 = or(_T_1114, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5502 = bits(_out_T_5501, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_549 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_549 = orr(_out_rimask_T_549) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_549 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_549 = andr(_out_wimask_T_549) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_549 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_549 = orr(_out_romask_T_549) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_549 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_549 = andr(_out_womask_T_549) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_549 = and(out_rivalid_1[427], out_rimask_549) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_549 = and(out_roready_1[427], out_romask_549) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_549 = and(out_wivalid_1[427], out_wimask_549) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_549 = and(out_woready_1[427], out_womask_549) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5503 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5504 = and(out_f_rivalid_549, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5505 = and(UInt<1>(0h1), out_f_roready_549) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5506 = eq(out_rimask_549, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5507 = eq(out_wimask_549, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5508 = eq(out_romask_549, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5509 = eq(out_womask_549, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_466 = or(_out_T_5502, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_466 = cat(_T_1115, _out_prepend_T_466) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5510 = or(out_prepend_466, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5511 = bits(_out_T_5510, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_550 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_550 = orr(_out_rimask_T_550) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_550 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_550 = andr(_out_wimask_T_550) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_550 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_550 = orr(_out_romask_T_550) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_550 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_550 = andr(_out_womask_T_550) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_550 = and(out_rivalid_1[428], out_rimask_550) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_550 = and(out_roready_1[428], out_romask_550) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_550 = and(out_wivalid_1[428], out_wimask_550) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_550 = and(out_woready_1[428], out_womask_550) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5512 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5513 = and(out_f_rivalid_550, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5514 = and(UInt<1>(0h1), out_f_roready_550) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5515 = eq(out_rimask_550, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5516 = eq(out_wimask_550, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5517 = eq(out_romask_550, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5518 = eq(out_womask_550, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_467 = or(_out_T_5511, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_467 = cat(_T_1116, _out_prepend_T_467) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5519 = or(out_prepend_467, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5520 = bits(_out_T_5519, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_551 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_551 = orr(_out_rimask_T_551) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_551 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_551 = andr(_out_wimask_T_551) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_551 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_551 = orr(_out_romask_T_551) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_551 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_551 = andr(_out_womask_T_551) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_551 = and(out_rivalid_1[429], out_rimask_551) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_551 = and(out_roready_1[429], out_romask_551) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_551 = and(out_wivalid_1[429], out_wimask_551) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_551 = and(out_woready_1[429], out_womask_551) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5521 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5522 = and(out_f_rivalid_551, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5523 = and(UInt<1>(0h1), out_f_roready_551) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5524 = eq(out_rimask_551, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5525 = eq(out_wimask_551, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5526 = eq(out_romask_551, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5527 = eq(out_womask_551, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_468 = or(_out_T_5520, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_468 = cat(_T_1117, _out_prepend_T_468) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5528 = or(out_prepend_468, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5529 = bits(_out_T_5528, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_552 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_552 = orr(_out_rimask_T_552) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_552 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_552 = andr(_out_wimask_T_552) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_552 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_552 = orr(_out_romask_T_552) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_552 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_552 = andr(_out_womask_T_552) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_552 = and(out_rivalid_1[430], out_rimask_552) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_552 = and(out_roready_1[430], out_romask_552) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_552 = and(out_wivalid_1[430], out_wimask_552) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_552 = and(out_woready_1[430], out_womask_552) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5530 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5531 = and(out_f_rivalid_552, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5532 = and(UInt<1>(0h1), out_f_roready_552) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5533 = eq(out_rimask_552, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5534 = eq(out_wimask_552, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5535 = eq(out_romask_552, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5536 = eq(out_womask_552, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_469 = or(_out_T_5529, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_469 = cat(_T_1118, _out_prepend_T_469) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5537 = or(out_prepend_469, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5538 = bits(_out_T_5537, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_553 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_553 = orr(_out_rimask_T_553) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_553 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_553 = andr(_out_wimask_T_553) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_553 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_553 = orr(_out_romask_T_553) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_553 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_553 = andr(_out_womask_T_553) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_553 = and(out_rivalid_1[431], out_rimask_553) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_553 = and(out_roready_1[431], out_romask_553) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_553 = and(out_wivalid_1[431], out_wimask_553) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_553 = and(out_woready_1[431], out_womask_553) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5539 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5540 = and(out_f_rivalid_553, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5541 = and(UInt<1>(0h1), out_f_roready_553) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5542 = eq(out_rimask_553, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5543 = eq(out_wimask_553, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5544 = eq(out_romask_553, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5545 = eq(out_womask_553, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_470 = or(_out_T_5538, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_470 = cat(_T_1119, _out_prepend_T_470) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5546 = or(out_prepend_470, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5547 = bits(_out_T_5546, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_554 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_554 = orr(_out_rimask_T_554) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_554 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_554 = andr(_out_wimask_T_554) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_554 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_554 = orr(_out_romask_T_554) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_554 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_554 = andr(_out_womask_T_554) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_554 = and(out_rivalid_1[432], out_rimask_554) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_554 = and(out_roready_1[432], out_romask_554) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_554 = and(out_wivalid_1[432], out_wimask_554) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_554 = and(out_woready_1[432], out_womask_554) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5548 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5549 = and(out_f_rivalid_554, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5550 = and(UInt<1>(0h1), out_f_roready_554) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5551 = eq(out_rimask_554, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5552 = eq(out_wimask_554, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5553 = eq(out_romask_554, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5554 = eq(out_womask_554, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_471 = or(_out_T_5547, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_471 = cat(_T_1120, _out_prepend_T_471) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5555 = or(out_prepend_471, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5556 = bits(_out_T_5555, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_555 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_555 = orr(_out_rimask_T_555) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_555 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_555 = andr(_out_wimask_T_555) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_555 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_555 = orr(_out_romask_T_555) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_555 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_555 = andr(_out_womask_T_555) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_555 = and(out_rivalid_1[433], out_rimask_555) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_555 = and(out_roready_1[433], out_romask_555) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_555 = and(out_wivalid_1[433], out_wimask_555) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_555 = and(out_woready_1[433], out_womask_555) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5557 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5558 = and(out_f_rivalid_555, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5559 = and(UInt<1>(0h1), out_f_roready_555) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5560 = eq(out_rimask_555, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5561 = eq(out_wimask_555, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5562 = eq(out_romask_555, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5563 = eq(out_womask_555, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_472 = or(_out_T_5556, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_472 = cat(_T_1121, _out_prepend_T_472) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5564 = or(out_prepend_472, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5565 = bits(_out_T_5564, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_556 = bits(out_frontMask_1, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_556 = orr(_out_rimask_T_556) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_556 = bits(out_frontMask_1, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_556 = andr(_out_wimask_T_556) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_556 = bits(out_backMask_1, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_556 = orr(_out_romask_T_556) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_556 = bits(out_backMask_1, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_556 = andr(_out_womask_T_556) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_556 = and(out_rivalid_1[434], out_rimask_556) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_556 = and(out_roready_1[434], out_romask_556) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_556 = and(out_wivalid_1[434], out_wimask_556) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_556 = and(out_woready_1[434], out_womask_556) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5566 = bits(out_front_1.bits.data, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5567 = and(out_f_rivalid_556, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5568 = and(UInt<1>(0h1), out_f_roready_556) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5569 = eq(out_rimask_556, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5570 = eq(out_wimask_556, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5571 = eq(out_romask_556, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5572 = eq(out_womask_556, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5573 = or(_T_441, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5574 = bits(_out_T_5573, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_557 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_557 = orr(_out_rimask_T_557) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_557 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_557 = andr(_out_wimask_T_557) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_557 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_557 = orr(_out_romask_T_557) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_557 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_557 = andr(_out_womask_T_557) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_557 = and(out_rivalid_1[435], out_rimask_557) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_557 = and(out_roready_1[435], out_romask_557) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_557 = and(out_wivalid_1[435], out_wimask_557) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_557 = and(out_woready_1[435], out_womask_557) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5575 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_557 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[40], _out_T_5575 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_5576 = and(out_f_rivalid_557, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5577 = and(UInt<1>(0h1), out_f_roready_557) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5578 = and(out_f_wivalid_557, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5579 = and(UInt<1>(0h1), out_f_woready_557) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5580 = eq(out_rimask_557, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5581 = eq(out_wimask_557, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5582 = eq(out_romask_557, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5583 = eq(out_womask_557, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5584 = or(programBufferMem[40], UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5585 = bits(_out_T_5584, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_558 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_558 = orr(_out_rimask_T_558) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_558 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_558 = andr(_out_wimask_T_558) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_558 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_558 = orr(_out_romask_T_558) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_558 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_558 = andr(_out_womask_T_558) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_558 = and(out_rivalid_1[436], out_rimask_558) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_558 = and(out_roready_1[436], out_romask_558) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_558 = and(out_wivalid_1[436], out_wimask_558) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_558 = and(out_woready_1[436], out_womask_558) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5586 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_558 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[41], _out_T_5586 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_5587 = and(out_f_rivalid_558, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5588 = and(UInt<1>(0h1), out_f_roready_558) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5589 = and(out_f_wivalid_558, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5590 = and(UInt<1>(0h1), out_f_woready_558) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5591 = eq(out_rimask_558, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5592 = eq(out_wimask_558, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5593 = eq(out_romask_558, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5594 = eq(out_womask_558, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_473 = or(_out_T_5585, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_473 = cat(programBufferMem[41], _out_prepend_T_473) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5595 = or(out_prepend_473, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5596 = bits(_out_T_5595, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_559 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_559 = orr(_out_rimask_T_559) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_559 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_559 = andr(_out_wimask_T_559) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_559 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_559 = orr(_out_romask_T_559) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_559 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_559 = andr(_out_womask_T_559) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_559 = and(out_rivalid_1[437], out_rimask_559) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_559 = and(out_roready_1[437], out_romask_559) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_559 = and(out_wivalid_1[437], out_wimask_559) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_559 = and(out_woready_1[437], out_womask_559) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5597 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_559 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[42], _out_T_5597 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_5598 = and(out_f_rivalid_559, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5599 = and(UInt<1>(0h1), out_f_roready_559) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5600 = and(out_f_wivalid_559, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5601 = and(UInt<1>(0h1), out_f_woready_559) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5602 = eq(out_rimask_559, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5603 = eq(out_wimask_559, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5604 = eq(out_romask_559, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5605 = eq(out_womask_559, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_474 = or(_out_T_5596, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_474 = cat(programBufferMem[42], _out_prepend_T_474) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5606 = or(out_prepend_474, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5607 = bits(_out_T_5606, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_560 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_560 = orr(_out_rimask_T_560) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_560 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_560 = andr(_out_wimask_T_560) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_560 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_560 = orr(_out_romask_T_560) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_560 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_560 = andr(_out_womask_T_560) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_560 = and(out_rivalid_1[438], out_rimask_560) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_560 = and(out_roready_1[438], out_romask_560) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_560 = and(out_wivalid_1[438], out_wimask_560) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_560 = and(out_woready_1[438], out_womask_560) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5608 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_560 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[43], _out_T_5608 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_5609 = and(out_f_rivalid_560, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5610 = and(UInt<1>(0h1), out_f_roready_560) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5611 = and(out_f_wivalid_560, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5612 = and(UInt<1>(0h1), out_f_woready_560) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5613 = eq(out_rimask_560, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5614 = eq(out_wimask_560, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5615 = eq(out_romask_560, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5616 = eq(out_womask_560, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_475 = or(_out_T_5607, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_475 = cat(programBufferMem[43], _out_prepend_T_475) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5617 = or(out_prepend_475, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5618 = bits(_out_T_5617, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_561 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_561 = orr(_out_rimask_T_561) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_561 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_561 = andr(_out_wimask_T_561) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_561 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_561 = orr(_out_romask_T_561) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_561 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_561 = andr(_out_womask_T_561) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_561 = and(out_rivalid_1[439], out_rimask_561) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_561 = and(out_roready_1[439], out_romask_561) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_561 = and(out_wivalid_1[439], out_wimask_561) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_561 = and(out_woready_1[439], out_womask_561) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5619 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_561 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[44], _out_T_5619 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_5620 = and(out_f_rivalid_561, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5621 = and(UInt<1>(0h1), out_f_roready_561) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5622 = and(out_f_wivalid_561, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5623 = and(UInt<1>(0h1), out_f_woready_561) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5624 = eq(out_rimask_561, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5625 = eq(out_wimask_561, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5626 = eq(out_romask_561, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5627 = eq(out_womask_561, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_476 = or(_out_T_5618, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_476 = cat(programBufferMem[44], _out_prepend_T_476) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5628 = or(out_prepend_476, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5629 = bits(_out_T_5628, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_562 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_562 = orr(_out_rimask_T_562) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_562 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_562 = andr(_out_wimask_T_562) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_562 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_562 = orr(_out_romask_T_562) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_562 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_562 = andr(_out_womask_T_562) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_562 = and(out_rivalid_1[440], out_rimask_562) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_562 = and(out_roready_1[440], out_romask_562) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_562 = and(out_wivalid_1[440], out_wimask_562) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_562 = and(out_woready_1[440], out_womask_562) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5630 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_562 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[45], _out_T_5630 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_5631 = and(out_f_rivalid_562, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5632 = and(UInt<1>(0h1), out_f_roready_562) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5633 = and(out_f_wivalid_562, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5634 = and(UInt<1>(0h1), out_f_woready_562) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5635 = eq(out_rimask_562, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5636 = eq(out_wimask_562, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5637 = eq(out_romask_562, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5638 = eq(out_womask_562, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_477 = or(_out_T_5629, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_477 = cat(programBufferMem[45], _out_prepend_T_477) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5639 = or(out_prepend_477, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5640 = bits(_out_T_5639, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_563 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_563 = orr(_out_rimask_T_563) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_563 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_563 = andr(_out_wimask_T_563) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_563 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_563 = orr(_out_romask_T_563) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_563 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_563 = andr(_out_womask_T_563) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_563 = and(out_rivalid_1[441], out_rimask_563) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_563 = and(out_roready_1[441], out_romask_563) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_563 = and(out_wivalid_1[441], out_wimask_563) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_563 = and(out_woready_1[441], out_womask_563) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5641 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_563 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[46], _out_T_5641 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_5642 = and(out_f_rivalid_563, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5643 = and(UInt<1>(0h1), out_f_roready_563) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5644 = and(out_f_wivalid_563, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5645 = and(UInt<1>(0h1), out_f_woready_563) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5646 = eq(out_rimask_563, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5647 = eq(out_wimask_563, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5648 = eq(out_romask_563, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5649 = eq(out_womask_563, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_478 = or(_out_T_5640, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_478 = cat(programBufferMem[46], _out_prepend_T_478) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5650 = or(out_prepend_478, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5651 = bits(_out_T_5650, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_564 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_564 = orr(_out_rimask_T_564) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_564 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_564 = andr(_out_wimask_T_564) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_564 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_564 = orr(_out_romask_T_564) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_564 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_564 = andr(_out_womask_T_564) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_564 = and(out_rivalid_1[442], out_rimask_564) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_564 = and(out_roready_1[442], out_romask_564) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_564 = and(out_wivalid_1[442], out_wimask_564) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_564 = and(out_woready_1[442], out_womask_564) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5652 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_564 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[47], _out_T_5652 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_5653 = and(out_f_rivalid_564, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5654 = and(UInt<1>(0h1), out_f_roready_564) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5655 = and(out_f_wivalid_564, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5656 = and(UInt<1>(0h1), out_f_woready_564) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5657 = eq(out_rimask_564, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5658 = eq(out_wimask_564, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5659 = eq(out_romask_564, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5660 = eq(out_womask_564, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_479 = or(_out_T_5651, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_479 = cat(programBufferMem[47], _out_prepend_T_479) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5661 = or(out_prepend_479, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5662 = bits(_out_T_5661, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_565 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_565 = orr(_out_rimask_T_565) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_565 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_565 = andr(_out_wimask_T_565) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_565 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_565 = orr(_out_romask_T_565) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_565 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_565 = andr(_out_womask_T_565) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_565 = and(out_rivalid_1[443], out_rimask_565) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_565 = and(out_roready_1[443], out_romask_565) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_565 = and(out_wivalid_1[443], out_wimask_565) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_565 = and(out_woready_1[443], out_womask_565) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5663 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5664 = and(out_f_rivalid_565, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5665 = and(UInt<1>(0h1), out_f_roready_565) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5666 = eq(out_rimask_565, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5667 = eq(out_wimask_565, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5668 = eq(out_romask_565, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5669 = eq(out_womask_565, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5670 = or(UInt<8>(0h6f), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5671 = bits(_out_T_5670, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_566 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_566 = orr(_out_rimask_T_566) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_566 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_566 = andr(_out_wimask_T_566) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_566 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_566 = orr(_out_romask_T_566) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_566 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_566 = andr(_out_womask_T_566) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_566 = and(out_rivalid_1[444], out_rimask_566) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_566 = and(out_roready_1[444], out_romask_566) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_566 = and(out_wivalid_1[444], out_wimask_566) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_566 = and(out_woready_1[444], out_womask_566) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5672 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5673 = and(out_f_rivalid_566, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5674 = and(UInt<1>(0h1), out_f_roready_566) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5675 = eq(out_rimask_566, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5676 = eq(out_wimask_566, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5677 = eq(out_romask_566, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5678 = eq(out_womask_566, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_480 = or(_out_T_5671, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_480 = cat(UInt<8>(0h0), _out_prepend_T_480) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5679 = or(out_prepend_480, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5680 = bits(_out_T_5679, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_567 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_567 = orr(_out_rimask_T_567) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_567 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_567 = andr(_out_wimask_T_567) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_567 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_567 = orr(_out_romask_T_567) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_567 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_567 = andr(_out_womask_T_567) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_567 = and(out_rivalid_1[445], out_rimask_567) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_567 = and(out_roready_1[445], out_romask_567) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_567 = and(out_wivalid_1[445], out_wimask_567) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_567 = and(out_woready_1[445], out_womask_567) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5681 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5682 = and(out_f_rivalid_567, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5683 = and(UInt<1>(0h1), out_f_roready_567) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5684 = eq(out_rimask_567, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5685 = eq(out_wimask_567, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5686 = eq(out_romask_567, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5687 = eq(out_womask_567, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_481 = or(_out_T_5680, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_481 = cat(UInt<8>(0hc0), _out_prepend_T_481) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5688 = or(out_prepend_481, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5689 = bits(_out_T_5688, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_568 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_568 = orr(_out_rimask_T_568) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_568 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_568 = andr(_out_wimask_T_568) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_568 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_568 = orr(_out_romask_T_568) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_568 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_568 = andr(_out_womask_T_568) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_568 = and(out_rivalid_1[446], out_rimask_568) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_568 = and(out_roready_1[446], out_romask_568) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_568 = and(out_wivalid_1[446], out_wimask_568) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_568 = and(out_woready_1[446], out_womask_568) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5690 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5691 = and(out_f_rivalid_568, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5692 = and(UInt<1>(0h1), out_f_roready_568) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5693 = eq(out_rimask_568, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5694 = eq(out_wimask_568, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5695 = eq(out_romask_568, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5696 = eq(out_womask_568, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_482 = or(_out_T_5689, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_482 = cat(UInt<8>(0h0), _out_prepend_T_482) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5697 = or(out_prepend_482, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5698 = bits(_out_T_5697, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_569 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_569 = orr(_out_rimask_T_569) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_569 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_569 = andr(_out_wimask_T_569) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_569 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_569 = orr(_out_romask_T_569) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_569 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_569 = andr(_out_womask_T_569) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_569 = and(out_rivalid_1[447], out_rimask_569) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_569 = and(out_roready_1[447], out_romask_569) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_569 = and(out_wivalid_1[447], out_wimask_569) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_569 = and(out_woready_1[447], out_womask_569) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5699 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5700 = and(out_f_rivalid_569, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5701 = and(UInt<1>(0h1), out_f_roready_569) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5702 = eq(out_rimask_569, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5703 = eq(out_wimask_569, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5704 = eq(out_romask_569, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5705 = eq(out_womask_569, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_483 = or(_out_T_5698, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_483 = cat(UInt<8>(0h6f), _out_prepend_T_483) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5706 = or(out_prepend_483, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5707 = bits(_out_T_5706, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_570 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_570 = orr(_out_rimask_T_570) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_570 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_570 = andr(_out_wimask_T_570) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_570 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_570 = orr(_out_romask_T_570) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_570 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_570 = andr(_out_womask_T_570) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_570 = and(out_rivalid_1[448], out_rimask_570) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_570 = and(out_roready_1[448], out_romask_570) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_570 = and(out_wivalid_1[448], out_wimask_570) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_570 = and(out_woready_1[448], out_womask_570) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5708 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5709 = and(out_f_rivalid_570, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5710 = and(UInt<1>(0h1), out_f_roready_570) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5711 = eq(out_rimask_570, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5712 = eq(out_wimask_570, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5713 = eq(out_romask_570, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5714 = eq(out_womask_570, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_484 = or(_out_T_5707, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_484 = cat(UInt<8>(0h0), _out_prepend_T_484) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5715 = or(out_prepend_484, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5716 = bits(_out_T_5715, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_571 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_571 = orr(_out_rimask_T_571) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_571 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_571 = andr(_out_wimask_T_571) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_571 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_571 = orr(_out_romask_T_571) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_571 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_571 = andr(_out_womask_T_571) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_571 = and(out_rivalid_1[449], out_rimask_571) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_571 = and(out_roready_1[449], out_romask_571) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_571 = and(out_wivalid_1[449], out_wimask_571) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_571 = and(out_woready_1[449], out_womask_571) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5717 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5718 = and(out_f_rivalid_571, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5719 = and(UInt<1>(0h1), out_f_roready_571) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5720 = eq(out_rimask_571, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5721 = eq(out_wimask_571, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5722 = eq(out_romask_571, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5723 = eq(out_womask_571, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_485 = or(_out_T_5716, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_485 = cat(UInt<8>(0h80), _out_prepend_T_485) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5724 = or(out_prepend_485, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5725 = bits(_out_T_5724, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_572 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_572 = orr(_out_rimask_T_572) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_572 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_572 = andr(_out_wimask_T_572) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_572 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_572 = orr(_out_romask_T_572) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_572 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_572 = andr(_out_womask_T_572) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_572 = and(out_rivalid_1[450], out_rimask_572) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_572 = and(out_roready_1[450], out_romask_572) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_572 = and(out_wivalid_1[450], out_wimask_572) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_572 = and(out_woready_1[450], out_womask_572) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5726 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5727 = and(out_f_rivalid_572, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5728 = and(UInt<1>(0h1), out_f_roready_572) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5729 = eq(out_rimask_572, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5730 = eq(out_wimask_572, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5731 = eq(out_romask_572, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5732 = eq(out_womask_572, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_486 = or(_out_T_5725, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_486 = cat(UInt<8>(0h3), _out_prepend_T_486) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5733 = or(out_prepend_486, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5734 = bits(_out_T_5733, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_573 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_573 = orr(_out_rimask_T_573) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_573 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_573 = andr(_out_wimask_T_573) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_573 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_573 = orr(_out_romask_T_573) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_573 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_573 = andr(_out_womask_T_573) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_573 = and(out_rivalid_1[451], out_rimask_573) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_573 = and(out_roready_1[451], out_romask_573) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_573 = and(out_wivalid_1[451], out_wimask_573) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_573 = and(out_woready_1[451], out_womask_573) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5735 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5736 = and(out_f_rivalid_573, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5737 = and(UInt<1>(0h1), out_f_roready_573) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5738 = eq(out_rimask_573, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5739 = eq(out_wimask_573, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5740 = eq(out_romask_573, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5741 = eq(out_womask_573, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5742 = or(_T_802, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5743 = bits(_out_T_5742, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_574 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_574 = orr(_out_rimask_T_574) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_574 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_574 = andr(_out_wimask_T_574) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_574 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_574 = orr(_out_romask_T_574) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_574 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_574 = andr(_out_womask_T_574) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_574 = and(out_rivalid_1[452], out_rimask_574) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_574 = and(out_roready_1[452], out_romask_574) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_574 = and(out_wivalid_1[452], out_wimask_574) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_574 = and(out_woready_1[452], out_womask_574) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5744 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5745 = and(out_f_rivalid_574, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5746 = and(UInt<1>(0h1), out_f_roready_574) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5747 = eq(out_rimask_574, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5748 = eq(out_wimask_574, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5749 = eq(out_romask_574, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5750 = eq(out_womask_574, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_487 = or(_out_T_5743, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_487 = cat(_T_803, _out_prepend_T_487) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5751 = or(out_prepend_487, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5752 = bits(_out_T_5751, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_575 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_575 = orr(_out_rimask_T_575) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_575 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_575 = andr(_out_wimask_T_575) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_575 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_575 = orr(_out_romask_T_575) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_575 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_575 = andr(_out_womask_T_575) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_575 = and(out_rivalid_1[453], out_rimask_575) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_575 = and(out_roready_1[453], out_romask_575) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_575 = and(out_wivalid_1[453], out_wimask_575) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_575 = and(out_woready_1[453], out_womask_575) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5753 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5754 = and(out_f_rivalid_575, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5755 = and(UInt<1>(0h1), out_f_roready_575) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5756 = eq(out_rimask_575, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5757 = eq(out_wimask_575, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5758 = eq(out_romask_575, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5759 = eq(out_womask_575, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_488 = or(_out_T_5752, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_488 = cat(_T_804, _out_prepend_T_488) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5760 = or(out_prepend_488, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5761 = bits(_out_T_5760, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_576 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_576 = orr(_out_rimask_T_576) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_576 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_576 = andr(_out_wimask_T_576) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_576 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_576 = orr(_out_romask_T_576) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_576 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_576 = andr(_out_womask_T_576) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_576 = and(out_rivalid_1[454], out_rimask_576) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_576 = and(out_roready_1[454], out_romask_576) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_576 = and(out_wivalid_1[454], out_wimask_576) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_576 = and(out_woready_1[454], out_womask_576) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5762 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5763 = and(out_f_rivalid_576, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5764 = and(UInt<1>(0h1), out_f_roready_576) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5765 = eq(out_rimask_576, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5766 = eq(out_wimask_576, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5767 = eq(out_romask_576, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5768 = eq(out_womask_576, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_489 = or(_out_T_5761, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_489 = cat(_T_805, _out_prepend_T_489) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5769 = or(out_prepend_489, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5770 = bits(_out_T_5769, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_577 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_577 = orr(_out_rimask_T_577) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_577 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_577 = andr(_out_wimask_T_577) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_577 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_577 = orr(_out_romask_T_577) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_577 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_577 = andr(_out_womask_T_577) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_577 = and(out_rivalid_1[455], out_rimask_577) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_577 = and(out_roready_1[455], out_romask_577) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_577 = and(out_wivalid_1[455], out_wimask_577) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_577 = and(out_woready_1[455], out_womask_577) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5771 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5772 = and(out_f_rivalid_577, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5773 = and(UInt<1>(0h1), out_f_roready_577) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5774 = eq(out_rimask_577, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5775 = eq(out_wimask_577, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5776 = eq(out_romask_577, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5777 = eq(out_womask_577, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_490 = or(_out_T_5770, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_490 = cat(_T_806, _out_prepend_T_490) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5778 = or(out_prepend_490, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5779 = bits(_out_T_5778, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_578 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_578 = orr(_out_rimask_T_578) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_578 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_578 = andr(_out_wimask_T_578) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_578 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_578 = orr(_out_romask_T_578) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_578 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_578 = andr(_out_womask_T_578) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_578 = and(out_rivalid_1[456], out_rimask_578) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_578 = and(out_roready_1[456], out_romask_578) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_578 = and(out_wivalid_1[456], out_wimask_578) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_578 = and(out_woready_1[456], out_womask_578) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5780 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5781 = and(out_f_rivalid_578, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5782 = and(UInt<1>(0h1), out_f_roready_578) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5783 = eq(out_rimask_578, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5784 = eq(out_wimask_578, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5785 = eq(out_romask_578, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5786 = eq(out_womask_578, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_491 = or(_out_T_5779, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_491 = cat(_T_807, _out_prepend_T_491) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5787 = or(out_prepend_491, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5788 = bits(_out_T_5787, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_579 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_579 = orr(_out_rimask_T_579) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_579 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_579 = andr(_out_wimask_T_579) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_579 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_579 = orr(_out_romask_T_579) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_579 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_579 = andr(_out_womask_T_579) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_579 = and(out_rivalid_1[457], out_rimask_579) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_579 = and(out_roready_1[457], out_romask_579) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_579 = and(out_wivalid_1[457], out_wimask_579) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_579 = and(out_woready_1[457], out_womask_579) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5789 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5790 = and(out_f_rivalid_579, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5791 = and(UInt<1>(0h1), out_f_roready_579) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5792 = eq(out_rimask_579, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5793 = eq(out_wimask_579, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5794 = eq(out_romask_579, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5795 = eq(out_womask_579, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_492 = or(_out_T_5788, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_492 = cat(_T_808, _out_prepend_T_492) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5796 = or(out_prepend_492, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5797 = bits(_out_T_5796, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_580 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_580 = orr(_out_rimask_T_580) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_580 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_580 = andr(_out_wimask_T_580) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_580 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_580 = orr(_out_romask_T_580) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_580 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_580 = andr(_out_womask_T_580) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_580 = and(out_rivalid_1[458], out_rimask_580) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_580 = and(out_roready_1[458], out_romask_580) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_580 = and(out_wivalid_1[458], out_wimask_580) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_580 = and(out_woready_1[458], out_womask_580) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5798 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5799 = and(out_f_rivalid_580, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5800 = and(UInt<1>(0h1), out_f_roready_580) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5801 = eq(out_rimask_580, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5802 = eq(out_wimask_580, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5803 = eq(out_romask_580, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5804 = eq(out_womask_580, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_493 = or(_out_T_5797, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_493 = cat(_T_809, _out_prepend_T_493) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5805 = or(out_prepend_493, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5806 = bits(_out_T_5805, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_581 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_581 = orr(_out_rimask_T_581) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_581 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_581 = andr(_out_wimask_T_581) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_581 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_581 = orr(_out_romask_T_581) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_581 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_581 = andr(_out_womask_T_581) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_581 = and(out_rivalid_1[459], out_rimask_581) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_581 = and(out_roready_1[459], out_romask_581) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_581 = and(out_wivalid_1[459], out_wimask_581) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_581 = and(out_woready_1[459], out_womask_581) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5807 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5808 = and(out_f_rivalid_581, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5809 = and(UInt<1>(0h1), out_f_roready_581) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5810 = eq(out_rimask_581, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5811 = eq(out_wimask_581, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5812 = eq(out_romask_581, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5813 = eq(out_womask_581, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5814 = or(_T_450, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5815 = bits(_out_T_5814, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_582 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_582 = orr(_out_rimask_T_582) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_582 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_582 = andr(_out_wimask_T_582) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_582 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_582 = orr(_out_romask_T_582) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_582 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_582 = andr(_out_womask_T_582) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_582 = and(out_rivalid_1[460], out_rimask_582) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_582 = and(out_roready_1[460], out_romask_582) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_582 = and(out_wivalid_1[460], out_wimask_582) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_582 = and(out_woready_1[460], out_womask_582) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5816 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5817 = and(out_f_rivalid_582, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5818 = and(UInt<1>(0h1), out_f_roready_582) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5819 = eq(out_rimask_582, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5820 = eq(out_wimask_582, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5821 = eq(out_romask_582, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5822 = eq(out_womask_582, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_494 = or(_out_T_5815, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_494 = cat(_T_451, _out_prepend_T_494) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5823 = or(out_prepend_494, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5824 = bits(_out_T_5823, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_583 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_583 = orr(_out_rimask_T_583) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_583 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_583 = andr(_out_wimask_T_583) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_583 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_583 = orr(_out_romask_T_583) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_583 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_583 = andr(_out_womask_T_583) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_583 = and(out_rivalid_1[461], out_rimask_583) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_583 = and(out_roready_1[461], out_romask_583) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_583 = and(out_wivalid_1[461], out_wimask_583) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_583 = and(out_woready_1[461], out_womask_583) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5825 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5826 = and(out_f_rivalid_583, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5827 = and(UInt<1>(0h1), out_f_roready_583) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5828 = eq(out_rimask_583, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5829 = eq(out_wimask_583, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5830 = eq(out_romask_583, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5831 = eq(out_womask_583, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_495 = or(_out_T_5824, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_495 = cat(_T_452, _out_prepend_T_495) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5832 = or(out_prepend_495, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5833 = bits(_out_T_5832, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_584 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_584 = orr(_out_rimask_T_584) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_584 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_584 = andr(_out_wimask_T_584) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_584 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_584 = orr(_out_romask_T_584) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_584 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_584 = andr(_out_womask_T_584) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_584 = and(out_rivalid_1[462], out_rimask_584) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_584 = and(out_roready_1[462], out_romask_584) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_584 = and(out_wivalid_1[462], out_wimask_584) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_584 = and(out_woready_1[462], out_womask_584) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5834 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5835 = and(out_f_rivalid_584, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5836 = and(UInt<1>(0h1), out_f_roready_584) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5837 = eq(out_rimask_584, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5838 = eq(out_wimask_584, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5839 = eq(out_romask_584, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5840 = eq(out_womask_584, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_496 = or(_out_T_5833, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_496 = cat(_T_453, _out_prepend_T_496) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5841 = or(out_prepend_496, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5842 = bits(_out_T_5841, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_585 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_585 = orr(_out_rimask_T_585) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_585 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_585 = andr(_out_wimask_T_585) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_585 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_585 = orr(_out_romask_T_585) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_585 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_585 = andr(_out_womask_T_585) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_585 = and(out_rivalid_1[463], out_rimask_585) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_585 = and(out_roready_1[463], out_romask_585) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_585 = and(out_wivalid_1[463], out_wimask_585) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_585 = and(out_woready_1[463], out_womask_585) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5843 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5844 = and(out_f_rivalid_585, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5845 = and(UInt<1>(0h1), out_f_roready_585) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5846 = eq(out_rimask_585, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5847 = eq(out_wimask_585, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5848 = eq(out_romask_585, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5849 = eq(out_womask_585, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_497 = or(_out_T_5842, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_497 = cat(_T_454, _out_prepend_T_497) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5850 = or(out_prepend_497, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5851 = bits(_out_T_5850, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_586 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_586 = orr(_out_rimask_T_586) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_586 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_586 = andr(_out_wimask_T_586) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_586 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_586 = orr(_out_romask_T_586) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_586 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_586 = andr(_out_womask_T_586) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_586 = and(out_rivalid_1[464], out_rimask_586) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_586 = and(out_roready_1[464], out_romask_586) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_586 = and(out_wivalid_1[464], out_wimask_586) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_586 = and(out_woready_1[464], out_womask_586) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5852 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5853 = and(out_f_rivalid_586, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5854 = and(UInt<1>(0h1), out_f_roready_586) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5855 = eq(out_rimask_586, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5856 = eq(out_wimask_586, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5857 = eq(out_romask_586, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5858 = eq(out_womask_586, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_498 = or(_out_T_5851, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_498 = cat(_T_455, _out_prepend_T_498) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5859 = or(out_prepend_498, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5860 = bits(_out_T_5859, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_587 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_587 = orr(_out_rimask_T_587) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_587 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_587 = andr(_out_wimask_T_587) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_587 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_587 = orr(_out_romask_T_587) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_587 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_587 = andr(_out_womask_T_587) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_587 = and(out_rivalid_1[465], out_rimask_587) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_587 = and(out_roready_1[465], out_romask_587) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_587 = and(out_wivalid_1[465], out_wimask_587) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_587 = and(out_woready_1[465], out_womask_587) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5861 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5862 = and(out_f_rivalid_587, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5863 = and(UInt<1>(0h1), out_f_roready_587) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5864 = eq(out_rimask_587, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5865 = eq(out_wimask_587, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5866 = eq(out_romask_587, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5867 = eq(out_womask_587, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_499 = or(_out_T_5860, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_499 = cat(_T_456, _out_prepend_T_499) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5868 = or(out_prepend_499, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5869 = bits(_out_T_5868, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_588 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_588 = orr(_out_rimask_T_588) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_588 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_588 = andr(_out_wimask_T_588) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_588 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_588 = orr(_out_romask_T_588) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_588 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_588 = andr(_out_womask_T_588) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_588 = and(out_rivalid_1[466], out_rimask_588) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_588 = and(out_roready_1[466], out_romask_588) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_588 = and(out_wivalid_1[466], out_wimask_588) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_588 = and(out_woready_1[466], out_womask_588) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5870 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5871 = and(out_f_rivalid_588, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5872 = and(UInt<1>(0h1), out_f_roready_588) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5873 = eq(out_rimask_588, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5874 = eq(out_wimask_588, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5875 = eq(out_romask_588, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5876 = eq(out_womask_588, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_500 = or(_out_T_5869, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_500 = cat(_T_457, _out_prepend_T_500) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5877 = or(out_prepend_500, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5878 = bits(_out_T_5877, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_589 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_589 = orr(_out_rimask_T_589) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_589 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_589 = andr(_out_wimask_T_589) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_589 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_589 = orr(_out_romask_T_589) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_589 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_589 = andr(_out_womask_T_589) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_589 = and(out_rivalid_1[467], out_rimask_589) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_589 = and(out_roready_1[467], out_romask_589) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_589 = and(out_wivalid_1[467], out_wimask_589) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_589 = and(out_woready_1[467], out_womask_589) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5879 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5880 = and(out_f_rivalid_589, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5881 = and(UInt<1>(0h1), out_f_roready_589) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5882 = eq(out_rimask_589, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5883 = eq(out_wimask_589, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5884 = eq(out_romask_589, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5885 = eq(out_womask_589, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5886 = or(_T_490, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5887 = bits(_out_T_5886, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_590 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_590 = orr(_out_rimask_T_590) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_590 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_590 = andr(_out_wimask_T_590) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_590 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_590 = orr(_out_romask_T_590) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_590 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_590 = andr(_out_womask_T_590) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_590 = and(out_rivalid_1[468], out_rimask_590) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_590 = and(out_roready_1[468], out_romask_590) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_590 = and(out_wivalid_1[468], out_wimask_590) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_590 = and(out_woready_1[468], out_womask_590) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5888 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5889 = and(out_f_rivalid_590, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5890 = and(UInt<1>(0h1), out_f_roready_590) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5891 = eq(out_rimask_590, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5892 = eq(out_wimask_590, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5893 = eq(out_romask_590, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5894 = eq(out_womask_590, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_501 = or(_out_T_5887, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_501 = cat(_T_491, _out_prepend_T_501) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5895 = or(out_prepend_501, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5896 = bits(_out_T_5895, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_591 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_591 = orr(_out_rimask_T_591) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_591 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_591 = andr(_out_wimask_T_591) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_591 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_591 = orr(_out_romask_T_591) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_591 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_591 = andr(_out_womask_T_591) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_591 = and(out_rivalid_1[469], out_rimask_591) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_591 = and(out_roready_1[469], out_romask_591) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_591 = and(out_wivalid_1[469], out_wimask_591) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_591 = and(out_woready_1[469], out_womask_591) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5897 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5898 = and(out_f_rivalid_591, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5899 = and(UInt<1>(0h1), out_f_roready_591) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5900 = eq(out_rimask_591, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5901 = eq(out_wimask_591, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5902 = eq(out_romask_591, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5903 = eq(out_womask_591, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_502 = or(_out_T_5896, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_502 = cat(_T_492, _out_prepend_T_502) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5904 = or(out_prepend_502, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5905 = bits(_out_T_5904, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_592 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_592 = orr(_out_rimask_T_592) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_592 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_592 = andr(_out_wimask_T_592) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_592 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_592 = orr(_out_romask_T_592) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_592 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_592 = andr(_out_womask_T_592) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_592 = and(out_rivalid_1[470], out_rimask_592) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_592 = and(out_roready_1[470], out_romask_592) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_592 = and(out_wivalid_1[470], out_wimask_592) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_592 = and(out_woready_1[470], out_womask_592) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5906 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5907 = and(out_f_rivalid_592, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5908 = and(UInt<1>(0h1), out_f_roready_592) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5909 = eq(out_rimask_592, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5910 = eq(out_wimask_592, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5911 = eq(out_romask_592, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5912 = eq(out_womask_592, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_503 = or(_out_T_5905, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_503 = cat(_T_493, _out_prepend_T_503) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5913 = or(out_prepend_503, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5914 = bits(_out_T_5913, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_593 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_593 = orr(_out_rimask_T_593) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_593 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_593 = andr(_out_wimask_T_593) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_593 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_593 = orr(_out_romask_T_593) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_593 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_593 = andr(_out_womask_T_593) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_593 = and(out_rivalid_1[471], out_rimask_593) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_593 = and(out_roready_1[471], out_romask_593) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_593 = and(out_wivalid_1[471], out_wimask_593) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_593 = and(out_woready_1[471], out_womask_593) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5915 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5916 = and(out_f_rivalid_593, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5917 = and(UInt<1>(0h1), out_f_roready_593) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5918 = eq(out_rimask_593, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5919 = eq(out_wimask_593, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5920 = eq(out_romask_593, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5921 = eq(out_womask_593, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_504 = or(_out_T_5914, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_504 = cat(_T_494, _out_prepend_T_504) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5922 = or(out_prepend_504, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5923 = bits(_out_T_5922, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_594 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_594 = orr(_out_rimask_T_594) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_594 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_594 = andr(_out_wimask_T_594) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_594 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_594 = orr(_out_romask_T_594) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_594 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_594 = andr(_out_womask_T_594) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_594 = and(out_rivalid_1[472], out_rimask_594) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_594 = and(out_roready_1[472], out_romask_594) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_594 = and(out_wivalid_1[472], out_wimask_594) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_594 = and(out_woready_1[472], out_womask_594) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5924 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5925 = and(out_f_rivalid_594, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5926 = and(UInt<1>(0h1), out_f_roready_594) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5927 = eq(out_rimask_594, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5928 = eq(out_wimask_594, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5929 = eq(out_romask_594, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5930 = eq(out_womask_594, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_505 = or(_out_T_5923, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_505 = cat(_T_495, _out_prepend_T_505) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5931 = or(out_prepend_505, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5932 = bits(_out_T_5931, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_595 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_595 = orr(_out_rimask_T_595) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_595 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_595 = andr(_out_wimask_T_595) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_595 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_595 = orr(_out_romask_T_595) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_595 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_595 = andr(_out_womask_T_595) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_595 = and(out_rivalid_1[473], out_rimask_595) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_595 = and(out_roready_1[473], out_romask_595) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_595 = and(out_wivalid_1[473], out_wimask_595) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_595 = and(out_woready_1[473], out_womask_595) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5933 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5934 = and(out_f_rivalid_595, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5935 = and(UInt<1>(0h1), out_f_roready_595) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5936 = eq(out_rimask_595, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5937 = eq(out_wimask_595, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5938 = eq(out_romask_595, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5939 = eq(out_womask_595, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_506 = or(_out_T_5932, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_506 = cat(_T_496, _out_prepend_T_506) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5940 = or(out_prepend_506, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5941 = bits(_out_T_5940, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_596 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_596 = orr(_out_rimask_T_596) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_596 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_596 = andr(_out_wimask_T_596) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_596 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_596 = orr(_out_romask_T_596) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_596 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_596 = andr(_out_womask_T_596) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_596 = and(out_rivalid_1[474], out_rimask_596) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_596 = and(out_roready_1[474], out_romask_596) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_596 = and(out_wivalid_1[474], out_wimask_596) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_596 = and(out_woready_1[474], out_womask_596) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5942 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5943 = and(out_f_rivalid_596, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5944 = and(UInt<1>(0h1), out_f_roready_596) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5945 = eq(out_rimask_596, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5946 = eq(out_wimask_596, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5947 = eq(out_romask_596, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5948 = eq(out_womask_596, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_507 = or(_out_T_5941, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_507 = cat(_T_497, _out_prepend_T_507) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5949 = or(out_prepend_507, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5950 = bits(_out_T_5949, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_597 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_597 = orr(_out_rimask_T_597) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_597 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_597 = andr(_out_wimask_T_597) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_597 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_597 = orr(_out_romask_T_597) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_597 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_597 = andr(_out_womask_T_597) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_597 = and(out_rivalid_1[475], out_rimask_597) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_597 = and(out_roready_1[475], out_romask_597) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_597 = and(out_wivalid_1[475], out_wimask_597) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_597 = and(out_woready_1[475], out_womask_597) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5951 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5952 = and(out_f_rivalid_597, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5953 = and(UInt<1>(0h1), out_f_roready_597) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5954 = eq(out_rimask_597, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5955 = eq(out_wimask_597, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5956 = eq(out_romask_597, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5957 = eq(out_womask_597, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5958 = or(UInt<8>(0h73), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5959 = bits(_out_T_5958, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_598 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_598 = orr(_out_rimask_T_598) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_598 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_598 = andr(_out_wimask_T_598) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_598 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_598 = orr(_out_romask_T_598) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_598 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_598 = andr(_out_womask_T_598) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_598 = and(out_rivalid_1[476], out_rimask_598) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_598 = and(out_roready_1[476], out_romask_598) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_598 = and(out_wivalid_1[476], out_wimask_598) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_598 = and(out_woready_1[476], out_womask_598) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5960 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5961 = and(out_f_rivalid_598, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5962 = and(UInt<1>(0h1), out_f_roready_598) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5963 = eq(out_rimask_598, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5964 = eq(out_wimask_598, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5965 = eq(out_romask_598, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5966 = eq(out_womask_598, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_508 = or(_out_T_5959, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_508 = cat(UInt<8>(0h0), _out_prepend_T_508) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5967 = or(out_prepend_508, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5968 = bits(_out_T_5967, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_599 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_599 = orr(_out_rimask_T_599) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_599 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_599 = andr(_out_wimask_T_599) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_599 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_599 = orr(_out_romask_T_599) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_599 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_599 = andr(_out_womask_T_599) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_599 = and(out_rivalid_1[477], out_rimask_599) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_599 = and(out_roready_1[477], out_romask_599) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_599 = and(out_wivalid_1[477], out_wimask_599) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_599 = and(out_woready_1[477], out_womask_599) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5969 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5970 = and(out_f_rivalid_599, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5971 = and(UInt<1>(0h1), out_f_roready_599) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5972 = eq(out_rimask_599, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5973 = eq(out_wimask_599, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5974 = eq(out_romask_599, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5975 = eq(out_womask_599, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_509 = or(_out_T_5968, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_509 = cat(UInt<8>(0h10), _out_prepend_T_509) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5976 = or(out_prepend_509, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5977 = bits(_out_T_5976, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_600 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_600 = orr(_out_rimask_T_600) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_600 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_600 = andr(_out_wimask_T_600) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_600 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_600 = orr(_out_romask_T_600) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_600 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_600 = andr(_out_womask_T_600) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_600 = and(out_rivalid_1[478], out_rimask_600) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_600 = and(out_roready_1[478], out_romask_600) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_600 = and(out_wivalid_1[478], out_wimask_600) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_600 = and(out_woready_1[478], out_womask_600) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5978 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5979 = and(out_f_rivalid_600, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5980 = and(UInt<1>(0h1), out_f_roready_600) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5981 = eq(out_rimask_600, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5982 = eq(out_wimask_600, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5983 = eq(out_romask_600, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5984 = eq(out_womask_600, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_510 = or(_out_T_5977, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_510 = cat(UInt<8>(0h0), _out_prepend_T_510) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5985 = or(out_prepend_510, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5986 = bits(_out_T_5985, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_601 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_601 = orr(_out_rimask_T_601) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_601 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_601 = andr(_out_wimask_T_601) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_601 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_601 = orr(_out_romask_T_601) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_601 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_601 = andr(_out_womask_T_601) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_601 = and(out_rivalid_1[479], out_rimask_601) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_601 = and(out_roready_1[479], out_romask_601) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_601 = and(out_wivalid_1[479], out_wimask_601) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_601 = and(out_woready_1[479], out_womask_601) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5987 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5988 = and(out_f_rivalid_601, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5989 = and(UInt<1>(0h1), out_f_roready_601) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5990 = eq(out_rimask_601, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5991 = eq(out_wimask_601, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5992 = eq(out_romask_601, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5993 = eq(out_womask_601, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5994 = or(_T_1058, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5995 = bits(_out_T_5994, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_602 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_602 = orr(_out_rimask_T_602) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_602 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_602 = andr(_out_wimask_T_602) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_602 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_602 = orr(_out_romask_T_602) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_602 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_602 = andr(_out_womask_T_602) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_602 = and(out_rivalid_1[480], out_rimask_602) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_602 = and(out_roready_1[480], out_romask_602) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_602 = and(out_wivalid_1[480], out_wimask_602) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_602 = and(out_woready_1[480], out_womask_602) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5996 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5997 = and(out_f_rivalid_602, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5998 = and(UInt<1>(0h1), out_f_roready_602) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5999 = eq(out_rimask_602, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6000 = eq(out_wimask_602, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6001 = eq(out_romask_602, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6002 = eq(out_womask_602, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_511 = or(_out_T_5995, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_511 = cat(_T_1059, _out_prepend_T_511) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6003 = or(out_prepend_511, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6004 = bits(_out_T_6003, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_603 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_603 = orr(_out_rimask_T_603) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_603 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_603 = andr(_out_wimask_T_603) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_603 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_603 = orr(_out_romask_T_603) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_603 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_603 = andr(_out_womask_T_603) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_603 = and(out_rivalid_1[481], out_rimask_603) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_603 = and(out_roready_1[481], out_romask_603) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_603 = and(out_wivalid_1[481], out_wimask_603) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_603 = and(out_woready_1[481], out_womask_603) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6005 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6006 = and(out_f_rivalid_603, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6007 = and(UInt<1>(0h1), out_f_roready_603) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6008 = eq(out_rimask_603, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6009 = eq(out_wimask_603, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6010 = eq(out_romask_603, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6011 = eq(out_womask_603, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_512 = or(_out_T_6004, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_512 = cat(_T_1060, _out_prepend_T_512) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6012 = or(out_prepend_512, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6013 = bits(_out_T_6012, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_604 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_604 = orr(_out_rimask_T_604) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_604 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_604 = andr(_out_wimask_T_604) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_604 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_604 = orr(_out_romask_T_604) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_604 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_604 = andr(_out_womask_T_604) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_604 = and(out_rivalid_1[482], out_rimask_604) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_604 = and(out_roready_1[482], out_romask_604) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_604 = and(out_wivalid_1[482], out_wimask_604) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_604 = and(out_woready_1[482], out_womask_604) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6014 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6015 = and(out_f_rivalid_604, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6016 = and(UInt<1>(0h1), out_f_roready_604) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6017 = eq(out_rimask_604, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6018 = eq(out_wimask_604, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6019 = eq(out_romask_604, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6020 = eq(out_womask_604, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_513 = or(_out_T_6013, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_513 = cat(_T_1061, _out_prepend_T_513) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6021 = or(out_prepend_513, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6022 = bits(_out_T_6021, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_605 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_605 = orr(_out_rimask_T_605) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_605 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_605 = andr(_out_wimask_T_605) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_605 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_605 = orr(_out_romask_T_605) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_605 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_605 = andr(_out_womask_T_605) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_605 = and(out_rivalid_1[483], out_rimask_605) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_605 = and(out_roready_1[483], out_romask_605) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_605 = and(out_wivalid_1[483], out_wimask_605) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_605 = and(out_woready_1[483], out_womask_605) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6023 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6024 = and(out_f_rivalid_605, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6025 = and(UInt<1>(0h1), out_f_roready_605) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6026 = eq(out_rimask_605, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6027 = eq(out_wimask_605, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6028 = eq(out_romask_605, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6029 = eq(out_womask_605, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_514 = or(_out_T_6022, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_514 = cat(_T_1062, _out_prepend_T_514) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6030 = or(out_prepend_514, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6031 = bits(_out_T_6030, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_606 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_606 = orr(_out_rimask_T_606) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_606 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_606 = andr(_out_wimask_T_606) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_606 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_606 = orr(_out_romask_T_606) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_606 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_606 = andr(_out_womask_T_606) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_606 = and(out_rivalid_1[484], out_rimask_606) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_606 = and(out_roready_1[484], out_romask_606) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_606 = and(out_wivalid_1[484], out_wimask_606) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_606 = and(out_woready_1[484], out_womask_606) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6032 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6033 = and(out_f_rivalid_606, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6034 = and(UInt<1>(0h1), out_f_roready_606) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6035 = eq(out_rimask_606, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6036 = eq(out_wimask_606, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6037 = eq(out_romask_606, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6038 = eq(out_womask_606, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_515 = or(_out_T_6031, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_515 = cat(_T_1063, _out_prepend_T_515) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6039 = or(out_prepend_515, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6040 = bits(_out_T_6039, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_607 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_607 = orr(_out_rimask_T_607) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_607 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_607 = andr(_out_wimask_T_607) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_607 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_607 = orr(_out_romask_T_607) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_607 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_607 = andr(_out_womask_T_607) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_607 = and(out_rivalid_1[485], out_rimask_607) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_607 = and(out_roready_1[485], out_romask_607) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_607 = and(out_wivalid_1[485], out_wimask_607) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_607 = and(out_woready_1[485], out_womask_607) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6041 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6042 = and(out_f_rivalid_607, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6043 = and(UInt<1>(0h1), out_f_roready_607) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6044 = eq(out_rimask_607, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6045 = eq(out_wimask_607, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6046 = eq(out_romask_607, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6047 = eq(out_womask_607, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_516 = or(_out_T_6040, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_516 = cat(_T_1064, _out_prepend_T_516) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6048 = or(out_prepend_516, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6049 = bits(_out_T_6048, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_608 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_608 = orr(_out_rimask_T_608) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_608 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_608 = andr(_out_wimask_T_608) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_608 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_608 = orr(_out_romask_T_608) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_608 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_608 = andr(_out_womask_T_608) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_608 = and(out_rivalid_1[486], out_rimask_608) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_608 = and(out_roready_1[486], out_romask_608) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_608 = and(out_wivalid_1[486], out_wimask_608) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_608 = and(out_woready_1[486], out_womask_608) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6050 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6051 = and(out_f_rivalid_608, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6052 = and(UInt<1>(0h1), out_f_roready_608) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6053 = eq(out_rimask_608, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6054 = eq(out_wimask_608, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6055 = eq(out_romask_608, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6056 = eq(out_womask_608, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_517 = or(_out_T_6049, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_517 = cat(_T_1065, _out_prepend_T_517) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6057 = or(out_prepend_517, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6058 = bits(_out_T_6057, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_609 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_609 = orr(_out_rimask_T_609) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_609 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_609 = andr(_out_wimask_T_609) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_609 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_609 = orr(_out_romask_T_609) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_609 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_609 = andr(_out_womask_T_609) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_609 = and(out_rivalid_1[487], out_rimask_609) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_609 = and(out_roready_1[487], out_romask_609) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_609 = and(out_wivalid_1[487], out_wimask_609) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_609 = and(out_woready_1[487], out_womask_609) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6059 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6060 = and(out_f_rivalid_609, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6061 = and(UInt<1>(0h1), out_f_roready_609) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6062 = eq(out_rimask_609, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6063 = eq(out_wimask_609, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6064 = eq(out_romask_609, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6065 = eq(out_womask_609, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6066 = or(_T_442, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6067 = bits(_out_T_6066, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_610 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_610 = orr(_out_rimask_T_610) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_610 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_610 = andr(_out_wimask_T_610) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_610 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_610 = orr(_out_romask_T_610) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_610 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_610 = andr(_out_womask_T_610) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_610 = and(out_rivalid_1[488], out_rimask_610) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_610 = and(out_roready_1[488], out_romask_610) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_610 = and(out_wivalid_1[488], out_wimask_610) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_610 = and(out_woready_1[488], out_womask_610) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6068 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6069 = and(out_f_rivalid_610, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6070 = and(UInt<1>(0h1), out_f_roready_610) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6071 = eq(out_rimask_610, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6072 = eq(out_wimask_610, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6073 = eq(out_romask_610, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6074 = eq(out_womask_610, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_518 = or(_out_T_6067, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_518 = cat(_T_443, _out_prepend_T_518) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6075 = or(out_prepend_518, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6076 = bits(_out_T_6075, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_611 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_611 = orr(_out_rimask_T_611) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_611 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_611 = andr(_out_wimask_T_611) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_611 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_611 = orr(_out_romask_T_611) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_611 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_611 = andr(_out_womask_T_611) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_611 = and(out_rivalid_1[489], out_rimask_611) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_611 = and(out_roready_1[489], out_romask_611) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_611 = and(out_wivalid_1[489], out_wimask_611) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_611 = and(out_woready_1[489], out_womask_611) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6077 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6078 = and(out_f_rivalid_611, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6079 = and(UInt<1>(0h1), out_f_roready_611) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6080 = eq(out_rimask_611, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6081 = eq(out_wimask_611, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6082 = eq(out_romask_611, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6083 = eq(out_womask_611, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_519 = or(_out_T_6076, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_519 = cat(_T_444, _out_prepend_T_519) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6084 = or(out_prepend_519, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6085 = bits(_out_T_6084, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_612 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_612 = orr(_out_rimask_T_612) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_612 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_612 = andr(_out_wimask_T_612) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_612 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_612 = orr(_out_romask_T_612) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_612 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_612 = andr(_out_womask_T_612) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_612 = and(out_rivalid_1[490], out_rimask_612) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_612 = and(out_roready_1[490], out_romask_612) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_612 = and(out_wivalid_1[490], out_wimask_612) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_612 = and(out_woready_1[490], out_womask_612) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6086 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6087 = and(out_f_rivalid_612, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6088 = and(UInt<1>(0h1), out_f_roready_612) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6089 = eq(out_rimask_612, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6090 = eq(out_wimask_612, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6091 = eq(out_romask_612, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6092 = eq(out_womask_612, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_520 = or(_out_T_6085, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_520 = cat(_T_445, _out_prepend_T_520) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6093 = or(out_prepend_520, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6094 = bits(_out_T_6093, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_613 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_613 = orr(_out_rimask_T_613) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_613 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_613 = andr(_out_wimask_T_613) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_613 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_613 = orr(_out_romask_T_613) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_613 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_613 = andr(_out_womask_T_613) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_613 = and(out_rivalid_1[491], out_rimask_613) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_613 = and(out_roready_1[491], out_romask_613) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_613 = and(out_wivalid_1[491], out_wimask_613) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_613 = and(out_woready_1[491], out_womask_613) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6095 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6096 = and(out_f_rivalid_613, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6097 = and(UInt<1>(0h1), out_f_roready_613) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6098 = eq(out_rimask_613, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6099 = eq(out_wimask_613, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6100 = eq(out_romask_613, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6101 = eq(out_womask_613, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_521 = or(_out_T_6094, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_521 = cat(_T_446, _out_prepend_T_521) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6102 = or(out_prepend_521, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6103 = bits(_out_T_6102, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_614 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_614 = orr(_out_rimask_T_614) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_614 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_614 = andr(_out_wimask_T_614) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_614 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_614 = orr(_out_romask_T_614) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_614 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_614 = andr(_out_womask_T_614) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_614 = and(out_rivalid_1[492], out_rimask_614) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_614 = and(out_roready_1[492], out_romask_614) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_614 = and(out_wivalid_1[492], out_wimask_614) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_614 = and(out_woready_1[492], out_womask_614) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6104 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6105 = and(out_f_rivalid_614, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6106 = and(UInt<1>(0h1), out_f_roready_614) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6107 = eq(out_rimask_614, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6108 = eq(out_wimask_614, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6109 = eq(out_romask_614, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6110 = eq(out_womask_614, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_522 = or(_out_T_6103, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_522 = cat(_T_447, _out_prepend_T_522) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6111 = or(out_prepend_522, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6112 = bits(_out_T_6111, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_615 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_615 = orr(_out_rimask_T_615) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_615 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_615 = andr(_out_wimask_T_615) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_615 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_615 = orr(_out_romask_T_615) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_615 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_615 = andr(_out_womask_T_615) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_615 = and(out_rivalid_1[493], out_rimask_615) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_615 = and(out_roready_1[493], out_romask_615) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_615 = and(out_wivalid_1[493], out_wimask_615) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_615 = and(out_woready_1[493], out_womask_615) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6113 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6114 = and(out_f_rivalid_615, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6115 = and(UInt<1>(0h1), out_f_roready_615) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6116 = eq(out_rimask_615, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6117 = eq(out_wimask_615, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6118 = eq(out_romask_615, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6119 = eq(out_womask_615, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_523 = or(_out_T_6112, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_523 = cat(_T_448, _out_prepend_T_523) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6120 = or(out_prepend_523, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6121 = bits(_out_T_6120, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_616 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_616 = orr(_out_rimask_T_616) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_616 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_616 = andr(_out_wimask_T_616) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_616 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_616 = orr(_out_romask_T_616) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_616 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_616 = andr(_out_womask_T_616) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_616 = and(out_rivalid_1[494], out_rimask_616) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_616 = and(out_roready_1[494], out_romask_616) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_616 = and(out_wivalid_1[494], out_wimask_616) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_616 = and(out_woready_1[494], out_womask_616) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6122 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6123 = and(out_f_rivalid_616, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6124 = and(UInt<1>(0h1), out_f_roready_616) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6125 = eq(out_rimask_616, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6126 = eq(out_wimask_616, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6127 = eq(out_romask_616, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6128 = eq(out_womask_616, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_524 = or(_out_T_6121, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_524 = cat(_T_449, _out_prepend_T_524) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6129 = or(out_prepend_524, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6130 = bits(_out_T_6129, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_617 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_617 = orr(_out_rimask_T_617) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_617 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_617 = andr(_out_wimask_T_617) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_617 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_617 = orr(_out_romask_T_617) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_617 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_617 = andr(_out_womask_T_617) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_617 = and(out_rivalid_1[495], out_rimask_617) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_617 = and(out_roready_1[495], out_romask_617) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_617 = and(out_wivalid_1[495], out_wimask_617) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_617 = and(out_woready_1[495], out_womask_617) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6131 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6132 = and(out_f_rivalid_617, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6133 = and(UInt<1>(0h1), out_f_roready_617) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6134 = eq(out_rimask_617, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6135 = eq(out_wimask_617, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6136 = eq(out_romask_617, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6137 = eq(out_womask_617, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6138 = or(_T_1314, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6139 = bits(_out_T_6138, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_618 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_618 = orr(_out_rimask_T_618) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_618 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_618 = andr(_out_wimask_T_618) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_618 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_618 = orr(_out_romask_T_618) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_618 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_618 = andr(_out_womask_T_618) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_618 = and(out_rivalid_1[496], out_rimask_618) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_618 = and(out_roready_1[496], out_romask_618) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_618 = and(out_wivalid_1[496], out_wimask_618) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_618 = and(out_woready_1[496], out_womask_618) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6140 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6141 = and(out_f_rivalid_618, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6142 = and(UInt<1>(0h1), out_f_roready_618) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6143 = eq(out_rimask_618, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6144 = eq(out_wimask_618, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6145 = eq(out_romask_618, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6146 = eq(out_womask_618, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_525 = or(_out_T_6139, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_525 = cat(_T_1315, _out_prepend_T_525) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6147 = or(out_prepend_525, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6148 = bits(_out_T_6147, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_619 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_619 = orr(_out_rimask_T_619) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_619 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_619 = andr(_out_wimask_T_619) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_619 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_619 = orr(_out_romask_T_619) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_619 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_619 = andr(_out_womask_T_619) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_619 = and(out_rivalid_1[497], out_rimask_619) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_619 = and(out_roready_1[497], out_romask_619) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_619 = and(out_wivalid_1[497], out_wimask_619) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_619 = and(out_woready_1[497], out_womask_619) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6149 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6150 = and(out_f_rivalid_619, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6151 = and(UInt<1>(0h1), out_f_roready_619) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6152 = eq(out_rimask_619, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6153 = eq(out_wimask_619, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6154 = eq(out_romask_619, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6155 = eq(out_womask_619, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_526 = or(_out_T_6148, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_526 = cat(_T_1316, _out_prepend_T_526) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6156 = or(out_prepend_526, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6157 = bits(_out_T_6156, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_620 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_620 = orr(_out_rimask_T_620) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_620 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_620 = andr(_out_wimask_T_620) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_620 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_620 = orr(_out_romask_T_620) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_620 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_620 = andr(_out_womask_T_620) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_620 = and(out_rivalid_1[498], out_rimask_620) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_620 = and(out_roready_1[498], out_romask_620) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_620 = and(out_wivalid_1[498], out_wimask_620) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_620 = and(out_woready_1[498], out_womask_620) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6158 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6159 = and(out_f_rivalid_620, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6160 = and(UInt<1>(0h1), out_f_roready_620) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6161 = eq(out_rimask_620, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6162 = eq(out_wimask_620, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6163 = eq(out_romask_620, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6164 = eq(out_womask_620, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_527 = or(_out_T_6157, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_527 = cat(_T_1317, _out_prepend_T_527) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6165 = or(out_prepend_527, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6166 = bits(_out_T_6165, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_621 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_621 = orr(_out_rimask_T_621) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_621 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_621 = andr(_out_wimask_T_621) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_621 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_621 = orr(_out_romask_T_621) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_621 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_621 = andr(_out_womask_T_621) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_621 = and(out_rivalid_1[499], out_rimask_621) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_621 = and(out_roready_1[499], out_romask_621) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_621 = and(out_wivalid_1[499], out_wimask_621) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_621 = and(out_woready_1[499], out_womask_621) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6167 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6168 = and(out_f_rivalid_621, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6169 = and(UInt<1>(0h1), out_f_roready_621) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6170 = eq(out_rimask_621, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6171 = eq(out_wimask_621, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6172 = eq(out_romask_621, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6173 = eq(out_womask_621, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_528 = or(_out_T_6166, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_528 = cat(_T_1318, _out_prepend_T_528) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6174 = or(out_prepend_528, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6175 = bits(_out_T_6174, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_622 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_622 = orr(_out_rimask_T_622) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_622 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_622 = andr(_out_wimask_T_622) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_622 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_622 = orr(_out_romask_T_622) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_622 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_622 = andr(_out_womask_T_622) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_622 = and(out_rivalid_1[500], out_rimask_622) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_622 = and(out_roready_1[500], out_romask_622) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_622 = and(out_wivalid_1[500], out_wimask_622) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_622 = and(out_woready_1[500], out_womask_622) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6176 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6177 = and(out_f_rivalid_622, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6178 = and(UInt<1>(0h1), out_f_roready_622) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6179 = eq(out_rimask_622, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6180 = eq(out_wimask_622, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6181 = eq(out_romask_622, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6182 = eq(out_womask_622, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_529 = or(_out_T_6175, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_529 = cat(_T_1319, _out_prepend_T_529) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6183 = or(out_prepend_529, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6184 = bits(_out_T_6183, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_623 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_623 = orr(_out_rimask_T_623) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_623 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_623 = andr(_out_wimask_T_623) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_623 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_623 = orr(_out_romask_T_623) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_623 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_623 = andr(_out_womask_T_623) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_623 = and(out_rivalid_1[501], out_rimask_623) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_623 = and(out_roready_1[501], out_romask_623) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_623 = and(out_wivalid_1[501], out_wimask_623) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_623 = and(out_woready_1[501], out_womask_623) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6185 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6186 = and(out_f_rivalid_623, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6187 = and(UInt<1>(0h1), out_f_roready_623) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6188 = eq(out_rimask_623, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6189 = eq(out_wimask_623, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6190 = eq(out_romask_623, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6191 = eq(out_womask_623, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_530 = or(_out_T_6184, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_530 = cat(_T_1320, _out_prepend_T_530) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6192 = or(out_prepend_530, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6193 = bits(_out_T_6192, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_624 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_624 = orr(_out_rimask_T_624) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_624 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_624 = andr(_out_wimask_T_624) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_624 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_624 = orr(_out_romask_T_624) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_624 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_624 = andr(_out_womask_T_624) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_624 = and(out_rivalid_1[502], out_rimask_624) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_624 = and(out_roready_1[502], out_romask_624) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_624 = and(out_wivalid_1[502], out_wimask_624) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_624 = and(out_woready_1[502], out_womask_624) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6194 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6195 = and(out_f_rivalid_624, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6196 = and(UInt<1>(0h1), out_f_roready_624) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6197 = eq(out_rimask_624, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6198 = eq(out_wimask_624, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6199 = eq(out_romask_624, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6200 = eq(out_womask_624, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_531 = or(_out_T_6193, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_531 = cat(_T_1321, _out_prepend_T_531) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6201 = or(out_prepend_531, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6202 = bits(_out_T_6201, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_625 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_625 = orr(_out_rimask_T_625) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_625 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_625 = andr(_out_wimask_T_625) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_625 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_625 = orr(_out_romask_T_625) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_625 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_625 = andr(_out_womask_T_625) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_625 = and(out_rivalid_1[503], out_rimask_625) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_625 = and(out_roready_1[503], out_romask_625) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_625 = and(out_wivalid_1[503], out_wimask_625) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_625 = and(out_woready_1[503], out_womask_625) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6203 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_625 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[8], _out_T_6203 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_6204 = and(out_f_rivalid_625, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6205 = and(UInt<1>(0h1), out_f_roready_625) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6206 = and(out_f_wivalid_625, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6207 = and(UInt<1>(0h1), out_f_woready_625) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6208 = eq(out_rimask_625, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6209 = eq(out_wimask_625, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6210 = eq(out_romask_625, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6211 = eq(out_womask_625, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6212 = or(programBufferMem[8], UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6213 = bits(_out_T_6212, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_626 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_626 = orr(_out_rimask_T_626) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_626 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_626 = andr(_out_wimask_T_626) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_626 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_626 = orr(_out_romask_T_626) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_626 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_626 = andr(_out_womask_T_626) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_626 = and(out_rivalid_1[504], out_rimask_626) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_626 = and(out_roready_1[504], out_romask_626) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_626 = and(out_wivalid_1[504], out_wimask_626) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_626 = and(out_woready_1[504], out_womask_626) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6214 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_626 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[9], _out_T_6214 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_6215 = and(out_f_rivalid_626, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6216 = and(UInt<1>(0h1), out_f_roready_626) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6217 = and(out_f_wivalid_626, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6218 = and(UInt<1>(0h1), out_f_woready_626) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6219 = eq(out_rimask_626, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6220 = eq(out_wimask_626, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6221 = eq(out_romask_626, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6222 = eq(out_womask_626, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_532 = or(_out_T_6213, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_532 = cat(programBufferMem[9], _out_prepend_T_532) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6223 = or(out_prepend_532, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6224 = bits(_out_T_6223, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_627 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_627 = orr(_out_rimask_T_627) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_627 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_627 = andr(_out_wimask_T_627) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_627 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_627 = orr(_out_romask_T_627) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_627 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_627 = andr(_out_womask_T_627) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_627 = and(out_rivalid_1[505], out_rimask_627) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_627 = and(out_roready_1[505], out_romask_627) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_627 = and(out_wivalid_1[505], out_wimask_627) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_627 = and(out_woready_1[505], out_womask_627) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6225 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_627 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[10], _out_T_6225 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_6226 = and(out_f_rivalid_627, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6227 = and(UInt<1>(0h1), out_f_roready_627) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6228 = and(out_f_wivalid_627, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6229 = and(UInt<1>(0h1), out_f_woready_627) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6230 = eq(out_rimask_627, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6231 = eq(out_wimask_627, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6232 = eq(out_romask_627, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6233 = eq(out_womask_627, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_533 = or(_out_T_6224, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_533 = cat(programBufferMem[10], _out_prepend_T_533) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6234 = or(out_prepend_533, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6235 = bits(_out_T_6234, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_628 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_628 = orr(_out_rimask_T_628) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_628 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_628 = andr(_out_wimask_T_628) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_628 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_628 = orr(_out_romask_T_628) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_628 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_628 = andr(_out_womask_T_628) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_628 = and(out_rivalid_1[506], out_rimask_628) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_628 = and(out_roready_1[506], out_romask_628) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_628 = and(out_wivalid_1[506], out_wimask_628) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_628 = and(out_woready_1[506], out_womask_628) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6236 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_628 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[11], _out_T_6236 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_6237 = and(out_f_rivalid_628, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6238 = and(UInt<1>(0h1), out_f_roready_628) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6239 = and(out_f_wivalid_628, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6240 = and(UInt<1>(0h1), out_f_woready_628) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6241 = eq(out_rimask_628, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6242 = eq(out_wimask_628, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6243 = eq(out_romask_628, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6244 = eq(out_womask_628, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_534 = or(_out_T_6235, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_534 = cat(programBufferMem[11], _out_prepend_T_534) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6245 = or(out_prepend_534, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6246 = bits(_out_T_6245, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_629 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_629 = orr(_out_rimask_T_629) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_629 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_629 = andr(_out_wimask_T_629) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_629 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_629 = orr(_out_romask_T_629) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_629 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_629 = andr(_out_womask_T_629) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_629 = and(out_rivalid_1[507], out_rimask_629) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_629 = and(out_roready_1[507], out_romask_629) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_629 = and(out_wivalid_1[507], out_wimask_629) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_629 = and(out_woready_1[507], out_womask_629) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6247 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_629 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[12], _out_T_6247 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_6248 = and(out_f_rivalid_629, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6249 = and(UInt<1>(0h1), out_f_roready_629) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6250 = and(out_f_wivalid_629, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6251 = and(UInt<1>(0h1), out_f_woready_629) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6252 = eq(out_rimask_629, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6253 = eq(out_wimask_629, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6254 = eq(out_romask_629, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6255 = eq(out_womask_629, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_535 = or(_out_T_6246, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_535 = cat(programBufferMem[12], _out_prepend_T_535) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6256 = or(out_prepend_535, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6257 = bits(_out_T_6256, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_630 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_630 = orr(_out_rimask_T_630) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_630 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_630 = andr(_out_wimask_T_630) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_630 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_630 = orr(_out_romask_T_630) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_630 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_630 = andr(_out_womask_T_630) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_630 = and(out_rivalid_1[508], out_rimask_630) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_630 = and(out_roready_1[508], out_romask_630) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_630 = and(out_wivalid_1[508], out_wimask_630) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_630 = and(out_woready_1[508], out_womask_630) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6258 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_630 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[13], _out_T_6258 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_6259 = and(out_f_rivalid_630, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6260 = and(UInt<1>(0h1), out_f_roready_630) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6261 = and(out_f_wivalid_630, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6262 = and(UInt<1>(0h1), out_f_woready_630) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6263 = eq(out_rimask_630, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6264 = eq(out_wimask_630, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6265 = eq(out_romask_630, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6266 = eq(out_womask_630, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_536 = or(_out_T_6257, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_536 = cat(programBufferMem[13], _out_prepend_T_536) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6267 = or(out_prepend_536, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6268 = bits(_out_T_6267, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_631 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_631 = orr(_out_rimask_T_631) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_631 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_631 = andr(_out_wimask_T_631) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_631 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_631 = orr(_out_romask_T_631) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_631 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_631 = andr(_out_womask_T_631) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_631 = and(out_rivalid_1[509], out_rimask_631) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_631 = and(out_roready_1[509], out_romask_631) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_631 = and(out_wivalid_1[509], out_wimask_631) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_631 = and(out_woready_1[509], out_womask_631) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6269 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_631 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[14], _out_T_6269 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_6270 = and(out_f_rivalid_631, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6271 = and(UInt<1>(0h1), out_f_roready_631) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6272 = and(out_f_wivalid_631, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6273 = and(UInt<1>(0h1), out_f_woready_631) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6274 = eq(out_rimask_631, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6275 = eq(out_wimask_631, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6276 = eq(out_romask_631, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6277 = eq(out_womask_631, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_537 = or(_out_T_6268, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_537 = cat(programBufferMem[14], _out_prepend_T_537) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6278 = or(out_prepend_537, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6279 = bits(_out_T_6278, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_632 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_632 = orr(_out_rimask_T_632) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_632 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_632 = andr(_out_wimask_T_632) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_632 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_632 = orr(_out_romask_T_632) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_632 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_632 = andr(_out_womask_T_632) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_632 = and(out_rivalid_1[510], out_rimask_632) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_632 = and(out_roready_1[510], out_romask_632) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_632 = and(out_wivalid_1[510], out_wimask_632) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_632 = and(out_woready_1[510], out_womask_632) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6280 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_632 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[15], _out_T_6280 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_6281 = and(out_f_rivalid_632, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6282 = and(UInt<1>(0h1), out_f_roready_632) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6283 = and(out_f_wivalid_632, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6284 = and(UInt<1>(0h1), out_f_woready_632) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6285 = eq(out_rimask_632, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6286 = eq(out_wimask_632, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6287 = eq(out_romask_632, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6288 = eq(out_womask_632, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_538 = or(_out_T_6279, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_538 = cat(programBufferMem[15], _out_prepend_T_538) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6289 = or(out_prepend_538, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6290 = bits(_out_T_6289, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_633 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_633 = orr(_out_rimask_T_633) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_633 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_633 = andr(_out_wimask_T_633) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_633 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_633 = orr(_out_romask_T_633) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_633 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_633 = andr(_out_womask_T_633) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_633 = and(out_rivalid_1[511], out_rimask_633) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_633 = and(out_roready_1[511], out_romask_633) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_633 = and(out_wivalid_1[511], out_wimask_633) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_633 = and(out_woready_1[511], out_womask_633) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6291 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6292 = and(out_f_rivalid_633, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6293 = and(UInt<1>(0h1), out_f_roready_633) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6294 = eq(out_rimask_633, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6295 = eq(out_wimask_633, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6296 = eq(out_romask_633, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6297 = eq(out_womask_633, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6298 = or(_T_1370, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6299 = bits(_out_T_6298, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_634 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_634 = orr(_out_rimask_T_634) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_634 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_634 = andr(_out_wimask_T_634) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_634 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_634 = orr(_out_romask_T_634) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_634 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_634 = andr(_out_womask_T_634) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_634 = and(out_rivalid_1[512], out_rimask_634) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_634 = and(out_roready_1[512], out_romask_634) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_634 = and(out_wivalid_1[512], out_wimask_634) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_634 = and(out_woready_1[512], out_womask_634) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6300 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6301 = and(out_f_rivalid_634, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6302 = and(UInt<1>(0h1), out_f_roready_634) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6303 = eq(out_rimask_634, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6304 = eq(out_wimask_634, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6305 = eq(out_romask_634, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6306 = eq(out_womask_634, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_539 = or(_out_T_6299, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_539 = cat(_T_1371, _out_prepend_T_539) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6307 = or(out_prepend_539, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6308 = bits(_out_T_6307, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_635 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_635 = orr(_out_rimask_T_635) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_635 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_635 = andr(_out_wimask_T_635) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_635 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_635 = orr(_out_romask_T_635) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_635 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_635 = andr(_out_womask_T_635) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_635 = and(out_rivalid_1[513], out_rimask_635) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_635 = and(out_roready_1[513], out_romask_635) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_635 = and(out_wivalid_1[513], out_wimask_635) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_635 = and(out_woready_1[513], out_womask_635) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6309 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6310 = and(out_f_rivalid_635, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6311 = and(UInt<1>(0h1), out_f_roready_635) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6312 = eq(out_rimask_635, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6313 = eq(out_wimask_635, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6314 = eq(out_romask_635, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6315 = eq(out_womask_635, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_540 = or(_out_T_6308, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_540 = cat(_T_1372, _out_prepend_T_540) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6316 = or(out_prepend_540, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6317 = bits(_out_T_6316, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_636 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_636 = orr(_out_rimask_T_636) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_636 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_636 = andr(_out_wimask_T_636) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_636 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_636 = orr(_out_romask_T_636) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_636 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_636 = andr(_out_womask_T_636) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_636 = and(out_rivalid_1[514], out_rimask_636) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_636 = and(out_roready_1[514], out_romask_636) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_636 = and(out_wivalid_1[514], out_wimask_636) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_636 = and(out_woready_1[514], out_womask_636) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6318 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6319 = and(out_f_rivalid_636, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6320 = and(UInt<1>(0h1), out_f_roready_636) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6321 = eq(out_rimask_636, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6322 = eq(out_wimask_636, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6323 = eq(out_romask_636, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6324 = eq(out_womask_636, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_541 = or(_out_T_6317, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_541 = cat(_T_1373, _out_prepend_T_541) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6325 = or(out_prepend_541, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6326 = bits(_out_T_6325, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_637 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_637 = orr(_out_rimask_T_637) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_637 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_637 = andr(_out_wimask_T_637) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_637 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_637 = orr(_out_romask_T_637) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_637 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_637 = andr(_out_womask_T_637) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_637 = and(out_rivalid_1[515], out_rimask_637) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_637 = and(out_roready_1[515], out_romask_637) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_637 = and(out_wivalid_1[515], out_wimask_637) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_637 = and(out_woready_1[515], out_womask_637) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6327 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6328 = and(out_f_rivalid_637, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6329 = and(UInt<1>(0h1), out_f_roready_637) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6330 = eq(out_rimask_637, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6331 = eq(out_wimask_637, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6332 = eq(out_romask_637, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6333 = eq(out_womask_637, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_542 = or(_out_T_6326, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_542 = cat(_T_1374, _out_prepend_T_542) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6334 = or(out_prepend_542, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6335 = bits(_out_T_6334, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_638 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_638 = orr(_out_rimask_T_638) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_638 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_638 = andr(_out_wimask_T_638) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_638 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_638 = orr(_out_romask_T_638) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_638 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_638 = andr(_out_womask_T_638) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_638 = and(out_rivalid_1[516], out_rimask_638) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_638 = and(out_roready_1[516], out_romask_638) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_638 = and(out_wivalid_1[516], out_wimask_638) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_638 = and(out_woready_1[516], out_womask_638) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6336 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6337 = and(out_f_rivalid_638, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6338 = and(UInt<1>(0h1), out_f_roready_638) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6339 = eq(out_rimask_638, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6340 = eq(out_wimask_638, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6341 = eq(out_romask_638, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6342 = eq(out_womask_638, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_543 = or(_out_T_6335, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_543 = cat(_T_1375, _out_prepend_T_543) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6343 = or(out_prepend_543, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6344 = bits(_out_T_6343, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_639 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_639 = orr(_out_rimask_T_639) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_639 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_639 = andr(_out_wimask_T_639) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_639 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_639 = orr(_out_romask_T_639) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_639 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_639 = andr(_out_womask_T_639) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_639 = and(out_rivalid_1[517], out_rimask_639) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_639 = and(out_roready_1[517], out_romask_639) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_639 = and(out_wivalid_1[517], out_wimask_639) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_639 = and(out_woready_1[517], out_womask_639) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6345 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6346 = and(out_f_rivalid_639, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6347 = and(UInt<1>(0h1), out_f_roready_639) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6348 = eq(out_rimask_639, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6349 = eq(out_wimask_639, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6350 = eq(out_romask_639, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6351 = eq(out_womask_639, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_544 = or(_out_T_6344, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_544 = cat(_T_1376, _out_prepend_T_544) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6352 = or(out_prepend_544, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6353 = bits(_out_T_6352, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_640 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_640 = orr(_out_rimask_T_640) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_640 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_640 = andr(_out_wimask_T_640) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_640 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_640 = orr(_out_romask_T_640) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_640 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_640 = andr(_out_womask_T_640) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_640 = and(out_rivalid_1[518], out_rimask_640) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_640 = and(out_roready_1[518], out_romask_640) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_640 = and(out_wivalid_1[518], out_wimask_640) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_640 = and(out_woready_1[518], out_womask_640) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6354 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6355 = and(out_f_rivalid_640, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6356 = and(UInt<1>(0h1), out_f_roready_640) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6357 = eq(out_rimask_640, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6358 = eq(out_wimask_640, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6359 = eq(out_romask_640, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6360 = eq(out_womask_640, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_545 = or(_out_T_6353, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_545 = cat(_T_1377, _out_prepend_T_545) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6361 = or(out_prepend_545, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6362 = bits(_out_T_6361, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_641 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_641 = orr(_out_rimask_T_641) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_641 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_641 = andr(_out_wimask_T_641) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_641 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_641 = orr(_out_romask_T_641) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_641 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_641 = andr(_out_womask_T_641) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_641 = and(out_rivalid_1[519], out_rimask_641) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_641 = and(out_roready_1[519], out_romask_641) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_641 = and(out_wivalid_1[519], out_wimask_641) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_641 = and(out_woready_1[519], out_womask_641) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6363 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6364 = and(out_f_rivalid_641, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6365 = and(UInt<1>(0h1), out_f_roready_641) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6366 = eq(out_rimask_641, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6367 = eq(out_wimask_641, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6368 = eq(out_romask_641, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6369 = eq(out_womask_641, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6370 = or(_T_746, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6371 = bits(_out_T_6370, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_642 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_642 = orr(_out_rimask_T_642) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_642 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_642 = andr(_out_wimask_T_642) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_642 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_642 = orr(_out_romask_T_642) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_642 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_642 = andr(_out_womask_T_642) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_642 = and(out_rivalid_1[520], out_rimask_642) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_642 = and(out_roready_1[520], out_romask_642) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_642 = and(out_wivalid_1[520], out_wimask_642) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_642 = and(out_woready_1[520], out_womask_642) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6372 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6373 = and(out_f_rivalid_642, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6374 = and(UInt<1>(0h1), out_f_roready_642) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6375 = eq(out_rimask_642, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6376 = eq(out_wimask_642, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6377 = eq(out_romask_642, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6378 = eq(out_womask_642, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_546 = or(_out_T_6371, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_546 = cat(_T_747, _out_prepend_T_546) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6379 = or(out_prepend_546, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6380 = bits(_out_T_6379, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_643 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_643 = orr(_out_rimask_T_643) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_643 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_643 = andr(_out_wimask_T_643) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_643 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_643 = orr(_out_romask_T_643) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_643 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_643 = andr(_out_womask_T_643) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_643 = and(out_rivalid_1[521], out_rimask_643) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_643 = and(out_roready_1[521], out_romask_643) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_643 = and(out_wivalid_1[521], out_wimask_643) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_643 = and(out_woready_1[521], out_womask_643) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6381 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6382 = and(out_f_rivalid_643, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6383 = and(UInt<1>(0h1), out_f_roready_643) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6384 = eq(out_rimask_643, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6385 = eq(out_wimask_643, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6386 = eq(out_romask_643, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6387 = eq(out_womask_643, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_547 = or(_out_T_6380, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_547 = cat(_T_748, _out_prepend_T_547) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6388 = or(out_prepend_547, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6389 = bits(_out_T_6388, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_644 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_644 = orr(_out_rimask_T_644) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_644 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_644 = andr(_out_wimask_T_644) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_644 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_644 = orr(_out_romask_T_644) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_644 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_644 = andr(_out_womask_T_644) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_644 = and(out_rivalid_1[522], out_rimask_644) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_644 = and(out_roready_1[522], out_romask_644) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_644 = and(out_wivalid_1[522], out_wimask_644) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_644 = and(out_woready_1[522], out_womask_644) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6390 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6391 = and(out_f_rivalid_644, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6392 = and(UInt<1>(0h1), out_f_roready_644) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6393 = eq(out_rimask_644, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6394 = eq(out_wimask_644, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6395 = eq(out_romask_644, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6396 = eq(out_womask_644, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_548 = or(_out_T_6389, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_548 = cat(_T_749, _out_prepend_T_548) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6397 = or(out_prepend_548, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6398 = bits(_out_T_6397, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_645 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_645 = orr(_out_rimask_T_645) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_645 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_645 = andr(_out_wimask_T_645) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_645 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_645 = orr(_out_romask_T_645) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_645 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_645 = andr(_out_womask_T_645) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_645 = and(out_rivalid_1[523], out_rimask_645) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_645 = and(out_roready_1[523], out_romask_645) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_645 = and(out_wivalid_1[523], out_wimask_645) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_645 = and(out_woready_1[523], out_womask_645) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6399 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6400 = and(out_f_rivalid_645, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6401 = and(UInt<1>(0h1), out_f_roready_645) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6402 = eq(out_rimask_645, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6403 = eq(out_wimask_645, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6404 = eq(out_romask_645, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6405 = eq(out_womask_645, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_549 = or(_out_T_6398, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_549 = cat(_T_750, _out_prepend_T_549) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6406 = or(out_prepend_549, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6407 = bits(_out_T_6406, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_646 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_646 = orr(_out_rimask_T_646) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_646 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_646 = andr(_out_wimask_T_646) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_646 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_646 = orr(_out_romask_T_646) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_646 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_646 = andr(_out_womask_T_646) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_646 = and(out_rivalid_1[524], out_rimask_646) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_646 = and(out_roready_1[524], out_romask_646) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_646 = and(out_wivalid_1[524], out_wimask_646) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_646 = and(out_woready_1[524], out_womask_646) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6408 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6409 = and(out_f_rivalid_646, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6410 = and(UInt<1>(0h1), out_f_roready_646) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6411 = eq(out_rimask_646, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6412 = eq(out_wimask_646, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6413 = eq(out_romask_646, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6414 = eq(out_womask_646, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_550 = or(_out_T_6407, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_550 = cat(_T_751, _out_prepend_T_550) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6415 = or(out_prepend_550, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6416 = bits(_out_T_6415, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_647 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_647 = orr(_out_rimask_T_647) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_647 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_647 = andr(_out_wimask_T_647) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_647 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_647 = orr(_out_romask_T_647) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_647 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_647 = andr(_out_womask_T_647) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_647 = and(out_rivalid_1[525], out_rimask_647) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_647 = and(out_roready_1[525], out_romask_647) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_647 = and(out_wivalid_1[525], out_wimask_647) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_647 = and(out_woready_1[525], out_womask_647) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6417 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6418 = and(out_f_rivalid_647, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6419 = and(UInt<1>(0h1), out_f_roready_647) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6420 = eq(out_rimask_647, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6421 = eq(out_wimask_647, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6422 = eq(out_romask_647, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6423 = eq(out_womask_647, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_551 = or(_out_T_6416, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_551 = cat(_T_752, _out_prepend_T_551) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6424 = or(out_prepend_551, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6425 = bits(_out_T_6424, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_648 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_648 = orr(_out_rimask_T_648) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_648 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_648 = andr(_out_wimask_T_648) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_648 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_648 = orr(_out_romask_T_648) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_648 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_648 = andr(_out_womask_T_648) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_648 = and(out_rivalid_1[526], out_rimask_648) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_648 = and(out_roready_1[526], out_romask_648) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_648 = and(out_wivalid_1[526], out_wimask_648) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_648 = and(out_woready_1[526], out_womask_648) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6426 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6427 = and(out_f_rivalid_648, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6428 = and(UInt<1>(0h1), out_f_roready_648) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6429 = eq(out_rimask_648, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6430 = eq(out_wimask_648, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6431 = eq(out_romask_648, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6432 = eq(out_womask_648, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_552 = or(_out_T_6425, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_552 = cat(_T_753, _out_prepend_T_552) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6433 = or(out_prepend_552, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6434 = bits(_out_T_6433, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_649 = bits(out_frontMask_1, 9, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_649 = orr(_out_rimask_T_649) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_649 = bits(out_frontMask_1, 9, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_649 = andr(_out_wimask_T_649) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_649 = bits(out_backMask_1, 9, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_649 = orr(_out_romask_T_649) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_649 = bits(out_backMask_1, 9, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_649 = andr(_out_womask_T_649) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_649 = and(out_rivalid_1[527], out_rimask_649) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_649 = and(out_roready_1[527], out_romask_649) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_649 = and(out_wivalid_1[527], out_wimask_649) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_649 = and(out_woready_1[527], out_womask_649) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6435 = bits(out_front_1.bits.data, 9, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect hartHaltedWrEn, out_f_woready_649 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 282:11] connect hartHaltedId, _out_T_6435 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 283:13] node _out_T_6436 = and(out_f_wivalid_649, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6437 = and(UInt<1>(0h1), out_f_woready_649) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6438 = eq(out_rimask_649, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6439 = eq(out_wimask_649, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6440 = eq(out_romask_649, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6441 = eq(out_womask_649, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6442 = or(UInt<1>(0h0), UInt<10>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6443 = bits(_out_T_6442, 9, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_650 = bits(out_frontMask_1, 41, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_650 = orr(_out_rimask_T_650) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_650 = bits(out_frontMask_1, 41, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_650 = andr(_out_wimask_T_650) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_650 = bits(out_backMask_1, 41, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_650 = orr(_out_romask_T_650) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_650 = bits(out_backMask_1, 41, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_650 = andr(_out_womask_T_650) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_650 = and(out_rivalid_1[528], out_rimask_650) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_650 = and(out_roready_1[528], out_romask_650) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_650 = and(out_wivalid_1[528], out_wimask_650) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_650 = and(out_woready_1[528], out_womask_650) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6444 = bits(out_front_1.bits.data, 41, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect hartGoingWrEn, out_f_woready_650 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 282:11] connect hartGoingId, _out_T_6444 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 283:13] node _out_T_6445 = and(out_f_wivalid_650, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6446 = and(UInt<1>(0h1), out_f_woready_650) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6447 = eq(out_rimask_650, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6448 = eq(out_wimask_650, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6449 = eq(out_romask_650, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6450 = eq(out_womask_650, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_553 = or(_out_T_6443, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_553 = cat(UInt<1>(0h0), _out_prepend_T_553) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6451 = or(out_prepend_553, UInt<42>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6452 = bits(_out_T_6451, 41, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_651 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_651 = orr(_out_rimask_T_651) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_651 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_651 = andr(_out_wimask_T_651) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_651 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_651 = orr(_out_romask_T_651) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_651 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_651 = andr(_out_womask_T_651) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_651 = and(out_rivalid_1[529], out_rimask_651) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_651 = and(out_roready_1[529], out_romask_651) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_651 = and(out_wivalid_1[529], out_wimask_651) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_651 = and(out_woready_1[529], out_womask_651) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6453 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6454 = and(out_f_rivalid_651, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6455 = and(UInt<1>(0h1), out_f_roready_651) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6456 = eq(out_rimask_651, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6457 = eq(out_wimask_651, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6458 = eq(out_romask_651, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6459 = eq(out_womask_651, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6460 = or(_T_602, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6461 = bits(_out_T_6460, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_652 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_652 = orr(_out_rimask_T_652) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_652 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_652 = andr(_out_wimask_T_652) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_652 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_652 = orr(_out_romask_T_652) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_652 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_652 = andr(_out_womask_T_652) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_652 = and(out_rivalid_1[530], out_rimask_652) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_652 = and(out_roready_1[530], out_romask_652) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_652 = and(out_wivalid_1[530], out_wimask_652) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_652 = and(out_woready_1[530], out_womask_652) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6462 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6463 = and(out_f_rivalid_652, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6464 = and(UInt<1>(0h1), out_f_roready_652) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6465 = eq(out_rimask_652, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6466 = eq(out_wimask_652, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6467 = eq(out_romask_652, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6468 = eq(out_womask_652, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_554 = or(_out_T_6461, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_554 = cat(_T_603, _out_prepend_T_554) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6469 = or(out_prepend_554, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6470 = bits(_out_T_6469, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_653 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_653 = orr(_out_rimask_T_653) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_653 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_653 = andr(_out_wimask_T_653) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_653 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_653 = orr(_out_romask_T_653) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_653 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_653 = andr(_out_womask_T_653) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_653 = and(out_rivalid_1[531], out_rimask_653) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_653 = and(out_roready_1[531], out_romask_653) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_653 = and(out_wivalid_1[531], out_wimask_653) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_653 = and(out_woready_1[531], out_womask_653) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6471 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6472 = and(out_f_rivalid_653, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6473 = and(UInt<1>(0h1), out_f_roready_653) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6474 = eq(out_rimask_653, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6475 = eq(out_wimask_653, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6476 = eq(out_romask_653, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6477 = eq(out_womask_653, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_555 = or(_out_T_6470, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_555 = cat(_T_604, _out_prepend_T_555) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6478 = or(out_prepend_555, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6479 = bits(_out_T_6478, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_654 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_654 = orr(_out_rimask_T_654) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_654 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_654 = andr(_out_wimask_T_654) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_654 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_654 = orr(_out_romask_T_654) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_654 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_654 = andr(_out_womask_T_654) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_654 = and(out_rivalid_1[532], out_rimask_654) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_654 = and(out_roready_1[532], out_romask_654) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_654 = and(out_wivalid_1[532], out_wimask_654) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_654 = and(out_woready_1[532], out_womask_654) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6480 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6481 = and(out_f_rivalid_654, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6482 = and(UInt<1>(0h1), out_f_roready_654) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6483 = eq(out_rimask_654, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6484 = eq(out_wimask_654, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6485 = eq(out_romask_654, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6486 = eq(out_womask_654, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_556 = or(_out_T_6479, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_556 = cat(_T_605, _out_prepend_T_556) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6487 = or(out_prepend_556, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6488 = bits(_out_T_6487, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_655 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_655 = orr(_out_rimask_T_655) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_655 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_655 = andr(_out_wimask_T_655) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_655 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_655 = orr(_out_romask_T_655) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_655 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_655 = andr(_out_womask_T_655) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_655 = and(out_rivalid_1[533], out_rimask_655) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_655 = and(out_roready_1[533], out_romask_655) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_655 = and(out_wivalid_1[533], out_wimask_655) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_655 = and(out_woready_1[533], out_womask_655) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6489 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6490 = and(out_f_rivalid_655, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6491 = and(UInt<1>(0h1), out_f_roready_655) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6492 = eq(out_rimask_655, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6493 = eq(out_wimask_655, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6494 = eq(out_romask_655, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6495 = eq(out_womask_655, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_557 = or(_out_T_6488, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_557 = cat(_T_606, _out_prepend_T_557) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6496 = or(out_prepend_557, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6497 = bits(_out_T_6496, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_656 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_656 = orr(_out_rimask_T_656) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_656 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_656 = andr(_out_wimask_T_656) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_656 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_656 = orr(_out_romask_T_656) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_656 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_656 = andr(_out_womask_T_656) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_656 = and(out_rivalid_1[534], out_rimask_656) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_656 = and(out_roready_1[534], out_romask_656) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_656 = and(out_wivalid_1[534], out_wimask_656) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_656 = and(out_woready_1[534], out_womask_656) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6498 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6499 = and(out_f_rivalid_656, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6500 = and(UInt<1>(0h1), out_f_roready_656) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6501 = eq(out_rimask_656, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6502 = eq(out_wimask_656, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6503 = eq(out_romask_656, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6504 = eq(out_womask_656, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_558 = or(_out_T_6497, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_558 = cat(_T_607, _out_prepend_T_558) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6505 = or(out_prepend_558, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6506 = bits(_out_T_6505, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_657 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_657 = orr(_out_rimask_T_657) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_657 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_657 = andr(_out_wimask_T_657) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_657 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_657 = orr(_out_romask_T_657) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_657 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_657 = andr(_out_womask_T_657) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_657 = and(out_rivalid_1[535], out_rimask_657) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_657 = and(out_roready_1[535], out_romask_657) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_657 = and(out_wivalid_1[535], out_wimask_657) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_657 = and(out_woready_1[535], out_womask_657) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6507 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6508 = and(out_f_rivalid_657, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6509 = and(UInt<1>(0h1), out_f_roready_657) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6510 = eq(out_rimask_657, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6511 = eq(out_wimask_657, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6512 = eq(out_romask_657, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6513 = eq(out_womask_657, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_559 = or(_out_T_6506, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_559 = cat(_T_608, _out_prepend_T_559) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6514 = or(out_prepend_559, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6515 = bits(_out_T_6514, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_658 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_658 = orr(_out_rimask_T_658) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_658 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_658 = andr(_out_wimask_T_658) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_658 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_658 = orr(_out_romask_T_658) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_658 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_658 = andr(_out_womask_T_658) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_658 = and(out_rivalid_1[536], out_rimask_658) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_658 = and(out_roready_1[536], out_romask_658) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_658 = and(out_wivalid_1[536], out_wimask_658) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_658 = and(out_woready_1[536], out_womask_658) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6516 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6517 = and(out_f_rivalid_658, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6518 = and(UInt<1>(0h1), out_f_roready_658) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6519 = eq(out_rimask_658, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6520 = eq(out_wimask_658, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6521 = eq(out_romask_658, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6522 = eq(out_womask_658, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_560 = or(_out_T_6515, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_560 = cat(_T_609, _out_prepend_T_560) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6523 = or(out_prepend_560, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6524 = bits(_out_T_6523, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_659 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_659 = orr(_out_rimask_T_659) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_659 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_659 = andr(_out_wimask_T_659) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_659 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_659 = orr(_out_romask_T_659) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_659 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_659 = andr(_out_womask_T_659) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_659 = and(out_rivalid_1[537], out_rimask_659) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_659 = and(out_roready_1[537], out_romask_659) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_659 = and(out_wivalid_1[537], out_wimask_659) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_659 = and(out_woready_1[537], out_womask_659) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6525 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6526 = and(out_f_rivalid_659, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6527 = and(UInt<1>(0h1), out_f_roready_659) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6528 = eq(out_rimask_659, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6529 = eq(out_wimask_659, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6530 = eq(out_romask_659, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6531 = eq(out_womask_659, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6532 = or(UInt<8>(0h23), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6533 = bits(_out_T_6532, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_660 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_660 = orr(_out_rimask_T_660) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_660 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_660 = andr(_out_wimask_T_660) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_660 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_660 = orr(_out_romask_T_660) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_660 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_660 = andr(_out_womask_T_660) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_660 = and(out_rivalid_1[538], out_rimask_660) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_660 = and(out_roready_1[538], out_romask_660) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_660 = and(out_wivalid_1[538], out_wimask_660) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_660 = and(out_woready_1[538], out_womask_660) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6534 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6535 = and(out_f_rivalid_660, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6536 = and(UInt<1>(0h1), out_f_roready_660) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6537 = eq(out_rimask_660, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6538 = eq(out_wimask_660, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6539 = eq(out_romask_660, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6540 = eq(out_womask_660, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_561 = or(_out_T_6533, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_561 = cat(UInt<8>(0h24), _out_prepend_T_561) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6541 = or(out_prepend_561, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6542 = bits(_out_T_6541, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_661 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_661 = orr(_out_rimask_T_661) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_661 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_661 = andr(_out_wimask_T_661) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_661 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_661 = orr(_out_romask_T_661) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_661 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_661 = andr(_out_womask_T_661) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_661 = and(out_rivalid_1[539], out_rimask_661) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_661 = and(out_roready_1[539], out_romask_661) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_661 = and(out_wivalid_1[539], out_wimask_661) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_661 = and(out_woready_1[539], out_womask_661) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6543 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6544 = and(out_f_rivalid_661, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6545 = and(UInt<1>(0h1), out_f_roready_661) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6546 = eq(out_rimask_661, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6547 = eq(out_wimask_661, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6548 = eq(out_romask_661, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6549 = eq(out_womask_661, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_562 = or(_out_T_6542, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_562 = cat(UInt<8>(0h80), _out_prepend_T_562) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6550 = or(out_prepend_562, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6551 = bits(_out_T_6550, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_662 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_662 = orr(_out_rimask_T_662) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_662 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_662 = andr(_out_wimask_T_662) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_662 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_662 = orr(_out_romask_T_662) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_662 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_662 = andr(_out_womask_T_662) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_662 = and(out_rivalid_1[540], out_rimask_662) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_662 = and(out_roready_1[540], out_romask_662) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_662 = and(out_wivalid_1[540], out_wimask_662) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_662 = and(out_woready_1[540], out_womask_662) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6552 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6553 = and(out_f_rivalid_662, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6554 = and(UInt<1>(0h1), out_f_roready_662) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6555 = eq(out_rimask_662, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6556 = eq(out_wimask_662, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6557 = eq(out_romask_662, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6558 = eq(out_womask_662, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_563 = or(_out_T_6551, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_563 = cat(UInt<8>(0h10), _out_prepend_T_563) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6559 = or(out_prepend_563, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6560 = bits(_out_T_6559, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_663 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_663 = orr(_out_rimask_T_663) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_663 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_663 = andr(_out_wimask_T_663) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_663 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_663 = orr(_out_romask_T_663) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_663 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_663 = andr(_out_womask_T_663) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_663 = and(out_rivalid_1[541], out_rimask_663) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_663 = and(out_roready_1[541], out_romask_663) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_663 = and(out_wivalid_1[541], out_wimask_663) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_663 = and(out_woready_1[541], out_womask_663) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6561 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6562 = and(out_f_rivalid_663, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6563 = and(UInt<1>(0h1), out_f_roready_663) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6564 = eq(out_rimask_663, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6565 = eq(out_wimask_663, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6566 = eq(out_romask_663, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6567 = eq(out_womask_663, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_564 = or(_out_T_6560, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_564 = cat(UInt<8>(0h73), _out_prepend_T_564) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6568 = or(out_prepend_564, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6569 = bits(_out_T_6568, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_664 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_664 = orr(_out_rimask_T_664) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_664 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_664 = andr(_out_wimask_T_664) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_664 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_664 = orr(_out_romask_T_664) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_664 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_664 = andr(_out_womask_T_664) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_664 = and(out_rivalid_1[542], out_rimask_664) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_664 = and(out_roready_1[542], out_romask_664) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_664 = and(out_wivalid_1[542], out_wimask_664) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_664 = and(out_woready_1[542], out_womask_664) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6570 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6571 = and(out_f_rivalid_664, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6572 = and(UInt<1>(0h1), out_f_roready_664) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6573 = eq(out_rimask_664, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6574 = eq(out_wimask_664, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6575 = eq(out_romask_664, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6576 = eq(out_womask_664, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_565 = or(_out_T_6569, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_565 = cat(UInt<8>(0h24), _out_prepend_T_565) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6577 = or(out_prepend_565, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6578 = bits(_out_T_6577, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_665 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_665 = orr(_out_rimask_T_665) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_665 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_665 = andr(_out_wimask_T_665) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_665 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_665 = orr(_out_romask_T_665) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_665 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_665 = andr(_out_womask_T_665) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_665 = and(out_rivalid_1[543], out_rimask_665) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_665 = and(out_roready_1[543], out_romask_665) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_665 = and(out_wivalid_1[543], out_wimask_665) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_665 = and(out_woready_1[543], out_womask_665) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6579 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6580 = and(out_f_rivalid_665, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6581 = and(UInt<1>(0h1), out_f_roready_665) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6582 = eq(out_rimask_665, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6583 = eq(out_wimask_665, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6584 = eq(out_romask_665, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6585 = eq(out_womask_665, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_566 = or(_out_T_6578, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_566 = cat(UInt<8>(0h20), _out_prepend_T_566) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6586 = or(out_prepend_566, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6587 = bits(_out_T_6586, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_666 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_666 = orr(_out_rimask_T_666) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_666 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_666 = andr(_out_wimask_T_666) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_666 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_666 = orr(_out_romask_T_666) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_666 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_666 = andr(_out_womask_T_666) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_666 = and(out_rivalid_1[544], out_rimask_666) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_666 = and(out_roready_1[544], out_romask_666) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_666 = and(out_wivalid_1[544], out_wimask_666) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_666 = and(out_woready_1[544], out_womask_666) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6588 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6589 = and(out_f_rivalid_666, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6590 = and(UInt<1>(0h1), out_f_roready_666) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6591 = eq(out_rimask_666, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6592 = eq(out_wimask_666, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6593 = eq(out_romask_666, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6594 = eq(out_womask_666, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_567 = or(_out_T_6587, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_567 = cat(UInt<8>(0h7b), _out_prepend_T_567) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6595 = or(out_prepend_567, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6596 = bits(_out_T_6595, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_667 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_667 = orr(_out_rimask_T_667) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_667 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_667 = andr(_out_wimask_T_667) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_667 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_667 = orr(_out_romask_T_667) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_667 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_667 = andr(_out_womask_T_667) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_667 = and(out_rivalid_1[545], out_rimask_667) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_667 = and(out_roready_1[545], out_romask_667) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_667 = and(out_wivalid_1[545], out_wimask_667) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_667 = and(out_woready_1[545], out_womask_667) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6597 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6598 = and(out_f_rivalid_667, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6599 = and(UInt<1>(0h1), out_f_roready_667) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6600 = eq(out_rimask_667, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6601 = eq(out_wimask_667, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6602 = eq(out_romask_667, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6603 = eq(out_womask_667, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6604 = or(_T_706, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6605 = bits(_out_T_6604, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_668 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_668 = orr(_out_rimask_T_668) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_668 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_668 = andr(_out_wimask_T_668) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_668 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_668 = orr(_out_romask_T_668) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_668 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_668 = andr(_out_womask_T_668) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_668 = and(out_rivalid_1[546], out_rimask_668) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_668 = and(out_roready_1[546], out_romask_668) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_668 = and(out_wivalid_1[546], out_wimask_668) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_668 = and(out_woready_1[546], out_womask_668) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6606 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6607 = and(out_f_rivalid_668, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6608 = and(UInt<1>(0h1), out_f_roready_668) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6609 = eq(out_rimask_668, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6610 = eq(out_wimask_668, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6611 = eq(out_romask_668, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6612 = eq(out_womask_668, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_568 = or(_out_T_6605, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_568 = cat(_T_707, _out_prepend_T_568) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6613 = or(out_prepend_568, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6614 = bits(_out_T_6613, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_669 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_669 = orr(_out_rimask_T_669) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_669 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_669 = andr(_out_wimask_T_669) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_669 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_669 = orr(_out_romask_T_669) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_669 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_669 = andr(_out_womask_T_669) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_669 = and(out_rivalid_1[547], out_rimask_669) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_669 = and(out_roready_1[547], out_romask_669) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_669 = and(out_wivalid_1[547], out_wimask_669) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_669 = and(out_woready_1[547], out_womask_669) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6615 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6616 = and(out_f_rivalid_669, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6617 = and(UInt<1>(0h1), out_f_roready_669) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6618 = eq(out_rimask_669, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6619 = eq(out_wimask_669, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6620 = eq(out_romask_669, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6621 = eq(out_womask_669, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_569 = or(_out_T_6614, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_569 = cat(_T_708, _out_prepend_T_569) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6622 = or(out_prepend_569, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6623 = bits(_out_T_6622, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_670 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_670 = orr(_out_rimask_T_670) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_670 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_670 = andr(_out_wimask_T_670) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_670 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_670 = orr(_out_romask_T_670) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_670 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_670 = andr(_out_womask_T_670) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_670 = and(out_rivalid_1[548], out_rimask_670) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_670 = and(out_roready_1[548], out_romask_670) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_670 = and(out_wivalid_1[548], out_wimask_670) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_670 = and(out_woready_1[548], out_womask_670) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6624 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6625 = and(out_f_rivalid_670, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6626 = and(UInt<1>(0h1), out_f_roready_670) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6627 = eq(out_rimask_670, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6628 = eq(out_wimask_670, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6629 = eq(out_romask_670, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6630 = eq(out_womask_670, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_570 = or(_out_T_6623, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_570 = cat(_T_709, _out_prepend_T_570) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6631 = or(out_prepend_570, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6632 = bits(_out_T_6631, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_671 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_671 = orr(_out_rimask_T_671) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_671 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_671 = andr(_out_wimask_T_671) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_671 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_671 = orr(_out_romask_T_671) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_671 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_671 = andr(_out_womask_T_671) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_671 = and(out_rivalid_1[549], out_rimask_671) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_671 = and(out_roready_1[549], out_romask_671) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_671 = and(out_wivalid_1[549], out_wimask_671) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_671 = and(out_woready_1[549], out_womask_671) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6633 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6634 = and(out_f_rivalid_671, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6635 = and(UInt<1>(0h1), out_f_roready_671) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6636 = eq(out_rimask_671, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6637 = eq(out_wimask_671, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6638 = eq(out_romask_671, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6639 = eq(out_womask_671, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_571 = or(_out_T_6632, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_571 = cat(_T_710, _out_prepend_T_571) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6640 = or(out_prepend_571, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6641 = bits(_out_T_6640, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_672 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_672 = orr(_out_rimask_T_672) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_672 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_672 = andr(_out_wimask_T_672) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_672 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_672 = orr(_out_romask_T_672) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_672 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_672 = andr(_out_womask_T_672) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_672 = and(out_rivalid_1[550], out_rimask_672) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_672 = and(out_roready_1[550], out_romask_672) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_672 = and(out_wivalid_1[550], out_wimask_672) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_672 = and(out_woready_1[550], out_womask_672) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6642 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6643 = and(out_f_rivalid_672, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6644 = and(UInt<1>(0h1), out_f_roready_672) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6645 = eq(out_rimask_672, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6646 = eq(out_wimask_672, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6647 = eq(out_romask_672, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6648 = eq(out_womask_672, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_572 = or(_out_T_6641, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_572 = cat(_T_711, _out_prepend_T_572) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6649 = or(out_prepend_572, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6650 = bits(_out_T_6649, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_673 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_673 = orr(_out_rimask_T_673) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_673 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_673 = andr(_out_wimask_T_673) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_673 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_673 = orr(_out_romask_T_673) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_673 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_673 = andr(_out_womask_T_673) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_673 = and(out_rivalid_1[551], out_rimask_673) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_673 = and(out_roready_1[551], out_romask_673) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_673 = and(out_wivalid_1[551], out_wimask_673) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_673 = and(out_woready_1[551], out_womask_673) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6651 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6652 = and(out_f_rivalid_673, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6653 = and(UInt<1>(0h1), out_f_roready_673) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6654 = eq(out_rimask_673, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6655 = eq(out_wimask_673, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6656 = eq(out_romask_673, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6657 = eq(out_womask_673, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_573 = or(_out_T_6650, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_573 = cat(_T_712, _out_prepend_T_573) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6658 = or(out_prepend_573, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6659 = bits(_out_T_6658, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_674 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_674 = orr(_out_rimask_T_674) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_674 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_674 = andr(_out_wimask_T_674) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_674 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_674 = orr(_out_romask_T_674) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_674 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_674 = andr(_out_womask_T_674) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_674 = and(out_rivalid_1[552], out_rimask_674) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_674 = and(out_roready_1[552], out_romask_674) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_674 = and(out_wivalid_1[552], out_wimask_674) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_674 = and(out_woready_1[552], out_womask_674) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6660 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6661 = and(out_f_rivalid_674, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6662 = and(UInt<1>(0h1), out_f_roready_674) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6663 = eq(out_rimask_674, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6664 = eq(out_wimask_674, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6665 = eq(out_romask_674, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6666 = eq(out_womask_674, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_574 = or(_out_T_6659, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_574 = cat(_T_713, _out_prepend_T_574) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6667 = or(out_prepend_574, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6668 = bits(_out_T_6667, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_675 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_675 = orr(_out_rimask_T_675) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_675 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_675 = andr(_out_wimask_T_675) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_675 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_675 = orr(_out_romask_T_675) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_675 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_675 = andr(_out_womask_T_675) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_675 = and(out_rivalid_1[553], out_rimask_675) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_675 = and(out_roready_1[553], out_romask_675) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_675 = and(out_wivalid_1[553], out_wimask_675) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_675 = and(out_woready_1[553], out_womask_675) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6669 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6670 = and(out_f_rivalid_675, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6671 = and(UInt<1>(0h1), out_f_roready_675) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6672 = eq(out_rimask_675, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6673 = eq(out_wimask_675, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6674 = eq(out_romask_675, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6675 = eq(out_womask_675, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6676 = or(_T_858, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6677 = bits(_out_T_6676, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_676 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_676 = orr(_out_rimask_T_676) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_676 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_676 = andr(_out_wimask_T_676) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_676 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_676 = orr(_out_romask_T_676) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_676 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_676 = andr(_out_womask_T_676) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_676 = and(out_rivalid_1[554], out_rimask_676) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_676 = and(out_roready_1[554], out_romask_676) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_676 = and(out_wivalid_1[554], out_wimask_676) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_676 = and(out_woready_1[554], out_womask_676) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6678 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6679 = and(out_f_rivalid_676, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6680 = and(UInt<1>(0h1), out_f_roready_676) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6681 = eq(out_rimask_676, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6682 = eq(out_wimask_676, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6683 = eq(out_romask_676, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6684 = eq(out_womask_676, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_575 = or(_out_T_6677, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_575 = cat(_T_859, _out_prepend_T_575) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6685 = or(out_prepend_575, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6686 = bits(_out_T_6685, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_677 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_677 = orr(_out_rimask_T_677) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_677 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_677 = andr(_out_wimask_T_677) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_677 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_677 = orr(_out_romask_T_677) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_677 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_677 = andr(_out_womask_T_677) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_677 = and(out_rivalid_1[555], out_rimask_677) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_677 = and(out_roready_1[555], out_romask_677) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_677 = and(out_wivalid_1[555], out_wimask_677) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_677 = and(out_woready_1[555], out_womask_677) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6687 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6688 = and(out_f_rivalid_677, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6689 = and(UInt<1>(0h1), out_f_roready_677) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6690 = eq(out_rimask_677, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6691 = eq(out_wimask_677, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6692 = eq(out_romask_677, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6693 = eq(out_womask_677, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_576 = or(_out_T_6686, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_576 = cat(_T_860, _out_prepend_T_576) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6694 = or(out_prepend_576, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6695 = bits(_out_T_6694, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_678 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_678 = orr(_out_rimask_T_678) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_678 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_678 = andr(_out_wimask_T_678) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_678 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_678 = orr(_out_romask_T_678) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_678 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_678 = andr(_out_womask_T_678) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_678 = and(out_rivalid_1[556], out_rimask_678) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_678 = and(out_roready_1[556], out_romask_678) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_678 = and(out_wivalid_1[556], out_wimask_678) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_678 = and(out_woready_1[556], out_womask_678) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6696 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6697 = and(out_f_rivalid_678, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6698 = and(UInt<1>(0h1), out_f_roready_678) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6699 = eq(out_rimask_678, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6700 = eq(out_wimask_678, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6701 = eq(out_romask_678, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6702 = eq(out_womask_678, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_577 = or(_out_T_6695, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_577 = cat(_T_861, _out_prepend_T_577) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6703 = or(out_prepend_577, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6704 = bits(_out_T_6703, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_679 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_679 = orr(_out_rimask_T_679) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_679 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_679 = andr(_out_wimask_T_679) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_679 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_679 = orr(_out_romask_T_679) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_679 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_679 = andr(_out_womask_T_679) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_679 = and(out_rivalid_1[557], out_rimask_679) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_679 = and(out_roready_1[557], out_romask_679) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_679 = and(out_wivalid_1[557], out_wimask_679) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_679 = and(out_woready_1[557], out_womask_679) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6705 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6706 = and(out_f_rivalid_679, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6707 = and(UInt<1>(0h1), out_f_roready_679) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6708 = eq(out_rimask_679, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6709 = eq(out_wimask_679, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6710 = eq(out_romask_679, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6711 = eq(out_womask_679, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_578 = or(_out_T_6704, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_578 = cat(_T_862, _out_prepend_T_578) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6712 = or(out_prepend_578, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6713 = bits(_out_T_6712, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_680 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_680 = orr(_out_rimask_T_680) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_680 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_680 = andr(_out_wimask_T_680) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_680 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_680 = orr(_out_romask_T_680) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_680 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_680 = andr(_out_womask_T_680) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_680 = and(out_rivalid_1[558], out_rimask_680) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_680 = and(out_roready_1[558], out_romask_680) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_680 = and(out_wivalid_1[558], out_wimask_680) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_680 = and(out_woready_1[558], out_womask_680) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6714 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6715 = and(out_f_rivalid_680, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6716 = and(UInt<1>(0h1), out_f_roready_680) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6717 = eq(out_rimask_680, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6718 = eq(out_wimask_680, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6719 = eq(out_romask_680, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6720 = eq(out_womask_680, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_579 = or(_out_T_6713, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_579 = cat(_T_863, _out_prepend_T_579) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6721 = or(out_prepend_579, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6722 = bits(_out_T_6721, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_681 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_681 = orr(_out_rimask_T_681) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_681 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_681 = andr(_out_wimask_T_681) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_681 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_681 = orr(_out_romask_T_681) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_681 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_681 = andr(_out_womask_T_681) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_681 = and(out_rivalid_1[559], out_rimask_681) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_681 = and(out_roready_1[559], out_romask_681) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_681 = and(out_wivalid_1[559], out_wimask_681) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_681 = and(out_woready_1[559], out_womask_681) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6723 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6724 = and(out_f_rivalid_681, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6725 = and(UInt<1>(0h1), out_f_roready_681) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6726 = eq(out_rimask_681, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6727 = eq(out_wimask_681, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6728 = eq(out_romask_681, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6729 = eq(out_womask_681, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_580 = or(_out_T_6722, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_580 = cat(_T_864, _out_prepend_T_580) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6730 = or(out_prepend_580, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6731 = bits(_out_T_6730, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_682 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_682 = orr(_out_rimask_T_682) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_682 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_682 = andr(_out_wimask_T_682) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_682 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_682 = orr(_out_romask_T_682) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_682 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_682 = andr(_out_womask_T_682) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_682 = and(out_rivalid_1[560], out_rimask_682) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_682 = and(out_roready_1[560], out_romask_682) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_682 = and(out_wivalid_1[560], out_wimask_682) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_682 = and(out_woready_1[560], out_womask_682) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6732 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6733 = and(out_f_rivalid_682, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6734 = and(UInt<1>(0h1), out_f_roready_682) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6735 = eq(out_rimask_682, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6736 = eq(out_wimask_682, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6737 = eq(out_romask_682, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6738 = eq(out_womask_682, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_581 = or(_out_T_6731, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_581 = cat(_T_865, _out_prepend_T_581) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6739 = or(out_prepend_581, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6740 = bits(_out_T_6739, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_683 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_683 = orr(_out_rimask_T_683) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_683 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_683 = andr(_out_wimask_T_683) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_683 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_683 = orr(_out_romask_T_683) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_683 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_683 = andr(_out_womask_T_683) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_683 = and(out_rivalid_1[561], out_rimask_683) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_683 = and(out_roready_1[561], out_romask_683) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_683 = and(out_wivalid_1[561], out_wimask_683) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_683 = and(out_woready_1[561], out_womask_683) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6741 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6742 = and(out_f_rivalid_683, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6743 = and(UInt<1>(0h1), out_f_roready_683) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6744 = eq(out_rimask_683, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6745 = eq(out_wimask_683, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6746 = eq(out_romask_683, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6747 = eq(out_womask_683, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6748 = or(_T_610, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6749 = bits(_out_T_6748, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_684 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_684 = orr(_out_rimask_T_684) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_684 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_684 = andr(_out_wimask_T_684) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_684 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_684 = orr(_out_romask_T_684) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_684 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_684 = andr(_out_womask_T_684) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_684 = and(out_rivalid_1[562], out_rimask_684) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_684 = and(out_roready_1[562], out_romask_684) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_684 = and(out_wivalid_1[562], out_wimask_684) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_684 = and(out_woready_1[562], out_womask_684) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6750 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6751 = and(out_f_rivalid_684, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6752 = and(UInt<1>(0h1), out_f_roready_684) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6753 = eq(out_rimask_684, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6754 = eq(out_wimask_684, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6755 = eq(out_romask_684, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6756 = eq(out_womask_684, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_582 = or(_out_T_6749, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_582 = cat(_T_611, _out_prepend_T_582) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6757 = or(out_prepend_582, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6758 = bits(_out_T_6757, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_685 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_685 = orr(_out_rimask_T_685) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_685 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_685 = andr(_out_wimask_T_685) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_685 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_685 = orr(_out_romask_T_685) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_685 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_685 = andr(_out_womask_T_685) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_685 = and(out_rivalid_1[563], out_rimask_685) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_685 = and(out_roready_1[563], out_romask_685) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_685 = and(out_wivalid_1[563], out_wimask_685) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_685 = and(out_woready_1[563], out_womask_685) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6759 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6760 = and(out_f_rivalid_685, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6761 = and(UInt<1>(0h1), out_f_roready_685) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6762 = eq(out_rimask_685, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6763 = eq(out_wimask_685, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6764 = eq(out_romask_685, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6765 = eq(out_womask_685, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_583 = or(_out_T_6758, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_583 = cat(_T_612, _out_prepend_T_583) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6766 = or(out_prepend_583, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6767 = bits(_out_T_6766, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_686 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_686 = orr(_out_rimask_T_686) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_686 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_686 = andr(_out_wimask_T_686) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_686 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_686 = orr(_out_romask_T_686) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_686 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_686 = andr(_out_womask_T_686) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_686 = and(out_rivalid_1[564], out_rimask_686) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_686 = and(out_roready_1[564], out_romask_686) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_686 = and(out_wivalid_1[564], out_wimask_686) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_686 = and(out_woready_1[564], out_womask_686) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6768 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6769 = and(out_f_rivalid_686, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6770 = and(UInt<1>(0h1), out_f_roready_686) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6771 = eq(out_rimask_686, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6772 = eq(out_wimask_686, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6773 = eq(out_romask_686, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6774 = eq(out_womask_686, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_584 = or(_out_T_6767, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_584 = cat(_T_613, _out_prepend_T_584) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6775 = or(out_prepend_584, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6776 = bits(_out_T_6775, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_687 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_687 = orr(_out_rimask_T_687) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_687 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_687 = andr(_out_wimask_T_687) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_687 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_687 = orr(_out_romask_T_687) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_687 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_687 = andr(_out_womask_T_687) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_687 = and(out_rivalid_1[565], out_rimask_687) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_687 = and(out_roready_1[565], out_romask_687) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_687 = and(out_wivalid_1[565], out_wimask_687) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_687 = and(out_woready_1[565], out_womask_687) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6777 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6778 = and(out_f_rivalid_687, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6779 = and(UInt<1>(0h1), out_f_roready_687) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6780 = eq(out_rimask_687, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6781 = eq(out_wimask_687, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6782 = eq(out_romask_687, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6783 = eq(out_womask_687, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_585 = or(_out_T_6776, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_585 = cat(_T_614, _out_prepend_T_585) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6784 = or(out_prepend_585, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6785 = bits(_out_T_6784, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_688 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_688 = orr(_out_rimask_T_688) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_688 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_688 = andr(_out_wimask_T_688) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_688 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_688 = orr(_out_romask_T_688) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_688 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_688 = andr(_out_womask_T_688) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_688 = and(out_rivalid_1[566], out_rimask_688) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_688 = and(out_roready_1[566], out_romask_688) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_688 = and(out_wivalid_1[566], out_wimask_688) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_688 = and(out_woready_1[566], out_womask_688) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6786 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6787 = and(out_f_rivalid_688, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6788 = and(UInt<1>(0h1), out_f_roready_688) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6789 = eq(out_rimask_688, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6790 = eq(out_wimask_688, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6791 = eq(out_romask_688, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6792 = eq(out_womask_688, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_586 = or(_out_T_6785, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_586 = cat(_T_615, _out_prepend_T_586) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6793 = or(out_prepend_586, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6794 = bits(_out_T_6793, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_689 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_689 = orr(_out_rimask_T_689) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_689 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_689 = andr(_out_wimask_T_689) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_689 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_689 = orr(_out_romask_T_689) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_689 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_689 = andr(_out_womask_T_689) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_689 = and(out_rivalid_1[567], out_rimask_689) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_689 = and(out_roready_1[567], out_romask_689) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_689 = and(out_wivalid_1[567], out_wimask_689) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_689 = and(out_woready_1[567], out_womask_689) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6795 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6796 = and(out_f_rivalid_689, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6797 = and(UInt<1>(0h1), out_f_roready_689) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6798 = eq(out_rimask_689, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6799 = eq(out_wimask_689, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6800 = eq(out_romask_689, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6801 = eq(out_womask_689, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_587 = or(_out_T_6794, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_587 = cat(_T_616, _out_prepend_T_587) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6802 = or(out_prepend_587, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6803 = bits(_out_T_6802, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_690 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_690 = orr(_out_rimask_T_690) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_690 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_690 = andr(_out_wimask_T_690) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_690 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_690 = orr(_out_romask_T_690) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_690 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_690 = andr(_out_womask_T_690) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_690 = and(out_rivalid_1[568], out_rimask_690) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_690 = and(out_roready_1[568], out_romask_690) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_690 = and(out_wivalid_1[568], out_wimask_690) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_690 = and(out_woready_1[568], out_womask_690) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6804 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6805 = and(out_f_rivalid_690, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6806 = and(UInt<1>(0h1), out_f_roready_690) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6807 = eq(out_rimask_690, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6808 = eq(out_wimask_690, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6809 = eq(out_romask_690, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6810 = eq(out_womask_690, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_588 = or(_out_T_6803, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_588 = cat(_T_617, _out_prepend_T_588) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6811 = or(out_prepend_588, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6812 = bits(_out_T_6811, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_691 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_691 = orr(_out_rimask_T_691) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_691 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_691 = andr(_out_wimask_T_691) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_691 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_691 = orr(_out_romask_T_691) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_691 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_691 = andr(_out_womask_T_691) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_691 = and(out_rivalid_1[569], out_rimask_691) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_691 = and(out_roready_1[569], out_romask_691) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_691 = and(out_wivalid_1[569], out_wimask_691) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_691 = and(out_woready_1[569], out_womask_691) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6813 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6814 = and(out_f_rivalid_691, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6815 = and(UInt<1>(0h1), out_f_roready_691) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6816 = eq(out_rimask_691, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6817 = eq(out_wimask_691, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6818 = eq(out_romask_691, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6819 = eq(out_womask_691, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6820 = or(_T_826, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6821 = bits(_out_T_6820, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_692 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_692 = orr(_out_rimask_T_692) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_692 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_692 = andr(_out_wimask_T_692) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_692 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_692 = orr(_out_romask_T_692) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_692 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_692 = andr(_out_womask_T_692) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_692 = and(out_rivalid_1[570], out_rimask_692) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_692 = and(out_roready_1[570], out_romask_692) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_692 = and(out_wivalid_1[570], out_wimask_692) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_692 = and(out_woready_1[570], out_womask_692) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6822 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6823 = and(out_f_rivalid_692, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6824 = and(UInt<1>(0h1), out_f_roready_692) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6825 = eq(out_rimask_692, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6826 = eq(out_wimask_692, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6827 = eq(out_romask_692, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6828 = eq(out_womask_692, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_589 = or(_out_T_6821, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_589 = cat(_T_827, _out_prepend_T_589) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6829 = or(out_prepend_589, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6830 = bits(_out_T_6829, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_693 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_693 = orr(_out_rimask_T_693) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_693 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_693 = andr(_out_wimask_T_693) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_693 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_693 = orr(_out_romask_T_693) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_693 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_693 = andr(_out_womask_T_693) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_693 = and(out_rivalid_1[571], out_rimask_693) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_693 = and(out_roready_1[571], out_romask_693) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_693 = and(out_wivalid_1[571], out_wimask_693) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_693 = and(out_woready_1[571], out_womask_693) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6831 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6832 = and(out_f_rivalid_693, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6833 = and(UInt<1>(0h1), out_f_roready_693) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6834 = eq(out_rimask_693, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6835 = eq(out_wimask_693, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6836 = eq(out_romask_693, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6837 = eq(out_womask_693, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_590 = or(_out_T_6830, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_590 = cat(_T_828, _out_prepend_T_590) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6838 = or(out_prepend_590, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6839 = bits(_out_T_6838, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_694 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_694 = orr(_out_rimask_T_694) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_694 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_694 = andr(_out_wimask_T_694) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_694 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_694 = orr(_out_romask_T_694) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_694 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_694 = andr(_out_womask_T_694) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_694 = and(out_rivalid_1[572], out_rimask_694) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_694 = and(out_roready_1[572], out_romask_694) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_694 = and(out_wivalid_1[572], out_wimask_694) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_694 = and(out_woready_1[572], out_womask_694) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6840 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6841 = and(out_f_rivalid_694, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6842 = and(UInt<1>(0h1), out_f_roready_694) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6843 = eq(out_rimask_694, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6844 = eq(out_wimask_694, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6845 = eq(out_romask_694, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6846 = eq(out_womask_694, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_591 = or(_out_T_6839, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_591 = cat(_T_829, _out_prepend_T_591) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6847 = or(out_prepend_591, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6848 = bits(_out_T_6847, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_695 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_695 = orr(_out_rimask_T_695) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_695 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_695 = andr(_out_wimask_T_695) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_695 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_695 = orr(_out_romask_T_695) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_695 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_695 = andr(_out_womask_T_695) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_695 = and(out_rivalid_1[573], out_rimask_695) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_695 = and(out_roready_1[573], out_romask_695) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_695 = and(out_wivalid_1[573], out_wimask_695) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_695 = and(out_woready_1[573], out_womask_695) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6849 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6850 = and(out_f_rivalid_695, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6851 = and(UInt<1>(0h1), out_f_roready_695) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6852 = eq(out_rimask_695, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6853 = eq(out_wimask_695, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6854 = eq(out_romask_695, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6855 = eq(out_womask_695, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_592 = or(_out_T_6848, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_592 = cat(_T_830, _out_prepend_T_592) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6856 = or(out_prepend_592, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6857 = bits(_out_T_6856, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_696 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_696 = orr(_out_rimask_T_696) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_696 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_696 = andr(_out_wimask_T_696) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_696 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_696 = orr(_out_romask_T_696) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_696 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_696 = andr(_out_womask_T_696) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_696 = and(out_rivalid_1[574], out_rimask_696) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_696 = and(out_roready_1[574], out_romask_696) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_696 = and(out_wivalid_1[574], out_wimask_696) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_696 = and(out_woready_1[574], out_womask_696) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6858 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6859 = and(out_f_rivalid_696, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6860 = and(UInt<1>(0h1), out_f_roready_696) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6861 = eq(out_rimask_696, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6862 = eq(out_wimask_696, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6863 = eq(out_romask_696, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6864 = eq(out_womask_696, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_593 = or(_out_T_6857, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_593 = cat(_T_831, _out_prepend_T_593) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6865 = or(out_prepend_593, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6866 = bits(_out_T_6865, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_697 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_697 = orr(_out_rimask_T_697) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_697 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_697 = andr(_out_wimask_T_697) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_697 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_697 = orr(_out_romask_T_697) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_697 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_697 = andr(_out_womask_T_697) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_697 = and(out_rivalid_1[575], out_rimask_697) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_697 = and(out_roready_1[575], out_romask_697) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_697 = and(out_wivalid_1[575], out_wimask_697) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_697 = and(out_woready_1[575], out_womask_697) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6867 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6868 = and(out_f_rivalid_697, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6869 = and(UInt<1>(0h1), out_f_roready_697) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6870 = eq(out_rimask_697, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6871 = eq(out_wimask_697, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6872 = eq(out_romask_697, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6873 = eq(out_womask_697, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_594 = or(_out_T_6866, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_594 = cat(_T_832, _out_prepend_T_594) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6874 = or(out_prepend_594, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6875 = bits(_out_T_6874, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_698 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_698 = orr(_out_rimask_T_698) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_698 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_698 = andr(_out_wimask_T_698) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_698 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_698 = orr(_out_romask_T_698) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_698 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_698 = andr(_out_womask_T_698) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_698 = and(out_rivalid_1[576], out_rimask_698) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_698 = and(out_roready_1[576], out_romask_698) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_698 = and(out_wivalid_1[576], out_wimask_698) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_698 = and(out_woready_1[576], out_womask_698) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6876 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6877 = and(out_f_rivalid_698, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6878 = and(UInt<1>(0h1), out_f_roready_698) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6879 = eq(out_rimask_698, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6880 = eq(out_wimask_698, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6881 = eq(out_romask_698, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6882 = eq(out_womask_698, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_595 = or(_out_T_6875, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_595 = cat(_T_833, _out_prepend_T_595) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6883 = or(out_prepend_595, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6884 = bits(_out_T_6883, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_699 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_699 = orr(_out_rimask_T_699) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_699 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_699 = andr(_out_wimask_T_699) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_699 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_699 = orr(_out_romask_T_699) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_699 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_699 = andr(_out_womask_T_699) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_699 = and(out_rivalid_1[577], out_rimask_699) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_699 = and(out_roready_1[577], out_romask_699) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_699 = and(out_wivalid_1[577], out_wimask_699) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_699 = and(out_woready_1[577], out_womask_699) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6885 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6886 = and(out_f_rivalid_699, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6887 = and(UInt<1>(0h1), out_f_roready_699) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6888 = eq(out_rimask_699, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6889 = eq(out_wimask_699, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6890 = eq(out_romask_699, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6891 = eq(out_womask_699, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6892 = or(_T_946, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6893 = bits(_out_T_6892, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_700 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_700 = orr(_out_rimask_T_700) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_700 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_700 = andr(_out_wimask_T_700) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_700 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_700 = orr(_out_romask_T_700) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_700 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_700 = andr(_out_womask_T_700) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_700 = and(out_rivalid_1[578], out_rimask_700) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_700 = and(out_roready_1[578], out_romask_700) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_700 = and(out_wivalid_1[578], out_wimask_700) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_700 = and(out_woready_1[578], out_womask_700) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6894 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6895 = and(out_f_rivalid_700, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6896 = and(UInt<1>(0h1), out_f_roready_700) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6897 = eq(out_rimask_700, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6898 = eq(out_wimask_700, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6899 = eq(out_romask_700, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6900 = eq(out_womask_700, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_596 = or(_out_T_6893, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_596 = cat(_T_947, _out_prepend_T_596) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6901 = or(out_prepend_596, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6902 = bits(_out_T_6901, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_701 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_701 = orr(_out_rimask_T_701) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_701 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_701 = andr(_out_wimask_T_701) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_701 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_701 = orr(_out_romask_T_701) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_701 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_701 = andr(_out_womask_T_701) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_701 = and(out_rivalid_1[579], out_rimask_701) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_701 = and(out_roready_1[579], out_romask_701) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_701 = and(out_wivalid_1[579], out_wimask_701) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_701 = and(out_woready_1[579], out_womask_701) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6903 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6904 = and(out_f_rivalid_701, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6905 = and(UInt<1>(0h1), out_f_roready_701) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6906 = eq(out_rimask_701, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6907 = eq(out_wimask_701, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6908 = eq(out_romask_701, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6909 = eq(out_womask_701, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_597 = or(_out_T_6902, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_597 = cat(_T_948, _out_prepend_T_597) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6910 = or(out_prepend_597, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6911 = bits(_out_T_6910, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_702 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_702 = orr(_out_rimask_T_702) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_702 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_702 = andr(_out_wimask_T_702) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_702 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_702 = orr(_out_romask_T_702) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_702 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_702 = andr(_out_womask_T_702) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_702 = and(out_rivalid_1[580], out_rimask_702) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_702 = and(out_roready_1[580], out_romask_702) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_702 = and(out_wivalid_1[580], out_wimask_702) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_702 = and(out_woready_1[580], out_womask_702) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6912 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6913 = and(out_f_rivalid_702, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6914 = and(UInt<1>(0h1), out_f_roready_702) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6915 = eq(out_rimask_702, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6916 = eq(out_wimask_702, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6917 = eq(out_romask_702, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6918 = eq(out_womask_702, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_598 = or(_out_T_6911, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_598 = cat(_T_949, _out_prepend_T_598) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6919 = or(out_prepend_598, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6920 = bits(_out_T_6919, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_703 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_703 = orr(_out_rimask_T_703) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_703 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_703 = andr(_out_wimask_T_703) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_703 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_703 = orr(_out_romask_T_703) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_703 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_703 = andr(_out_womask_T_703) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_703 = and(out_rivalid_1[581], out_rimask_703) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_703 = and(out_roready_1[581], out_romask_703) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_703 = and(out_wivalid_1[581], out_wimask_703) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_703 = and(out_woready_1[581], out_womask_703) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6921 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6922 = and(out_f_rivalid_703, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6923 = and(UInt<1>(0h1), out_f_roready_703) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6924 = eq(out_rimask_703, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6925 = eq(out_wimask_703, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6926 = eq(out_romask_703, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6927 = eq(out_womask_703, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_599 = or(_out_T_6920, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_599 = cat(_T_950, _out_prepend_T_599) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6928 = or(out_prepend_599, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6929 = bits(_out_T_6928, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_704 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_704 = orr(_out_rimask_T_704) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_704 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_704 = andr(_out_wimask_T_704) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_704 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_704 = orr(_out_romask_T_704) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_704 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_704 = andr(_out_womask_T_704) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_704 = and(out_rivalid_1[582], out_rimask_704) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_704 = and(out_roready_1[582], out_romask_704) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_704 = and(out_wivalid_1[582], out_wimask_704) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_704 = and(out_woready_1[582], out_womask_704) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6930 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6931 = and(out_f_rivalid_704, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6932 = and(UInt<1>(0h1), out_f_roready_704) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6933 = eq(out_rimask_704, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6934 = eq(out_wimask_704, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6935 = eq(out_romask_704, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6936 = eq(out_womask_704, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_600 = or(_out_T_6929, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_600 = cat(_T_951, _out_prepend_T_600) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6937 = or(out_prepend_600, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6938 = bits(_out_T_6937, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_705 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_705 = orr(_out_rimask_T_705) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_705 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_705 = andr(_out_wimask_T_705) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_705 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_705 = orr(_out_romask_T_705) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_705 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_705 = andr(_out_womask_T_705) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_705 = and(out_rivalid_1[583], out_rimask_705) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_705 = and(out_roready_1[583], out_romask_705) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_705 = and(out_wivalid_1[583], out_wimask_705) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_705 = and(out_woready_1[583], out_womask_705) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6939 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6940 = and(out_f_rivalid_705, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6941 = and(UInt<1>(0h1), out_f_roready_705) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6942 = eq(out_rimask_705, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6943 = eq(out_wimask_705, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6944 = eq(out_romask_705, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6945 = eq(out_womask_705, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_601 = or(_out_T_6938, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_601 = cat(_T_952, _out_prepend_T_601) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6946 = or(out_prepend_601, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6947 = bits(_out_T_6946, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_706 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_706 = orr(_out_rimask_T_706) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_706 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_706 = andr(_out_wimask_T_706) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_706 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_706 = orr(_out_romask_T_706) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_706 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_706 = andr(_out_womask_T_706) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_706 = and(out_rivalid_1[584], out_rimask_706) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_706 = and(out_roready_1[584], out_romask_706) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_706 = and(out_wivalid_1[584], out_wimask_706) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_706 = and(out_woready_1[584], out_womask_706) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6948 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6949 = and(out_f_rivalid_706, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6950 = and(UInt<1>(0h1), out_f_roready_706) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6951 = eq(out_rimask_706, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6952 = eq(out_wimask_706, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6953 = eq(out_romask_706, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6954 = eq(out_womask_706, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_602 = or(_out_T_6947, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_602 = cat(_T_953, _out_prepend_T_602) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6955 = or(out_prepend_602, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6956 = bits(_out_T_6955, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_707 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_707 = orr(_out_rimask_T_707) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_707 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_707 = andr(_out_wimask_T_707) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_707 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_707 = orr(_out_romask_T_707) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_707 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_707 = andr(_out_womask_T_707) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_707 = and(out_rivalid_1[585], out_rimask_707) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_707 = and(out_roready_1[585], out_romask_707) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_707 = and(out_wivalid_1[585], out_wimask_707) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_707 = and(out_woready_1[585], out_womask_707) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6957 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6958 = and(out_f_rivalid_707, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6959 = and(UInt<1>(0h1), out_f_roready_707) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6960 = eq(out_rimask_707, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6961 = eq(out_wimask_707, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6962 = eq(out_romask_707, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6963 = eq(out_womask_707, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6964 = or(_T_1050, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6965 = bits(_out_T_6964, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_708 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_708 = orr(_out_rimask_T_708) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_708 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_708 = andr(_out_wimask_T_708) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_708 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_708 = orr(_out_romask_T_708) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_708 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_708 = andr(_out_womask_T_708) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_708 = and(out_rivalid_1[586], out_rimask_708) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_708 = and(out_roready_1[586], out_romask_708) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_708 = and(out_wivalid_1[586], out_wimask_708) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_708 = and(out_woready_1[586], out_womask_708) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6966 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6967 = and(out_f_rivalid_708, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6968 = and(UInt<1>(0h1), out_f_roready_708) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6969 = eq(out_rimask_708, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6970 = eq(out_wimask_708, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6971 = eq(out_romask_708, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6972 = eq(out_womask_708, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_603 = or(_out_T_6965, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_603 = cat(_T_1051, _out_prepend_T_603) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6973 = or(out_prepend_603, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6974 = bits(_out_T_6973, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_709 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_709 = orr(_out_rimask_T_709) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_709 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_709 = andr(_out_wimask_T_709) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_709 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_709 = orr(_out_romask_T_709) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_709 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_709 = andr(_out_womask_T_709) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_709 = and(out_rivalid_1[587], out_rimask_709) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_709 = and(out_roready_1[587], out_romask_709) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_709 = and(out_wivalid_1[587], out_wimask_709) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_709 = and(out_woready_1[587], out_womask_709) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6975 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6976 = and(out_f_rivalid_709, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6977 = and(UInt<1>(0h1), out_f_roready_709) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6978 = eq(out_rimask_709, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6979 = eq(out_wimask_709, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6980 = eq(out_romask_709, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6981 = eq(out_womask_709, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_604 = or(_out_T_6974, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_604 = cat(_T_1052, _out_prepend_T_604) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6982 = or(out_prepend_604, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6983 = bits(_out_T_6982, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_710 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_710 = orr(_out_rimask_T_710) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_710 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_710 = andr(_out_wimask_T_710) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_710 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_710 = orr(_out_romask_T_710) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_710 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_710 = andr(_out_womask_T_710) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_710 = and(out_rivalid_1[588], out_rimask_710) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_710 = and(out_roready_1[588], out_romask_710) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_710 = and(out_wivalid_1[588], out_wimask_710) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_710 = and(out_woready_1[588], out_womask_710) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6984 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6985 = and(out_f_rivalid_710, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6986 = and(UInt<1>(0h1), out_f_roready_710) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6987 = eq(out_rimask_710, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6988 = eq(out_wimask_710, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6989 = eq(out_romask_710, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6990 = eq(out_womask_710, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_605 = or(_out_T_6983, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_605 = cat(_T_1053, _out_prepend_T_605) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6991 = or(out_prepend_605, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6992 = bits(_out_T_6991, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_711 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_711 = orr(_out_rimask_T_711) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_711 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_711 = andr(_out_wimask_T_711) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_711 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_711 = orr(_out_romask_T_711) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_711 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_711 = andr(_out_womask_T_711) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_711 = and(out_rivalid_1[589], out_rimask_711) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_711 = and(out_roready_1[589], out_romask_711) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_711 = and(out_wivalid_1[589], out_wimask_711) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_711 = and(out_woready_1[589], out_womask_711) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6993 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6994 = and(out_f_rivalid_711, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6995 = and(UInt<1>(0h1), out_f_roready_711) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6996 = eq(out_rimask_711, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6997 = eq(out_wimask_711, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6998 = eq(out_romask_711, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6999 = eq(out_womask_711, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_606 = or(_out_T_6992, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_606 = cat(_T_1054, _out_prepend_T_606) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7000 = or(out_prepend_606, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7001 = bits(_out_T_7000, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_712 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_712 = orr(_out_rimask_T_712) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_712 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_712 = andr(_out_wimask_T_712) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_712 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_712 = orr(_out_romask_T_712) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_712 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_712 = andr(_out_womask_T_712) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_712 = and(out_rivalid_1[590], out_rimask_712) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_712 = and(out_roready_1[590], out_romask_712) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_712 = and(out_wivalid_1[590], out_wimask_712) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_712 = and(out_woready_1[590], out_womask_712) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7002 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7003 = and(out_f_rivalid_712, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7004 = and(UInt<1>(0h1), out_f_roready_712) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7005 = eq(out_rimask_712, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7006 = eq(out_wimask_712, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7007 = eq(out_romask_712, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7008 = eq(out_womask_712, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_607 = or(_out_T_7001, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_607 = cat(_T_1055, _out_prepend_T_607) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7009 = or(out_prepend_607, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7010 = bits(_out_T_7009, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_713 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_713 = orr(_out_rimask_T_713) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_713 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_713 = andr(_out_wimask_T_713) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_713 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_713 = orr(_out_romask_T_713) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_713 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_713 = andr(_out_womask_T_713) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_713 = and(out_rivalid_1[591], out_rimask_713) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_713 = and(out_roready_1[591], out_romask_713) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_713 = and(out_wivalid_1[591], out_wimask_713) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_713 = and(out_woready_1[591], out_womask_713) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7011 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7012 = and(out_f_rivalid_713, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7013 = and(UInt<1>(0h1), out_f_roready_713) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7014 = eq(out_rimask_713, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7015 = eq(out_wimask_713, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7016 = eq(out_romask_713, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7017 = eq(out_womask_713, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_608 = or(_out_T_7010, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_608 = cat(_T_1056, _out_prepend_T_608) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7018 = or(out_prepend_608, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7019 = bits(_out_T_7018, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_714 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_714 = orr(_out_rimask_T_714) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_714 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_714 = andr(_out_wimask_T_714) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_714 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_714 = orr(_out_romask_T_714) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_714 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_714 = andr(_out_womask_T_714) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_714 = and(out_rivalid_1[592], out_rimask_714) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_714 = and(out_roready_1[592], out_romask_714) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_714 = and(out_wivalid_1[592], out_wimask_714) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_714 = and(out_woready_1[592], out_womask_714) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7020 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7021 = and(out_f_rivalid_714, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7022 = and(UInt<1>(0h1), out_f_roready_714) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7023 = eq(out_rimask_714, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7024 = eq(out_wimask_714, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7025 = eq(out_romask_714, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7026 = eq(out_womask_714, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_609 = or(_out_T_7019, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_609 = cat(_T_1057, _out_prepend_T_609) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7027 = or(out_prepend_609, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7028 = bits(_out_T_7027, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_715 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_715 = orr(_out_rimask_T_715) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_715 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_715 = andr(_out_wimask_T_715) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_715 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_715 = orr(_out_romask_T_715) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_715 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_715 = andr(_out_womask_T_715) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_715 = and(out_rivalid_1[593], out_rimask_715) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_715 = and(out_roready_1[593], out_romask_715) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_715 = and(out_wivalid_1[593], out_wimask_715) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_715 = and(out_woready_1[593], out_womask_715) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7029 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7030 = and(out_f_rivalid_715, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7031 = and(UInt<1>(0h1), out_f_roready_715) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7032 = eq(out_rimask_715, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7033 = eq(out_wimask_715, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7034 = eq(out_romask_715, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7035 = eq(out_womask_715, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7036 = or(UInt<8>(0h23), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7037 = bits(_out_T_7036, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_716 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_716 = orr(_out_rimask_T_716) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_716 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_716 = andr(_out_wimask_T_716) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_716 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_716 = orr(_out_romask_T_716) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_716 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_716 = andr(_out_womask_T_716) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_716 = and(out_rivalid_1[594], out_rimask_716) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_716 = and(out_roready_1[594], out_romask_716) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_716 = and(out_wivalid_1[594], out_wimask_716) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_716 = and(out_woready_1[594], out_womask_716) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7038 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7039 = and(out_f_rivalid_716, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7040 = and(UInt<1>(0h1), out_f_roready_716) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7041 = eq(out_rimask_716, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7042 = eq(out_wimask_716, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7043 = eq(out_romask_716, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7044 = eq(out_womask_716, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_610 = or(_out_T_7037, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_610 = cat(UInt<8>(0h20), _out_prepend_T_610) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7045 = or(out_prepend_610, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7046 = bits(_out_T_7045, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_717 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_717 = orr(_out_rimask_T_717) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_717 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_717 = andr(_out_wimask_T_717) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_717 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_717 = orr(_out_romask_T_717) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_717 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_717 = andr(_out_womask_T_717) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_717 = and(out_rivalid_1[595], out_rimask_717) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_717 = and(out_roready_1[595], out_romask_717) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_717 = and(out_wivalid_1[595], out_wimask_717) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_717 = and(out_woready_1[595], out_womask_717) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7047 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7048 = and(out_f_rivalid_717, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7049 = and(UInt<1>(0h1), out_f_roready_717) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7050 = eq(out_rimask_717, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7051 = eq(out_wimask_717, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7052 = eq(out_romask_717, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7053 = eq(out_womask_717, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_611 = or(_out_T_7046, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_611 = cat(UInt<8>(0h80), _out_prepend_T_611) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7054 = or(out_prepend_611, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7055 = bits(_out_T_7054, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_718 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_718 = orr(_out_rimask_T_718) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_718 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_718 = andr(_out_wimask_T_718) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_718 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_718 = orr(_out_romask_T_718) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_718 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_718 = andr(_out_womask_T_718) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_718 = and(out_rivalid_1[596], out_rimask_718) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_718 = and(out_roready_1[596], out_romask_718) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_718 = and(out_wivalid_1[596], out_wimask_718) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_718 = and(out_woready_1[596], out_womask_718) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7056 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7057 = and(out_f_rivalid_718, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7058 = and(UInt<1>(0h1), out_f_roready_718) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7059 = eq(out_rimask_718, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7060 = eq(out_wimask_718, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7061 = eq(out_romask_718, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7062 = eq(out_womask_718, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_612 = or(_out_T_7055, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_612 = cat(UInt<8>(0h10), _out_prepend_T_612) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7063 = or(out_prepend_612, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7064 = bits(_out_T_7063, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_719 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_719 = orr(_out_rimask_T_719) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_719 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_719 = andr(_out_wimask_T_719) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_719 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_719 = orr(_out_romask_T_719) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_719 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_719 = andr(_out_womask_T_719) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_719 = and(out_rivalid_1[597], out_rimask_719) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_719 = and(out_roready_1[597], out_romask_719) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_719 = and(out_wivalid_1[597], out_wimask_719) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_719 = and(out_woready_1[597], out_womask_719) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7065 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7066 = and(out_f_rivalid_719, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7067 = and(UInt<1>(0h1), out_f_roready_719) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7068 = eq(out_rimask_719, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7069 = eq(out_wimask_719, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7070 = eq(out_romask_719, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7071 = eq(out_womask_719, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_613 = or(_out_T_7064, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_613 = cat(UInt<8>(0h3), _out_prepend_T_613) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7072 = or(out_prepend_613, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7073 = bits(_out_T_7072, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_720 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_720 = orr(_out_rimask_T_720) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_720 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_720 = andr(_out_wimask_T_720) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_720 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_720 = orr(_out_romask_T_720) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_720 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_720 = andr(_out_womask_T_720) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_720 = and(out_rivalid_1[598], out_rimask_720) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_720 = and(out_roready_1[598], out_romask_720) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_720 = and(out_wivalid_1[598], out_wimask_720) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_720 = and(out_woready_1[598], out_womask_720) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7074 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7075 = and(out_f_rivalid_720, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7076 = and(UInt<1>(0h1), out_f_roready_720) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7077 = eq(out_rimask_720, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7078 = eq(out_wimask_720, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7079 = eq(out_romask_720, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7080 = eq(out_womask_720, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_614 = or(_out_T_7073, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_614 = cat(UInt<8>(0h44), _out_prepend_T_614) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7081 = or(out_prepend_614, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7082 = bits(_out_T_7081, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_721 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_721 = orr(_out_rimask_T_721) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_721 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_721 = andr(_out_wimask_T_721) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_721 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_721 = orr(_out_romask_T_721) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_721 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_721 = andr(_out_womask_T_721) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_721 = and(out_rivalid_1[599], out_rimask_721) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_721 = and(out_roready_1[599], out_romask_721) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_721 = and(out_wivalid_1[599], out_wimask_721) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_721 = and(out_woready_1[599], out_womask_721) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7083 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7084 = and(out_f_rivalid_721, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7085 = and(UInt<1>(0h1), out_f_roready_721) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7086 = eq(out_rimask_721, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7087 = eq(out_wimask_721, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7088 = eq(out_romask_721, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7089 = eq(out_womask_721, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_615 = or(_out_T_7082, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_615 = cat(UInt<8>(0h4), _out_prepend_T_615) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7090 = or(out_prepend_615, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7091 = bits(_out_T_7090, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_722 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_722 = orr(_out_rimask_T_722) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_722 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_722 = andr(_out_wimask_T_722) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_722 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_722 = orr(_out_romask_T_722) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_722 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_722 = andr(_out_womask_T_722) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_722 = and(out_rivalid_1[600], out_rimask_722) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_722 = and(out_roready_1[600], out_romask_722) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_722 = and(out_wivalid_1[600], out_wimask_722) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_722 = and(out_woready_1[600], out_womask_722) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7092 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7093 = and(out_f_rivalid_722, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7094 = and(UInt<1>(0h1), out_f_roready_722) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7095 = eq(out_rimask_722, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7096 = eq(out_wimask_722, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7097 = eq(out_romask_722, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7098 = eq(out_womask_722, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_616 = or(_out_T_7091, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_616 = cat(UInt<8>(0h40), _out_prepend_T_616) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7099 = or(out_prepend_616, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7100 = bits(_out_T_7099, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_723 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_723 = orr(_out_rimask_T_723) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_723 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_723 = andr(_out_wimask_T_723) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_723 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_723 = orr(_out_romask_T_723) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_723 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_723 = andr(_out_womask_T_723) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_723 = and(out_rivalid_1[601], out_rimask_723) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_723 = and(out_roready_1[601], out_romask_723) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_723 = and(out_wivalid_1[601], out_wimask_723) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_723 = and(out_woready_1[601], out_womask_723) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7101 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7102 = and(out_f_rivalid_723, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7103 = and(UInt<1>(0h1), out_f_roready_723) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7104 = eq(out_rimask_723, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7105 = eq(out_wimask_723, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7106 = eq(out_romask_723, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7107 = eq(out_womask_723, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7108 = or(_T_570, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7109 = bits(_out_T_7108, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_724 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_724 = orr(_out_rimask_T_724) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_724 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_724 = andr(_out_wimask_T_724) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_724 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_724 = orr(_out_romask_T_724) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_724 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_724 = andr(_out_womask_T_724) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_724 = and(out_rivalid_1[602], out_rimask_724) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_724 = and(out_roready_1[602], out_romask_724) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_724 = and(out_wivalid_1[602], out_wimask_724) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_724 = and(out_woready_1[602], out_womask_724) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7110 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7111 = and(out_f_rivalid_724, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7112 = and(UInt<1>(0h1), out_f_roready_724) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7113 = eq(out_rimask_724, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7114 = eq(out_wimask_724, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7115 = eq(out_romask_724, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7116 = eq(out_womask_724, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_617 = or(_out_T_7109, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_617 = cat(_T_571, _out_prepend_T_617) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7117 = or(out_prepend_617, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7118 = bits(_out_T_7117, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_725 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_725 = orr(_out_rimask_T_725) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_725 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_725 = andr(_out_wimask_T_725) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_725 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_725 = orr(_out_romask_T_725) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_725 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_725 = andr(_out_womask_T_725) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_725 = and(out_rivalid_1[603], out_rimask_725) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_725 = and(out_roready_1[603], out_romask_725) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_725 = and(out_wivalid_1[603], out_wimask_725) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_725 = and(out_woready_1[603], out_womask_725) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7119 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7120 = and(out_f_rivalid_725, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7121 = and(UInt<1>(0h1), out_f_roready_725) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7122 = eq(out_rimask_725, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7123 = eq(out_wimask_725, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7124 = eq(out_romask_725, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7125 = eq(out_womask_725, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_618 = or(_out_T_7118, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_618 = cat(_T_572, _out_prepend_T_618) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7126 = or(out_prepend_618, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7127 = bits(_out_T_7126, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_726 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_726 = orr(_out_rimask_T_726) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_726 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_726 = andr(_out_wimask_T_726) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_726 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_726 = orr(_out_romask_T_726) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_726 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_726 = andr(_out_womask_T_726) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_726 = and(out_rivalid_1[604], out_rimask_726) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_726 = and(out_roready_1[604], out_romask_726) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_726 = and(out_wivalid_1[604], out_wimask_726) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_726 = and(out_woready_1[604], out_womask_726) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7128 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7129 = and(out_f_rivalid_726, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7130 = and(UInt<1>(0h1), out_f_roready_726) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7131 = eq(out_rimask_726, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7132 = eq(out_wimask_726, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7133 = eq(out_romask_726, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7134 = eq(out_womask_726, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_619 = or(_out_T_7127, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_619 = cat(_T_573, _out_prepend_T_619) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7135 = or(out_prepend_619, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7136 = bits(_out_T_7135, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_727 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_727 = orr(_out_rimask_T_727) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_727 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_727 = andr(_out_wimask_T_727) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_727 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_727 = orr(_out_romask_T_727) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_727 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_727 = andr(_out_womask_T_727) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_727 = and(out_rivalid_1[605], out_rimask_727) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_727 = and(out_roready_1[605], out_romask_727) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_727 = and(out_wivalid_1[605], out_wimask_727) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_727 = and(out_woready_1[605], out_womask_727) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7137 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7138 = and(out_f_rivalid_727, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7139 = and(UInt<1>(0h1), out_f_roready_727) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7140 = eq(out_rimask_727, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7141 = eq(out_wimask_727, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7142 = eq(out_romask_727, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7143 = eq(out_womask_727, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_620 = or(_out_T_7136, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_620 = cat(_T_574, _out_prepend_T_620) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7144 = or(out_prepend_620, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7145 = bits(_out_T_7144, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_728 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_728 = orr(_out_rimask_T_728) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_728 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_728 = andr(_out_wimask_T_728) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_728 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_728 = orr(_out_romask_T_728) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_728 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_728 = andr(_out_womask_T_728) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_728 = and(out_rivalid_1[606], out_rimask_728) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_728 = and(out_roready_1[606], out_romask_728) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_728 = and(out_wivalid_1[606], out_wimask_728) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_728 = and(out_woready_1[606], out_womask_728) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7146 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7147 = and(out_f_rivalid_728, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7148 = and(UInt<1>(0h1), out_f_roready_728) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7149 = eq(out_rimask_728, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7150 = eq(out_wimask_728, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7151 = eq(out_romask_728, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7152 = eq(out_womask_728, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_621 = or(_out_T_7145, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_621 = cat(_T_575, _out_prepend_T_621) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7153 = or(out_prepend_621, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7154 = bits(_out_T_7153, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_729 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_729 = orr(_out_rimask_T_729) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_729 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_729 = andr(_out_wimask_T_729) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_729 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_729 = orr(_out_romask_T_729) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_729 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_729 = andr(_out_womask_T_729) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_729 = and(out_rivalid_1[607], out_rimask_729) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_729 = and(out_roready_1[607], out_romask_729) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_729 = and(out_wivalid_1[607], out_wimask_729) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_729 = and(out_woready_1[607], out_womask_729) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7155 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7156 = and(out_f_rivalid_729, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7157 = and(UInt<1>(0h1), out_f_roready_729) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7158 = eq(out_rimask_729, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7159 = eq(out_wimask_729, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7160 = eq(out_romask_729, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7161 = eq(out_womask_729, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_622 = or(_out_T_7154, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_622 = cat(_T_576, _out_prepend_T_622) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7162 = or(out_prepend_622, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7163 = bits(_out_T_7162, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_730 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_730 = orr(_out_rimask_T_730) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_730 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_730 = andr(_out_wimask_T_730) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_730 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_730 = orr(_out_romask_T_730) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_730 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_730 = andr(_out_womask_T_730) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_730 = and(out_rivalid_1[608], out_rimask_730) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_730 = and(out_roready_1[608], out_romask_730) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_730 = and(out_wivalid_1[608], out_wimask_730) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_730 = and(out_woready_1[608], out_womask_730) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7164 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7165 = and(out_f_rivalid_730, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7166 = and(UInt<1>(0h1), out_f_roready_730) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7167 = eq(out_rimask_730, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7168 = eq(out_wimask_730, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7169 = eq(out_romask_730, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7170 = eq(out_womask_730, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_623 = or(_out_T_7163, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_623 = cat(_T_577, _out_prepend_T_623) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7171 = or(out_prepend_623, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7172 = bits(_out_T_7171, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_731 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_731 = orr(_out_rimask_T_731) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_731 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_731 = andr(_out_wimask_T_731) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_731 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_731 = orr(_out_romask_T_731) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_731 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_731 = andr(_out_womask_T_731) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_731 = and(out_rivalid_1[609], out_rimask_731) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_731 = and(out_roready_1[609], out_romask_731) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_731 = and(out_wivalid_1[609], out_wimask_731) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_731 = and(out_woready_1[609], out_womask_731) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7173 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7174 = and(out_f_rivalid_731, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7175 = and(UInt<1>(0h1), out_f_roready_731) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7176 = eq(out_rimask_731, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7177 = eq(out_wimask_731, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7178 = eq(out_romask_731, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7179 = eq(out_womask_731, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7180 = or(_T_1306, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7181 = bits(_out_T_7180, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_732 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_732 = orr(_out_rimask_T_732) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_732 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_732 = andr(_out_wimask_T_732) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_732 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_732 = orr(_out_romask_T_732) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_732 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_732 = andr(_out_womask_T_732) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_732 = and(out_rivalid_1[610], out_rimask_732) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_732 = and(out_roready_1[610], out_romask_732) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_732 = and(out_wivalid_1[610], out_wimask_732) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_732 = and(out_woready_1[610], out_womask_732) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7182 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7183 = and(out_f_rivalid_732, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7184 = and(UInt<1>(0h1), out_f_roready_732) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7185 = eq(out_rimask_732, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7186 = eq(out_wimask_732, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7187 = eq(out_romask_732, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7188 = eq(out_womask_732, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_624 = or(_out_T_7181, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_624 = cat(_T_1307, _out_prepend_T_624) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7189 = or(out_prepend_624, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7190 = bits(_out_T_7189, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_733 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_733 = orr(_out_rimask_T_733) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_733 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_733 = andr(_out_wimask_T_733) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_733 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_733 = orr(_out_romask_T_733) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_733 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_733 = andr(_out_womask_T_733) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_733 = and(out_rivalid_1[611], out_rimask_733) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_733 = and(out_roready_1[611], out_romask_733) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_733 = and(out_wivalid_1[611], out_wimask_733) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_733 = and(out_woready_1[611], out_womask_733) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7191 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7192 = and(out_f_rivalid_733, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7193 = and(UInt<1>(0h1), out_f_roready_733) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7194 = eq(out_rimask_733, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7195 = eq(out_wimask_733, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7196 = eq(out_romask_733, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7197 = eq(out_womask_733, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_625 = or(_out_T_7190, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_625 = cat(_T_1308, _out_prepend_T_625) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7198 = or(out_prepend_625, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7199 = bits(_out_T_7198, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_734 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_734 = orr(_out_rimask_T_734) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_734 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_734 = andr(_out_wimask_T_734) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_734 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_734 = orr(_out_romask_T_734) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_734 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_734 = andr(_out_womask_T_734) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_734 = and(out_rivalid_1[612], out_rimask_734) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_734 = and(out_roready_1[612], out_romask_734) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_734 = and(out_wivalid_1[612], out_wimask_734) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_734 = and(out_woready_1[612], out_womask_734) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7200 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7201 = and(out_f_rivalid_734, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7202 = and(UInt<1>(0h1), out_f_roready_734) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7203 = eq(out_rimask_734, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7204 = eq(out_wimask_734, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7205 = eq(out_romask_734, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7206 = eq(out_womask_734, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_626 = or(_out_T_7199, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_626 = cat(_T_1309, _out_prepend_T_626) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7207 = or(out_prepend_626, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7208 = bits(_out_T_7207, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_735 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_735 = orr(_out_rimask_T_735) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_735 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_735 = andr(_out_wimask_T_735) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_735 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_735 = orr(_out_romask_T_735) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_735 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_735 = andr(_out_womask_T_735) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_735 = and(out_rivalid_1[613], out_rimask_735) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_735 = and(out_roready_1[613], out_romask_735) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_735 = and(out_wivalid_1[613], out_wimask_735) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_735 = and(out_woready_1[613], out_womask_735) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7209 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7210 = and(out_f_rivalid_735, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7211 = and(UInt<1>(0h1), out_f_roready_735) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7212 = eq(out_rimask_735, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7213 = eq(out_wimask_735, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7214 = eq(out_romask_735, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7215 = eq(out_womask_735, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_627 = or(_out_T_7208, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_627 = cat(_T_1310, _out_prepend_T_627) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7216 = or(out_prepend_627, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7217 = bits(_out_T_7216, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_736 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_736 = orr(_out_rimask_T_736) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_736 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_736 = andr(_out_wimask_T_736) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_736 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_736 = orr(_out_romask_T_736) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_736 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_736 = andr(_out_womask_T_736) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_736 = and(out_rivalid_1[614], out_rimask_736) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_736 = and(out_roready_1[614], out_romask_736) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_736 = and(out_wivalid_1[614], out_wimask_736) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_736 = and(out_woready_1[614], out_womask_736) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7218 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7219 = and(out_f_rivalid_736, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7220 = and(UInt<1>(0h1), out_f_roready_736) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7221 = eq(out_rimask_736, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7222 = eq(out_wimask_736, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7223 = eq(out_romask_736, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7224 = eq(out_womask_736, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_628 = or(_out_T_7217, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_628 = cat(_T_1311, _out_prepend_T_628) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7225 = or(out_prepend_628, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7226 = bits(_out_T_7225, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_737 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_737 = orr(_out_rimask_T_737) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_737 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_737 = andr(_out_wimask_T_737) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_737 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_737 = orr(_out_romask_T_737) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_737 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_737 = andr(_out_womask_T_737) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_737 = and(out_rivalid_1[615], out_rimask_737) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_737 = and(out_roready_1[615], out_romask_737) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_737 = and(out_wivalid_1[615], out_wimask_737) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_737 = and(out_woready_1[615], out_womask_737) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7227 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7228 = and(out_f_rivalid_737, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7229 = and(UInt<1>(0h1), out_f_roready_737) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7230 = eq(out_rimask_737, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7231 = eq(out_wimask_737, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7232 = eq(out_romask_737, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7233 = eq(out_womask_737, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_629 = or(_out_T_7226, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_629 = cat(_T_1312, _out_prepend_T_629) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7234 = or(out_prepend_629, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7235 = bits(_out_T_7234, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_738 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_738 = orr(_out_rimask_T_738) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_738 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_738 = andr(_out_wimask_T_738) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_738 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_738 = orr(_out_romask_T_738) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_738 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_738 = andr(_out_womask_T_738) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_738 = and(out_rivalid_1[616], out_rimask_738) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_738 = and(out_roready_1[616], out_romask_738) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_738 = and(out_wivalid_1[616], out_wimask_738) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_738 = and(out_woready_1[616], out_womask_738) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7236 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7237 = and(out_f_rivalid_738, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7238 = and(UInt<1>(0h1), out_f_roready_738) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7239 = eq(out_rimask_738, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7240 = eq(out_wimask_738, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7241 = eq(out_romask_738, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7242 = eq(out_womask_738, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_630 = or(_out_T_7235, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_630 = cat(_T_1313, _out_prepend_T_630) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7243 = or(out_prepend_630, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7244 = bits(_out_T_7243, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_739 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_739 = orr(_out_rimask_T_739) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_739 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_739 = andr(_out_wimask_T_739) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_739 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_739 = orr(_out_romask_T_739) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_739 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_739 = andr(_out_womask_T_739) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_739 = and(out_rivalid_1[617], out_rimask_739) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_739 = and(out_roready_1[617], out_romask_739) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_739 = and(out_wivalid_1[617], out_wimask_739) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_739 = and(out_woready_1[617], out_womask_739) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7245 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7246 = and(out_f_rivalid_739, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7247 = and(UInt<1>(0h1), out_f_roready_739) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7248 = eq(out_rimask_739, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7249 = eq(out_wimask_739, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7250 = eq(out_romask_739, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7251 = eq(out_womask_739, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7252 = or(_T_866, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7253 = bits(_out_T_7252, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_740 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_740 = orr(_out_rimask_T_740) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_740 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_740 = andr(_out_wimask_T_740) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_740 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_740 = orr(_out_romask_T_740) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_740 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_740 = andr(_out_womask_T_740) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_740 = and(out_rivalid_1[618], out_rimask_740) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_740 = and(out_roready_1[618], out_romask_740) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_740 = and(out_wivalid_1[618], out_wimask_740) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_740 = and(out_woready_1[618], out_womask_740) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7254 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7255 = and(out_f_rivalid_740, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7256 = and(UInt<1>(0h1), out_f_roready_740) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7257 = eq(out_rimask_740, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7258 = eq(out_wimask_740, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7259 = eq(out_romask_740, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7260 = eq(out_womask_740, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_631 = or(_out_T_7253, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_631 = cat(_T_867, _out_prepend_T_631) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7261 = or(out_prepend_631, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7262 = bits(_out_T_7261, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_741 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_741 = orr(_out_rimask_T_741) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_741 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_741 = andr(_out_wimask_T_741) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_741 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_741 = orr(_out_romask_T_741) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_741 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_741 = andr(_out_womask_T_741) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_741 = and(out_rivalid_1[619], out_rimask_741) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_741 = and(out_roready_1[619], out_romask_741) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_741 = and(out_wivalid_1[619], out_wimask_741) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_741 = and(out_woready_1[619], out_womask_741) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7263 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7264 = and(out_f_rivalid_741, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7265 = and(UInt<1>(0h1), out_f_roready_741) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7266 = eq(out_rimask_741, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7267 = eq(out_wimask_741, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7268 = eq(out_romask_741, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7269 = eq(out_womask_741, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_632 = or(_out_T_7262, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_632 = cat(_T_868, _out_prepend_T_632) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7270 = or(out_prepend_632, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7271 = bits(_out_T_7270, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_742 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_742 = orr(_out_rimask_T_742) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_742 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_742 = andr(_out_wimask_T_742) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_742 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_742 = orr(_out_romask_T_742) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_742 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_742 = andr(_out_womask_T_742) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_742 = and(out_rivalid_1[620], out_rimask_742) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_742 = and(out_roready_1[620], out_romask_742) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_742 = and(out_wivalid_1[620], out_wimask_742) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_742 = and(out_woready_1[620], out_womask_742) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7272 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7273 = and(out_f_rivalid_742, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7274 = and(UInt<1>(0h1), out_f_roready_742) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7275 = eq(out_rimask_742, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7276 = eq(out_wimask_742, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7277 = eq(out_romask_742, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7278 = eq(out_womask_742, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_633 = or(_out_T_7271, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_633 = cat(_T_869, _out_prepend_T_633) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7279 = or(out_prepend_633, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7280 = bits(_out_T_7279, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_743 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_743 = orr(_out_rimask_T_743) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_743 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_743 = andr(_out_wimask_T_743) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_743 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_743 = orr(_out_romask_T_743) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_743 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_743 = andr(_out_womask_T_743) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_743 = and(out_rivalid_1[621], out_rimask_743) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_743 = and(out_roready_1[621], out_romask_743) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_743 = and(out_wivalid_1[621], out_wimask_743) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_743 = and(out_woready_1[621], out_womask_743) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7281 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7282 = and(out_f_rivalid_743, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7283 = and(UInt<1>(0h1), out_f_roready_743) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7284 = eq(out_rimask_743, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7285 = eq(out_wimask_743, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7286 = eq(out_romask_743, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7287 = eq(out_womask_743, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_634 = or(_out_T_7280, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_634 = cat(_T_870, _out_prepend_T_634) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7288 = or(out_prepend_634, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7289 = bits(_out_T_7288, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_744 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_744 = orr(_out_rimask_T_744) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_744 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_744 = andr(_out_wimask_T_744) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_744 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_744 = orr(_out_romask_T_744) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_744 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_744 = andr(_out_womask_T_744) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_744 = and(out_rivalid_1[622], out_rimask_744) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_744 = and(out_roready_1[622], out_romask_744) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_744 = and(out_wivalid_1[622], out_wimask_744) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_744 = and(out_woready_1[622], out_womask_744) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7290 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7291 = and(out_f_rivalid_744, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7292 = and(UInt<1>(0h1), out_f_roready_744) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7293 = eq(out_rimask_744, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7294 = eq(out_wimask_744, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7295 = eq(out_romask_744, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7296 = eq(out_womask_744, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_635 = or(_out_T_7289, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_635 = cat(_T_871, _out_prepend_T_635) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7297 = or(out_prepend_635, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7298 = bits(_out_T_7297, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_745 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_745 = orr(_out_rimask_T_745) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_745 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_745 = andr(_out_wimask_T_745) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_745 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_745 = orr(_out_romask_T_745) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_745 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_745 = andr(_out_womask_T_745) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_745 = and(out_rivalid_1[623], out_rimask_745) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_745 = and(out_roready_1[623], out_romask_745) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_745 = and(out_wivalid_1[623], out_wimask_745) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_745 = and(out_woready_1[623], out_womask_745) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7299 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7300 = and(out_f_rivalid_745, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7301 = and(UInt<1>(0h1), out_f_roready_745) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7302 = eq(out_rimask_745, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7303 = eq(out_wimask_745, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7304 = eq(out_romask_745, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7305 = eq(out_womask_745, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_636 = or(_out_T_7298, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_636 = cat(_T_872, _out_prepend_T_636) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7306 = or(out_prepend_636, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7307 = bits(_out_T_7306, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_746 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_746 = orr(_out_rimask_T_746) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_746 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_746 = andr(_out_wimask_T_746) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_746 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_746 = orr(_out_romask_T_746) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_746 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_746 = andr(_out_womask_T_746) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_746 = and(out_rivalid_1[624], out_rimask_746) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_746 = and(out_roready_1[624], out_romask_746) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_746 = and(out_wivalid_1[624], out_wimask_746) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_746 = and(out_woready_1[624], out_womask_746) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7308 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7309 = and(out_f_rivalid_746, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7310 = and(UInt<1>(0h1), out_f_roready_746) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7311 = eq(out_rimask_746, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7312 = eq(out_wimask_746, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7313 = eq(out_romask_746, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7314 = eq(out_womask_746, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_637 = or(_out_T_7307, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_637 = cat(_T_873, _out_prepend_T_637) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7315 = or(out_prepend_637, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7316 = bits(_out_T_7315, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_747 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_747 = orr(_out_rimask_T_747) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_747 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_747 = andr(_out_wimask_T_747) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_747 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_747 = orr(_out_romask_T_747) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_747 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_747 = andr(_out_womask_T_747) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_747 = and(out_rivalid_1[625], out_rimask_747) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_747 = and(out_roready_1[625], out_romask_747) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_747 = and(out_wivalid_1[625], out_wimask_747) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_747 = and(out_woready_1[625], out_womask_747) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7317 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7318 = and(out_f_rivalid_747, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7319 = and(UInt<1>(0h1), out_f_roready_747) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7320 = eq(out_rimask_747, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7321 = eq(out_wimask_747, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7322 = eq(out_romask_747, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7323 = eq(out_womask_747, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7324 = or(_T_690, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7325 = bits(_out_T_7324, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_748 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_748 = orr(_out_rimask_T_748) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_748 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_748 = andr(_out_wimask_T_748) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_748 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_748 = orr(_out_romask_T_748) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_748 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_748 = andr(_out_womask_T_748) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_748 = and(out_rivalid_1[626], out_rimask_748) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_748 = and(out_roready_1[626], out_romask_748) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_748 = and(out_wivalid_1[626], out_wimask_748) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_748 = and(out_woready_1[626], out_womask_748) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7326 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7327 = and(out_f_rivalid_748, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7328 = and(UInt<1>(0h1), out_f_roready_748) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7329 = eq(out_rimask_748, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7330 = eq(out_wimask_748, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7331 = eq(out_romask_748, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7332 = eq(out_womask_748, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_638 = or(_out_T_7325, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_638 = cat(_T_691, _out_prepend_T_638) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7333 = or(out_prepend_638, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7334 = bits(_out_T_7333, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_749 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_749 = orr(_out_rimask_T_749) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_749 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_749 = andr(_out_wimask_T_749) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_749 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_749 = orr(_out_romask_T_749) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_749 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_749 = andr(_out_womask_T_749) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_749 = and(out_rivalid_1[627], out_rimask_749) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_749 = and(out_roready_1[627], out_romask_749) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_749 = and(out_wivalid_1[627], out_wimask_749) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_749 = and(out_woready_1[627], out_womask_749) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7335 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7336 = and(out_f_rivalid_749, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7337 = and(UInt<1>(0h1), out_f_roready_749) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7338 = eq(out_rimask_749, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7339 = eq(out_wimask_749, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7340 = eq(out_romask_749, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7341 = eq(out_womask_749, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_639 = or(_out_T_7334, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_639 = cat(_T_692, _out_prepend_T_639) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7342 = or(out_prepend_639, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7343 = bits(_out_T_7342, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_750 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_750 = orr(_out_rimask_T_750) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_750 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_750 = andr(_out_wimask_T_750) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_750 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_750 = orr(_out_romask_T_750) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_750 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_750 = andr(_out_womask_T_750) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_750 = and(out_rivalid_1[628], out_rimask_750) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_750 = and(out_roready_1[628], out_romask_750) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_750 = and(out_wivalid_1[628], out_wimask_750) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_750 = and(out_woready_1[628], out_womask_750) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7344 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7345 = and(out_f_rivalid_750, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7346 = and(UInt<1>(0h1), out_f_roready_750) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7347 = eq(out_rimask_750, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7348 = eq(out_wimask_750, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7349 = eq(out_romask_750, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7350 = eq(out_womask_750, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_640 = or(_out_T_7343, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_640 = cat(_T_693, _out_prepend_T_640) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7351 = or(out_prepend_640, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7352 = bits(_out_T_7351, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_751 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_751 = orr(_out_rimask_T_751) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_751 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_751 = andr(_out_wimask_T_751) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_751 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_751 = orr(_out_romask_T_751) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_751 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_751 = andr(_out_womask_T_751) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_751 = and(out_rivalid_1[629], out_rimask_751) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_751 = and(out_roready_1[629], out_romask_751) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_751 = and(out_wivalid_1[629], out_wimask_751) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_751 = and(out_woready_1[629], out_womask_751) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7353 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7354 = and(out_f_rivalid_751, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7355 = and(UInt<1>(0h1), out_f_roready_751) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7356 = eq(out_rimask_751, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7357 = eq(out_wimask_751, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7358 = eq(out_romask_751, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7359 = eq(out_womask_751, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_641 = or(_out_T_7352, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_641 = cat(_T_694, _out_prepend_T_641) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7360 = or(out_prepend_641, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7361 = bits(_out_T_7360, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_752 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_752 = orr(_out_rimask_T_752) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_752 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_752 = andr(_out_wimask_T_752) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_752 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_752 = orr(_out_romask_T_752) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_752 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_752 = andr(_out_womask_T_752) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_752 = and(out_rivalid_1[630], out_rimask_752) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_752 = and(out_roready_1[630], out_romask_752) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_752 = and(out_wivalid_1[630], out_wimask_752) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_752 = and(out_woready_1[630], out_womask_752) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7362 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7363 = and(out_f_rivalid_752, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7364 = and(UInt<1>(0h1), out_f_roready_752) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7365 = eq(out_rimask_752, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7366 = eq(out_wimask_752, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7367 = eq(out_romask_752, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7368 = eq(out_womask_752, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_642 = or(_out_T_7361, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_642 = cat(_T_695, _out_prepend_T_642) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7369 = or(out_prepend_642, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7370 = bits(_out_T_7369, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_753 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_753 = orr(_out_rimask_T_753) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_753 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_753 = andr(_out_wimask_T_753) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_753 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_753 = orr(_out_romask_T_753) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_753 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_753 = andr(_out_womask_T_753) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_753 = and(out_rivalid_1[631], out_rimask_753) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_753 = and(out_roready_1[631], out_romask_753) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_753 = and(out_wivalid_1[631], out_wimask_753) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_753 = and(out_woready_1[631], out_womask_753) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7371 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7372 = and(out_f_rivalid_753, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7373 = and(UInt<1>(0h1), out_f_roready_753) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7374 = eq(out_rimask_753, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7375 = eq(out_wimask_753, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7376 = eq(out_romask_753, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7377 = eq(out_womask_753, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_643 = or(_out_T_7370, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_643 = cat(_T_696, _out_prepend_T_643) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7378 = or(out_prepend_643, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7379 = bits(_out_T_7378, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_754 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_754 = orr(_out_rimask_T_754) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_754 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_754 = andr(_out_wimask_T_754) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_754 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_754 = orr(_out_romask_T_754) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_754 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_754 = andr(_out_womask_T_754) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_754 = and(out_rivalid_1[632], out_rimask_754) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_754 = and(out_roready_1[632], out_romask_754) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_754 = and(out_wivalid_1[632], out_wimask_754) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_754 = and(out_woready_1[632], out_womask_754) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7380 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7381 = and(out_f_rivalid_754, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7382 = and(UInt<1>(0h1), out_f_roready_754) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7383 = eq(out_rimask_754, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7384 = eq(out_wimask_754, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7385 = eq(out_romask_754, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7386 = eq(out_womask_754, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_644 = or(_out_T_7379, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_644 = cat(_T_697, _out_prepend_T_644) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7387 = or(out_prepend_644, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7388 = bits(_out_T_7387, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_755 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_755 = orr(_out_rimask_T_755) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_755 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_755 = andr(_out_wimask_T_755) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_755 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_755 = orr(_out_romask_T_755) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_755 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_755 = andr(_out_womask_T_755) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_755 = and(out_rivalid_1[633], out_rimask_755) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_755 = and(out_roready_1[633], out_romask_755) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_755 = and(out_wivalid_1[633], out_wimask_755) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_755 = and(out_woready_1[633], out_womask_755) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7389 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7390 = and(out_f_rivalid_755, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7391 = and(UInt<1>(0h1), out_f_roready_755) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7392 = eq(out_rimask_755, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7393 = eq(out_wimask_755, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7394 = eq(out_romask_755, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7395 = eq(out_womask_755, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7396 = or(_T_914, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7397 = bits(_out_T_7396, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_756 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_756 = orr(_out_rimask_T_756) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_756 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_756 = andr(_out_wimask_T_756) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_756 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_756 = orr(_out_romask_T_756) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_756 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_756 = andr(_out_womask_T_756) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_756 = and(out_rivalid_1[634], out_rimask_756) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_756 = and(out_roready_1[634], out_romask_756) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_756 = and(out_wivalid_1[634], out_wimask_756) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_756 = and(out_woready_1[634], out_womask_756) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7398 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7399 = and(out_f_rivalid_756, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7400 = and(UInt<1>(0h1), out_f_roready_756) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7401 = eq(out_rimask_756, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7402 = eq(out_wimask_756, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7403 = eq(out_romask_756, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7404 = eq(out_womask_756, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_645 = or(_out_T_7397, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_645 = cat(_T_915, _out_prepend_T_645) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7405 = or(out_prepend_645, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7406 = bits(_out_T_7405, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_757 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_757 = orr(_out_rimask_T_757) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_757 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_757 = andr(_out_wimask_T_757) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_757 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_757 = orr(_out_romask_T_757) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_757 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_757 = andr(_out_womask_T_757) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_757 = and(out_rivalid_1[635], out_rimask_757) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_757 = and(out_roready_1[635], out_romask_757) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_757 = and(out_wivalid_1[635], out_wimask_757) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_757 = and(out_woready_1[635], out_womask_757) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7407 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7408 = and(out_f_rivalid_757, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7409 = and(UInt<1>(0h1), out_f_roready_757) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7410 = eq(out_rimask_757, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7411 = eq(out_wimask_757, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7412 = eq(out_romask_757, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7413 = eq(out_womask_757, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_646 = or(_out_T_7406, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_646 = cat(_T_916, _out_prepend_T_646) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7414 = or(out_prepend_646, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7415 = bits(_out_T_7414, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_758 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_758 = orr(_out_rimask_T_758) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_758 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_758 = andr(_out_wimask_T_758) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_758 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_758 = orr(_out_romask_T_758) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_758 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_758 = andr(_out_womask_T_758) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_758 = and(out_rivalid_1[636], out_rimask_758) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_758 = and(out_roready_1[636], out_romask_758) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_758 = and(out_wivalid_1[636], out_wimask_758) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_758 = and(out_woready_1[636], out_womask_758) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7416 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7417 = and(out_f_rivalid_758, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7418 = and(UInt<1>(0h1), out_f_roready_758) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7419 = eq(out_rimask_758, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7420 = eq(out_wimask_758, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7421 = eq(out_romask_758, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7422 = eq(out_womask_758, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_647 = or(_out_T_7415, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_647 = cat(_T_917, _out_prepend_T_647) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7423 = or(out_prepend_647, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7424 = bits(_out_T_7423, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_759 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_759 = orr(_out_rimask_T_759) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_759 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_759 = andr(_out_wimask_T_759) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_759 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_759 = orr(_out_romask_T_759) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_759 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_759 = andr(_out_womask_T_759) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_759 = and(out_rivalid_1[637], out_rimask_759) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_759 = and(out_roready_1[637], out_romask_759) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_759 = and(out_wivalid_1[637], out_wimask_759) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_759 = and(out_woready_1[637], out_womask_759) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7425 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7426 = and(out_f_rivalid_759, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7427 = and(UInt<1>(0h1), out_f_roready_759) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7428 = eq(out_rimask_759, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7429 = eq(out_wimask_759, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7430 = eq(out_romask_759, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7431 = eq(out_womask_759, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_648 = or(_out_T_7424, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_648 = cat(_T_918, _out_prepend_T_648) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7432 = or(out_prepend_648, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7433 = bits(_out_T_7432, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_760 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_760 = orr(_out_rimask_T_760) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_760 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_760 = andr(_out_wimask_T_760) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_760 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_760 = orr(_out_romask_T_760) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_760 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_760 = andr(_out_womask_T_760) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_760 = and(out_rivalid_1[638], out_rimask_760) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_760 = and(out_roready_1[638], out_romask_760) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_760 = and(out_wivalid_1[638], out_wimask_760) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_760 = and(out_woready_1[638], out_womask_760) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7434 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7435 = and(out_f_rivalid_760, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7436 = and(UInt<1>(0h1), out_f_roready_760) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7437 = eq(out_rimask_760, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7438 = eq(out_wimask_760, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7439 = eq(out_romask_760, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7440 = eq(out_womask_760, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_649 = or(_out_T_7433, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_649 = cat(_T_919, _out_prepend_T_649) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7441 = or(out_prepend_649, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7442 = bits(_out_T_7441, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_761 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_761 = orr(_out_rimask_T_761) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_761 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_761 = andr(_out_wimask_T_761) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_761 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_761 = orr(_out_romask_T_761) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_761 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_761 = andr(_out_womask_T_761) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_761 = and(out_rivalid_1[639], out_rimask_761) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_761 = and(out_roready_1[639], out_romask_761) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_761 = and(out_wivalid_1[639], out_wimask_761) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_761 = and(out_woready_1[639], out_womask_761) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7443 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7444 = and(out_f_rivalid_761, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7445 = and(UInt<1>(0h1), out_f_roready_761) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7446 = eq(out_rimask_761, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7447 = eq(out_wimask_761, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7448 = eq(out_romask_761, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7449 = eq(out_womask_761, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_650 = or(_out_T_7442, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_650 = cat(_T_920, _out_prepend_T_650) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7450 = or(out_prepend_650, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7451 = bits(_out_T_7450, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_762 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_762 = orr(_out_rimask_T_762) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_762 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_762 = andr(_out_wimask_T_762) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_762 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_762 = orr(_out_romask_T_762) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_762 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_762 = andr(_out_womask_T_762) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_762 = and(out_rivalid_1[640], out_rimask_762) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_762 = and(out_roready_1[640], out_romask_762) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_762 = and(out_wivalid_1[640], out_wimask_762) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_762 = and(out_woready_1[640], out_womask_762) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7452 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7453 = and(out_f_rivalid_762, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7454 = and(UInt<1>(0h1), out_f_roready_762) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7455 = eq(out_rimask_762, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7456 = eq(out_wimask_762, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7457 = eq(out_romask_762, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7458 = eq(out_womask_762, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_651 = or(_out_T_7451, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_651 = cat(_T_921, _out_prepend_T_651) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7459 = or(out_prepend_651, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7460 = bits(_out_T_7459, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_763 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_763 = orr(_out_rimask_T_763) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_763 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_763 = andr(_out_wimask_T_763) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_763 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_763 = orr(_out_romask_T_763) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_763 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_763 = andr(_out_womask_T_763) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_763 = and(out_rivalid_1[641], out_rimask_763) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_763 = and(out_roready_1[641], out_romask_763) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_763 = and(out_wivalid_1[641], out_wimask_763) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_763 = and(out_woready_1[641], out_womask_763) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7461 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7462 = and(out_f_rivalid_763, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7463 = and(UInt<1>(0h1), out_f_roready_763) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7464 = eq(out_rimask_763, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7465 = eq(out_wimask_763, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7466 = eq(out_romask_763, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7467 = eq(out_womask_763, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7468 = or(_T_794, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7469 = bits(_out_T_7468, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_764 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_764 = orr(_out_rimask_T_764) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_764 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_764 = andr(_out_wimask_T_764) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_764 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_764 = orr(_out_romask_T_764) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_764 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_764 = andr(_out_womask_T_764) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_764 = and(out_rivalid_1[642], out_rimask_764) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_764 = and(out_roready_1[642], out_romask_764) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_764 = and(out_wivalid_1[642], out_wimask_764) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_764 = and(out_woready_1[642], out_womask_764) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7470 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7471 = and(out_f_rivalid_764, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7472 = and(UInt<1>(0h1), out_f_roready_764) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7473 = eq(out_rimask_764, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7474 = eq(out_wimask_764, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7475 = eq(out_romask_764, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7476 = eq(out_womask_764, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_652 = or(_out_T_7469, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_652 = cat(_T_795, _out_prepend_T_652) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7477 = or(out_prepend_652, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7478 = bits(_out_T_7477, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_765 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_765 = orr(_out_rimask_T_765) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_765 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_765 = andr(_out_wimask_T_765) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_765 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_765 = orr(_out_romask_T_765) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_765 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_765 = andr(_out_womask_T_765) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_765 = and(out_rivalid_1[643], out_rimask_765) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_765 = and(out_roready_1[643], out_romask_765) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_765 = and(out_wivalid_1[643], out_wimask_765) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_765 = and(out_woready_1[643], out_womask_765) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7479 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7480 = and(out_f_rivalid_765, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7481 = and(UInt<1>(0h1), out_f_roready_765) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7482 = eq(out_rimask_765, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7483 = eq(out_wimask_765, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7484 = eq(out_romask_765, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7485 = eq(out_womask_765, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_653 = or(_out_T_7478, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_653 = cat(_T_796, _out_prepend_T_653) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7486 = or(out_prepend_653, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7487 = bits(_out_T_7486, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_766 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_766 = orr(_out_rimask_T_766) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_766 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_766 = andr(_out_wimask_T_766) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_766 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_766 = orr(_out_romask_T_766) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_766 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_766 = andr(_out_womask_T_766) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_766 = and(out_rivalid_1[644], out_rimask_766) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_766 = and(out_roready_1[644], out_romask_766) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_766 = and(out_wivalid_1[644], out_wimask_766) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_766 = and(out_woready_1[644], out_womask_766) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7488 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7489 = and(out_f_rivalid_766, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7490 = and(UInt<1>(0h1), out_f_roready_766) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7491 = eq(out_rimask_766, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7492 = eq(out_wimask_766, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7493 = eq(out_romask_766, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7494 = eq(out_womask_766, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_654 = or(_out_T_7487, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_654 = cat(_T_797, _out_prepend_T_654) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7495 = or(out_prepend_654, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7496 = bits(_out_T_7495, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_767 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_767 = orr(_out_rimask_T_767) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_767 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_767 = andr(_out_wimask_T_767) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_767 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_767 = orr(_out_romask_T_767) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_767 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_767 = andr(_out_womask_T_767) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_767 = and(out_rivalid_1[645], out_rimask_767) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_767 = and(out_roready_1[645], out_romask_767) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_767 = and(out_wivalid_1[645], out_wimask_767) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_767 = and(out_woready_1[645], out_womask_767) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7497 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7498 = and(out_f_rivalid_767, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7499 = and(UInt<1>(0h1), out_f_roready_767) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7500 = eq(out_rimask_767, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7501 = eq(out_wimask_767, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7502 = eq(out_romask_767, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7503 = eq(out_womask_767, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_655 = or(_out_T_7496, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_655 = cat(_T_798, _out_prepend_T_655) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7504 = or(out_prepend_655, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7505 = bits(_out_T_7504, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_768 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_768 = orr(_out_rimask_T_768) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_768 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_768 = andr(_out_wimask_T_768) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_768 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_768 = orr(_out_romask_T_768) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_768 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_768 = andr(_out_womask_T_768) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_768 = and(out_rivalid_1[646], out_rimask_768) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_768 = and(out_roready_1[646], out_romask_768) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_768 = and(out_wivalid_1[646], out_wimask_768) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_768 = and(out_woready_1[646], out_womask_768) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7506 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7507 = and(out_f_rivalid_768, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7508 = and(UInt<1>(0h1), out_f_roready_768) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7509 = eq(out_rimask_768, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7510 = eq(out_wimask_768, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7511 = eq(out_romask_768, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7512 = eq(out_womask_768, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_656 = or(_out_T_7505, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_656 = cat(_T_799, _out_prepend_T_656) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7513 = or(out_prepend_656, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7514 = bits(_out_T_7513, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_769 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_769 = orr(_out_rimask_T_769) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_769 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_769 = andr(_out_wimask_T_769) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_769 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_769 = orr(_out_romask_T_769) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_769 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_769 = andr(_out_womask_T_769) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_769 = and(out_rivalid_1[647], out_rimask_769) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_769 = and(out_roready_1[647], out_romask_769) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_769 = and(out_wivalid_1[647], out_wimask_769) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_769 = and(out_woready_1[647], out_womask_769) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7515 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7516 = and(out_f_rivalid_769, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7517 = and(UInt<1>(0h1), out_f_roready_769) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7518 = eq(out_rimask_769, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7519 = eq(out_wimask_769, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7520 = eq(out_romask_769, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7521 = eq(out_womask_769, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_657 = or(_out_T_7514, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_657 = cat(_T_800, _out_prepend_T_657) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7522 = or(out_prepend_657, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7523 = bits(_out_T_7522, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_770 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_770 = orr(_out_rimask_T_770) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_770 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_770 = andr(_out_wimask_T_770) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_770 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_770 = orr(_out_romask_T_770) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_770 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_770 = andr(_out_womask_T_770) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_770 = and(out_rivalid_1[648], out_rimask_770) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_770 = and(out_roready_1[648], out_romask_770) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_770 = and(out_wivalid_1[648], out_wimask_770) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_770 = and(out_woready_1[648], out_womask_770) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7524 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7525 = and(out_f_rivalid_770, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7526 = and(UInt<1>(0h1), out_f_roready_770) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7527 = eq(out_rimask_770, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7528 = eq(out_wimask_770, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7529 = eq(out_romask_770, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7530 = eq(out_womask_770, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_658 = or(_out_T_7523, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_658 = cat(_T_801, _out_prepend_T_658) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7531 = or(out_prepend_658, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7532 = bits(_out_T_7531, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_771 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_771 = orr(_out_rimask_T_771) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_771 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_771 = andr(_out_wimask_T_771) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_771 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_771 = orr(_out_romask_T_771) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_771 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_771 = andr(_out_womask_T_771) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_771 = and(out_rivalid_1[649], out_rimask_771) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_771 = and(out_roready_1[649], out_romask_771) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_771 = and(out_wivalid_1[649], out_wimask_771) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_771 = and(out_woready_1[649], out_womask_771) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7533 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7534 = and(out_f_rivalid_771, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7535 = and(UInt<1>(0h1), out_f_roready_771) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7536 = eq(out_rimask_771, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7537 = eq(out_wimask_771, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7538 = eq(out_romask_771, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7539 = eq(out_womask_771, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7540 = or(_T_1170, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7541 = bits(_out_T_7540, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_772 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_772 = orr(_out_rimask_T_772) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_772 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_772 = andr(_out_wimask_T_772) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_772 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_772 = orr(_out_romask_T_772) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_772 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_772 = andr(_out_womask_T_772) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_772 = and(out_rivalid_1[650], out_rimask_772) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_772 = and(out_roready_1[650], out_romask_772) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_772 = and(out_wivalid_1[650], out_wimask_772) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_772 = and(out_woready_1[650], out_womask_772) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7542 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7543 = and(out_f_rivalid_772, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7544 = and(UInt<1>(0h1), out_f_roready_772) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7545 = eq(out_rimask_772, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7546 = eq(out_wimask_772, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7547 = eq(out_romask_772, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7548 = eq(out_womask_772, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_659 = or(_out_T_7541, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_659 = cat(_T_1171, _out_prepend_T_659) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7549 = or(out_prepend_659, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7550 = bits(_out_T_7549, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_773 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_773 = orr(_out_rimask_T_773) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_773 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_773 = andr(_out_wimask_T_773) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_773 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_773 = orr(_out_romask_T_773) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_773 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_773 = andr(_out_womask_T_773) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_773 = and(out_rivalid_1[651], out_rimask_773) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_773 = and(out_roready_1[651], out_romask_773) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_773 = and(out_wivalid_1[651], out_wimask_773) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_773 = and(out_woready_1[651], out_womask_773) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7551 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7552 = and(out_f_rivalid_773, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7553 = and(UInt<1>(0h1), out_f_roready_773) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7554 = eq(out_rimask_773, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7555 = eq(out_wimask_773, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7556 = eq(out_romask_773, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7557 = eq(out_womask_773, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_660 = or(_out_T_7550, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_660 = cat(_T_1172, _out_prepend_T_660) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7558 = or(out_prepend_660, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7559 = bits(_out_T_7558, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_774 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_774 = orr(_out_rimask_T_774) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_774 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_774 = andr(_out_wimask_T_774) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_774 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_774 = orr(_out_romask_T_774) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_774 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_774 = andr(_out_womask_T_774) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_774 = and(out_rivalid_1[652], out_rimask_774) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_774 = and(out_roready_1[652], out_romask_774) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_774 = and(out_wivalid_1[652], out_wimask_774) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_774 = and(out_woready_1[652], out_womask_774) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7560 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7561 = and(out_f_rivalid_774, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7562 = and(UInt<1>(0h1), out_f_roready_774) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7563 = eq(out_rimask_774, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7564 = eq(out_wimask_774, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7565 = eq(out_romask_774, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7566 = eq(out_womask_774, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_661 = or(_out_T_7559, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_661 = cat(_T_1173, _out_prepend_T_661) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7567 = or(out_prepend_661, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7568 = bits(_out_T_7567, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_775 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_775 = orr(_out_rimask_T_775) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_775 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_775 = andr(_out_wimask_T_775) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_775 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_775 = orr(_out_romask_T_775) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_775 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_775 = andr(_out_womask_T_775) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_775 = and(out_rivalid_1[653], out_rimask_775) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_775 = and(out_roready_1[653], out_romask_775) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_775 = and(out_wivalid_1[653], out_wimask_775) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_775 = and(out_woready_1[653], out_womask_775) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7569 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7570 = and(out_f_rivalid_775, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7571 = and(UInt<1>(0h1), out_f_roready_775) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7572 = eq(out_rimask_775, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7573 = eq(out_wimask_775, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7574 = eq(out_romask_775, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7575 = eq(out_womask_775, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_662 = or(_out_T_7568, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_662 = cat(_T_1174, _out_prepend_T_662) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7576 = or(out_prepend_662, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7577 = bits(_out_T_7576, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_776 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_776 = orr(_out_rimask_T_776) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_776 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_776 = andr(_out_wimask_T_776) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_776 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_776 = orr(_out_romask_T_776) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_776 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_776 = andr(_out_womask_T_776) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_776 = and(out_rivalid_1[654], out_rimask_776) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_776 = and(out_roready_1[654], out_romask_776) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_776 = and(out_wivalid_1[654], out_wimask_776) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_776 = and(out_woready_1[654], out_womask_776) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7578 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7579 = and(out_f_rivalid_776, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7580 = and(UInt<1>(0h1), out_f_roready_776) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7581 = eq(out_rimask_776, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7582 = eq(out_wimask_776, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7583 = eq(out_romask_776, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7584 = eq(out_womask_776, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_663 = or(_out_T_7577, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_663 = cat(_T_1175, _out_prepend_T_663) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7585 = or(out_prepend_663, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7586 = bits(_out_T_7585, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_777 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_777 = orr(_out_rimask_T_777) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_777 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_777 = andr(_out_wimask_T_777) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_777 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_777 = orr(_out_romask_T_777) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_777 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_777 = andr(_out_womask_T_777) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_777 = and(out_rivalid_1[655], out_rimask_777) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_777 = and(out_roready_1[655], out_romask_777) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_777 = and(out_wivalid_1[655], out_wimask_777) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_777 = and(out_woready_1[655], out_womask_777) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7587 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7588 = and(out_f_rivalid_777, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7589 = and(UInt<1>(0h1), out_f_roready_777) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7590 = eq(out_rimask_777, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7591 = eq(out_wimask_777, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7592 = eq(out_romask_777, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7593 = eq(out_womask_777, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_664 = or(_out_T_7586, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_664 = cat(_T_1176, _out_prepend_T_664) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7594 = or(out_prepend_664, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7595 = bits(_out_T_7594, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_778 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_778 = orr(_out_rimask_T_778) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_778 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_778 = andr(_out_wimask_T_778) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_778 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_778 = orr(_out_romask_T_778) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_778 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_778 = andr(_out_womask_T_778) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_778 = and(out_rivalid_1[656], out_rimask_778) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_778 = and(out_roready_1[656], out_romask_778) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_778 = and(out_wivalid_1[656], out_wimask_778) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_778 = and(out_woready_1[656], out_womask_778) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7596 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7597 = and(out_f_rivalid_778, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7598 = and(UInt<1>(0h1), out_f_roready_778) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7599 = eq(out_rimask_778, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7600 = eq(out_wimask_778, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7601 = eq(out_romask_778, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7602 = eq(out_womask_778, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_665 = or(_out_T_7595, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_665 = cat(_T_1177, _out_prepend_T_665) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7603 = or(out_prepend_665, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7604 = bits(_out_T_7603, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_779 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_779 = orr(_out_rimask_T_779) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_779 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_779 = andr(_out_wimask_T_779) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_779 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_779 = orr(_out_romask_T_779) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_779 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_779 = andr(_out_womask_T_779) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_779 = and(out_rivalid_1[657], out_rimask_779) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_779 = and(out_roready_1[657], out_romask_779) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_779 = and(out_wivalid_1[657], out_wimask_779) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_779 = and(out_woready_1[657], out_womask_779) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7605 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7606 = and(out_f_rivalid_779, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7607 = and(UInt<1>(0h1), out_f_roready_779) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7608 = eq(out_rimask_779, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7609 = eq(out_wimask_779, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7610 = eq(out_romask_779, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7611 = eq(out_womask_779, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7612 = or(_T_1258, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7613 = bits(_out_T_7612, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_780 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_780 = orr(_out_rimask_T_780) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_780 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_780 = andr(_out_wimask_T_780) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_780 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_780 = orr(_out_romask_T_780) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_780 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_780 = andr(_out_womask_T_780) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_780 = and(out_rivalid_1[658], out_rimask_780) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_780 = and(out_roready_1[658], out_romask_780) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_780 = and(out_wivalid_1[658], out_wimask_780) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_780 = and(out_woready_1[658], out_womask_780) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7614 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7615 = and(out_f_rivalid_780, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7616 = and(UInt<1>(0h1), out_f_roready_780) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7617 = eq(out_rimask_780, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7618 = eq(out_wimask_780, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7619 = eq(out_romask_780, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7620 = eq(out_womask_780, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_666 = or(_out_T_7613, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_666 = cat(_T_1259, _out_prepend_T_666) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7621 = or(out_prepend_666, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7622 = bits(_out_T_7621, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_781 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_781 = orr(_out_rimask_T_781) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_781 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_781 = andr(_out_wimask_T_781) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_781 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_781 = orr(_out_romask_T_781) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_781 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_781 = andr(_out_womask_T_781) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_781 = and(out_rivalid_1[659], out_rimask_781) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_781 = and(out_roready_1[659], out_romask_781) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_781 = and(out_wivalid_1[659], out_wimask_781) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_781 = and(out_woready_1[659], out_womask_781) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7623 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7624 = and(out_f_rivalid_781, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7625 = and(UInt<1>(0h1), out_f_roready_781) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7626 = eq(out_rimask_781, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7627 = eq(out_wimask_781, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7628 = eq(out_romask_781, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7629 = eq(out_womask_781, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_667 = or(_out_T_7622, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_667 = cat(_T_1260, _out_prepend_T_667) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7630 = or(out_prepend_667, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7631 = bits(_out_T_7630, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_782 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_782 = orr(_out_rimask_T_782) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_782 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_782 = andr(_out_wimask_T_782) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_782 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_782 = orr(_out_romask_T_782) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_782 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_782 = andr(_out_womask_T_782) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_782 = and(out_rivalid_1[660], out_rimask_782) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_782 = and(out_roready_1[660], out_romask_782) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_782 = and(out_wivalid_1[660], out_wimask_782) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_782 = and(out_woready_1[660], out_womask_782) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7632 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7633 = and(out_f_rivalid_782, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7634 = and(UInt<1>(0h1), out_f_roready_782) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7635 = eq(out_rimask_782, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7636 = eq(out_wimask_782, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7637 = eq(out_romask_782, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7638 = eq(out_womask_782, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_668 = or(_out_T_7631, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_668 = cat(_T_1261, _out_prepend_T_668) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7639 = or(out_prepend_668, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7640 = bits(_out_T_7639, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_783 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_783 = orr(_out_rimask_T_783) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_783 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_783 = andr(_out_wimask_T_783) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_783 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_783 = orr(_out_romask_T_783) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_783 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_783 = andr(_out_womask_T_783) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_783 = and(out_rivalid_1[661], out_rimask_783) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_783 = and(out_roready_1[661], out_romask_783) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_783 = and(out_wivalid_1[661], out_wimask_783) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_783 = and(out_woready_1[661], out_womask_783) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7641 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7642 = and(out_f_rivalid_783, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7643 = and(UInt<1>(0h1), out_f_roready_783) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7644 = eq(out_rimask_783, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7645 = eq(out_wimask_783, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7646 = eq(out_romask_783, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7647 = eq(out_womask_783, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_669 = or(_out_T_7640, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_669 = cat(_T_1262, _out_prepend_T_669) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7648 = or(out_prepend_669, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7649 = bits(_out_T_7648, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_784 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_784 = orr(_out_rimask_T_784) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_784 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_784 = andr(_out_wimask_T_784) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_784 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_784 = orr(_out_romask_T_784) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_784 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_784 = andr(_out_womask_T_784) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_784 = and(out_rivalid_1[662], out_rimask_784) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_784 = and(out_roready_1[662], out_romask_784) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_784 = and(out_wivalid_1[662], out_wimask_784) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_784 = and(out_woready_1[662], out_womask_784) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7650 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7651 = and(out_f_rivalid_784, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7652 = and(UInt<1>(0h1), out_f_roready_784) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7653 = eq(out_rimask_784, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7654 = eq(out_wimask_784, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7655 = eq(out_romask_784, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7656 = eq(out_womask_784, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_670 = or(_out_T_7649, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_670 = cat(_T_1263, _out_prepend_T_670) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7657 = or(out_prepend_670, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7658 = bits(_out_T_7657, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_785 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_785 = orr(_out_rimask_T_785) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_785 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_785 = andr(_out_wimask_T_785) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_785 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_785 = orr(_out_romask_T_785) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_785 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_785 = andr(_out_womask_T_785) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_785 = and(out_rivalid_1[663], out_rimask_785) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_785 = and(out_roready_1[663], out_romask_785) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_785 = and(out_wivalid_1[663], out_wimask_785) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_785 = and(out_woready_1[663], out_womask_785) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7659 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7660 = and(out_f_rivalid_785, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7661 = and(UInt<1>(0h1), out_f_roready_785) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7662 = eq(out_rimask_785, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7663 = eq(out_wimask_785, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7664 = eq(out_romask_785, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7665 = eq(out_womask_785, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_671 = or(_out_T_7658, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_671 = cat(_T_1264, _out_prepend_T_671) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7666 = or(out_prepend_671, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7667 = bits(_out_T_7666, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_786 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_786 = orr(_out_rimask_T_786) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_786 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_786 = andr(_out_wimask_T_786) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_786 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_786 = orr(_out_romask_T_786) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_786 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_786 = andr(_out_womask_T_786) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_786 = and(out_rivalid_1[664], out_rimask_786) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_786 = and(out_roready_1[664], out_romask_786) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_786 = and(out_wivalid_1[664], out_wimask_786) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_786 = and(out_woready_1[664], out_womask_786) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7668 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7669 = and(out_f_rivalid_786, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7670 = and(UInt<1>(0h1), out_f_roready_786) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7671 = eq(out_rimask_786, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7672 = eq(out_wimask_786, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7673 = eq(out_romask_786, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7674 = eq(out_womask_786, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_672 = or(_out_T_7667, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_672 = cat(_T_1265, _out_prepend_T_672) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7675 = or(out_prepend_672, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7676 = bits(_out_T_7675, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_787 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_787 = orr(_out_rimask_T_787) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_787 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_787 = andr(_out_wimask_T_787) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_787 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_787 = orr(_out_romask_T_787) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_787 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_787 = andr(_out_womask_T_787) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_787 = and(out_rivalid_1[665], out_rimask_787) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_787 = and(out_roready_1[665], out_romask_787) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_787 = and(out_wivalid_1[665], out_wimask_787) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_787 = and(out_woready_1[665], out_womask_787) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7677 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7678 = and(out_f_rivalid_787, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7679 = and(UInt<1>(0h1), out_f_roready_787) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7680 = eq(out_rimask_787, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7681 = eq(out_wimask_787, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7682 = eq(out_romask_787, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7683 = eq(out_womask_787, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7684 = or(_T_1378, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7685 = bits(_out_T_7684, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_788 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_788 = orr(_out_rimask_T_788) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_788 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_788 = andr(_out_wimask_T_788) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_788 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_788 = orr(_out_romask_T_788) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_788 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_788 = andr(_out_womask_T_788) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_788 = and(out_rivalid_1[666], out_rimask_788) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_788 = and(out_roready_1[666], out_romask_788) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_788 = and(out_wivalid_1[666], out_wimask_788) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_788 = and(out_woready_1[666], out_womask_788) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7686 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7687 = and(out_f_rivalid_788, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7688 = and(UInt<1>(0h1), out_f_roready_788) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7689 = eq(out_rimask_788, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7690 = eq(out_wimask_788, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7691 = eq(out_romask_788, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7692 = eq(out_womask_788, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_673 = or(_out_T_7685, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_673 = cat(_T_1379, _out_prepend_T_673) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7693 = or(out_prepend_673, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7694 = bits(_out_T_7693, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_789 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_789 = orr(_out_rimask_T_789) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_789 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_789 = andr(_out_wimask_T_789) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_789 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_789 = orr(_out_romask_T_789) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_789 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_789 = andr(_out_womask_T_789) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_789 = and(out_rivalid_1[667], out_rimask_789) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_789 = and(out_roready_1[667], out_romask_789) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_789 = and(out_wivalid_1[667], out_wimask_789) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_789 = and(out_woready_1[667], out_womask_789) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7695 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7696 = and(out_f_rivalid_789, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7697 = and(UInt<1>(0h1), out_f_roready_789) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7698 = eq(out_rimask_789, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7699 = eq(out_wimask_789, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7700 = eq(out_romask_789, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7701 = eq(out_womask_789, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_674 = or(_out_T_7694, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_674 = cat(_T_1380, _out_prepend_T_674) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7702 = or(out_prepend_674, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7703 = bits(_out_T_7702, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_790 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_790 = orr(_out_rimask_T_790) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_790 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_790 = andr(_out_wimask_T_790) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_790 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_790 = orr(_out_romask_T_790) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_790 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_790 = andr(_out_womask_T_790) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_790 = and(out_rivalid_1[668], out_rimask_790) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_790 = and(out_roready_1[668], out_romask_790) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_790 = and(out_wivalid_1[668], out_wimask_790) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_790 = and(out_woready_1[668], out_womask_790) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7704 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7705 = and(out_f_rivalid_790, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7706 = and(UInt<1>(0h1), out_f_roready_790) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7707 = eq(out_rimask_790, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7708 = eq(out_wimask_790, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7709 = eq(out_romask_790, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7710 = eq(out_womask_790, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_675 = or(_out_T_7703, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_675 = cat(_T_1381, _out_prepend_T_675) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7711 = or(out_prepend_675, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7712 = bits(_out_T_7711, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_791 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_791 = orr(_out_rimask_T_791) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_791 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_791 = andr(_out_wimask_T_791) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_791 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_791 = orr(_out_romask_T_791) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_791 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_791 = andr(_out_womask_T_791) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_791 = and(out_rivalid_1[669], out_rimask_791) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_791 = and(out_roready_1[669], out_romask_791) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_791 = and(out_wivalid_1[669], out_wimask_791) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_791 = and(out_woready_1[669], out_womask_791) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7713 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7714 = and(out_f_rivalid_791, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7715 = and(UInt<1>(0h1), out_f_roready_791) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7716 = eq(out_rimask_791, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7717 = eq(out_wimask_791, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7718 = eq(out_romask_791, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7719 = eq(out_womask_791, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_676 = or(_out_T_7712, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_676 = cat(_T_1382, _out_prepend_T_676) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7720 = or(out_prepend_676, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7721 = bits(_out_T_7720, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_792 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_792 = orr(_out_rimask_T_792) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_792 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_792 = andr(_out_wimask_T_792) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_792 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_792 = orr(_out_romask_T_792) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_792 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_792 = andr(_out_womask_T_792) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_792 = and(out_rivalid_1[670], out_rimask_792) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_792 = and(out_roready_1[670], out_romask_792) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_792 = and(out_wivalid_1[670], out_wimask_792) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_792 = and(out_woready_1[670], out_womask_792) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7722 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7723 = and(out_f_rivalid_792, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7724 = and(UInt<1>(0h1), out_f_roready_792) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7725 = eq(out_rimask_792, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7726 = eq(out_wimask_792, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7727 = eq(out_romask_792, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7728 = eq(out_womask_792, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_677 = or(_out_T_7721, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_677 = cat(_T_1383, _out_prepend_T_677) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7729 = or(out_prepend_677, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7730 = bits(_out_T_7729, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_793 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_793 = orr(_out_rimask_T_793) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_793 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_793 = andr(_out_wimask_T_793) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_793 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_793 = orr(_out_romask_T_793) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_793 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_793 = andr(_out_womask_T_793) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_793 = and(out_rivalid_1[671], out_rimask_793) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_793 = and(out_roready_1[671], out_romask_793) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_793 = and(out_wivalid_1[671], out_wimask_793) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_793 = and(out_woready_1[671], out_womask_793) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7731 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7732 = and(out_f_rivalid_793, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7733 = and(UInt<1>(0h1), out_f_roready_793) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7734 = eq(out_rimask_793, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7735 = eq(out_wimask_793, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7736 = eq(out_romask_793, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7737 = eq(out_womask_793, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_678 = or(_out_T_7730, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_678 = cat(_T_1384, _out_prepend_T_678) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7738 = or(out_prepend_678, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7739 = bits(_out_T_7738, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_794 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_794 = orr(_out_rimask_T_794) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_794 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_794 = andr(_out_wimask_T_794) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_794 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_794 = orr(_out_romask_T_794) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_794 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_794 = andr(_out_womask_T_794) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_794 = and(out_rivalid_1[672], out_rimask_794) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_794 = and(out_roready_1[672], out_romask_794) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_794 = and(out_wivalid_1[672], out_wimask_794) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_794 = and(out_woready_1[672], out_womask_794) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7740 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7741 = and(out_f_rivalid_794, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7742 = and(UInt<1>(0h1), out_f_roready_794) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7743 = eq(out_rimask_794, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7744 = eq(out_wimask_794, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7745 = eq(out_romask_794, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7746 = eq(out_womask_794, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_679 = or(_out_T_7739, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_679 = cat(_T_1385, _out_prepend_T_679) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7747 = or(out_prepend_679, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7748 = bits(_out_T_7747, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_795 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_795 = orr(_out_rimask_T_795) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_795 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_795 = andr(_out_wimask_T_795) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_795 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_795 = orr(_out_romask_T_795) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_795 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_795 = andr(_out_womask_T_795) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_795 = and(out_rivalid_1[673], out_rimask_795) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_795 = and(out_roready_1[673], out_romask_795) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_795 = and(out_wivalid_1[673], out_wimask_795) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_795 = and(out_woready_1[673], out_womask_795) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7749 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7750 = and(out_f_rivalid_795, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7751 = and(UInt<1>(0h1), out_f_roready_795) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7752 = eq(out_rimask_795, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7753 = eq(out_wimask_795, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7754 = eq(out_romask_795, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7755 = eq(out_womask_795, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7756 = or(_T_1082, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7757 = bits(_out_T_7756, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_796 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_796 = orr(_out_rimask_T_796) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_796 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_796 = andr(_out_wimask_T_796) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_796 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_796 = orr(_out_romask_T_796) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_796 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_796 = andr(_out_womask_T_796) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_796 = and(out_rivalid_1[674], out_rimask_796) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_796 = and(out_roready_1[674], out_romask_796) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_796 = and(out_wivalid_1[674], out_wimask_796) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_796 = and(out_woready_1[674], out_womask_796) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7758 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7759 = and(out_f_rivalid_796, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7760 = and(UInt<1>(0h1), out_f_roready_796) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7761 = eq(out_rimask_796, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7762 = eq(out_wimask_796, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7763 = eq(out_romask_796, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7764 = eq(out_womask_796, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_680 = or(_out_T_7757, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_680 = cat(_T_1083, _out_prepend_T_680) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7765 = or(out_prepend_680, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7766 = bits(_out_T_7765, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_797 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_797 = orr(_out_rimask_T_797) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_797 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_797 = andr(_out_wimask_T_797) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_797 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_797 = orr(_out_romask_T_797) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_797 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_797 = andr(_out_womask_T_797) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_797 = and(out_rivalid_1[675], out_rimask_797) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_797 = and(out_roready_1[675], out_romask_797) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_797 = and(out_wivalid_1[675], out_wimask_797) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_797 = and(out_woready_1[675], out_womask_797) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7767 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7768 = and(out_f_rivalid_797, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7769 = and(UInt<1>(0h1), out_f_roready_797) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7770 = eq(out_rimask_797, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7771 = eq(out_wimask_797, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7772 = eq(out_romask_797, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7773 = eq(out_womask_797, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_681 = or(_out_T_7766, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_681 = cat(_T_1084, _out_prepend_T_681) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7774 = or(out_prepend_681, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7775 = bits(_out_T_7774, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_798 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_798 = orr(_out_rimask_T_798) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_798 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_798 = andr(_out_wimask_T_798) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_798 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_798 = orr(_out_romask_T_798) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_798 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_798 = andr(_out_womask_T_798) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_798 = and(out_rivalid_1[676], out_rimask_798) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_798 = and(out_roready_1[676], out_romask_798) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_798 = and(out_wivalid_1[676], out_wimask_798) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_798 = and(out_woready_1[676], out_womask_798) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7776 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7777 = and(out_f_rivalid_798, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7778 = and(UInt<1>(0h1), out_f_roready_798) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7779 = eq(out_rimask_798, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7780 = eq(out_wimask_798, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7781 = eq(out_romask_798, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7782 = eq(out_womask_798, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_682 = or(_out_T_7775, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_682 = cat(_T_1085, _out_prepend_T_682) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7783 = or(out_prepend_682, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7784 = bits(_out_T_7783, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_799 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_799 = orr(_out_rimask_T_799) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_799 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_799 = andr(_out_wimask_T_799) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_799 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_799 = orr(_out_romask_T_799) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_799 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_799 = andr(_out_womask_T_799) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_799 = and(out_rivalid_1[677], out_rimask_799) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_799 = and(out_roready_1[677], out_romask_799) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_799 = and(out_wivalid_1[677], out_wimask_799) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_799 = and(out_woready_1[677], out_womask_799) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7785 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7786 = and(out_f_rivalid_799, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7787 = and(UInt<1>(0h1), out_f_roready_799) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7788 = eq(out_rimask_799, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7789 = eq(out_wimask_799, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7790 = eq(out_romask_799, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7791 = eq(out_womask_799, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_683 = or(_out_T_7784, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_683 = cat(_T_1086, _out_prepend_T_683) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7792 = or(out_prepend_683, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7793 = bits(_out_T_7792, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_800 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_800 = orr(_out_rimask_T_800) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_800 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_800 = andr(_out_wimask_T_800) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_800 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_800 = orr(_out_romask_T_800) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_800 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_800 = andr(_out_womask_T_800) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_800 = and(out_rivalid_1[678], out_rimask_800) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_800 = and(out_roready_1[678], out_romask_800) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_800 = and(out_wivalid_1[678], out_wimask_800) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_800 = and(out_woready_1[678], out_womask_800) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7794 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7795 = and(out_f_rivalid_800, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7796 = and(UInt<1>(0h1), out_f_roready_800) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7797 = eq(out_rimask_800, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7798 = eq(out_wimask_800, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7799 = eq(out_romask_800, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7800 = eq(out_womask_800, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_684 = or(_out_T_7793, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_684 = cat(_T_1087, _out_prepend_T_684) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7801 = or(out_prepend_684, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7802 = bits(_out_T_7801, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_801 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_801 = orr(_out_rimask_T_801) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_801 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_801 = andr(_out_wimask_T_801) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_801 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_801 = orr(_out_romask_T_801) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_801 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_801 = andr(_out_womask_T_801) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_801 = and(out_rivalid_1[679], out_rimask_801) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_801 = and(out_roready_1[679], out_romask_801) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_801 = and(out_wivalid_1[679], out_wimask_801) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_801 = and(out_woready_1[679], out_womask_801) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7803 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7804 = and(out_f_rivalid_801, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7805 = and(UInt<1>(0h1), out_f_roready_801) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7806 = eq(out_rimask_801, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7807 = eq(out_wimask_801, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7808 = eq(out_romask_801, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7809 = eq(out_womask_801, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_685 = or(_out_T_7802, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_685 = cat(_T_1088, _out_prepend_T_685) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7810 = or(out_prepend_685, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7811 = bits(_out_T_7810, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_802 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_802 = orr(_out_rimask_T_802) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_802 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_802 = andr(_out_wimask_T_802) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_802 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_802 = orr(_out_romask_T_802) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_802 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_802 = andr(_out_womask_T_802) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_802 = and(out_rivalid_1[680], out_rimask_802) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_802 = and(out_roready_1[680], out_romask_802) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_802 = and(out_wivalid_1[680], out_wimask_802) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_802 = and(out_woready_1[680], out_womask_802) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7812 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7813 = and(out_f_rivalid_802, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7814 = and(UInt<1>(0h1), out_f_roready_802) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7815 = eq(out_rimask_802, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7816 = eq(out_wimask_802, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7817 = eq(out_romask_802, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7818 = eq(out_womask_802, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_686 = or(_out_T_7811, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_686 = cat(_T_1089, _out_prepend_T_686) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7819 = or(out_prepend_686, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7820 = bits(_out_T_7819, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_803 = bits(out_frontMask_1, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_803 = orr(_out_rimask_T_803) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_803 = bits(out_frontMask_1, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_803 = andr(_out_wimask_T_803) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_803 = bits(out_backMask_1, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_803 = orr(_out_romask_T_803) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_803 = bits(out_backMask_1, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_803 = andr(_out_womask_T_803) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_803 = and(out_rivalid_1[681], out_rimask_803) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_803 = and(out_roready_1[681], out_romask_803) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_803 = and(out_wivalid_1[681], out_wimask_803) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_803 = and(out_woready_1[681], out_womask_803) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7821 = bits(out_front_1.bits.data, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7822 = and(out_f_rivalid_803, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7823 = and(UInt<1>(0h1), out_f_roready_803) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7824 = eq(out_rimask_803, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7825 = eq(out_wimask_803, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7826 = eq(out_romask_803, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7827 = eq(out_womask_803, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7828 = or(abstractGeneratedMem[0], UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7829 = bits(_out_T_7828, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_804 = bits(out_frontMask_1, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_804 = orr(_out_rimask_T_804) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_804 = bits(out_frontMask_1, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_804 = andr(_out_wimask_T_804) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_804 = bits(out_backMask_1, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_804 = orr(_out_romask_T_804) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_804 = bits(out_backMask_1, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_804 = andr(_out_womask_T_804) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_804 = and(out_rivalid_1[682], out_rimask_804) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_804 = and(out_roready_1[682], out_romask_804) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_804 = and(out_wivalid_1[682], out_wimask_804) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_804 = and(out_woready_1[682], out_womask_804) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7830 = bits(out_front_1.bits.data, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7831 = and(out_f_rivalid_804, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7832 = and(UInt<1>(0h1), out_f_roready_804) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7833 = eq(out_rimask_804, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7834 = eq(out_wimask_804, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7835 = eq(out_romask_804, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7836 = eq(out_womask_804, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_687 = or(_out_T_7829, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_687 = cat(abstractGeneratedMem[1], _out_prepend_T_687) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7837 = or(out_prepend_687, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7838 = bits(_out_T_7837, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_805 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_805 = orr(_out_rimask_T_805) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_805 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_805 = andr(_out_wimask_T_805) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_805 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_805 = orr(_out_romask_T_805) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_805 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_805 = andr(_out_womask_T_805) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_805 = and(out_rivalid_1[683], out_rimask_805) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_805 = and(out_roready_1[683], out_romask_805) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_805 = and(out_wivalid_1[683], out_wimask_805) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_805 = and(out_woready_1[683], out_womask_805) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7839 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7840 = and(out_f_rivalid_805, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7841 = and(UInt<1>(0h1), out_f_roready_805) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7842 = eq(out_rimask_805, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7843 = eq(out_wimask_805, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7844 = eq(out_romask_805, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7845 = eq(out_womask_805, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7846 = or(_T_538, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7847 = bits(_out_T_7846, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_806 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_806 = orr(_out_rimask_T_806) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_806 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_806 = andr(_out_wimask_T_806) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_806 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_806 = orr(_out_romask_T_806) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_806 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_806 = andr(_out_womask_T_806) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_806 = and(out_rivalid_1[684], out_rimask_806) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_806 = and(out_roready_1[684], out_romask_806) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_806 = and(out_wivalid_1[684], out_wimask_806) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_806 = and(out_woready_1[684], out_womask_806) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7848 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7849 = and(out_f_rivalid_806, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7850 = and(UInt<1>(0h1), out_f_roready_806) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7851 = eq(out_rimask_806, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7852 = eq(out_wimask_806, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7853 = eq(out_romask_806, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7854 = eq(out_womask_806, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_688 = or(_out_T_7847, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_688 = cat(_T_539, _out_prepend_T_688) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7855 = or(out_prepend_688, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7856 = bits(_out_T_7855, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_807 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_807 = orr(_out_rimask_T_807) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_807 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_807 = andr(_out_wimask_T_807) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_807 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_807 = orr(_out_romask_T_807) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_807 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_807 = andr(_out_womask_T_807) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_807 = and(out_rivalid_1[685], out_rimask_807) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_807 = and(out_roready_1[685], out_romask_807) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_807 = and(out_wivalid_1[685], out_wimask_807) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_807 = and(out_woready_1[685], out_womask_807) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7857 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7858 = and(out_f_rivalid_807, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7859 = and(UInt<1>(0h1), out_f_roready_807) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7860 = eq(out_rimask_807, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7861 = eq(out_wimask_807, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7862 = eq(out_romask_807, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7863 = eq(out_womask_807, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_689 = or(_out_T_7856, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_689 = cat(_T_540, _out_prepend_T_689) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7864 = or(out_prepend_689, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7865 = bits(_out_T_7864, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_808 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_808 = orr(_out_rimask_T_808) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_808 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_808 = andr(_out_wimask_T_808) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_808 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_808 = orr(_out_romask_T_808) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_808 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_808 = andr(_out_womask_T_808) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_808 = and(out_rivalid_1[686], out_rimask_808) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_808 = and(out_roready_1[686], out_romask_808) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_808 = and(out_wivalid_1[686], out_wimask_808) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_808 = and(out_woready_1[686], out_womask_808) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7866 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7867 = and(out_f_rivalid_808, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7868 = and(UInt<1>(0h1), out_f_roready_808) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7869 = eq(out_rimask_808, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7870 = eq(out_wimask_808, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7871 = eq(out_romask_808, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7872 = eq(out_womask_808, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_690 = or(_out_T_7865, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_690 = cat(_T_541, _out_prepend_T_690) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7873 = or(out_prepend_690, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7874 = bits(_out_T_7873, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_809 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_809 = orr(_out_rimask_T_809) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_809 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_809 = andr(_out_wimask_T_809) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_809 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_809 = orr(_out_romask_T_809) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_809 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_809 = andr(_out_womask_T_809) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_809 = and(out_rivalid_1[687], out_rimask_809) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_809 = and(out_roready_1[687], out_romask_809) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_809 = and(out_wivalid_1[687], out_wimask_809) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_809 = and(out_woready_1[687], out_womask_809) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7875 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7876 = and(out_f_rivalid_809, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7877 = and(UInt<1>(0h1), out_f_roready_809) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7878 = eq(out_rimask_809, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7879 = eq(out_wimask_809, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7880 = eq(out_romask_809, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7881 = eq(out_womask_809, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_691 = or(_out_T_7874, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_691 = cat(_T_542, _out_prepend_T_691) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7882 = or(out_prepend_691, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7883 = bits(_out_T_7882, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_810 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_810 = orr(_out_rimask_T_810) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_810 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_810 = andr(_out_wimask_T_810) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_810 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_810 = orr(_out_romask_T_810) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_810 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_810 = andr(_out_womask_T_810) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_810 = and(out_rivalid_1[688], out_rimask_810) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_810 = and(out_roready_1[688], out_romask_810) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_810 = and(out_wivalid_1[688], out_wimask_810) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_810 = and(out_woready_1[688], out_womask_810) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7884 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7885 = and(out_f_rivalid_810, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7886 = and(UInt<1>(0h1), out_f_roready_810) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7887 = eq(out_rimask_810, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7888 = eq(out_wimask_810, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7889 = eq(out_romask_810, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7890 = eq(out_womask_810, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_692 = or(_out_T_7883, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_692 = cat(_T_543, _out_prepend_T_692) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7891 = or(out_prepend_692, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7892 = bits(_out_T_7891, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_811 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_811 = orr(_out_rimask_T_811) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_811 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_811 = andr(_out_wimask_T_811) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_811 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_811 = orr(_out_romask_T_811) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_811 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_811 = andr(_out_womask_T_811) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_811 = and(out_rivalid_1[689], out_rimask_811) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_811 = and(out_roready_1[689], out_romask_811) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_811 = and(out_wivalid_1[689], out_wimask_811) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_811 = and(out_woready_1[689], out_womask_811) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7893 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7894 = and(out_f_rivalid_811, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7895 = and(UInt<1>(0h1), out_f_roready_811) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7896 = eq(out_rimask_811, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7897 = eq(out_wimask_811, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7898 = eq(out_romask_811, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7899 = eq(out_womask_811, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_693 = or(_out_T_7892, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_693 = cat(_T_544, _out_prepend_T_693) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7900 = or(out_prepend_693, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7901 = bits(_out_T_7900, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_812 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_812 = orr(_out_rimask_T_812) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_812 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_812 = andr(_out_wimask_T_812) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_812 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_812 = orr(_out_romask_T_812) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_812 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_812 = andr(_out_womask_T_812) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_812 = and(out_rivalid_1[690], out_rimask_812) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_812 = and(out_roready_1[690], out_romask_812) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_812 = and(out_wivalid_1[690], out_wimask_812) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_812 = and(out_woready_1[690], out_womask_812) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7902 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7903 = and(out_f_rivalid_812, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7904 = and(UInt<1>(0h1), out_f_roready_812) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7905 = eq(out_rimask_812, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7906 = eq(out_wimask_812, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7907 = eq(out_romask_812, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7908 = eq(out_womask_812, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_694 = or(_out_T_7901, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_694 = cat(_T_545, _out_prepend_T_694) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7909 = or(out_prepend_694, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7910 = bits(_out_T_7909, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_813 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_813 = orr(_out_rimask_T_813) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_813 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_813 = andr(_out_wimask_T_813) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_813 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_813 = orr(_out_romask_T_813) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_813 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_813 = andr(_out_womask_T_813) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_813 = and(out_rivalid_1[691], out_rimask_813) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_813 = and(out_roready_1[691], out_romask_813) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_813 = and(out_wivalid_1[691], out_wimask_813) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_813 = and(out_woready_1[691], out_womask_813) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7911 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7912 = and(out_f_rivalid_813, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7913 = and(UInt<1>(0h1), out_f_roready_813) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7914 = eq(out_rimask_813, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7915 = eq(out_wimask_813, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7916 = eq(out_romask_813, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7917 = eq(out_womask_813, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7918 = or(_T_1122, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7919 = bits(_out_T_7918, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_814 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_814 = orr(_out_rimask_T_814) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_814 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_814 = andr(_out_wimask_T_814) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_814 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_814 = orr(_out_romask_T_814) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_814 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_814 = andr(_out_womask_T_814) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_814 = and(out_rivalid_1[692], out_rimask_814) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_814 = and(out_roready_1[692], out_romask_814) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_814 = and(out_wivalid_1[692], out_wimask_814) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_814 = and(out_woready_1[692], out_womask_814) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7920 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7921 = and(out_f_rivalid_814, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7922 = and(UInt<1>(0h1), out_f_roready_814) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7923 = eq(out_rimask_814, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7924 = eq(out_wimask_814, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7925 = eq(out_romask_814, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7926 = eq(out_womask_814, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_695 = or(_out_T_7919, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_695 = cat(_T_1123, _out_prepend_T_695) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7927 = or(out_prepend_695, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7928 = bits(_out_T_7927, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_815 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_815 = orr(_out_rimask_T_815) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_815 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_815 = andr(_out_wimask_T_815) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_815 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_815 = orr(_out_romask_T_815) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_815 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_815 = andr(_out_womask_T_815) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_815 = and(out_rivalid_1[693], out_rimask_815) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_815 = and(out_roready_1[693], out_romask_815) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_815 = and(out_wivalid_1[693], out_wimask_815) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_815 = and(out_woready_1[693], out_womask_815) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7929 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7930 = and(out_f_rivalid_815, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7931 = and(UInt<1>(0h1), out_f_roready_815) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7932 = eq(out_rimask_815, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7933 = eq(out_wimask_815, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7934 = eq(out_romask_815, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7935 = eq(out_womask_815, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_696 = or(_out_T_7928, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_696 = cat(_T_1124, _out_prepend_T_696) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7936 = or(out_prepend_696, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7937 = bits(_out_T_7936, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_816 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_816 = orr(_out_rimask_T_816) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_816 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_816 = andr(_out_wimask_T_816) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_816 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_816 = orr(_out_romask_T_816) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_816 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_816 = andr(_out_womask_T_816) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_816 = and(out_rivalid_1[694], out_rimask_816) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_816 = and(out_roready_1[694], out_romask_816) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_816 = and(out_wivalid_1[694], out_wimask_816) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_816 = and(out_woready_1[694], out_womask_816) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7938 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7939 = and(out_f_rivalid_816, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7940 = and(UInt<1>(0h1), out_f_roready_816) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7941 = eq(out_rimask_816, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7942 = eq(out_wimask_816, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7943 = eq(out_romask_816, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7944 = eq(out_womask_816, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_697 = or(_out_T_7937, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_697 = cat(_T_1125, _out_prepend_T_697) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7945 = or(out_prepend_697, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7946 = bits(_out_T_7945, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_817 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_817 = orr(_out_rimask_T_817) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_817 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_817 = andr(_out_wimask_T_817) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_817 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_817 = orr(_out_romask_T_817) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_817 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_817 = andr(_out_womask_T_817) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_817 = and(out_rivalid_1[695], out_rimask_817) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_817 = and(out_roready_1[695], out_romask_817) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_817 = and(out_wivalid_1[695], out_wimask_817) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_817 = and(out_woready_1[695], out_womask_817) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7947 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7948 = and(out_f_rivalid_817, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7949 = and(UInt<1>(0h1), out_f_roready_817) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7950 = eq(out_rimask_817, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7951 = eq(out_wimask_817, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7952 = eq(out_romask_817, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7953 = eq(out_womask_817, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_698 = or(_out_T_7946, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_698 = cat(_T_1126, _out_prepend_T_698) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7954 = or(out_prepend_698, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7955 = bits(_out_T_7954, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_818 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_818 = orr(_out_rimask_T_818) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_818 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_818 = andr(_out_wimask_T_818) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_818 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_818 = orr(_out_romask_T_818) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_818 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_818 = andr(_out_womask_T_818) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_818 = and(out_rivalid_1[696], out_rimask_818) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_818 = and(out_roready_1[696], out_romask_818) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_818 = and(out_wivalid_1[696], out_wimask_818) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_818 = and(out_woready_1[696], out_womask_818) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7956 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7957 = and(out_f_rivalid_818, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7958 = and(UInt<1>(0h1), out_f_roready_818) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7959 = eq(out_rimask_818, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7960 = eq(out_wimask_818, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7961 = eq(out_romask_818, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7962 = eq(out_womask_818, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_699 = or(_out_T_7955, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_699 = cat(_T_1127, _out_prepend_T_699) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7963 = or(out_prepend_699, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7964 = bits(_out_T_7963, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_819 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_819 = orr(_out_rimask_T_819) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_819 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_819 = andr(_out_wimask_T_819) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_819 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_819 = orr(_out_romask_T_819) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_819 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_819 = andr(_out_womask_T_819) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_819 = and(out_rivalid_1[697], out_rimask_819) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_819 = and(out_roready_1[697], out_romask_819) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_819 = and(out_wivalid_1[697], out_wimask_819) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_819 = and(out_woready_1[697], out_womask_819) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7965 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7966 = and(out_f_rivalid_819, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7967 = and(UInt<1>(0h1), out_f_roready_819) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7968 = eq(out_rimask_819, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7969 = eq(out_wimask_819, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7970 = eq(out_romask_819, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7971 = eq(out_womask_819, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_700 = or(_out_T_7964, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_700 = cat(_T_1128, _out_prepend_T_700) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7972 = or(out_prepend_700, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7973 = bits(_out_T_7972, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_820 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_820 = orr(_out_rimask_T_820) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_820 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_820 = andr(_out_wimask_T_820) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_820 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_820 = orr(_out_romask_T_820) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_820 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_820 = andr(_out_womask_T_820) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_820 = and(out_rivalid_1[698], out_rimask_820) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_820 = and(out_roready_1[698], out_romask_820) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_820 = and(out_wivalid_1[698], out_wimask_820) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_820 = and(out_woready_1[698], out_womask_820) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7974 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7975 = and(out_f_rivalid_820, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7976 = and(UInt<1>(0h1), out_f_roready_820) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7977 = eq(out_rimask_820, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7978 = eq(out_wimask_820, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7979 = eq(out_romask_820, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7980 = eq(out_womask_820, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_701 = or(_out_T_7973, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_701 = cat(_T_1129, _out_prepend_T_701) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7981 = or(out_prepend_701, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7982 = bits(_out_T_7981, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_821 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_821 = orr(_out_rimask_T_821) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_821 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_821 = andr(_out_wimask_T_821) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_821 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_821 = orr(_out_romask_T_821) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_821 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_821 = andr(_out_womask_T_821) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_821 = and(out_rivalid_1[699], out_rimask_821) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_821 = and(out_roready_1[699], out_romask_821) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_821 = and(out_wivalid_1[699], out_wimask_821) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_821 = and(out_woready_1[699], out_womask_821) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7983 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7984 = and(out_f_rivalid_821, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7985 = and(UInt<1>(0h1), out_f_roready_821) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7986 = eq(out_rimask_821, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7987 = eq(out_wimask_821, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7988 = eq(out_romask_821, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7989 = eq(out_womask_821, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7990 = or(_T_658, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7991 = bits(_out_T_7990, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_822 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_822 = orr(_out_rimask_T_822) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_822 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_822 = andr(_out_wimask_T_822) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_822 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_822 = orr(_out_romask_T_822) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_822 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_822 = andr(_out_womask_T_822) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_822 = and(out_rivalid_1[700], out_rimask_822) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_822 = and(out_roready_1[700], out_romask_822) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_822 = and(out_wivalid_1[700], out_wimask_822) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_822 = and(out_woready_1[700], out_womask_822) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7992 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7993 = and(out_f_rivalid_822, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7994 = and(UInt<1>(0h1), out_f_roready_822) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7995 = eq(out_rimask_822, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7996 = eq(out_wimask_822, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7997 = eq(out_romask_822, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7998 = eq(out_womask_822, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_702 = or(_out_T_7991, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_702 = cat(_T_659, _out_prepend_T_702) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7999 = or(out_prepend_702, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8000 = bits(_out_T_7999, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_823 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_823 = orr(_out_rimask_T_823) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_823 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_823 = andr(_out_wimask_T_823) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_823 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_823 = orr(_out_romask_T_823) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_823 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_823 = andr(_out_womask_T_823) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_823 = and(out_rivalid_1[701], out_rimask_823) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_823 = and(out_roready_1[701], out_romask_823) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_823 = and(out_wivalid_1[701], out_wimask_823) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_823 = and(out_woready_1[701], out_womask_823) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8001 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8002 = and(out_f_rivalid_823, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8003 = and(UInt<1>(0h1), out_f_roready_823) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8004 = eq(out_rimask_823, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8005 = eq(out_wimask_823, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8006 = eq(out_romask_823, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8007 = eq(out_womask_823, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_703 = or(_out_T_8000, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_703 = cat(_T_660, _out_prepend_T_703) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8008 = or(out_prepend_703, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8009 = bits(_out_T_8008, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_824 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_824 = orr(_out_rimask_T_824) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_824 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_824 = andr(_out_wimask_T_824) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_824 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_824 = orr(_out_romask_T_824) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_824 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_824 = andr(_out_womask_T_824) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_824 = and(out_rivalid_1[702], out_rimask_824) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_824 = and(out_roready_1[702], out_romask_824) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_824 = and(out_wivalid_1[702], out_wimask_824) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_824 = and(out_woready_1[702], out_womask_824) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8010 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8011 = and(out_f_rivalid_824, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8012 = and(UInt<1>(0h1), out_f_roready_824) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8013 = eq(out_rimask_824, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8014 = eq(out_wimask_824, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8015 = eq(out_romask_824, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8016 = eq(out_womask_824, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_704 = or(_out_T_8009, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_704 = cat(_T_661, _out_prepend_T_704) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8017 = or(out_prepend_704, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8018 = bits(_out_T_8017, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_825 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_825 = orr(_out_rimask_T_825) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_825 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_825 = andr(_out_wimask_T_825) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_825 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_825 = orr(_out_romask_T_825) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_825 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_825 = andr(_out_womask_T_825) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_825 = and(out_rivalid_1[703], out_rimask_825) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_825 = and(out_roready_1[703], out_romask_825) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_825 = and(out_wivalid_1[703], out_wimask_825) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_825 = and(out_woready_1[703], out_womask_825) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8019 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8020 = and(out_f_rivalid_825, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8021 = and(UInt<1>(0h1), out_f_roready_825) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8022 = eq(out_rimask_825, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8023 = eq(out_wimask_825, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8024 = eq(out_romask_825, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8025 = eq(out_womask_825, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_705 = or(_out_T_8018, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_705 = cat(_T_662, _out_prepend_T_705) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8026 = or(out_prepend_705, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8027 = bits(_out_T_8026, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_826 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_826 = orr(_out_rimask_T_826) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_826 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_826 = andr(_out_wimask_T_826) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_826 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_826 = orr(_out_romask_T_826) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_826 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_826 = andr(_out_womask_T_826) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_826 = and(out_rivalid_1[704], out_rimask_826) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_826 = and(out_roready_1[704], out_romask_826) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_826 = and(out_wivalid_1[704], out_wimask_826) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_826 = and(out_woready_1[704], out_womask_826) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8028 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8029 = and(out_f_rivalid_826, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8030 = and(UInt<1>(0h1), out_f_roready_826) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8031 = eq(out_rimask_826, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8032 = eq(out_wimask_826, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8033 = eq(out_romask_826, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8034 = eq(out_womask_826, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_706 = or(_out_T_8027, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_706 = cat(_T_663, _out_prepend_T_706) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8035 = or(out_prepend_706, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8036 = bits(_out_T_8035, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_827 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_827 = orr(_out_rimask_T_827) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_827 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_827 = andr(_out_wimask_T_827) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_827 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_827 = orr(_out_romask_T_827) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_827 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_827 = andr(_out_womask_T_827) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_827 = and(out_rivalid_1[705], out_rimask_827) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_827 = and(out_roready_1[705], out_romask_827) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_827 = and(out_wivalid_1[705], out_wimask_827) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_827 = and(out_woready_1[705], out_womask_827) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8037 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8038 = and(out_f_rivalid_827, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8039 = and(UInt<1>(0h1), out_f_roready_827) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8040 = eq(out_rimask_827, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8041 = eq(out_wimask_827, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8042 = eq(out_romask_827, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8043 = eq(out_womask_827, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_707 = or(_out_T_8036, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_707 = cat(_T_664, _out_prepend_T_707) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8044 = or(out_prepend_707, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8045 = bits(_out_T_8044, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_828 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_828 = orr(_out_rimask_T_828) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_828 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_828 = andr(_out_wimask_T_828) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_828 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_828 = orr(_out_romask_T_828) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_828 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_828 = andr(_out_womask_T_828) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_828 = and(out_rivalid_1[706], out_rimask_828) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_828 = and(out_roready_1[706], out_romask_828) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_828 = and(out_wivalid_1[706], out_wimask_828) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_828 = and(out_woready_1[706], out_womask_828) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8046 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8047 = and(out_f_rivalid_828, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8048 = and(UInt<1>(0h1), out_f_roready_828) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8049 = eq(out_rimask_828, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8050 = eq(out_wimask_828, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8051 = eq(out_romask_828, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8052 = eq(out_womask_828, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_708 = or(_out_T_8045, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_708 = cat(_T_665, _out_prepend_T_708) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8053 = or(out_prepend_708, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8054 = bits(_out_T_8053, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_829 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_829 = orr(_out_rimask_T_829) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_829 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_829 = andr(_out_wimask_T_829) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_829 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_829 = orr(_out_romask_T_829) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_829 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_829 = andr(_out_womask_T_829) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_829 = and(out_rivalid_1[707], out_rimask_829) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_829 = and(out_roready_1[707], out_romask_829) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_829 = and(out_wivalid_1[707], out_wimask_829) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_829 = and(out_woready_1[707], out_womask_829) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8055 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8056 = and(out_f_rivalid_829, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8057 = and(UInt<1>(0h1), out_f_roready_829) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8058 = eq(out_rimask_829, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8059 = eq(out_wimask_829, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8060 = eq(out_romask_829, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8061 = eq(out_womask_829, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8062 = or(_T_1002, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8063 = bits(_out_T_8062, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_830 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_830 = orr(_out_rimask_T_830) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_830 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_830 = andr(_out_wimask_T_830) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_830 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_830 = orr(_out_romask_T_830) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_830 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_830 = andr(_out_womask_T_830) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_830 = and(out_rivalid_1[708], out_rimask_830) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_830 = and(out_roready_1[708], out_romask_830) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_830 = and(out_wivalid_1[708], out_wimask_830) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_830 = and(out_woready_1[708], out_womask_830) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8064 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8065 = and(out_f_rivalid_830, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8066 = and(UInt<1>(0h1), out_f_roready_830) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8067 = eq(out_rimask_830, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8068 = eq(out_wimask_830, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8069 = eq(out_romask_830, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8070 = eq(out_womask_830, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_709 = or(_out_T_8063, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_709 = cat(_T_1003, _out_prepend_T_709) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8071 = or(out_prepend_709, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8072 = bits(_out_T_8071, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_831 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_831 = orr(_out_rimask_T_831) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_831 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_831 = andr(_out_wimask_T_831) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_831 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_831 = orr(_out_romask_T_831) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_831 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_831 = andr(_out_womask_T_831) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_831 = and(out_rivalid_1[709], out_rimask_831) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_831 = and(out_roready_1[709], out_romask_831) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_831 = and(out_wivalid_1[709], out_wimask_831) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_831 = and(out_woready_1[709], out_womask_831) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8073 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8074 = and(out_f_rivalid_831, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8075 = and(UInt<1>(0h1), out_f_roready_831) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8076 = eq(out_rimask_831, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8077 = eq(out_wimask_831, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8078 = eq(out_romask_831, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8079 = eq(out_womask_831, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_710 = or(_out_T_8072, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_710 = cat(_T_1004, _out_prepend_T_710) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8080 = or(out_prepend_710, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8081 = bits(_out_T_8080, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_832 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_832 = orr(_out_rimask_T_832) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_832 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_832 = andr(_out_wimask_T_832) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_832 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_832 = orr(_out_romask_T_832) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_832 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_832 = andr(_out_womask_T_832) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_832 = and(out_rivalid_1[710], out_rimask_832) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_832 = and(out_roready_1[710], out_romask_832) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_832 = and(out_wivalid_1[710], out_wimask_832) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_832 = and(out_woready_1[710], out_womask_832) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8082 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8083 = and(out_f_rivalid_832, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8084 = and(UInt<1>(0h1), out_f_roready_832) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8085 = eq(out_rimask_832, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8086 = eq(out_wimask_832, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8087 = eq(out_romask_832, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8088 = eq(out_womask_832, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_711 = or(_out_T_8081, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_711 = cat(_T_1005, _out_prepend_T_711) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8089 = or(out_prepend_711, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8090 = bits(_out_T_8089, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_833 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_833 = orr(_out_rimask_T_833) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_833 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_833 = andr(_out_wimask_T_833) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_833 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_833 = orr(_out_romask_T_833) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_833 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_833 = andr(_out_womask_T_833) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_833 = and(out_rivalid_1[711], out_rimask_833) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_833 = and(out_roready_1[711], out_romask_833) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_833 = and(out_wivalid_1[711], out_wimask_833) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_833 = and(out_woready_1[711], out_womask_833) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8091 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8092 = and(out_f_rivalid_833, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8093 = and(UInt<1>(0h1), out_f_roready_833) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8094 = eq(out_rimask_833, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8095 = eq(out_wimask_833, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8096 = eq(out_romask_833, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8097 = eq(out_womask_833, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_712 = or(_out_T_8090, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_712 = cat(_T_1006, _out_prepend_T_712) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8098 = or(out_prepend_712, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8099 = bits(_out_T_8098, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_834 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_834 = orr(_out_rimask_T_834) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_834 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_834 = andr(_out_wimask_T_834) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_834 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_834 = orr(_out_romask_T_834) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_834 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_834 = andr(_out_womask_T_834) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_834 = and(out_rivalid_1[712], out_rimask_834) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_834 = and(out_roready_1[712], out_romask_834) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_834 = and(out_wivalid_1[712], out_wimask_834) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_834 = and(out_woready_1[712], out_womask_834) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8100 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8101 = and(out_f_rivalid_834, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8102 = and(UInt<1>(0h1), out_f_roready_834) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8103 = eq(out_rimask_834, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8104 = eq(out_wimask_834, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8105 = eq(out_romask_834, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8106 = eq(out_womask_834, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_713 = or(_out_T_8099, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_713 = cat(_T_1007, _out_prepend_T_713) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8107 = or(out_prepend_713, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8108 = bits(_out_T_8107, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_835 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_835 = orr(_out_rimask_T_835) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_835 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_835 = andr(_out_wimask_T_835) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_835 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_835 = orr(_out_romask_T_835) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_835 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_835 = andr(_out_womask_T_835) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_835 = and(out_rivalid_1[713], out_rimask_835) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_835 = and(out_roready_1[713], out_romask_835) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_835 = and(out_wivalid_1[713], out_wimask_835) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_835 = and(out_woready_1[713], out_womask_835) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8109 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8110 = and(out_f_rivalid_835, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8111 = and(UInt<1>(0h1), out_f_roready_835) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8112 = eq(out_rimask_835, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8113 = eq(out_wimask_835, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8114 = eq(out_romask_835, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8115 = eq(out_womask_835, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_714 = or(_out_T_8108, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_714 = cat(_T_1008, _out_prepend_T_714) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8116 = or(out_prepend_714, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8117 = bits(_out_T_8116, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_836 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_836 = orr(_out_rimask_T_836) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_836 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_836 = andr(_out_wimask_T_836) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_836 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_836 = orr(_out_romask_T_836) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_836 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_836 = andr(_out_womask_T_836) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_836 = and(out_rivalid_1[714], out_rimask_836) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_836 = and(out_roready_1[714], out_romask_836) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_836 = and(out_wivalid_1[714], out_wimask_836) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_836 = and(out_woready_1[714], out_womask_836) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8118 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8119 = and(out_f_rivalid_836, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8120 = and(UInt<1>(0h1), out_f_roready_836) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8121 = eq(out_rimask_836, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8122 = eq(out_wimask_836, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8123 = eq(out_romask_836, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8124 = eq(out_womask_836, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_715 = or(_out_T_8117, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_715 = cat(_T_1009, _out_prepend_T_715) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8125 = or(out_prepend_715, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8126 = bits(_out_T_8125, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_837 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_837 = orr(_out_rimask_T_837) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_837 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_837 = andr(_out_wimask_T_837) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_837 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_837 = orr(_out_romask_T_837) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_837 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_837 = andr(_out_womask_T_837) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_837 = and(out_rivalid_1[715], out_rimask_837) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_837 = and(out_roready_1[715], out_romask_837) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_837 = and(out_wivalid_1[715], out_wimask_837) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_837 = and(out_woready_1[715], out_womask_837) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8127 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_837 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[32], _out_T_8127 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_8128 = and(out_f_rivalid_837, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8129 = and(UInt<1>(0h1), out_f_roready_837) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8130 = and(out_f_wivalid_837, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8131 = and(UInt<1>(0h1), out_f_woready_837) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8132 = eq(out_rimask_837, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8133 = eq(out_wimask_837, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8134 = eq(out_romask_837, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8135 = eq(out_womask_837, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8136 = or(programBufferMem[32], UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8137 = bits(_out_T_8136, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_838 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_838 = orr(_out_rimask_T_838) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_838 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_838 = andr(_out_wimask_T_838) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_838 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_838 = orr(_out_romask_T_838) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_838 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_838 = andr(_out_womask_T_838) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_838 = and(out_rivalid_1[716], out_rimask_838) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_838 = and(out_roready_1[716], out_romask_838) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_838 = and(out_wivalid_1[716], out_wimask_838) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_838 = and(out_woready_1[716], out_womask_838) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8138 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_838 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[33], _out_T_8138 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_8139 = and(out_f_rivalid_838, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8140 = and(UInt<1>(0h1), out_f_roready_838) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8141 = and(out_f_wivalid_838, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8142 = and(UInt<1>(0h1), out_f_woready_838) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8143 = eq(out_rimask_838, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8144 = eq(out_wimask_838, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8145 = eq(out_romask_838, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8146 = eq(out_womask_838, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_716 = or(_out_T_8137, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_716 = cat(programBufferMem[33], _out_prepend_T_716) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8147 = or(out_prepend_716, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8148 = bits(_out_T_8147, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_839 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_839 = orr(_out_rimask_T_839) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_839 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_839 = andr(_out_wimask_T_839) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_839 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_839 = orr(_out_romask_T_839) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_839 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_839 = andr(_out_womask_T_839) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_839 = and(out_rivalid_1[717], out_rimask_839) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_839 = and(out_roready_1[717], out_romask_839) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_839 = and(out_wivalid_1[717], out_wimask_839) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_839 = and(out_woready_1[717], out_womask_839) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8149 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_839 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[34], _out_T_8149 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_8150 = and(out_f_rivalid_839, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8151 = and(UInt<1>(0h1), out_f_roready_839) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8152 = and(out_f_wivalid_839, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8153 = and(UInt<1>(0h1), out_f_woready_839) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8154 = eq(out_rimask_839, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8155 = eq(out_wimask_839, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8156 = eq(out_romask_839, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8157 = eq(out_womask_839, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_717 = or(_out_T_8148, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_717 = cat(programBufferMem[34], _out_prepend_T_717) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8158 = or(out_prepend_717, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8159 = bits(_out_T_8158, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_840 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_840 = orr(_out_rimask_T_840) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_840 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_840 = andr(_out_wimask_T_840) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_840 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_840 = orr(_out_romask_T_840) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_840 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_840 = andr(_out_womask_T_840) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_840 = and(out_rivalid_1[718], out_rimask_840) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_840 = and(out_roready_1[718], out_romask_840) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_840 = and(out_wivalid_1[718], out_wimask_840) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_840 = and(out_woready_1[718], out_womask_840) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8160 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_840 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[35], _out_T_8160 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_8161 = and(out_f_rivalid_840, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8162 = and(UInt<1>(0h1), out_f_roready_840) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8163 = and(out_f_wivalid_840, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8164 = and(UInt<1>(0h1), out_f_woready_840) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8165 = eq(out_rimask_840, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8166 = eq(out_wimask_840, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8167 = eq(out_romask_840, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8168 = eq(out_womask_840, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_718 = or(_out_T_8159, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_718 = cat(programBufferMem[35], _out_prepend_T_718) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8169 = or(out_prepend_718, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8170 = bits(_out_T_8169, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_841 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_841 = orr(_out_rimask_T_841) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_841 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_841 = andr(_out_wimask_T_841) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_841 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_841 = orr(_out_romask_T_841) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_841 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_841 = andr(_out_womask_T_841) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_841 = and(out_rivalid_1[719], out_rimask_841) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_841 = and(out_roready_1[719], out_romask_841) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_841 = and(out_wivalid_1[719], out_wimask_841) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_841 = and(out_woready_1[719], out_womask_841) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8171 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_841 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[36], _out_T_8171 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_8172 = and(out_f_rivalid_841, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8173 = and(UInt<1>(0h1), out_f_roready_841) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8174 = and(out_f_wivalid_841, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8175 = and(UInt<1>(0h1), out_f_woready_841) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8176 = eq(out_rimask_841, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8177 = eq(out_wimask_841, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8178 = eq(out_romask_841, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8179 = eq(out_womask_841, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_719 = or(_out_T_8170, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_719 = cat(programBufferMem[36], _out_prepend_T_719) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8180 = or(out_prepend_719, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8181 = bits(_out_T_8180, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_842 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_842 = orr(_out_rimask_T_842) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_842 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_842 = andr(_out_wimask_T_842) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_842 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_842 = orr(_out_romask_T_842) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_842 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_842 = andr(_out_womask_T_842) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_842 = and(out_rivalid_1[720], out_rimask_842) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_842 = and(out_roready_1[720], out_romask_842) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_842 = and(out_wivalid_1[720], out_wimask_842) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_842 = and(out_woready_1[720], out_womask_842) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8182 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_842 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[37], _out_T_8182 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_8183 = and(out_f_rivalid_842, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8184 = and(UInt<1>(0h1), out_f_roready_842) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8185 = and(out_f_wivalid_842, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8186 = and(UInt<1>(0h1), out_f_woready_842) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8187 = eq(out_rimask_842, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8188 = eq(out_wimask_842, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8189 = eq(out_romask_842, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8190 = eq(out_womask_842, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_720 = or(_out_T_8181, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_720 = cat(programBufferMem[37], _out_prepend_T_720) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8191 = or(out_prepend_720, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8192 = bits(_out_T_8191, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_843 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_843 = orr(_out_rimask_T_843) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_843 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_843 = andr(_out_wimask_T_843) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_843 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_843 = orr(_out_romask_T_843) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_843 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_843 = andr(_out_womask_T_843) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_843 = and(out_rivalid_1[721], out_rimask_843) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_843 = and(out_roready_1[721], out_romask_843) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_843 = and(out_wivalid_1[721], out_wimask_843) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_843 = and(out_woready_1[721], out_womask_843) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8193 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_843 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[38], _out_T_8193 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_8194 = and(out_f_rivalid_843, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8195 = and(UInt<1>(0h1), out_f_roready_843) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8196 = and(out_f_wivalid_843, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8197 = and(UInt<1>(0h1), out_f_woready_843) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8198 = eq(out_rimask_843, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8199 = eq(out_wimask_843, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8200 = eq(out_romask_843, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8201 = eq(out_womask_843, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_721 = or(_out_T_8192, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_721 = cat(programBufferMem[38], _out_prepend_T_721) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8202 = or(out_prepend_721, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8203 = bits(_out_T_8202, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_844 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_844 = orr(_out_rimask_T_844) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_844 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_844 = andr(_out_wimask_T_844) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_844 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_844 = orr(_out_romask_T_844) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_844 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_844 = andr(_out_womask_T_844) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_844 = and(out_rivalid_1[722], out_rimask_844) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_844 = and(out_roready_1[722], out_romask_844) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_844 = and(out_wivalid_1[722], out_wimask_844) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_844 = and(out_woready_1[722], out_womask_844) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8204 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_844 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[39], _out_T_8204 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_8205 = and(out_f_rivalid_844, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8206 = and(UInt<1>(0h1), out_f_roready_844) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8207 = and(out_f_wivalid_844, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8208 = and(UInt<1>(0h1), out_f_woready_844) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8209 = eq(out_rimask_844, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8210 = eq(out_wimask_844, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8211 = eq(out_romask_844, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8212 = eq(out_womask_844, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_722 = or(_out_T_8203, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_722 = cat(programBufferMem[39], _out_prepend_T_722) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8213 = or(out_prepend_722, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8214 = bits(_out_T_8213, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_845 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_845 = orr(_out_rimask_T_845) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_845 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_845 = andr(_out_wimask_T_845) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_845 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_845 = orr(_out_romask_T_845) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_845 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_845 = andr(_out_womask_T_845) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_845 = and(out_rivalid_1[723], out_rimask_845) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_845 = and(out_roready_1[723], out_romask_845) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_845 = and(out_wivalid_1[723], out_wimask_845) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_845 = and(out_woready_1[723], out_womask_845) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8215 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8216 = and(out_f_rivalid_845, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8217 = and(UInt<1>(0h1), out_f_roready_845) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8218 = eq(out_rimask_845, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8219 = eq(out_wimask_845, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8220 = eq(out_romask_845, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8221 = eq(out_womask_845, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8222 = or(_T_1338, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8223 = bits(_out_T_8222, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_846 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_846 = orr(_out_rimask_T_846) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_846 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_846 = andr(_out_wimask_T_846) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_846 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_846 = orr(_out_romask_T_846) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_846 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_846 = andr(_out_womask_T_846) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_846 = and(out_rivalid_1[724], out_rimask_846) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_846 = and(out_roready_1[724], out_romask_846) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_846 = and(out_wivalid_1[724], out_wimask_846) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_846 = and(out_woready_1[724], out_womask_846) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8224 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8225 = and(out_f_rivalid_846, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8226 = and(UInt<1>(0h1), out_f_roready_846) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8227 = eq(out_rimask_846, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8228 = eq(out_wimask_846, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8229 = eq(out_romask_846, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8230 = eq(out_womask_846, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_723 = or(_out_T_8223, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_723 = cat(_T_1339, _out_prepend_T_723) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8231 = or(out_prepend_723, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8232 = bits(_out_T_8231, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_847 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_847 = orr(_out_rimask_T_847) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_847 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_847 = andr(_out_wimask_T_847) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_847 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_847 = orr(_out_romask_T_847) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_847 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_847 = andr(_out_womask_T_847) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_847 = and(out_rivalid_1[725], out_rimask_847) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_847 = and(out_roready_1[725], out_romask_847) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_847 = and(out_wivalid_1[725], out_wimask_847) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_847 = and(out_woready_1[725], out_womask_847) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8233 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8234 = and(out_f_rivalid_847, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8235 = and(UInt<1>(0h1), out_f_roready_847) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8236 = eq(out_rimask_847, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8237 = eq(out_wimask_847, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8238 = eq(out_romask_847, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8239 = eq(out_womask_847, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_724 = or(_out_T_8232, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_724 = cat(_T_1340, _out_prepend_T_724) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8240 = or(out_prepend_724, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8241 = bits(_out_T_8240, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_848 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_848 = orr(_out_rimask_T_848) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_848 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_848 = andr(_out_wimask_T_848) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_848 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_848 = orr(_out_romask_T_848) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_848 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_848 = andr(_out_womask_T_848) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_848 = and(out_rivalid_1[726], out_rimask_848) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_848 = and(out_roready_1[726], out_romask_848) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_848 = and(out_wivalid_1[726], out_wimask_848) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_848 = and(out_woready_1[726], out_womask_848) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8242 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8243 = and(out_f_rivalid_848, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8244 = and(UInt<1>(0h1), out_f_roready_848) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8245 = eq(out_rimask_848, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8246 = eq(out_wimask_848, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8247 = eq(out_romask_848, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8248 = eq(out_womask_848, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_725 = or(_out_T_8241, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_725 = cat(_T_1341, _out_prepend_T_725) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8249 = or(out_prepend_725, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8250 = bits(_out_T_8249, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_849 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_849 = orr(_out_rimask_T_849) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_849 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_849 = andr(_out_wimask_T_849) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_849 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_849 = orr(_out_romask_T_849) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_849 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_849 = andr(_out_womask_T_849) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_849 = and(out_rivalid_1[727], out_rimask_849) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_849 = and(out_roready_1[727], out_romask_849) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_849 = and(out_wivalid_1[727], out_wimask_849) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_849 = and(out_woready_1[727], out_womask_849) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8251 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8252 = and(out_f_rivalid_849, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8253 = and(UInt<1>(0h1), out_f_roready_849) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8254 = eq(out_rimask_849, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8255 = eq(out_wimask_849, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8256 = eq(out_romask_849, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8257 = eq(out_womask_849, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_726 = or(_out_T_8250, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_726 = cat(_T_1342, _out_prepend_T_726) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8258 = or(out_prepend_726, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8259 = bits(_out_T_8258, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_850 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_850 = orr(_out_rimask_T_850) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_850 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_850 = andr(_out_wimask_T_850) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_850 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_850 = orr(_out_romask_T_850) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_850 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_850 = andr(_out_womask_T_850) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_850 = and(out_rivalid_1[728], out_rimask_850) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_850 = and(out_roready_1[728], out_romask_850) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_850 = and(out_wivalid_1[728], out_wimask_850) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_850 = and(out_woready_1[728], out_womask_850) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8260 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8261 = and(out_f_rivalid_850, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8262 = and(UInt<1>(0h1), out_f_roready_850) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8263 = eq(out_rimask_850, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8264 = eq(out_wimask_850, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8265 = eq(out_romask_850, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8266 = eq(out_womask_850, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_727 = or(_out_T_8259, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_727 = cat(_T_1343, _out_prepend_T_727) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8267 = or(out_prepend_727, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8268 = bits(_out_T_8267, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_851 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_851 = orr(_out_rimask_T_851) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_851 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_851 = andr(_out_wimask_T_851) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_851 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_851 = orr(_out_romask_T_851) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_851 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_851 = andr(_out_womask_T_851) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_851 = and(out_rivalid_1[729], out_rimask_851) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_851 = and(out_roready_1[729], out_romask_851) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_851 = and(out_wivalid_1[729], out_wimask_851) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_851 = and(out_woready_1[729], out_womask_851) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8269 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8270 = and(out_f_rivalid_851, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8271 = and(UInt<1>(0h1), out_f_roready_851) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8272 = eq(out_rimask_851, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8273 = eq(out_wimask_851, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8274 = eq(out_romask_851, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8275 = eq(out_womask_851, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_728 = or(_out_T_8268, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_728 = cat(_T_1344, _out_prepend_T_728) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8276 = or(out_prepend_728, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8277 = bits(_out_T_8276, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_852 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_852 = orr(_out_rimask_T_852) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_852 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_852 = andr(_out_wimask_T_852) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_852 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_852 = orr(_out_romask_T_852) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_852 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_852 = andr(_out_womask_T_852) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_852 = and(out_rivalid_1[730], out_rimask_852) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_852 = and(out_roready_1[730], out_romask_852) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_852 = and(out_wivalid_1[730], out_wimask_852) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_852 = and(out_woready_1[730], out_womask_852) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8278 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8279 = and(out_f_rivalid_852, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8280 = and(UInt<1>(0h1), out_f_roready_852) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8281 = eq(out_rimask_852, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8282 = eq(out_wimask_852, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8283 = eq(out_romask_852, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8284 = eq(out_womask_852, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_729 = or(_out_T_8277, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_729 = cat(_T_1345, _out_prepend_T_729) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8285 = or(out_prepend_729, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8286 = bits(_out_T_8285, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_853 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_853 = orr(_out_rimask_T_853) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_853 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_853 = andr(_out_wimask_T_853) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_853 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_853 = orr(_out_romask_T_853) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_853 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_853 = andr(_out_womask_T_853) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_853 = and(out_rivalid_1[731], out_rimask_853) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_853 = and(out_roready_1[731], out_romask_853) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_853 = and(out_wivalid_1[731], out_wimask_853) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_853 = and(out_woready_1[731], out_womask_853) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8287 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8288 = and(out_f_rivalid_853, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8289 = and(UInt<1>(0h1), out_f_roready_853) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8290 = eq(out_rimask_853, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8291 = eq(out_wimask_853, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8292 = eq(out_romask_853, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8293 = eq(out_womask_853, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8294 = or(_T_1426, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8295 = bits(_out_T_8294, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_854 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_854 = orr(_out_rimask_T_854) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_854 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_854 = andr(_out_wimask_T_854) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_854 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_854 = orr(_out_romask_T_854) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_854 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_854 = andr(_out_womask_T_854) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_854 = and(out_rivalid_1[732], out_rimask_854) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_854 = and(out_roready_1[732], out_romask_854) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_854 = and(out_wivalid_1[732], out_wimask_854) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_854 = and(out_woready_1[732], out_womask_854) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8296 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8297 = and(out_f_rivalid_854, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8298 = and(UInt<1>(0h1), out_f_roready_854) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8299 = eq(out_rimask_854, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8300 = eq(out_wimask_854, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8301 = eq(out_romask_854, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8302 = eq(out_womask_854, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_730 = or(_out_T_8295, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_730 = cat(_T_1427, _out_prepend_T_730) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8303 = or(out_prepend_730, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8304 = bits(_out_T_8303, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_855 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_855 = orr(_out_rimask_T_855) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_855 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_855 = andr(_out_wimask_T_855) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_855 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_855 = orr(_out_romask_T_855) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_855 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_855 = andr(_out_womask_T_855) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_855 = and(out_rivalid_1[733], out_rimask_855) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_855 = and(out_roready_1[733], out_romask_855) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_855 = and(out_wivalid_1[733], out_wimask_855) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_855 = and(out_woready_1[733], out_womask_855) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8305 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8306 = and(out_f_rivalid_855, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8307 = and(UInt<1>(0h1), out_f_roready_855) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8308 = eq(out_rimask_855, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8309 = eq(out_wimask_855, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8310 = eq(out_romask_855, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8311 = eq(out_womask_855, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_731 = or(_out_T_8304, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_731 = cat(_T_1428, _out_prepend_T_731) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8312 = or(out_prepend_731, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8313 = bits(_out_T_8312, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_856 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_856 = orr(_out_rimask_T_856) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_856 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_856 = andr(_out_wimask_T_856) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_856 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_856 = orr(_out_romask_T_856) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_856 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_856 = andr(_out_womask_T_856) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_856 = and(out_rivalid_1[734], out_rimask_856) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_856 = and(out_roready_1[734], out_romask_856) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_856 = and(out_wivalid_1[734], out_wimask_856) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_856 = and(out_woready_1[734], out_womask_856) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8314 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8315 = and(out_f_rivalid_856, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8316 = and(UInt<1>(0h1), out_f_roready_856) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8317 = eq(out_rimask_856, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8318 = eq(out_wimask_856, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8319 = eq(out_romask_856, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8320 = eq(out_womask_856, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_732 = or(_out_T_8313, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_732 = cat(_T_1429, _out_prepend_T_732) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8321 = or(out_prepend_732, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8322 = bits(_out_T_8321, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_857 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_857 = orr(_out_rimask_T_857) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_857 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_857 = andr(_out_wimask_T_857) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_857 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_857 = orr(_out_romask_T_857) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_857 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_857 = andr(_out_womask_T_857) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_857 = and(out_rivalid_1[735], out_rimask_857) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_857 = and(out_roready_1[735], out_romask_857) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_857 = and(out_wivalid_1[735], out_wimask_857) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_857 = and(out_woready_1[735], out_womask_857) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8323 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8324 = and(out_f_rivalid_857, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8325 = and(UInt<1>(0h1), out_f_roready_857) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8326 = eq(out_rimask_857, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8327 = eq(out_wimask_857, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8328 = eq(out_romask_857, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8329 = eq(out_womask_857, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_733 = or(_out_T_8322, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_733 = cat(_T_1430, _out_prepend_T_733) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8330 = or(out_prepend_733, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8331 = bits(_out_T_8330, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_858 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_858 = orr(_out_rimask_T_858) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_858 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_858 = andr(_out_wimask_T_858) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_858 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_858 = orr(_out_romask_T_858) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_858 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_858 = andr(_out_womask_T_858) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_858 = and(out_rivalid_1[736], out_rimask_858) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_858 = and(out_roready_1[736], out_romask_858) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_858 = and(out_wivalid_1[736], out_wimask_858) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_858 = and(out_woready_1[736], out_womask_858) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8332 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8333 = and(out_f_rivalid_858, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8334 = and(UInt<1>(0h1), out_f_roready_858) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8335 = eq(out_rimask_858, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8336 = eq(out_wimask_858, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8337 = eq(out_romask_858, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8338 = eq(out_womask_858, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_734 = or(_out_T_8331, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_734 = cat(_T_1431, _out_prepend_T_734) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8339 = or(out_prepend_734, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8340 = bits(_out_T_8339, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_859 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_859 = orr(_out_rimask_T_859) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_859 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_859 = andr(_out_wimask_T_859) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_859 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_859 = orr(_out_romask_T_859) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_859 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_859 = andr(_out_womask_T_859) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_859 = and(out_rivalid_1[737], out_rimask_859) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_859 = and(out_roready_1[737], out_romask_859) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_859 = and(out_wivalid_1[737], out_wimask_859) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_859 = and(out_woready_1[737], out_womask_859) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8341 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8342 = and(out_f_rivalid_859, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8343 = and(UInt<1>(0h1), out_f_roready_859) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8344 = eq(out_rimask_859, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8345 = eq(out_wimask_859, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8346 = eq(out_romask_859, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8347 = eq(out_womask_859, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_735 = or(_out_T_8340, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_735 = cat(_T_1432, _out_prepend_T_735) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8348 = or(out_prepend_735, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8349 = bits(_out_T_8348, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_860 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_860 = orr(_out_rimask_T_860) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_860 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_860 = andr(_out_wimask_T_860) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_860 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_860 = orr(_out_romask_T_860) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_860 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_860 = andr(_out_womask_T_860) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_860 = and(out_rivalid_1[738], out_rimask_860) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_860 = and(out_roready_1[738], out_romask_860) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_860 = and(out_wivalid_1[738], out_wimask_860) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_860 = and(out_woready_1[738], out_womask_860) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8350 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8351 = and(out_f_rivalid_860, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8352 = and(UInt<1>(0h1), out_f_roready_860) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8353 = eq(out_rimask_860, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8354 = eq(out_wimask_860, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8355 = eq(out_romask_860, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8356 = eq(out_womask_860, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_736 = or(_out_T_8349, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_736 = cat(_T_1433, _out_prepend_T_736) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8357 = or(out_prepend_736, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8358 = bits(_out_T_8357, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_861 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_861 = orr(_out_rimask_T_861) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_861 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_861 = andr(_out_wimask_T_861) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_861 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_861 = orr(_out_romask_T_861) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_861 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_861 = andr(_out_womask_T_861) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_861 = and(out_rivalid_1[739], out_rimask_861) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_861 = and(out_roready_1[739], out_romask_861) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_861 = and(out_wivalid_1[739], out_wimask_861) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_861 = and(out_woready_1[739], out_womask_861) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8359 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8360 = and(out_f_rivalid_861, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8361 = and(UInt<1>(0h1), out_f_roready_861) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8362 = eq(out_rimask_861, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8363 = eq(out_wimask_861, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8364 = eq(out_romask_861, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8365 = eq(out_womask_861, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8366 = or(_T_458, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8367 = bits(_out_T_8366, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_862 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_862 = orr(_out_rimask_T_862) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_862 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_862 = andr(_out_wimask_T_862) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_862 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_862 = orr(_out_romask_T_862) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_862 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_862 = andr(_out_womask_T_862) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_862 = and(out_rivalid_1[740], out_rimask_862) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_862 = and(out_roready_1[740], out_romask_862) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_862 = and(out_wivalid_1[740], out_wimask_862) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_862 = and(out_woready_1[740], out_womask_862) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8368 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8369 = and(out_f_rivalid_862, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8370 = and(UInt<1>(0h1), out_f_roready_862) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8371 = eq(out_rimask_862, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8372 = eq(out_wimask_862, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8373 = eq(out_romask_862, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8374 = eq(out_womask_862, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_737 = or(_out_T_8367, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_737 = cat(_T_459, _out_prepend_T_737) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8375 = or(out_prepend_737, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8376 = bits(_out_T_8375, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_863 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_863 = orr(_out_rimask_T_863) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_863 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_863 = andr(_out_wimask_T_863) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_863 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_863 = orr(_out_romask_T_863) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_863 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_863 = andr(_out_womask_T_863) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_863 = and(out_rivalid_1[741], out_rimask_863) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_863 = and(out_roready_1[741], out_romask_863) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_863 = and(out_wivalid_1[741], out_wimask_863) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_863 = and(out_woready_1[741], out_womask_863) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8377 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8378 = and(out_f_rivalid_863, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8379 = and(UInt<1>(0h1), out_f_roready_863) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8380 = eq(out_rimask_863, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8381 = eq(out_wimask_863, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8382 = eq(out_romask_863, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8383 = eq(out_womask_863, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_738 = or(_out_T_8376, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_738 = cat(_T_460, _out_prepend_T_738) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8384 = or(out_prepend_738, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8385 = bits(_out_T_8384, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_864 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_864 = orr(_out_rimask_T_864) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_864 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_864 = andr(_out_wimask_T_864) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_864 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_864 = orr(_out_romask_T_864) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_864 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_864 = andr(_out_womask_T_864) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_864 = and(out_rivalid_1[742], out_rimask_864) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_864 = and(out_roready_1[742], out_romask_864) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_864 = and(out_wivalid_1[742], out_wimask_864) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_864 = and(out_woready_1[742], out_womask_864) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8386 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8387 = and(out_f_rivalid_864, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8388 = and(UInt<1>(0h1), out_f_roready_864) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8389 = eq(out_rimask_864, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8390 = eq(out_wimask_864, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8391 = eq(out_romask_864, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8392 = eq(out_womask_864, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_739 = or(_out_T_8385, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_739 = cat(_T_461, _out_prepend_T_739) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8393 = or(out_prepend_739, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8394 = bits(_out_T_8393, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_865 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_865 = orr(_out_rimask_T_865) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_865 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_865 = andr(_out_wimask_T_865) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_865 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_865 = orr(_out_romask_T_865) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_865 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_865 = andr(_out_womask_T_865) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_865 = and(out_rivalid_1[743], out_rimask_865) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_865 = and(out_roready_1[743], out_romask_865) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_865 = and(out_wivalid_1[743], out_wimask_865) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_865 = and(out_woready_1[743], out_womask_865) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8395 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8396 = and(out_f_rivalid_865, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8397 = and(UInt<1>(0h1), out_f_roready_865) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8398 = eq(out_rimask_865, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8399 = eq(out_wimask_865, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8400 = eq(out_romask_865, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8401 = eq(out_womask_865, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_740 = or(_out_T_8394, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_740 = cat(_T_462, _out_prepend_T_740) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8402 = or(out_prepend_740, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8403 = bits(_out_T_8402, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_866 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_866 = orr(_out_rimask_T_866) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_866 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_866 = andr(_out_wimask_T_866) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_866 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_866 = orr(_out_romask_T_866) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_866 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_866 = andr(_out_womask_T_866) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_866 = and(out_rivalid_1[744], out_rimask_866) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_866 = and(out_roready_1[744], out_romask_866) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_866 = and(out_wivalid_1[744], out_wimask_866) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_866 = and(out_woready_1[744], out_womask_866) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8404 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8405 = and(out_f_rivalid_866, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8406 = and(UInt<1>(0h1), out_f_roready_866) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8407 = eq(out_rimask_866, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8408 = eq(out_wimask_866, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8409 = eq(out_romask_866, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8410 = eq(out_womask_866, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_741 = or(_out_T_8403, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_741 = cat(_T_463, _out_prepend_T_741) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8411 = or(out_prepend_741, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8412 = bits(_out_T_8411, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_867 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_867 = orr(_out_rimask_T_867) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_867 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_867 = andr(_out_wimask_T_867) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_867 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_867 = orr(_out_romask_T_867) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_867 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_867 = andr(_out_womask_T_867) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_867 = and(out_rivalid_1[745], out_rimask_867) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_867 = and(out_roready_1[745], out_romask_867) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_867 = and(out_wivalid_1[745], out_wimask_867) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_867 = and(out_woready_1[745], out_womask_867) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8413 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8414 = and(out_f_rivalid_867, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8415 = and(UInt<1>(0h1), out_f_roready_867) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8416 = eq(out_rimask_867, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8417 = eq(out_wimask_867, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8418 = eq(out_romask_867, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8419 = eq(out_womask_867, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_742 = or(_out_T_8412, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_742 = cat(_T_464, _out_prepend_T_742) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8420 = or(out_prepend_742, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8421 = bits(_out_T_8420, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_868 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_868 = orr(_out_rimask_T_868) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_868 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_868 = andr(_out_wimask_T_868) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_868 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_868 = orr(_out_romask_T_868) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_868 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_868 = andr(_out_womask_T_868) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_868 = and(out_rivalid_1[746], out_rimask_868) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_868 = and(out_roready_1[746], out_romask_868) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_868 = and(out_wivalid_1[746], out_wimask_868) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_868 = and(out_woready_1[746], out_womask_868) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8422 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8423 = and(out_f_rivalid_868, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8424 = and(UInt<1>(0h1), out_f_roready_868) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8425 = eq(out_rimask_868, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8426 = eq(out_wimask_868, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8427 = eq(out_romask_868, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8428 = eq(out_womask_868, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_743 = or(_out_T_8421, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_743 = cat(_T_465, _out_prepend_T_743) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8429 = or(out_prepend_743, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8430 = bits(_out_T_8429, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_869 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_869 = orr(_out_rimask_T_869) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_869 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_869 = andr(_out_wimask_T_869) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_869 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_869 = orr(_out_romask_T_869) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_869 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_869 = andr(_out_womask_T_869) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_869 = and(out_rivalid_1[747], out_rimask_869) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_869 = and(out_roready_1[747], out_romask_869) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_869 = and(out_wivalid_1[747], out_wimask_869) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_869 = and(out_woready_1[747], out_womask_869) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8431 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8432 = and(out_f_rivalid_869, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8433 = and(UInt<1>(0h1), out_f_roready_869) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8434 = eq(out_rimask_869, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8435 = eq(out_wimask_869, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8436 = eq(out_romask_869, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8437 = eq(out_womask_869, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8438 = or(_T_1202, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8439 = bits(_out_T_8438, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_870 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_870 = orr(_out_rimask_T_870) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_870 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_870 = andr(_out_wimask_T_870) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_870 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_870 = orr(_out_romask_T_870) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_870 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_870 = andr(_out_womask_T_870) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_870 = and(out_rivalid_1[748], out_rimask_870) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_870 = and(out_roready_1[748], out_romask_870) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_870 = and(out_wivalid_1[748], out_wimask_870) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_870 = and(out_woready_1[748], out_womask_870) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8440 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8441 = and(out_f_rivalid_870, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8442 = and(UInt<1>(0h1), out_f_roready_870) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8443 = eq(out_rimask_870, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8444 = eq(out_wimask_870, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8445 = eq(out_romask_870, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8446 = eq(out_womask_870, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_744 = or(_out_T_8439, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_744 = cat(_T_1203, _out_prepend_T_744) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8447 = or(out_prepend_744, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8448 = bits(_out_T_8447, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_871 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_871 = orr(_out_rimask_T_871) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_871 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_871 = andr(_out_wimask_T_871) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_871 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_871 = orr(_out_romask_T_871) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_871 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_871 = andr(_out_womask_T_871) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_871 = and(out_rivalid_1[749], out_rimask_871) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_871 = and(out_roready_1[749], out_romask_871) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_871 = and(out_wivalid_1[749], out_wimask_871) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_871 = and(out_woready_1[749], out_womask_871) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8449 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8450 = and(out_f_rivalid_871, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8451 = and(UInt<1>(0h1), out_f_roready_871) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8452 = eq(out_rimask_871, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8453 = eq(out_wimask_871, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8454 = eq(out_romask_871, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8455 = eq(out_womask_871, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_745 = or(_out_T_8448, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_745 = cat(_T_1204, _out_prepend_T_745) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8456 = or(out_prepend_745, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8457 = bits(_out_T_8456, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_872 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_872 = orr(_out_rimask_T_872) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_872 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_872 = andr(_out_wimask_T_872) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_872 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_872 = orr(_out_romask_T_872) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_872 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_872 = andr(_out_womask_T_872) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_872 = and(out_rivalid_1[750], out_rimask_872) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_872 = and(out_roready_1[750], out_romask_872) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_872 = and(out_wivalid_1[750], out_wimask_872) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_872 = and(out_woready_1[750], out_womask_872) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8458 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8459 = and(out_f_rivalid_872, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8460 = and(UInt<1>(0h1), out_f_roready_872) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8461 = eq(out_rimask_872, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8462 = eq(out_wimask_872, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8463 = eq(out_romask_872, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8464 = eq(out_womask_872, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_746 = or(_out_T_8457, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_746 = cat(_T_1205, _out_prepend_T_746) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8465 = or(out_prepend_746, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8466 = bits(_out_T_8465, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_873 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_873 = orr(_out_rimask_T_873) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_873 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_873 = andr(_out_wimask_T_873) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_873 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_873 = orr(_out_romask_T_873) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_873 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_873 = andr(_out_womask_T_873) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_873 = and(out_rivalid_1[751], out_rimask_873) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_873 = and(out_roready_1[751], out_romask_873) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_873 = and(out_wivalid_1[751], out_wimask_873) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_873 = and(out_woready_1[751], out_womask_873) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8467 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8468 = and(out_f_rivalid_873, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8469 = and(UInt<1>(0h1), out_f_roready_873) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8470 = eq(out_rimask_873, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8471 = eq(out_wimask_873, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8472 = eq(out_romask_873, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8473 = eq(out_womask_873, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_747 = or(_out_T_8466, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_747 = cat(_T_1206, _out_prepend_T_747) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8474 = or(out_prepend_747, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8475 = bits(_out_T_8474, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_874 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_874 = orr(_out_rimask_T_874) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_874 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_874 = andr(_out_wimask_T_874) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_874 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_874 = orr(_out_romask_T_874) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_874 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_874 = andr(_out_womask_T_874) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_874 = and(out_rivalid_1[752], out_rimask_874) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_874 = and(out_roready_1[752], out_romask_874) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_874 = and(out_wivalid_1[752], out_wimask_874) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_874 = and(out_woready_1[752], out_womask_874) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8476 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8477 = and(out_f_rivalid_874, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8478 = and(UInt<1>(0h1), out_f_roready_874) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8479 = eq(out_rimask_874, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8480 = eq(out_wimask_874, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8481 = eq(out_romask_874, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8482 = eq(out_womask_874, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_748 = or(_out_T_8475, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_748 = cat(_T_1207, _out_prepend_T_748) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8483 = or(out_prepend_748, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8484 = bits(_out_T_8483, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_875 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_875 = orr(_out_rimask_T_875) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_875 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_875 = andr(_out_wimask_T_875) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_875 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_875 = orr(_out_romask_T_875) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_875 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_875 = andr(_out_womask_T_875) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_875 = and(out_rivalid_1[753], out_rimask_875) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_875 = and(out_roready_1[753], out_romask_875) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_875 = and(out_wivalid_1[753], out_wimask_875) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_875 = and(out_woready_1[753], out_womask_875) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8485 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8486 = and(out_f_rivalid_875, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8487 = and(UInt<1>(0h1), out_f_roready_875) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8488 = eq(out_rimask_875, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8489 = eq(out_wimask_875, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8490 = eq(out_romask_875, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8491 = eq(out_womask_875, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_749 = or(_out_T_8484, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_749 = cat(_T_1208, _out_prepend_T_749) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8492 = or(out_prepend_749, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8493 = bits(_out_T_8492, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_876 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_876 = orr(_out_rimask_T_876) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_876 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_876 = andr(_out_wimask_T_876) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_876 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_876 = orr(_out_romask_T_876) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_876 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_876 = andr(_out_womask_T_876) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_876 = and(out_rivalid_1[754], out_rimask_876) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_876 = and(out_roready_1[754], out_romask_876) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_876 = and(out_wivalid_1[754], out_wimask_876) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_876 = and(out_woready_1[754], out_womask_876) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8494 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8495 = and(out_f_rivalid_876, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8496 = and(UInt<1>(0h1), out_f_roready_876) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8497 = eq(out_rimask_876, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8498 = eq(out_wimask_876, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8499 = eq(out_romask_876, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8500 = eq(out_womask_876, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_750 = or(_out_T_8493, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_750 = cat(_T_1209, _out_prepend_T_750) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8501 = or(out_prepend_750, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8502 = bits(_out_T_8501, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_877 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_877 = orr(_out_rimask_T_877) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_877 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_877 = andr(_out_wimask_T_877) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_877 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_877 = orr(_out_romask_T_877) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_877 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_877 = andr(_out_womask_T_877) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_877 = and(out_rivalid_1[755], out_rimask_877) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_877 = and(out_roready_1[755], out_romask_877) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_877 = and(out_wivalid_1[755], out_wimask_877) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_877 = and(out_woready_1[755], out_womask_877) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8503 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8504 = and(out_f_rivalid_877, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8505 = and(UInt<1>(0h1), out_f_roready_877) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8506 = eq(out_rimask_877, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8507 = eq(out_wimask_877, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8508 = eq(out_romask_877, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8509 = eq(out_womask_877, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8510 = or(_T_498, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8511 = bits(_out_T_8510, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_878 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_878 = orr(_out_rimask_T_878) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_878 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_878 = andr(_out_wimask_T_878) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_878 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_878 = orr(_out_romask_T_878) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_878 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_878 = andr(_out_womask_T_878) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_878 = and(out_rivalid_1[756], out_rimask_878) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_878 = and(out_roready_1[756], out_romask_878) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_878 = and(out_wivalid_1[756], out_wimask_878) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_878 = and(out_woready_1[756], out_womask_878) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8512 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8513 = and(out_f_rivalid_878, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8514 = and(UInt<1>(0h1), out_f_roready_878) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8515 = eq(out_rimask_878, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8516 = eq(out_wimask_878, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8517 = eq(out_romask_878, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8518 = eq(out_womask_878, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_751 = or(_out_T_8511, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_751 = cat(_T_499, _out_prepend_T_751) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8519 = or(out_prepend_751, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8520 = bits(_out_T_8519, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_879 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_879 = orr(_out_rimask_T_879) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_879 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_879 = andr(_out_wimask_T_879) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_879 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_879 = orr(_out_romask_T_879) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_879 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_879 = andr(_out_womask_T_879) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_879 = and(out_rivalid_1[757], out_rimask_879) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_879 = and(out_roready_1[757], out_romask_879) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_879 = and(out_wivalid_1[757], out_wimask_879) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_879 = and(out_woready_1[757], out_womask_879) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8521 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8522 = and(out_f_rivalid_879, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8523 = and(UInt<1>(0h1), out_f_roready_879) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8524 = eq(out_rimask_879, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8525 = eq(out_wimask_879, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8526 = eq(out_romask_879, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8527 = eq(out_womask_879, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_752 = or(_out_T_8520, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_752 = cat(_T_500, _out_prepend_T_752) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8528 = or(out_prepend_752, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8529 = bits(_out_T_8528, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_880 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_880 = orr(_out_rimask_T_880) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_880 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_880 = andr(_out_wimask_T_880) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_880 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_880 = orr(_out_romask_T_880) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_880 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_880 = andr(_out_womask_T_880) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_880 = and(out_rivalid_1[758], out_rimask_880) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_880 = and(out_roready_1[758], out_romask_880) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_880 = and(out_wivalid_1[758], out_wimask_880) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_880 = and(out_woready_1[758], out_womask_880) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8530 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8531 = and(out_f_rivalid_880, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8532 = and(UInt<1>(0h1), out_f_roready_880) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8533 = eq(out_rimask_880, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8534 = eq(out_wimask_880, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8535 = eq(out_romask_880, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8536 = eq(out_womask_880, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_753 = or(_out_T_8529, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_753 = cat(_T_501, _out_prepend_T_753) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8537 = or(out_prepend_753, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8538 = bits(_out_T_8537, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_881 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_881 = orr(_out_rimask_T_881) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_881 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_881 = andr(_out_wimask_T_881) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_881 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_881 = orr(_out_romask_T_881) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_881 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_881 = andr(_out_womask_T_881) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_881 = and(out_rivalid_1[759], out_rimask_881) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_881 = and(out_roready_1[759], out_romask_881) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_881 = and(out_wivalid_1[759], out_wimask_881) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_881 = and(out_woready_1[759], out_womask_881) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8539 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8540 = and(out_f_rivalid_881, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8541 = and(UInt<1>(0h1), out_f_roready_881) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8542 = eq(out_rimask_881, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8543 = eq(out_wimask_881, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8544 = eq(out_romask_881, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8545 = eq(out_womask_881, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_754 = or(_out_T_8538, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_754 = cat(_T_502, _out_prepend_T_754) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8546 = or(out_prepend_754, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8547 = bits(_out_T_8546, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_882 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_882 = orr(_out_rimask_T_882) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_882 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_882 = andr(_out_wimask_T_882) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_882 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_882 = orr(_out_romask_T_882) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_882 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_882 = andr(_out_womask_T_882) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_882 = and(out_rivalid_1[760], out_rimask_882) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_882 = and(out_roready_1[760], out_romask_882) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_882 = and(out_wivalid_1[760], out_wimask_882) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_882 = and(out_woready_1[760], out_womask_882) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8548 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8549 = and(out_f_rivalid_882, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8550 = and(UInt<1>(0h1), out_f_roready_882) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8551 = eq(out_rimask_882, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8552 = eq(out_wimask_882, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8553 = eq(out_romask_882, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8554 = eq(out_womask_882, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_755 = or(_out_T_8547, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_755 = cat(_T_503, _out_prepend_T_755) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8555 = or(out_prepend_755, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8556 = bits(_out_T_8555, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_883 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_883 = orr(_out_rimask_T_883) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_883 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_883 = andr(_out_wimask_T_883) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_883 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_883 = orr(_out_romask_T_883) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_883 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_883 = andr(_out_womask_T_883) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_883 = and(out_rivalid_1[761], out_rimask_883) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_883 = and(out_roready_1[761], out_romask_883) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_883 = and(out_wivalid_1[761], out_wimask_883) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_883 = and(out_woready_1[761], out_womask_883) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8557 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8558 = and(out_f_rivalid_883, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8559 = and(UInt<1>(0h1), out_f_roready_883) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8560 = eq(out_rimask_883, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8561 = eq(out_wimask_883, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8562 = eq(out_romask_883, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8563 = eq(out_womask_883, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_756 = or(_out_T_8556, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_756 = cat(_T_504, _out_prepend_T_756) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8564 = or(out_prepend_756, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8565 = bits(_out_T_8564, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_884 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_884 = orr(_out_rimask_T_884) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_884 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_884 = andr(_out_wimask_T_884) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_884 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_884 = orr(_out_romask_T_884) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_884 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_884 = andr(_out_womask_T_884) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_884 = and(out_rivalid_1[762], out_rimask_884) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_884 = and(out_roready_1[762], out_romask_884) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_884 = and(out_wivalid_1[762], out_wimask_884) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_884 = and(out_woready_1[762], out_womask_884) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8566 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8567 = and(out_f_rivalid_884, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8568 = and(UInt<1>(0h1), out_f_roready_884) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8569 = eq(out_rimask_884, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8570 = eq(out_wimask_884, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8571 = eq(out_romask_884, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8572 = eq(out_womask_884, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_757 = or(_out_T_8565, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_757 = cat(_T_505, _out_prepend_T_757) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8573 = or(out_prepend_757, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8574 = bits(_out_T_8573, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_885 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_885 = orr(_out_rimask_T_885) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_885 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_885 = andr(_out_wimask_T_885) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_885 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_885 = orr(_out_romask_T_885) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_885 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_885 = andr(_out_womask_T_885) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_885 = and(out_rivalid_1[763], out_rimask_885) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_885 = and(out_roready_1[763], out_romask_885) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_885 = and(out_wivalid_1[763], out_wimask_885) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_885 = and(out_woready_1[763], out_womask_885) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8575 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8576 = and(out_f_rivalid_885, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8577 = and(UInt<1>(0h1), out_f_roready_885) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8578 = eq(out_rimask_885, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8579 = eq(out_wimask_885, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8580 = eq(out_romask_885, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8581 = eq(out_womask_885, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8582 = or(_T_1226, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8583 = bits(_out_T_8582, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_886 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_886 = orr(_out_rimask_T_886) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_886 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_886 = andr(_out_wimask_T_886) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_886 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_886 = orr(_out_romask_T_886) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_886 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_886 = andr(_out_womask_T_886) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_886 = and(out_rivalid_1[764], out_rimask_886) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_886 = and(out_roready_1[764], out_romask_886) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_886 = and(out_wivalid_1[764], out_wimask_886) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_886 = and(out_woready_1[764], out_womask_886) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8584 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8585 = and(out_f_rivalid_886, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8586 = and(UInt<1>(0h1), out_f_roready_886) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8587 = eq(out_rimask_886, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8588 = eq(out_wimask_886, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8589 = eq(out_romask_886, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8590 = eq(out_womask_886, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_758 = or(_out_T_8583, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_758 = cat(_T_1227, _out_prepend_T_758) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8591 = or(out_prepend_758, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8592 = bits(_out_T_8591, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_887 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_887 = orr(_out_rimask_T_887) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_887 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_887 = andr(_out_wimask_T_887) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_887 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_887 = orr(_out_romask_T_887) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_887 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_887 = andr(_out_womask_T_887) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_887 = and(out_rivalid_1[765], out_rimask_887) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_887 = and(out_roready_1[765], out_romask_887) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_887 = and(out_wivalid_1[765], out_wimask_887) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_887 = and(out_woready_1[765], out_womask_887) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8593 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8594 = and(out_f_rivalid_887, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8595 = and(UInt<1>(0h1), out_f_roready_887) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8596 = eq(out_rimask_887, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8597 = eq(out_wimask_887, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8598 = eq(out_romask_887, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8599 = eq(out_womask_887, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_759 = or(_out_T_8592, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_759 = cat(_T_1228, _out_prepend_T_759) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8600 = or(out_prepend_759, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8601 = bits(_out_T_8600, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_888 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_888 = orr(_out_rimask_T_888) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_888 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_888 = andr(_out_wimask_T_888) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_888 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_888 = orr(_out_romask_T_888) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_888 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_888 = andr(_out_womask_T_888) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_888 = and(out_rivalid_1[766], out_rimask_888) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_888 = and(out_roready_1[766], out_romask_888) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_888 = and(out_wivalid_1[766], out_wimask_888) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_888 = and(out_woready_1[766], out_womask_888) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8602 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8603 = and(out_f_rivalid_888, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8604 = and(UInt<1>(0h1), out_f_roready_888) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8605 = eq(out_rimask_888, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8606 = eq(out_wimask_888, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8607 = eq(out_romask_888, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8608 = eq(out_womask_888, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_760 = or(_out_T_8601, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_760 = cat(_T_1229, _out_prepend_T_760) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8609 = or(out_prepend_760, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8610 = bits(_out_T_8609, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_889 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_889 = orr(_out_rimask_T_889) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_889 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_889 = andr(_out_wimask_T_889) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_889 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_889 = orr(_out_romask_T_889) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_889 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_889 = andr(_out_womask_T_889) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_889 = and(out_rivalid_1[767], out_rimask_889) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_889 = and(out_roready_1[767], out_romask_889) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_889 = and(out_wivalid_1[767], out_wimask_889) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_889 = and(out_woready_1[767], out_womask_889) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8611 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8612 = and(out_f_rivalid_889, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8613 = and(UInt<1>(0h1), out_f_roready_889) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8614 = eq(out_rimask_889, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8615 = eq(out_wimask_889, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8616 = eq(out_romask_889, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8617 = eq(out_womask_889, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_761 = or(_out_T_8610, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_761 = cat(_T_1230, _out_prepend_T_761) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8618 = or(out_prepend_761, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8619 = bits(_out_T_8618, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_890 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_890 = orr(_out_rimask_T_890) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_890 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_890 = andr(_out_wimask_T_890) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_890 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_890 = orr(_out_romask_T_890) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_890 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_890 = andr(_out_womask_T_890) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_890 = and(out_rivalid_1[768], out_rimask_890) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_890 = and(out_roready_1[768], out_romask_890) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_890 = and(out_wivalid_1[768], out_wimask_890) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_890 = and(out_woready_1[768], out_womask_890) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8620 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8621 = and(out_f_rivalid_890, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8622 = and(UInt<1>(0h1), out_f_roready_890) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8623 = eq(out_rimask_890, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8624 = eq(out_wimask_890, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8625 = eq(out_romask_890, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8626 = eq(out_womask_890, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_762 = or(_out_T_8619, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_762 = cat(_T_1231, _out_prepend_T_762) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8627 = or(out_prepend_762, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8628 = bits(_out_T_8627, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_891 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_891 = orr(_out_rimask_T_891) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_891 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_891 = andr(_out_wimask_T_891) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_891 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_891 = orr(_out_romask_T_891) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_891 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_891 = andr(_out_womask_T_891) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_891 = and(out_rivalid_1[769], out_rimask_891) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_891 = and(out_roready_1[769], out_romask_891) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_891 = and(out_wivalid_1[769], out_wimask_891) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_891 = and(out_woready_1[769], out_womask_891) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8629 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8630 = and(out_f_rivalid_891, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8631 = and(UInt<1>(0h1), out_f_roready_891) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8632 = eq(out_rimask_891, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8633 = eq(out_wimask_891, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8634 = eq(out_romask_891, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8635 = eq(out_womask_891, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_763 = or(_out_T_8628, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_763 = cat(_T_1232, _out_prepend_T_763) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8636 = or(out_prepend_763, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8637 = bits(_out_T_8636, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_892 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_892 = orr(_out_rimask_T_892) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_892 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_892 = andr(_out_wimask_T_892) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_892 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_892 = orr(_out_romask_T_892) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_892 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_892 = andr(_out_womask_T_892) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_892 = and(out_rivalid_1[770], out_rimask_892) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_892 = and(out_roready_1[770], out_romask_892) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_892 = and(out_wivalid_1[770], out_wimask_892) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_892 = and(out_woready_1[770], out_womask_892) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8638 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8639 = and(out_f_rivalid_892, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8640 = and(UInt<1>(0h1), out_f_roready_892) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8641 = eq(out_rimask_892, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8642 = eq(out_wimask_892, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8643 = eq(out_romask_892, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8644 = eq(out_womask_892, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_764 = or(_out_T_8637, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_764 = cat(_T_1233, _out_prepend_T_764) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8645 = or(out_prepend_764, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8646 = bits(_out_T_8645, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_893 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_893 = orr(_out_rimask_T_893) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_893 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_893 = andr(_out_wimask_T_893) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_893 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_893 = orr(_out_romask_T_893) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_893 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_893 = andr(_out_womask_T_893) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_893 = and(out_rivalid_1[771], out_rimask_893) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_893 = and(out_roready_1[771], out_romask_893) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_893 = and(out_wivalid_1[771], out_wimask_893) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_893 = and(out_woready_1[771], out_womask_893) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8647 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8648 = and(out_f_rivalid_893, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8649 = and(UInt<1>(0h1), out_f_roready_893) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8650 = eq(out_rimask_893, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8651 = eq(out_wimask_893, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8652 = eq(out_romask_893, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8653 = eq(out_womask_893, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8654 = or(_T_1346, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8655 = bits(_out_T_8654, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_894 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_894 = orr(_out_rimask_T_894) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_894 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_894 = andr(_out_wimask_T_894) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_894 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_894 = orr(_out_romask_T_894) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_894 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_894 = andr(_out_womask_T_894) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_894 = and(out_rivalid_1[772], out_rimask_894) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_894 = and(out_roready_1[772], out_romask_894) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_894 = and(out_wivalid_1[772], out_wimask_894) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_894 = and(out_woready_1[772], out_womask_894) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8656 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8657 = and(out_f_rivalid_894, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8658 = and(UInt<1>(0h1), out_f_roready_894) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8659 = eq(out_rimask_894, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8660 = eq(out_wimask_894, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8661 = eq(out_romask_894, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8662 = eq(out_womask_894, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_765 = or(_out_T_8655, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_765 = cat(_T_1347, _out_prepend_T_765) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8663 = or(out_prepend_765, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8664 = bits(_out_T_8663, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_895 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_895 = orr(_out_rimask_T_895) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_895 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_895 = andr(_out_wimask_T_895) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_895 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_895 = orr(_out_romask_T_895) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_895 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_895 = andr(_out_womask_T_895) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_895 = and(out_rivalid_1[773], out_rimask_895) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_895 = and(out_roready_1[773], out_romask_895) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_895 = and(out_wivalid_1[773], out_wimask_895) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_895 = and(out_woready_1[773], out_womask_895) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8665 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8666 = and(out_f_rivalid_895, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8667 = and(UInt<1>(0h1), out_f_roready_895) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8668 = eq(out_rimask_895, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8669 = eq(out_wimask_895, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8670 = eq(out_romask_895, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8671 = eq(out_womask_895, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_766 = or(_out_T_8664, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_766 = cat(_T_1348, _out_prepend_T_766) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8672 = or(out_prepend_766, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8673 = bits(_out_T_8672, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_896 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_896 = orr(_out_rimask_T_896) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_896 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_896 = andr(_out_wimask_T_896) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_896 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_896 = orr(_out_romask_T_896) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_896 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_896 = andr(_out_womask_T_896) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_896 = and(out_rivalid_1[774], out_rimask_896) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_896 = and(out_roready_1[774], out_romask_896) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_896 = and(out_wivalid_1[774], out_wimask_896) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_896 = and(out_woready_1[774], out_womask_896) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8674 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8675 = and(out_f_rivalid_896, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8676 = and(UInt<1>(0h1), out_f_roready_896) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8677 = eq(out_rimask_896, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8678 = eq(out_wimask_896, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8679 = eq(out_romask_896, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8680 = eq(out_womask_896, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_767 = or(_out_T_8673, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_767 = cat(_T_1349, _out_prepend_T_767) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8681 = or(out_prepend_767, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8682 = bits(_out_T_8681, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_897 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_897 = orr(_out_rimask_T_897) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_897 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_897 = andr(_out_wimask_T_897) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_897 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_897 = orr(_out_romask_T_897) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_897 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_897 = andr(_out_womask_T_897) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_897 = and(out_rivalid_1[775], out_rimask_897) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_897 = and(out_roready_1[775], out_romask_897) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_897 = and(out_wivalid_1[775], out_wimask_897) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_897 = and(out_woready_1[775], out_womask_897) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8683 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8684 = and(out_f_rivalid_897, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8685 = and(UInt<1>(0h1), out_f_roready_897) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8686 = eq(out_rimask_897, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8687 = eq(out_wimask_897, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8688 = eq(out_romask_897, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8689 = eq(out_womask_897, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_768 = or(_out_T_8682, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_768 = cat(_T_1350, _out_prepend_T_768) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8690 = or(out_prepend_768, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8691 = bits(_out_T_8690, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_898 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_898 = orr(_out_rimask_T_898) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_898 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_898 = andr(_out_wimask_T_898) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_898 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_898 = orr(_out_romask_T_898) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_898 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_898 = andr(_out_womask_T_898) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_898 = and(out_rivalid_1[776], out_rimask_898) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_898 = and(out_roready_1[776], out_romask_898) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_898 = and(out_wivalid_1[776], out_wimask_898) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_898 = and(out_woready_1[776], out_womask_898) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8692 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8693 = and(out_f_rivalid_898, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8694 = and(UInt<1>(0h1), out_f_roready_898) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8695 = eq(out_rimask_898, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8696 = eq(out_wimask_898, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8697 = eq(out_romask_898, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8698 = eq(out_womask_898, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_769 = or(_out_T_8691, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_769 = cat(_T_1351, _out_prepend_T_769) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8699 = or(out_prepend_769, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8700 = bits(_out_T_8699, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_899 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_899 = orr(_out_rimask_T_899) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_899 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_899 = andr(_out_wimask_T_899) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_899 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_899 = orr(_out_romask_T_899) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_899 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_899 = andr(_out_womask_T_899) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_899 = and(out_rivalid_1[777], out_rimask_899) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_899 = and(out_roready_1[777], out_romask_899) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_899 = and(out_wivalid_1[777], out_wimask_899) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_899 = and(out_woready_1[777], out_womask_899) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8701 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8702 = and(out_f_rivalid_899, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8703 = and(UInt<1>(0h1), out_f_roready_899) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8704 = eq(out_rimask_899, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8705 = eq(out_wimask_899, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8706 = eq(out_romask_899, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8707 = eq(out_womask_899, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_770 = or(_out_T_8700, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_770 = cat(_T_1352, _out_prepend_T_770) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8708 = or(out_prepend_770, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8709 = bits(_out_T_8708, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_900 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_900 = orr(_out_rimask_T_900) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_900 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_900 = andr(_out_wimask_T_900) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_900 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_900 = orr(_out_romask_T_900) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_900 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_900 = andr(_out_womask_T_900) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_900 = and(out_rivalid_1[778], out_rimask_900) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_900 = and(out_roready_1[778], out_romask_900) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_900 = and(out_wivalid_1[778], out_wimask_900) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_900 = and(out_woready_1[778], out_womask_900) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8710 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8711 = and(out_f_rivalid_900, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8712 = and(UInt<1>(0h1), out_f_roready_900) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8713 = eq(out_rimask_900, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8714 = eq(out_wimask_900, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8715 = eq(out_romask_900, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8716 = eq(out_womask_900, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_771 = or(_out_T_8709, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_771 = cat(_T_1353, _out_prepend_T_771) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8717 = or(out_prepend_771, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8718 = bits(_out_T_8717, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_901 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_901 = orr(_out_rimask_T_901) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_901 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_901 = andr(_out_wimask_T_901) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_901 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_901 = orr(_out_romask_T_901) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_901 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_901 = andr(_out_womask_T_901) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_901 = and(out_rivalid_1[779], out_rimask_901) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_901 = and(out_roready_1[779], out_romask_901) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_901 = and(out_wivalid_1[779], out_wimask_901) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_901 = and(out_woready_1[779], out_womask_901) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8719 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8720 = and(out_f_rivalid_901, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8721 = and(UInt<1>(0h1), out_f_roready_901) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8722 = eq(out_rimask_901, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8723 = eq(out_wimask_901, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8724 = eq(out_romask_901, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8725 = eq(out_womask_901, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8726 = or(_T_754, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8727 = bits(_out_T_8726, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_902 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_902 = orr(_out_rimask_T_902) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_902 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_902 = andr(_out_wimask_T_902) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_902 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_902 = orr(_out_romask_T_902) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_902 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_902 = andr(_out_womask_T_902) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_902 = and(out_rivalid_1[780], out_rimask_902) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_902 = and(out_roready_1[780], out_romask_902) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_902 = and(out_wivalid_1[780], out_wimask_902) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_902 = and(out_woready_1[780], out_womask_902) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8728 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8729 = and(out_f_rivalid_902, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8730 = and(UInt<1>(0h1), out_f_roready_902) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8731 = eq(out_rimask_902, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8732 = eq(out_wimask_902, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8733 = eq(out_romask_902, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8734 = eq(out_womask_902, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_772 = or(_out_T_8727, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_772 = cat(_T_755, _out_prepend_T_772) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8735 = or(out_prepend_772, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8736 = bits(_out_T_8735, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_903 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_903 = orr(_out_rimask_T_903) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_903 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_903 = andr(_out_wimask_T_903) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_903 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_903 = orr(_out_romask_T_903) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_903 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_903 = andr(_out_womask_T_903) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_903 = and(out_rivalid_1[781], out_rimask_903) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_903 = and(out_roready_1[781], out_romask_903) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_903 = and(out_wivalid_1[781], out_wimask_903) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_903 = and(out_woready_1[781], out_womask_903) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8737 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8738 = and(out_f_rivalid_903, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8739 = and(UInt<1>(0h1), out_f_roready_903) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8740 = eq(out_rimask_903, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8741 = eq(out_wimask_903, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8742 = eq(out_romask_903, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8743 = eq(out_womask_903, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_773 = or(_out_T_8736, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_773 = cat(_T_756, _out_prepend_T_773) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8744 = or(out_prepend_773, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8745 = bits(_out_T_8744, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_904 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_904 = orr(_out_rimask_T_904) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_904 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_904 = andr(_out_wimask_T_904) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_904 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_904 = orr(_out_romask_T_904) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_904 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_904 = andr(_out_womask_T_904) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_904 = and(out_rivalid_1[782], out_rimask_904) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_904 = and(out_roready_1[782], out_romask_904) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_904 = and(out_wivalid_1[782], out_wimask_904) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_904 = and(out_woready_1[782], out_womask_904) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8746 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8747 = and(out_f_rivalid_904, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8748 = and(UInt<1>(0h1), out_f_roready_904) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8749 = eq(out_rimask_904, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8750 = eq(out_wimask_904, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8751 = eq(out_romask_904, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8752 = eq(out_womask_904, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_774 = or(_out_T_8745, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_774 = cat(_T_757, _out_prepend_T_774) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8753 = or(out_prepend_774, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8754 = bits(_out_T_8753, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_905 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_905 = orr(_out_rimask_T_905) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_905 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_905 = andr(_out_wimask_T_905) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_905 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_905 = orr(_out_romask_T_905) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_905 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_905 = andr(_out_womask_T_905) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_905 = and(out_rivalid_1[783], out_rimask_905) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_905 = and(out_roready_1[783], out_romask_905) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_905 = and(out_wivalid_1[783], out_wimask_905) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_905 = and(out_woready_1[783], out_womask_905) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8755 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8756 = and(out_f_rivalid_905, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8757 = and(UInt<1>(0h1), out_f_roready_905) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8758 = eq(out_rimask_905, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8759 = eq(out_wimask_905, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8760 = eq(out_romask_905, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8761 = eq(out_womask_905, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_775 = or(_out_T_8754, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_775 = cat(_T_758, _out_prepend_T_775) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8762 = or(out_prepend_775, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8763 = bits(_out_T_8762, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_906 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_906 = orr(_out_rimask_T_906) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_906 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_906 = andr(_out_wimask_T_906) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_906 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_906 = orr(_out_romask_T_906) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_906 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_906 = andr(_out_womask_T_906) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_906 = and(out_rivalid_1[784], out_rimask_906) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_906 = and(out_roready_1[784], out_romask_906) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_906 = and(out_wivalid_1[784], out_wimask_906) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_906 = and(out_woready_1[784], out_womask_906) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8764 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8765 = and(out_f_rivalid_906, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8766 = and(UInt<1>(0h1), out_f_roready_906) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8767 = eq(out_rimask_906, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8768 = eq(out_wimask_906, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8769 = eq(out_romask_906, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8770 = eq(out_womask_906, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_776 = or(_out_T_8763, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_776 = cat(_T_759, _out_prepend_T_776) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8771 = or(out_prepend_776, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8772 = bits(_out_T_8771, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_907 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_907 = orr(_out_rimask_T_907) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_907 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_907 = andr(_out_wimask_T_907) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_907 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_907 = orr(_out_romask_T_907) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_907 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_907 = andr(_out_womask_T_907) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_907 = and(out_rivalid_1[785], out_rimask_907) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_907 = and(out_roready_1[785], out_romask_907) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_907 = and(out_wivalid_1[785], out_wimask_907) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_907 = and(out_woready_1[785], out_womask_907) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8773 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8774 = and(out_f_rivalid_907, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8775 = and(UInt<1>(0h1), out_f_roready_907) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8776 = eq(out_rimask_907, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8777 = eq(out_wimask_907, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8778 = eq(out_romask_907, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8779 = eq(out_womask_907, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_777 = or(_out_T_8772, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_777 = cat(_T_760, _out_prepend_T_777) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8780 = or(out_prepend_777, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8781 = bits(_out_T_8780, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_908 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_908 = orr(_out_rimask_T_908) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_908 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_908 = andr(_out_wimask_T_908) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_908 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_908 = orr(_out_romask_T_908) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_908 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_908 = andr(_out_womask_T_908) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_908 = and(out_rivalid_1[786], out_rimask_908) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_908 = and(out_roready_1[786], out_romask_908) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_908 = and(out_wivalid_1[786], out_wimask_908) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_908 = and(out_woready_1[786], out_womask_908) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8782 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8783 = and(out_f_rivalid_908, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8784 = and(UInt<1>(0h1), out_f_roready_908) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8785 = eq(out_rimask_908, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8786 = eq(out_wimask_908, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8787 = eq(out_romask_908, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8788 = eq(out_womask_908, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_778 = or(_out_T_8781, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_778 = cat(_T_761, _out_prepend_T_778) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8789 = or(out_prepend_778, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8790 = bits(_out_T_8789, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_909 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_909 = orr(_out_rimask_T_909) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_909 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_909 = andr(_out_wimask_T_909) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_909 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_909 = orr(_out_romask_T_909) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_909 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_909 = andr(_out_womask_T_909) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_909 = and(out_rivalid_1[787], out_rimask_909) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_909 = and(out_roready_1[787], out_romask_909) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_909 = and(out_wivalid_1[787], out_wimask_909) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_909 = and(out_woready_1[787], out_womask_909) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8791 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8792 = and(out_f_rivalid_909, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8793 = and(UInt<1>(0h1), out_f_roready_909) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8794 = eq(out_rimask_909, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8795 = eq(out_wimask_909, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8796 = eq(out_romask_909, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8797 = eq(out_womask_909, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8798 = or(_T_714, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8799 = bits(_out_T_8798, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_910 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_910 = orr(_out_rimask_T_910) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_910 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_910 = andr(_out_wimask_T_910) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_910 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_910 = orr(_out_romask_T_910) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_910 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_910 = andr(_out_womask_T_910) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_910 = and(out_rivalid_1[788], out_rimask_910) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_910 = and(out_roready_1[788], out_romask_910) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_910 = and(out_wivalid_1[788], out_wimask_910) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_910 = and(out_woready_1[788], out_womask_910) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8800 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8801 = and(out_f_rivalid_910, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8802 = and(UInt<1>(0h1), out_f_roready_910) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8803 = eq(out_rimask_910, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8804 = eq(out_wimask_910, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8805 = eq(out_romask_910, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8806 = eq(out_womask_910, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_779 = or(_out_T_8799, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_779 = cat(_T_715, _out_prepend_T_779) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8807 = or(out_prepend_779, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8808 = bits(_out_T_8807, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_911 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_911 = orr(_out_rimask_T_911) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_911 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_911 = andr(_out_wimask_T_911) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_911 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_911 = orr(_out_romask_T_911) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_911 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_911 = andr(_out_womask_T_911) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_911 = and(out_rivalid_1[789], out_rimask_911) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_911 = and(out_roready_1[789], out_romask_911) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_911 = and(out_wivalid_1[789], out_wimask_911) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_911 = and(out_woready_1[789], out_womask_911) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8809 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8810 = and(out_f_rivalid_911, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8811 = and(UInt<1>(0h1), out_f_roready_911) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8812 = eq(out_rimask_911, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8813 = eq(out_wimask_911, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8814 = eq(out_romask_911, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8815 = eq(out_womask_911, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_780 = or(_out_T_8808, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_780 = cat(_T_716, _out_prepend_T_780) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8816 = or(out_prepend_780, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8817 = bits(_out_T_8816, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_912 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_912 = orr(_out_rimask_T_912) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_912 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_912 = andr(_out_wimask_T_912) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_912 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_912 = orr(_out_romask_T_912) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_912 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_912 = andr(_out_womask_T_912) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_912 = and(out_rivalid_1[790], out_rimask_912) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_912 = and(out_roready_1[790], out_romask_912) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_912 = and(out_wivalid_1[790], out_wimask_912) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_912 = and(out_woready_1[790], out_womask_912) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8818 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8819 = and(out_f_rivalid_912, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8820 = and(UInt<1>(0h1), out_f_roready_912) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8821 = eq(out_rimask_912, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8822 = eq(out_wimask_912, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8823 = eq(out_romask_912, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8824 = eq(out_womask_912, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_781 = or(_out_T_8817, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_781 = cat(_T_717, _out_prepend_T_781) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8825 = or(out_prepend_781, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8826 = bits(_out_T_8825, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_913 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_913 = orr(_out_rimask_T_913) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_913 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_913 = andr(_out_wimask_T_913) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_913 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_913 = orr(_out_romask_T_913) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_913 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_913 = andr(_out_womask_T_913) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_913 = and(out_rivalid_1[791], out_rimask_913) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_913 = and(out_roready_1[791], out_romask_913) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_913 = and(out_wivalid_1[791], out_wimask_913) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_913 = and(out_woready_1[791], out_womask_913) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8827 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8828 = and(out_f_rivalid_913, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8829 = and(UInt<1>(0h1), out_f_roready_913) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8830 = eq(out_rimask_913, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8831 = eq(out_wimask_913, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8832 = eq(out_romask_913, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8833 = eq(out_womask_913, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_782 = or(_out_T_8826, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_782 = cat(_T_718, _out_prepend_T_782) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8834 = or(out_prepend_782, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8835 = bits(_out_T_8834, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_914 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_914 = orr(_out_rimask_T_914) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_914 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_914 = andr(_out_wimask_T_914) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_914 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_914 = orr(_out_romask_T_914) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_914 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_914 = andr(_out_womask_T_914) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_914 = and(out_rivalid_1[792], out_rimask_914) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_914 = and(out_roready_1[792], out_romask_914) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_914 = and(out_wivalid_1[792], out_wimask_914) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_914 = and(out_woready_1[792], out_womask_914) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8836 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8837 = and(out_f_rivalid_914, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8838 = and(UInt<1>(0h1), out_f_roready_914) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8839 = eq(out_rimask_914, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8840 = eq(out_wimask_914, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8841 = eq(out_romask_914, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8842 = eq(out_womask_914, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_783 = or(_out_T_8835, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_783 = cat(_T_719, _out_prepend_T_783) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8843 = or(out_prepend_783, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8844 = bits(_out_T_8843, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_915 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_915 = orr(_out_rimask_T_915) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_915 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_915 = andr(_out_wimask_T_915) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_915 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_915 = orr(_out_romask_T_915) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_915 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_915 = andr(_out_womask_T_915) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_915 = and(out_rivalid_1[793], out_rimask_915) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_915 = and(out_roready_1[793], out_romask_915) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_915 = and(out_wivalid_1[793], out_wimask_915) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_915 = and(out_woready_1[793], out_womask_915) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8845 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8846 = and(out_f_rivalid_915, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8847 = and(UInt<1>(0h1), out_f_roready_915) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8848 = eq(out_rimask_915, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8849 = eq(out_wimask_915, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8850 = eq(out_romask_915, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8851 = eq(out_womask_915, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_784 = or(_out_T_8844, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_784 = cat(_T_720, _out_prepend_T_784) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8852 = or(out_prepend_784, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8853 = bits(_out_T_8852, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_916 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_916 = orr(_out_rimask_T_916) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_916 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_916 = andr(_out_wimask_T_916) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_916 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_916 = orr(_out_romask_T_916) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_916 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_916 = andr(_out_womask_T_916) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_916 = and(out_rivalid_1[794], out_rimask_916) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_916 = and(out_roready_1[794], out_romask_916) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_916 = and(out_wivalid_1[794], out_wimask_916) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_916 = and(out_woready_1[794], out_womask_916) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8854 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8855 = and(out_f_rivalid_916, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8856 = and(UInt<1>(0h1), out_f_roready_916) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8857 = eq(out_rimask_916, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8858 = eq(out_wimask_916, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8859 = eq(out_romask_916, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8860 = eq(out_womask_916, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_785 = or(_out_T_8853, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_785 = cat(_T_721, _out_prepend_T_785) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8861 = or(out_prepend_785, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8862 = bits(_out_T_8861, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_917 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_917 = orr(_out_rimask_T_917) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_917 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_917 = andr(_out_wimask_T_917) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_917 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_917 = orr(_out_romask_T_917) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_917 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_917 = andr(_out_womask_T_917) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_917 = and(out_rivalid_1[795], out_rimask_917) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_917 = and(out_roready_1[795], out_romask_917) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_917 = and(out_wivalid_1[795], out_wimask_917) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_917 = and(out_woready_1[795], out_womask_917) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8863 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8864 = and(out_f_rivalid_917, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8865 = and(UInt<1>(0h1), out_f_roready_917) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8866 = eq(out_rimask_917, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8867 = eq(out_wimask_917, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8868 = eq(out_romask_917, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8869 = eq(out_womask_917, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8870 = or(_T_1458, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8871 = bits(_out_T_8870, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_918 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_918 = orr(_out_rimask_T_918) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_918 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_918 = andr(_out_wimask_T_918) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_918 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_918 = orr(_out_romask_T_918) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_918 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_918 = andr(_out_womask_T_918) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_918 = and(out_rivalid_1[796], out_rimask_918) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_918 = and(out_roready_1[796], out_romask_918) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_918 = and(out_wivalid_1[796], out_wimask_918) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_918 = and(out_woready_1[796], out_womask_918) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8872 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8873 = and(out_f_rivalid_918, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8874 = and(UInt<1>(0h1), out_f_roready_918) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8875 = eq(out_rimask_918, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8876 = eq(out_wimask_918, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8877 = eq(out_romask_918, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8878 = eq(out_womask_918, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_786 = or(_out_T_8871, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_786 = cat(_T_1459, _out_prepend_T_786) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8879 = or(out_prepend_786, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8880 = bits(_out_T_8879, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_919 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_919 = orr(_out_rimask_T_919) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_919 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_919 = andr(_out_wimask_T_919) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_919 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_919 = orr(_out_romask_T_919) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_919 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_919 = andr(_out_womask_T_919) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_919 = and(out_rivalid_1[797], out_rimask_919) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_919 = and(out_roready_1[797], out_romask_919) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_919 = and(out_wivalid_1[797], out_wimask_919) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_919 = and(out_woready_1[797], out_womask_919) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8881 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8882 = and(out_f_rivalid_919, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8883 = and(UInt<1>(0h1), out_f_roready_919) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8884 = eq(out_rimask_919, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8885 = eq(out_wimask_919, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8886 = eq(out_romask_919, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8887 = eq(out_womask_919, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_787 = or(_out_T_8880, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_787 = cat(_T_1460, _out_prepend_T_787) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8888 = or(out_prepend_787, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8889 = bits(_out_T_8888, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_920 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_920 = orr(_out_rimask_T_920) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_920 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_920 = andr(_out_wimask_T_920) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_920 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_920 = orr(_out_romask_T_920) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_920 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_920 = andr(_out_womask_T_920) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_920 = and(out_rivalid_1[798], out_rimask_920) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_920 = and(out_roready_1[798], out_romask_920) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_920 = and(out_wivalid_1[798], out_wimask_920) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_920 = and(out_woready_1[798], out_womask_920) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8890 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8891 = and(out_f_rivalid_920, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8892 = and(UInt<1>(0h1), out_f_roready_920) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8893 = eq(out_rimask_920, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8894 = eq(out_wimask_920, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8895 = eq(out_romask_920, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8896 = eq(out_womask_920, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_788 = or(_out_T_8889, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_788 = cat(_T_1461, _out_prepend_T_788) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8897 = or(out_prepend_788, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8898 = bits(_out_T_8897, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_921 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_921 = orr(_out_rimask_T_921) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_921 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_921 = andr(_out_wimask_T_921) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_921 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_921 = orr(_out_romask_T_921) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_921 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_921 = andr(_out_womask_T_921) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_921 = and(out_rivalid_1[799], out_rimask_921) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_921 = and(out_roready_1[799], out_romask_921) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_921 = and(out_wivalid_1[799], out_wimask_921) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_921 = and(out_woready_1[799], out_womask_921) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8899 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8900 = and(out_f_rivalid_921, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8901 = and(UInt<1>(0h1), out_f_roready_921) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8902 = eq(out_rimask_921, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8903 = eq(out_wimask_921, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8904 = eq(out_romask_921, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8905 = eq(out_womask_921, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_789 = or(_out_T_8898, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_789 = cat(_T_1462, _out_prepend_T_789) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8906 = or(out_prepend_789, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8907 = bits(_out_T_8906, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_922 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_922 = orr(_out_rimask_T_922) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_922 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_922 = andr(_out_wimask_T_922) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_922 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_922 = orr(_out_romask_T_922) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_922 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_922 = andr(_out_womask_T_922) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_922 = and(out_rivalid_1[800], out_rimask_922) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_922 = and(out_roready_1[800], out_romask_922) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_922 = and(out_wivalid_1[800], out_wimask_922) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_922 = and(out_woready_1[800], out_womask_922) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8908 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8909 = and(out_f_rivalid_922, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8910 = and(UInt<1>(0h1), out_f_roready_922) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8911 = eq(out_rimask_922, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8912 = eq(out_wimask_922, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8913 = eq(out_romask_922, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8914 = eq(out_womask_922, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_790 = or(_out_T_8907, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_790 = cat(_T_1463, _out_prepend_T_790) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8915 = or(out_prepend_790, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8916 = bits(_out_T_8915, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_923 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_923 = orr(_out_rimask_T_923) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_923 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_923 = andr(_out_wimask_T_923) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_923 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_923 = orr(_out_romask_T_923) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_923 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_923 = andr(_out_womask_T_923) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_923 = and(out_rivalid_1[801], out_rimask_923) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_923 = and(out_roready_1[801], out_romask_923) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_923 = and(out_wivalid_1[801], out_wimask_923) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_923 = and(out_woready_1[801], out_womask_923) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8917 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8918 = and(out_f_rivalid_923, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8919 = and(UInt<1>(0h1), out_f_roready_923) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8920 = eq(out_rimask_923, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8921 = eq(out_wimask_923, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8922 = eq(out_romask_923, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8923 = eq(out_womask_923, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_791 = or(_out_T_8916, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_791 = cat(_T_1464, _out_prepend_T_791) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8924 = or(out_prepend_791, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8925 = bits(_out_T_8924, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_924 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_924 = orr(_out_rimask_T_924) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_924 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_924 = andr(_out_wimask_T_924) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_924 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_924 = orr(_out_romask_T_924) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_924 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_924 = andr(_out_womask_T_924) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_924 = and(out_rivalid_1[802], out_rimask_924) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_924 = and(out_roready_1[802], out_romask_924) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_924 = and(out_wivalid_1[802], out_wimask_924) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_924 = and(out_woready_1[802], out_womask_924) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8926 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8927 = and(out_f_rivalid_924, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8928 = and(UInt<1>(0h1), out_f_roready_924) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8929 = eq(out_rimask_924, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8930 = eq(out_wimask_924, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8931 = eq(out_romask_924, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8932 = eq(out_womask_924, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_792 = or(_out_T_8925, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_792 = cat(_T_1465, _out_prepend_T_792) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8933 = or(out_prepend_792, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8934 = bits(_out_T_8933, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_925 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_925 = orr(_out_rimask_T_925) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_925 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_925 = andr(_out_wimask_T_925) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_925 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_925 = orr(_out_romask_T_925) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_925 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_925 = andr(_out_womask_T_925) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_925 = and(out_rivalid_1[803], out_rimask_925) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_925 = and(out_roready_1[803], out_romask_925) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_925 = and(out_wivalid_1[803], out_wimask_925) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_925 = and(out_woready_1[803], out_womask_925) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8935 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8936 = and(out_f_rivalid_925, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8937 = and(UInt<1>(0h1), out_f_roready_925) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8938 = eq(out_rimask_925, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8939 = eq(out_wimask_925, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8940 = eq(out_romask_925, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8941 = eq(out_womask_925, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8942 = or(_T_1090, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8943 = bits(_out_T_8942, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_926 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_926 = orr(_out_rimask_T_926) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_926 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_926 = andr(_out_wimask_T_926) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_926 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_926 = orr(_out_romask_T_926) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_926 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_926 = andr(_out_womask_T_926) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_926 = and(out_rivalid_1[804], out_rimask_926) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_926 = and(out_roready_1[804], out_romask_926) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_926 = and(out_wivalid_1[804], out_wimask_926) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_926 = and(out_woready_1[804], out_womask_926) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8944 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8945 = and(out_f_rivalid_926, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8946 = and(UInt<1>(0h1), out_f_roready_926) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8947 = eq(out_rimask_926, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8948 = eq(out_wimask_926, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8949 = eq(out_romask_926, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8950 = eq(out_womask_926, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_793 = or(_out_T_8943, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_793 = cat(_T_1091, _out_prepend_T_793) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8951 = or(out_prepend_793, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8952 = bits(_out_T_8951, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_927 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_927 = orr(_out_rimask_T_927) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_927 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_927 = andr(_out_wimask_T_927) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_927 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_927 = orr(_out_romask_T_927) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_927 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_927 = andr(_out_womask_T_927) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_927 = and(out_rivalid_1[805], out_rimask_927) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_927 = and(out_roready_1[805], out_romask_927) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_927 = and(out_wivalid_1[805], out_wimask_927) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_927 = and(out_woready_1[805], out_womask_927) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8953 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8954 = and(out_f_rivalid_927, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8955 = and(UInt<1>(0h1), out_f_roready_927) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8956 = eq(out_rimask_927, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8957 = eq(out_wimask_927, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8958 = eq(out_romask_927, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8959 = eq(out_womask_927, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_794 = or(_out_T_8952, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_794 = cat(_T_1092, _out_prepend_T_794) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8960 = or(out_prepend_794, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8961 = bits(_out_T_8960, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_928 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_928 = orr(_out_rimask_T_928) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_928 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_928 = andr(_out_wimask_T_928) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_928 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_928 = orr(_out_romask_T_928) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_928 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_928 = andr(_out_womask_T_928) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_928 = and(out_rivalid_1[806], out_rimask_928) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_928 = and(out_roready_1[806], out_romask_928) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_928 = and(out_wivalid_1[806], out_wimask_928) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_928 = and(out_woready_1[806], out_womask_928) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8962 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8963 = and(out_f_rivalid_928, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8964 = and(UInt<1>(0h1), out_f_roready_928) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8965 = eq(out_rimask_928, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8966 = eq(out_wimask_928, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8967 = eq(out_romask_928, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8968 = eq(out_womask_928, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_795 = or(_out_T_8961, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_795 = cat(_T_1093, _out_prepend_T_795) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8969 = or(out_prepend_795, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8970 = bits(_out_T_8969, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_929 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_929 = orr(_out_rimask_T_929) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_929 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_929 = andr(_out_wimask_T_929) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_929 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_929 = orr(_out_romask_T_929) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_929 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_929 = andr(_out_womask_T_929) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_929 = and(out_rivalid_1[807], out_rimask_929) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_929 = and(out_roready_1[807], out_romask_929) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_929 = and(out_wivalid_1[807], out_wimask_929) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_929 = and(out_woready_1[807], out_womask_929) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8971 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8972 = and(out_f_rivalid_929, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8973 = and(UInt<1>(0h1), out_f_roready_929) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8974 = eq(out_rimask_929, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8975 = eq(out_wimask_929, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8976 = eq(out_romask_929, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8977 = eq(out_womask_929, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_796 = or(_out_T_8970, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_796 = cat(_T_1094, _out_prepend_T_796) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8978 = or(out_prepend_796, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8979 = bits(_out_T_8978, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_930 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_930 = orr(_out_rimask_T_930) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_930 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_930 = andr(_out_wimask_T_930) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_930 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_930 = orr(_out_romask_T_930) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_930 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_930 = andr(_out_womask_T_930) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_930 = and(out_rivalid_1[808], out_rimask_930) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_930 = and(out_roready_1[808], out_romask_930) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_930 = and(out_wivalid_1[808], out_wimask_930) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_930 = and(out_woready_1[808], out_womask_930) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8980 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8981 = and(out_f_rivalid_930, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8982 = and(UInt<1>(0h1), out_f_roready_930) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8983 = eq(out_rimask_930, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8984 = eq(out_wimask_930, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8985 = eq(out_romask_930, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8986 = eq(out_womask_930, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_797 = or(_out_T_8979, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_797 = cat(_T_1095, _out_prepend_T_797) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8987 = or(out_prepend_797, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8988 = bits(_out_T_8987, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_931 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_931 = orr(_out_rimask_T_931) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_931 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_931 = andr(_out_wimask_T_931) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_931 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_931 = orr(_out_romask_T_931) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_931 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_931 = andr(_out_womask_T_931) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_931 = and(out_rivalid_1[809], out_rimask_931) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_931 = and(out_roready_1[809], out_romask_931) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_931 = and(out_wivalid_1[809], out_wimask_931) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_931 = and(out_woready_1[809], out_womask_931) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8989 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8990 = and(out_f_rivalid_931, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8991 = and(UInt<1>(0h1), out_f_roready_931) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8992 = eq(out_rimask_931, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8993 = eq(out_wimask_931, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8994 = eq(out_romask_931, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8995 = eq(out_womask_931, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_798 = or(_out_T_8988, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_798 = cat(_T_1096, _out_prepend_T_798) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8996 = or(out_prepend_798, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8997 = bits(_out_T_8996, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_932 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_932 = orr(_out_rimask_T_932) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_932 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_932 = andr(_out_wimask_T_932) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_932 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_932 = orr(_out_romask_T_932) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_932 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_932 = andr(_out_womask_T_932) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_932 = and(out_rivalid_1[810], out_rimask_932) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_932 = and(out_roready_1[810], out_romask_932) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_932 = and(out_wivalid_1[810], out_wimask_932) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_932 = and(out_woready_1[810], out_womask_932) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8998 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8999 = and(out_f_rivalid_932, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9000 = and(UInt<1>(0h1), out_f_roready_932) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9001 = eq(out_rimask_932, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9002 = eq(out_wimask_932, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9003 = eq(out_romask_932, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9004 = eq(out_womask_932, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_799 = or(_out_T_8997, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_799 = cat(_T_1097, _out_prepend_T_799) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9005 = or(out_prepend_799, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9006 = bits(_out_T_9005, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_933 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_933 = orr(_out_rimask_T_933) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_933 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_933 = andr(_out_wimask_T_933) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_933 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_933 = orr(_out_romask_T_933) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_933 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_933 = andr(_out_womask_T_933) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_933 = and(out_rivalid_1[811], out_rimask_933) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_933 = and(out_roready_1[811], out_romask_933) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_933 = and(out_wivalid_1[811], out_wimask_933) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_933 = and(out_woready_1[811], out_womask_933) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9007 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_933 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect abstractDataMem[0], _out_T_9007 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_9008 = and(out_f_rivalid_933, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9009 = and(UInt<1>(0h1), out_f_roready_933) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9010 = and(out_f_wivalid_933, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9011 = and(UInt<1>(0h1), out_f_woready_933) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9012 = eq(out_rimask_933, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9013 = eq(out_wimask_933, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9014 = eq(out_romask_933, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9015 = eq(out_womask_933, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9016 = or(abstractDataMem[0], UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9017 = bits(_out_T_9016, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_934 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_934 = orr(_out_rimask_T_934) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_934 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_934 = andr(_out_wimask_T_934) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_934 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_934 = orr(_out_romask_T_934) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_934 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_934 = andr(_out_womask_T_934) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_934 = and(out_rivalid_1[812], out_rimask_934) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_934 = and(out_roready_1[812], out_romask_934) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_934 = and(out_wivalid_1[812], out_wimask_934) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_934 = and(out_woready_1[812], out_womask_934) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9018 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_934 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect abstractDataMem[1], _out_T_9018 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_9019 = and(out_f_rivalid_934, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9020 = and(UInt<1>(0h1), out_f_roready_934) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9021 = and(out_f_wivalid_934, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9022 = and(UInt<1>(0h1), out_f_woready_934) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9023 = eq(out_rimask_934, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9024 = eq(out_wimask_934, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9025 = eq(out_romask_934, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9026 = eq(out_womask_934, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_800 = or(_out_T_9017, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_800 = cat(abstractDataMem[1], _out_prepend_T_800) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9027 = or(out_prepend_800, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9028 = bits(_out_T_9027, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_935 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_935 = orr(_out_rimask_T_935) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_935 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_935 = andr(_out_wimask_T_935) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_935 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_935 = orr(_out_romask_T_935) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_935 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_935 = andr(_out_womask_T_935) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_935 = and(out_rivalid_1[813], out_rimask_935) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_935 = and(out_roready_1[813], out_romask_935) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_935 = and(out_wivalid_1[813], out_wimask_935) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_935 = and(out_woready_1[813], out_womask_935) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9029 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_935 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect abstractDataMem[2], _out_T_9029 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_9030 = and(out_f_rivalid_935, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9031 = and(UInt<1>(0h1), out_f_roready_935) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9032 = and(out_f_wivalid_935, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9033 = and(UInt<1>(0h1), out_f_woready_935) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9034 = eq(out_rimask_935, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9035 = eq(out_wimask_935, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9036 = eq(out_romask_935, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9037 = eq(out_womask_935, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_801 = or(_out_T_9028, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_801 = cat(abstractDataMem[2], _out_prepend_T_801) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9038 = or(out_prepend_801, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9039 = bits(_out_T_9038, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_936 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_936 = orr(_out_rimask_T_936) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_936 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_936 = andr(_out_wimask_T_936) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_936 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_936 = orr(_out_romask_T_936) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_936 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_936 = andr(_out_womask_T_936) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_936 = and(out_rivalid_1[814], out_rimask_936) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_936 = and(out_roready_1[814], out_romask_936) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_936 = and(out_wivalid_1[814], out_wimask_936) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_936 = and(out_woready_1[814], out_womask_936) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9040 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_936 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect abstractDataMem[3], _out_T_9040 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_9041 = and(out_f_rivalid_936, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9042 = and(UInt<1>(0h1), out_f_roready_936) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9043 = and(out_f_wivalid_936, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9044 = and(UInt<1>(0h1), out_f_woready_936) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9045 = eq(out_rimask_936, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9046 = eq(out_wimask_936, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9047 = eq(out_romask_936, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9048 = eq(out_womask_936, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_802 = or(_out_T_9039, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_802 = cat(abstractDataMem[3], _out_prepend_T_802) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9049 = or(out_prepend_802, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9050 = bits(_out_T_9049, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_937 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_937 = orr(_out_rimask_T_937) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_937 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_937 = andr(_out_wimask_T_937) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_937 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_937 = orr(_out_romask_T_937) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_937 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_937 = andr(_out_womask_T_937) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_937 = and(out_rivalid_1[815], out_rimask_937) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_937 = and(out_roready_1[815], out_romask_937) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_937 = and(out_wivalid_1[815], out_wimask_937) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_937 = and(out_woready_1[815], out_womask_937) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9051 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_937 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect abstractDataMem[4], _out_T_9051 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_9052 = and(out_f_rivalid_937, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9053 = and(UInt<1>(0h1), out_f_roready_937) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9054 = and(out_f_wivalid_937, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9055 = and(UInt<1>(0h1), out_f_woready_937) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9056 = eq(out_rimask_937, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9057 = eq(out_wimask_937, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9058 = eq(out_romask_937, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9059 = eq(out_womask_937, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_803 = or(_out_T_9050, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_803 = cat(abstractDataMem[4], _out_prepend_T_803) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9060 = or(out_prepend_803, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9061 = bits(_out_T_9060, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_938 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_938 = orr(_out_rimask_T_938) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_938 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_938 = andr(_out_wimask_T_938) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_938 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_938 = orr(_out_romask_T_938) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_938 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_938 = andr(_out_womask_T_938) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_938 = and(out_rivalid_1[816], out_rimask_938) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_938 = and(out_roready_1[816], out_romask_938) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_938 = and(out_wivalid_1[816], out_wimask_938) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_938 = and(out_woready_1[816], out_womask_938) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9062 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_938 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect abstractDataMem[5], _out_T_9062 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_9063 = and(out_f_rivalid_938, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9064 = and(UInt<1>(0h1), out_f_roready_938) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9065 = and(out_f_wivalid_938, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9066 = and(UInt<1>(0h1), out_f_woready_938) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9067 = eq(out_rimask_938, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9068 = eq(out_wimask_938, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9069 = eq(out_romask_938, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9070 = eq(out_womask_938, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_804 = or(_out_T_9061, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_804 = cat(abstractDataMem[5], _out_prepend_T_804) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9071 = or(out_prepend_804, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9072 = bits(_out_T_9071, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_939 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_939 = orr(_out_rimask_T_939) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_939 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_939 = andr(_out_wimask_T_939) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_939 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_939 = orr(_out_romask_T_939) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_939 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_939 = andr(_out_womask_T_939) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_939 = and(out_rivalid_1[817], out_rimask_939) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_939 = and(out_roready_1[817], out_romask_939) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_939 = and(out_wivalid_1[817], out_wimask_939) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_939 = and(out_woready_1[817], out_womask_939) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9073 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_939 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect abstractDataMem[6], _out_T_9073 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_9074 = and(out_f_rivalid_939, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9075 = and(UInt<1>(0h1), out_f_roready_939) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9076 = and(out_f_wivalid_939, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9077 = and(UInt<1>(0h1), out_f_woready_939) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9078 = eq(out_rimask_939, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9079 = eq(out_wimask_939, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9080 = eq(out_romask_939, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9081 = eq(out_womask_939, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_805 = or(_out_T_9072, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_805 = cat(abstractDataMem[6], _out_prepend_T_805) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9082 = or(out_prepend_805, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9083 = bits(_out_T_9082, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_940 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_940 = orr(_out_rimask_T_940) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_940 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_940 = andr(_out_wimask_T_940) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_940 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_940 = orr(_out_romask_T_940) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_940 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_940 = andr(_out_womask_T_940) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_940 = and(out_rivalid_1[818], out_rimask_940) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_940 = and(out_roready_1[818], out_romask_940) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_940 = and(out_wivalid_1[818], out_wimask_940) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_940 = and(out_woready_1[818], out_womask_940) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9084 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_940 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect abstractDataMem[7], _out_T_9084 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_9085 = and(out_f_rivalid_940, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9086 = and(UInt<1>(0h1), out_f_roready_940) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9087 = and(out_f_wivalid_940, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9088 = and(UInt<1>(0h1), out_f_woready_940) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9089 = eq(out_rimask_940, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9090 = eq(out_wimask_940, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9091 = eq(out_romask_940, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9092 = eq(out_womask_940, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_806 = or(_out_T_9083, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_806 = cat(abstractDataMem[7], _out_prepend_T_806) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9093 = or(out_prepend_806, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9094 = bits(_out_T_9093, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_941 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_941 = orr(_out_rimask_T_941) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_941 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_941 = andr(_out_wimask_T_941) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_941 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_941 = orr(_out_romask_T_941) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_941 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_941 = andr(_out_womask_T_941) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_941 = and(out_rivalid_1[819], out_rimask_941) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_941 = and(out_roready_1[819], out_romask_941) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_941 = and(out_wivalid_1[819], out_wimask_941) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_941 = and(out_woready_1[819], out_womask_941) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9095 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9096 = and(out_f_rivalid_941, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9097 = and(UInt<1>(0h1), out_f_roready_941) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9098 = eq(out_rimask_941, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9099 = eq(out_wimask_941, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9100 = eq(out_romask_941, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9101 = eq(out_womask_941, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9102 = or(_T_970, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9103 = bits(_out_T_9102, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_942 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_942 = orr(_out_rimask_T_942) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_942 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_942 = andr(_out_wimask_T_942) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_942 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_942 = orr(_out_romask_T_942) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_942 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_942 = andr(_out_womask_T_942) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_942 = and(out_rivalid_1[820], out_rimask_942) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_942 = and(out_roready_1[820], out_romask_942) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_942 = and(out_wivalid_1[820], out_wimask_942) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_942 = and(out_woready_1[820], out_womask_942) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9104 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9105 = and(out_f_rivalid_942, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9106 = and(UInt<1>(0h1), out_f_roready_942) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9107 = eq(out_rimask_942, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9108 = eq(out_wimask_942, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9109 = eq(out_romask_942, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9110 = eq(out_womask_942, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_807 = or(_out_T_9103, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_807 = cat(_T_971, _out_prepend_T_807) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9111 = or(out_prepend_807, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9112 = bits(_out_T_9111, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_943 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_943 = orr(_out_rimask_T_943) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_943 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_943 = andr(_out_wimask_T_943) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_943 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_943 = orr(_out_romask_T_943) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_943 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_943 = andr(_out_womask_T_943) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_943 = and(out_rivalid_1[821], out_rimask_943) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_943 = and(out_roready_1[821], out_romask_943) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_943 = and(out_wivalid_1[821], out_wimask_943) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_943 = and(out_woready_1[821], out_womask_943) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9113 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9114 = and(out_f_rivalid_943, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9115 = and(UInt<1>(0h1), out_f_roready_943) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9116 = eq(out_rimask_943, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9117 = eq(out_wimask_943, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9118 = eq(out_romask_943, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9119 = eq(out_womask_943, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_808 = or(_out_T_9112, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_808 = cat(_T_972, _out_prepend_T_808) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9120 = or(out_prepend_808, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9121 = bits(_out_T_9120, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_944 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_944 = orr(_out_rimask_T_944) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_944 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_944 = andr(_out_wimask_T_944) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_944 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_944 = orr(_out_romask_T_944) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_944 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_944 = andr(_out_womask_T_944) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_944 = and(out_rivalid_1[822], out_rimask_944) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_944 = and(out_roready_1[822], out_romask_944) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_944 = and(out_wivalid_1[822], out_wimask_944) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_944 = and(out_woready_1[822], out_womask_944) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9122 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9123 = and(out_f_rivalid_944, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9124 = and(UInt<1>(0h1), out_f_roready_944) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9125 = eq(out_rimask_944, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9126 = eq(out_wimask_944, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9127 = eq(out_romask_944, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9128 = eq(out_womask_944, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_809 = or(_out_T_9121, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_809 = cat(_T_973, _out_prepend_T_809) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9129 = or(out_prepend_809, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9130 = bits(_out_T_9129, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_945 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_945 = orr(_out_rimask_T_945) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_945 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_945 = andr(_out_wimask_T_945) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_945 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_945 = orr(_out_romask_T_945) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_945 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_945 = andr(_out_womask_T_945) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_945 = and(out_rivalid_1[823], out_rimask_945) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_945 = and(out_roready_1[823], out_romask_945) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_945 = and(out_wivalid_1[823], out_wimask_945) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_945 = and(out_woready_1[823], out_womask_945) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9131 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9132 = and(out_f_rivalid_945, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9133 = and(UInt<1>(0h1), out_f_roready_945) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9134 = eq(out_rimask_945, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9135 = eq(out_wimask_945, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9136 = eq(out_romask_945, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9137 = eq(out_womask_945, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_810 = or(_out_T_9130, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_810 = cat(_T_974, _out_prepend_T_810) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9138 = or(out_prepend_810, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9139 = bits(_out_T_9138, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_946 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_946 = orr(_out_rimask_T_946) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_946 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_946 = andr(_out_wimask_T_946) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_946 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_946 = orr(_out_romask_T_946) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_946 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_946 = andr(_out_womask_T_946) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_946 = and(out_rivalid_1[824], out_rimask_946) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_946 = and(out_roready_1[824], out_romask_946) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_946 = and(out_wivalid_1[824], out_wimask_946) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_946 = and(out_woready_1[824], out_womask_946) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9140 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9141 = and(out_f_rivalid_946, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9142 = and(UInt<1>(0h1), out_f_roready_946) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9143 = eq(out_rimask_946, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9144 = eq(out_wimask_946, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9145 = eq(out_romask_946, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9146 = eq(out_womask_946, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_811 = or(_out_T_9139, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_811 = cat(_T_975, _out_prepend_T_811) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9147 = or(out_prepend_811, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9148 = bits(_out_T_9147, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_947 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_947 = orr(_out_rimask_T_947) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_947 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_947 = andr(_out_wimask_T_947) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_947 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_947 = orr(_out_romask_T_947) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_947 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_947 = andr(_out_womask_T_947) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_947 = and(out_rivalid_1[825], out_rimask_947) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_947 = and(out_roready_1[825], out_romask_947) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_947 = and(out_wivalid_1[825], out_wimask_947) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_947 = and(out_woready_1[825], out_womask_947) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9149 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9150 = and(out_f_rivalid_947, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9151 = and(UInt<1>(0h1), out_f_roready_947) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9152 = eq(out_rimask_947, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9153 = eq(out_wimask_947, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9154 = eq(out_romask_947, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9155 = eq(out_womask_947, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_812 = or(_out_T_9148, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_812 = cat(_T_976, _out_prepend_T_812) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9156 = or(out_prepend_812, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9157 = bits(_out_T_9156, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_948 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_948 = orr(_out_rimask_T_948) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_948 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_948 = andr(_out_wimask_T_948) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_948 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_948 = orr(_out_romask_T_948) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_948 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_948 = andr(_out_womask_T_948) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_948 = and(out_rivalid_1[826], out_rimask_948) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_948 = and(out_roready_1[826], out_romask_948) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_948 = and(out_wivalid_1[826], out_wimask_948) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_948 = and(out_woready_1[826], out_womask_948) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9158 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9159 = and(out_f_rivalid_948, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9160 = and(UInt<1>(0h1), out_f_roready_948) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9161 = eq(out_rimask_948, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9162 = eq(out_wimask_948, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9163 = eq(out_romask_948, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9164 = eq(out_womask_948, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_813 = or(_out_T_9157, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_813 = cat(_T_977, _out_prepend_T_813) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9165 = or(out_prepend_813, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9166 = bits(_out_T_9165, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_949 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_949 = orr(_out_rimask_T_949) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_949 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_949 = andr(_out_wimask_T_949) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_949 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_949 = orr(_out_romask_T_949) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_949 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_949 = andr(_out_womask_T_949) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_949 = and(out_rivalid_1[827], out_rimask_949) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_949 = and(out_roready_1[827], out_romask_949) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_949 = and(out_wivalid_1[827], out_wimask_949) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_949 = and(out_woready_1[827], out_womask_949) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9167 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9168 = and(out_f_rivalid_949, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9169 = and(UInt<1>(0h1), out_f_roready_949) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9170 = eq(out_rimask_949, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9171 = eq(out_wimask_949, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9172 = eq(out_romask_949, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9173 = eq(out_womask_949, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9174 = or(_T_578, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9175 = bits(_out_T_9174, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_950 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_950 = orr(_out_rimask_T_950) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_950 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_950 = andr(_out_wimask_T_950) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_950 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_950 = orr(_out_romask_T_950) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_950 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_950 = andr(_out_womask_T_950) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_950 = and(out_rivalid_1[828], out_rimask_950) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_950 = and(out_roready_1[828], out_romask_950) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_950 = and(out_wivalid_1[828], out_wimask_950) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_950 = and(out_woready_1[828], out_womask_950) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9176 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9177 = and(out_f_rivalid_950, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9178 = and(UInt<1>(0h1), out_f_roready_950) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9179 = eq(out_rimask_950, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9180 = eq(out_wimask_950, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9181 = eq(out_romask_950, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9182 = eq(out_womask_950, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_814 = or(_out_T_9175, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_814 = cat(_T_579, _out_prepend_T_814) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9183 = or(out_prepend_814, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9184 = bits(_out_T_9183, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_951 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_951 = orr(_out_rimask_T_951) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_951 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_951 = andr(_out_wimask_T_951) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_951 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_951 = orr(_out_romask_T_951) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_951 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_951 = andr(_out_womask_T_951) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_951 = and(out_rivalid_1[829], out_rimask_951) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_951 = and(out_roready_1[829], out_romask_951) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_951 = and(out_wivalid_1[829], out_wimask_951) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_951 = and(out_woready_1[829], out_womask_951) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9185 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9186 = and(out_f_rivalid_951, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9187 = and(UInt<1>(0h1), out_f_roready_951) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9188 = eq(out_rimask_951, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9189 = eq(out_wimask_951, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9190 = eq(out_romask_951, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9191 = eq(out_womask_951, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_815 = or(_out_T_9184, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_815 = cat(_T_580, _out_prepend_T_815) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9192 = or(out_prepend_815, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9193 = bits(_out_T_9192, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_952 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_952 = orr(_out_rimask_T_952) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_952 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_952 = andr(_out_wimask_T_952) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_952 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_952 = orr(_out_romask_T_952) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_952 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_952 = andr(_out_womask_T_952) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_952 = and(out_rivalid_1[830], out_rimask_952) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_952 = and(out_roready_1[830], out_romask_952) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_952 = and(out_wivalid_1[830], out_wimask_952) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_952 = and(out_woready_1[830], out_womask_952) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9194 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9195 = and(out_f_rivalid_952, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9196 = and(UInt<1>(0h1), out_f_roready_952) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9197 = eq(out_rimask_952, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9198 = eq(out_wimask_952, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9199 = eq(out_romask_952, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9200 = eq(out_womask_952, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_816 = or(_out_T_9193, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_816 = cat(_T_581, _out_prepend_T_816) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9201 = or(out_prepend_816, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9202 = bits(_out_T_9201, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_953 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_953 = orr(_out_rimask_T_953) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_953 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_953 = andr(_out_wimask_T_953) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_953 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_953 = orr(_out_romask_T_953) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_953 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_953 = andr(_out_womask_T_953) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_953 = and(out_rivalid_1[831], out_rimask_953) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_953 = and(out_roready_1[831], out_romask_953) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_953 = and(out_wivalid_1[831], out_wimask_953) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_953 = and(out_woready_1[831], out_womask_953) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9203 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9204 = and(out_f_rivalid_953, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9205 = and(UInt<1>(0h1), out_f_roready_953) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9206 = eq(out_rimask_953, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9207 = eq(out_wimask_953, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9208 = eq(out_romask_953, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9209 = eq(out_womask_953, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_817 = or(_out_T_9202, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_817 = cat(_T_582, _out_prepend_T_817) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9210 = or(out_prepend_817, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9211 = bits(_out_T_9210, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_954 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_954 = orr(_out_rimask_T_954) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_954 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_954 = andr(_out_wimask_T_954) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_954 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_954 = orr(_out_romask_T_954) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_954 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_954 = andr(_out_womask_T_954) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_954 = and(out_rivalid_1[832], out_rimask_954) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_954 = and(out_roready_1[832], out_romask_954) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_954 = and(out_wivalid_1[832], out_wimask_954) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_954 = and(out_woready_1[832], out_womask_954) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9212 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9213 = and(out_f_rivalid_954, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9214 = and(UInt<1>(0h1), out_f_roready_954) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9215 = eq(out_rimask_954, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9216 = eq(out_wimask_954, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9217 = eq(out_romask_954, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9218 = eq(out_womask_954, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_818 = or(_out_T_9211, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_818 = cat(_T_583, _out_prepend_T_818) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9219 = or(out_prepend_818, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9220 = bits(_out_T_9219, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_955 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_955 = orr(_out_rimask_T_955) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_955 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_955 = andr(_out_wimask_T_955) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_955 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_955 = orr(_out_romask_T_955) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_955 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_955 = andr(_out_womask_T_955) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_955 = and(out_rivalid_1[833], out_rimask_955) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_955 = and(out_roready_1[833], out_romask_955) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_955 = and(out_wivalid_1[833], out_wimask_955) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_955 = and(out_woready_1[833], out_womask_955) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9221 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9222 = and(out_f_rivalid_955, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9223 = and(UInt<1>(0h1), out_f_roready_955) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9224 = eq(out_rimask_955, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9225 = eq(out_wimask_955, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9226 = eq(out_romask_955, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9227 = eq(out_womask_955, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_819 = or(_out_T_9220, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_819 = cat(_T_584, _out_prepend_T_819) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9228 = or(out_prepend_819, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9229 = bits(_out_T_9228, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_956 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_956 = orr(_out_rimask_T_956) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_956 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_956 = andr(_out_wimask_T_956) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_956 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_956 = orr(_out_romask_T_956) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_956 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_956 = andr(_out_womask_T_956) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_956 = and(out_rivalid_1[834], out_rimask_956) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_956 = and(out_roready_1[834], out_romask_956) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_956 = and(out_wivalid_1[834], out_wimask_956) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_956 = and(out_woready_1[834], out_womask_956) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9230 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9231 = and(out_f_rivalid_956, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9232 = and(UInt<1>(0h1), out_f_roready_956) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9233 = eq(out_rimask_956, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9234 = eq(out_wimask_956, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9235 = eq(out_romask_956, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9236 = eq(out_womask_956, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_820 = or(_out_T_9229, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_820 = cat(_T_585, _out_prepend_T_820) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9237 = or(out_prepend_820, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9238 = bits(_out_T_9237, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_957 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_957 = orr(_out_rimask_T_957) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_957 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_957 = andr(_out_wimask_T_957) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_957 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_957 = orr(_out_romask_T_957) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_957 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_957 = andr(_out_womask_T_957) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_957 = and(out_rivalid_1[835], out_rimask_957) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_957 = and(out_roready_1[835], out_romask_957) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_957 = and(out_wivalid_1[835], out_wimask_957) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_957 = and(out_woready_1[835], out_womask_957) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9239 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9240 = and(out_f_rivalid_957, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9241 = and(UInt<1>(0h1), out_f_roready_957) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9242 = eq(out_rimask_957, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9243 = eq(out_wimask_957, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9244 = eq(out_romask_957, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9245 = eq(out_womask_957, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9246 = or(_T_618, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9247 = bits(_out_T_9246, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_958 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_958 = orr(_out_rimask_T_958) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_958 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_958 = andr(_out_wimask_T_958) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_958 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_958 = orr(_out_romask_T_958) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_958 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_958 = andr(_out_womask_T_958) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_958 = and(out_rivalid_1[836], out_rimask_958) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_958 = and(out_roready_1[836], out_romask_958) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_958 = and(out_wivalid_1[836], out_wimask_958) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_958 = and(out_woready_1[836], out_womask_958) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9248 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9249 = and(out_f_rivalid_958, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9250 = and(UInt<1>(0h1), out_f_roready_958) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9251 = eq(out_rimask_958, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9252 = eq(out_wimask_958, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9253 = eq(out_romask_958, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9254 = eq(out_womask_958, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_821 = or(_out_T_9247, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_821 = cat(_T_619, _out_prepend_T_821) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9255 = or(out_prepend_821, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9256 = bits(_out_T_9255, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_959 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_959 = orr(_out_rimask_T_959) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_959 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_959 = andr(_out_wimask_T_959) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_959 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_959 = orr(_out_romask_T_959) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_959 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_959 = andr(_out_womask_T_959) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_959 = and(out_rivalid_1[837], out_rimask_959) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_959 = and(out_roready_1[837], out_romask_959) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_959 = and(out_wivalid_1[837], out_wimask_959) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_959 = and(out_woready_1[837], out_womask_959) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9257 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9258 = and(out_f_rivalid_959, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9259 = and(UInt<1>(0h1), out_f_roready_959) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9260 = eq(out_rimask_959, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9261 = eq(out_wimask_959, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9262 = eq(out_romask_959, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9263 = eq(out_womask_959, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_822 = or(_out_T_9256, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_822 = cat(_T_620, _out_prepend_T_822) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9264 = or(out_prepend_822, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9265 = bits(_out_T_9264, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_960 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_960 = orr(_out_rimask_T_960) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_960 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_960 = andr(_out_wimask_T_960) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_960 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_960 = orr(_out_romask_T_960) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_960 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_960 = andr(_out_womask_T_960) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_960 = and(out_rivalid_1[838], out_rimask_960) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_960 = and(out_roready_1[838], out_romask_960) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_960 = and(out_wivalid_1[838], out_wimask_960) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_960 = and(out_woready_1[838], out_womask_960) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9266 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9267 = and(out_f_rivalid_960, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9268 = and(UInt<1>(0h1), out_f_roready_960) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9269 = eq(out_rimask_960, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9270 = eq(out_wimask_960, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9271 = eq(out_romask_960, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9272 = eq(out_womask_960, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_823 = or(_out_T_9265, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_823 = cat(_T_621, _out_prepend_T_823) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9273 = or(out_prepend_823, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9274 = bits(_out_T_9273, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_961 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_961 = orr(_out_rimask_T_961) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_961 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_961 = andr(_out_wimask_T_961) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_961 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_961 = orr(_out_romask_T_961) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_961 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_961 = andr(_out_womask_T_961) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_961 = and(out_rivalid_1[839], out_rimask_961) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_961 = and(out_roready_1[839], out_romask_961) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_961 = and(out_wivalid_1[839], out_wimask_961) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_961 = and(out_woready_1[839], out_womask_961) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9275 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9276 = and(out_f_rivalid_961, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9277 = and(UInt<1>(0h1), out_f_roready_961) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9278 = eq(out_rimask_961, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9279 = eq(out_wimask_961, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9280 = eq(out_romask_961, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9281 = eq(out_womask_961, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_824 = or(_out_T_9274, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_824 = cat(_T_622, _out_prepend_T_824) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9282 = or(out_prepend_824, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9283 = bits(_out_T_9282, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_962 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_962 = orr(_out_rimask_T_962) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_962 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_962 = andr(_out_wimask_T_962) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_962 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_962 = orr(_out_romask_T_962) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_962 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_962 = andr(_out_womask_T_962) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_962 = and(out_rivalid_1[840], out_rimask_962) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_962 = and(out_roready_1[840], out_romask_962) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_962 = and(out_wivalid_1[840], out_wimask_962) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_962 = and(out_woready_1[840], out_womask_962) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9284 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9285 = and(out_f_rivalid_962, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9286 = and(UInt<1>(0h1), out_f_roready_962) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9287 = eq(out_rimask_962, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9288 = eq(out_wimask_962, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9289 = eq(out_romask_962, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9290 = eq(out_womask_962, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_825 = or(_out_T_9283, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_825 = cat(_T_623, _out_prepend_T_825) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9291 = or(out_prepend_825, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9292 = bits(_out_T_9291, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_963 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_963 = orr(_out_rimask_T_963) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_963 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_963 = andr(_out_wimask_T_963) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_963 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_963 = orr(_out_romask_T_963) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_963 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_963 = andr(_out_womask_T_963) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_963 = and(out_rivalid_1[841], out_rimask_963) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_963 = and(out_roready_1[841], out_romask_963) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_963 = and(out_wivalid_1[841], out_wimask_963) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_963 = and(out_woready_1[841], out_womask_963) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9293 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9294 = and(out_f_rivalid_963, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9295 = and(UInt<1>(0h1), out_f_roready_963) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9296 = eq(out_rimask_963, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9297 = eq(out_wimask_963, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9298 = eq(out_romask_963, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9299 = eq(out_womask_963, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_826 = or(_out_T_9292, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_826 = cat(_T_624, _out_prepend_T_826) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9300 = or(out_prepend_826, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9301 = bits(_out_T_9300, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_964 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_964 = orr(_out_rimask_T_964) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_964 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_964 = andr(_out_wimask_T_964) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_964 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_964 = orr(_out_romask_T_964) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_964 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_964 = andr(_out_womask_T_964) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_964 = and(out_rivalid_1[842], out_rimask_964) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_964 = and(out_roready_1[842], out_romask_964) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_964 = and(out_wivalid_1[842], out_wimask_964) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_964 = and(out_woready_1[842], out_womask_964) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9302 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9303 = and(out_f_rivalid_964, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9304 = and(UInt<1>(0h1), out_f_roready_964) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9305 = eq(out_rimask_964, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9306 = eq(out_wimask_964, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9307 = eq(out_romask_964, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9308 = eq(out_womask_964, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_827 = or(_out_T_9301, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_827 = cat(_T_625, _out_prepend_T_827) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9309 = or(out_prepend_827, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9310 = bits(_out_T_9309, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_965 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_965 = orr(_out_rimask_T_965) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_965 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_965 = andr(_out_wimask_T_965) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_965 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_965 = orr(_out_romask_T_965) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_965 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_965 = andr(_out_womask_T_965) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_965 = and(out_rivalid_1[843], out_rimask_965) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_965 = and(out_roready_1[843], out_romask_965) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_965 = and(out_wivalid_1[843], out_wimask_965) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_965 = and(out_woready_1[843], out_womask_965) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9311 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9312 = and(out_f_rivalid_965, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9313 = and(UInt<1>(0h1), out_f_roready_965) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9314 = eq(out_rimask_965, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9315 = eq(out_wimask_965, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9316 = eq(out_romask_965, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9317 = eq(out_womask_965, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9318 = or(UInt<8>(0h67), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9319 = bits(_out_T_9318, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_966 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_966 = orr(_out_rimask_T_966) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_966 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_966 = andr(_out_wimask_T_966) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_966 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_966 = orr(_out_romask_T_966) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_966 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_966 = andr(_out_womask_T_966) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_966 = and(out_rivalid_1[844], out_rimask_966) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_966 = and(out_roready_1[844], out_romask_966) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_966 = and(out_wivalid_1[844], out_wimask_966) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_966 = and(out_woready_1[844], out_womask_966) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9320 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9321 = and(out_f_rivalid_966, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9322 = and(UInt<1>(0h1), out_f_roready_966) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9323 = eq(out_rimask_966, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9324 = eq(out_wimask_966, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9325 = eq(out_romask_966, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9326 = eq(out_womask_966, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_828 = or(_out_T_9319, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_828 = cat(UInt<8>(0h0), _out_prepend_T_828) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9327 = or(out_prepend_828, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9328 = bits(_out_T_9327, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_967 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_967 = orr(_out_rimask_T_967) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_967 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_967 = andr(_out_wimask_T_967) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_967 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_967 = orr(_out_romask_T_967) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_967 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_967 = andr(_out_womask_T_967) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_967 = and(out_rivalid_1[845], out_rimask_967) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_967 = and(out_roready_1[845], out_romask_967) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_967 = and(out_wivalid_1[845], out_wimask_967) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_967 = and(out_woready_1[845], out_womask_967) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9329 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9330 = and(out_f_rivalid_967, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9331 = and(UInt<1>(0h1), out_f_roready_967) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9332 = eq(out_rimask_967, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9333 = eq(out_wimask_967, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9334 = eq(out_romask_967, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9335 = eq(out_womask_967, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_829 = or(_out_T_9328, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_829 = cat(UInt<8>(0h0), _out_prepend_T_829) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9336 = or(out_prepend_829, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9337 = bits(_out_T_9336, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_968 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_968 = orr(_out_rimask_T_968) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_968 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_968 = andr(_out_wimask_T_968) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_968 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_968 = orr(_out_romask_T_968) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_968 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_968 = andr(_out_womask_T_968) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_968 = and(out_rivalid_1[846], out_rimask_968) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_968 = and(out_roready_1[846], out_romask_968) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_968 = and(out_wivalid_1[846], out_wimask_968) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_968 = and(out_woready_1[846], out_womask_968) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9338 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9339 = and(out_f_rivalid_968, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9340 = and(UInt<1>(0h1), out_f_roready_968) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9341 = eq(out_rimask_968, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9342 = eq(out_wimask_968, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9343 = eq(out_romask_968, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9344 = eq(out_womask_968, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_830 = or(_out_T_9337, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_830 = cat(UInt<8>(0h30), _out_prepend_T_830) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9345 = or(out_prepend_830, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9346 = bits(_out_T_9345, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_969 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_969 = orr(_out_rimask_T_969) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_969 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_969 = andr(_out_wimask_T_969) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_969 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_969 = orr(_out_romask_T_969) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_969 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_969 = andr(_out_womask_T_969) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_969 = and(out_rivalid_1[847], out_rimask_969) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_969 = and(out_roready_1[847], out_romask_969) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_969 = and(out_wivalid_1[847], out_wimask_969) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_969 = and(out_woready_1[847], out_womask_969) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9347 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9348 = and(out_f_rivalid_969, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9349 = and(UInt<1>(0h1), out_f_roready_969) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9350 = eq(out_rimask_969, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9351 = eq(out_wimask_969, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9352 = eq(out_romask_969, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9353 = eq(out_womask_969, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_831 = or(_out_T_9346, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_831 = cat(UInt<8>(0h73), _out_prepend_T_831) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9354 = or(out_prepend_831, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9355 = bits(_out_T_9354, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_970 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_970 = orr(_out_rimask_T_970) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_970 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_970 = andr(_out_wimask_T_970) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_970 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_970 = orr(_out_romask_T_970) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_970 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_970 = andr(_out_womask_T_970) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_970 = and(out_rivalid_1[848], out_rimask_970) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_970 = and(out_roready_1[848], out_romask_970) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_970 = and(out_wivalid_1[848], out_wimask_970) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_970 = and(out_woready_1[848], out_womask_970) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9356 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9357 = and(out_f_rivalid_970, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9358 = and(UInt<1>(0h1), out_f_roready_970) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9359 = eq(out_rimask_970, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9360 = eq(out_wimask_970, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9361 = eq(out_romask_970, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9362 = eq(out_womask_970, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_832 = or(_out_T_9355, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_832 = cat(UInt<8>(0h24), _out_prepend_T_832) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9363 = or(out_prepend_832, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9364 = bits(_out_T_9363, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_971 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_971 = orr(_out_rimask_T_971) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_971 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_971 = andr(_out_wimask_T_971) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_971 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_971 = orr(_out_romask_T_971) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_971 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_971 = andr(_out_womask_T_971) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_971 = and(out_rivalid_1[849], out_rimask_971) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_971 = and(out_roready_1[849], out_romask_971) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_971 = and(out_wivalid_1[849], out_wimask_971) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_971 = and(out_woready_1[849], out_womask_971) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9365 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9366 = and(out_f_rivalid_971, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9367 = and(UInt<1>(0h1), out_f_roready_971) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9368 = eq(out_rimask_971, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9369 = eq(out_wimask_971, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9370 = eq(out_romask_971, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9371 = eq(out_womask_971, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_833 = or(_out_T_9364, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_833 = cat(UInt<8>(0h40), _out_prepend_T_833) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9372 = or(out_prepend_833, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9373 = bits(_out_T_9372, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_972 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_972 = orr(_out_rimask_T_972) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_972 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_972 = andr(_out_wimask_T_972) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_972 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_972 = orr(_out_romask_T_972) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_972 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_972 = andr(_out_womask_T_972) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_972 = and(out_rivalid_1[850], out_rimask_972) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_972 = and(out_roready_1[850], out_romask_972) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_972 = and(out_wivalid_1[850], out_wimask_972) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_972 = and(out_woready_1[850], out_womask_972) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9374 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9375 = and(out_f_rivalid_972, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9376 = and(UInt<1>(0h1), out_f_roready_972) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9377 = eq(out_rimask_972, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9378 = eq(out_wimask_972, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9379 = eq(out_romask_972, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9380 = eq(out_womask_972, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_834 = or(_out_T_9373, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_834 = cat(UInt<8>(0hf1), _out_prepend_T_834) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9381 = or(out_prepend_834, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9382 = bits(_out_T_9381, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_973 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_973 = orr(_out_rimask_T_973) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_973 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_973 = andr(_out_wimask_T_973) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_973 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_973 = orr(_out_romask_T_973) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_973 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_973 = andr(_out_womask_T_973) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_973 = and(out_rivalid_1[851], out_rimask_973) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_973 = and(out_roready_1[851], out_romask_973) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_973 = and(out_wivalid_1[851], out_wimask_973) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_973 = and(out_woready_1[851], out_womask_973) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9383 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9384 = and(out_f_rivalid_973, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9385 = and(UInt<1>(0h1), out_f_roready_973) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9386 = eq(out_rimask_973, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9387 = eq(out_wimask_973, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9388 = eq(out_romask_973, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9389 = eq(out_womask_973, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9390 = or(_T_1010, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9391 = bits(_out_T_9390, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_974 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_974 = orr(_out_rimask_T_974) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_974 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_974 = andr(_out_wimask_T_974) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_974 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_974 = orr(_out_romask_T_974) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_974 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_974 = andr(_out_womask_T_974) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_974 = and(out_rivalid_1[852], out_rimask_974) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_974 = and(out_roready_1[852], out_romask_974) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_974 = and(out_wivalid_1[852], out_wimask_974) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_974 = and(out_woready_1[852], out_womask_974) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9392 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9393 = and(out_f_rivalid_974, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9394 = and(UInt<1>(0h1), out_f_roready_974) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9395 = eq(out_rimask_974, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9396 = eq(out_wimask_974, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9397 = eq(out_romask_974, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9398 = eq(out_womask_974, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_835 = or(_out_T_9391, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_835 = cat(_T_1011, _out_prepend_T_835) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9399 = or(out_prepend_835, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9400 = bits(_out_T_9399, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_975 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_975 = orr(_out_rimask_T_975) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_975 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_975 = andr(_out_wimask_T_975) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_975 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_975 = orr(_out_romask_T_975) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_975 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_975 = andr(_out_womask_T_975) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_975 = and(out_rivalid_1[853], out_rimask_975) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_975 = and(out_roready_1[853], out_romask_975) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_975 = and(out_wivalid_1[853], out_wimask_975) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_975 = and(out_woready_1[853], out_womask_975) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9401 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9402 = and(out_f_rivalid_975, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9403 = and(UInt<1>(0h1), out_f_roready_975) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9404 = eq(out_rimask_975, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9405 = eq(out_wimask_975, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9406 = eq(out_romask_975, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9407 = eq(out_womask_975, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_836 = or(_out_T_9400, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_836 = cat(_T_1012, _out_prepend_T_836) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9408 = or(out_prepend_836, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9409 = bits(_out_T_9408, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_976 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_976 = orr(_out_rimask_T_976) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_976 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_976 = andr(_out_wimask_T_976) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_976 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_976 = orr(_out_romask_T_976) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_976 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_976 = andr(_out_womask_T_976) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_976 = and(out_rivalid_1[854], out_rimask_976) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_976 = and(out_roready_1[854], out_romask_976) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_976 = and(out_wivalid_1[854], out_wimask_976) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_976 = and(out_woready_1[854], out_womask_976) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9410 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9411 = and(out_f_rivalid_976, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9412 = and(UInt<1>(0h1), out_f_roready_976) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9413 = eq(out_rimask_976, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9414 = eq(out_wimask_976, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9415 = eq(out_romask_976, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9416 = eq(out_womask_976, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_837 = or(_out_T_9409, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_837 = cat(_T_1013, _out_prepend_T_837) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9417 = or(out_prepend_837, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9418 = bits(_out_T_9417, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_977 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_977 = orr(_out_rimask_T_977) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_977 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_977 = andr(_out_wimask_T_977) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_977 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_977 = orr(_out_romask_T_977) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_977 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_977 = andr(_out_womask_T_977) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_977 = and(out_rivalid_1[855], out_rimask_977) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_977 = and(out_roready_1[855], out_romask_977) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_977 = and(out_wivalid_1[855], out_wimask_977) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_977 = and(out_woready_1[855], out_womask_977) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9419 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9420 = and(out_f_rivalid_977, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9421 = and(UInt<1>(0h1), out_f_roready_977) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9422 = eq(out_rimask_977, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9423 = eq(out_wimask_977, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9424 = eq(out_romask_977, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9425 = eq(out_womask_977, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_838 = or(_out_T_9418, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_838 = cat(_T_1014, _out_prepend_T_838) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9426 = or(out_prepend_838, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9427 = bits(_out_T_9426, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_978 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_978 = orr(_out_rimask_T_978) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_978 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_978 = andr(_out_wimask_T_978) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_978 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_978 = orr(_out_romask_T_978) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_978 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_978 = andr(_out_womask_T_978) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_978 = and(out_rivalid_1[856], out_rimask_978) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_978 = and(out_roready_1[856], out_romask_978) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_978 = and(out_wivalid_1[856], out_wimask_978) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_978 = and(out_woready_1[856], out_womask_978) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9428 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9429 = and(out_f_rivalid_978, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9430 = and(UInt<1>(0h1), out_f_roready_978) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9431 = eq(out_rimask_978, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9432 = eq(out_wimask_978, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9433 = eq(out_romask_978, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9434 = eq(out_womask_978, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_839 = or(_out_T_9427, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_839 = cat(_T_1015, _out_prepend_T_839) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9435 = or(out_prepend_839, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9436 = bits(_out_T_9435, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_979 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_979 = orr(_out_rimask_T_979) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_979 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_979 = andr(_out_wimask_T_979) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_979 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_979 = orr(_out_romask_T_979) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_979 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_979 = andr(_out_womask_T_979) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_979 = and(out_rivalid_1[857], out_rimask_979) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_979 = and(out_roready_1[857], out_romask_979) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_979 = and(out_wivalid_1[857], out_wimask_979) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_979 = and(out_woready_1[857], out_womask_979) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9437 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9438 = and(out_f_rivalid_979, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9439 = and(UInt<1>(0h1), out_f_roready_979) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9440 = eq(out_rimask_979, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9441 = eq(out_wimask_979, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9442 = eq(out_romask_979, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9443 = eq(out_womask_979, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_840 = or(_out_T_9436, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_840 = cat(_T_1016, _out_prepend_T_840) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9444 = or(out_prepend_840, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9445 = bits(_out_T_9444, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_980 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_980 = orr(_out_rimask_T_980) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_980 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_980 = andr(_out_wimask_T_980) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_980 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_980 = orr(_out_romask_T_980) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_980 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_980 = andr(_out_womask_T_980) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_980 = and(out_rivalid_1[858], out_rimask_980) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_980 = and(out_roready_1[858], out_romask_980) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_980 = and(out_wivalid_1[858], out_wimask_980) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_980 = and(out_woready_1[858], out_womask_980) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9446 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9447 = and(out_f_rivalid_980, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9448 = and(UInt<1>(0h1), out_f_roready_980) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9449 = eq(out_rimask_980, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9450 = eq(out_wimask_980, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9451 = eq(out_romask_980, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9452 = eq(out_womask_980, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_841 = or(_out_T_9445, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_841 = cat(_T_1017, _out_prepend_T_841) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9453 = or(out_prepend_841, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9454 = bits(_out_T_9453, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_981 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_981 = orr(_out_rimask_T_981) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_981 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_981 = andr(_out_wimask_T_981) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_981 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_981 = orr(_out_romask_T_981) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_981 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_981 = andr(_out_womask_T_981) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_981 = and(out_rivalid_1[859], out_rimask_981) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_981 = and(out_roready_1[859], out_romask_981) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_981 = and(out_wivalid_1[859], out_wimask_981) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_981 = and(out_woready_1[859], out_womask_981) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9455 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9456 = and(out_f_rivalid_981, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9457 = and(UInt<1>(0h1), out_f_roready_981) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9458 = eq(out_rimask_981, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9459 = eq(out_wimask_981, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9460 = eq(out_romask_981, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9461 = eq(out_womask_981, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9462 = or(_T_834, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9463 = bits(_out_T_9462, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_982 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_982 = orr(_out_rimask_T_982) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_982 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_982 = andr(_out_wimask_T_982) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_982 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_982 = orr(_out_romask_T_982) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_982 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_982 = andr(_out_womask_T_982) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_982 = and(out_rivalid_1[860], out_rimask_982) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_982 = and(out_roready_1[860], out_romask_982) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_982 = and(out_wivalid_1[860], out_wimask_982) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_982 = and(out_woready_1[860], out_womask_982) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9464 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9465 = and(out_f_rivalid_982, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9466 = and(UInt<1>(0h1), out_f_roready_982) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9467 = eq(out_rimask_982, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9468 = eq(out_wimask_982, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9469 = eq(out_romask_982, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9470 = eq(out_womask_982, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_842 = or(_out_T_9463, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_842 = cat(_T_835, _out_prepend_T_842) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9471 = or(out_prepend_842, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9472 = bits(_out_T_9471, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_983 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_983 = orr(_out_rimask_T_983) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_983 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_983 = andr(_out_wimask_T_983) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_983 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_983 = orr(_out_romask_T_983) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_983 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_983 = andr(_out_womask_T_983) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_983 = and(out_rivalid_1[861], out_rimask_983) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_983 = and(out_roready_1[861], out_romask_983) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_983 = and(out_wivalid_1[861], out_wimask_983) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_983 = and(out_woready_1[861], out_womask_983) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9473 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9474 = and(out_f_rivalid_983, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9475 = and(UInt<1>(0h1), out_f_roready_983) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9476 = eq(out_rimask_983, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9477 = eq(out_wimask_983, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9478 = eq(out_romask_983, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9479 = eq(out_womask_983, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_843 = or(_out_T_9472, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_843 = cat(_T_836, _out_prepend_T_843) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9480 = or(out_prepend_843, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9481 = bits(_out_T_9480, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_984 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_984 = orr(_out_rimask_T_984) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_984 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_984 = andr(_out_wimask_T_984) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_984 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_984 = orr(_out_romask_T_984) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_984 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_984 = andr(_out_womask_T_984) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_984 = and(out_rivalid_1[862], out_rimask_984) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_984 = and(out_roready_1[862], out_romask_984) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_984 = and(out_wivalid_1[862], out_wimask_984) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_984 = and(out_woready_1[862], out_womask_984) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9482 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9483 = and(out_f_rivalid_984, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9484 = and(UInt<1>(0h1), out_f_roready_984) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9485 = eq(out_rimask_984, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9486 = eq(out_wimask_984, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9487 = eq(out_romask_984, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9488 = eq(out_womask_984, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_844 = or(_out_T_9481, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_844 = cat(_T_837, _out_prepend_T_844) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9489 = or(out_prepend_844, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9490 = bits(_out_T_9489, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_985 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_985 = orr(_out_rimask_T_985) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_985 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_985 = andr(_out_wimask_T_985) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_985 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_985 = orr(_out_romask_T_985) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_985 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_985 = andr(_out_womask_T_985) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_985 = and(out_rivalid_1[863], out_rimask_985) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_985 = and(out_roready_1[863], out_romask_985) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_985 = and(out_wivalid_1[863], out_wimask_985) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_985 = and(out_woready_1[863], out_womask_985) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9491 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9492 = and(out_f_rivalid_985, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9493 = and(UInt<1>(0h1), out_f_roready_985) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9494 = eq(out_rimask_985, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9495 = eq(out_wimask_985, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9496 = eq(out_romask_985, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9497 = eq(out_womask_985, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_845 = or(_out_T_9490, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_845 = cat(_T_838, _out_prepend_T_845) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9498 = or(out_prepend_845, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9499 = bits(_out_T_9498, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_986 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_986 = orr(_out_rimask_T_986) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_986 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_986 = andr(_out_wimask_T_986) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_986 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_986 = orr(_out_romask_T_986) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_986 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_986 = andr(_out_womask_T_986) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_986 = and(out_rivalid_1[864], out_rimask_986) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_986 = and(out_roready_1[864], out_romask_986) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_986 = and(out_wivalid_1[864], out_wimask_986) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_986 = and(out_woready_1[864], out_womask_986) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9500 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9501 = and(out_f_rivalid_986, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9502 = and(UInt<1>(0h1), out_f_roready_986) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9503 = eq(out_rimask_986, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9504 = eq(out_wimask_986, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9505 = eq(out_romask_986, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9506 = eq(out_womask_986, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_846 = or(_out_T_9499, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_846 = cat(_T_839, _out_prepend_T_846) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9507 = or(out_prepend_846, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9508 = bits(_out_T_9507, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_987 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_987 = orr(_out_rimask_T_987) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_987 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_987 = andr(_out_wimask_T_987) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_987 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_987 = orr(_out_romask_T_987) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_987 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_987 = andr(_out_womask_T_987) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_987 = and(out_rivalid_1[865], out_rimask_987) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_987 = and(out_roready_1[865], out_romask_987) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_987 = and(out_wivalid_1[865], out_wimask_987) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_987 = and(out_woready_1[865], out_womask_987) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9509 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9510 = and(out_f_rivalid_987, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9511 = and(UInt<1>(0h1), out_f_roready_987) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9512 = eq(out_rimask_987, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9513 = eq(out_wimask_987, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9514 = eq(out_romask_987, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9515 = eq(out_womask_987, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_847 = or(_out_T_9508, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_847 = cat(_T_840, _out_prepend_T_847) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9516 = or(out_prepend_847, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9517 = bits(_out_T_9516, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_988 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_988 = orr(_out_rimask_T_988) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_988 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_988 = andr(_out_wimask_T_988) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_988 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_988 = orr(_out_romask_T_988) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_988 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_988 = andr(_out_womask_T_988) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_988 = and(out_rivalid_1[866], out_rimask_988) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_988 = and(out_roready_1[866], out_romask_988) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_988 = and(out_wivalid_1[866], out_wimask_988) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_988 = and(out_woready_1[866], out_womask_988) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9518 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9519 = and(out_f_rivalid_988, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9520 = and(UInt<1>(0h1), out_f_roready_988) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9521 = eq(out_rimask_988, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9522 = eq(out_wimask_988, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9523 = eq(out_romask_988, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9524 = eq(out_womask_988, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_848 = or(_out_T_9517, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_848 = cat(_T_841, _out_prepend_T_848) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9525 = or(out_prepend_848, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9526 = bits(_out_T_9525, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_989 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_989 = orr(_out_rimask_T_989) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_989 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_989 = andr(_out_wimask_T_989) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_989 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_989 = orr(_out_romask_T_989) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_989 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_989 = andr(_out_womask_T_989) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_989 = and(out_rivalid_1[867], out_rimask_989) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_989 = and(out_roready_1[867], out_romask_989) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_989 = and(out_wivalid_1[867], out_wimask_989) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_989 = and(out_woready_1[867], out_womask_989) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9527 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9528 = and(out_f_rivalid_989, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9529 = and(UInt<1>(0h1), out_f_roready_989) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9530 = eq(out_rimask_989, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9531 = eq(out_wimask_989, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9532 = eq(out_romask_989, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9533 = eq(out_womask_989, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9534 = or(_T_874, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9535 = bits(_out_T_9534, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_990 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_990 = orr(_out_rimask_T_990) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_990 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_990 = andr(_out_wimask_T_990) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_990 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_990 = orr(_out_romask_T_990) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_990 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_990 = andr(_out_womask_T_990) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_990 = and(out_rivalid_1[868], out_rimask_990) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_990 = and(out_roready_1[868], out_romask_990) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_990 = and(out_wivalid_1[868], out_wimask_990) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_990 = and(out_woready_1[868], out_womask_990) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9536 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9537 = and(out_f_rivalid_990, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9538 = and(UInt<1>(0h1), out_f_roready_990) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9539 = eq(out_rimask_990, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9540 = eq(out_wimask_990, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9541 = eq(out_romask_990, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9542 = eq(out_womask_990, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_849 = or(_out_T_9535, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_849 = cat(_T_875, _out_prepend_T_849) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9543 = or(out_prepend_849, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9544 = bits(_out_T_9543, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_991 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_991 = orr(_out_rimask_T_991) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_991 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_991 = andr(_out_wimask_T_991) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_991 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_991 = orr(_out_romask_T_991) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_991 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_991 = andr(_out_womask_T_991) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_991 = and(out_rivalid_1[869], out_rimask_991) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_991 = and(out_roready_1[869], out_romask_991) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_991 = and(out_wivalid_1[869], out_wimask_991) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_991 = and(out_woready_1[869], out_womask_991) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9545 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9546 = and(out_f_rivalid_991, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9547 = and(UInt<1>(0h1), out_f_roready_991) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9548 = eq(out_rimask_991, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9549 = eq(out_wimask_991, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9550 = eq(out_romask_991, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9551 = eq(out_womask_991, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_850 = or(_out_T_9544, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_850 = cat(_T_876, _out_prepend_T_850) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9552 = or(out_prepend_850, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9553 = bits(_out_T_9552, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_992 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_992 = orr(_out_rimask_T_992) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_992 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_992 = andr(_out_wimask_T_992) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_992 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_992 = orr(_out_romask_T_992) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_992 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_992 = andr(_out_womask_T_992) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_992 = and(out_rivalid_1[870], out_rimask_992) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_992 = and(out_roready_1[870], out_romask_992) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_992 = and(out_wivalid_1[870], out_wimask_992) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_992 = and(out_woready_1[870], out_womask_992) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9554 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9555 = and(out_f_rivalid_992, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9556 = and(UInt<1>(0h1), out_f_roready_992) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9557 = eq(out_rimask_992, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9558 = eq(out_wimask_992, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9559 = eq(out_romask_992, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9560 = eq(out_womask_992, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_851 = or(_out_T_9553, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_851 = cat(_T_877, _out_prepend_T_851) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9561 = or(out_prepend_851, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9562 = bits(_out_T_9561, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_993 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_993 = orr(_out_rimask_T_993) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_993 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_993 = andr(_out_wimask_T_993) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_993 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_993 = orr(_out_romask_T_993) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_993 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_993 = andr(_out_womask_T_993) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_993 = and(out_rivalid_1[871], out_rimask_993) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_993 = and(out_roready_1[871], out_romask_993) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_993 = and(out_wivalid_1[871], out_wimask_993) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_993 = and(out_woready_1[871], out_womask_993) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9563 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9564 = and(out_f_rivalid_993, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9565 = and(UInt<1>(0h1), out_f_roready_993) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9566 = eq(out_rimask_993, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9567 = eq(out_wimask_993, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9568 = eq(out_romask_993, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9569 = eq(out_womask_993, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_852 = or(_out_T_9562, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_852 = cat(_T_878, _out_prepend_T_852) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9570 = or(out_prepend_852, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9571 = bits(_out_T_9570, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_994 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_994 = orr(_out_rimask_T_994) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_994 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_994 = andr(_out_wimask_T_994) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_994 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_994 = orr(_out_romask_T_994) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_994 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_994 = andr(_out_womask_T_994) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_994 = and(out_rivalid_1[872], out_rimask_994) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_994 = and(out_roready_1[872], out_romask_994) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_994 = and(out_wivalid_1[872], out_wimask_994) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_994 = and(out_woready_1[872], out_womask_994) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9572 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9573 = and(out_f_rivalid_994, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9574 = and(UInt<1>(0h1), out_f_roready_994) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9575 = eq(out_rimask_994, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9576 = eq(out_wimask_994, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9577 = eq(out_romask_994, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9578 = eq(out_womask_994, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_853 = or(_out_T_9571, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_853 = cat(_T_879, _out_prepend_T_853) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9579 = or(out_prepend_853, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9580 = bits(_out_T_9579, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_995 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_995 = orr(_out_rimask_T_995) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_995 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_995 = andr(_out_wimask_T_995) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_995 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_995 = orr(_out_romask_T_995) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_995 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_995 = andr(_out_womask_T_995) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_995 = and(out_rivalid_1[873], out_rimask_995) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_995 = and(out_roready_1[873], out_romask_995) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_995 = and(out_wivalid_1[873], out_wimask_995) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_995 = and(out_woready_1[873], out_womask_995) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9581 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9582 = and(out_f_rivalid_995, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9583 = and(UInt<1>(0h1), out_f_roready_995) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9584 = eq(out_rimask_995, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9585 = eq(out_wimask_995, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9586 = eq(out_romask_995, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9587 = eq(out_womask_995, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_854 = or(_out_T_9580, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_854 = cat(_T_880, _out_prepend_T_854) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9588 = or(out_prepend_854, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9589 = bits(_out_T_9588, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_996 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_996 = orr(_out_rimask_T_996) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_996 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_996 = andr(_out_wimask_T_996) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_996 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_996 = orr(_out_romask_T_996) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_996 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_996 = andr(_out_womask_T_996) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_996 = and(out_rivalid_1[874], out_rimask_996) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_996 = and(out_roready_1[874], out_romask_996) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_996 = and(out_wivalid_1[874], out_wimask_996) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_996 = and(out_woready_1[874], out_womask_996) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9590 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9591 = and(out_f_rivalid_996, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9592 = and(UInt<1>(0h1), out_f_roready_996) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9593 = eq(out_rimask_996, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9594 = eq(out_wimask_996, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9595 = eq(out_romask_996, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9596 = eq(out_womask_996, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_855 = or(_out_T_9589, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_855 = cat(_T_881, _out_prepend_T_855) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9597 = or(out_prepend_855, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9598 = bits(_out_T_9597, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_997 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_997 = orr(_out_rimask_T_997) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_997 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_997 = andr(_out_wimask_T_997) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_997 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_997 = orr(_out_romask_T_997) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_997 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_997 = andr(_out_womask_T_997) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_997 = and(out_rivalid_1[875], out_rimask_997) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_997 = and(out_roready_1[875], out_romask_997) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_997 = and(out_wivalid_1[875], out_wimask_997) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_997 = and(out_woready_1[875], out_womask_997) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9599 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9600 = and(out_f_rivalid_997, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9601 = and(UInt<1>(0h1), out_f_roready_997) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9602 = eq(out_rimask_997, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9603 = eq(out_wimask_997, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9604 = eq(out_romask_997, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9605 = eq(out_womask_997, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9606 = or(_T_650, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9607 = bits(_out_T_9606, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_998 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_998 = orr(_out_rimask_T_998) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_998 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_998 = andr(_out_wimask_T_998) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_998 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_998 = orr(_out_romask_T_998) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_998 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_998 = andr(_out_womask_T_998) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_998 = and(out_rivalid_1[876], out_rimask_998) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_998 = and(out_roready_1[876], out_romask_998) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_998 = and(out_wivalid_1[876], out_wimask_998) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_998 = and(out_woready_1[876], out_womask_998) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9608 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9609 = and(out_f_rivalid_998, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9610 = and(UInt<1>(0h1), out_f_roready_998) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9611 = eq(out_rimask_998, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9612 = eq(out_wimask_998, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9613 = eq(out_romask_998, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9614 = eq(out_womask_998, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_856 = or(_out_T_9607, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_856 = cat(_T_651, _out_prepend_T_856) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9615 = or(out_prepend_856, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9616 = bits(_out_T_9615, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_999 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_999 = orr(_out_rimask_T_999) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_999 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_999 = andr(_out_wimask_T_999) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_999 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_999 = orr(_out_romask_T_999) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_999 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_999 = andr(_out_womask_T_999) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_999 = and(out_rivalid_1[877], out_rimask_999) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_999 = and(out_roready_1[877], out_romask_999) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_999 = and(out_wivalid_1[877], out_wimask_999) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_999 = and(out_woready_1[877], out_womask_999) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9617 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9618 = and(out_f_rivalid_999, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9619 = and(UInt<1>(0h1), out_f_roready_999) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9620 = eq(out_rimask_999, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9621 = eq(out_wimask_999, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9622 = eq(out_romask_999, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9623 = eq(out_womask_999, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_857 = or(_out_T_9616, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_857 = cat(_T_652, _out_prepend_T_857) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9624 = or(out_prepend_857, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9625 = bits(_out_T_9624, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1000 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1000 = orr(_out_rimask_T_1000) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1000 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1000 = andr(_out_wimask_T_1000) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1000 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1000 = orr(_out_romask_T_1000) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1000 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1000 = andr(_out_womask_T_1000) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1000 = and(out_rivalid_1[878], out_rimask_1000) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1000 = and(out_roready_1[878], out_romask_1000) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1000 = and(out_wivalid_1[878], out_wimask_1000) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1000 = and(out_woready_1[878], out_womask_1000) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9626 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9627 = and(out_f_rivalid_1000, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9628 = and(UInt<1>(0h1), out_f_roready_1000) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9629 = eq(out_rimask_1000, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9630 = eq(out_wimask_1000, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9631 = eq(out_romask_1000, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9632 = eq(out_womask_1000, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_858 = or(_out_T_9625, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_858 = cat(_T_653, _out_prepend_T_858) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9633 = or(out_prepend_858, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9634 = bits(_out_T_9633, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1001 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1001 = orr(_out_rimask_T_1001) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1001 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1001 = andr(_out_wimask_T_1001) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1001 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1001 = orr(_out_romask_T_1001) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1001 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1001 = andr(_out_womask_T_1001) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1001 = and(out_rivalid_1[879], out_rimask_1001) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1001 = and(out_roready_1[879], out_romask_1001) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1001 = and(out_wivalid_1[879], out_wimask_1001) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1001 = and(out_woready_1[879], out_womask_1001) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9635 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9636 = and(out_f_rivalid_1001, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9637 = and(UInt<1>(0h1), out_f_roready_1001) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9638 = eq(out_rimask_1001, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9639 = eq(out_wimask_1001, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9640 = eq(out_romask_1001, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9641 = eq(out_womask_1001, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_859 = or(_out_T_9634, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_859 = cat(_T_654, _out_prepend_T_859) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9642 = or(out_prepend_859, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9643 = bits(_out_T_9642, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1002 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1002 = orr(_out_rimask_T_1002) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1002 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1002 = andr(_out_wimask_T_1002) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1002 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1002 = orr(_out_romask_T_1002) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1002 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1002 = andr(_out_womask_T_1002) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1002 = and(out_rivalid_1[880], out_rimask_1002) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1002 = and(out_roready_1[880], out_romask_1002) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1002 = and(out_wivalid_1[880], out_wimask_1002) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1002 = and(out_woready_1[880], out_womask_1002) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9644 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9645 = and(out_f_rivalid_1002, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9646 = and(UInt<1>(0h1), out_f_roready_1002) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9647 = eq(out_rimask_1002, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9648 = eq(out_wimask_1002, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9649 = eq(out_romask_1002, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9650 = eq(out_womask_1002, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_860 = or(_out_T_9643, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_860 = cat(_T_655, _out_prepend_T_860) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9651 = or(out_prepend_860, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9652 = bits(_out_T_9651, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1003 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1003 = orr(_out_rimask_T_1003) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1003 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1003 = andr(_out_wimask_T_1003) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1003 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1003 = orr(_out_romask_T_1003) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1003 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1003 = andr(_out_womask_T_1003) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1003 = and(out_rivalid_1[881], out_rimask_1003) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1003 = and(out_roready_1[881], out_romask_1003) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1003 = and(out_wivalid_1[881], out_wimask_1003) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1003 = and(out_woready_1[881], out_womask_1003) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9653 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9654 = and(out_f_rivalid_1003, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9655 = and(UInt<1>(0h1), out_f_roready_1003) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9656 = eq(out_rimask_1003, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9657 = eq(out_wimask_1003, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9658 = eq(out_romask_1003, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9659 = eq(out_womask_1003, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_861 = or(_out_T_9652, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_861 = cat(_T_656, _out_prepend_T_861) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9660 = or(out_prepend_861, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9661 = bits(_out_T_9660, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1004 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1004 = orr(_out_rimask_T_1004) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1004 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1004 = andr(_out_wimask_T_1004) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1004 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1004 = orr(_out_romask_T_1004) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1004 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1004 = andr(_out_womask_T_1004) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1004 = and(out_rivalid_1[882], out_rimask_1004) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1004 = and(out_roready_1[882], out_romask_1004) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1004 = and(out_wivalid_1[882], out_wimask_1004) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1004 = and(out_woready_1[882], out_womask_1004) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9662 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9663 = and(out_f_rivalid_1004, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9664 = and(UInt<1>(0h1), out_f_roready_1004) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9665 = eq(out_rimask_1004, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9666 = eq(out_wimask_1004, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9667 = eq(out_romask_1004, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9668 = eq(out_womask_1004, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_862 = or(_out_T_9661, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_862 = cat(_T_657, _out_prepend_T_862) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9669 = or(out_prepend_862, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9670 = bits(_out_T_9669, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1005 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1005 = orr(_out_rimask_T_1005) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1005 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1005 = andr(_out_wimask_T_1005) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1005 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1005 = orr(_out_romask_T_1005) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1005 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1005 = andr(_out_womask_T_1005) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1005 = and(out_rivalid_1[883], out_rimask_1005) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1005 = and(out_roready_1[883], out_romask_1005) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1005 = and(out_wivalid_1[883], out_wimask_1005) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1005 = and(out_woready_1[883], out_womask_1005) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9671 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9672 = and(out_f_rivalid_1005, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9673 = and(UInt<1>(0h1), out_f_roready_1005) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9674 = eq(out_rimask_1005, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9675 = eq(out_wimask_1005, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9676 = eq(out_romask_1005, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9677 = eq(out_womask_1005, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9678 = or(_T_818, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9679 = bits(_out_T_9678, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1006 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1006 = orr(_out_rimask_T_1006) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1006 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1006 = andr(_out_wimask_T_1006) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1006 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1006 = orr(_out_romask_T_1006) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1006 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1006 = andr(_out_womask_T_1006) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1006 = and(out_rivalid_1[884], out_rimask_1006) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1006 = and(out_roready_1[884], out_romask_1006) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1006 = and(out_wivalid_1[884], out_wimask_1006) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1006 = and(out_woready_1[884], out_womask_1006) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9680 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9681 = and(out_f_rivalid_1006, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9682 = and(UInt<1>(0h1), out_f_roready_1006) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9683 = eq(out_rimask_1006, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9684 = eq(out_wimask_1006, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9685 = eq(out_romask_1006, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9686 = eq(out_womask_1006, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_863 = or(_out_T_9679, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_863 = cat(_T_819, _out_prepend_T_863) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9687 = or(out_prepend_863, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9688 = bits(_out_T_9687, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1007 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1007 = orr(_out_rimask_T_1007) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1007 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1007 = andr(_out_wimask_T_1007) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1007 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1007 = orr(_out_romask_T_1007) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1007 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1007 = andr(_out_womask_T_1007) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1007 = and(out_rivalid_1[885], out_rimask_1007) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1007 = and(out_roready_1[885], out_romask_1007) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1007 = and(out_wivalid_1[885], out_wimask_1007) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1007 = and(out_woready_1[885], out_womask_1007) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9689 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9690 = and(out_f_rivalid_1007, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9691 = and(UInt<1>(0h1), out_f_roready_1007) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9692 = eq(out_rimask_1007, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9693 = eq(out_wimask_1007, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9694 = eq(out_romask_1007, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9695 = eq(out_womask_1007, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_864 = or(_out_T_9688, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_864 = cat(_T_820, _out_prepend_T_864) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9696 = or(out_prepend_864, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9697 = bits(_out_T_9696, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1008 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1008 = orr(_out_rimask_T_1008) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1008 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1008 = andr(_out_wimask_T_1008) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1008 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1008 = orr(_out_romask_T_1008) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1008 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1008 = andr(_out_womask_T_1008) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1008 = and(out_rivalid_1[886], out_rimask_1008) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1008 = and(out_roready_1[886], out_romask_1008) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1008 = and(out_wivalid_1[886], out_wimask_1008) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1008 = and(out_woready_1[886], out_womask_1008) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9698 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9699 = and(out_f_rivalid_1008, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9700 = and(UInt<1>(0h1), out_f_roready_1008) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9701 = eq(out_rimask_1008, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9702 = eq(out_wimask_1008, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9703 = eq(out_romask_1008, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9704 = eq(out_womask_1008, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_865 = or(_out_T_9697, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_865 = cat(_T_821, _out_prepend_T_865) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9705 = or(out_prepend_865, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9706 = bits(_out_T_9705, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1009 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1009 = orr(_out_rimask_T_1009) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1009 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1009 = andr(_out_wimask_T_1009) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1009 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1009 = orr(_out_romask_T_1009) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1009 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1009 = andr(_out_womask_T_1009) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1009 = and(out_rivalid_1[887], out_rimask_1009) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1009 = and(out_roready_1[887], out_romask_1009) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1009 = and(out_wivalid_1[887], out_wimask_1009) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1009 = and(out_woready_1[887], out_womask_1009) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9707 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9708 = and(out_f_rivalid_1009, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9709 = and(UInt<1>(0h1), out_f_roready_1009) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9710 = eq(out_rimask_1009, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9711 = eq(out_wimask_1009, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9712 = eq(out_romask_1009, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9713 = eq(out_womask_1009, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_866 = or(_out_T_9706, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_866 = cat(_T_822, _out_prepend_T_866) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9714 = or(out_prepend_866, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9715 = bits(_out_T_9714, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1010 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1010 = orr(_out_rimask_T_1010) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1010 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1010 = andr(_out_wimask_T_1010) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1010 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1010 = orr(_out_romask_T_1010) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1010 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1010 = andr(_out_womask_T_1010) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1010 = and(out_rivalid_1[888], out_rimask_1010) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1010 = and(out_roready_1[888], out_romask_1010) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1010 = and(out_wivalid_1[888], out_wimask_1010) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1010 = and(out_woready_1[888], out_womask_1010) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9716 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9717 = and(out_f_rivalid_1010, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9718 = and(UInt<1>(0h1), out_f_roready_1010) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9719 = eq(out_rimask_1010, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9720 = eq(out_wimask_1010, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9721 = eq(out_romask_1010, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9722 = eq(out_womask_1010, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_867 = or(_out_T_9715, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_867 = cat(_T_823, _out_prepend_T_867) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9723 = or(out_prepend_867, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9724 = bits(_out_T_9723, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1011 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1011 = orr(_out_rimask_T_1011) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1011 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1011 = andr(_out_wimask_T_1011) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1011 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1011 = orr(_out_romask_T_1011) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1011 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1011 = andr(_out_womask_T_1011) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1011 = and(out_rivalid_1[889], out_rimask_1011) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1011 = and(out_roready_1[889], out_romask_1011) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1011 = and(out_wivalid_1[889], out_wimask_1011) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1011 = and(out_woready_1[889], out_womask_1011) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9725 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9726 = and(out_f_rivalid_1011, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9727 = and(UInt<1>(0h1), out_f_roready_1011) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9728 = eq(out_rimask_1011, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9729 = eq(out_wimask_1011, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9730 = eq(out_romask_1011, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9731 = eq(out_womask_1011, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_868 = or(_out_T_9724, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_868 = cat(_T_824, _out_prepend_T_868) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9732 = or(out_prepend_868, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9733 = bits(_out_T_9732, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1012 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1012 = orr(_out_rimask_T_1012) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1012 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1012 = andr(_out_wimask_T_1012) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1012 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1012 = orr(_out_romask_T_1012) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1012 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1012 = andr(_out_womask_T_1012) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1012 = and(out_rivalid_1[890], out_rimask_1012) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1012 = and(out_roready_1[890], out_romask_1012) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1012 = and(out_wivalid_1[890], out_wimask_1012) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1012 = and(out_woready_1[890], out_womask_1012) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9734 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9735 = and(out_f_rivalid_1012, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9736 = and(UInt<1>(0h1), out_f_roready_1012) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9737 = eq(out_rimask_1012, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9738 = eq(out_wimask_1012, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9739 = eq(out_romask_1012, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9740 = eq(out_womask_1012, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_869 = or(_out_T_9733, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_869 = cat(_T_825, _out_prepend_T_869) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9741 = or(out_prepend_869, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9742 = bits(_out_T_9741, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1013 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1013 = orr(_out_rimask_T_1013) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1013 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1013 = andr(_out_wimask_T_1013) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1013 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1013 = orr(_out_romask_T_1013) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1013 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1013 = andr(_out_womask_T_1013) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1013 = and(out_rivalid_1[891], out_rimask_1013) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1013 = and(out_roready_1[891], out_romask_1013) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1013 = and(out_wivalid_1[891], out_wimask_1013) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1013 = and(out_woready_1[891], out_womask_1013) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9743 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9744 = and(out_f_rivalid_1013, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9745 = and(UInt<1>(0h1), out_f_roready_1013) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9746 = eq(out_rimask_1013, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9747 = eq(out_wimask_1013, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9748 = eq(out_romask_1013, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9749 = eq(out_womask_1013, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9750 = or(_T_562, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9751 = bits(_out_T_9750, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1014 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1014 = orr(_out_rimask_T_1014) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1014 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1014 = andr(_out_wimask_T_1014) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1014 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1014 = orr(_out_romask_T_1014) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1014 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1014 = andr(_out_womask_T_1014) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1014 = and(out_rivalid_1[892], out_rimask_1014) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1014 = and(out_roready_1[892], out_romask_1014) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1014 = and(out_wivalid_1[892], out_wimask_1014) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1014 = and(out_woready_1[892], out_womask_1014) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9752 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9753 = and(out_f_rivalid_1014, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9754 = and(UInt<1>(0h1), out_f_roready_1014) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9755 = eq(out_rimask_1014, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9756 = eq(out_wimask_1014, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9757 = eq(out_romask_1014, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9758 = eq(out_womask_1014, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_870 = or(_out_T_9751, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_870 = cat(_T_563, _out_prepend_T_870) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9759 = or(out_prepend_870, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9760 = bits(_out_T_9759, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1015 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1015 = orr(_out_rimask_T_1015) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1015 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1015 = andr(_out_wimask_T_1015) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1015 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1015 = orr(_out_romask_T_1015) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1015 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1015 = andr(_out_womask_T_1015) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1015 = and(out_rivalid_1[893], out_rimask_1015) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1015 = and(out_roready_1[893], out_romask_1015) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1015 = and(out_wivalid_1[893], out_wimask_1015) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1015 = and(out_woready_1[893], out_womask_1015) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9761 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9762 = and(out_f_rivalid_1015, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9763 = and(UInt<1>(0h1), out_f_roready_1015) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9764 = eq(out_rimask_1015, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9765 = eq(out_wimask_1015, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9766 = eq(out_romask_1015, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9767 = eq(out_womask_1015, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_871 = or(_out_T_9760, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_871 = cat(_T_564, _out_prepend_T_871) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9768 = or(out_prepend_871, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9769 = bits(_out_T_9768, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1016 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1016 = orr(_out_rimask_T_1016) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1016 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1016 = andr(_out_wimask_T_1016) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1016 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1016 = orr(_out_romask_T_1016) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1016 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1016 = andr(_out_womask_T_1016) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1016 = and(out_rivalid_1[894], out_rimask_1016) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1016 = and(out_roready_1[894], out_romask_1016) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1016 = and(out_wivalid_1[894], out_wimask_1016) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1016 = and(out_woready_1[894], out_womask_1016) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9770 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9771 = and(out_f_rivalid_1016, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9772 = and(UInt<1>(0h1), out_f_roready_1016) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9773 = eq(out_rimask_1016, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9774 = eq(out_wimask_1016, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9775 = eq(out_romask_1016, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9776 = eq(out_womask_1016, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_872 = or(_out_T_9769, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_872 = cat(_T_565, _out_prepend_T_872) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9777 = or(out_prepend_872, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9778 = bits(_out_T_9777, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1017 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1017 = orr(_out_rimask_T_1017) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1017 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1017 = andr(_out_wimask_T_1017) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1017 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1017 = orr(_out_romask_T_1017) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1017 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1017 = andr(_out_womask_T_1017) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1017 = and(out_rivalid_1[895], out_rimask_1017) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1017 = and(out_roready_1[895], out_romask_1017) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1017 = and(out_wivalid_1[895], out_wimask_1017) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1017 = and(out_woready_1[895], out_womask_1017) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9779 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9780 = and(out_f_rivalid_1017, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9781 = and(UInt<1>(0h1), out_f_roready_1017) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9782 = eq(out_rimask_1017, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9783 = eq(out_wimask_1017, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9784 = eq(out_romask_1017, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9785 = eq(out_womask_1017, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_873 = or(_out_T_9778, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_873 = cat(_T_566, _out_prepend_T_873) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9786 = or(out_prepend_873, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9787 = bits(_out_T_9786, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1018 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1018 = orr(_out_rimask_T_1018) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1018 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1018 = andr(_out_wimask_T_1018) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1018 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1018 = orr(_out_romask_T_1018) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1018 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1018 = andr(_out_womask_T_1018) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1018 = and(out_rivalid_1[896], out_rimask_1018) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1018 = and(out_roready_1[896], out_romask_1018) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1018 = and(out_wivalid_1[896], out_wimask_1018) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1018 = and(out_woready_1[896], out_womask_1018) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9788 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9789 = and(out_f_rivalid_1018, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9790 = and(UInt<1>(0h1), out_f_roready_1018) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9791 = eq(out_rimask_1018, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9792 = eq(out_wimask_1018, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9793 = eq(out_romask_1018, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9794 = eq(out_womask_1018, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_874 = or(_out_T_9787, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_874 = cat(_T_567, _out_prepend_T_874) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9795 = or(out_prepend_874, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9796 = bits(_out_T_9795, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1019 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1019 = orr(_out_rimask_T_1019) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1019 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1019 = andr(_out_wimask_T_1019) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1019 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1019 = orr(_out_romask_T_1019) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1019 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1019 = andr(_out_womask_T_1019) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1019 = and(out_rivalid_1[897], out_rimask_1019) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1019 = and(out_roready_1[897], out_romask_1019) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1019 = and(out_wivalid_1[897], out_wimask_1019) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1019 = and(out_woready_1[897], out_womask_1019) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9797 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9798 = and(out_f_rivalid_1019, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9799 = and(UInt<1>(0h1), out_f_roready_1019) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9800 = eq(out_rimask_1019, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9801 = eq(out_wimask_1019, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9802 = eq(out_romask_1019, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9803 = eq(out_womask_1019, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_875 = or(_out_T_9796, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_875 = cat(_T_568, _out_prepend_T_875) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9804 = or(out_prepend_875, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9805 = bits(_out_T_9804, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1020 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1020 = orr(_out_rimask_T_1020) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1020 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1020 = andr(_out_wimask_T_1020) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1020 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1020 = orr(_out_romask_T_1020) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1020 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1020 = andr(_out_womask_T_1020) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1020 = and(out_rivalid_1[898], out_rimask_1020) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1020 = and(out_roready_1[898], out_romask_1020) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1020 = and(out_wivalid_1[898], out_wimask_1020) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1020 = and(out_woready_1[898], out_womask_1020) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9806 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9807 = and(out_f_rivalid_1020, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9808 = and(UInt<1>(0h1), out_f_roready_1020) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9809 = eq(out_rimask_1020, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9810 = eq(out_wimask_1020, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9811 = eq(out_romask_1020, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9812 = eq(out_womask_1020, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_876 = or(_out_T_9805, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_876 = cat(_T_569, _out_prepend_T_876) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9813 = or(out_prepend_876, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9814 = bits(_out_T_9813, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1021 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1021 = orr(_out_rimask_T_1021) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1021 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1021 = andr(_out_wimask_T_1021) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1021 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1021 = orr(_out_romask_T_1021) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1021 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1021 = andr(_out_womask_T_1021) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1021 = and(out_rivalid_1[899], out_rimask_1021) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1021 = and(out_roready_1[899], out_romask_1021) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1021 = and(out_wivalid_1[899], out_wimask_1021) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1021 = and(out_woready_1[899], out_womask_1021) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9815 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9816 = and(out_f_rivalid_1021, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9817 = and(UInt<1>(0h1), out_f_roready_1021) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9818 = eq(out_rimask_1021, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9819 = eq(out_wimask_1021, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9820 = eq(out_romask_1021, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9821 = eq(out_womask_1021, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9822 = or(_T_1042, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9823 = bits(_out_T_9822, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1022 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1022 = orr(_out_rimask_T_1022) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1022 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1022 = andr(_out_wimask_T_1022) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1022 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1022 = orr(_out_romask_T_1022) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1022 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1022 = andr(_out_womask_T_1022) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1022 = and(out_rivalid_1[900], out_rimask_1022) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1022 = and(out_roready_1[900], out_romask_1022) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1022 = and(out_wivalid_1[900], out_wimask_1022) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1022 = and(out_woready_1[900], out_womask_1022) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9824 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9825 = and(out_f_rivalid_1022, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9826 = and(UInt<1>(0h1), out_f_roready_1022) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9827 = eq(out_rimask_1022, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9828 = eq(out_wimask_1022, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9829 = eq(out_romask_1022, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9830 = eq(out_womask_1022, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_877 = or(_out_T_9823, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_877 = cat(_T_1043, _out_prepend_T_877) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9831 = or(out_prepend_877, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9832 = bits(_out_T_9831, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1023 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1023 = orr(_out_rimask_T_1023) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1023 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1023 = andr(_out_wimask_T_1023) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1023 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1023 = orr(_out_romask_T_1023) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1023 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1023 = andr(_out_womask_T_1023) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1023 = and(out_rivalid_1[901], out_rimask_1023) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1023 = and(out_roready_1[901], out_romask_1023) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1023 = and(out_wivalid_1[901], out_wimask_1023) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1023 = and(out_woready_1[901], out_womask_1023) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9833 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9834 = and(out_f_rivalid_1023, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9835 = and(UInt<1>(0h1), out_f_roready_1023) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9836 = eq(out_rimask_1023, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9837 = eq(out_wimask_1023, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9838 = eq(out_romask_1023, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9839 = eq(out_womask_1023, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_878 = or(_out_T_9832, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_878 = cat(_T_1044, _out_prepend_T_878) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9840 = or(out_prepend_878, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9841 = bits(_out_T_9840, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1024 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1024 = orr(_out_rimask_T_1024) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1024 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1024 = andr(_out_wimask_T_1024) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1024 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1024 = orr(_out_romask_T_1024) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1024 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1024 = andr(_out_womask_T_1024) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1024 = and(out_rivalid_1[902], out_rimask_1024) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1024 = and(out_roready_1[902], out_romask_1024) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1024 = and(out_wivalid_1[902], out_wimask_1024) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1024 = and(out_woready_1[902], out_womask_1024) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9842 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9843 = and(out_f_rivalid_1024, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9844 = and(UInt<1>(0h1), out_f_roready_1024) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9845 = eq(out_rimask_1024, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9846 = eq(out_wimask_1024, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9847 = eq(out_romask_1024, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9848 = eq(out_womask_1024, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_879 = or(_out_T_9841, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_879 = cat(_T_1045, _out_prepend_T_879) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9849 = or(out_prepend_879, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9850 = bits(_out_T_9849, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1025 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1025 = orr(_out_rimask_T_1025) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1025 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1025 = andr(_out_wimask_T_1025) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1025 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1025 = orr(_out_romask_T_1025) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1025 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1025 = andr(_out_womask_T_1025) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1025 = and(out_rivalid_1[903], out_rimask_1025) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1025 = and(out_roready_1[903], out_romask_1025) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1025 = and(out_wivalid_1[903], out_wimask_1025) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1025 = and(out_woready_1[903], out_womask_1025) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9851 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9852 = and(out_f_rivalid_1025, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9853 = and(UInt<1>(0h1), out_f_roready_1025) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9854 = eq(out_rimask_1025, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9855 = eq(out_wimask_1025, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9856 = eq(out_romask_1025, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9857 = eq(out_womask_1025, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_880 = or(_out_T_9850, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_880 = cat(_T_1046, _out_prepend_T_880) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9858 = or(out_prepend_880, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9859 = bits(_out_T_9858, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1026 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1026 = orr(_out_rimask_T_1026) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1026 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1026 = andr(_out_wimask_T_1026) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1026 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1026 = orr(_out_romask_T_1026) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1026 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1026 = andr(_out_womask_T_1026) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1026 = and(out_rivalid_1[904], out_rimask_1026) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1026 = and(out_roready_1[904], out_romask_1026) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1026 = and(out_wivalid_1[904], out_wimask_1026) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1026 = and(out_woready_1[904], out_womask_1026) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9860 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9861 = and(out_f_rivalid_1026, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9862 = and(UInt<1>(0h1), out_f_roready_1026) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9863 = eq(out_rimask_1026, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9864 = eq(out_wimask_1026, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9865 = eq(out_romask_1026, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9866 = eq(out_womask_1026, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_881 = or(_out_T_9859, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_881 = cat(_T_1047, _out_prepend_T_881) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9867 = or(out_prepend_881, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9868 = bits(_out_T_9867, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1027 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1027 = orr(_out_rimask_T_1027) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1027 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1027 = andr(_out_wimask_T_1027) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1027 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1027 = orr(_out_romask_T_1027) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1027 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1027 = andr(_out_womask_T_1027) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1027 = and(out_rivalid_1[905], out_rimask_1027) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1027 = and(out_roready_1[905], out_romask_1027) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1027 = and(out_wivalid_1[905], out_wimask_1027) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1027 = and(out_woready_1[905], out_womask_1027) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9869 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9870 = and(out_f_rivalid_1027, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9871 = and(UInt<1>(0h1), out_f_roready_1027) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9872 = eq(out_rimask_1027, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9873 = eq(out_wimask_1027, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9874 = eq(out_romask_1027, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9875 = eq(out_womask_1027, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_882 = or(_out_T_9868, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_882 = cat(_T_1048, _out_prepend_T_882) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9876 = or(out_prepend_882, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9877 = bits(_out_T_9876, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1028 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1028 = orr(_out_rimask_T_1028) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1028 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1028 = andr(_out_wimask_T_1028) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1028 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1028 = orr(_out_romask_T_1028) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1028 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1028 = andr(_out_womask_T_1028) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1028 = and(out_rivalid_1[906], out_rimask_1028) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1028 = and(out_roready_1[906], out_romask_1028) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1028 = and(out_wivalid_1[906], out_wimask_1028) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1028 = and(out_woready_1[906], out_womask_1028) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9878 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9879 = and(out_f_rivalid_1028, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9880 = and(UInt<1>(0h1), out_f_roready_1028) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9881 = eq(out_rimask_1028, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9882 = eq(out_wimask_1028, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9883 = eq(out_romask_1028, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9884 = eq(out_womask_1028, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_883 = or(_out_T_9877, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_883 = cat(_T_1049, _out_prepend_T_883) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9885 = or(out_prepend_883, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9886 = bits(_out_T_9885, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1029 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1029 = orr(_out_rimask_T_1029) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1029 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1029 = andr(_out_wimask_T_1029) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1029 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1029 = orr(_out_romask_T_1029) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1029 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1029 = andr(_out_womask_T_1029) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1029 = and(out_rivalid_1[907], out_rimask_1029) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1029 = and(out_roready_1[907], out_romask_1029) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1029 = and(out_wivalid_1[907], out_wimask_1029) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1029 = and(out_woready_1[907], out_womask_1029) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9887 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9888 = and(out_f_rivalid_1029, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9889 = and(UInt<1>(0h1), out_f_roready_1029) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9890 = eq(out_rimask_1029, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9891 = eq(out_wimask_1029, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9892 = eq(out_romask_1029, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9893 = eq(out_womask_1029, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9894 = or(_T_1162, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9895 = bits(_out_T_9894, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1030 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1030 = orr(_out_rimask_T_1030) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1030 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1030 = andr(_out_wimask_T_1030) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1030 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1030 = orr(_out_romask_T_1030) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1030 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1030 = andr(_out_womask_T_1030) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1030 = and(out_rivalid_1[908], out_rimask_1030) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1030 = and(out_roready_1[908], out_romask_1030) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1030 = and(out_wivalid_1[908], out_wimask_1030) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1030 = and(out_woready_1[908], out_womask_1030) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9896 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9897 = and(out_f_rivalid_1030, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9898 = and(UInt<1>(0h1), out_f_roready_1030) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9899 = eq(out_rimask_1030, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9900 = eq(out_wimask_1030, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9901 = eq(out_romask_1030, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9902 = eq(out_womask_1030, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_884 = or(_out_T_9895, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_884 = cat(_T_1163, _out_prepend_T_884) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9903 = or(out_prepend_884, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9904 = bits(_out_T_9903, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1031 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1031 = orr(_out_rimask_T_1031) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1031 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1031 = andr(_out_wimask_T_1031) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1031 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1031 = orr(_out_romask_T_1031) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1031 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1031 = andr(_out_womask_T_1031) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1031 = and(out_rivalid_1[909], out_rimask_1031) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1031 = and(out_roready_1[909], out_romask_1031) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1031 = and(out_wivalid_1[909], out_wimask_1031) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1031 = and(out_woready_1[909], out_womask_1031) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9905 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9906 = and(out_f_rivalid_1031, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9907 = and(UInt<1>(0h1), out_f_roready_1031) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9908 = eq(out_rimask_1031, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9909 = eq(out_wimask_1031, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9910 = eq(out_romask_1031, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9911 = eq(out_womask_1031, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_885 = or(_out_T_9904, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_885 = cat(_T_1164, _out_prepend_T_885) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9912 = or(out_prepend_885, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9913 = bits(_out_T_9912, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1032 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1032 = orr(_out_rimask_T_1032) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1032 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1032 = andr(_out_wimask_T_1032) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1032 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1032 = orr(_out_romask_T_1032) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1032 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1032 = andr(_out_womask_T_1032) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1032 = and(out_rivalid_1[910], out_rimask_1032) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1032 = and(out_roready_1[910], out_romask_1032) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1032 = and(out_wivalid_1[910], out_wimask_1032) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1032 = and(out_woready_1[910], out_womask_1032) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9914 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9915 = and(out_f_rivalid_1032, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9916 = and(UInt<1>(0h1), out_f_roready_1032) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9917 = eq(out_rimask_1032, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9918 = eq(out_wimask_1032, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9919 = eq(out_romask_1032, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9920 = eq(out_womask_1032, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_886 = or(_out_T_9913, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_886 = cat(_T_1165, _out_prepend_T_886) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9921 = or(out_prepend_886, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9922 = bits(_out_T_9921, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1033 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1033 = orr(_out_rimask_T_1033) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1033 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1033 = andr(_out_wimask_T_1033) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1033 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1033 = orr(_out_romask_T_1033) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1033 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1033 = andr(_out_womask_T_1033) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1033 = and(out_rivalid_1[911], out_rimask_1033) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1033 = and(out_roready_1[911], out_romask_1033) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1033 = and(out_wivalid_1[911], out_wimask_1033) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1033 = and(out_woready_1[911], out_womask_1033) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9923 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9924 = and(out_f_rivalid_1033, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9925 = and(UInt<1>(0h1), out_f_roready_1033) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9926 = eq(out_rimask_1033, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9927 = eq(out_wimask_1033, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9928 = eq(out_romask_1033, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9929 = eq(out_womask_1033, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_887 = or(_out_T_9922, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_887 = cat(_T_1166, _out_prepend_T_887) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9930 = or(out_prepend_887, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9931 = bits(_out_T_9930, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1034 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1034 = orr(_out_rimask_T_1034) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1034 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1034 = andr(_out_wimask_T_1034) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1034 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1034 = orr(_out_romask_T_1034) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1034 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1034 = andr(_out_womask_T_1034) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1034 = and(out_rivalid_1[912], out_rimask_1034) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1034 = and(out_roready_1[912], out_romask_1034) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1034 = and(out_wivalid_1[912], out_wimask_1034) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1034 = and(out_woready_1[912], out_womask_1034) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9932 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9933 = and(out_f_rivalid_1034, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9934 = and(UInt<1>(0h1), out_f_roready_1034) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9935 = eq(out_rimask_1034, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9936 = eq(out_wimask_1034, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9937 = eq(out_romask_1034, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9938 = eq(out_womask_1034, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_888 = or(_out_T_9931, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_888 = cat(_T_1167, _out_prepend_T_888) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9939 = or(out_prepend_888, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9940 = bits(_out_T_9939, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1035 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1035 = orr(_out_rimask_T_1035) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1035 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1035 = andr(_out_wimask_T_1035) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1035 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1035 = orr(_out_romask_T_1035) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1035 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1035 = andr(_out_womask_T_1035) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1035 = and(out_rivalid_1[913], out_rimask_1035) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1035 = and(out_roready_1[913], out_romask_1035) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1035 = and(out_wivalid_1[913], out_wimask_1035) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1035 = and(out_woready_1[913], out_womask_1035) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9941 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9942 = and(out_f_rivalid_1035, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9943 = and(UInt<1>(0h1), out_f_roready_1035) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9944 = eq(out_rimask_1035, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9945 = eq(out_wimask_1035, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9946 = eq(out_romask_1035, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9947 = eq(out_womask_1035, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_889 = or(_out_T_9940, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_889 = cat(_T_1168, _out_prepend_T_889) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9948 = or(out_prepend_889, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9949 = bits(_out_T_9948, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1036 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1036 = orr(_out_rimask_T_1036) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1036 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1036 = andr(_out_wimask_T_1036) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1036 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1036 = orr(_out_romask_T_1036) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1036 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1036 = andr(_out_womask_T_1036) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1036 = and(out_rivalid_1[914], out_rimask_1036) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1036 = and(out_roready_1[914], out_romask_1036) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1036 = and(out_wivalid_1[914], out_wimask_1036) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1036 = and(out_woready_1[914], out_womask_1036) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9950 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9951 = and(out_f_rivalid_1036, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9952 = and(UInt<1>(0h1), out_f_roready_1036) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9953 = eq(out_rimask_1036, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9954 = eq(out_wimask_1036, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9955 = eq(out_romask_1036, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9956 = eq(out_womask_1036, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_890 = or(_out_T_9949, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_890 = cat(_T_1169, _out_prepend_T_890) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9957 = or(out_prepend_890, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9958 = bits(_out_T_9957, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1037 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1037 = orr(_out_rimask_T_1037) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1037 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1037 = andr(_out_wimask_T_1037) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1037 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1037 = orr(_out_romask_T_1037) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1037 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1037 = andr(_out_womask_T_1037) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1037 = and(out_rivalid_1[915], out_rimask_1037) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1037 = and(out_roready_1[915], out_romask_1037) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1037 = and(out_wivalid_1[915], out_wimask_1037) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1037 = and(out_woready_1[915], out_womask_1037) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9959 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1037 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[0], _out_T_9959 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_9960 = and(out_f_rivalid_1037, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9961 = and(UInt<1>(0h1), out_f_roready_1037) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9962 = and(out_f_wivalid_1037, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9963 = and(UInt<1>(0h1), out_f_woready_1037) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9964 = eq(out_rimask_1037, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9965 = eq(out_wimask_1037, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9966 = eq(out_romask_1037, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9967 = eq(out_womask_1037, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9968 = or(programBufferMem[0], UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9969 = bits(_out_T_9968, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1038 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1038 = orr(_out_rimask_T_1038) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1038 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1038 = andr(_out_wimask_T_1038) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1038 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1038 = orr(_out_romask_T_1038) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1038 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1038 = andr(_out_womask_T_1038) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1038 = and(out_rivalid_1[916], out_rimask_1038) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1038 = and(out_roready_1[916], out_romask_1038) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1038 = and(out_wivalid_1[916], out_wimask_1038) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1038 = and(out_woready_1[916], out_womask_1038) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9970 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1038 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[1], _out_T_9970 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_9971 = and(out_f_rivalid_1038, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9972 = and(UInt<1>(0h1), out_f_roready_1038) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9973 = and(out_f_wivalid_1038, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9974 = and(UInt<1>(0h1), out_f_woready_1038) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9975 = eq(out_rimask_1038, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9976 = eq(out_wimask_1038, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9977 = eq(out_romask_1038, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9978 = eq(out_womask_1038, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_891 = or(_out_T_9969, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_891 = cat(programBufferMem[1], _out_prepend_T_891) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9979 = or(out_prepend_891, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9980 = bits(_out_T_9979, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1039 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1039 = orr(_out_rimask_T_1039) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1039 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1039 = andr(_out_wimask_T_1039) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1039 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1039 = orr(_out_romask_T_1039) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1039 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1039 = andr(_out_womask_T_1039) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1039 = and(out_rivalid_1[917], out_rimask_1039) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1039 = and(out_roready_1[917], out_romask_1039) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1039 = and(out_wivalid_1[917], out_wimask_1039) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1039 = and(out_woready_1[917], out_womask_1039) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9981 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1039 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[2], _out_T_9981 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_9982 = and(out_f_rivalid_1039, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9983 = and(UInt<1>(0h1), out_f_roready_1039) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9984 = and(out_f_wivalid_1039, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9985 = and(UInt<1>(0h1), out_f_woready_1039) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9986 = eq(out_rimask_1039, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9987 = eq(out_wimask_1039, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9988 = eq(out_romask_1039, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9989 = eq(out_womask_1039, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_892 = or(_out_T_9980, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_892 = cat(programBufferMem[2], _out_prepend_T_892) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9990 = or(out_prepend_892, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9991 = bits(_out_T_9990, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1040 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1040 = orr(_out_rimask_T_1040) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1040 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1040 = andr(_out_wimask_T_1040) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1040 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1040 = orr(_out_romask_T_1040) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1040 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1040 = andr(_out_womask_T_1040) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1040 = and(out_rivalid_1[918], out_rimask_1040) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1040 = and(out_roready_1[918], out_romask_1040) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1040 = and(out_wivalid_1[918], out_wimask_1040) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1040 = and(out_woready_1[918], out_womask_1040) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9992 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1040 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[3], _out_T_9992 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_9993 = and(out_f_rivalid_1040, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9994 = and(UInt<1>(0h1), out_f_roready_1040) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9995 = and(out_f_wivalid_1040, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9996 = and(UInt<1>(0h1), out_f_woready_1040) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9997 = eq(out_rimask_1040, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9998 = eq(out_wimask_1040, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9999 = eq(out_romask_1040, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10000 = eq(out_womask_1040, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_893 = or(_out_T_9991, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_893 = cat(programBufferMem[3], _out_prepend_T_893) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10001 = or(out_prepend_893, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10002 = bits(_out_T_10001, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1041 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1041 = orr(_out_rimask_T_1041) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1041 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1041 = andr(_out_wimask_T_1041) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1041 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1041 = orr(_out_romask_T_1041) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1041 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1041 = andr(_out_womask_T_1041) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1041 = and(out_rivalid_1[919], out_rimask_1041) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1041 = and(out_roready_1[919], out_romask_1041) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1041 = and(out_wivalid_1[919], out_wimask_1041) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1041 = and(out_woready_1[919], out_womask_1041) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10003 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1041 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[4], _out_T_10003 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_10004 = and(out_f_rivalid_1041, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10005 = and(UInt<1>(0h1), out_f_roready_1041) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10006 = and(out_f_wivalid_1041, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10007 = and(UInt<1>(0h1), out_f_woready_1041) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10008 = eq(out_rimask_1041, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10009 = eq(out_wimask_1041, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10010 = eq(out_romask_1041, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10011 = eq(out_womask_1041, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_894 = or(_out_T_10002, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_894 = cat(programBufferMem[4], _out_prepend_T_894) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10012 = or(out_prepend_894, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10013 = bits(_out_T_10012, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1042 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1042 = orr(_out_rimask_T_1042) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1042 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1042 = andr(_out_wimask_T_1042) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1042 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1042 = orr(_out_romask_T_1042) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1042 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1042 = andr(_out_womask_T_1042) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1042 = and(out_rivalid_1[920], out_rimask_1042) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1042 = and(out_roready_1[920], out_romask_1042) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1042 = and(out_wivalid_1[920], out_wimask_1042) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1042 = and(out_woready_1[920], out_womask_1042) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10014 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1042 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[5], _out_T_10014 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_10015 = and(out_f_rivalid_1042, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10016 = and(UInt<1>(0h1), out_f_roready_1042) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10017 = and(out_f_wivalid_1042, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10018 = and(UInt<1>(0h1), out_f_woready_1042) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10019 = eq(out_rimask_1042, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10020 = eq(out_wimask_1042, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10021 = eq(out_romask_1042, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10022 = eq(out_womask_1042, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_895 = or(_out_T_10013, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_895 = cat(programBufferMem[5], _out_prepend_T_895) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10023 = or(out_prepend_895, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10024 = bits(_out_T_10023, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1043 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1043 = orr(_out_rimask_T_1043) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1043 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1043 = andr(_out_wimask_T_1043) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1043 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1043 = orr(_out_romask_T_1043) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1043 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1043 = andr(_out_womask_T_1043) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1043 = and(out_rivalid_1[921], out_rimask_1043) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1043 = and(out_roready_1[921], out_romask_1043) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1043 = and(out_wivalid_1[921], out_wimask_1043) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1043 = and(out_woready_1[921], out_womask_1043) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10025 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1043 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[6], _out_T_10025 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_10026 = and(out_f_rivalid_1043, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10027 = and(UInt<1>(0h1), out_f_roready_1043) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10028 = and(out_f_wivalid_1043, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10029 = and(UInt<1>(0h1), out_f_woready_1043) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10030 = eq(out_rimask_1043, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10031 = eq(out_wimask_1043, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10032 = eq(out_romask_1043, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10033 = eq(out_womask_1043, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_896 = or(_out_T_10024, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_896 = cat(programBufferMem[6], _out_prepend_T_896) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10034 = or(out_prepend_896, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10035 = bits(_out_T_10034, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1044 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1044 = orr(_out_rimask_T_1044) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1044 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1044 = andr(_out_wimask_T_1044) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1044 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1044 = orr(_out_romask_T_1044) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1044 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1044 = andr(_out_womask_T_1044) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1044 = and(out_rivalid_1[922], out_rimask_1044) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1044 = and(out_roready_1[922], out_romask_1044) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1044 = and(out_wivalid_1[922], out_wimask_1044) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1044 = and(out_woready_1[922], out_womask_1044) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10036 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1044 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[7], _out_T_10036 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_10037 = and(out_f_rivalid_1044, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10038 = and(UInt<1>(0h1), out_f_roready_1044) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10039 = and(out_f_wivalid_1044, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10040 = and(UInt<1>(0h1), out_f_woready_1044) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10041 = eq(out_rimask_1044, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10042 = eq(out_wimask_1044, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10043 = eq(out_romask_1044, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10044 = eq(out_womask_1044, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_897 = or(_out_T_10035, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_897 = cat(programBufferMem[7], _out_prepend_T_897) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10045 = or(out_prepend_897, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10046 = bits(_out_T_10045, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1045 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1045 = orr(_out_rimask_T_1045) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1045 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1045 = andr(_out_wimask_T_1045) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1045 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1045 = orr(_out_romask_T_1045) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1045 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1045 = andr(_out_womask_T_1045) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1045 = and(out_rivalid_1[923], out_rimask_1045) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1045 = and(out_roready_1[923], out_romask_1045) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1045 = and(out_wivalid_1[923], out_wimask_1045) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1045 = and(out_woready_1[923], out_womask_1045) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10047 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10048 = and(out_f_rivalid_1045, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10049 = and(UInt<1>(0h1), out_f_roready_1045) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10050 = eq(out_rimask_1045, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10051 = eq(out_wimask_1045, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10052 = eq(out_romask_1045, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10053 = eq(out_womask_1045, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10054 = or(_T_1418, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10055 = bits(_out_T_10054, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1046 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1046 = orr(_out_rimask_T_1046) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1046 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1046 = andr(_out_wimask_T_1046) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1046 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1046 = orr(_out_romask_T_1046) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1046 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1046 = andr(_out_womask_T_1046) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1046 = and(out_rivalid_1[924], out_rimask_1046) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1046 = and(out_roready_1[924], out_romask_1046) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1046 = and(out_wivalid_1[924], out_wimask_1046) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1046 = and(out_woready_1[924], out_womask_1046) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10056 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10057 = and(out_f_rivalid_1046, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10058 = and(UInt<1>(0h1), out_f_roready_1046) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10059 = eq(out_rimask_1046, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10060 = eq(out_wimask_1046, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10061 = eq(out_romask_1046, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10062 = eq(out_womask_1046, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_898 = or(_out_T_10055, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_898 = cat(_T_1419, _out_prepend_T_898) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10063 = or(out_prepend_898, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10064 = bits(_out_T_10063, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1047 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1047 = orr(_out_rimask_T_1047) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1047 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1047 = andr(_out_wimask_T_1047) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1047 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1047 = orr(_out_romask_T_1047) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1047 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1047 = andr(_out_womask_T_1047) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1047 = and(out_rivalid_1[925], out_rimask_1047) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1047 = and(out_roready_1[925], out_romask_1047) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1047 = and(out_wivalid_1[925], out_wimask_1047) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1047 = and(out_woready_1[925], out_womask_1047) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10065 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10066 = and(out_f_rivalid_1047, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10067 = and(UInt<1>(0h1), out_f_roready_1047) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10068 = eq(out_rimask_1047, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10069 = eq(out_wimask_1047, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10070 = eq(out_romask_1047, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10071 = eq(out_womask_1047, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_899 = or(_out_T_10064, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_899 = cat(_T_1420, _out_prepend_T_899) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10072 = or(out_prepend_899, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10073 = bits(_out_T_10072, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1048 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1048 = orr(_out_rimask_T_1048) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1048 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1048 = andr(_out_wimask_T_1048) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1048 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1048 = orr(_out_romask_T_1048) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1048 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1048 = andr(_out_womask_T_1048) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1048 = and(out_rivalid_1[926], out_rimask_1048) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1048 = and(out_roready_1[926], out_romask_1048) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1048 = and(out_wivalid_1[926], out_wimask_1048) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1048 = and(out_woready_1[926], out_womask_1048) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10074 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10075 = and(out_f_rivalid_1048, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10076 = and(UInt<1>(0h1), out_f_roready_1048) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10077 = eq(out_rimask_1048, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10078 = eq(out_wimask_1048, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10079 = eq(out_romask_1048, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10080 = eq(out_womask_1048, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_900 = or(_out_T_10073, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_900 = cat(_T_1421, _out_prepend_T_900) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10081 = or(out_prepend_900, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10082 = bits(_out_T_10081, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1049 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1049 = orr(_out_rimask_T_1049) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1049 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1049 = andr(_out_wimask_T_1049) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1049 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1049 = orr(_out_romask_T_1049) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1049 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1049 = andr(_out_womask_T_1049) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1049 = and(out_rivalid_1[927], out_rimask_1049) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1049 = and(out_roready_1[927], out_romask_1049) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1049 = and(out_wivalid_1[927], out_wimask_1049) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1049 = and(out_woready_1[927], out_womask_1049) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10083 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10084 = and(out_f_rivalid_1049, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10085 = and(UInt<1>(0h1), out_f_roready_1049) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10086 = eq(out_rimask_1049, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10087 = eq(out_wimask_1049, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10088 = eq(out_romask_1049, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10089 = eq(out_womask_1049, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_901 = or(_out_T_10082, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_901 = cat(_T_1422, _out_prepend_T_901) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10090 = or(out_prepend_901, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10091 = bits(_out_T_10090, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1050 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1050 = orr(_out_rimask_T_1050) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1050 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1050 = andr(_out_wimask_T_1050) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1050 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1050 = orr(_out_romask_T_1050) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1050 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1050 = andr(_out_womask_T_1050) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1050 = and(out_rivalid_1[928], out_rimask_1050) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1050 = and(out_roready_1[928], out_romask_1050) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1050 = and(out_wivalid_1[928], out_wimask_1050) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1050 = and(out_woready_1[928], out_womask_1050) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10092 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10093 = and(out_f_rivalid_1050, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10094 = and(UInt<1>(0h1), out_f_roready_1050) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10095 = eq(out_rimask_1050, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10096 = eq(out_wimask_1050, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10097 = eq(out_romask_1050, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10098 = eq(out_womask_1050, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_902 = or(_out_T_10091, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_902 = cat(_T_1423, _out_prepend_T_902) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10099 = or(out_prepend_902, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10100 = bits(_out_T_10099, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1051 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1051 = orr(_out_rimask_T_1051) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1051 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1051 = andr(_out_wimask_T_1051) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1051 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1051 = orr(_out_romask_T_1051) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1051 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1051 = andr(_out_womask_T_1051) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1051 = and(out_rivalid_1[929], out_rimask_1051) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1051 = and(out_roready_1[929], out_romask_1051) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1051 = and(out_wivalid_1[929], out_wimask_1051) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1051 = and(out_woready_1[929], out_womask_1051) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10101 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10102 = and(out_f_rivalid_1051, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10103 = and(UInt<1>(0h1), out_f_roready_1051) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10104 = eq(out_rimask_1051, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10105 = eq(out_wimask_1051, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10106 = eq(out_romask_1051, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10107 = eq(out_womask_1051, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_903 = or(_out_T_10100, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_903 = cat(_T_1424, _out_prepend_T_903) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10108 = or(out_prepend_903, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10109 = bits(_out_T_10108, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1052 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1052 = orr(_out_rimask_T_1052) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1052 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1052 = andr(_out_wimask_T_1052) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1052 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1052 = orr(_out_romask_T_1052) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1052 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1052 = andr(_out_womask_T_1052) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1052 = and(out_rivalid_1[930], out_rimask_1052) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1052 = and(out_roready_1[930], out_romask_1052) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1052 = and(out_wivalid_1[930], out_wimask_1052) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1052 = and(out_woready_1[930], out_womask_1052) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10110 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10111 = and(out_f_rivalid_1052, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10112 = and(UInt<1>(0h1), out_f_roready_1052) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10113 = eq(out_rimask_1052, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10114 = eq(out_wimask_1052, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10115 = eq(out_romask_1052, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10116 = eq(out_womask_1052, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_904 = or(_out_T_10109, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_904 = cat(_T_1425, _out_prepend_T_904) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10117 = or(out_prepend_904, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10118 = bits(_out_T_10117, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1053 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1053 = orr(_out_rimask_T_1053) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1053 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1053 = andr(_out_wimask_T_1053) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1053 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1053 = orr(_out_romask_T_1053) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1053 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1053 = andr(_out_womask_T_1053) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1053 = and(out_rivalid_1[931], out_rimask_1053) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1053 = and(out_roready_1[931], out_romask_1053) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1053 = and(out_wivalid_1[931], out_wimask_1053) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1053 = and(out_woready_1[931], out_womask_1053) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10119 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10120 = and(out_f_rivalid_1053, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10121 = and(UInt<1>(0h1), out_f_roready_1053) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10122 = eq(out_rimask_1053, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10123 = eq(out_wimask_1053, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10124 = eq(out_romask_1053, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10125 = eq(out_womask_1053, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10126 = or(_T_1266, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10127 = bits(_out_T_10126, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1054 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1054 = orr(_out_rimask_T_1054) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1054 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1054 = andr(_out_wimask_T_1054) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1054 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1054 = orr(_out_romask_T_1054) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1054 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1054 = andr(_out_womask_T_1054) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1054 = and(out_rivalid_1[932], out_rimask_1054) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1054 = and(out_roready_1[932], out_romask_1054) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1054 = and(out_wivalid_1[932], out_wimask_1054) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1054 = and(out_woready_1[932], out_womask_1054) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10128 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10129 = and(out_f_rivalid_1054, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10130 = and(UInt<1>(0h1), out_f_roready_1054) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10131 = eq(out_rimask_1054, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10132 = eq(out_wimask_1054, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10133 = eq(out_romask_1054, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10134 = eq(out_womask_1054, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_905 = or(_out_T_10127, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_905 = cat(_T_1267, _out_prepend_T_905) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10135 = or(out_prepend_905, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10136 = bits(_out_T_10135, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1055 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1055 = orr(_out_rimask_T_1055) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1055 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1055 = andr(_out_wimask_T_1055) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1055 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1055 = orr(_out_romask_T_1055) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1055 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1055 = andr(_out_womask_T_1055) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1055 = and(out_rivalid_1[933], out_rimask_1055) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1055 = and(out_roready_1[933], out_romask_1055) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1055 = and(out_wivalid_1[933], out_wimask_1055) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1055 = and(out_woready_1[933], out_womask_1055) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10137 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10138 = and(out_f_rivalid_1055, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10139 = and(UInt<1>(0h1), out_f_roready_1055) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10140 = eq(out_rimask_1055, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10141 = eq(out_wimask_1055, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10142 = eq(out_romask_1055, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10143 = eq(out_womask_1055, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_906 = or(_out_T_10136, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_906 = cat(_T_1268, _out_prepend_T_906) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10144 = or(out_prepend_906, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10145 = bits(_out_T_10144, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1056 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1056 = orr(_out_rimask_T_1056) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1056 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1056 = andr(_out_wimask_T_1056) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1056 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1056 = orr(_out_romask_T_1056) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1056 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1056 = andr(_out_womask_T_1056) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1056 = and(out_rivalid_1[934], out_rimask_1056) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1056 = and(out_roready_1[934], out_romask_1056) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1056 = and(out_wivalid_1[934], out_wimask_1056) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1056 = and(out_woready_1[934], out_womask_1056) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10146 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10147 = and(out_f_rivalid_1056, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10148 = and(UInt<1>(0h1), out_f_roready_1056) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10149 = eq(out_rimask_1056, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10150 = eq(out_wimask_1056, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10151 = eq(out_romask_1056, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10152 = eq(out_womask_1056, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_907 = or(_out_T_10145, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_907 = cat(_T_1269, _out_prepend_T_907) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10153 = or(out_prepend_907, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10154 = bits(_out_T_10153, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1057 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1057 = orr(_out_rimask_T_1057) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1057 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1057 = andr(_out_wimask_T_1057) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1057 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1057 = orr(_out_romask_T_1057) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1057 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1057 = andr(_out_womask_T_1057) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1057 = and(out_rivalid_1[935], out_rimask_1057) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1057 = and(out_roready_1[935], out_romask_1057) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1057 = and(out_wivalid_1[935], out_wimask_1057) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1057 = and(out_woready_1[935], out_womask_1057) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10155 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10156 = and(out_f_rivalid_1057, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10157 = and(UInt<1>(0h1), out_f_roready_1057) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10158 = eq(out_rimask_1057, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10159 = eq(out_wimask_1057, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10160 = eq(out_romask_1057, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10161 = eq(out_womask_1057, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_908 = or(_out_T_10154, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_908 = cat(_T_1270, _out_prepend_T_908) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10162 = or(out_prepend_908, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10163 = bits(_out_T_10162, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1058 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1058 = orr(_out_rimask_T_1058) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1058 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1058 = andr(_out_wimask_T_1058) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1058 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1058 = orr(_out_romask_T_1058) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1058 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1058 = andr(_out_womask_T_1058) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1058 = and(out_rivalid_1[936], out_rimask_1058) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1058 = and(out_roready_1[936], out_romask_1058) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1058 = and(out_wivalid_1[936], out_wimask_1058) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1058 = and(out_woready_1[936], out_womask_1058) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10164 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10165 = and(out_f_rivalid_1058, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10166 = and(UInt<1>(0h1), out_f_roready_1058) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10167 = eq(out_rimask_1058, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10168 = eq(out_wimask_1058, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10169 = eq(out_romask_1058, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10170 = eq(out_womask_1058, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_909 = or(_out_T_10163, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_909 = cat(_T_1271, _out_prepend_T_909) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10171 = or(out_prepend_909, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10172 = bits(_out_T_10171, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1059 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1059 = orr(_out_rimask_T_1059) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1059 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1059 = andr(_out_wimask_T_1059) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1059 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1059 = orr(_out_romask_T_1059) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1059 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1059 = andr(_out_womask_T_1059) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1059 = and(out_rivalid_1[937], out_rimask_1059) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1059 = and(out_roready_1[937], out_romask_1059) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1059 = and(out_wivalid_1[937], out_wimask_1059) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1059 = and(out_woready_1[937], out_womask_1059) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10173 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10174 = and(out_f_rivalid_1059, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10175 = and(UInt<1>(0h1), out_f_roready_1059) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10176 = eq(out_rimask_1059, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10177 = eq(out_wimask_1059, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10178 = eq(out_romask_1059, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10179 = eq(out_womask_1059, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_910 = or(_out_T_10172, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_910 = cat(_T_1272, _out_prepend_T_910) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10180 = or(out_prepend_910, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10181 = bits(_out_T_10180, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1060 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1060 = orr(_out_rimask_T_1060) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1060 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1060 = andr(_out_wimask_T_1060) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1060 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1060 = orr(_out_romask_T_1060) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1060 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1060 = andr(_out_womask_T_1060) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1060 = and(out_rivalid_1[938], out_rimask_1060) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1060 = and(out_roready_1[938], out_romask_1060) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1060 = and(out_wivalid_1[938], out_wimask_1060) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1060 = and(out_woready_1[938], out_womask_1060) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10182 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10183 = and(out_f_rivalid_1060, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10184 = and(UInt<1>(0h1), out_f_roready_1060) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10185 = eq(out_rimask_1060, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10186 = eq(out_wimask_1060, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10187 = eq(out_romask_1060, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10188 = eq(out_womask_1060, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_911 = or(_out_T_10181, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_911 = cat(_T_1273, _out_prepend_T_911) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10189 = or(out_prepend_911, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10190 = bits(_out_T_10189, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1061 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1061 = orr(_out_rimask_T_1061) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1061 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1061 = andr(_out_wimask_T_1061) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1061 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1061 = orr(_out_romask_T_1061) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1061 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1061 = andr(_out_womask_T_1061) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1061 = and(out_rivalid_1[939], out_rimask_1061) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1061 = and(out_roready_1[939], out_romask_1061) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1061 = and(out_wivalid_1[939], out_wimask_1061) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1061 = and(out_woready_1[939], out_womask_1061) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10191 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10192 = and(out_f_rivalid_1061, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10193 = and(UInt<1>(0h1), out_f_roready_1061) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10194 = eq(out_rimask_1061, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10195 = eq(out_wimask_1061, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10196 = eq(out_romask_1061, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10197 = eq(out_womask_1061, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10198 = or(UInt<8>(0h73), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10199 = bits(_out_T_10198, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1062 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1062 = orr(_out_rimask_T_1062) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1062 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1062 = andr(_out_wimask_T_1062) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1062 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1062 = orr(_out_romask_T_1062) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1062 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1062 = andr(_out_womask_T_1062) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1062 = and(out_rivalid_1[940], out_rimask_1062) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1062 = and(out_roready_1[940], out_romask_1062) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1062 = and(out_wivalid_1[940], out_wimask_1062) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1062 = and(out_woready_1[940], out_womask_1062) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10200 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10201 = and(out_f_rivalid_1062, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10202 = and(UInt<1>(0h1), out_f_roready_1062) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10203 = eq(out_rimask_1062, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10204 = eq(out_wimask_1062, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10205 = eq(out_romask_1062, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10206 = eq(out_womask_1062, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_912 = or(_out_T_10199, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_912 = cat(UInt<8>(0h10), _out_prepend_T_912) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10207 = or(out_prepend_912, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10208 = bits(_out_T_10207, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1063 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1063 = orr(_out_rimask_T_1063) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1063 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1063 = andr(_out_wimask_T_1063) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1063 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1063 = orr(_out_romask_T_1063) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1063 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1063 = andr(_out_womask_T_1063) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1063 = and(out_rivalid_1[941], out_rimask_1063) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1063 = and(out_roready_1[941], out_romask_1063) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1063 = and(out_wivalid_1[941], out_wimask_1063) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1063 = and(out_woready_1[941], out_womask_1063) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10209 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10210 = and(out_f_rivalid_1063, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10211 = and(UInt<1>(0h1), out_f_roready_1063) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10212 = eq(out_rimask_1063, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10213 = eq(out_wimask_1063, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10214 = eq(out_romask_1063, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10215 = eq(out_womask_1063, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_913 = or(_out_T_10208, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_913 = cat(UInt<8>(0h24), _out_prepend_T_913) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10216 = or(out_prepend_913, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10217 = bits(_out_T_10216, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1064 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1064 = orr(_out_rimask_T_1064) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1064 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1064 = andr(_out_wimask_T_1064) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1064 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1064 = orr(_out_romask_T_1064) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1064 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1064 = andr(_out_womask_T_1064) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1064 = and(out_rivalid_1[942], out_rimask_1064) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1064 = and(out_roready_1[942], out_romask_1064) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1064 = and(out_wivalid_1[942], out_wimask_1064) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1064 = and(out_woready_1[942], out_womask_1064) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10218 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10219 = and(out_f_rivalid_1064, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10220 = and(UInt<1>(0h1), out_f_roready_1064) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10221 = eq(out_rimask_1064, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10222 = eq(out_wimask_1064, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10223 = eq(out_romask_1064, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10224 = eq(out_womask_1064, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_914 = or(_out_T_10217, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_914 = cat(UInt<8>(0h7b), _out_prepend_T_914) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10225 = or(out_prepend_914, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10226 = bits(_out_T_10225, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1065 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1065 = orr(_out_rimask_T_1065) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1065 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1065 = andr(_out_wimask_T_1065) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1065 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1065 = orr(_out_romask_T_1065) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1065 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1065 = andr(_out_womask_T_1065) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1065 = and(out_rivalid_1[943], out_rimask_1065) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1065 = and(out_roready_1[943], out_romask_1065) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1065 = and(out_wivalid_1[943], out_wimask_1065) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1065 = and(out_woready_1[943], out_womask_1065) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10227 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10228 = and(out_f_rivalid_1065, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10229 = and(UInt<1>(0h1), out_f_roready_1065) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10230 = eq(out_rimask_1065, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10231 = eq(out_wimask_1065, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10232 = eq(out_romask_1065, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10233 = eq(out_womask_1065, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_915 = or(_out_T_10226, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_915 = cat(UInt<8>(0h73), _out_prepend_T_915) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10234 = or(out_prepend_915, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10235 = bits(_out_T_10234, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1066 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1066 = orr(_out_rimask_T_1066) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1066 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1066 = andr(_out_wimask_T_1066) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1066 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1066 = orr(_out_romask_T_1066) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1066 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1066 = andr(_out_womask_T_1066) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1066 = and(out_rivalid_1[944], out_rimask_1066) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1066 = and(out_roready_1[944], out_romask_1066) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1066 = and(out_wivalid_1[944], out_wimask_1066) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1066 = and(out_woready_1[944], out_womask_1066) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10236 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10237 = and(out_f_rivalid_1066, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10238 = and(UInt<1>(0h1), out_f_roready_1066) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10239 = eq(out_rimask_1066, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10240 = eq(out_wimask_1066, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10241 = eq(out_romask_1066, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10242 = eq(out_womask_1066, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_916 = or(_out_T_10235, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_916 = cat(UInt<8>(0h24), _out_prepend_T_916) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10243 = or(out_prepend_916, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10244 = bits(_out_T_10243, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1067 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1067 = orr(_out_rimask_T_1067) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1067 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1067 = andr(_out_wimask_T_1067) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1067 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1067 = orr(_out_romask_T_1067) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1067 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1067 = andr(_out_womask_T_1067) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1067 = and(out_rivalid_1[945], out_rimask_1067) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1067 = and(out_roready_1[945], out_romask_1067) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1067 = and(out_wivalid_1[945], out_wimask_1067) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1067 = and(out_woready_1[945], out_womask_1067) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10245 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10246 = and(out_f_rivalid_1067, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10247 = and(UInt<1>(0h1), out_f_roready_1067) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10248 = eq(out_rimask_1067, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10249 = eq(out_wimask_1067, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10250 = eq(out_romask_1067, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10251 = eq(out_womask_1067, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_917 = or(_out_T_10244, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_917 = cat(UInt<8>(0h40), _out_prepend_T_917) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10252 = or(out_prepend_917, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10253 = bits(_out_T_10252, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1068 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1068 = orr(_out_rimask_T_1068) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1068 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1068 = andr(_out_wimask_T_1068) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1068 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1068 = orr(_out_romask_T_1068) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1068 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1068 = andr(_out_womask_T_1068) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1068 = and(out_rivalid_1[946], out_rimask_1068) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1068 = and(out_roready_1[946], out_romask_1068) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1068 = and(out_wivalid_1[946], out_wimask_1068) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1068 = and(out_woready_1[946], out_womask_1068) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10254 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10255 = and(out_f_rivalid_1068, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10256 = and(UInt<1>(0h1), out_f_roready_1068) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10257 = eq(out_rimask_1068, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10258 = eq(out_wimask_1068, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10259 = eq(out_romask_1068, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10260 = eq(out_womask_1068, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_918 = or(_out_T_10253, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_918 = cat(UInt<8>(0hf1), _out_prepend_T_918) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10261 = or(out_prepend_918, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10262 = bits(_out_T_10261, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1069 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1069 = orr(_out_rimask_T_1069) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1069 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1069 = andr(_out_wimask_T_1069) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1069 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1069 = orr(_out_romask_T_1069) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1069 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1069 = andr(_out_womask_T_1069) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1069 = and(out_rivalid_1[947], out_rimask_1069) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1069 = and(out_roready_1[947], out_romask_1069) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1069 = and(out_wivalid_1[947], out_wimask_1069) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1069 = and(out_woready_1[947], out_womask_1069) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10263 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10264 = and(out_f_rivalid_1069, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10265 = and(UInt<1>(0h1), out_f_roready_1069) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10266 = eq(out_rimask_1069, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10267 = eq(out_wimask_1069, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10268 = eq(out_romask_1069, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10269 = eq(out_womask_1069, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10270 = or(_T_682, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10271 = bits(_out_T_10270, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1070 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1070 = orr(_out_rimask_T_1070) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1070 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1070 = andr(_out_wimask_T_1070) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1070 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1070 = orr(_out_romask_T_1070) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1070 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1070 = andr(_out_womask_T_1070) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1070 = and(out_rivalid_1[948], out_rimask_1070) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1070 = and(out_roready_1[948], out_romask_1070) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1070 = and(out_wivalid_1[948], out_wimask_1070) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1070 = and(out_woready_1[948], out_womask_1070) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10272 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10273 = and(out_f_rivalid_1070, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10274 = and(UInt<1>(0h1), out_f_roready_1070) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10275 = eq(out_rimask_1070, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10276 = eq(out_wimask_1070, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10277 = eq(out_romask_1070, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10278 = eq(out_womask_1070, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_919 = or(_out_T_10271, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_919 = cat(_T_683, _out_prepend_T_919) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10279 = or(out_prepend_919, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10280 = bits(_out_T_10279, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1071 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1071 = orr(_out_rimask_T_1071) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1071 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1071 = andr(_out_wimask_T_1071) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1071 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1071 = orr(_out_romask_T_1071) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1071 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1071 = andr(_out_womask_T_1071) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1071 = and(out_rivalid_1[949], out_rimask_1071) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1071 = and(out_roready_1[949], out_romask_1071) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1071 = and(out_wivalid_1[949], out_wimask_1071) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1071 = and(out_woready_1[949], out_womask_1071) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10281 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10282 = and(out_f_rivalid_1071, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10283 = and(UInt<1>(0h1), out_f_roready_1071) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10284 = eq(out_rimask_1071, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10285 = eq(out_wimask_1071, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10286 = eq(out_romask_1071, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10287 = eq(out_womask_1071, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_920 = or(_out_T_10280, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_920 = cat(_T_684, _out_prepend_T_920) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10288 = or(out_prepend_920, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10289 = bits(_out_T_10288, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1072 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1072 = orr(_out_rimask_T_1072) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1072 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1072 = andr(_out_wimask_T_1072) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1072 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1072 = orr(_out_romask_T_1072) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1072 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1072 = andr(_out_womask_T_1072) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1072 = and(out_rivalid_1[950], out_rimask_1072) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1072 = and(out_roready_1[950], out_romask_1072) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1072 = and(out_wivalid_1[950], out_wimask_1072) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1072 = and(out_woready_1[950], out_womask_1072) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10290 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10291 = and(out_f_rivalid_1072, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10292 = and(UInt<1>(0h1), out_f_roready_1072) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10293 = eq(out_rimask_1072, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10294 = eq(out_wimask_1072, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10295 = eq(out_romask_1072, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10296 = eq(out_womask_1072, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_921 = or(_out_T_10289, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_921 = cat(_T_685, _out_prepend_T_921) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10297 = or(out_prepend_921, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10298 = bits(_out_T_10297, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1073 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1073 = orr(_out_rimask_T_1073) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1073 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1073 = andr(_out_wimask_T_1073) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1073 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1073 = orr(_out_romask_T_1073) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1073 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1073 = andr(_out_womask_T_1073) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1073 = and(out_rivalid_1[951], out_rimask_1073) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1073 = and(out_roready_1[951], out_romask_1073) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1073 = and(out_wivalid_1[951], out_wimask_1073) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1073 = and(out_woready_1[951], out_womask_1073) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10299 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10300 = and(out_f_rivalid_1073, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10301 = and(UInt<1>(0h1), out_f_roready_1073) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10302 = eq(out_rimask_1073, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10303 = eq(out_wimask_1073, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10304 = eq(out_romask_1073, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10305 = eq(out_womask_1073, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_922 = or(_out_T_10298, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_922 = cat(_T_686, _out_prepend_T_922) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10306 = or(out_prepend_922, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10307 = bits(_out_T_10306, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1074 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1074 = orr(_out_rimask_T_1074) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1074 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1074 = andr(_out_wimask_T_1074) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1074 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1074 = orr(_out_romask_T_1074) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1074 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1074 = andr(_out_womask_T_1074) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1074 = and(out_rivalid_1[952], out_rimask_1074) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1074 = and(out_roready_1[952], out_romask_1074) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1074 = and(out_wivalid_1[952], out_wimask_1074) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1074 = and(out_woready_1[952], out_womask_1074) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10308 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10309 = and(out_f_rivalid_1074, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10310 = and(UInt<1>(0h1), out_f_roready_1074) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10311 = eq(out_rimask_1074, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10312 = eq(out_wimask_1074, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10313 = eq(out_romask_1074, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10314 = eq(out_womask_1074, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_923 = or(_out_T_10307, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_923 = cat(_T_687, _out_prepend_T_923) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10315 = or(out_prepend_923, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10316 = bits(_out_T_10315, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1075 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1075 = orr(_out_rimask_T_1075) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1075 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1075 = andr(_out_wimask_T_1075) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1075 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1075 = orr(_out_romask_T_1075) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1075 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1075 = andr(_out_womask_T_1075) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1075 = and(out_rivalid_1[953], out_rimask_1075) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1075 = and(out_roready_1[953], out_romask_1075) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1075 = and(out_wivalid_1[953], out_wimask_1075) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1075 = and(out_woready_1[953], out_womask_1075) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10317 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10318 = and(out_f_rivalid_1075, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10319 = and(UInt<1>(0h1), out_f_roready_1075) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10320 = eq(out_rimask_1075, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10321 = eq(out_wimask_1075, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10322 = eq(out_romask_1075, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10323 = eq(out_womask_1075, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_924 = or(_out_T_10316, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_924 = cat(_T_688, _out_prepend_T_924) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10324 = or(out_prepend_924, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10325 = bits(_out_T_10324, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1076 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1076 = orr(_out_rimask_T_1076) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1076 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1076 = andr(_out_wimask_T_1076) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1076 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1076 = orr(_out_romask_T_1076) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1076 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1076 = andr(_out_womask_T_1076) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1076 = and(out_rivalid_1[954], out_rimask_1076) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1076 = and(out_roready_1[954], out_romask_1076) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1076 = and(out_wivalid_1[954], out_wimask_1076) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1076 = and(out_woready_1[954], out_womask_1076) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10326 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10327 = and(out_f_rivalid_1076, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10328 = and(UInt<1>(0h1), out_f_roready_1076) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10329 = eq(out_rimask_1076, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10330 = eq(out_wimask_1076, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10331 = eq(out_romask_1076, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10332 = eq(out_womask_1076, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_925 = or(_out_T_10325, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_925 = cat(_T_689, _out_prepend_T_925) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10333 = or(out_prepend_925, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10334 = bits(_out_T_10333, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1077 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1077 = orr(_out_rimask_T_1077) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1077 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1077 = andr(_out_wimask_T_1077) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1077 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1077 = orr(_out_romask_T_1077) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1077 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1077 = andr(_out_womask_T_1077) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1077 = and(out_rivalid_1[955], out_rimask_1077) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1077 = and(out_roready_1[955], out_romask_1077) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1077 = and(out_wivalid_1[955], out_wimask_1077) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1077 = and(out_woready_1[955], out_womask_1077) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10335 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10336 = and(out_f_rivalid_1077, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10337 = and(UInt<1>(0h1), out_f_roready_1077) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10338 = eq(out_rimask_1077, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10339 = eq(out_wimask_1077, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10340 = eq(out_romask_1077, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10341 = eq(out_womask_1077, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10342 = or(_T_906, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10343 = bits(_out_T_10342, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1078 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1078 = orr(_out_rimask_T_1078) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1078 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1078 = andr(_out_wimask_T_1078) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1078 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1078 = orr(_out_romask_T_1078) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1078 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1078 = andr(_out_womask_T_1078) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1078 = and(out_rivalid_1[956], out_rimask_1078) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1078 = and(out_roready_1[956], out_romask_1078) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1078 = and(out_wivalid_1[956], out_wimask_1078) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1078 = and(out_woready_1[956], out_womask_1078) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10344 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10345 = and(out_f_rivalid_1078, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10346 = and(UInt<1>(0h1), out_f_roready_1078) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10347 = eq(out_rimask_1078, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10348 = eq(out_wimask_1078, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10349 = eq(out_romask_1078, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10350 = eq(out_womask_1078, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_926 = or(_out_T_10343, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_926 = cat(_T_907, _out_prepend_T_926) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10351 = or(out_prepend_926, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10352 = bits(_out_T_10351, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1079 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1079 = orr(_out_rimask_T_1079) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1079 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1079 = andr(_out_wimask_T_1079) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1079 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1079 = orr(_out_romask_T_1079) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1079 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1079 = andr(_out_womask_T_1079) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1079 = and(out_rivalid_1[957], out_rimask_1079) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1079 = and(out_roready_1[957], out_romask_1079) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1079 = and(out_wivalid_1[957], out_wimask_1079) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1079 = and(out_woready_1[957], out_womask_1079) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10353 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10354 = and(out_f_rivalid_1079, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10355 = and(UInt<1>(0h1), out_f_roready_1079) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10356 = eq(out_rimask_1079, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10357 = eq(out_wimask_1079, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10358 = eq(out_romask_1079, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10359 = eq(out_womask_1079, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_927 = or(_out_T_10352, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_927 = cat(_T_908, _out_prepend_T_927) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10360 = or(out_prepend_927, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10361 = bits(_out_T_10360, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1080 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1080 = orr(_out_rimask_T_1080) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1080 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1080 = andr(_out_wimask_T_1080) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1080 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1080 = orr(_out_romask_T_1080) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1080 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1080 = andr(_out_womask_T_1080) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1080 = and(out_rivalid_1[958], out_rimask_1080) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1080 = and(out_roready_1[958], out_romask_1080) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1080 = and(out_wivalid_1[958], out_wimask_1080) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1080 = and(out_woready_1[958], out_womask_1080) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10362 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10363 = and(out_f_rivalid_1080, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10364 = and(UInt<1>(0h1), out_f_roready_1080) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10365 = eq(out_rimask_1080, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10366 = eq(out_wimask_1080, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10367 = eq(out_romask_1080, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10368 = eq(out_womask_1080, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_928 = or(_out_T_10361, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_928 = cat(_T_909, _out_prepend_T_928) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10369 = or(out_prepend_928, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10370 = bits(_out_T_10369, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1081 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1081 = orr(_out_rimask_T_1081) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1081 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1081 = andr(_out_wimask_T_1081) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1081 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1081 = orr(_out_romask_T_1081) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1081 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1081 = andr(_out_womask_T_1081) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1081 = and(out_rivalid_1[959], out_rimask_1081) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1081 = and(out_roready_1[959], out_romask_1081) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1081 = and(out_wivalid_1[959], out_wimask_1081) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1081 = and(out_woready_1[959], out_womask_1081) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10371 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10372 = and(out_f_rivalid_1081, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10373 = and(UInt<1>(0h1), out_f_roready_1081) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10374 = eq(out_rimask_1081, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10375 = eq(out_wimask_1081, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10376 = eq(out_romask_1081, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10377 = eq(out_womask_1081, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_929 = or(_out_T_10370, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_929 = cat(_T_910, _out_prepend_T_929) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10378 = or(out_prepend_929, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10379 = bits(_out_T_10378, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1082 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1082 = orr(_out_rimask_T_1082) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1082 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1082 = andr(_out_wimask_T_1082) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1082 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1082 = orr(_out_romask_T_1082) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1082 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1082 = andr(_out_womask_T_1082) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1082 = and(out_rivalid_1[960], out_rimask_1082) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1082 = and(out_roready_1[960], out_romask_1082) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1082 = and(out_wivalid_1[960], out_wimask_1082) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1082 = and(out_woready_1[960], out_womask_1082) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10380 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10381 = and(out_f_rivalid_1082, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10382 = and(UInt<1>(0h1), out_f_roready_1082) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10383 = eq(out_rimask_1082, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10384 = eq(out_wimask_1082, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10385 = eq(out_romask_1082, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10386 = eq(out_womask_1082, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_930 = or(_out_T_10379, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_930 = cat(_T_911, _out_prepend_T_930) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10387 = or(out_prepend_930, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10388 = bits(_out_T_10387, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1083 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1083 = orr(_out_rimask_T_1083) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1083 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1083 = andr(_out_wimask_T_1083) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1083 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1083 = orr(_out_romask_T_1083) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1083 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1083 = andr(_out_womask_T_1083) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1083 = and(out_rivalid_1[961], out_rimask_1083) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1083 = and(out_roready_1[961], out_romask_1083) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1083 = and(out_wivalid_1[961], out_wimask_1083) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1083 = and(out_woready_1[961], out_womask_1083) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10389 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10390 = and(out_f_rivalid_1083, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10391 = and(UInt<1>(0h1), out_f_roready_1083) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10392 = eq(out_rimask_1083, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10393 = eq(out_wimask_1083, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10394 = eq(out_romask_1083, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10395 = eq(out_womask_1083, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_931 = or(_out_T_10388, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_931 = cat(_T_912, _out_prepend_T_931) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10396 = or(out_prepend_931, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10397 = bits(_out_T_10396, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1084 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1084 = orr(_out_rimask_T_1084) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1084 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1084 = andr(_out_wimask_T_1084) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1084 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1084 = orr(_out_romask_T_1084) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1084 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1084 = andr(_out_womask_T_1084) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1084 = and(out_rivalid_1[962], out_rimask_1084) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1084 = and(out_roready_1[962], out_romask_1084) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1084 = and(out_wivalid_1[962], out_wimask_1084) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1084 = and(out_woready_1[962], out_womask_1084) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10398 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10399 = and(out_f_rivalid_1084, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10400 = and(UInt<1>(0h1), out_f_roready_1084) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10401 = eq(out_rimask_1084, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10402 = eq(out_wimask_1084, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10403 = eq(out_romask_1084, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10404 = eq(out_womask_1084, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_932 = or(_out_T_10397, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_932 = cat(_T_913, _out_prepend_T_932) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10405 = or(out_prepend_932, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10406 = bits(_out_T_10405, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1085 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1085 = orr(_out_rimask_T_1085) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1085 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1085 = andr(_out_wimask_T_1085) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1085 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1085 = orr(_out_romask_T_1085) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1085 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1085 = andr(_out_womask_T_1085) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1085 = and(out_rivalid_1[963], out_rimask_1085) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1085 = and(out_roready_1[963], out_romask_1085) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1085 = and(out_wivalid_1[963], out_wimask_1085) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1085 = and(out_woready_1[963], out_womask_1085) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10407 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10408 = and(out_f_rivalid_1085, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10409 = and(UInt<1>(0h1), out_f_roready_1085) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10410 = eq(out_rimask_1085, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10411 = eq(out_wimask_1085, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10412 = eq(out_romask_1085, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10413 = eq(out_womask_1085, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10414 = or(_T_786, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10415 = bits(_out_T_10414, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1086 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1086 = orr(_out_rimask_T_1086) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1086 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1086 = andr(_out_wimask_T_1086) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1086 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1086 = orr(_out_romask_T_1086) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1086 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1086 = andr(_out_womask_T_1086) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1086 = and(out_rivalid_1[964], out_rimask_1086) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1086 = and(out_roready_1[964], out_romask_1086) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1086 = and(out_wivalid_1[964], out_wimask_1086) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1086 = and(out_woready_1[964], out_womask_1086) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10416 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10417 = and(out_f_rivalid_1086, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10418 = and(UInt<1>(0h1), out_f_roready_1086) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10419 = eq(out_rimask_1086, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10420 = eq(out_wimask_1086, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10421 = eq(out_romask_1086, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10422 = eq(out_womask_1086, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_933 = or(_out_T_10415, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_933 = cat(_T_787, _out_prepend_T_933) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10423 = or(out_prepend_933, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10424 = bits(_out_T_10423, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1087 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1087 = orr(_out_rimask_T_1087) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1087 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1087 = andr(_out_wimask_T_1087) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1087 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1087 = orr(_out_romask_T_1087) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1087 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1087 = andr(_out_womask_T_1087) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1087 = and(out_rivalid_1[965], out_rimask_1087) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1087 = and(out_roready_1[965], out_romask_1087) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1087 = and(out_wivalid_1[965], out_wimask_1087) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1087 = and(out_woready_1[965], out_womask_1087) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10425 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10426 = and(out_f_rivalid_1087, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10427 = and(UInt<1>(0h1), out_f_roready_1087) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10428 = eq(out_rimask_1087, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10429 = eq(out_wimask_1087, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10430 = eq(out_romask_1087, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10431 = eq(out_womask_1087, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_934 = or(_out_T_10424, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_934 = cat(_T_788, _out_prepend_T_934) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10432 = or(out_prepend_934, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10433 = bits(_out_T_10432, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1088 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1088 = orr(_out_rimask_T_1088) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1088 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1088 = andr(_out_wimask_T_1088) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1088 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1088 = orr(_out_romask_T_1088) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1088 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1088 = andr(_out_womask_T_1088) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1088 = and(out_rivalid_1[966], out_rimask_1088) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1088 = and(out_roready_1[966], out_romask_1088) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1088 = and(out_wivalid_1[966], out_wimask_1088) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1088 = and(out_woready_1[966], out_womask_1088) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10434 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10435 = and(out_f_rivalid_1088, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10436 = and(UInt<1>(0h1), out_f_roready_1088) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10437 = eq(out_rimask_1088, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10438 = eq(out_wimask_1088, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10439 = eq(out_romask_1088, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10440 = eq(out_womask_1088, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_935 = or(_out_T_10433, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_935 = cat(_T_789, _out_prepend_T_935) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10441 = or(out_prepend_935, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10442 = bits(_out_T_10441, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1089 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1089 = orr(_out_rimask_T_1089) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1089 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1089 = andr(_out_wimask_T_1089) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1089 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1089 = orr(_out_romask_T_1089) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1089 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1089 = andr(_out_womask_T_1089) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1089 = and(out_rivalid_1[967], out_rimask_1089) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1089 = and(out_roready_1[967], out_romask_1089) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1089 = and(out_wivalid_1[967], out_wimask_1089) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1089 = and(out_woready_1[967], out_womask_1089) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10443 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10444 = and(out_f_rivalid_1089, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10445 = and(UInt<1>(0h1), out_f_roready_1089) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10446 = eq(out_rimask_1089, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10447 = eq(out_wimask_1089, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10448 = eq(out_romask_1089, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10449 = eq(out_womask_1089, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_936 = or(_out_T_10442, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_936 = cat(_T_790, _out_prepend_T_936) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10450 = or(out_prepend_936, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10451 = bits(_out_T_10450, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1090 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1090 = orr(_out_rimask_T_1090) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1090 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1090 = andr(_out_wimask_T_1090) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1090 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1090 = orr(_out_romask_T_1090) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1090 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1090 = andr(_out_womask_T_1090) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1090 = and(out_rivalid_1[968], out_rimask_1090) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1090 = and(out_roready_1[968], out_romask_1090) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1090 = and(out_wivalid_1[968], out_wimask_1090) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1090 = and(out_woready_1[968], out_womask_1090) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10452 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10453 = and(out_f_rivalid_1090, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10454 = and(UInt<1>(0h1), out_f_roready_1090) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10455 = eq(out_rimask_1090, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10456 = eq(out_wimask_1090, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10457 = eq(out_romask_1090, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10458 = eq(out_womask_1090, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_937 = or(_out_T_10451, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_937 = cat(_T_791, _out_prepend_T_937) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10459 = or(out_prepend_937, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10460 = bits(_out_T_10459, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1091 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1091 = orr(_out_rimask_T_1091) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1091 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1091 = andr(_out_wimask_T_1091) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1091 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1091 = orr(_out_romask_T_1091) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1091 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1091 = andr(_out_womask_T_1091) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1091 = and(out_rivalid_1[969], out_rimask_1091) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1091 = and(out_roready_1[969], out_romask_1091) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1091 = and(out_wivalid_1[969], out_wimask_1091) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1091 = and(out_woready_1[969], out_womask_1091) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10461 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10462 = and(out_f_rivalid_1091, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10463 = and(UInt<1>(0h1), out_f_roready_1091) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10464 = eq(out_rimask_1091, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10465 = eq(out_wimask_1091, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10466 = eq(out_romask_1091, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10467 = eq(out_womask_1091, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_938 = or(_out_T_10460, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_938 = cat(_T_792, _out_prepend_T_938) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10468 = or(out_prepend_938, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10469 = bits(_out_T_10468, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1092 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1092 = orr(_out_rimask_T_1092) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1092 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1092 = andr(_out_wimask_T_1092) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1092 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1092 = orr(_out_romask_T_1092) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1092 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1092 = andr(_out_womask_T_1092) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1092 = and(out_rivalid_1[970], out_rimask_1092) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1092 = and(out_roready_1[970], out_romask_1092) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1092 = and(out_wivalid_1[970], out_wimask_1092) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1092 = and(out_woready_1[970], out_womask_1092) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10470 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10471 = and(out_f_rivalid_1092, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10472 = and(UInt<1>(0h1), out_f_roready_1092) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10473 = eq(out_rimask_1092, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10474 = eq(out_wimask_1092, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10475 = eq(out_romask_1092, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10476 = eq(out_womask_1092, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_939 = or(_out_T_10469, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_939 = cat(_T_793, _out_prepend_T_939) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10477 = or(out_prepend_939, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10478 = bits(_out_T_10477, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1093 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1093 = orr(_out_rimask_T_1093) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1093 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1093 = andr(_out_wimask_T_1093) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1093 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1093 = orr(_out_romask_T_1093) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1093 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1093 = andr(_out_womask_T_1093) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1093 = and(out_rivalid_1[971], out_rimask_1093) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1093 = and(out_roready_1[971], out_romask_1093) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1093 = and(out_wivalid_1[971], out_wimask_1093) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1093 = and(out_woready_1[971], out_womask_1093) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10479 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10480 = and(out_f_rivalid_1093, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10481 = and(UInt<1>(0h1), out_f_roready_1093) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10482 = eq(out_rimask_1093, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10483 = eq(out_wimask_1093, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10484 = eq(out_romask_1093, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10485 = eq(out_womask_1093, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10486 = or(_T_530, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10487 = bits(_out_T_10486, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1094 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1094 = orr(_out_rimask_T_1094) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1094 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1094 = andr(_out_wimask_T_1094) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1094 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1094 = orr(_out_romask_T_1094) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1094 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1094 = andr(_out_womask_T_1094) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1094 = and(out_rivalid_1[972], out_rimask_1094) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1094 = and(out_roready_1[972], out_romask_1094) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1094 = and(out_wivalid_1[972], out_wimask_1094) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1094 = and(out_woready_1[972], out_womask_1094) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10488 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10489 = and(out_f_rivalid_1094, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10490 = and(UInt<1>(0h1), out_f_roready_1094) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10491 = eq(out_rimask_1094, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10492 = eq(out_wimask_1094, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10493 = eq(out_romask_1094, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10494 = eq(out_womask_1094, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_940 = or(_out_T_10487, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_940 = cat(_T_531, _out_prepend_T_940) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10495 = or(out_prepend_940, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10496 = bits(_out_T_10495, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1095 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1095 = orr(_out_rimask_T_1095) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1095 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1095 = andr(_out_wimask_T_1095) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1095 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1095 = orr(_out_romask_T_1095) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1095 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1095 = andr(_out_womask_T_1095) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1095 = and(out_rivalid_1[973], out_rimask_1095) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1095 = and(out_roready_1[973], out_romask_1095) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1095 = and(out_wivalid_1[973], out_wimask_1095) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1095 = and(out_woready_1[973], out_womask_1095) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10497 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10498 = and(out_f_rivalid_1095, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10499 = and(UInt<1>(0h1), out_f_roready_1095) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10500 = eq(out_rimask_1095, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10501 = eq(out_wimask_1095, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10502 = eq(out_romask_1095, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10503 = eq(out_womask_1095, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_941 = or(_out_T_10496, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_941 = cat(_T_532, _out_prepend_T_941) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10504 = or(out_prepend_941, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10505 = bits(_out_T_10504, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1096 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1096 = orr(_out_rimask_T_1096) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1096 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1096 = andr(_out_wimask_T_1096) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1096 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1096 = orr(_out_romask_T_1096) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1096 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1096 = andr(_out_womask_T_1096) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1096 = and(out_rivalid_1[974], out_rimask_1096) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1096 = and(out_roready_1[974], out_romask_1096) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1096 = and(out_wivalid_1[974], out_wimask_1096) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1096 = and(out_woready_1[974], out_womask_1096) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10506 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10507 = and(out_f_rivalid_1096, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10508 = and(UInt<1>(0h1), out_f_roready_1096) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10509 = eq(out_rimask_1096, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10510 = eq(out_wimask_1096, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10511 = eq(out_romask_1096, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10512 = eq(out_womask_1096, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_942 = or(_out_T_10505, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_942 = cat(_T_533, _out_prepend_T_942) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10513 = or(out_prepend_942, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10514 = bits(_out_T_10513, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1097 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1097 = orr(_out_rimask_T_1097) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1097 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1097 = andr(_out_wimask_T_1097) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1097 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1097 = orr(_out_romask_T_1097) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1097 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1097 = andr(_out_womask_T_1097) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1097 = and(out_rivalid_1[975], out_rimask_1097) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1097 = and(out_roready_1[975], out_romask_1097) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1097 = and(out_wivalid_1[975], out_wimask_1097) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1097 = and(out_woready_1[975], out_womask_1097) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10515 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10516 = and(out_f_rivalid_1097, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10517 = and(UInt<1>(0h1), out_f_roready_1097) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10518 = eq(out_rimask_1097, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10519 = eq(out_wimask_1097, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10520 = eq(out_romask_1097, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10521 = eq(out_womask_1097, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_943 = or(_out_T_10514, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_943 = cat(_T_534, _out_prepend_T_943) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10522 = or(out_prepend_943, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10523 = bits(_out_T_10522, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1098 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1098 = orr(_out_rimask_T_1098) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1098 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1098 = andr(_out_wimask_T_1098) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1098 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1098 = orr(_out_romask_T_1098) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1098 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1098 = andr(_out_womask_T_1098) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1098 = and(out_rivalid_1[976], out_rimask_1098) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1098 = and(out_roready_1[976], out_romask_1098) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1098 = and(out_wivalid_1[976], out_wimask_1098) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1098 = and(out_woready_1[976], out_womask_1098) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10524 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10525 = and(out_f_rivalid_1098, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10526 = and(UInt<1>(0h1), out_f_roready_1098) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10527 = eq(out_rimask_1098, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10528 = eq(out_wimask_1098, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10529 = eq(out_romask_1098, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10530 = eq(out_womask_1098, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_944 = or(_out_T_10523, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_944 = cat(_T_535, _out_prepend_T_944) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10531 = or(out_prepend_944, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10532 = bits(_out_T_10531, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1099 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1099 = orr(_out_rimask_T_1099) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1099 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1099 = andr(_out_wimask_T_1099) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1099 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1099 = orr(_out_romask_T_1099) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1099 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1099 = andr(_out_womask_T_1099) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1099 = and(out_rivalid_1[977], out_rimask_1099) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1099 = and(out_roready_1[977], out_romask_1099) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1099 = and(out_wivalid_1[977], out_wimask_1099) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1099 = and(out_woready_1[977], out_womask_1099) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10533 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10534 = and(out_f_rivalid_1099, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10535 = and(UInt<1>(0h1), out_f_roready_1099) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10536 = eq(out_rimask_1099, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10537 = eq(out_wimask_1099, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10538 = eq(out_romask_1099, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10539 = eq(out_womask_1099, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_945 = or(_out_T_10532, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_945 = cat(_T_536, _out_prepend_T_945) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10540 = or(out_prepend_945, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10541 = bits(_out_T_10540, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1100 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1100 = orr(_out_rimask_T_1100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1100 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1100 = andr(_out_wimask_T_1100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1100 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1100 = orr(_out_romask_T_1100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1100 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1100 = andr(_out_womask_T_1100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1100 = and(out_rivalid_1[978], out_rimask_1100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1100 = and(out_roready_1[978], out_romask_1100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1100 = and(out_wivalid_1[978], out_wimask_1100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1100 = and(out_woready_1[978], out_womask_1100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10542 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10543 = and(out_f_rivalid_1100, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10544 = and(UInt<1>(0h1), out_f_roready_1100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10545 = eq(out_rimask_1100, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10546 = eq(out_wimask_1100, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10547 = eq(out_romask_1100, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10548 = eq(out_womask_1100, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_946 = or(_out_T_10541, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_946 = cat(_T_537, _out_prepend_T_946) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10549 = or(out_prepend_946, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10550 = bits(_out_T_10549, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1101 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1101 = orr(_out_rimask_T_1101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1101 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1101 = andr(_out_wimask_T_1101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1101 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1101 = orr(_out_romask_T_1101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1101 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1101 = andr(_out_womask_T_1101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1101 = and(out_rivalid_1[979], out_rimask_1101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1101 = and(out_roready_1[979], out_romask_1101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1101 = and(out_wivalid_1[979], out_wimask_1101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1101 = and(out_woready_1[979], out_womask_1101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10551 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10552 = and(out_f_rivalid_1101, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10553 = and(UInt<1>(0h1), out_f_roready_1101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10554 = eq(out_rimask_1101, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10555 = eq(out_wimask_1101, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10556 = eq(out_romask_1101, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10557 = eq(out_womask_1101, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10558 = or(_T_1074, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10559 = bits(_out_T_10558, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1102 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1102 = orr(_out_rimask_T_1102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1102 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1102 = andr(_out_wimask_T_1102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1102 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1102 = orr(_out_romask_T_1102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1102 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1102 = andr(_out_womask_T_1102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1102 = and(out_rivalid_1[980], out_rimask_1102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1102 = and(out_roready_1[980], out_romask_1102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1102 = and(out_wivalid_1[980], out_wimask_1102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1102 = and(out_woready_1[980], out_womask_1102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10560 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10561 = and(out_f_rivalid_1102, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10562 = and(UInt<1>(0h1), out_f_roready_1102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10563 = eq(out_rimask_1102, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10564 = eq(out_wimask_1102, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10565 = eq(out_romask_1102, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10566 = eq(out_womask_1102, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_947 = or(_out_T_10559, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_947 = cat(_T_1075, _out_prepend_T_947) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10567 = or(out_prepend_947, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10568 = bits(_out_T_10567, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1103 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1103 = orr(_out_rimask_T_1103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1103 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1103 = andr(_out_wimask_T_1103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1103 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1103 = orr(_out_romask_T_1103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1103 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1103 = andr(_out_womask_T_1103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1103 = and(out_rivalid_1[981], out_rimask_1103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1103 = and(out_roready_1[981], out_romask_1103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1103 = and(out_wivalid_1[981], out_wimask_1103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1103 = and(out_woready_1[981], out_womask_1103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10569 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10570 = and(out_f_rivalid_1103, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10571 = and(UInt<1>(0h1), out_f_roready_1103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10572 = eq(out_rimask_1103, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10573 = eq(out_wimask_1103, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10574 = eq(out_romask_1103, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10575 = eq(out_womask_1103, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_948 = or(_out_T_10568, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_948 = cat(_T_1076, _out_prepend_T_948) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10576 = or(out_prepend_948, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10577 = bits(_out_T_10576, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1104 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1104 = orr(_out_rimask_T_1104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1104 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1104 = andr(_out_wimask_T_1104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1104 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1104 = orr(_out_romask_T_1104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1104 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1104 = andr(_out_womask_T_1104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1104 = and(out_rivalid_1[982], out_rimask_1104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1104 = and(out_roready_1[982], out_romask_1104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1104 = and(out_wivalid_1[982], out_wimask_1104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1104 = and(out_woready_1[982], out_womask_1104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10578 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10579 = and(out_f_rivalid_1104, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10580 = and(UInt<1>(0h1), out_f_roready_1104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10581 = eq(out_rimask_1104, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10582 = eq(out_wimask_1104, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10583 = eq(out_romask_1104, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10584 = eq(out_womask_1104, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_949 = or(_out_T_10577, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_949 = cat(_T_1077, _out_prepend_T_949) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10585 = or(out_prepend_949, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10586 = bits(_out_T_10585, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1105 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1105 = orr(_out_rimask_T_1105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1105 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1105 = andr(_out_wimask_T_1105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1105 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1105 = orr(_out_romask_T_1105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1105 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1105 = andr(_out_womask_T_1105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1105 = and(out_rivalid_1[983], out_rimask_1105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1105 = and(out_roready_1[983], out_romask_1105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1105 = and(out_wivalid_1[983], out_wimask_1105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1105 = and(out_woready_1[983], out_womask_1105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10587 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10588 = and(out_f_rivalid_1105, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10589 = and(UInt<1>(0h1), out_f_roready_1105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10590 = eq(out_rimask_1105, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10591 = eq(out_wimask_1105, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10592 = eq(out_romask_1105, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10593 = eq(out_womask_1105, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_950 = or(_out_T_10586, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_950 = cat(_T_1078, _out_prepend_T_950) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10594 = or(out_prepend_950, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10595 = bits(_out_T_10594, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1106 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1106 = orr(_out_rimask_T_1106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1106 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1106 = andr(_out_wimask_T_1106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1106 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1106 = orr(_out_romask_T_1106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1106 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1106 = andr(_out_womask_T_1106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1106 = and(out_rivalid_1[984], out_rimask_1106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1106 = and(out_roready_1[984], out_romask_1106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1106 = and(out_wivalid_1[984], out_wimask_1106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1106 = and(out_woready_1[984], out_womask_1106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10596 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10597 = and(out_f_rivalid_1106, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10598 = and(UInt<1>(0h1), out_f_roready_1106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10599 = eq(out_rimask_1106, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10600 = eq(out_wimask_1106, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10601 = eq(out_romask_1106, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10602 = eq(out_womask_1106, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_951 = or(_out_T_10595, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_951 = cat(_T_1079, _out_prepend_T_951) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10603 = or(out_prepend_951, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10604 = bits(_out_T_10603, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1107 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1107 = orr(_out_rimask_T_1107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1107 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1107 = andr(_out_wimask_T_1107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1107 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1107 = orr(_out_romask_T_1107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1107 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1107 = andr(_out_womask_T_1107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1107 = and(out_rivalid_1[985], out_rimask_1107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1107 = and(out_roready_1[985], out_romask_1107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1107 = and(out_wivalid_1[985], out_wimask_1107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1107 = and(out_woready_1[985], out_womask_1107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10605 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10606 = and(out_f_rivalid_1107, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10607 = and(UInt<1>(0h1), out_f_roready_1107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10608 = eq(out_rimask_1107, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10609 = eq(out_wimask_1107, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10610 = eq(out_romask_1107, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10611 = eq(out_womask_1107, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_952 = or(_out_T_10604, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_952 = cat(_T_1080, _out_prepend_T_952) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10612 = or(out_prepend_952, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10613 = bits(_out_T_10612, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1108 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1108 = orr(_out_rimask_T_1108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1108 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1108 = andr(_out_wimask_T_1108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1108 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1108 = orr(_out_romask_T_1108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1108 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1108 = andr(_out_womask_T_1108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1108 = and(out_rivalid_1[986], out_rimask_1108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1108 = and(out_roready_1[986], out_romask_1108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1108 = and(out_wivalid_1[986], out_wimask_1108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1108 = and(out_woready_1[986], out_womask_1108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10614 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10615 = and(out_f_rivalid_1108, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10616 = and(UInt<1>(0h1), out_f_roready_1108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10617 = eq(out_rimask_1108, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10618 = eq(out_wimask_1108, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10619 = eq(out_romask_1108, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10620 = eq(out_womask_1108, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_953 = or(_out_T_10613, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_953 = cat(_T_1081, _out_prepend_T_953) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10621 = or(out_prepend_953, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10622 = bits(_out_T_10621, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1109 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1109 = orr(_out_rimask_T_1109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1109 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1109 = andr(_out_wimask_T_1109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1109 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1109 = orr(_out_romask_T_1109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1109 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1109 = andr(_out_womask_T_1109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1109 = and(out_rivalid_1[987], out_rimask_1109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1109 = and(out_roready_1[987], out_romask_1109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1109 = and(out_wivalid_1[987], out_wimask_1109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1109 = and(out_woready_1[987], out_womask_1109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10623 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10624 = and(out_f_rivalid_1109, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10625 = and(UInt<1>(0h1), out_f_roready_1109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10626 = eq(out_rimask_1109, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10627 = eq(out_wimask_1109, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10628 = eq(out_romask_1109, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10629 = eq(out_womask_1109, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10630 = or(_T_1130, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10631 = bits(_out_T_10630, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1110 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1110 = orr(_out_rimask_T_1110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1110 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1110 = andr(_out_wimask_T_1110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1110 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1110 = orr(_out_romask_T_1110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1110 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1110 = andr(_out_womask_T_1110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1110 = and(out_rivalid_1[988], out_rimask_1110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1110 = and(out_roready_1[988], out_romask_1110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1110 = and(out_wivalid_1[988], out_wimask_1110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1110 = and(out_woready_1[988], out_womask_1110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10632 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10633 = and(out_f_rivalid_1110, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10634 = and(UInt<1>(0h1), out_f_roready_1110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10635 = eq(out_rimask_1110, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10636 = eq(out_wimask_1110, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10637 = eq(out_romask_1110, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10638 = eq(out_womask_1110, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_954 = or(_out_T_10631, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_954 = cat(_T_1131, _out_prepend_T_954) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10639 = or(out_prepend_954, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10640 = bits(_out_T_10639, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1111 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1111 = orr(_out_rimask_T_1111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1111 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1111 = andr(_out_wimask_T_1111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1111 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1111 = orr(_out_romask_T_1111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1111 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1111 = andr(_out_womask_T_1111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1111 = and(out_rivalid_1[989], out_rimask_1111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1111 = and(out_roready_1[989], out_romask_1111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1111 = and(out_wivalid_1[989], out_wimask_1111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1111 = and(out_woready_1[989], out_womask_1111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10641 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10642 = and(out_f_rivalid_1111, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10643 = and(UInt<1>(0h1), out_f_roready_1111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10644 = eq(out_rimask_1111, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10645 = eq(out_wimask_1111, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10646 = eq(out_romask_1111, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10647 = eq(out_womask_1111, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_955 = or(_out_T_10640, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_955 = cat(_T_1132, _out_prepend_T_955) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10648 = or(out_prepend_955, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10649 = bits(_out_T_10648, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1112 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1112 = orr(_out_rimask_T_1112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1112 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1112 = andr(_out_wimask_T_1112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1112 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1112 = orr(_out_romask_T_1112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1112 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1112 = andr(_out_womask_T_1112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1112 = and(out_rivalid_1[990], out_rimask_1112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1112 = and(out_roready_1[990], out_romask_1112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1112 = and(out_wivalid_1[990], out_wimask_1112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1112 = and(out_woready_1[990], out_womask_1112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10650 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10651 = and(out_f_rivalid_1112, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10652 = and(UInt<1>(0h1), out_f_roready_1112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10653 = eq(out_rimask_1112, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10654 = eq(out_wimask_1112, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10655 = eq(out_romask_1112, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10656 = eq(out_womask_1112, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_956 = or(_out_T_10649, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_956 = cat(_T_1133, _out_prepend_T_956) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10657 = or(out_prepend_956, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10658 = bits(_out_T_10657, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1113 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1113 = orr(_out_rimask_T_1113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1113 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1113 = andr(_out_wimask_T_1113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1113 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1113 = orr(_out_romask_T_1113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1113 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1113 = andr(_out_womask_T_1113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1113 = and(out_rivalid_1[991], out_rimask_1113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1113 = and(out_roready_1[991], out_romask_1113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1113 = and(out_wivalid_1[991], out_wimask_1113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1113 = and(out_woready_1[991], out_womask_1113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10659 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10660 = and(out_f_rivalid_1113, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10661 = and(UInt<1>(0h1), out_f_roready_1113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10662 = eq(out_rimask_1113, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10663 = eq(out_wimask_1113, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10664 = eq(out_romask_1113, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10665 = eq(out_womask_1113, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_957 = or(_out_T_10658, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_957 = cat(_T_1134, _out_prepend_T_957) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10666 = or(out_prepend_957, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10667 = bits(_out_T_10666, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1114 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1114 = orr(_out_rimask_T_1114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1114 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1114 = andr(_out_wimask_T_1114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1114 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1114 = orr(_out_romask_T_1114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1114 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1114 = andr(_out_womask_T_1114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1114 = and(out_rivalid_1[992], out_rimask_1114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1114 = and(out_roready_1[992], out_romask_1114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1114 = and(out_wivalid_1[992], out_wimask_1114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1114 = and(out_woready_1[992], out_womask_1114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10668 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10669 = and(out_f_rivalid_1114, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10670 = and(UInt<1>(0h1), out_f_roready_1114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10671 = eq(out_rimask_1114, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10672 = eq(out_wimask_1114, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10673 = eq(out_romask_1114, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10674 = eq(out_womask_1114, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_958 = or(_out_T_10667, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_958 = cat(_T_1135, _out_prepend_T_958) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10675 = or(out_prepend_958, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10676 = bits(_out_T_10675, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1115 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1115 = orr(_out_rimask_T_1115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1115 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1115 = andr(_out_wimask_T_1115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1115 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1115 = orr(_out_romask_T_1115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1115 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1115 = andr(_out_womask_T_1115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1115 = and(out_rivalid_1[993], out_rimask_1115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1115 = and(out_roready_1[993], out_romask_1115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1115 = and(out_wivalid_1[993], out_wimask_1115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1115 = and(out_woready_1[993], out_womask_1115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10677 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10678 = and(out_f_rivalid_1115, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10679 = and(UInt<1>(0h1), out_f_roready_1115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10680 = eq(out_rimask_1115, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10681 = eq(out_wimask_1115, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10682 = eq(out_romask_1115, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10683 = eq(out_womask_1115, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_959 = or(_out_T_10676, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_959 = cat(_T_1136, _out_prepend_T_959) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10684 = or(out_prepend_959, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10685 = bits(_out_T_10684, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1116 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1116 = orr(_out_rimask_T_1116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1116 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1116 = andr(_out_wimask_T_1116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1116 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1116 = orr(_out_romask_T_1116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1116 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1116 = andr(_out_womask_T_1116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1116 = and(out_rivalid_1[994], out_rimask_1116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1116 = and(out_roready_1[994], out_romask_1116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1116 = and(out_wivalid_1[994], out_wimask_1116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1116 = and(out_woready_1[994], out_womask_1116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10686 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10687 = and(out_f_rivalid_1116, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10688 = and(UInt<1>(0h1), out_f_roready_1116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10689 = eq(out_rimask_1116, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10690 = eq(out_wimask_1116, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10691 = eq(out_romask_1116, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10692 = eq(out_womask_1116, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_960 = or(_out_T_10685, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_960 = cat(_T_1137, _out_prepend_T_960) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10693 = or(out_prepend_960, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10694 = bits(_out_T_10693, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1117 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1117 = orr(_out_rimask_T_1117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1117 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1117 = andr(_out_wimask_T_1117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1117 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1117 = orr(_out_romask_T_1117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1117 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1117 = andr(_out_womask_T_1117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1117 = and(out_rivalid_1[995], out_rimask_1117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1117 = and(out_roready_1[995], out_romask_1117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1117 = and(out_wivalid_1[995], out_wimask_1117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1117 = and(out_woready_1[995], out_womask_1117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10695 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10696 = and(out_f_rivalid_1117, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10697 = and(UInt<1>(0h1), out_f_roready_1117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10698 = eq(out_rimask_1117, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10699 = eq(out_wimask_1117, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10700 = eq(out_romask_1117, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10701 = eq(out_womask_1117, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10702 = or(_T_1298, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10703 = bits(_out_T_10702, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1118 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1118 = orr(_out_rimask_T_1118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1118 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1118 = andr(_out_wimask_T_1118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1118 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1118 = orr(_out_romask_T_1118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1118 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1118 = andr(_out_womask_T_1118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1118 = and(out_rivalid_1[996], out_rimask_1118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1118 = and(out_roready_1[996], out_romask_1118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1118 = and(out_wivalid_1[996], out_wimask_1118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1118 = and(out_woready_1[996], out_womask_1118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10704 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10705 = and(out_f_rivalid_1118, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10706 = and(UInt<1>(0h1), out_f_roready_1118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10707 = eq(out_rimask_1118, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10708 = eq(out_wimask_1118, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10709 = eq(out_romask_1118, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10710 = eq(out_womask_1118, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_961 = or(_out_T_10703, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_961 = cat(_T_1299, _out_prepend_T_961) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10711 = or(out_prepend_961, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10712 = bits(_out_T_10711, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1119 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1119 = orr(_out_rimask_T_1119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1119 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1119 = andr(_out_wimask_T_1119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1119 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1119 = orr(_out_romask_T_1119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1119 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1119 = andr(_out_womask_T_1119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1119 = and(out_rivalid_1[997], out_rimask_1119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1119 = and(out_roready_1[997], out_romask_1119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1119 = and(out_wivalid_1[997], out_wimask_1119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1119 = and(out_woready_1[997], out_womask_1119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10713 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10714 = and(out_f_rivalid_1119, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10715 = and(UInt<1>(0h1), out_f_roready_1119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10716 = eq(out_rimask_1119, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10717 = eq(out_wimask_1119, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10718 = eq(out_romask_1119, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10719 = eq(out_womask_1119, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_962 = or(_out_T_10712, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_962 = cat(_T_1300, _out_prepend_T_962) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10720 = or(out_prepend_962, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10721 = bits(_out_T_10720, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1120 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1120 = orr(_out_rimask_T_1120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1120 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1120 = andr(_out_wimask_T_1120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1120 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1120 = orr(_out_romask_T_1120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1120 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1120 = andr(_out_womask_T_1120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1120 = and(out_rivalid_1[998], out_rimask_1120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1120 = and(out_roready_1[998], out_romask_1120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1120 = and(out_wivalid_1[998], out_wimask_1120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1120 = and(out_woready_1[998], out_womask_1120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10722 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10723 = and(out_f_rivalid_1120, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10724 = and(UInt<1>(0h1), out_f_roready_1120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10725 = eq(out_rimask_1120, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10726 = eq(out_wimask_1120, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10727 = eq(out_romask_1120, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10728 = eq(out_womask_1120, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_963 = or(_out_T_10721, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_963 = cat(_T_1301, _out_prepend_T_963) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10729 = or(out_prepend_963, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10730 = bits(_out_T_10729, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1121 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1121 = orr(_out_rimask_T_1121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1121 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1121 = andr(_out_wimask_T_1121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1121 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1121 = orr(_out_romask_T_1121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1121 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1121 = andr(_out_womask_T_1121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1121 = and(out_rivalid_1[999], out_rimask_1121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1121 = and(out_roready_1[999], out_romask_1121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1121 = and(out_wivalid_1[999], out_wimask_1121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1121 = and(out_woready_1[999], out_womask_1121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10731 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10732 = and(out_f_rivalid_1121, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10733 = and(UInt<1>(0h1), out_f_roready_1121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10734 = eq(out_rimask_1121, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10735 = eq(out_wimask_1121, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10736 = eq(out_romask_1121, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10737 = eq(out_womask_1121, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_964 = or(_out_T_10730, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_964 = cat(_T_1302, _out_prepend_T_964) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10738 = or(out_prepend_964, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10739 = bits(_out_T_10738, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1122 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1122 = orr(_out_rimask_T_1122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1122 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1122 = andr(_out_wimask_T_1122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1122 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1122 = orr(_out_romask_T_1122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1122 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1122 = andr(_out_womask_T_1122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1122 = and(out_rivalid_1[1000], out_rimask_1122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1122 = and(out_roready_1[1000], out_romask_1122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1122 = and(out_wivalid_1[1000], out_wimask_1122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1122 = and(out_woready_1[1000], out_womask_1122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10740 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10741 = and(out_f_rivalid_1122, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10742 = and(UInt<1>(0h1), out_f_roready_1122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10743 = eq(out_rimask_1122, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10744 = eq(out_wimask_1122, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10745 = eq(out_romask_1122, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10746 = eq(out_womask_1122, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_965 = or(_out_T_10739, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_965 = cat(_T_1303, _out_prepend_T_965) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10747 = or(out_prepend_965, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10748 = bits(_out_T_10747, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1123 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1123 = orr(_out_rimask_T_1123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1123 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1123 = andr(_out_wimask_T_1123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1123 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1123 = orr(_out_romask_T_1123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1123 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1123 = andr(_out_womask_T_1123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1123 = and(out_rivalid_1[1001], out_rimask_1123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1123 = and(out_roready_1[1001], out_romask_1123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1123 = and(out_wivalid_1[1001], out_wimask_1123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1123 = and(out_woready_1[1001], out_womask_1123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10749 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10750 = and(out_f_rivalid_1123, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10751 = and(UInt<1>(0h1), out_f_roready_1123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10752 = eq(out_rimask_1123, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10753 = eq(out_wimask_1123, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10754 = eq(out_romask_1123, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10755 = eq(out_womask_1123, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_966 = or(_out_T_10748, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_966 = cat(_T_1304, _out_prepend_T_966) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10756 = or(out_prepend_966, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10757 = bits(_out_T_10756, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1124 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1124 = orr(_out_rimask_T_1124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1124 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1124 = andr(_out_wimask_T_1124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1124 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1124 = orr(_out_romask_T_1124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1124 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1124 = andr(_out_womask_T_1124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1124 = and(out_rivalid_1[1002], out_rimask_1124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1124 = and(out_roready_1[1002], out_romask_1124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1124 = and(out_wivalid_1[1002], out_wimask_1124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1124 = and(out_woready_1[1002], out_womask_1124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10758 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10759 = and(out_f_rivalid_1124, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10760 = and(UInt<1>(0h1), out_f_roready_1124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10761 = eq(out_rimask_1124, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10762 = eq(out_wimask_1124, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10763 = eq(out_romask_1124, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10764 = eq(out_womask_1124, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_967 = or(_out_T_10757, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_967 = cat(_T_1305, _out_prepend_T_967) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10765 = or(out_prepend_967, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10766 = bits(_out_T_10765, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1125 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1125 = orr(_out_rimask_T_1125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1125 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1125 = andr(_out_wimask_T_1125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1125 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1125 = orr(_out_romask_T_1125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1125 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1125 = andr(_out_womask_T_1125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1125 = and(out_rivalid_1[1003], out_rimask_1125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1125 = and(out_roready_1[1003], out_romask_1125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1125 = and(out_wivalid_1[1003], out_wimask_1125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1125 = and(out_woready_1[1003], out_womask_1125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10767 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10768 = and(out_f_rivalid_1125, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10769 = and(UInt<1>(0h1), out_f_roready_1125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10770 = eq(out_rimask_1125, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10771 = eq(out_wimask_1125, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10772 = eq(out_romask_1125, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10773 = eq(out_womask_1125, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10774 = or(_T_1386, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10775 = bits(_out_T_10774, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1126 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1126 = orr(_out_rimask_T_1126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1126 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1126 = andr(_out_wimask_T_1126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1126 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1126 = orr(_out_romask_T_1126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1126 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1126 = andr(_out_womask_T_1126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1126 = and(out_rivalid_1[1004], out_rimask_1126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1126 = and(out_roready_1[1004], out_romask_1126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1126 = and(out_wivalid_1[1004], out_wimask_1126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1126 = and(out_woready_1[1004], out_womask_1126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10776 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10777 = and(out_f_rivalid_1126, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10778 = and(UInt<1>(0h1), out_f_roready_1126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10779 = eq(out_rimask_1126, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10780 = eq(out_wimask_1126, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10781 = eq(out_romask_1126, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10782 = eq(out_womask_1126, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_968 = or(_out_T_10775, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_968 = cat(_T_1387, _out_prepend_T_968) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10783 = or(out_prepend_968, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10784 = bits(_out_T_10783, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1127 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1127 = orr(_out_rimask_T_1127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1127 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1127 = andr(_out_wimask_T_1127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1127 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1127 = orr(_out_romask_T_1127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1127 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1127 = andr(_out_womask_T_1127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1127 = and(out_rivalid_1[1005], out_rimask_1127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1127 = and(out_roready_1[1005], out_romask_1127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1127 = and(out_wivalid_1[1005], out_wimask_1127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1127 = and(out_woready_1[1005], out_womask_1127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10785 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10786 = and(out_f_rivalid_1127, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10787 = and(UInt<1>(0h1), out_f_roready_1127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10788 = eq(out_rimask_1127, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10789 = eq(out_wimask_1127, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10790 = eq(out_romask_1127, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10791 = eq(out_womask_1127, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_969 = or(_out_T_10784, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_969 = cat(_T_1388, _out_prepend_T_969) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10792 = or(out_prepend_969, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10793 = bits(_out_T_10792, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1128 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1128 = orr(_out_rimask_T_1128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1128 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1128 = andr(_out_wimask_T_1128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1128 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1128 = orr(_out_romask_T_1128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1128 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1128 = andr(_out_womask_T_1128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1128 = and(out_rivalid_1[1006], out_rimask_1128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1128 = and(out_roready_1[1006], out_romask_1128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1128 = and(out_wivalid_1[1006], out_wimask_1128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1128 = and(out_woready_1[1006], out_womask_1128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10794 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10795 = and(out_f_rivalid_1128, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10796 = and(UInt<1>(0h1), out_f_roready_1128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10797 = eq(out_rimask_1128, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10798 = eq(out_wimask_1128, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10799 = eq(out_romask_1128, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10800 = eq(out_womask_1128, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_970 = or(_out_T_10793, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_970 = cat(_T_1389, _out_prepend_T_970) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10801 = or(out_prepend_970, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10802 = bits(_out_T_10801, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1129 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1129 = orr(_out_rimask_T_1129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1129 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1129 = andr(_out_wimask_T_1129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1129 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1129 = orr(_out_romask_T_1129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1129 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1129 = andr(_out_womask_T_1129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1129 = and(out_rivalid_1[1007], out_rimask_1129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1129 = and(out_roready_1[1007], out_romask_1129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1129 = and(out_wivalid_1[1007], out_wimask_1129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1129 = and(out_woready_1[1007], out_womask_1129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10803 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10804 = and(out_f_rivalid_1129, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10805 = and(UInt<1>(0h1), out_f_roready_1129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10806 = eq(out_rimask_1129, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10807 = eq(out_wimask_1129, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10808 = eq(out_romask_1129, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10809 = eq(out_womask_1129, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_971 = or(_out_T_10802, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_971 = cat(_T_1390, _out_prepend_T_971) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10810 = or(out_prepend_971, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10811 = bits(_out_T_10810, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1130 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1130 = orr(_out_rimask_T_1130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1130 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1130 = andr(_out_wimask_T_1130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1130 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1130 = orr(_out_romask_T_1130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1130 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1130 = andr(_out_womask_T_1130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1130 = and(out_rivalid_1[1008], out_rimask_1130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1130 = and(out_roready_1[1008], out_romask_1130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1130 = and(out_wivalid_1[1008], out_wimask_1130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1130 = and(out_woready_1[1008], out_womask_1130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10812 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10813 = and(out_f_rivalid_1130, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10814 = and(UInt<1>(0h1), out_f_roready_1130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10815 = eq(out_rimask_1130, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10816 = eq(out_wimask_1130, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10817 = eq(out_romask_1130, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10818 = eq(out_womask_1130, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_972 = or(_out_T_10811, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_972 = cat(_T_1391, _out_prepend_T_972) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10819 = or(out_prepend_972, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10820 = bits(_out_T_10819, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1131 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1131 = orr(_out_rimask_T_1131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1131 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1131 = andr(_out_wimask_T_1131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1131 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1131 = orr(_out_romask_T_1131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1131 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1131 = andr(_out_womask_T_1131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1131 = and(out_rivalid_1[1009], out_rimask_1131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1131 = and(out_roready_1[1009], out_romask_1131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1131 = and(out_wivalid_1[1009], out_wimask_1131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1131 = and(out_woready_1[1009], out_womask_1131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10821 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10822 = and(out_f_rivalid_1131, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10823 = and(UInt<1>(0h1), out_f_roready_1131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10824 = eq(out_rimask_1131, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10825 = eq(out_wimask_1131, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10826 = eq(out_romask_1131, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10827 = eq(out_womask_1131, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_973 = or(_out_T_10820, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_973 = cat(_T_1392, _out_prepend_T_973) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10828 = or(out_prepend_973, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10829 = bits(_out_T_10828, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1132 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1132 = orr(_out_rimask_T_1132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1132 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1132 = andr(_out_wimask_T_1132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1132 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1132 = orr(_out_romask_T_1132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1132 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1132 = andr(_out_womask_T_1132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1132 = and(out_rivalid_1[1010], out_rimask_1132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1132 = and(out_roready_1[1010], out_romask_1132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1132 = and(out_wivalid_1[1010], out_wimask_1132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1132 = and(out_woready_1[1010], out_womask_1132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10830 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10831 = and(out_f_rivalid_1132, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10832 = and(UInt<1>(0h1), out_f_roready_1132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10833 = eq(out_rimask_1132, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10834 = eq(out_wimask_1132, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10835 = eq(out_romask_1132, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10836 = eq(out_womask_1132, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_974 = or(_out_T_10829, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_974 = cat(_T_1393, _out_prepend_T_974) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10837 = or(out_prepend_974, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10838 = bits(_out_T_10837, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1133 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1133 = orr(_out_rimask_T_1133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1133 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1133 = andr(_out_wimask_T_1133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1133 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1133 = orr(_out_romask_T_1133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1133 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1133 = andr(_out_womask_T_1133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1133 = and(out_rivalid_1[1011], out_rimask_1133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1133 = and(out_roready_1[1011], out_romask_1133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1133 = and(out_wivalid_1[1011], out_wimask_1133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1133 = and(out_woready_1[1011], out_womask_1133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10839 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10840 = and(out_f_rivalid_1133, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10841 = and(UInt<1>(0h1), out_f_roready_1133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10842 = eq(out_rimask_1133, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10843 = eq(out_wimask_1133, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10844 = eq(out_romask_1133, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10845 = eq(out_womask_1133, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10846 = or(_T_626, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10847 = bits(_out_T_10846, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1134 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1134 = orr(_out_rimask_T_1134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1134 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1134 = andr(_out_wimask_T_1134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1134 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1134 = orr(_out_romask_T_1134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1134 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1134 = andr(_out_womask_T_1134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1134 = and(out_rivalid_1[1012], out_rimask_1134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1134 = and(out_roready_1[1012], out_romask_1134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1134 = and(out_wivalid_1[1012], out_wimask_1134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1134 = and(out_woready_1[1012], out_womask_1134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10848 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10849 = and(out_f_rivalid_1134, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10850 = and(UInt<1>(0h1), out_f_roready_1134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10851 = eq(out_rimask_1134, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10852 = eq(out_wimask_1134, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10853 = eq(out_romask_1134, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10854 = eq(out_womask_1134, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_975 = or(_out_T_10847, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_975 = cat(_T_627, _out_prepend_T_975) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10855 = or(out_prepend_975, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10856 = bits(_out_T_10855, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1135 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1135 = orr(_out_rimask_T_1135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1135 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1135 = andr(_out_wimask_T_1135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1135 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1135 = orr(_out_romask_T_1135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1135 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1135 = andr(_out_womask_T_1135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1135 = and(out_rivalid_1[1013], out_rimask_1135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1135 = and(out_roready_1[1013], out_romask_1135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1135 = and(out_wivalid_1[1013], out_wimask_1135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1135 = and(out_woready_1[1013], out_womask_1135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10857 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10858 = and(out_f_rivalid_1135, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10859 = and(UInt<1>(0h1), out_f_roready_1135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10860 = eq(out_rimask_1135, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10861 = eq(out_wimask_1135, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10862 = eq(out_romask_1135, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10863 = eq(out_womask_1135, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_976 = or(_out_T_10856, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_976 = cat(_T_628, _out_prepend_T_976) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10864 = or(out_prepend_976, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10865 = bits(_out_T_10864, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1136 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1136 = orr(_out_rimask_T_1136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1136 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1136 = andr(_out_wimask_T_1136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1136 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1136 = orr(_out_romask_T_1136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1136 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1136 = andr(_out_womask_T_1136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1136 = and(out_rivalid_1[1014], out_rimask_1136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1136 = and(out_roready_1[1014], out_romask_1136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1136 = and(out_wivalid_1[1014], out_wimask_1136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1136 = and(out_woready_1[1014], out_womask_1136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10866 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10867 = and(out_f_rivalid_1136, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10868 = and(UInt<1>(0h1), out_f_roready_1136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10869 = eq(out_rimask_1136, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10870 = eq(out_wimask_1136, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10871 = eq(out_romask_1136, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10872 = eq(out_womask_1136, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_977 = or(_out_T_10865, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_977 = cat(_T_629, _out_prepend_T_977) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10873 = or(out_prepend_977, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10874 = bits(_out_T_10873, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1137 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1137 = orr(_out_rimask_T_1137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1137 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1137 = andr(_out_wimask_T_1137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1137 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1137 = orr(_out_romask_T_1137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1137 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1137 = andr(_out_womask_T_1137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1137 = and(out_rivalid_1[1015], out_rimask_1137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1137 = and(out_roready_1[1015], out_romask_1137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1137 = and(out_wivalid_1[1015], out_wimask_1137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1137 = and(out_woready_1[1015], out_womask_1137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10875 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10876 = and(out_f_rivalid_1137, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10877 = and(UInt<1>(0h1), out_f_roready_1137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10878 = eq(out_rimask_1137, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10879 = eq(out_wimask_1137, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10880 = eq(out_romask_1137, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10881 = eq(out_womask_1137, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_978 = or(_out_T_10874, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_978 = cat(_T_630, _out_prepend_T_978) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10882 = or(out_prepend_978, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10883 = bits(_out_T_10882, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1138 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1138 = orr(_out_rimask_T_1138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1138 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1138 = andr(_out_wimask_T_1138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1138 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1138 = orr(_out_romask_T_1138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1138 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1138 = andr(_out_womask_T_1138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1138 = and(out_rivalid_1[1016], out_rimask_1138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1138 = and(out_roready_1[1016], out_romask_1138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1138 = and(out_wivalid_1[1016], out_wimask_1138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1138 = and(out_woready_1[1016], out_womask_1138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10884 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10885 = and(out_f_rivalid_1138, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10886 = and(UInt<1>(0h1), out_f_roready_1138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10887 = eq(out_rimask_1138, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10888 = eq(out_wimask_1138, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10889 = eq(out_romask_1138, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10890 = eq(out_womask_1138, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_979 = or(_out_T_10883, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_979 = cat(_T_631, _out_prepend_T_979) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10891 = or(out_prepend_979, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10892 = bits(_out_T_10891, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1139 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1139 = orr(_out_rimask_T_1139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1139 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1139 = andr(_out_wimask_T_1139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1139 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1139 = orr(_out_romask_T_1139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1139 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1139 = andr(_out_womask_T_1139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1139 = and(out_rivalid_1[1017], out_rimask_1139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1139 = and(out_roready_1[1017], out_romask_1139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1139 = and(out_wivalid_1[1017], out_wimask_1139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1139 = and(out_woready_1[1017], out_womask_1139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10893 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10894 = and(out_f_rivalid_1139, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10895 = and(UInt<1>(0h1), out_f_roready_1139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10896 = eq(out_rimask_1139, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10897 = eq(out_wimask_1139, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10898 = eq(out_romask_1139, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10899 = eq(out_womask_1139, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_980 = or(_out_T_10892, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_980 = cat(_T_632, _out_prepend_T_980) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10900 = or(out_prepend_980, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10901 = bits(_out_T_10900, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1140 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1140 = orr(_out_rimask_T_1140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1140 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1140 = andr(_out_wimask_T_1140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1140 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1140 = orr(_out_romask_T_1140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1140 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1140 = andr(_out_womask_T_1140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1140 = and(out_rivalid_1[1018], out_rimask_1140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1140 = and(out_roready_1[1018], out_romask_1140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1140 = and(out_wivalid_1[1018], out_wimask_1140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1140 = and(out_woready_1[1018], out_womask_1140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10902 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10903 = and(out_f_rivalid_1140, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10904 = and(UInt<1>(0h1), out_f_roready_1140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10905 = eq(out_rimask_1140, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10906 = eq(out_wimask_1140, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10907 = eq(out_romask_1140, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10908 = eq(out_womask_1140, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_981 = or(_out_T_10901, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_981 = cat(_T_633, _out_prepend_T_981) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10909 = or(out_prepend_981, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10910 = bits(_out_T_10909, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1141 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1141 = orr(_out_rimask_T_1141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1141 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1141 = andr(_out_wimask_T_1141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1141 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1141 = orr(_out_romask_T_1141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1141 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1141 = andr(_out_womask_T_1141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1141 = and(out_rivalid_1[1019], out_rimask_1141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1141 = and(out_roready_1[1019], out_romask_1141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1141 = and(out_wivalid_1[1019], out_wimask_1141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1141 = and(out_woready_1[1019], out_womask_1141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10911 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10912 = and(out_f_rivalid_1141, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10913 = and(UInt<1>(0h1), out_f_roready_1141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10914 = eq(out_rimask_1141, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10915 = eq(out_wimask_1141, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10916 = eq(out_romask_1141, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10917 = eq(out_womask_1141, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10918 = or(_T_586, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10919 = bits(_out_T_10918, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1142 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1142 = orr(_out_rimask_T_1142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1142 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1142 = andr(_out_wimask_T_1142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1142 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1142 = orr(_out_romask_T_1142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1142 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1142 = andr(_out_womask_T_1142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1142 = and(out_rivalid_1[1020], out_rimask_1142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1142 = and(out_roready_1[1020], out_romask_1142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1142 = and(out_wivalid_1[1020], out_wimask_1142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1142 = and(out_woready_1[1020], out_womask_1142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10920 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10921 = and(out_f_rivalid_1142, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10922 = and(UInt<1>(0h1), out_f_roready_1142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10923 = eq(out_rimask_1142, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10924 = eq(out_wimask_1142, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10925 = eq(out_romask_1142, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10926 = eq(out_womask_1142, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_982 = or(_out_T_10919, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_982 = cat(_T_587, _out_prepend_T_982) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10927 = or(out_prepend_982, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10928 = bits(_out_T_10927, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1143 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1143 = orr(_out_rimask_T_1143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1143 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1143 = andr(_out_wimask_T_1143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1143 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1143 = orr(_out_romask_T_1143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1143 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1143 = andr(_out_womask_T_1143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1143 = and(out_rivalid_1[1021], out_rimask_1143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1143 = and(out_roready_1[1021], out_romask_1143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1143 = and(out_wivalid_1[1021], out_wimask_1143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1143 = and(out_woready_1[1021], out_womask_1143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10929 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10930 = and(out_f_rivalid_1143, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10931 = and(UInt<1>(0h1), out_f_roready_1143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10932 = eq(out_rimask_1143, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10933 = eq(out_wimask_1143, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10934 = eq(out_romask_1143, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10935 = eq(out_womask_1143, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_983 = or(_out_T_10928, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_983 = cat(_T_588, _out_prepend_T_983) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10936 = or(out_prepend_983, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10937 = bits(_out_T_10936, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1144 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1144 = orr(_out_rimask_T_1144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1144 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1144 = andr(_out_wimask_T_1144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1144 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1144 = orr(_out_romask_T_1144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1144 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1144 = andr(_out_womask_T_1144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1144 = and(out_rivalid_1[1022], out_rimask_1144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1144 = and(out_roready_1[1022], out_romask_1144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1144 = and(out_wivalid_1[1022], out_wimask_1144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1144 = and(out_woready_1[1022], out_womask_1144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10938 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10939 = and(out_f_rivalid_1144, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10940 = and(UInt<1>(0h1), out_f_roready_1144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10941 = eq(out_rimask_1144, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10942 = eq(out_wimask_1144, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10943 = eq(out_romask_1144, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10944 = eq(out_womask_1144, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_984 = or(_out_T_10937, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_984 = cat(_T_589, _out_prepend_T_984) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10945 = or(out_prepend_984, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10946 = bits(_out_T_10945, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1145 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1145 = orr(_out_rimask_T_1145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1145 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1145 = andr(_out_wimask_T_1145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1145 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1145 = orr(_out_romask_T_1145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1145 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1145 = andr(_out_womask_T_1145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1145 = and(out_rivalid_1[1023], out_rimask_1145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1145 = and(out_roready_1[1023], out_romask_1145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1145 = and(out_wivalid_1[1023], out_wimask_1145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1145 = and(out_woready_1[1023], out_womask_1145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10947 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10948 = and(out_f_rivalid_1145, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10949 = and(UInt<1>(0h1), out_f_roready_1145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10950 = eq(out_rimask_1145, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10951 = eq(out_wimask_1145, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10952 = eq(out_romask_1145, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10953 = eq(out_womask_1145, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_985 = or(_out_T_10946, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_985 = cat(_T_590, _out_prepend_T_985) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10954 = or(out_prepend_985, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10955 = bits(_out_T_10954, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1146 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1146 = orr(_out_rimask_T_1146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1146 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1146 = andr(_out_wimask_T_1146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1146 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1146 = orr(_out_romask_T_1146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1146 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1146 = andr(_out_womask_T_1146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1146 = and(out_rivalid_1[1024], out_rimask_1146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1146 = and(out_roready_1[1024], out_romask_1146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1146 = and(out_wivalid_1[1024], out_wimask_1146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1146 = and(out_woready_1[1024], out_womask_1146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10956 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10957 = and(out_f_rivalid_1146, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10958 = and(UInt<1>(0h1), out_f_roready_1146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10959 = eq(out_rimask_1146, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10960 = eq(out_wimask_1146, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10961 = eq(out_romask_1146, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10962 = eq(out_womask_1146, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_986 = or(_out_T_10955, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_986 = cat(_T_591, _out_prepend_T_986) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10963 = or(out_prepend_986, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10964 = bits(_out_T_10963, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1147 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1147 = orr(_out_rimask_T_1147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1147 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1147 = andr(_out_wimask_T_1147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1147 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1147 = orr(_out_romask_T_1147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1147 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1147 = andr(_out_womask_T_1147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1147 = and(out_rivalid_1[1025], out_rimask_1147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1147 = and(out_roready_1[1025], out_romask_1147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1147 = and(out_wivalid_1[1025], out_wimask_1147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1147 = and(out_woready_1[1025], out_womask_1147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10965 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10966 = and(out_f_rivalid_1147, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10967 = and(UInt<1>(0h1), out_f_roready_1147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10968 = eq(out_rimask_1147, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10969 = eq(out_wimask_1147, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10970 = eq(out_romask_1147, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10971 = eq(out_womask_1147, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_987 = or(_out_T_10964, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_987 = cat(_T_592, _out_prepend_T_987) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10972 = or(out_prepend_987, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10973 = bits(_out_T_10972, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1148 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1148 = orr(_out_rimask_T_1148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1148 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1148 = andr(_out_wimask_T_1148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1148 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1148 = orr(_out_romask_T_1148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1148 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1148 = andr(_out_womask_T_1148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1148 = and(out_rivalid_1[1026], out_rimask_1148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1148 = and(out_roready_1[1026], out_romask_1148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1148 = and(out_wivalid_1[1026], out_wimask_1148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1148 = and(out_woready_1[1026], out_womask_1148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10974 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10975 = and(out_f_rivalid_1148, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10976 = and(UInt<1>(0h1), out_f_roready_1148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10977 = eq(out_rimask_1148, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10978 = eq(out_wimask_1148, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10979 = eq(out_romask_1148, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10980 = eq(out_womask_1148, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_988 = or(_out_T_10973, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_988 = cat(_T_593, _out_prepend_T_988) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10981 = or(out_prepend_988, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10982 = bits(_out_T_10981, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1149 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1149 = orr(_out_rimask_T_1149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1149 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1149 = andr(_out_wimask_T_1149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1149 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1149 = orr(_out_romask_T_1149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1149 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1149 = andr(_out_womask_T_1149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1149 = and(out_rivalid_1[1027], out_rimask_1149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1149 = and(out_roready_1[1027], out_romask_1149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1149 = and(out_wivalid_1[1027], out_wimask_1149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1149 = and(out_woready_1[1027], out_womask_1149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10983 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10984 = and(out_f_rivalid_1149, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10985 = and(UInt<1>(0h1), out_f_roready_1149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10986 = eq(out_rimask_1149, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10987 = eq(out_wimask_1149, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10988 = eq(out_romask_1149, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10989 = eq(out_womask_1149, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10990 = or(_T_938, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10991 = bits(_out_T_10990, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1150 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1150 = orr(_out_rimask_T_1150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1150 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1150 = andr(_out_wimask_T_1150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1150 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1150 = orr(_out_romask_T_1150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1150 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1150 = andr(_out_womask_T_1150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1150 = and(out_rivalid_1[1028], out_rimask_1150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1150 = and(out_roready_1[1028], out_romask_1150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1150 = and(out_wivalid_1[1028], out_wimask_1150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1150 = and(out_woready_1[1028], out_womask_1150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10992 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10993 = and(out_f_rivalid_1150, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10994 = and(UInt<1>(0h1), out_f_roready_1150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10995 = eq(out_rimask_1150, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10996 = eq(out_wimask_1150, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10997 = eq(out_romask_1150, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10998 = eq(out_womask_1150, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_989 = or(_out_T_10991, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_989 = cat(_T_939, _out_prepend_T_989) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10999 = or(out_prepend_989, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11000 = bits(_out_T_10999, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1151 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1151 = orr(_out_rimask_T_1151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1151 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1151 = andr(_out_wimask_T_1151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1151 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1151 = orr(_out_romask_T_1151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1151 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1151 = andr(_out_womask_T_1151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1151 = and(out_rivalid_1[1029], out_rimask_1151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1151 = and(out_roready_1[1029], out_romask_1151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1151 = and(out_wivalid_1[1029], out_wimask_1151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1151 = and(out_woready_1[1029], out_womask_1151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11001 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11002 = and(out_f_rivalid_1151, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11003 = and(UInt<1>(0h1), out_f_roready_1151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11004 = eq(out_rimask_1151, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11005 = eq(out_wimask_1151, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11006 = eq(out_romask_1151, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11007 = eq(out_womask_1151, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_990 = or(_out_T_11000, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_990 = cat(_T_940, _out_prepend_T_990) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11008 = or(out_prepend_990, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11009 = bits(_out_T_11008, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1152 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1152 = orr(_out_rimask_T_1152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1152 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1152 = andr(_out_wimask_T_1152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1152 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1152 = orr(_out_romask_T_1152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1152 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1152 = andr(_out_womask_T_1152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1152 = and(out_rivalid_1[1030], out_rimask_1152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1152 = and(out_roready_1[1030], out_romask_1152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1152 = and(out_wivalid_1[1030], out_wimask_1152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1152 = and(out_woready_1[1030], out_womask_1152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11010 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11011 = and(out_f_rivalid_1152, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11012 = and(UInt<1>(0h1), out_f_roready_1152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11013 = eq(out_rimask_1152, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11014 = eq(out_wimask_1152, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11015 = eq(out_romask_1152, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11016 = eq(out_womask_1152, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_991 = or(_out_T_11009, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_991 = cat(_T_941, _out_prepend_T_991) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11017 = or(out_prepend_991, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11018 = bits(_out_T_11017, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1153 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1153 = orr(_out_rimask_T_1153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1153 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1153 = andr(_out_wimask_T_1153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1153 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1153 = orr(_out_romask_T_1153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1153 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1153 = andr(_out_womask_T_1153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1153 = and(out_rivalid_1[1031], out_rimask_1153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1153 = and(out_roready_1[1031], out_romask_1153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1153 = and(out_wivalid_1[1031], out_wimask_1153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1153 = and(out_woready_1[1031], out_womask_1153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11019 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11020 = and(out_f_rivalid_1153, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11021 = and(UInt<1>(0h1), out_f_roready_1153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11022 = eq(out_rimask_1153, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11023 = eq(out_wimask_1153, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11024 = eq(out_romask_1153, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11025 = eq(out_womask_1153, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_992 = or(_out_T_11018, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_992 = cat(_T_942, _out_prepend_T_992) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11026 = or(out_prepend_992, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11027 = bits(_out_T_11026, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1154 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1154 = orr(_out_rimask_T_1154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1154 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1154 = andr(_out_wimask_T_1154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1154 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1154 = orr(_out_romask_T_1154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1154 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1154 = andr(_out_womask_T_1154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1154 = and(out_rivalid_1[1032], out_rimask_1154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1154 = and(out_roready_1[1032], out_romask_1154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1154 = and(out_wivalid_1[1032], out_wimask_1154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1154 = and(out_woready_1[1032], out_womask_1154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11028 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11029 = and(out_f_rivalid_1154, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11030 = and(UInt<1>(0h1), out_f_roready_1154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11031 = eq(out_rimask_1154, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11032 = eq(out_wimask_1154, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11033 = eq(out_romask_1154, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11034 = eq(out_womask_1154, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_993 = or(_out_T_11027, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_993 = cat(_T_943, _out_prepend_T_993) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11035 = or(out_prepend_993, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11036 = bits(_out_T_11035, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1155 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1155 = orr(_out_rimask_T_1155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1155 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1155 = andr(_out_wimask_T_1155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1155 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1155 = orr(_out_romask_T_1155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1155 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1155 = andr(_out_womask_T_1155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1155 = and(out_rivalid_1[1033], out_rimask_1155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1155 = and(out_roready_1[1033], out_romask_1155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1155 = and(out_wivalid_1[1033], out_wimask_1155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1155 = and(out_woready_1[1033], out_womask_1155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11037 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11038 = and(out_f_rivalid_1155, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11039 = and(UInt<1>(0h1), out_f_roready_1155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11040 = eq(out_rimask_1155, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11041 = eq(out_wimask_1155, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11042 = eq(out_romask_1155, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11043 = eq(out_womask_1155, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_994 = or(_out_T_11036, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_994 = cat(_T_944, _out_prepend_T_994) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11044 = or(out_prepend_994, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11045 = bits(_out_T_11044, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1156 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1156 = orr(_out_rimask_T_1156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1156 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1156 = andr(_out_wimask_T_1156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1156 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1156 = orr(_out_romask_T_1156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1156 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1156 = andr(_out_womask_T_1156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1156 = and(out_rivalid_1[1034], out_rimask_1156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1156 = and(out_roready_1[1034], out_romask_1156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1156 = and(out_wivalid_1[1034], out_wimask_1156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1156 = and(out_woready_1[1034], out_womask_1156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11046 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11047 = and(out_f_rivalid_1156, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11048 = and(UInt<1>(0h1), out_f_roready_1156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11049 = eq(out_rimask_1156, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11050 = eq(out_wimask_1156, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11051 = eq(out_romask_1156, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11052 = eq(out_womask_1156, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_995 = or(_out_T_11045, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_995 = cat(_T_945, _out_prepend_T_995) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11053 = or(out_prepend_995, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11054 = bits(_out_T_11053, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1157 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1157 = orr(_out_rimask_T_1157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1157 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1157 = andr(_out_wimask_T_1157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1157 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1157 = orr(_out_romask_T_1157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1157 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1157 = andr(_out_womask_T_1157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1157 = and(out_rivalid_1[1035], out_rimask_1157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1157 = and(out_roready_1[1035], out_romask_1157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1157 = and(out_wivalid_1[1035], out_wimask_1157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1157 = and(out_woready_1[1035], out_womask_1157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11055 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11056 = and(out_f_rivalid_1157, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11057 = and(UInt<1>(0h1), out_f_roready_1157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11058 = eq(out_rimask_1157, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11059 = eq(out_wimask_1157, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11060 = eq(out_romask_1157, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11061 = eq(out_womask_1157, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11062 = or(_T_882, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11063 = bits(_out_T_11062, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1158 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1158 = orr(_out_rimask_T_1158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1158 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1158 = andr(_out_wimask_T_1158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1158 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1158 = orr(_out_romask_T_1158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1158 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1158 = andr(_out_womask_T_1158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1158 = and(out_rivalid_1[1036], out_rimask_1158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1158 = and(out_roready_1[1036], out_romask_1158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1158 = and(out_wivalid_1[1036], out_wimask_1158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1158 = and(out_woready_1[1036], out_womask_1158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11064 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11065 = and(out_f_rivalid_1158, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11066 = and(UInt<1>(0h1), out_f_roready_1158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11067 = eq(out_rimask_1158, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11068 = eq(out_wimask_1158, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11069 = eq(out_romask_1158, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11070 = eq(out_womask_1158, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_996 = or(_out_T_11063, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_996 = cat(_T_883, _out_prepend_T_996) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11071 = or(out_prepend_996, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11072 = bits(_out_T_11071, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1159 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1159 = orr(_out_rimask_T_1159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1159 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1159 = andr(_out_wimask_T_1159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1159 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1159 = orr(_out_romask_T_1159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1159 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1159 = andr(_out_womask_T_1159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1159 = and(out_rivalid_1[1037], out_rimask_1159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1159 = and(out_roready_1[1037], out_romask_1159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1159 = and(out_wivalid_1[1037], out_wimask_1159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1159 = and(out_woready_1[1037], out_womask_1159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11073 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11074 = and(out_f_rivalid_1159, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11075 = and(UInt<1>(0h1), out_f_roready_1159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11076 = eq(out_rimask_1159, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11077 = eq(out_wimask_1159, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11078 = eq(out_romask_1159, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11079 = eq(out_womask_1159, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_997 = or(_out_T_11072, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_997 = cat(_T_884, _out_prepend_T_997) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11080 = or(out_prepend_997, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11081 = bits(_out_T_11080, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1160 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1160 = orr(_out_rimask_T_1160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1160 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1160 = andr(_out_wimask_T_1160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1160 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1160 = orr(_out_romask_T_1160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1160 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1160 = andr(_out_womask_T_1160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1160 = and(out_rivalid_1[1038], out_rimask_1160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1160 = and(out_roready_1[1038], out_romask_1160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1160 = and(out_wivalid_1[1038], out_wimask_1160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1160 = and(out_woready_1[1038], out_womask_1160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11082 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11083 = and(out_f_rivalid_1160, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11084 = and(UInt<1>(0h1), out_f_roready_1160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11085 = eq(out_rimask_1160, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11086 = eq(out_wimask_1160, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11087 = eq(out_romask_1160, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11088 = eq(out_womask_1160, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_998 = or(_out_T_11081, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_998 = cat(_T_885, _out_prepend_T_998) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11089 = or(out_prepend_998, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11090 = bits(_out_T_11089, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1161 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1161 = orr(_out_rimask_T_1161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1161 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1161 = andr(_out_wimask_T_1161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1161 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1161 = orr(_out_romask_T_1161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1161 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1161 = andr(_out_womask_T_1161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1161 = and(out_rivalid_1[1039], out_rimask_1161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1161 = and(out_roready_1[1039], out_romask_1161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1161 = and(out_wivalid_1[1039], out_wimask_1161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1161 = and(out_woready_1[1039], out_womask_1161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11091 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11092 = and(out_f_rivalid_1161, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11093 = and(UInt<1>(0h1), out_f_roready_1161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11094 = eq(out_rimask_1161, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11095 = eq(out_wimask_1161, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11096 = eq(out_romask_1161, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11097 = eq(out_womask_1161, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_999 = or(_out_T_11090, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_999 = cat(_T_886, _out_prepend_T_999) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11098 = or(out_prepend_999, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11099 = bits(_out_T_11098, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1162 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1162 = orr(_out_rimask_T_1162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1162 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1162 = andr(_out_wimask_T_1162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1162 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1162 = orr(_out_romask_T_1162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1162 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1162 = andr(_out_womask_T_1162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1162 = and(out_rivalid_1[1040], out_rimask_1162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1162 = and(out_roready_1[1040], out_romask_1162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1162 = and(out_wivalid_1[1040], out_wimask_1162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1162 = and(out_woready_1[1040], out_womask_1162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11100 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11101 = and(out_f_rivalid_1162, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11102 = and(UInt<1>(0h1), out_f_roready_1162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11103 = eq(out_rimask_1162, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11104 = eq(out_wimask_1162, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11105 = eq(out_romask_1162, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11106 = eq(out_womask_1162, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1000 = or(_out_T_11099, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1000 = cat(_T_887, _out_prepend_T_1000) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11107 = or(out_prepend_1000, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11108 = bits(_out_T_11107, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1163 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1163 = orr(_out_rimask_T_1163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1163 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1163 = andr(_out_wimask_T_1163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1163 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1163 = orr(_out_romask_T_1163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1163 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1163 = andr(_out_womask_T_1163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1163 = and(out_rivalid_1[1041], out_rimask_1163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1163 = and(out_roready_1[1041], out_romask_1163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1163 = and(out_wivalid_1[1041], out_wimask_1163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1163 = and(out_woready_1[1041], out_womask_1163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11109 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11110 = and(out_f_rivalid_1163, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11111 = and(UInt<1>(0h1), out_f_roready_1163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11112 = eq(out_rimask_1163, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11113 = eq(out_wimask_1163, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11114 = eq(out_romask_1163, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11115 = eq(out_womask_1163, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1001 = or(_out_T_11108, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1001 = cat(_T_888, _out_prepend_T_1001) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11116 = or(out_prepend_1001, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11117 = bits(_out_T_11116, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1164 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1164 = orr(_out_rimask_T_1164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1164 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1164 = andr(_out_wimask_T_1164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1164 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1164 = orr(_out_romask_T_1164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1164 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1164 = andr(_out_womask_T_1164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1164 = and(out_rivalid_1[1042], out_rimask_1164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1164 = and(out_roready_1[1042], out_romask_1164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1164 = and(out_wivalid_1[1042], out_wimask_1164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1164 = and(out_woready_1[1042], out_womask_1164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11118 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11119 = and(out_f_rivalid_1164, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11120 = and(UInt<1>(0h1), out_f_roready_1164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11121 = eq(out_rimask_1164, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11122 = eq(out_wimask_1164, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11123 = eq(out_romask_1164, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11124 = eq(out_womask_1164, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1002 = or(_out_T_11117, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1002 = cat(_T_889, _out_prepend_T_1002) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11125 = or(out_prepend_1002, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11126 = bits(_out_T_11125, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1165 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1165 = orr(_out_rimask_T_1165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1165 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1165 = andr(_out_wimask_T_1165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1165 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1165 = orr(_out_romask_T_1165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1165 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1165 = andr(_out_womask_T_1165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1165 = and(out_rivalid_1[1043], out_rimask_1165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1165 = and(out_roready_1[1043], out_romask_1165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1165 = and(out_wivalid_1[1043], out_wimask_1165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1165 = and(out_woready_1[1043], out_womask_1165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11127 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11128 = and(out_f_rivalid_1165, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11129 = and(UInt<1>(0h1), out_f_roready_1165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11130 = eq(out_rimask_1165, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11131 = eq(out_wimask_1165, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11132 = eq(out_romask_1165, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11133 = eq(out_womask_1165, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11134 = or(_T_762, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11135 = bits(_out_T_11134, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1166 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1166 = orr(_out_rimask_T_1166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1166 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1166 = andr(_out_wimask_T_1166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1166 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1166 = orr(_out_romask_T_1166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1166 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1166 = andr(_out_womask_T_1166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1166 = and(out_rivalid_1[1044], out_rimask_1166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1166 = and(out_roready_1[1044], out_romask_1166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1166 = and(out_wivalid_1[1044], out_wimask_1166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1166 = and(out_woready_1[1044], out_womask_1166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11136 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11137 = and(out_f_rivalid_1166, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11138 = and(UInt<1>(0h1), out_f_roready_1166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11139 = eq(out_rimask_1166, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11140 = eq(out_wimask_1166, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11141 = eq(out_romask_1166, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11142 = eq(out_womask_1166, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1003 = or(_out_T_11135, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1003 = cat(_T_763, _out_prepend_T_1003) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11143 = or(out_prepend_1003, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11144 = bits(_out_T_11143, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1167 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1167 = orr(_out_rimask_T_1167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1167 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1167 = andr(_out_wimask_T_1167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1167 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1167 = orr(_out_romask_T_1167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1167 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1167 = andr(_out_womask_T_1167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1167 = and(out_rivalid_1[1045], out_rimask_1167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1167 = and(out_roready_1[1045], out_romask_1167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1167 = and(out_wivalid_1[1045], out_wimask_1167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1167 = and(out_woready_1[1045], out_womask_1167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11145 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11146 = and(out_f_rivalid_1167, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11147 = and(UInt<1>(0h1), out_f_roready_1167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11148 = eq(out_rimask_1167, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11149 = eq(out_wimask_1167, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11150 = eq(out_romask_1167, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11151 = eq(out_womask_1167, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1004 = or(_out_T_11144, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1004 = cat(_T_764, _out_prepend_T_1004) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11152 = or(out_prepend_1004, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11153 = bits(_out_T_11152, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1168 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1168 = orr(_out_rimask_T_1168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1168 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1168 = andr(_out_wimask_T_1168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1168 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1168 = orr(_out_romask_T_1168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1168 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1168 = andr(_out_womask_T_1168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1168 = and(out_rivalid_1[1046], out_rimask_1168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1168 = and(out_roready_1[1046], out_romask_1168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1168 = and(out_wivalid_1[1046], out_wimask_1168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1168 = and(out_woready_1[1046], out_womask_1168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11154 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11155 = and(out_f_rivalid_1168, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11156 = and(UInt<1>(0h1), out_f_roready_1168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11157 = eq(out_rimask_1168, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11158 = eq(out_wimask_1168, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11159 = eq(out_romask_1168, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11160 = eq(out_womask_1168, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1005 = or(_out_T_11153, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1005 = cat(_T_765, _out_prepend_T_1005) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11161 = or(out_prepend_1005, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11162 = bits(_out_T_11161, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1169 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1169 = orr(_out_rimask_T_1169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1169 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1169 = andr(_out_wimask_T_1169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1169 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1169 = orr(_out_romask_T_1169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1169 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1169 = andr(_out_womask_T_1169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1169 = and(out_rivalid_1[1047], out_rimask_1169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1169 = and(out_roready_1[1047], out_romask_1169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1169 = and(out_wivalid_1[1047], out_wimask_1169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1169 = and(out_woready_1[1047], out_womask_1169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11163 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11164 = and(out_f_rivalid_1169, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11165 = and(UInt<1>(0h1), out_f_roready_1169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11166 = eq(out_rimask_1169, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11167 = eq(out_wimask_1169, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11168 = eq(out_romask_1169, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11169 = eq(out_womask_1169, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1006 = or(_out_T_11162, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1006 = cat(_T_766, _out_prepend_T_1006) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11170 = or(out_prepend_1006, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11171 = bits(_out_T_11170, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1170 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1170 = orr(_out_rimask_T_1170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1170 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1170 = andr(_out_wimask_T_1170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1170 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1170 = orr(_out_romask_T_1170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1170 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1170 = andr(_out_womask_T_1170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1170 = and(out_rivalid_1[1048], out_rimask_1170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1170 = and(out_roready_1[1048], out_romask_1170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1170 = and(out_wivalid_1[1048], out_wimask_1170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1170 = and(out_woready_1[1048], out_womask_1170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11172 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11173 = and(out_f_rivalid_1170, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11174 = and(UInt<1>(0h1), out_f_roready_1170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11175 = eq(out_rimask_1170, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11176 = eq(out_wimask_1170, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11177 = eq(out_romask_1170, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11178 = eq(out_womask_1170, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1007 = or(_out_T_11171, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1007 = cat(_T_767, _out_prepend_T_1007) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11179 = or(out_prepend_1007, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11180 = bits(_out_T_11179, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1171 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1171 = orr(_out_rimask_T_1171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1171 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1171 = andr(_out_wimask_T_1171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1171 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1171 = orr(_out_romask_T_1171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1171 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1171 = andr(_out_womask_T_1171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1171 = and(out_rivalid_1[1049], out_rimask_1171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1171 = and(out_roready_1[1049], out_romask_1171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1171 = and(out_wivalid_1[1049], out_wimask_1171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1171 = and(out_woready_1[1049], out_womask_1171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11181 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11182 = and(out_f_rivalid_1171, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11183 = and(UInt<1>(0h1), out_f_roready_1171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11184 = eq(out_rimask_1171, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11185 = eq(out_wimask_1171, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11186 = eq(out_romask_1171, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11187 = eq(out_womask_1171, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1008 = or(_out_T_11180, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1008 = cat(_T_768, _out_prepend_T_1008) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11188 = or(out_prepend_1008, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11189 = bits(_out_T_11188, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1172 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1172 = orr(_out_rimask_T_1172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1172 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1172 = andr(_out_wimask_T_1172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1172 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1172 = orr(_out_romask_T_1172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1172 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1172 = andr(_out_womask_T_1172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1172 = and(out_rivalid_1[1050], out_rimask_1172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1172 = and(out_roready_1[1050], out_romask_1172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1172 = and(out_wivalid_1[1050], out_wimask_1172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1172 = and(out_woready_1[1050], out_womask_1172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11190 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11191 = and(out_f_rivalid_1172, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11192 = and(UInt<1>(0h1), out_f_roready_1172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11193 = eq(out_rimask_1172, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11194 = eq(out_wimask_1172, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11195 = eq(out_romask_1172, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11196 = eq(out_womask_1172, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1009 = or(_out_T_11189, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1009 = cat(_T_769, _out_prepend_T_1009) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11197 = or(out_prepend_1009, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11198 = bits(_out_T_11197, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1173 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1173 = orr(_out_rimask_T_1173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1173 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1173 = andr(_out_wimask_T_1173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1173 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1173 = orr(_out_romask_T_1173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1173 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1173 = andr(_out_womask_T_1173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1173 = and(out_rivalid_1[1051], out_rimask_1173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1173 = and(out_roready_1[1051], out_romask_1173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1173 = and(out_wivalid_1[1051], out_wimask_1173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1173 = and(out_woready_1[1051], out_womask_1173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11199 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11200 = and(out_f_rivalid_1173, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11201 = and(UInt<1>(0h1), out_f_roready_1173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11202 = eq(out_rimask_1173, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11203 = eq(out_wimask_1173, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11204 = eq(out_romask_1173, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11205 = eq(out_womask_1173, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11206 = or(UInt<8>(0h73), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11207 = bits(_out_T_11206, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1174 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1174 = orr(_out_rimask_T_1174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1174 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1174 = andr(_out_wimask_T_1174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1174 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1174 = orr(_out_romask_T_1174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1174 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1174 = andr(_out_womask_T_1174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1174 = and(out_rivalid_1[1052], out_rimask_1174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1174 = and(out_roready_1[1052], out_romask_1174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1174 = and(out_wivalid_1[1052], out_wimask_1174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1174 = and(out_woready_1[1052], out_womask_1174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11208 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11209 = and(out_f_rivalid_1174, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11210 = and(UInt<1>(0h1), out_f_roready_1174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11211 = eq(out_rimask_1174, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11212 = eq(out_wimask_1174, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11213 = eq(out_romask_1174, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11214 = eq(out_womask_1174, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1010 = or(_out_T_11207, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1010 = cat(UInt<8>(0h24), _out_prepend_T_1010) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11215 = or(out_prepend_1010, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11216 = bits(_out_T_11215, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1175 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1175 = orr(_out_rimask_T_1175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1175 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1175 = andr(_out_wimask_T_1175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1175 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1175 = orr(_out_romask_T_1175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1175 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1175 = andr(_out_womask_T_1175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1175 = and(out_rivalid_1[1053], out_rimask_1175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1175 = and(out_roready_1[1053], out_romask_1175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1175 = and(out_wivalid_1[1053], out_wimask_1175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1175 = and(out_woready_1[1053], out_womask_1175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11217 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11218 = and(out_f_rivalid_1175, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11219 = and(UInt<1>(0h1), out_f_roready_1175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11220 = eq(out_rimask_1175, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11221 = eq(out_wimask_1175, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11222 = eq(out_romask_1175, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11223 = eq(out_womask_1175, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1011 = or(_out_T_11216, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1011 = cat(UInt<8>(0h20), _out_prepend_T_1011) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11224 = or(out_prepend_1011, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11225 = bits(_out_T_11224, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1176 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1176 = orr(_out_rimask_T_1176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1176 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1176 = andr(_out_wimask_T_1176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1176 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1176 = orr(_out_romask_T_1176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1176 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1176 = andr(_out_womask_T_1176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1176 = and(out_rivalid_1[1054], out_rimask_1176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1176 = and(out_roready_1[1054], out_romask_1176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1176 = and(out_wivalid_1[1054], out_wimask_1176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1176 = and(out_woready_1[1054], out_womask_1176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11226 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11227 = and(out_f_rivalid_1176, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11228 = and(UInt<1>(0h1), out_f_roready_1176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11229 = eq(out_rimask_1176, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11230 = eq(out_wimask_1176, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11231 = eq(out_romask_1176, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11232 = eq(out_womask_1176, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1012 = or(_out_T_11225, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1012 = cat(UInt<8>(0h7b), _out_prepend_T_1012) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11233 = or(out_prepend_1012, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11234 = bits(_out_T_11233, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1177 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1177 = orr(_out_rimask_T_1177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1177 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1177 = andr(_out_wimask_T_1177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1177 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1177 = orr(_out_romask_T_1177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1177 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1177 = andr(_out_womask_T_1177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1177 = and(out_rivalid_1[1055], out_rimask_1177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1177 = and(out_roready_1[1055], out_romask_1177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1177 = and(out_wivalid_1[1055], out_wimask_1177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1177 = and(out_woready_1[1055], out_womask_1177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11235 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11236 = and(out_f_rivalid_1177, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11237 = and(UInt<1>(0h1), out_f_roready_1177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11238 = eq(out_rimask_1177, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11239 = eq(out_wimask_1177, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11240 = eq(out_romask_1177, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11241 = eq(out_womask_1177, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1013 = or(_out_T_11234, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1013 = cat(UInt<8>(0h23), _out_prepend_T_1013) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11242 = or(out_prepend_1013, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11243 = bits(_out_T_11242, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1178 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1178 = orr(_out_rimask_T_1178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1178 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1178 = andr(_out_wimask_T_1178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1178 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1178 = orr(_out_romask_T_1178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1178 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1178 = andr(_out_womask_T_1178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1178 = and(out_rivalid_1[1056], out_rimask_1178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1178 = and(out_roready_1[1056], out_romask_1178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1178 = and(out_wivalid_1[1056], out_wimask_1178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1178 = and(out_woready_1[1056], out_womask_1178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11244 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11245 = and(out_f_rivalid_1178, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11246 = and(UInt<1>(0h1), out_f_roready_1178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11247 = eq(out_rimask_1178, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11248 = eq(out_wimask_1178, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11249 = eq(out_romask_1178, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11250 = eq(out_womask_1178, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1014 = or(_out_T_11243, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1014 = cat(UInt<8>(0h22), _out_prepend_T_1014) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11251 = or(out_prepend_1014, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11252 = bits(_out_T_11251, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1179 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1179 = orr(_out_rimask_T_1179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1179 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1179 = andr(_out_wimask_T_1179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1179 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1179 = orr(_out_romask_T_1179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1179 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1179 = andr(_out_womask_T_1179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1179 = and(out_rivalid_1[1057], out_rimask_1179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1179 = and(out_roready_1[1057], out_romask_1179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1179 = and(out_wivalid_1[1057], out_wimask_1179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1179 = and(out_woready_1[1057], out_womask_1179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11253 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11254 = and(out_f_rivalid_1179, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11255 = and(UInt<1>(0h1), out_f_roready_1179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11256 = eq(out_rimask_1179, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11257 = eq(out_wimask_1179, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11258 = eq(out_romask_1179, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11259 = eq(out_womask_1179, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1015 = or(_out_T_11252, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1015 = cat(UInt<8>(0h0), _out_prepend_T_1015) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11260 = or(out_prepend_1015, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11261 = bits(_out_T_11260, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1180 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1180 = orr(_out_rimask_T_1180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1180 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1180 = andr(_out_wimask_T_1180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1180 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1180 = orr(_out_romask_T_1180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1180 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1180 = andr(_out_womask_T_1180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1180 = and(out_rivalid_1[1058], out_rimask_1180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1180 = and(out_roready_1[1058], out_romask_1180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1180 = and(out_wivalid_1[1058], out_wimask_1180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1180 = and(out_woready_1[1058], out_womask_1180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11262 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11263 = and(out_f_rivalid_1180, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11264 = and(UInt<1>(0h1), out_f_roready_1180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11265 = eq(out_rimask_1180, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11266 = eq(out_wimask_1180, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11267 = eq(out_romask_1180, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11268 = eq(out_womask_1180, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1016 = or(_out_T_11261, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1016 = cat(UInt<8>(0h10), _out_prepend_T_1016) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11269 = or(out_prepend_1016, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11270 = bits(_out_T_11269, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1181 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1181 = orr(_out_rimask_T_1181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1181 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1181 = andr(_out_wimask_T_1181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1181 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1181 = orr(_out_romask_T_1181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1181 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1181 = andr(_out_womask_T_1181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1181 = and(out_rivalid_1[1059], out_rimask_1181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1181 = and(out_roready_1[1059], out_romask_1181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1181 = and(out_wivalid_1[1059], out_wimask_1181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1181 = and(out_woready_1[1059], out_womask_1181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11271 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11272 = and(out_f_rivalid_1181, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11273 = and(UInt<1>(0h1), out_f_roready_1181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11274 = eq(out_rimask_1181, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11275 = eq(out_wimask_1181, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11276 = eq(out_romask_1181, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11277 = eq(out_womask_1181, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11278 = or(_T_1098, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11279 = bits(_out_T_11278, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1182 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1182 = orr(_out_rimask_T_1182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1182 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1182 = andr(_out_wimask_T_1182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1182 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1182 = orr(_out_romask_T_1182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1182 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1182 = andr(_out_womask_T_1182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1182 = and(out_rivalid_1[1060], out_rimask_1182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1182 = and(out_roready_1[1060], out_romask_1182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1182 = and(out_wivalid_1[1060], out_wimask_1182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1182 = and(out_woready_1[1060], out_womask_1182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11280 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11281 = and(out_f_rivalid_1182, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11282 = and(UInt<1>(0h1), out_f_roready_1182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11283 = eq(out_rimask_1182, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11284 = eq(out_wimask_1182, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11285 = eq(out_romask_1182, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11286 = eq(out_womask_1182, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1017 = or(_out_T_11279, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1017 = cat(_T_1099, _out_prepend_T_1017) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11287 = or(out_prepend_1017, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11288 = bits(_out_T_11287, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1183 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1183 = orr(_out_rimask_T_1183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1183 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1183 = andr(_out_wimask_T_1183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1183 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1183 = orr(_out_romask_T_1183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1183 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1183 = andr(_out_womask_T_1183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1183 = and(out_rivalid_1[1061], out_rimask_1183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1183 = and(out_roready_1[1061], out_romask_1183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1183 = and(out_wivalid_1[1061], out_wimask_1183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1183 = and(out_woready_1[1061], out_womask_1183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11289 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11290 = and(out_f_rivalid_1183, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11291 = and(UInt<1>(0h1), out_f_roready_1183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11292 = eq(out_rimask_1183, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11293 = eq(out_wimask_1183, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11294 = eq(out_romask_1183, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11295 = eq(out_womask_1183, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1018 = or(_out_T_11288, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1018 = cat(_T_1100, _out_prepend_T_1018) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11296 = or(out_prepend_1018, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11297 = bits(_out_T_11296, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1184 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1184 = orr(_out_rimask_T_1184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1184 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1184 = andr(_out_wimask_T_1184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1184 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1184 = orr(_out_romask_T_1184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1184 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1184 = andr(_out_womask_T_1184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1184 = and(out_rivalid_1[1062], out_rimask_1184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1184 = and(out_roready_1[1062], out_romask_1184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1184 = and(out_wivalid_1[1062], out_wimask_1184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1184 = and(out_woready_1[1062], out_womask_1184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11298 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11299 = and(out_f_rivalid_1184, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11300 = and(UInt<1>(0h1), out_f_roready_1184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11301 = eq(out_rimask_1184, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11302 = eq(out_wimask_1184, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11303 = eq(out_romask_1184, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11304 = eq(out_womask_1184, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1019 = or(_out_T_11297, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1019 = cat(_T_1101, _out_prepend_T_1019) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11305 = or(out_prepend_1019, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11306 = bits(_out_T_11305, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1185 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1185 = orr(_out_rimask_T_1185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1185 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1185 = andr(_out_wimask_T_1185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1185 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1185 = orr(_out_romask_T_1185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1185 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1185 = andr(_out_womask_T_1185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1185 = and(out_rivalid_1[1063], out_rimask_1185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1185 = and(out_roready_1[1063], out_romask_1185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1185 = and(out_wivalid_1[1063], out_wimask_1185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1185 = and(out_woready_1[1063], out_womask_1185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11307 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11308 = and(out_f_rivalid_1185, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11309 = and(UInt<1>(0h1), out_f_roready_1185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11310 = eq(out_rimask_1185, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11311 = eq(out_wimask_1185, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11312 = eq(out_romask_1185, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11313 = eq(out_womask_1185, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1020 = or(_out_T_11306, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1020 = cat(_T_1102, _out_prepend_T_1020) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11314 = or(out_prepend_1020, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11315 = bits(_out_T_11314, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1186 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1186 = orr(_out_rimask_T_1186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1186 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1186 = andr(_out_wimask_T_1186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1186 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1186 = orr(_out_romask_T_1186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1186 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1186 = andr(_out_womask_T_1186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1186 = and(out_rivalid_1[1064], out_rimask_1186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1186 = and(out_roready_1[1064], out_romask_1186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1186 = and(out_wivalid_1[1064], out_wimask_1186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1186 = and(out_woready_1[1064], out_womask_1186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11316 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11317 = and(out_f_rivalid_1186, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11318 = and(UInt<1>(0h1), out_f_roready_1186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11319 = eq(out_rimask_1186, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11320 = eq(out_wimask_1186, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11321 = eq(out_romask_1186, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11322 = eq(out_womask_1186, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1021 = or(_out_T_11315, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1021 = cat(_T_1103, _out_prepend_T_1021) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11323 = or(out_prepend_1021, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11324 = bits(_out_T_11323, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1187 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1187 = orr(_out_rimask_T_1187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1187 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1187 = andr(_out_wimask_T_1187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1187 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1187 = orr(_out_romask_T_1187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1187 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1187 = andr(_out_womask_T_1187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1187 = and(out_rivalid_1[1065], out_rimask_1187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1187 = and(out_roready_1[1065], out_romask_1187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1187 = and(out_wivalid_1[1065], out_wimask_1187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1187 = and(out_woready_1[1065], out_womask_1187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11325 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11326 = and(out_f_rivalid_1187, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11327 = and(UInt<1>(0h1), out_f_roready_1187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11328 = eq(out_rimask_1187, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11329 = eq(out_wimask_1187, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11330 = eq(out_romask_1187, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11331 = eq(out_womask_1187, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1022 = or(_out_T_11324, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1022 = cat(_T_1104, _out_prepend_T_1022) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11332 = or(out_prepend_1022, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11333 = bits(_out_T_11332, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1188 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1188 = orr(_out_rimask_T_1188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1188 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1188 = andr(_out_wimask_T_1188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1188 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1188 = orr(_out_romask_T_1188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1188 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1188 = andr(_out_womask_T_1188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1188 = and(out_rivalid_1[1066], out_rimask_1188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1188 = and(out_roready_1[1066], out_romask_1188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1188 = and(out_wivalid_1[1066], out_wimask_1188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1188 = and(out_woready_1[1066], out_womask_1188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11334 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11335 = and(out_f_rivalid_1188, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11336 = and(UInt<1>(0h1), out_f_roready_1188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11337 = eq(out_rimask_1188, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11338 = eq(out_wimask_1188, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11339 = eq(out_romask_1188, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11340 = eq(out_womask_1188, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1023 = or(_out_T_11333, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1023 = cat(_T_1105, _out_prepend_T_1023) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11341 = or(out_prepend_1023, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11342 = bits(_out_T_11341, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1189 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1189 = orr(_out_rimask_T_1189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1189 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1189 = andr(_out_wimask_T_1189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1189 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1189 = orr(_out_romask_T_1189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1189 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1189 = andr(_out_womask_T_1189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1189 = and(out_rivalid_1[1067], out_rimask_1189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1189 = and(out_roready_1[1067], out_romask_1189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1189 = and(out_wivalid_1[1067], out_wimask_1189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1189 = and(out_woready_1[1067], out_womask_1189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11343 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1189 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[24], _out_T_11343 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_11344 = and(out_f_rivalid_1189, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11345 = and(UInt<1>(0h1), out_f_roready_1189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11346 = and(out_f_wivalid_1189, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11347 = and(UInt<1>(0h1), out_f_woready_1189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11348 = eq(out_rimask_1189, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11349 = eq(out_wimask_1189, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11350 = eq(out_romask_1189, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11351 = eq(out_womask_1189, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11352 = or(programBufferMem[24], UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11353 = bits(_out_T_11352, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1190 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1190 = orr(_out_rimask_T_1190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1190 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1190 = andr(_out_wimask_T_1190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1190 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1190 = orr(_out_romask_T_1190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1190 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1190 = andr(_out_womask_T_1190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1190 = and(out_rivalid_1[1068], out_rimask_1190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1190 = and(out_roready_1[1068], out_romask_1190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1190 = and(out_wivalid_1[1068], out_wimask_1190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1190 = and(out_woready_1[1068], out_womask_1190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11354 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1190 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[25], _out_T_11354 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_11355 = and(out_f_rivalid_1190, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11356 = and(UInt<1>(0h1), out_f_roready_1190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11357 = and(out_f_wivalid_1190, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11358 = and(UInt<1>(0h1), out_f_woready_1190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11359 = eq(out_rimask_1190, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11360 = eq(out_wimask_1190, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11361 = eq(out_romask_1190, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11362 = eq(out_womask_1190, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1024 = or(_out_T_11353, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1024 = cat(programBufferMem[25], _out_prepend_T_1024) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11363 = or(out_prepend_1024, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11364 = bits(_out_T_11363, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1191 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1191 = orr(_out_rimask_T_1191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1191 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1191 = andr(_out_wimask_T_1191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1191 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1191 = orr(_out_romask_T_1191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1191 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1191 = andr(_out_womask_T_1191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1191 = and(out_rivalid_1[1069], out_rimask_1191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1191 = and(out_roready_1[1069], out_romask_1191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1191 = and(out_wivalid_1[1069], out_wimask_1191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1191 = and(out_woready_1[1069], out_womask_1191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11365 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1191 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[26], _out_T_11365 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_11366 = and(out_f_rivalid_1191, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11367 = and(UInt<1>(0h1), out_f_roready_1191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11368 = and(out_f_wivalid_1191, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11369 = and(UInt<1>(0h1), out_f_woready_1191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11370 = eq(out_rimask_1191, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11371 = eq(out_wimask_1191, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11372 = eq(out_romask_1191, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11373 = eq(out_womask_1191, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1025 = or(_out_T_11364, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1025 = cat(programBufferMem[26], _out_prepend_T_1025) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11374 = or(out_prepend_1025, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11375 = bits(_out_T_11374, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1192 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1192 = orr(_out_rimask_T_1192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1192 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1192 = andr(_out_wimask_T_1192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1192 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1192 = orr(_out_romask_T_1192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1192 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1192 = andr(_out_womask_T_1192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1192 = and(out_rivalid_1[1070], out_rimask_1192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1192 = and(out_roready_1[1070], out_romask_1192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1192 = and(out_wivalid_1[1070], out_wimask_1192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1192 = and(out_woready_1[1070], out_womask_1192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11376 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1192 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[27], _out_T_11376 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_11377 = and(out_f_rivalid_1192, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11378 = and(UInt<1>(0h1), out_f_roready_1192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11379 = and(out_f_wivalid_1192, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11380 = and(UInt<1>(0h1), out_f_woready_1192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11381 = eq(out_rimask_1192, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11382 = eq(out_wimask_1192, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11383 = eq(out_romask_1192, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11384 = eq(out_womask_1192, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1026 = or(_out_T_11375, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1026 = cat(programBufferMem[27], _out_prepend_T_1026) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11385 = or(out_prepend_1026, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11386 = bits(_out_T_11385, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1193 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1193 = orr(_out_rimask_T_1193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1193 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1193 = andr(_out_wimask_T_1193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1193 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1193 = orr(_out_romask_T_1193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1193 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1193 = andr(_out_womask_T_1193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1193 = and(out_rivalid_1[1071], out_rimask_1193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1193 = and(out_roready_1[1071], out_romask_1193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1193 = and(out_wivalid_1[1071], out_wimask_1193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1193 = and(out_woready_1[1071], out_womask_1193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11387 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1193 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[28], _out_T_11387 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_11388 = and(out_f_rivalid_1193, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11389 = and(UInt<1>(0h1), out_f_roready_1193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11390 = and(out_f_wivalid_1193, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11391 = and(UInt<1>(0h1), out_f_woready_1193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11392 = eq(out_rimask_1193, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11393 = eq(out_wimask_1193, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11394 = eq(out_romask_1193, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11395 = eq(out_womask_1193, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1027 = or(_out_T_11386, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1027 = cat(programBufferMem[28], _out_prepend_T_1027) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11396 = or(out_prepend_1027, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11397 = bits(_out_T_11396, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1194 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1194 = orr(_out_rimask_T_1194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1194 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1194 = andr(_out_wimask_T_1194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1194 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1194 = orr(_out_romask_T_1194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1194 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1194 = andr(_out_womask_T_1194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1194 = and(out_rivalid_1[1072], out_rimask_1194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1194 = and(out_roready_1[1072], out_romask_1194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1194 = and(out_wivalid_1[1072], out_wimask_1194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1194 = and(out_woready_1[1072], out_womask_1194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11398 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1194 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[29], _out_T_11398 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_11399 = and(out_f_rivalid_1194, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11400 = and(UInt<1>(0h1), out_f_roready_1194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11401 = and(out_f_wivalid_1194, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11402 = and(UInt<1>(0h1), out_f_woready_1194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11403 = eq(out_rimask_1194, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11404 = eq(out_wimask_1194, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11405 = eq(out_romask_1194, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11406 = eq(out_womask_1194, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1028 = or(_out_T_11397, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1028 = cat(programBufferMem[29], _out_prepend_T_1028) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11407 = or(out_prepend_1028, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11408 = bits(_out_T_11407, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1195 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1195 = orr(_out_rimask_T_1195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1195 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1195 = andr(_out_wimask_T_1195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1195 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1195 = orr(_out_romask_T_1195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1195 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1195 = andr(_out_womask_T_1195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1195 = and(out_rivalid_1[1073], out_rimask_1195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1195 = and(out_roready_1[1073], out_romask_1195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1195 = and(out_wivalid_1[1073], out_wimask_1195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1195 = and(out_woready_1[1073], out_womask_1195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11409 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1195 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[30], _out_T_11409 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_11410 = and(out_f_rivalid_1195, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11411 = and(UInt<1>(0h1), out_f_roready_1195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11412 = and(out_f_wivalid_1195, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11413 = and(UInt<1>(0h1), out_f_woready_1195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11414 = eq(out_rimask_1195, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11415 = eq(out_wimask_1195, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11416 = eq(out_romask_1195, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11417 = eq(out_womask_1195, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1029 = or(_out_T_11408, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1029 = cat(programBufferMem[30], _out_prepend_T_1029) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11418 = or(out_prepend_1029, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11419 = bits(_out_T_11418, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1196 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1196 = orr(_out_rimask_T_1196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1196 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1196 = andr(_out_wimask_T_1196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1196 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1196 = orr(_out_romask_T_1196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1196 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1196 = andr(_out_womask_T_1196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1196 = and(out_rivalid_1[1074], out_rimask_1196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1196 = and(out_roready_1[1074], out_romask_1196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1196 = and(out_wivalid_1[1074], out_wimask_1196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1196 = and(out_woready_1[1074], out_womask_1196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11420 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1196 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[31], _out_T_11420 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_11421 = and(out_f_rivalid_1196, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11422 = and(UInt<1>(0h1), out_f_roready_1196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11423 = and(out_f_wivalid_1196, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11424 = and(UInt<1>(0h1), out_f_woready_1196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11425 = eq(out_rimask_1196, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11426 = eq(out_wimask_1196, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11427 = eq(out_romask_1196, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11428 = eq(out_womask_1196, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1030 = or(_out_T_11419, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1030 = cat(programBufferMem[31], _out_prepend_T_1030) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11429 = or(out_prepend_1030, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11430 = bits(_out_T_11429, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1197 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1197 = orr(_out_rimask_T_1197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1197 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1197 = andr(_out_wimask_T_1197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1197 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1197 = orr(_out_romask_T_1197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1197 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1197 = andr(_out_womask_T_1197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1197 = and(out_rivalid_1[1075], out_rimask_1197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1197 = and(out_roready_1[1075], out_romask_1197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1197 = and(out_wivalid_1[1075], out_wimask_1197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1197 = and(out_woready_1[1075], out_womask_1197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11431 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11432 = and(out_f_rivalid_1197, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11433 = and(UInt<1>(0h1), out_f_roready_1197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11434 = eq(out_rimask_1197, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11435 = eq(out_wimask_1197, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11436 = eq(out_romask_1197, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11437 = eq(out_womask_1197, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11438 = or(_T_506, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11439 = bits(_out_T_11438, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1198 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1198 = orr(_out_rimask_T_1198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1198 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1198 = andr(_out_wimask_T_1198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1198 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1198 = orr(_out_romask_T_1198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1198 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1198 = andr(_out_womask_T_1198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1198 = and(out_rivalid_1[1076], out_rimask_1198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1198 = and(out_roready_1[1076], out_romask_1198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1198 = and(out_wivalid_1[1076], out_wimask_1198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1198 = and(out_woready_1[1076], out_womask_1198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11440 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11441 = and(out_f_rivalid_1198, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11442 = and(UInt<1>(0h1), out_f_roready_1198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11443 = eq(out_rimask_1198, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11444 = eq(out_wimask_1198, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11445 = eq(out_romask_1198, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11446 = eq(out_womask_1198, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1031 = or(_out_T_11439, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1031 = cat(_T_507, _out_prepend_T_1031) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11447 = or(out_prepend_1031, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11448 = bits(_out_T_11447, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1199 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1199 = orr(_out_rimask_T_1199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1199 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1199 = andr(_out_wimask_T_1199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1199 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1199 = orr(_out_romask_T_1199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1199 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1199 = andr(_out_womask_T_1199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1199 = and(out_rivalid_1[1077], out_rimask_1199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1199 = and(out_roready_1[1077], out_romask_1199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1199 = and(out_wivalid_1[1077], out_wimask_1199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1199 = and(out_woready_1[1077], out_womask_1199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11449 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11450 = and(out_f_rivalid_1199, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11451 = and(UInt<1>(0h1), out_f_roready_1199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11452 = eq(out_rimask_1199, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11453 = eq(out_wimask_1199, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11454 = eq(out_romask_1199, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11455 = eq(out_womask_1199, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1032 = or(_out_T_11448, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1032 = cat(_T_508, _out_prepend_T_1032) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11456 = or(out_prepend_1032, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11457 = bits(_out_T_11456, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1200 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1200 = orr(_out_rimask_T_1200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1200 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1200 = andr(_out_wimask_T_1200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1200 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1200 = orr(_out_romask_T_1200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1200 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1200 = andr(_out_womask_T_1200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1200 = and(out_rivalid_1[1078], out_rimask_1200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1200 = and(out_roready_1[1078], out_romask_1200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1200 = and(out_wivalid_1[1078], out_wimask_1200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1200 = and(out_woready_1[1078], out_womask_1200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11458 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11459 = and(out_f_rivalid_1200, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11460 = and(UInt<1>(0h1), out_f_roready_1200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11461 = eq(out_rimask_1200, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11462 = eq(out_wimask_1200, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11463 = eq(out_romask_1200, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11464 = eq(out_womask_1200, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1033 = or(_out_T_11457, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1033 = cat(_T_509, _out_prepend_T_1033) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11465 = or(out_prepend_1033, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11466 = bits(_out_T_11465, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1201 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1201 = orr(_out_rimask_T_1201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1201 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1201 = andr(_out_wimask_T_1201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1201 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1201 = orr(_out_romask_T_1201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1201 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1201 = andr(_out_womask_T_1201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1201 = and(out_rivalid_1[1079], out_rimask_1201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1201 = and(out_roready_1[1079], out_romask_1201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1201 = and(out_wivalid_1[1079], out_wimask_1201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1201 = and(out_woready_1[1079], out_womask_1201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11467 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11468 = and(out_f_rivalid_1201, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11469 = and(UInt<1>(0h1), out_f_roready_1201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11470 = eq(out_rimask_1201, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11471 = eq(out_wimask_1201, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11472 = eq(out_romask_1201, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11473 = eq(out_womask_1201, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1034 = or(_out_T_11466, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1034 = cat(_T_510, _out_prepend_T_1034) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11474 = or(out_prepend_1034, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11475 = bits(_out_T_11474, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1202 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1202 = orr(_out_rimask_T_1202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1202 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1202 = andr(_out_wimask_T_1202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1202 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1202 = orr(_out_romask_T_1202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1202 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1202 = andr(_out_womask_T_1202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1202 = and(out_rivalid_1[1080], out_rimask_1202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1202 = and(out_roready_1[1080], out_romask_1202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1202 = and(out_wivalid_1[1080], out_wimask_1202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1202 = and(out_woready_1[1080], out_womask_1202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11476 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11477 = and(out_f_rivalid_1202, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11478 = and(UInt<1>(0h1), out_f_roready_1202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11479 = eq(out_rimask_1202, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11480 = eq(out_wimask_1202, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11481 = eq(out_romask_1202, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11482 = eq(out_womask_1202, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1035 = or(_out_T_11475, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1035 = cat(_T_511, _out_prepend_T_1035) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11483 = or(out_prepend_1035, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11484 = bits(_out_T_11483, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1203 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1203 = orr(_out_rimask_T_1203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1203 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1203 = andr(_out_wimask_T_1203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1203 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1203 = orr(_out_romask_T_1203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1203 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1203 = andr(_out_womask_T_1203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1203 = and(out_rivalid_1[1081], out_rimask_1203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1203 = and(out_roready_1[1081], out_romask_1203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1203 = and(out_wivalid_1[1081], out_wimask_1203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1203 = and(out_woready_1[1081], out_womask_1203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11485 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11486 = and(out_f_rivalid_1203, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11487 = and(UInt<1>(0h1), out_f_roready_1203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11488 = eq(out_rimask_1203, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11489 = eq(out_wimask_1203, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11490 = eq(out_romask_1203, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11491 = eq(out_womask_1203, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1036 = or(_out_T_11484, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1036 = cat(_T_512, _out_prepend_T_1036) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11492 = or(out_prepend_1036, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11493 = bits(_out_T_11492, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1204 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1204 = orr(_out_rimask_T_1204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1204 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1204 = andr(_out_wimask_T_1204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1204 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1204 = orr(_out_romask_T_1204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1204 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1204 = andr(_out_womask_T_1204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1204 = and(out_rivalid_1[1082], out_rimask_1204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1204 = and(out_roready_1[1082], out_romask_1204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1204 = and(out_wivalid_1[1082], out_wimask_1204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1204 = and(out_woready_1[1082], out_womask_1204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11494 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11495 = and(out_f_rivalid_1204, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11496 = and(UInt<1>(0h1), out_f_roready_1204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11497 = eq(out_rimask_1204, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11498 = eq(out_wimask_1204, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11499 = eq(out_romask_1204, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11500 = eq(out_womask_1204, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1037 = or(_out_T_11493, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1037 = cat(_T_513, _out_prepend_T_1037) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11501 = or(out_prepend_1037, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11502 = bits(_out_T_11501, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1205 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1205 = orr(_out_rimask_T_1205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1205 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1205 = andr(_out_wimask_T_1205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1205 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1205 = orr(_out_romask_T_1205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1205 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1205 = andr(_out_womask_T_1205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1205 = and(out_rivalid_1[1083], out_rimask_1205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1205 = and(out_roready_1[1083], out_romask_1205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1205 = and(out_wivalid_1[1083], out_wimask_1205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1205 = and(out_woready_1[1083], out_womask_1205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11503 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11504 = and(out_f_rivalid_1205, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11505 = and(UInt<1>(0h1), out_f_roready_1205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11506 = eq(out_rimask_1205, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11507 = eq(out_wimask_1205, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11508 = eq(out_romask_1205, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11509 = eq(out_womask_1205, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11510 = or(_T_978, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11511 = bits(_out_T_11510, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1206 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1206 = orr(_out_rimask_T_1206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1206 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1206 = andr(_out_wimask_T_1206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1206 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1206 = orr(_out_romask_T_1206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1206 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1206 = andr(_out_womask_T_1206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1206 = and(out_rivalid_1[1084], out_rimask_1206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1206 = and(out_roready_1[1084], out_romask_1206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1206 = and(out_wivalid_1[1084], out_wimask_1206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1206 = and(out_woready_1[1084], out_womask_1206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11512 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11513 = and(out_f_rivalid_1206, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11514 = and(UInt<1>(0h1), out_f_roready_1206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11515 = eq(out_rimask_1206, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11516 = eq(out_wimask_1206, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11517 = eq(out_romask_1206, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11518 = eq(out_womask_1206, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1038 = or(_out_T_11511, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1038 = cat(_T_979, _out_prepend_T_1038) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11519 = or(out_prepend_1038, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11520 = bits(_out_T_11519, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1207 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1207 = orr(_out_rimask_T_1207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1207 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1207 = andr(_out_wimask_T_1207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1207 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1207 = orr(_out_romask_T_1207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1207 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1207 = andr(_out_womask_T_1207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1207 = and(out_rivalid_1[1085], out_rimask_1207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1207 = and(out_roready_1[1085], out_romask_1207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1207 = and(out_wivalid_1[1085], out_wimask_1207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1207 = and(out_woready_1[1085], out_womask_1207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11521 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11522 = and(out_f_rivalid_1207, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11523 = and(UInt<1>(0h1), out_f_roready_1207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11524 = eq(out_rimask_1207, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11525 = eq(out_wimask_1207, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11526 = eq(out_romask_1207, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11527 = eq(out_womask_1207, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1039 = or(_out_T_11520, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1039 = cat(_T_980, _out_prepend_T_1039) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11528 = or(out_prepend_1039, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11529 = bits(_out_T_11528, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1208 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1208 = orr(_out_rimask_T_1208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1208 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1208 = andr(_out_wimask_T_1208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1208 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1208 = orr(_out_romask_T_1208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1208 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1208 = andr(_out_womask_T_1208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1208 = and(out_rivalid_1[1086], out_rimask_1208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1208 = and(out_roready_1[1086], out_romask_1208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1208 = and(out_wivalid_1[1086], out_wimask_1208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1208 = and(out_woready_1[1086], out_womask_1208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11530 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11531 = and(out_f_rivalid_1208, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11532 = and(UInt<1>(0h1), out_f_roready_1208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11533 = eq(out_rimask_1208, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11534 = eq(out_wimask_1208, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11535 = eq(out_romask_1208, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11536 = eq(out_womask_1208, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1040 = or(_out_T_11529, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1040 = cat(_T_981, _out_prepend_T_1040) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11537 = or(out_prepend_1040, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11538 = bits(_out_T_11537, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1209 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1209 = orr(_out_rimask_T_1209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1209 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1209 = andr(_out_wimask_T_1209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1209 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1209 = orr(_out_romask_T_1209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1209 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1209 = andr(_out_womask_T_1209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1209 = and(out_rivalid_1[1087], out_rimask_1209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1209 = and(out_roready_1[1087], out_romask_1209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1209 = and(out_wivalid_1[1087], out_wimask_1209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1209 = and(out_woready_1[1087], out_womask_1209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11539 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11540 = and(out_f_rivalid_1209, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11541 = and(UInt<1>(0h1), out_f_roready_1209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11542 = eq(out_rimask_1209, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11543 = eq(out_wimask_1209, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11544 = eq(out_romask_1209, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11545 = eq(out_womask_1209, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1041 = or(_out_T_11538, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1041 = cat(_T_982, _out_prepend_T_1041) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11546 = or(out_prepend_1041, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11547 = bits(_out_T_11546, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1210 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1210 = orr(_out_rimask_T_1210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1210 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1210 = andr(_out_wimask_T_1210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1210 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1210 = orr(_out_romask_T_1210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1210 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1210 = andr(_out_womask_T_1210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1210 = and(out_rivalid_1[1088], out_rimask_1210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1210 = and(out_roready_1[1088], out_romask_1210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1210 = and(out_wivalid_1[1088], out_wimask_1210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1210 = and(out_woready_1[1088], out_womask_1210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11548 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11549 = and(out_f_rivalid_1210, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11550 = and(UInt<1>(0h1), out_f_roready_1210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11551 = eq(out_rimask_1210, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11552 = eq(out_wimask_1210, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11553 = eq(out_romask_1210, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11554 = eq(out_womask_1210, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1042 = or(_out_T_11547, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1042 = cat(_T_983, _out_prepend_T_1042) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11555 = or(out_prepend_1042, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11556 = bits(_out_T_11555, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1211 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1211 = orr(_out_rimask_T_1211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1211 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1211 = andr(_out_wimask_T_1211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1211 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1211 = orr(_out_romask_T_1211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1211 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1211 = andr(_out_womask_T_1211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1211 = and(out_rivalid_1[1089], out_rimask_1211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1211 = and(out_roready_1[1089], out_romask_1211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1211 = and(out_wivalid_1[1089], out_wimask_1211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1211 = and(out_woready_1[1089], out_womask_1211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11557 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11558 = and(out_f_rivalid_1211, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11559 = and(UInt<1>(0h1), out_f_roready_1211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11560 = eq(out_rimask_1211, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11561 = eq(out_wimask_1211, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11562 = eq(out_romask_1211, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11563 = eq(out_womask_1211, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1043 = or(_out_T_11556, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1043 = cat(_T_984, _out_prepend_T_1043) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11564 = or(out_prepend_1043, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11565 = bits(_out_T_11564, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1212 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1212 = orr(_out_rimask_T_1212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1212 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1212 = andr(_out_wimask_T_1212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1212 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1212 = orr(_out_romask_T_1212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1212 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1212 = andr(_out_womask_T_1212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1212 = and(out_rivalid_1[1090], out_rimask_1212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1212 = and(out_roready_1[1090], out_romask_1212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1212 = and(out_wivalid_1[1090], out_wimask_1212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1212 = and(out_woready_1[1090], out_womask_1212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11566 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11567 = and(out_f_rivalid_1212, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11568 = and(UInt<1>(0h1), out_f_roready_1212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11569 = eq(out_rimask_1212, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11570 = eq(out_wimask_1212, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11571 = eq(out_romask_1212, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11572 = eq(out_womask_1212, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1044 = or(_out_T_11565, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1044 = cat(_T_985, _out_prepend_T_1044) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11573 = or(out_prepend_1044, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11574 = bits(_out_T_11573, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1213 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1213 = orr(_out_rimask_T_1213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1213 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1213 = andr(_out_wimask_T_1213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1213 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1213 = orr(_out_romask_T_1213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1213 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1213 = andr(_out_womask_T_1213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1213 = and(out_rivalid_1[1091], out_rimask_1213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1213 = and(out_roready_1[1091], out_romask_1213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1213 = and(out_wivalid_1[1091], out_wimask_1213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1213 = and(out_woready_1[1091], out_womask_1213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11575 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11576 = and(out_f_rivalid_1213, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11577 = and(UInt<1>(0h1), out_f_roready_1213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11578 = eq(out_rimask_1213, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11579 = eq(out_wimask_1213, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11580 = eq(out_romask_1213, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11581 = eq(out_womask_1213, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11582 = or(_T_1330, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11583 = bits(_out_T_11582, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1214 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1214 = orr(_out_rimask_T_1214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1214 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1214 = andr(_out_wimask_T_1214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1214 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1214 = orr(_out_romask_T_1214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1214 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1214 = andr(_out_womask_T_1214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1214 = and(out_rivalid_1[1092], out_rimask_1214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1214 = and(out_roready_1[1092], out_romask_1214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1214 = and(out_wivalid_1[1092], out_wimask_1214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1214 = and(out_woready_1[1092], out_womask_1214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11584 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11585 = and(out_f_rivalid_1214, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11586 = and(UInt<1>(0h1), out_f_roready_1214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11587 = eq(out_rimask_1214, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11588 = eq(out_wimask_1214, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11589 = eq(out_romask_1214, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11590 = eq(out_womask_1214, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1045 = or(_out_T_11583, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1045 = cat(_T_1331, _out_prepend_T_1045) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11591 = or(out_prepend_1045, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11592 = bits(_out_T_11591, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1215 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1215 = orr(_out_rimask_T_1215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1215 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1215 = andr(_out_wimask_T_1215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1215 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1215 = orr(_out_romask_T_1215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1215 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1215 = andr(_out_womask_T_1215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1215 = and(out_rivalid_1[1093], out_rimask_1215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1215 = and(out_roready_1[1093], out_romask_1215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1215 = and(out_wivalid_1[1093], out_wimask_1215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1215 = and(out_woready_1[1093], out_womask_1215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11593 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11594 = and(out_f_rivalid_1215, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11595 = and(UInt<1>(0h1), out_f_roready_1215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11596 = eq(out_rimask_1215, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11597 = eq(out_wimask_1215, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11598 = eq(out_romask_1215, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11599 = eq(out_womask_1215, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1046 = or(_out_T_11592, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1046 = cat(_T_1332, _out_prepend_T_1046) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11600 = or(out_prepend_1046, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11601 = bits(_out_T_11600, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1216 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1216 = orr(_out_rimask_T_1216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1216 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1216 = andr(_out_wimask_T_1216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1216 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1216 = orr(_out_romask_T_1216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1216 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1216 = andr(_out_womask_T_1216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1216 = and(out_rivalid_1[1094], out_rimask_1216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1216 = and(out_roready_1[1094], out_romask_1216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1216 = and(out_wivalid_1[1094], out_wimask_1216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1216 = and(out_woready_1[1094], out_womask_1216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11602 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11603 = and(out_f_rivalid_1216, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11604 = and(UInt<1>(0h1), out_f_roready_1216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11605 = eq(out_rimask_1216, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11606 = eq(out_wimask_1216, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11607 = eq(out_romask_1216, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11608 = eq(out_womask_1216, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1047 = or(_out_T_11601, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1047 = cat(_T_1333, _out_prepend_T_1047) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11609 = or(out_prepend_1047, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11610 = bits(_out_T_11609, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1217 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1217 = orr(_out_rimask_T_1217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1217 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1217 = andr(_out_wimask_T_1217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1217 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1217 = orr(_out_romask_T_1217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1217 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1217 = andr(_out_womask_T_1217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1217 = and(out_rivalid_1[1095], out_rimask_1217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1217 = and(out_roready_1[1095], out_romask_1217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1217 = and(out_wivalid_1[1095], out_wimask_1217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1217 = and(out_woready_1[1095], out_womask_1217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11611 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11612 = and(out_f_rivalid_1217, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11613 = and(UInt<1>(0h1), out_f_roready_1217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11614 = eq(out_rimask_1217, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11615 = eq(out_wimask_1217, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11616 = eq(out_romask_1217, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11617 = eq(out_womask_1217, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1048 = or(_out_T_11610, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1048 = cat(_T_1334, _out_prepend_T_1048) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11618 = or(out_prepend_1048, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11619 = bits(_out_T_11618, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1218 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1218 = orr(_out_rimask_T_1218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1218 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1218 = andr(_out_wimask_T_1218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1218 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1218 = orr(_out_romask_T_1218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1218 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1218 = andr(_out_womask_T_1218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1218 = and(out_rivalid_1[1096], out_rimask_1218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1218 = and(out_roready_1[1096], out_romask_1218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1218 = and(out_wivalid_1[1096], out_wimask_1218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1218 = and(out_woready_1[1096], out_womask_1218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11620 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11621 = and(out_f_rivalid_1218, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11622 = and(UInt<1>(0h1), out_f_roready_1218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11623 = eq(out_rimask_1218, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11624 = eq(out_wimask_1218, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11625 = eq(out_romask_1218, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11626 = eq(out_womask_1218, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1049 = or(_out_T_11619, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1049 = cat(_T_1335, _out_prepend_T_1049) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11627 = or(out_prepend_1049, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11628 = bits(_out_T_11627, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1219 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1219 = orr(_out_rimask_T_1219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1219 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1219 = andr(_out_wimask_T_1219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1219 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1219 = orr(_out_romask_T_1219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1219 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1219 = andr(_out_womask_T_1219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1219 = and(out_rivalid_1[1097], out_rimask_1219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1219 = and(out_roready_1[1097], out_romask_1219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1219 = and(out_wivalid_1[1097], out_wimask_1219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1219 = and(out_woready_1[1097], out_womask_1219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11629 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11630 = and(out_f_rivalid_1219, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11631 = and(UInt<1>(0h1), out_f_roready_1219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11632 = eq(out_rimask_1219, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11633 = eq(out_wimask_1219, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11634 = eq(out_romask_1219, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11635 = eq(out_womask_1219, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1050 = or(_out_T_11628, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1050 = cat(_T_1336, _out_prepend_T_1050) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11636 = or(out_prepend_1050, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11637 = bits(_out_T_11636, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1220 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1220 = orr(_out_rimask_T_1220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1220 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1220 = andr(_out_wimask_T_1220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1220 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1220 = orr(_out_romask_T_1220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1220 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1220 = andr(_out_womask_T_1220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1220 = and(out_rivalid_1[1098], out_rimask_1220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1220 = and(out_roready_1[1098], out_romask_1220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1220 = and(out_wivalid_1[1098], out_wimask_1220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1220 = and(out_woready_1[1098], out_womask_1220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11638 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11639 = and(out_f_rivalid_1220, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11640 = and(UInt<1>(0h1), out_f_roready_1220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11641 = eq(out_rimask_1220, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11642 = eq(out_wimask_1220, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11643 = eq(out_romask_1220, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11644 = eq(out_womask_1220, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1051 = or(_out_T_11637, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1051 = cat(_T_1337, _out_prepend_T_1051) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11645 = or(out_prepend_1051, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11646 = bits(_out_T_11645, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1221 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1221 = orr(_out_rimask_T_1221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1221 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1221 = andr(_out_wimask_T_1221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1221 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1221 = orr(_out_romask_T_1221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1221 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1221 = andr(_out_womask_T_1221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1221 = and(out_rivalid_1[1099], out_rimask_1221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1221 = and(out_roready_1[1099], out_romask_1221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1221 = and(out_wivalid_1[1099], out_wimask_1221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1221 = and(out_woready_1[1099], out_womask_1221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11647 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11648 = and(out_f_rivalid_1221, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11649 = and(UInt<1>(0h1), out_f_roready_1221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11650 = eq(out_rimask_1221, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11651 = eq(out_wimask_1221, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11652 = eq(out_romask_1221, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11653 = eq(out_womask_1221, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11654 = or(_T_1354, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11655 = bits(_out_T_11654, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1222 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1222 = orr(_out_rimask_T_1222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1222 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1222 = andr(_out_wimask_T_1222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1222 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1222 = orr(_out_romask_T_1222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1222 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1222 = andr(_out_womask_T_1222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1222 = and(out_rivalid_1[1100], out_rimask_1222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1222 = and(out_roready_1[1100], out_romask_1222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1222 = and(out_wivalid_1[1100], out_wimask_1222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1222 = and(out_woready_1[1100], out_womask_1222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11656 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11657 = and(out_f_rivalid_1222, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11658 = and(UInt<1>(0h1), out_f_roready_1222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11659 = eq(out_rimask_1222, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11660 = eq(out_wimask_1222, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11661 = eq(out_romask_1222, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11662 = eq(out_womask_1222, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1052 = or(_out_T_11655, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1052 = cat(_T_1355, _out_prepend_T_1052) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11663 = or(out_prepend_1052, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11664 = bits(_out_T_11663, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1223 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1223 = orr(_out_rimask_T_1223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1223 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1223 = andr(_out_wimask_T_1223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1223 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1223 = orr(_out_romask_T_1223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1223 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1223 = andr(_out_womask_T_1223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1223 = and(out_rivalid_1[1101], out_rimask_1223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1223 = and(out_roready_1[1101], out_romask_1223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1223 = and(out_wivalid_1[1101], out_wimask_1223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1223 = and(out_woready_1[1101], out_womask_1223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11665 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11666 = and(out_f_rivalid_1223, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11667 = and(UInt<1>(0h1), out_f_roready_1223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11668 = eq(out_rimask_1223, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11669 = eq(out_wimask_1223, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11670 = eq(out_romask_1223, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11671 = eq(out_womask_1223, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1053 = or(_out_T_11664, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1053 = cat(_T_1356, _out_prepend_T_1053) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11672 = or(out_prepend_1053, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11673 = bits(_out_T_11672, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1224 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1224 = orr(_out_rimask_T_1224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1224 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1224 = andr(_out_wimask_T_1224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1224 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1224 = orr(_out_romask_T_1224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1224 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1224 = andr(_out_womask_T_1224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1224 = and(out_rivalid_1[1102], out_rimask_1224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1224 = and(out_roready_1[1102], out_romask_1224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1224 = and(out_wivalid_1[1102], out_wimask_1224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1224 = and(out_woready_1[1102], out_womask_1224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11674 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11675 = and(out_f_rivalid_1224, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11676 = and(UInt<1>(0h1), out_f_roready_1224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11677 = eq(out_rimask_1224, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11678 = eq(out_wimask_1224, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11679 = eq(out_romask_1224, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11680 = eq(out_womask_1224, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1054 = or(_out_T_11673, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1054 = cat(_T_1357, _out_prepend_T_1054) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11681 = or(out_prepend_1054, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11682 = bits(_out_T_11681, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1225 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1225 = orr(_out_rimask_T_1225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1225 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1225 = andr(_out_wimask_T_1225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1225 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1225 = orr(_out_romask_T_1225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1225 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1225 = andr(_out_womask_T_1225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1225 = and(out_rivalid_1[1103], out_rimask_1225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1225 = and(out_roready_1[1103], out_romask_1225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1225 = and(out_wivalid_1[1103], out_wimask_1225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1225 = and(out_woready_1[1103], out_womask_1225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11683 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11684 = and(out_f_rivalid_1225, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11685 = and(UInt<1>(0h1), out_f_roready_1225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11686 = eq(out_rimask_1225, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11687 = eq(out_wimask_1225, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11688 = eq(out_romask_1225, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11689 = eq(out_womask_1225, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1055 = or(_out_T_11682, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1055 = cat(_T_1358, _out_prepend_T_1055) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11690 = or(out_prepend_1055, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11691 = bits(_out_T_11690, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1226 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1226 = orr(_out_rimask_T_1226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1226 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1226 = andr(_out_wimask_T_1226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1226 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1226 = orr(_out_romask_T_1226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1226 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1226 = andr(_out_womask_T_1226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1226 = and(out_rivalid_1[1104], out_rimask_1226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1226 = and(out_roready_1[1104], out_romask_1226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1226 = and(out_wivalid_1[1104], out_wimask_1226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1226 = and(out_woready_1[1104], out_womask_1226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11692 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11693 = and(out_f_rivalid_1226, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11694 = and(UInt<1>(0h1), out_f_roready_1226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11695 = eq(out_rimask_1226, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11696 = eq(out_wimask_1226, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11697 = eq(out_romask_1226, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11698 = eq(out_womask_1226, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1056 = or(_out_T_11691, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1056 = cat(_T_1359, _out_prepend_T_1056) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11699 = or(out_prepend_1056, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11700 = bits(_out_T_11699, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1227 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1227 = orr(_out_rimask_T_1227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1227 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1227 = andr(_out_wimask_T_1227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1227 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1227 = orr(_out_romask_T_1227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1227 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1227 = andr(_out_womask_T_1227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1227 = and(out_rivalid_1[1105], out_rimask_1227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1227 = and(out_roready_1[1105], out_romask_1227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1227 = and(out_wivalid_1[1105], out_wimask_1227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1227 = and(out_woready_1[1105], out_womask_1227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11701 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11702 = and(out_f_rivalid_1227, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11703 = and(UInt<1>(0h1), out_f_roready_1227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11704 = eq(out_rimask_1227, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11705 = eq(out_wimask_1227, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11706 = eq(out_romask_1227, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11707 = eq(out_womask_1227, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1057 = or(_out_T_11700, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1057 = cat(_T_1360, _out_prepend_T_1057) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11708 = or(out_prepend_1057, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11709 = bits(_out_T_11708, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1228 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1228 = orr(_out_rimask_T_1228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1228 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1228 = andr(_out_wimask_T_1228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1228 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1228 = orr(_out_romask_T_1228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1228 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1228 = andr(_out_womask_T_1228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1228 = and(out_rivalid_1[1106], out_rimask_1228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1228 = and(out_roready_1[1106], out_romask_1228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1228 = and(out_wivalid_1[1106], out_wimask_1228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1228 = and(out_woready_1[1106], out_womask_1228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11710 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11711 = and(out_f_rivalid_1228, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11712 = and(UInt<1>(0h1), out_f_roready_1228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11713 = eq(out_rimask_1228, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11714 = eq(out_wimask_1228, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11715 = eq(out_romask_1228, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11716 = eq(out_womask_1228, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1058 = or(_out_T_11709, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1058 = cat(_T_1361, _out_prepend_T_1058) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11717 = or(out_prepend_1058, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11718 = bits(_out_T_11717, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1229 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1229 = orr(_out_rimask_T_1229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1229 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1229 = andr(_out_wimask_T_1229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1229 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1229 = orr(_out_romask_T_1229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1229 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1229 = andr(_out_womask_T_1229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1229 = and(out_rivalid_1[1107], out_rimask_1229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1229 = and(out_roready_1[1107], out_romask_1229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1229 = and(out_wivalid_1[1107], out_wimask_1229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1229 = and(out_woready_1[1107], out_womask_1229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11719 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11720 = and(out_f_rivalid_1229, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11721 = and(UInt<1>(0h1), out_f_roready_1229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11722 = eq(out_rimask_1229, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11723 = eq(out_wimask_1229, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11724 = eq(out_romask_1229, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11725 = eq(out_womask_1229, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11726 = or(_T_466, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11727 = bits(_out_T_11726, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1230 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1230 = orr(_out_rimask_T_1230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1230 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1230 = andr(_out_wimask_T_1230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1230 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1230 = orr(_out_romask_T_1230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1230 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1230 = andr(_out_womask_T_1230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1230 = and(out_rivalid_1[1108], out_rimask_1230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1230 = and(out_roready_1[1108], out_romask_1230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1230 = and(out_wivalid_1[1108], out_wimask_1230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1230 = and(out_woready_1[1108], out_womask_1230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11728 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11729 = and(out_f_rivalid_1230, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11730 = and(UInt<1>(0h1), out_f_roready_1230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11731 = eq(out_rimask_1230, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11732 = eq(out_wimask_1230, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11733 = eq(out_romask_1230, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11734 = eq(out_womask_1230, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1059 = or(_out_T_11727, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1059 = cat(_T_467, _out_prepend_T_1059) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11735 = or(out_prepend_1059, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11736 = bits(_out_T_11735, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1231 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1231 = orr(_out_rimask_T_1231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1231 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1231 = andr(_out_wimask_T_1231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1231 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1231 = orr(_out_romask_T_1231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1231 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1231 = andr(_out_womask_T_1231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1231 = and(out_rivalid_1[1109], out_rimask_1231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1231 = and(out_roready_1[1109], out_romask_1231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1231 = and(out_wivalid_1[1109], out_wimask_1231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1231 = and(out_woready_1[1109], out_womask_1231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11737 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11738 = and(out_f_rivalid_1231, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11739 = and(UInt<1>(0h1), out_f_roready_1231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11740 = eq(out_rimask_1231, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11741 = eq(out_wimask_1231, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11742 = eq(out_romask_1231, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11743 = eq(out_womask_1231, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1060 = or(_out_T_11736, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1060 = cat(_T_468, _out_prepend_T_1060) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11744 = or(out_prepend_1060, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11745 = bits(_out_T_11744, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1232 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1232 = orr(_out_rimask_T_1232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1232 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1232 = andr(_out_wimask_T_1232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1232 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1232 = orr(_out_romask_T_1232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1232 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1232 = andr(_out_womask_T_1232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1232 = and(out_rivalid_1[1110], out_rimask_1232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1232 = and(out_roready_1[1110], out_romask_1232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1232 = and(out_wivalid_1[1110], out_wimask_1232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1232 = and(out_woready_1[1110], out_womask_1232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11746 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11747 = and(out_f_rivalid_1232, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11748 = and(UInt<1>(0h1), out_f_roready_1232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11749 = eq(out_rimask_1232, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11750 = eq(out_wimask_1232, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11751 = eq(out_romask_1232, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11752 = eq(out_womask_1232, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1061 = or(_out_T_11745, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1061 = cat(_T_469, _out_prepend_T_1061) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11753 = or(out_prepend_1061, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11754 = bits(_out_T_11753, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1233 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1233 = orr(_out_rimask_T_1233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1233 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1233 = andr(_out_wimask_T_1233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1233 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1233 = orr(_out_romask_T_1233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1233 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1233 = andr(_out_womask_T_1233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1233 = and(out_rivalid_1[1111], out_rimask_1233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1233 = and(out_roready_1[1111], out_romask_1233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1233 = and(out_wivalid_1[1111], out_wimask_1233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1233 = and(out_woready_1[1111], out_womask_1233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11755 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11756 = and(out_f_rivalid_1233, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11757 = and(UInt<1>(0h1), out_f_roready_1233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11758 = eq(out_rimask_1233, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11759 = eq(out_wimask_1233, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11760 = eq(out_romask_1233, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11761 = eq(out_womask_1233, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1062 = or(_out_T_11754, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1062 = cat(_T_470, _out_prepend_T_1062) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11762 = or(out_prepend_1062, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11763 = bits(_out_T_11762, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1234 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1234 = orr(_out_rimask_T_1234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1234 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1234 = andr(_out_wimask_T_1234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1234 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1234 = orr(_out_romask_T_1234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1234 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1234 = andr(_out_womask_T_1234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1234 = and(out_rivalid_1[1112], out_rimask_1234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1234 = and(out_roready_1[1112], out_romask_1234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1234 = and(out_wivalid_1[1112], out_wimask_1234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1234 = and(out_woready_1[1112], out_womask_1234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11764 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11765 = and(out_f_rivalid_1234, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11766 = and(UInt<1>(0h1), out_f_roready_1234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11767 = eq(out_rimask_1234, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11768 = eq(out_wimask_1234, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11769 = eq(out_romask_1234, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11770 = eq(out_womask_1234, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1063 = or(_out_T_11763, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1063 = cat(_T_471, _out_prepend_T_1063) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11771 = or(out_prepend_1063, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11772 = bits(_out_T_11771, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1235 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1235 = orr(_out_rimask_T_1235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1235 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1235 = andr(_out_wimask_T_1235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1235 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1235 = orr(_out_romask_T_1235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1235 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1235 = andr(_out_womask_T_1235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1235 = and(out_rivalid_1[1113], out_rimask_1235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1235 = and(out_roready_1[1113], out_romask_1235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1235 = and(out_wivalid_1[1113], out_wimask_1235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1235 = and(out_woready_1[1113], out_womask_1235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11773 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11774 = and(out_f_rivalid_1235, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11775 = and(UInt<1>(0h1), out_f_roready_1235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11776 = eq(out_rimask_1235, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11777 = eq(out_wimask_1235, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11778 = eq(out_romask_1235, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11779 = eq(out_womask_1235, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1064 = or(_out_T_11772, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1064 = cat(_T_472, _out_prepend_T_1064) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11780 = or(out_prepend_1064, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11781 = bits(_out_T_11780, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1236 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1236 = orr(_out_rimask_T_1236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1236 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1236 = andr(_out_wimask_T_1236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1236 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1236 = orr(_out_romask_T_1236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1236 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1236 = andr(_out_womask_T_1236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1236 = and(out_rivalid_1[1114], out_rimask_1236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1236 = and(out_roready_1[1114], out_romask_1236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1236 = and(out_wivalid_1[1114], out_wimask_1236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1236 = and(out_woready_1[1114], out_womask_1236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11782 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11783 = and(out_f_rivalid_1236, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11784 = and(UInt<1>(0h1), out_f_roready_1236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11785 = eq(out_rimask_1236, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11786 = eq(out_wimask_1236, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11787 = eq(out_romask_1236, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11788 = eq(out_womask_1236, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1065 = or(_out_T_11781, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1065 = cat(_T_473, _out_prepend_T_1065) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11789 = or(out_prepend_1065, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11790 = bits(_out_T_11789, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1237 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1237 = orr(_out_rimask_T_1237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1237 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1237 = andr(_out_wimask_T_1237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1237 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1237 = orr(_out_romask_T_1237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1237 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1237 = andr(_out_womask_T_1237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1237 = and(out_rivalid_1[1115], out_rimask_1237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1237 = and(out_roready_1[1115], out_romask_1237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1237 = and(out_wivalid_1[1115], out_wimask_1237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1237 = and(out_woready_1[1115], out_womask_1237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11791 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11792 = and(out_f_rivalid_1237, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11793 = and(UInt<1>(0h1), out_f_roready_1237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11794 = eq(out_rimask_1237, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11795 = eq(out_wimask_1237, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11796 = eq(out_romask_1237, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11797 = eq(out_womask_1237, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11798 = or(_T_842, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11799 = bits(_out_T_11798, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1238 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1238 = orr(_out_rimask_T_1238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1238 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1238 = andr(_out_wimask_T_1238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1238 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1238 = orr(_out_romask_T_1238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1238 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1238 = andr(_out_womask_T_1238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1238 = and(out_rivalid_1[1116], out_rimask_1238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1238 = and(out_roready_1[1116], out_romask_1238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1238 = and(out_wivalid_1[1116], out_wimask_1238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1238 = and(out_woready_1[1116], out_womask_1238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11800 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11801 = and(out_f_rivalid_1238, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11802 = and(UInt<1>(0h1), out_f_roready_1238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11803 = eq(out_rimask_1238, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11804 = eq(out_wimask_1238, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11805 = eq(out_romask_1238, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11806 = eq(out_womask_1238, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1066 = or(_out_T_11799, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1066 = cat(_T_843, _out_prepend_T_1066) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11807 = or(out_prepend_1066, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11808 = bits(_out_T_11807, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1239 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1239 = orr(_out_rimask_T_1239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1239 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1239 = andr(_out_wimask_T_1239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1239 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1239 = orr(_out_romask_T_1239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1239 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1239 = andr(_out_womask_T_1239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1239 = and(out_rivalid_1[1117], out_rimask_1239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1239 = and(out_roready_1[1117], out_romask_1239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1239 = and(out_wivalid_1[1117], out_wimask_1239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1239 = and(out_woready_1[1117], out_womask_1239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11809 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11810 = and(out_f_rivalid_1239, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11811 = and(UInt<1>(0h1), out_f_roready_1239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11812 = eq(out_rimask_1239, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11813 = eq(out_wimask_1239, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11814 = eq(out_romask_1239, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11815 = eq(out_womask_1239, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1067 = or(_out_T_11808, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1067 = cat(_T_844, _out_prepend_T_1067) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11816 = or(out_prepend_1067, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11817 = bits(_out_T_11816, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1240 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1240 = orr(_out_rimask_T_1240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1240 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1240 = andr(_out_wimask_T_1240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1240 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1240 = orr(_out_romask_T_1240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1240 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1240 = andr(_out_womask_T_1240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1240 = and(out_rivalid_1[1118], out_rimask_1240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1240 = and(out_roready_1[1118], out_romask_1240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1240 = and(out_wivalid_1[1118], out_wimask_1240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1240 = and(out_woready_1[1118], out_womask_1240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11818 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11819 = and(out_f_rivalid_1240, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11820 = and(UInt<1>(0h1), out_f_roready_1240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11821 = eq(out_rimask_1240, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11822 = eq(out_wimask_1240, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11823 = eq(out_romask_1240, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11824 = eq(out_womask_1240, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1068 = or(_out_T_11817, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1068 = cat(_T_845, _out_prepend_T_1068) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11825 = or(out_prepend_1068, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11826 = bits(_out_T_11825, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1241 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1241 = orr(_out_rimask_T_1241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1241 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1241 = andr(_out_wimask_T_1241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1241 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1241 = orr(_out_romask_T_1241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1241 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1241 = andr(_out_womask_T_1241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1241 = and(out_rivalid_1[1119], out_rimask_1241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1241 = and(out_roready_1[1119], out_romask_1241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1241 = and(out_wivalid_1[1119], out_wimask_1241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1241 = and(out_woready_1[1119], out_womask_1241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11827 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11828 = and(out_f_rivalid_1241, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11829 = and(UInt<1>(0h1), out_f_roready_1241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11830 = eq(out_rimask_1241, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11831 = eq(out_wimask_1241, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11832 = eq(out_romask_1241, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11833 = eq(out_womask_1241, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1069 = or(_out_T_11826, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1069 = cat(_T_846, _out_prepend_T_1069) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11834 = or(out_prepend_1069, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11835 = bits(_out_T_11834, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1242 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1242 = orr(_out_rimask_T_1242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1242 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1242 = andr(_out_wimask_T_1242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1242 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1242 = orr(_out_romask_T_1242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1242 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1242 = andr(_out_womask_T_1242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1242 = and(out_rivalid_1[1120], out_rimask_1242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1242 = and(out_roready_1[1120], out_romask_1242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1242 = and(out_wivalid_1[1120], out_wimask_1242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1242 = and(out_woready_1[1120], out_womask_1242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11836 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11837 = and(out_f_rivalid_1242, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11838 = and(UInt<1>(0h1), out_f_roready_1242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11839 = eq(out_rimask_1242, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11840 = eq(out_wimask_1242, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11841 = eq(out_romask_1242, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11842 = eq(out_womask_1242, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1070 = or(_out_T_11835, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1070 = cat(_T_847, _out_prepend_T_1070) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11843 = or(out_prepend_1070, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11844 = bits(_out_T_11843, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1243 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1243 = orr(_out_rimask_T_1243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1243 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1243 = andr(_out_wimask_T_1243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1243 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1243 = orr(_out_romask_T_1243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1243 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1243 = andr(_out_womask_T_1243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1243 = and(out_rivalid_1[1121], out_rimask_1243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1243 = and(out_roready_1[1121], out_romask_1243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1243 = and(out_wivalid_1[1121], out_wimask_1243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1243 = and(out_woready_1[1121], out_womask_1243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11845 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11846 = and(out_f_rivalid_1243, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11847 = and(UInt<1>(0h1), out_f_roready_1243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11848 = eq(out_rimask_1243, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11849 = eq(out_wimask_1243, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11850 = eq(out_romask_1243, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11851 = eq(out_womask_1243, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1071 = or(_out_T_11844, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1071 = cat(_T_848, _out_prepend_T_1071) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11852 = or(out_prepend_1071, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11853 = bits(_out_T_11852, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1244 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1244 = orr(_out_rimask_T_1244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1244 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1244 = andr(_out_wimask_T_1244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1244 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1244 = orr(_out_romask_T_1244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1244 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1244 = andr(_out_womask_T_1244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1244 = and(out_rivalid_1[1122], out_rimask_1244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1244 = and(out_roready_1[1122], out_romask_1244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1244 = and(out_wivalid_1[1122], out_wimask_1244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1244 = and(out_woready_1[1122], out_womask_1244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11854 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11855 = and(out_f_rivalid_1244, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11856 = and(UInt<1>(0h1), out_f_roready_1244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11857 = eq(out_rimask_1244, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11858 = eq(out_wimask_1244, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11859 = eq(out_romask_1244, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11860 = eq(out_womask_1244, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1072 = or(_out_T_11853, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1072 = cat(_T_849, _out_prepend_T_1072) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11861 = or(out_prepend_1072, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11862 = bits(_out_T_11861, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1245 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1245 = orr(_out_rimask_T_1245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1245 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1245 = andr(_out_wimask_T_1245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1245 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1245 = orr(_out_romask_T_1245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1245 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1245 = andr(_out_womask_T_1245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1245 = and(out_rivalid_1[1123], out_rimask_1245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1245 = and(out_roready_1[1123], out_romask_1245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1245 = and(out_wivalid_1[1123], out_wimask_1245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1245 = and(out_woready_1[1123], out_womask_1245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11863 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11864 = and(out_f_rivalid_1245, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11865 = and(UInt<1>(0h1), out_f_roready_1245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11866 = eq(out_rimask_1245, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11867 = eq(out_wimask_1245, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11868 = eq(out_romask_1245, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11869 = eq(out_womask_1245, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11870 = or(_T_722, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11871 = bits(_out_T_11870, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1246 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1246 = orr(_out_rimask_T_1246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1246 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1246 = andr(_out_wimask_T_1246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1246 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1246 = orr(_out_romask_T_1246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1246 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1246 = andr(_out_womask_T_1246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1246 = and(out_rivalid_1[1124], out_rimask_1246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1246 = and(out_roready_1[1124], out_romask_1246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1246 = and(out_wivalid_1[1124], out_wimask_1246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1246 = and(out_woready_1[1124], out_womask_1246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11872 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11873 = and(out_f_rivalid_1246, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11874 = and(UInt<1>(0h1), out_f_roready_1246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11875 = eq(out_rimask_1246, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11876 = eq(out_wimask_1246, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11877 = eq(out_romask_1246, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11878 = eq(out_womask_1246, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1073 = or(_out_T_11871, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1073 = cat(_T_723, _out_prepend_T_1073) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11879 = or(out_prepend_1073, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11880 = bits(_out_T_11879, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1247 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1247 = orr(_out_rimask_T_1247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1247 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1247 = andr(_out_wimask_T_1247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1247 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1247 = orr(_out_romask_T_1247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1247 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1247 = andr(_out_womask_T_1247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1247 = and(out_rivalid_1[1125], out_rimask_1247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1247 = and(out_roready_1[1125], out_romask_1247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1247 = and(out_wivalid_1[1125], out_wimask_1247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1247 = and(out_woready_1[1125], out_womask_1247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11881 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11882 = and(out_f_rivalid_1247, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11883 = and(UInt<1>(0h1), out_f_roready_1247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11884 = eq(out_rimask_1247, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11885 = eq(out_wimask_1247, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11886 = eq(out_romask_1247, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11887 = eq(out_womask_1247, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1074 = or(_out_T_11880, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1074 = cat(_T_724, _out_prepend_T_1074) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11888 = or(out_prepend_1074, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11889 = bits(_out_T_11888, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1248 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1248 = orr(_out_rimask_T_1248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1248 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1248 = andr(_out_wimask_T_1248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1248 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1248 = orr(_out_romask_T_1248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1248 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1248 = andr(_out_womask_T_1248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1248 = and(out_rivalid_1[1126], out_rimask_1248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1248 = and(out_roready_1[1126], out_romask_1248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1248 = and(out_wivalid_1[1126], out_wimask_1248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1248 = and(out_woready_1[1126], out_womask_1248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11890 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11891 = and(out_f_rivalid_1248, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11892 = and(UInt<1>(0h1), out_f_roready_1248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11893 = eq(out_rimask_1248, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11894 = eq(out_wimask_1248, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11895 = eq(out_romask_1248, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11896 = eq(out_womask_1248, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1075 = or(_out_T_11889, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1075 = cat(_T_725, _out_prepend_T_1075) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11897 = or(out_prepend_1075, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11898 = bits(_out_T_11897, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1249 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1249 = orr(_out_rimask_T_1249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1249 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1249 = andr(_out_wimask_T_1249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1249 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1249 = orr(_out_romask_T_1249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1249 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1249 = andr(_out_womask_T_1249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1249 = and(out_rivalid_1[1127], out_rimask_1249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1249 = and(out_roready_1[1127], out_romask_1249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1249 = and(out_wivalid_1[1127], out_wimask_1249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1249 = and(out_woready_1[1127], out_womask_1249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11899 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11900 = and(out_f_rivalid_1249, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11901 = and(UInt<1>(0h1), out_f_roready_1249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11902 = eq(out_rimask_1249, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11903 = eq(out_wimask_1249, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11904 = eq(out_romask_1249, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11905 = eq(out_womask_1249, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1076 = or(_out_T_11898, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1076 = cat(_T_726, _out_prepend_T_1076) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11906 = or(out_prepend_1076, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11907 = bits(_out_T_11906, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1250 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1250 = orr(_out_rimask_T_1250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1250 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1250 = andr(_out_wimask_T_1250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1250 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1250 = orr(_out_romask_T_1250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1250 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1250 = andr(_out_womask_T_1250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1250 = and(out_rivalid_1[1128], out_rimask_1250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1250 = and(out_roready_1[1128], out_romask_1250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1250 = and(out_wivalid_1[1128], out_wimask_1250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1250 = and(out_woready_1[1128], out_womask_1250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11908 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11909 = and(out_f_rivalid_1250, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11910 = and(UInt<1>(0h1), out_f_roready_1250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11911 = eq(out_rimask_1250, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11912 = eq(out_wimask_1250, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11913 = eq(out_romask_1250, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11914 = eq(out_womask_1250, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1077 = or(_out_T_11907, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1077 = cat(_T_727, _out_prepend_T_1077) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11915 = or(out_prepend_1077, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11916 = bits(_out_T_11915, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1251 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1251 = orr(_out_rimask_T_1251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1251 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1251 = andr(_out_wimask_T_1251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1251 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1251 = orr(_out_romask_T_1251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1251 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1251 = andr(_out_womask_T_1251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1251 = and(out_rivalid_1[1129], out_rimask_1251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1251 = and(out_roready_1[1129], out_romask_1251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1251 = and(out_wivalid_1[1129], out_wimask_1251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1251 = and(out_woready_1[1129], out_womask_1251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11917 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11918 = and(out_f_rivalid_1251, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11919 = and(UInt<1>(0h1), out_f_roready_1251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11920 = eq(out_rimask_1251, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11921 = eq(out_wimask_1251, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11922 = eq(out_romask_1251, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11923 = eq(out_womask_1251, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1078 = or(_out_T_11916, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1078 = cat(_T_728, _out_prepend_T_1078) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11924 = or(out_prepend_1078, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11925 = bits(_out_T_11924, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1252 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1252 = orr(_out_rimask_T_1252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1252 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1252 = andr(_out_wimask_T_1252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1252 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1252 = orr(_out_romask_T_1252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1252 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1252 = andr(_out_womask_T_1252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1252 = and(out_rivalid_1[1130], out_rimask_1252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1252 = and(out_roready_1[1130], out_romask_1252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1252 = and(out_wivalid_1[1130], out_wimask_1252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1252 = and(out_woready_1[1130], out_womask_1252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11926 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11927 = and(out_f_rivalid_1252, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11928 = and(UInt<1>(0h1), out_f_roready_1252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11929 = eq(out_rimask_1252, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11930 = eq(out_wimask_1252, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11931 = eq(out_romask_1252, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11932 = eq(out_womask_1252, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1079 = or(_out_T_11925, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1079 = cat(_T_729, _out_prepend_T_1079) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11933 = or(out_prepend_1079, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11934 = bits(_out_T_11933, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1253 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1253 = orr(_out_rimask_T_1253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1253 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1253 = andr(_out_wimask_T_1253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1253 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1253 = orr(_out_romask_T_1253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1253 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1253 = andr(_out_womask_T_1253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1253 = and(out_rivalid_1[1131], out_rimask_1253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1253 = and(out_roready_1[1131], out_romask_1253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1253 = and(out_wivalid_1[1131], out_wimask_1253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1253 = and(out_woready_1[1131], out_womask_1253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11935 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11936 = and(out_f_rivalid_1253, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11937 = and(UInt<1>(0h1), out_f_roready_1253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11938 = eq(out_rimask_1253, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11939 = eq(out_wimask_1253, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11940 = eq(out_romask_1253, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11941 = eq(out_womask_1253, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11942 = or(_T_1018, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11943 = bits(_out_T_11942, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1254 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1254 = orr(_out_rimask_T_1254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1254 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1254 = andr(_out_wimask_T_1254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1254 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1254 = orr(_out_romask_T_1254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1254 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1254 = andr(_out_womask_T_1254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1254 = and(out_rivalid_1[1132], out_rimask_1254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1254 = and(out_roready_1[1132], out_romask_1254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1254 = and(out_wivalid_1[1132], out_wimask_1254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1254 = and(out_woready_1[1132], out_womask_1254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11944 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11945 = and(out_f_rivalid_1254, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11946 = and(UInt<1>(0h1), out_f_roready_1254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11947 = eq(out_rimask_1254, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11948 = eq(out_wimask_1254, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11949 = eq(out_romask_1254, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11950 = eq(out_womask_1254, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1080 = or(_out_T_11943, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1080 = cat(_T_1019, _out_prepend_T_1080) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11951 = or(out_prepend_1080, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11952 = bits(_out_T_11951, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1255 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1255 = orr(_out_rimask_T_1255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1255 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1255 = andr(_out_wimask_T_1255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1255 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1255 = orr(_out_romask_T_1255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1255 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1255 = andr(_out_womask_T_1255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1255 = and(out_rivalid_1[1133], out_rimask_1255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1255 = and(out_roready_1[1133], out_romask_1255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1255 = and(out_wivalid_1[1133], out_wimask_1255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1255 = and(out_woready_1[1133], out_womask_1255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11953 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11954 = and(out_f_rivalid_1255, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11955 = and(UInt<1>(0h1), out_f_roready_1255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11956 = eq(out_rimask_1255, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11957 = eq(out_wimask_1255, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11958 = eq(out_romask_1255, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11959 = eq(out_womask_1255, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1081 = or(_out_T_11952, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1081 = cat(_T_1020, _out_prepend_T_1081) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11960 = or(out_prepend_1081, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11961 = bits(_out_T_11960, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1256 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1256 = orr(_out_rimask_T_1256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1256 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1256 = andr(_out_wimask_T_1256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1256 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1256 = orr(_out_romask_T_1256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1256 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1256 = andr(_out_womask_T_1256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1256 = and(out_rivalid_1[1134], out_rimask_1256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1256 = and(out_roready_1[1134], out_romask_1256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1256 = and(out_wivalid_1[1134], out_wimask_1256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1256 = and(out_woready_1[1134], out_womask_1256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11962 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11963 = and(out_f_rivalid_1256, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11964 = and(UInt<1>(0h1), out_f_roready_1256) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11965 = eq(out_rimask_1256, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11966 = eq(out_wimask_1256, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11967 = eq(out_romask_1256, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11968 = eq(out_womask_1256, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1082 = or(_out_T_11961, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1082 = cat(_T_1021, _out_prepend_T_1082) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11969 = or(out_prepend_1082, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11970 = bits(_out_T_11969, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1257 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1257 = orr(_out_rimask_T_1257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1257 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1257 = andr(_out_wimask_T_1257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1257 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1257 = orr(_out_romask_T_1257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1257 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1257 = andr(_out_womask_T_1257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1257 = and(out_rivalid_1[1135], out_rimask_1257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1257 = and(out_roready_1[1135], out_romask_1257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1257 = and(out_wivalid_1[1135], out_wimask_1257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1257 = and(out_woready_1[1135], out_womask_1257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11971 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11972 = and(out_f_rivalid_1257, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11973 = and(UInt<1>(0h1), out_f_roready_1257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11974 = eq(out_rimask_1257, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11975 = eq(out_wimask_1257, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11976 = eq(out_romask_1257, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11977 = eq(out_womask_1257, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1083 = or(_out_T_11970, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1083 = cat(_T_1022, _out_prepend_T_1083) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11978 = or(out_prepend_1083, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11979 = bits(_out_T_11978, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1258 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1258 = orr(_out_rimask_T_1258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1258 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1258 = andr(_out_wimask_T_1258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1258 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1258 = orr(_out_romask_T_1258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1258 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1258 = andr(_out_womask_T_1258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1258 = and(out_rivalid_1[1136], out_rimask_1258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1258 = and(out_roready_1[1136], out_romask_1258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1258 = and(out_wivalid_1[1136], out_wimask_1258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1258 = and(out_woready_1[1136], out_womask_1258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11980 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11981 = and(out_f_rivalid_1258, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11982 = and(UInt<1>(0h1), out_f_roready_1258) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11983 = eq(out_rimask_1258, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11984 = eq(out_wimask_1258, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11985 = eq(out_romask_1258, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11986 = eq(out_womask_1258, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1084 = or(_out_T_11979, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1084 = cat(_T_1023, _out_prepend_T_1084) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11987 = or(out_prepend_1084, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11988 = bits(_out_T_11987, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1259 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1259 = orr(_out_rimask_T_1259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1259 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1259 = andr(_out_wimask_T_1259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1259 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1259 = orr(_out_romask_T_1259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1259 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1259 = andr(_out_womask_T_1259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1259 = and(out_rivalid_1[1137], out_rimask_1259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1259 = and(out_roready_1[1137], out_romask_1259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1259 = and(out_wivalid_1[1137], out_wimask_1259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1259 = and(out_woready_1[1137], out_womask_1259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11989 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11990 = and(out_f_rivalid_1259, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11991 = and(UInt<1>(0h1), out_f_roready_1259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11992 = eq(out_rimask_1259, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11993 = eq(out_wimask_1259, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11994 = eq(out_romask_1259, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11995 = eq(out_womask_1259, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1085 = or(_out_T_11988, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1085 = cat(_T_1024, _out_prepend_T_1085) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11996 = or(out_prepend_1085, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11997 = bits(_out_T_11996, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1260 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1260 = orr(_out_rimask_T_1260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1260 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1260 = andr(_out_wimask_T_1260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1260 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1260 = orr(_out_romask_T_1260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1260 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1260 = andr(_out_womask_T_1260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1260 = and(out_rivalid_1[1138], out_rimask_1260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1260 = and(out_roready_1[1138], out_romask_1260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1260 = and(out_wivalid_1[1138], out_wimask_1260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1260 = and(out_woready_1[1138], out_womask_1260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11998 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11999 = and(out_f_rivalid_1260, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12000 = and(UInt<1>(0h1), out_f_roready_1260) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12001 = eq(out_rimask_1260, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12002 = eq(out_wimask_1260, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12003 = eq(out_romask_1260, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12004 = eq(out_womask_1260, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1086 = or(_out_T_11997, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1086 = cat(_T_1025, _out_prepend_T_1086) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12005 = or(out_prepend_1086, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12006 = bits(_out_T_12005, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1261 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1261 = orr(_out_rimask_T_1261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1261 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1261 = andr(_out_wimask_T_1261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1261 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1261 = orr(_out_romask_T_1261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1261 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1261 = andr(_out_womask_T_1261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1261 = and(out_rivalid_1[1139], out_rimask_1261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1261 = and(out_roready_1[1139], out_romask_1261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1261 = and(out_wivalid_1[1139], out_wimask_1261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1261 = and(out_woready_1[1139], out_womask_1261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12007 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1261 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[56], _out_T_12007 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_12008 = and(out_f_rivalid_1261, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12009 = and(UInt<1>(0h1), out_f_roready_1261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12010 = and(out_f_wivalid_1261, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12011 = and(UInt<1>(0h1), out_f_woready_1261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12012 = eq(out_rimask_1261, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12013 = eq(out_wimask_1261, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12014 = eq(out_romask_1261, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12015 = eq(out_womask_1261, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12016 = or(programBufferMem[56], UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12017 = bits(_out_T_12016, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1262 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1262 = orr(_out_rimask_T_1262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1262 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1262 = andr(_out_wimask_T_1262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1262 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1262 = orr(_out_romask_T_1262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1262 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1262 = andr(_out_womask_T_1262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1262 = and(out_rivalid_1[1140], out_rimask_1262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1262 = and(out_roready_1[1140], out_romask_1262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1262 = and(out_wivalid_1[1140], out_wimask_1262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1262 = and(out_woready_1[1140], out_womask_1262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12018 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1262 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[57], _out_T_12018 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_12019 = and(out_f_rivalid_1262, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12020 = and(UInt<1>(0h1), out_f_roready_1262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12021 = and(out_f_wivalid_1262, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12022 = and(UInt<1>(0h1), out_f_woready_1262) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12023 = eq(out_rimask_1262, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12024 = eq(out_wimask_1262, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12025 = eq(out_romask_1262, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12026 = eq(out_womask_1262, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1087 = or(_out_T_12017, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1087 = cat(programBufferMem[57], _out_prepend_T_1087) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12027 = or(out_prepend_1087, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12028 = bits(_out_T_12027, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1263 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1263 = orr(_out_rimask_T_1263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1263 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1263 = andr(_out_wimask_T_1263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1263 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1263 = orr(_out_romask_T_1263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1263 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1263 = andr(_out_womask_T_1263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1263 = and(out_rivalid_1[1141], out_rimask_1263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1263 = and(out_roready_1[1141], out_romask_1263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1263 = and(out_wivalid_1[1141], out_wimask_1263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1263 = and(out_woready_1[1141], out_womask_1263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12029 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1263 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[58], _out_T_12029 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_12030 = and(out_f_rivalid_1263, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12031 = and(UInt<1>(0h1), out_f_roready_1263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12032 = and(out_f_wivalid_1263, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12033 = and(UInt<1>(0h1), out_f_woready_1263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12034 = eq(out_rimask_1263, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12035 = eq(out_wimask_1263, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12036 = eq(out_romask_1263, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12037 = eq(out_womask_1263, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1088 = or(_out_T_12028, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1088 = cat(programBufferMem[58], _out_prepend_T_1088) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12038 = or(out_prepend_1088, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12039 = bits(_out_T_12038, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1264 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1264 = orr(_out_rimask_T_1264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1264 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1264 = andr(_out_wimask_T_1264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1264 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1264 = orr(_out_romask_T_1264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1264 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1264 = andr(_out_womask_T_1264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1264 = and(out_rivalid_1[1142], out_rimask_1264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1264 = and(out_roready_1[1142], out_romask_1264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1264 = and(out_wivalid_1[1142], out_wimask_1264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1264 = and(out_woready_1[1142], out_womask_1264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12040 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1264 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[59], _out_T_12040 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_12041 = and(out_f_rivalid_1264, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12042 = and(UInt<1>(0h1), out_f_roready_1264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12043 = and(out_f_wivalid_1264, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12044 = and(UInt<1>(0h1), out_f_woready_1264) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12045 = eq(out_rimask_1264, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12046 = eq(out_wimask_1264, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12047 = eq(out_romask_1264, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12048 = eq(out_womask_1264, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1089 = or(_out_T_12039, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1089 = cat(programBufferMem[59], _out_prepend_T_1089) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12049 = or(out_prepend_1089, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12050 = bits(_out_T_12049, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1265 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1265 = orr(_out_rimask_T_1265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1265 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1265 = andr(_out_wimask_T_1265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1265 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1265 = orr(_out_romask_T_1265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1265 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1265 = andr(_out_womask_T_1265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1265 = and(out_rivalid_1[1143], out_rimask_1265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1265 = and(out_roready_1[1143], out_romask_1265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1265 = and(out_wivalid_1[1143], out_wimask_1265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1265 = and(out_woready_1[1143], out_womask_1265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12051 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1265 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[60], _out_T_12051 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_12052 = and(out_f_rivalid_1265, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12053 = and(UInt<1>(0h1), out_f_roready_1265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12054 = and(out_f_wivalid_1265, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12055 = and(UInt<1>(0h1), out_f_woready_1265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12056 = eq(out_rimask_1265, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12057 = eq(out_wimask_1265, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12058 = eq(out_romask_1265, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12059 = eq(out_womask_1265, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1090 = or(_out_T_12050, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1090 = cat(programBufferMem[60], _out_prepend_T_1090) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12060 = or(out_prepend_1090, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12061 = bits(_out_T_12060, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1266 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1266 = orr(_out_rimask_T_1266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1266 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1266 = andr(_out_wimask_T_1266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1266 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1266 = orr(_out_romask_T_1266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1266 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1266 = andr(_out_womask_T_1266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1266 = and(out_rivalid_1[1144], out_rimask_1266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1266 = and(out_roready_1[1144], out_romask_1266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1266 = and(out_wivalid_1[1144], out_wimask_1266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1266 = and(out_woready_1[1144], out_womask_1266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12062 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1266 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[61], _out_T_12062 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_12063 = and(out_f_rivalid_1266, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12064 = and(UInt<1>(0h1), out_f_roready_1266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12065 = and(out_f_wivalid_1266, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12066 = and(UInt<1>(0h1), out_f_woready_1266) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12067 = eq(out_rimask_1266, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12068 = eq(out_wimask_1266, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12069 = eq(out_romask_1266, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12070 = eq(out_womask_1266, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1091 = or(_out_T_12061, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1091 = cat(programBufferMem[61], _out_prepend_T_1091) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12071 = or(out_prepend_1091, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12072 = bits(_out_T_12071, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1267 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1267 = orr(_out_rimask_T_1267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1267 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1267 = andr(_out_wimask_T_1267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1267 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1267 = orr(_out_romask_T_1267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1267 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1267 = andr(_out_womask_T_1267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1267 = and(out_rivalid_1[1145], out_rimask_1267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1267 = and(out_roready_1[1145], out_romask_1267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1267 = and(out_wivalid_1[1145], out_wimask_1267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1267 = and(out_woready_1[1145], out_womask_1267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12073 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1267 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[62], _out_T_12073 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_12074 = and(out_f_rivalid_1267, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12075 = and(UInt<1>(0h1), out_f_roready_1267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12076 = and(out_f_wivalid_1267, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12077 = and(UInt<1>(0h1), out_f_woready_1267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12078 = eq(out_rimask_1267, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12079 = eq(out_wimask_1267, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12080 = eq(out_romask_1267, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12081 = eq(out_womask_1267, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1092 = or(_out_T_12072, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1092 = cat(programBufferMem[62], _out_prepend_T_1092) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12082 = or(out_prepend_1092, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12083 = bits(_out_T_12082, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1268 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1268 = orr(_out_rimask_T_1268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1268 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1268 = andr(_out_wimask_T_1268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1268 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1268 = orr(_out_romask_T_1268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1268 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1268 = andr(_out_womask_T_1268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1268 = and(out_rivalid_1[1146], out_rimask_1268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1268 = and(out_roready_1[1146], out_romask_1268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1268 = and(out_wivalid_1[1146], out_wimask_1268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1268 = and(out_woready_1[1146], out_womask_1268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12084 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_1268 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect programBufferMem[63], _out_T_12084 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_12085 = and(out_f_rivalid_1268, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12086 = and(UInt<1>(0h1), out_f_roready_1268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12087 = and(out_f_wivalid_1268, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12088 = and(UInt<1>(0h1), out_f_woready_1268) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12089 = eq(out_rimask_1268, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12090 = eq(out_wimask_1268, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12091 = eq(out_romask_1268, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12092 = eq(out_womask_1268, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1093 = or(_out_T_12083, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1093 = cat(programBufferMem[63], _out_prepend_T_1093) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12093 = or(out_prepend_1093, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12094 = bits(_out_T_12093, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1269 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1269 = orr(_out_rimask_T_1269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1269 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1269 = andr(_out_wimask_T_1269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1269 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1269 = orr(_out_romask_T_1269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1269 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1269 = andr(_out_womask_T_1269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1269 = and(out_rivalid_1[1147], out_rimask_1269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1269 = and(out_roready_1[1147], out_romask_1269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1269 = and(out_wivalid_1[1147], out_wimask_1269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1269 = and(out_woready_1[1147], out_womask_1269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12095 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12096 = and(out_f_rivalid_1269, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12097 = and(UInt<1>(0h1), out_f_roready_1269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12098 = eq(out_rimask_1269, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12099 = eq(out_wimask_1269, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12100 = eq(out_romask_1269, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12101 = eq(out_womask_1269, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12102 = or(_T_1138, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12103 = bits(_out_T_12102, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1270 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1270 = orr(_out_rimask_T_1270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1270 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1270 = andr(_out_wimask_T_1270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1270 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1270 = orr(_out_romask_T_1270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1270 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1270 = andr(_out_womask_T_1270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1270 = and(out_rivalid_1[1148], out_rimask_1270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1270 = and(out_roready_1[1148], out_romask_1270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1270 = and(out_wivalid_1[1148], out_wimask_1270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1270 = and(out_woready_1[1148], out_womask_1270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12104 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12105 = and(out_f_rivalid_1270, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12106 = and(UInt<1>(0h1), out_f_roready_1270) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12107 = eq(out_rimask_1270, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12108 = eq(out_wimask_1270, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12109 = eq(out_romask_1270, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12110 = eq(out_womask_1270, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1094 = or(_out_T_12103, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1094 = cat(_T_1139, _out_prepend_T_1094) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12111 = or(out_prepend_1094, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12112 = bits(_out_T_12111, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1271 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1271 = orr(_out_rimask_T_1271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1271 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1271 = andr(_out_wimask_T_1271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1271 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1271 = orr(_out_romask_T_1271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1271 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1271 = andr(_out_womask_T_1271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1271 = and(out_rivalid_1[1149], out_rimask_1271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1271 = and(out_roready_1[1149], out_romask_1271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1271 = and(out_wivalid_1[1149], out_wimask_1271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1271 = and(out_woready_1[1149], out_womask_1271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12113 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12114 = and(out_f_rivalid_1271, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12115 = and(UInt<1>(0h1), out_f_roready_1271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12116 = eq(out_rimask_1271, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12117 = eq(out_wimask_1271, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12118 = eq(out_romask_1271, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12119 = eq(out_womask_1271, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1095 = or(_out_T_12112, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1095 = cat(_T_1140, _out_prepend_T_1095) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12120 = or(out_prepend_1095, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12121 = bits(_out_T_12120, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1272 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1272 = orr(_out_rimask_T_1272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1272 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1272 = andr(_out_wimask_T_1272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1272 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1272 = orr(_out_romask_T_1272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1272 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1272 = andr(_out_womask_T_1272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1272 = and(out_rivalid_1[1150], out_rimask_1272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1272 = and(out_roready_1[1150], out_romask_1272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1272 = and(out_wivalid_1[1150], out_wimask_1272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1272 = and(out_woready_1[1150], out_womask_1272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12122 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12123 = and(out_f_rivalid_1272, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12124 = and(UInt<1>(0h1), out_f_roready_1272) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12125 = eq(out_rimask_1272, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12126 = eq(out_wimask_1272, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12127 = eq(out_romask_1272, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12128 = eq(out_womask_1272, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1096 = or(_out_T_12121, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1096 = cat(_T_1141, _out_prepend_T_1096) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12129 = or(out_prepend_1096, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12130 = bits(_out_T_12129, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1273 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1273 = orr(_out_rimask_T_1273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1273 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1273 = andr(_out_wimask_T_1273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1273 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1273 = orr(_out_romask_T_1273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1273 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1273 = andr(_out_womask_T_1273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1273 = and(out_rivalid_1[1151], out_rimask_1273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1273 = and(out_roready_1[1151], out_romask_1273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1273 = and(out_wivalid_1[1151], out_wimask_1273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1273 = and(out_woready_1[1151], out_womask_1273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12131 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12132 = and(out_f_rivalid_1273, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12133 = and(UInt<1>(0h1), out_f_roready_1273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12134 = eq(out_rimask_1273, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12135 = eq(out_wimask_1273, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12136 = eq(out_romask_1273, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12137 = eq(out_womask_1273, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1097 = or(_out_T_12130, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1097 = cat(_T_1142, _out_prepend_T_1097) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12138 = or(out_prepend_1097, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12139 = bits(_out_T_12138, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1274 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1274 = orr(_out_rimask_T_1274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1274 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1274 = andr(_out_wimask_T_1274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1274 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1274 = orr(_out_romask_T_1274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1274 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1274 = andr(_out_womask_T_1274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1274 = and(out_rivalid_1[1152], out_rimask_1274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1274 = and(out_roready_1[1152], out_romask_1274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1274 = and(out_wivalid_1[1152], out_wimask_1274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1274 = and(out_woready_1[1152], out_womask_1274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12140 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12141 = and(out_f_rivalid_1274, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12142 = and(UInt<1>(0h1), out_f_roready_1274) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12143 = eq(out_rimask_1274, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12144 = eq(out_wimask_1274, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12145 = eq(out_romask_1274, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12146 = eq(out_womask_1274, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1098 = or(_out_T_12139, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1098 = cat(_T_1143, _out_prepend_T_1098) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12147 = or(out_prepend_1098, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12148 = bits(_out_T_12147, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1275 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1275 = orr(_out_rimask_T_1275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1275 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1275 = andr(_out_wimask_T_1275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1275 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1275 = orr(_out_romask_T_1275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1275 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1275 = andr(_out_womask_T_1275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1275 = and(out_rivalid_1[1153], out_rimask_1275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1275 = and(out_roready_1[1153], out_romask_1275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1275 = and(out_wivalid_1[1153], out_wimask_1275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1275 = and(out_woready_1[1153], out_womask_1275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12149 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12150 = and(out_f_rivalid_1275, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12151 = and(UInt<1>(0h1), out_f_roready_1275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12152 = eq(out_rimask_1275, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12153 = eq(out_wimask_1275, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12154 = eq(out_romask_1275, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12155 = eq(out_womask_1275, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1099 = or(_out_T_12148, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1099 = cat(_T_1144, _out_prepend_T_1099) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12156 = or(out_prepend_1099, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12157 = bits(_out_T_12156, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1276 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1276 = orr(_out_rimask_T_1276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1276 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1276 = andr(_out_wimask_T_1276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1276 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1276 = orr(_out_romask_T_1276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1276 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1276 = andr(_out_womask_T_1276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1276 = and(out_rivalid_1[1154], out_rimask_1276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1276 = and(out_roready_1[1154], out_romask_1276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1276 = and(out_wivalid_1[1154], out_wimask_1276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1276 = and(out_woready_1[1154], out_womask_1276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12158 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12159 = and(out_f_rivalid_1276, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12160 = and(UInt<1>(0h1), out_f_roready_1276) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12161 = eq(out_rimask_1276, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12162 = eq(out_wimask_1276, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12163 = eq(out_romask_1276, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12164 = eq(out_womask_1276, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1100 = or(_out_T_12157, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1100 = cat(_T_1145, _out_prepend_T_1100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12165 = or(out_prepend_1100, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12166 = bits(_out_T_12165, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1277 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1277 = orr(_out_rimask_T_1277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1277 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1277 = andr(_out_wimask_T_1277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1277 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1277 = orr(_out_romask_T_1277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1277 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1277 = andr(_out_womask_T_1277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1277 = and(out_rivalid_1[1155], out_rimask_1277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1277 = and(out_roready_1[1155], out_romask_1277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1277 = and(out_wivalid_1[1155], out_wimask_1277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1277 = and(out_woready_1[1155], out_womask_1277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12167 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12168 = and(out_f_rivalid_1277, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12169 = and(UInt<1>(0h1), out_f_roready_1277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12170 = eq(out_rimask_1277, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12171 = eq(out_wimask_1277, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12172 = eq(out_romask_1277, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12173 = eq(out_womask_1277, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12174 = or(_T_1194, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12175 = bits(_out_T_12174, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1278 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1278 = orr(_out_rimask_T_1278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1278 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1278 = andr(_out_wimask_T_1278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1278 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1278 = orr(_out_romask_T_1278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1278 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1278 = andr(_out_womask_T_1278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1278 = and(out_rivalid_1[1156], out_rimask_1278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1278 = and(out_roready_1[1156], out_romask_1278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1278 = and(out_wivalid_1[1156], out_wimask_1278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1278 = and(out_woready_1[1156], out_womask_1278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12176 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12177 = and(out_f_rivalid_1278, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12178 = and(UInt<1>(0h1), out_f_roready_1278) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12179 = eq(out_rimask_1278, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12180 = eq(out_wimask_1278, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12181 = eq(out_romask_1278, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12182 = eq(out_womask_1278, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1101 = or(_out_T_12175, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1101 = cat(_T_1195, _out_prepend_T_1101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12183 = or(out_prepend_1101, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12184 = bits(_out_T_12183, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1279 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1279 = orr(_out_rimask_T_1279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1279 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1279 = andr(_out_wimask_T_1279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1279 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1279 = orr(_out_romask_T_1279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1279 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1279 = andr(_out_womask_T_1279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1279 = and(out_rivalid_1[1157], out_rimask_1279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1279 = and(out_roready_1[1157], out_romask_1279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1279 = and(out_wivalid_1[1157], out_wimask_1279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1279 = and(out_woready_1[1157], out_womask_1279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12185 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12186 = and(out_f_rivalid_1279, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12187 = and(UInt<1>(0h1), out_f_roready_1279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12188 = eq(out_rimask_1279, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12189 = eq(out_wimask_1279, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12190 = eq(out_romask_1279, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12191 = eq(out_womask_1279, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1102 = or(_out_T_12184, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1102 = cat(_T_1196, _out_prepend_T_1102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12192 = or(out_prepend_1102, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12193 = bits(_out_T_12192, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1280 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1280 = orr(_out_rimask_T_1280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1280 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1280 = andr(_out_wimask_T_1280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1280 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1280 = orr(_out_romask_T_1280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1280 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1280 = andr(_out_womask_T_1280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1280 = and(out_rivalid_1[1158], out_rimask_1280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1280 = and(out_roready_1[1158], out_romask_1280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1280 = and(out_wivalid_1[1158], out_wimask_1280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1280 = and(out_woready_1[1158], out_womask_1280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12194 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12195 = and(out_f_rivalid_1280, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12196 = and(UInt<1>(0h1), out_f_roready_1280) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12197 = eq(out_rimask_1280, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12198 = eq(out_wimask_1280, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12199 = eq(out_romask_1280, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12200 = eq(out_womask_1280, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1103 = or(_out_T_12193, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1103 = cat(_T_1197, _out_prepend_T_1103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12201 = or(out_prepend_1103, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12202 = bits(_out_T_12201, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1281 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1281 = orr(_out_rimask_T_1281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1281 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1281 = andr(_out_wimask_T_1281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1281 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1281 = orr(_out_romask_T_1281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1281 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1281 = andr(_out_womask_T_1281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1281 = and(out_rivalid_1[1159], out_rimask_1281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1281 = and(out_roready_1[1159], out_romask_1281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1281 = and(out_wivalid_1[1159], out_wimask_1281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1281 = and(out_woready_1[1159], out_womask_1281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12203 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12204 = and(out_f_rivalid_1281, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12205 = and(UInt<1>(0h1), out_f_roready_1281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12206 = eq(out_rimask_1281, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12207 = eq(out_wimask_1281, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12208 = eq(out_romask_1281, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12209 = eq(out_womask_1281, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1104 = or(_out_T_12202, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1104 = cat(_T_1198, _out_prepend_T_1104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12210 = or(out_prepend_1104, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12211 = bits(_out_T_12210, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1282 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1282 = orr(_out_rimask_T_1282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1282 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1282 = andr(_out_wimask_T_1282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1282 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1282 = orr(_out_romask_T_1282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1282 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1282 = andr(_out_womask_T_1282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1282 = and(out_rivalid_1[1160], out_rimask_1282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1282 = and(out_roready_1[1160], out_romask_1282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1282 = and(out_wivalid_1[1160], out_wimask_1282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1282 = and(out_woready_1[1160], out_womask_1282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12212 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12213 = and(out_f_rivalid_1282, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12214 = and(UInt<1>(0h1), out_f_roready_1282) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12215 = eq(out_rimask_1282, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12216 = eq(out_wimask_1282, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12217 = eq(out_romask_1282, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12218 = eq(out_womask_1282, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1105 = or(_out_T_12211, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1105 = cat(_T_1199, _out_prepend_T_1105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12219 = or(out_prepend_1105, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12220 = bits(_out_T_12219, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1283 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1283 = orr(_out_rimask_T_1283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1283 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1283 = andr(_out_wimask_T_1283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1283 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1283 = orr(_out_romask_T_1283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1283 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1283 = andr(_out_womask_T_1283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1283 = and(out_rivalid_1[1161], out_rimask_1283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1283 = and(out_roready_1[1161], out_romask_1283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1283 = and(out_wivalid_1[1161], out_wimask_1283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1283 = and(out_woready_1[1161], out_womask_1283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12221 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12222 = and(out_f_rivalid_1283, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12223 = and(UInt<1>(0h1), out_f_roready_1283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12224 = eq(out_rimask_1283, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12225 = eq(out_wimask_1283, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12226 = eq(out_romask_1283, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12227 = eq(out_womask_1283, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1106 = or(_out_T_12220, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1106 = cat(_T_1200, _out_prepend_T_1106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12228 = or(out_prepend_1106, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12229 = bits(_out_T_12228, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1284 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1284 = orr(_out_rimask_T_1284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1284 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1284 = andr(_out_wimask_T_1284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1284 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1284 = orr(_out_romask_T_1284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1284 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1284 = andr(_out_womask_T_1284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1284 = and(out_rivalid_1[1162], out_rimask_1284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1284 = and(out_roready_1[1162], out_romask_1284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1284 = and(out_wivalid_1[1162], out_wimask_1284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1284 = and(out_woready_1[1162], out_womask_1284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12230 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12231 = and(out_f_rivalid_1284, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12232 = and(UInt<1>(0h1), out_f_roready_1284) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12233 = eq(out_rimask_1284, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12234 = eq(out_wimask_1284, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12235 = eq(out_romask_1284, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12236 = eq(out_womask_1284, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1107 = or(_out_T_12229, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1107 = cat(_T_1201, _out_prepend_T_1107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12237 = or(out_prepend_1107, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12238 = bits(_out_T_12237, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1285 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1285 = orr(_out_rimask_T_1285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1285 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1285 = andr(_out_wimask_T_1285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1285 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1285 = orr(_out_romask_T_1285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1285 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1285 = andr(_out_womask_T_1285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1285 = and(out_rivalid_1[1163], out_rimask_1285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1285 = and(out_roready_1[1163], out_romask_1285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1285 = and(out_wivalid_1[1163], out_wimask_1285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1285 = and(out_woready_1[1163], out_womask_1285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12239 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12240 = and(out_f_rivalid_1285, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12241 = and(UInt<1>(0h1), out_f_roready_1285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12242 = eq(out_rimask_1285, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12243 = eq(out_wimask_1285, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12244 = eq(out_romask_1285, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12245 = eq(out_womask_1285, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12246 = or(_T_1274, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12247 = bits(_out_T_12246, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1286 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1286 = orr(_out_rimask_T_1286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1286 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1286 = andr(_out_wimask_T_1286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1286 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1286 = orr(_out_romask_T_1286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1286 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1286 = andr(_out_womask_T_1286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1286 = and(out_rivalid_1[1164], out_rimask_1286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1286 = and(out_roready_1[1164], out_romask_1286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1286 = and(out_wivalid_1[1164], out_wimask_1286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1286 = and(out_woready_1[1164], out_womask_1286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12248 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12249 = and(out_f_rivalid_1286, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12250 = and(UInt<1>(0h1), out_f_roready_1286) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12251 = eq(out_rimask_1286, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12252 = eq(out_wimask_1286, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12253 = eq(out_romask_1286, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12254 = eq(out_womask_1286, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1108 = or(_out_T_12247, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1108 = cat(_T_1275, _out_prepend_T_1108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12255 = or(out_prepend_1108, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12256 = bits(_out_T_12255, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1287 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1287 = orr(_out_rimask_T_1287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1287 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1287 = andr(_out_wimask_T_1287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1287 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1287 = orr(_out_romask_T_1287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1287 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1287 = andr(_out_womask_T_1287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1287 = and(out_rivalid_1[1165], out_rimask_1287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1287 = and(out_roready_1[1165], out_romask_1287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1287 = and(out_wivalid_1[1165], out_wimask_1287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1287 = and(out_woready_1[1165], out_womask_1287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12257 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12258 = and(out_f_rivalid_1287, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12259 = and(UInt<1>(0h1), out_f_roready_1287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12260 = eq(out_rimask_1287, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12261 = eq(out_wimask_1287, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12262 = eq(out_romask_1287, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12263 = eq(out_womask_1287, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1109 = or(_out_T_12256, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1109 = cat(_T_1276, _out_prepend_T_1109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12264 = or(out_prepend_1109, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12265 = bits(_out_T_12264, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1288 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1288 = orr(_out_rimask_T_1288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1288 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1288 = andr(_out_wimask_T_1288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1288 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1288 = orr(_out_romask_T_1288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1288 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1288 = andr(_out_womask_T_1288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1288 = and(out_rivalid_1[1166], out_rimask_1288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1288 = and(out_roready_1[1166], out_romask_1288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1288 = and(out_wivalid_1[1166], out_wimask_1288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1288 = and(out_woready_1[1166], out_womask_1288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12266 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12267 = and(out_f_rivalid_1288, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12268 = and(UInt<1>(0h1), out_f_roready_1288) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12269 = eq(out_rimask_1288, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12270 = eq(out_wimask_1288, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12271 = eq(out_romask_1288, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12272 = eq(out_womask_1288, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1110 = or(_out_T_12265, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1110 = cat(_T_1277, _out_prepend_T_1110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12273 = or(out_prepend_1110, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12274 = bits(_out_T_12273, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1289 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1289 = orr(_out_rimask_T_1289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1289 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1289 = andr(_out_wimask_T_1289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1289 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1289 = orr(_out_romask_T_1289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1289 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1289 = andr(_out_womask_T_1289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1289 = and(out_rivalid_1[1167], out_rimask_1289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1289 = and(out_roready_1[1167], out_romask_1289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1289 = and(out_wivalid_1[1167], out_wimask_1289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1289 = and(out_woready_1[1167], out_womask_1289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12275 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12276 = and(out_f_rivalid_1289, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12277 = and(UInt<1>(0h1), out_f_roready_1289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12278 = eq(out_rimask_1289, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12279 = eq(out_wimask_1289, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12280 = eq(out_romask_1289, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12281 = eq(out_womask_1289, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1111 = or(_out_T_12274, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1111 = cat(_T_1278, _out_prepend_T_1111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12282 = or(out_prepend_1111, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12283 = bits(_out_T_12282, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1290 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1290 = orr(_out_rimask_T_1290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1290 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1290 = andr(_out_wimask_T_1290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1290 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1290 = orr(_out_romask_T_1290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1290 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1290 = andr(_out_womask_T_1290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1290 = and(out_rivalid_1[1168], out_rimask_1290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1290 = and(out_roready_1[1168], out_romask_1290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1290 = and(out_wivalid_1[1168], out_wimask_1290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1290 = and(out_woready_1[1168], out_womask_1290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12284 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12285 = and(out_f_rivalid_1290, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12286 = and(UInt<1>(0h1), out_f_roready_1290) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12287 = eq(out_rimask_1290, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12288 = eq(out_wimask_1290, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12289 = eq(out_romask_1290, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12290 = eq(out_womask_1290, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1112 = or(_out_T_12283, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1112 = cat(_T_1279, _out_prepend_T_1112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12291 = or(out_prepend_1112, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12292 = bits(_out_T_12291, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1291 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1291 = orr(_out_rimask_T_1291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1291 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1291 = andr(_out_wimask_T_1291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1291 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1291 = orr(_out_romask_T_1291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1291 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1291 = andr(_out_womask_T_1291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1291 = and(out_rivalid_1[1169], out_rimask_1291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1291 = and(out_roready_1[1169], out_romask_1291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1291 = and(out_wivalid_1[1169], out_wimask_1291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1291 = and(out_woready_1[1169], out_womask_1291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12293 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12294 = and(out_f_rivalid_1291, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12295 = and(UInt<1>(0h1), out_f_roready_1291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12296 = eq(out_rimask_1291, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12297 = eq(out_wimask_1291, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12298 = eq(out_romask_1291, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12299 = eq(out_womask_1291, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1113 = or(_out_T_12292, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1113 = cat(_T_1280, _out_prepend_T_1113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12300 = or(out_prepend_1113, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12301 = bits(_out_T_12300, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1292 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1292 = orr(_out_rimask_T_1292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1292 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1292 = andr(_out_wimask_T_1292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1292 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1292 = orr(_out_romask_T_1292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1292 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1292 = andr(_out_womask_T_1292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1292 = and(out_rivalid_1[1170], out_rimask_1292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1292 = and(out_roready_1[1170], out_romask_1292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1292 = and(out_wivalid_1[1170], out_wimask_1292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1292 = and(out_woready_1[1170], out_womask_1292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12302 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12303 = and(out_f_rivalid_1292, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12304 = and(UInt<1>(0h1), out_f_roready_1292) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12305 = eq(out_rimask_1292, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12306 = eq(out_wimask_1292, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12307 = eq(out_romask_1292, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12308 = eq(out_womask_1292, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1114 = or(_out_T_12301, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1114 = cat(_T_1281, _out_prepend_T_1114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12309 = or(out_prepend_1114, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12310 = bits(_out_T_12309, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1293 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1293 = orr(_out_rimask_T_1293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1293 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1293 = andr(_out_wimask_T_1293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1293 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1293 = orr(_out_romask_T_1293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1293 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1293 = andr(_out_womask_T_1293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1293 = and(out_rivalid_1[1171], out_rimask_1293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1293 = and(out_roready_1[1171], out_romask_1293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1293 = and(out_wivalid_1[1171], out_wimask_1293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1293 = and(out_woready_1[1171], out_womask_1293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12311 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12312 = and(out_f_rivalid_1293, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12313 = and(UInt<1>(0h1), out_f_roready_1293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12314 = eq(out_rimask_1293, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12315 = eq(out_wimask_1293, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12316 = eq(out_romask_1293, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12317 = eq(out_womask_1293, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12318 = or(_T_1450, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12319 = bits(_out_T_12318, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1294 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1294 = orr(_out_rimask_T_1294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1294 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1294 = andr(_out_wimask_T_1294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1294 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1294 = orr(_out_romask_T_1294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1294 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1294 = andr(_out_womask_T_1294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1294 = and(out_rivalid_1[1172], out_rimask_1294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1294 = and(out_roready_1[1172], out_romask_1294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1294 = and(out_wivalid_1[1172], out_wimask_1294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1294 = and(out_woready_1[1172], out_womask_1294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12320 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12321 = and(out_f_rivalid_1294, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12322 = and(UInt<1>(0h1), out_f_roready_1294) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12323 = eq(out_rimask_1294, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12324 = eq(out_wimask_1294, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12325 = eq(out_romask_1294, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12326 = eq(out_womask_1294, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1115 = or(_out_T_12319, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1115 = cat(_T_1451, _out_prepend_T_1115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12327 = or(out_prepend_1115, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12328 = bits(_out_T_12327, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1295 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1295 = orr(_out_rimask_T_1295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1295 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1295 = andr(_out_wimask_T_1295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1295 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1295 = orr(_out_romask_T_1295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1295 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1295 = andr(_out_womask_T_1295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1295 = and(out_rivalid_1[1173], out_rimask_1295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1295 = and(out_roready_1[1173], out_romask_1295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1295 = and(out_wivalid_1[1173], out_wimask_1295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1295 = and(out_woready_1[1173], out_womask_1295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12329 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12330 = and(out_f_rivalid_1295, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12331 = and(UInt<1>(0h1), out_f_roready_1295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12332 = eq(out_rimask_1295, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12333 = eq(out_wimask_1295, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12334 = eq(out_romask_1295, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12335 = eq(out_womask_1295, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1116 = or(_out_T_12328, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1116 = cat(_T_1452, _out_prepend_T_1116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12336 = or(out_prepend_1116, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12337 = bits(_out_T_12336, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1296 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1296 = orr(_out_rimask_T_1296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1296 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1296 = andr(_out_wimask_T_1296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1296 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1296 = orr(_out_romask_T_1296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1296 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1296 = andr(_out_womask_T_1296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1296 = and(out_rivalid_1[1174], out_rimask_1296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1296 = and(out_roready_1[1174], out_romask_1296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1296 = and(out_wivalid_1[1174], out_wimask_1296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1296 = and(out_woready_1[1174], out_womask_1296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12338 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12339 = and(out_f_rivalid_1296, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12340 = and(UInt<1>(0h1), out_f_roready_1296) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12341 = eq(out_rimask_1296, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12342 = eq(out_wimask_1296, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12343 = eq(out_romask_1296, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12344 = eq(out_womask_1296, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1117 = or(_out_T_12337, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1117 = cat(_T_1453, _out_prepend_T_1117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12345 = or(out_prepend_1117, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12346 = bits(_out_T_12345, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1297 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1297 = orr(_out_rimask_T_1297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1297 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1297 = andr(_out_wimask_T_1297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1297 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1297 = orr(_out_romask_T_1297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1297 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1297 = andr(_out_womask_T_1297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1297 = and(out_rivalid_1[1175], out_rimask_1297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1297 = and(out_roready_1[1175], out_romask_1297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1297 = and(out_wivalid_1[1175], out_wimask_1297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1297 = and(out_woready_1[1175], out_womask_1297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12347 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12348 = and(out_f_rivalid_1297, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12349 = and(UInt<1>(0h1), out_f_roready_1297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12350 = eq(out_rimask_1297, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12351 = eq(out_wimask_1297, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12352 = eq(out_romask_1297, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12353 = eq(out_womask_1297, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1118 = or(_out_T_12346, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1118 = cat(_T_1454, _out_prepend_T_1118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12354 = or(out_prepend_1118, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12355 = bits(_out_T_12354, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1298 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1298 = orr(_out_rimask_T_1298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1298 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1298 = andr(_out_wimask_T_1298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1298 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1298 = orr(_out_romask_T_1298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1298 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1298 = andr(_out_womask_T_1298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1298 = and(out_rivalid_1[1176], out_rimask_1298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1298 = and(out_roready_1[1176], out_romask_1298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1298 = and(out_wivalid_1[1176], out_wimask_1298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1298 = and(out_woready_1[1176], out_womask_1298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12356 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12357 = and(out_f_rivalid_1298, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12358 = and(UInt<1>(0h1), out_f_roready_1298) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12359 = eq(out_rimask_1298, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12360 = eq(out_wimask_1298, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12361 = eq(out_romask_1298, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12362 = eq(out_womask_1298, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1119 = or(_out_T_12355, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1119 = cat(_T_1455, _out_prepend_T_1119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12363 = or(out_prepend_1119, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12364 = bits(_out_T_12363, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1299 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1299 = orr(_out_rimask_T_1299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1299 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1299 = andr(_out_wimask_T_1299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1299 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1299 = orr(_out_romask_T_1299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1299 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1299 = andr(_out_womask_T_1299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1299 = and(out_rivalid_1[1177], out_rimask_1299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1299 = and(out_roready_1[1177], out_romask_1299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1299 = and(out_wivalid_1[1177], out_wimask_1299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1299 = and(out_woready_1[1177], out_womask_1299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12365 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12366 = and(out_f_rivalid_1299, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12367 = and(UInt<1>(0h1), out_f_roready_1299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12368 = eq(out_rimask_1299, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12369 = eq(out_wimask_1299, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12370 = eq(out_romask_1299, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12371 = eq(out_womask_1299, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1120 = or(_out_T_12364, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1120 = cat(_T_1456, _out_prepend_T_1120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12372 = or(out_prepend_1120, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12373 = bits(_out_T_12372, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1300 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1300 = orr(_out_rimask_T_1300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1300 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1300 = andr(_out_wimask_T_1300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1300 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1300 = orr(_out_romask_T_1300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1300 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1300 = andr(_out_womask_T_1300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1300 = and(out_rivalid_1[1178], out_rimask_1300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1300 = and(out_roready_1[1178], out_romask_1300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1300 = and(out_wivalid_1[1178], out_wimask_1300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1300 = and(out_woready_1[1178], out_womask_1300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12374 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12375 = and(out_f_rivalid_1300, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12376 = and(UInt<1>(0h1), out_f_roready_1300) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12377 = eq(out_rimask_1300, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12378 = eq(out_wimask_1300, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12379 = eq(out_romask_1300, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12380 = eq(out_womask_1300, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1121 = or(_out_T_12373, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1121 = cat(_T_1457, _out_prepend_T_1121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12381 = or(out_prepend_1121, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12382 = bits(_out_T_12381, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1301 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1301 = orr(_out_rimask_T_1301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1301 = bits(out_frontMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1301 = andr(_out_wimask_T_1301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1301 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1301 = orr(_out_romask_T_1301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1301 = bits(out_backMask_1, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1301 = andr(_out_womask_T_1301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1301 = and(out_rivalid_1[1179], out_rimask_1301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1301 = and(out_roready_1[1179], out_romask_1301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1301 = and(out_wivalid_1[1179], out_wimask_1301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1301 = and(out_woready_1[1179], out_womask_1301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12383 = bits(out_front_1.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12384 = and(out_f_rivalid_1301, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12385 = and(UInt<1>(0h1), out_f_roready_1301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12386 = eq(out_rimask_1301, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12387 = eq(out_wimask_1301, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12388 = eq(out_romask_1301, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12389 = eq(out_womask_1301, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12390 = or(_T_1234, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12391 = bits(_out_T_12390, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1302 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1302 = orr(_out_rimask_T_1302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1302 = bits(out_frontMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1302 = andr(_out_wimask_T_1302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1302 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1302 = orr(_out_romask_T_1302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1302 = bits(out_backMask_1, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1302 = andr(_out_womask_T_1302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1302 = and(out_rivalid_1[1180], out_rimask_1302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1302 = and(out_roready_1[1180], out_romask_1302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1302 = and(out_wivalid_1[1180], out_wimask_1302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1302 = and(out_woready_1[1180], out_womask_1302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12392 = bits(out_front_1.bits.data, 15, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12393 = and(out_f_rivalid_1302, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12394 = and(UInt<1>(0h1), out_f_roready_1302) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12395 = eq(out_rimask_1302, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12396 = eq(out_wimask_1302, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12397 = eq(out_romask_1302, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12398 = eq(out_womask_1302, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1122 = or(_out_T_12391, UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1122 = cat(_T_1235, _out_prepend_T_1122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12399 = or(out_prepend_1122, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12400 = bits(_out_T_12399, 15, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1303 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1303 = orr(_out_rimask_T_1303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1303 = bits(out_frontMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1303 = andr(_out_wimask_T_1303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1303 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1303 = orr(_out_romask_T_1303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1303 = bits(out_backMask_1, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1303 = andr(_out_womask_T_1303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1303 = and(out_rivalid_1[1181], out_rimask_1303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1303 = and(out_roready_1[1181], out_romask_1303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1303 = and(out_wivalid_1[1181], out_wimask_1303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1303 = and(out_woready_1[1181], out_womask_1303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12401 = bits(out_front_1.bits.data, 23, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12402 = and(out_f_rivalid_1303, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12403 = and(UInt<1>(0h1), out_f_roready_1303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12404 = eq(out_rimask_1303, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12405 = eq(out_wimask_1303, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12406 = eq(out_romask_1303, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12407 = eq(out_womask_1303, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1123 = or(_out_T_12400, UInt<16>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1123 = cat(_T_1236, _out_prepend_T_1123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12408 = or(out_prepend_1123, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12409 = bits(_out_T_12408, 23, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1304 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1304 = orr(_out_rimask_T_1304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1304 = bits(out_frontMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1304 = andr(_out_wimask_T_1304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1304 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1304 = orr(_out_romask_T_1304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1304 = bits(out_backMask_1, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1304 = andr(_out_womask_T_1304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1304 = and(out_rivalid_1[1182], out_rimask_1304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1304 = and(out_roready_1[1182], out_romask_1304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1304 = and(out_wivalid_1[1182], out_wimask_1304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1304 = and(out_woready_1[1182], out_womask_1304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12410 = bits(out_front_1.bits.data, 31, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12411 = and(out_f_rivalid_1304, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12412 = and(UInt<1>(0h1), out_f_roready_1304) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12413 = eq(out_rimask_1304, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12414 = eq(out_wimask_1304, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12415 = eq(out_romask_1304, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12416 = eq(out_womask_1304, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1124 = or(_out_T_12409, UInt<24>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1124 = cat(_T_1237, _out_prepend_T_1124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12417 = or(out_prepend_1124, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12418 = bits(_out_T_12417, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1305 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1305 = orr(_out_rimask_T_1305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1305 = bits(out_frontMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1305 = andr(_out_wimask_T_1305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1305 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1305 = orr(_out_romask_T_1305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1305 = bits(out_backMask_1, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1305 = andr(_out_womask_T_1305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1305 = and(out_rivalid_1[1183], out_rimask_1305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1305 = and(out_roready_1[1183], out_romask_1305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1305 = and(out_wivalid_1[1183], out_wimask_1305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1305 = and(out_woready_1[1183], out_womask_1305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12419 = bits(out_front_1.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12420 = and(out_f_rivalid_1305, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12421 = and(UInt<1>(0h1), out_f_roready_1305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12422 = eq(out_rimask_1305, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12423 = eq(out_wimask_1305, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12424 = eq(out_romask_1305, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12425 = eq(out_womask_1305, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1125 = or(_out_T_12418, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1125 = cat(_T_1238, _out_prepend_T_1125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12426 = or(out_prepend_1125, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12427 = bits(_out_T_12426, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1306 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1306 = orr(_out_rimask_T_1306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1306 = bits(out_frontMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1306 = andr(_out_wimask_T_1306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1306 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1306 = orr(_out_romask_T_1306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1306 = bits(out_backMask_1, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1306 = andr(_out_womask_T_1306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1306 = and(out_rivalid_1[1184], out_rimask_1306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1306 = and(out_roready_1[1184], out_romask_1306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1306 = and(out_wivalid_1[1184], out_wimask_1306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1306 = and(out_woready_1[1184], out_womask_1306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12428 = bits(out_front_1.bits.data, 47, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12429 = and(out_f_rivalid_1306, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12430 = and(UInt<1>(0h1), out_f_roready_1306) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12431 = eq(out_rimask_1306, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12432 = eq(out_wimask_1306, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12433 = eq(out_romask_1306, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12434 = eq(out_womask_1306, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1126 = or(_out_T_12427, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1126 = cat(_T_1239, _out_prepend_T_1126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12435 = or(out_prepend_1126, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12436 = bits(_out_T_12435, 47, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1307 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1307 = orr(_out_rimask_T_1307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1307 = bits(out_frontMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1307 = andr(_out_wimask_T_1307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1307 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1307 = orr(_out_romask_T_1307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1307 = bits(out_backMask_1, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1307 = andr(_out_womask_T_1307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1307 = and(out_rivalid_1[1185], out_rimask_1307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1307 = and(out_roready_1[1185], out_romask_1307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1307 = and(out_wivalid_1[1185], out_wimask_1307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1307 = and(out_woready_1[1185], out_womask_1307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12437 = bits(out_front_1.bits.data, 55, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12438 = and(out_f_rivalid_1307, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12439 = and(UInt<1>(0h1), out_f_roready_1307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12440 = eq(out_rimask_1307, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12441 = eq(out_wimask_1307, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12442 = eq(out_romask_1307, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12443 = eq(out_womask_1307, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1127 = or(_out_T_12436, UInt<48>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1127 = cat(_T_1240, _out_prepend_T_1127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12444 = or(out_prepend_1127, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12445 = bits(_out_T_12444, 55, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1308 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1308 = orr(_out_rimask_T_1308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1308 = bits(out_frontMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1308 = andr(_out_wimask_T_1308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1308 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1308 = orr(_out_romask_T_1308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1308 = bits(out_backMask_1, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1308 = andr(_out_womask_T_1308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1308 = and(out_rivalid_1[1186], out_rimask_1308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1308 = and(out_roready_1[1186], out_romask_1308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1308 = and(out_wivalid_1[1186], out_wimask_1308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1308 = and(out_woready_1[1186], out_womask_1308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12446 = bits(out_front_1.bits.data, 63, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12447 = and(out_f_rivalid_1308, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12448 = and(UInt<1>(0h1), out_f_roready_1308) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12449 = eq(out_rimask_1308, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12450 = eq(out_wimask_1308, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12451 = eq(out_romask_1308, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12452 = eq(out_womask_1308, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1128 = or(_out_T_12445, UInt<56>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1128 = cat(_T_1241, _out_prepend_T_1128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12453 = or(out_prepend_1128, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12454 = bits(_out_T_12453, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_7 = bits(out_front_1.bits.index, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_8 = bits(out_front_1.bits.index, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_9 = bits(out_front_1.bits.index, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_10 = bits(out_front_1.bits.index, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_11 = bits(out_front_1.bits.index, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_12 = bits(out_front_1.bits.index, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_13 = bits(out_front_1.bits.index, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_14 = bits(out_front_1.bits.index, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_15 = bits(out_front_1.bits.index, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex_lo_lo = cat(_out_iindex_T_8, _out_iindex_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex_lo_hi_1 = cat(_out_iindex_T_10, _out_iindex_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex_lo_1 = cat(out_iindex_lo_hi_1, out_iindex_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex_hi_lo = cat(_out_iindex_T_12, _out_iindex_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex_hi_hi_1 = cat(_out_iindex_T_14, _out_iindex_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex_hi_1 = cat(out_iindex_hi_hi_1, out_iindex_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex_1 = cat(out_iindex_hi_1, out_iindex_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_7 = bits(out_front_1.bits.index, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_8 = bits(out_front_1.bits.index, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_9 = bits(out_front_1.bits.index, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_10 = bits(out_front_1.bits.index, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_11 = bits(out_front_1.bits.index, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_12 = bits(out_front_1.bits.index, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_13 = bits(out_front_1.bits.index, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_14 = bits(out_front_1.bits.index, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_15 = bits(out_front_1.bits.index, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex_lo_lo = cat(_out_oindex_T_8, _out_oindex_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex_lo_hi_1 = cat(_out_oindex_T_10, _out_oindex_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex_lo_1 = cat(out_oindex_lo_hi_1, out_oindex_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex_hi_lo = cat(_out_oindex_T_12, _out_oindex_T_11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex_hi_hi_1 = cat(_out_oindex_T_14, _out_oindex_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex_hi_1 = cat(out_oindex_hi_hi_1, out_oindex_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex_1 = cat(out_oindex_hi_1, out_oindex_lo_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontSel_T_1 = dshl(UInt<1>(0h1), out_iindex_1) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node out_frontSel_0_1 = bits(_out_frontSel_T_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_1_1 = bits(_out_frontSel_T_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_2_1 = bits(_out_frontSel_T_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_3_1 = bits(_out_frontSel_T_1, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_4_1 = bits(_out_frontSel_T_1, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_5_1 = bits(_out_frontSel_T_1, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_6_1 = bits(_out_frontSel_T_1, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_7_1 = bits(_out_frontSel_T_1, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_8_1 = bits(_out_frontSel_T_1, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_9_1 = bits(_out_frontSel_T_1, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_10_1 = bits(_out_frontSel_T_1, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_11_1 = bits(_out_frontSel_T_1, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_12_1 = bits(_out_frontSel_T_1, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_13_1 = bits(_out_frontSel_T_1, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_14_1 = bits(_out_frontSel_T_1, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_15_1 = bits(_out_frontSel_T_1, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_16_1 = bits(_out_frontSel_T_1, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_17_1 = bits(_out_frontSel_T_1, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_18_1 = bits(_out_frontSel_T_1, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_19_1 = bits(_out_frontSel_T_1, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_20_1 = bits(_out_frontSel_T_1, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_21_1 = bits(_out_frontSel_T_1, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_22_1 = bits(_out_frontSel_T_1, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_23_1 = bits(_out_frontSel_T_1, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_24_1 = bits(_out_frontSel_T_1, 24, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_25_1 = bits(_out_frontSel_T_1, 25, 25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_26_1 = bits(_out_frontSel_T_1, 26, 26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_27_1 = bits(_out_frontSel_T_1, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_28_1 = bits(_out_frontSel_T_1, 28, 28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_29_1 = bits(_out_frontSel_T_1, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_30_1 = bits(_out_frontSel_T_1, 30, 30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_31_1 = bits(_out_frontSel_T_1, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_32_1 = bits(_out_frontSel_T_1, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_33_1 = bits(_out_frontSel_T_1, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_34_1 = bits(_out_frontSel_T_1, 34, 34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_35_1 = bits(_out_frontSel_T_1, 35, 35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_36_1 = bits(_out_frontSel_T_1, 36, 36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_37_1 = bits(_out_frontSel_T_1, 37, 37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_38_1 = bits(_out_frontSel_T_1, 38, 38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_39_1 = bits(_out_frontSel_T_1, 39, 39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_40_1 = bits(_out_frontSel_T_1, 40, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_41_1 = bits(_out_frontSel_T_1, 41, 41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_42_1 = bits(_out_frontSel_T_1, 42, 42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_43_1 = bits(_out_frontSel_T_1, 43, 43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_44_1 = bits(_out_frontSel_T_1, 44, 44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_45_1 = bits(_out_frontSel_T_1, 45, 45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_46_1 = bits(_out_frontSel_T_1, 46, 46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_47_1 = bits(_out_frontSel_T_1, 47, 47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_48_1 = bits(_out_frontSel_T_1, 48, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_49_1 = bits(_out_frontSel_T_1, 49, 49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_50_1 = bits(_out_frontSel_T_1, 50, 50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_51_1 = bits(_out_frontSel_T_1, 51, 51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_52_1 = bits(_out_frontSel_T_1, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_53_1 = bits(_out_frontSel_T_1, 53, 53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_54_1 = bits(_out_frontSel_T_1, 54, 54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_55_1 = bits(_out_frontSel_T_1, 55, 55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_56_1 = bits(_out_frontSel_T_1, 56, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_57_1 = bits(_out_frontSel_T_1, 57, 57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_58_1 = bits(_out_frontSel_T_1, 58, 58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_59_1 = bits(_out_frontSel_T_1, 59, 59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_60_1 = bits(_out_frontSel_T_1, 60, 60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_61_1 = bits(_out_frontSel_T_1, 61, 61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_62_1 = bits(_out_frontSel_T_1, 62, 62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_63_1 = bits(_out_frontSel_T_1, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_64 = bits(_out_frontSel_T_1, 64, 64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_65 = bits(_out_frontSel_T_1, 65, 65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_66 = bits(_out_frontSel_T_1, 66, 66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_67 = bits(_out_frontSel_T_1, 67, 67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_68 = bits(_out_frontSel_T_1, 68, 68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_69 = bits(_out_frontSel_T_1, 69, 69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_70 = bits(_out_frontSel_T_1, 70, 70) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_71 = bits(_out_frontSel_T_1, 71, 71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_72 = bits(_out_frontSel_T_1, 72, 72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_73 = bits(_out_frontSel_T_1, 73, 73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_74 = bits(_out_frontSel_T_1, 74, 74) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_75 = bits(_out_frontSel_T_1, 75, 75) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_76 = bits(_out_frontSel_T_1, 76, 76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_77 = bits(_out_frontSel_T_1, 77, 77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_78 = bits(_out_frontSel_T_1, 78, 78) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_79 = bits(_out_frontSel_T_1, 79, 79) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_80 = bits(_out_frontSel_T_1, 80, 80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_81 = bits(_out_frontSel_T_1, 81, 81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_82 = bits(_out_frontSel_T_1, 82, 82) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_83 = bits(_out_frontSel_T_1, 83, 83) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_84 = bits(_out_frontSel_T_1, 84, 84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_85 = bits(_out_frontSel_T_1, 85, 85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_86 = bits(_out_frontSel_T_1, 86, 86) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_87 = bits(_out_frontSel_T_1, 87, 87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_88 = bits(_out_frontSel_T_1, 88, 88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_89 = bits(_out_frontSel_T_1, 89, 89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_90 = bits(_out_frontSel_T_1, 90, 90) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_91 = bits(_out_frontSel_T_1, 91, 91) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_92 = bits(_out_frontSel_T_1, 92, 92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_93 = bits(_out_frontSel_T_1, 93, 93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_94 = bits(_out_frontSel_T_1, 94, 94) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_95 = bits(_out_frontSel_T_1, 95, 95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_96 = bits(_out_frontSel_T_1, 96, 96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_97 = bits(_out_frontSel_T_1, 97, 97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_98 = bits(_out_frontSel_T_1, 98, 98) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_99 = bits(_out_frontSel_T_1, 99, 99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_100 = bits(_out_frontSel_T_1, 100, 100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_101 = bits(_out_frontSel_T_1, 101, 101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_102 = bits(_out_frontSel_T_1, 102, 102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_103 = bits(_out_frontSel_T_1, 103, 103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_104 = bits(_out_frontSel_T_1, 104, 104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_105 = bits(_out_frontSel_T_1, 105, 105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_106 = bits(_out_frontSel_T_1, 106, 106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_107 = bits(_out_frontSel_T_1, 107, 107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_108 = bits(_out_frontSel_T_1, 108, 108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_109 = bits(_out_frontSel_T_1, 109, 109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_110 = bits(_out_frontSel_T_1, 110, 110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_111 = bits(_out_frontSel_T_1, 111, 111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_112 = bits(_out_frontSel_T_1, 112, 112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_113 = bits(_out_frontSel_T_1, 113, 113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_114 = bits(_out_frontSel_T_1, 114, 114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_115 = bits(_out_frontSel_T_1, 115, 115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_116 = bits(_out_frontSel_T_1, 116, 116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_117 = bits(_out_frontSel_T_1, 117, 117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_118 = bits(_out_frontSel_T_1, 118, 118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_119 = bits(_out_frontSel_T_1, 119, 119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_120 = bits(_out_frontSel_T_1, 120, 120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_121 = bits(_out_frontSel_T_1, 121, 121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_122 = bits(_out_frontSel_T_1, 122, 122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_123 = bits(_out_frontSel_T_1, 123, 123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_124 = bits(_out_frontSel_T_1, 124, 124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_125 = bits(_out_frontSel_T_1, 125, 125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_126 = bits(_out_frontSel_T_1, 126, 126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_127 = bits(_out_frontSel_T_1, 127, 127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_128 = bits(_out_frontSel_T_1, 128, 128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_129 = bits(_out_frontSel_T_1, 129, 129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_130 = bits(_out_frontSel_T_1, 130, 130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_131 = bits(_out_frontSel_T_1, 131, 131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_132 = bits(_out_frontSel_T_1, 132, 132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_133 = bits(_out_frontSel_T_1, 133, 133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_134 = bits(_out_frontSel_T_1, 134, 134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_135 = bits(_out_frontSel_T_1, 135, 135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_136 = bits(_out_frontSel_T_1, 136, 136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_137 = bits(_out_frontSel_T_1, 137, 137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_138 = bits(_out_frontSel_T_1, 138, 138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_139 = bits(_out_frontSel_T_1, 139, 139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_140 = bits(_out_frontSel_T_1, 140, 140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_141 = bits(_out_frontSel_T_1, 141, 141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_142 = bits(_out_frontSel_T_1, 142, 142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_143 = bits(_out_frontSel_T_1, 143, 143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_144 = bits(_out_frontSel_T_1, 144, 144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_145 = bits(_out_frontSel_T_1, 145, 145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_146 = bits(_out_frontSel_T_1, 146, 146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_147 = bits(_out_frontSel_T_1, 147, 147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_148 = bits(_out_frontSel_T_1, 148, 148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_149 = bits(_out_frontSel_T_1, 149, 149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_150 = bits(_out_frontSel_T_1, 150, 150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_151 = bits(_out_frontSel_T_1, 151, 151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_152 = bits(_out_frontSel_T_1, 152, 152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_153 = bits(_out_frontSel_T_1, 153, 153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_154 = bits(_out_frontSel_T_1, 154, 154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_155 = bits(_out_frontSel_T_1, 155, 155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_156 = bits(_out_frontSel_T_1, 156, 156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_157 = bits(_out_frontSel_T_1, 157, 157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_158 = bits(_out_frontSel_T_1, 158, 158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_159 = bits(_out_frontSel_T_1, 159, 159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_160 = bits(_out_frontSel_T_1, 160, 160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_161 = bits(_out_frontSel_T_1, 161, 161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_162 = bits(_out_frontSel_T_1, 162, 162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_163 = bits(_out_frontSel_T_1, 163, 163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_164 = bits(_out_frontSel_T_1, 164, 164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_165 = bits(_out_frontSel_T_1, 165, 165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_166 = bits(_out_frontSel_T_1, 166, 166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_167 = bits(_out_frontSel_T_1, 167, 167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_168 = bits(_out_frontSel_T_1, 168, 168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_169 = bits(_out_frontSel_T_1, 169, 169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_170 = bits(_out_frontSel_T_1, 170, 170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_171 = bits(_out_frontSel_T_1, 171, 171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_172 = bits(_out_frontSel_T_1, 172, 172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_173 = bits(_out_frontSel_T_1, 173, 173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_174 = bits(_out_frontSel_T_1, 174, 174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_175 = bits(_out_frontSel_T_1, 175, 175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_176 = bits(_out_frontSel_T_1, 176, 176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_177 = bits(_out_frontSel_T_1, 177, 177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_178 = bits(_out_frontSel_T_1, 178, 178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_179 = bits(_out_frontSel_T_1, 179, 179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_180 = bits(_out_frontSel_T_1, 180, 180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_181 = bits(_out_frontSel_T_1, 181, 181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_182 = bits(_out_frontSel_T_1, 182, 182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_183 = bits(_out_frontSel_T_1, 183, 183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_184 = bits(_out_frontSel_T_1, 184, 184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_185 = bits(_out_frontSel_T_1, 185, 185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_186 = bits(_out_frontSel_T_1, 186, 186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_187 = bits(_out_frontSel_T_1, 187, 187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_188 = bits(_out_frontSel_T_1, 188, 188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_189 = bits(_out_frontSel_T_1, 189, 189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_190 = bits(_out_frontSel_T_1, 190, 190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_191 = bits(_out_frontSel_T_1, 191, 191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_192 = bits(_out_frontSel_T_1, 192, 192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_193 = bits(_out_frontSel_T_1, 193, 193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_194 = bits(_out_frontSel_T_1, 194, 194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_195 = bits(_out_frontSel_T_1, 195, 195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_196 = bits(_out_frontSel_T_1, 196, 196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_197 = bits(_out_frontSel_T_1, 197, 197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_198 = bits(_out_frontSel_T_1, 198, 198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_199 = bits(_out_frontSel_T_1, 199, 199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_200 = bits(_out_frontSel_T_1, 200, 200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_201 = bits(_out_frontSel_T_1, 201, 201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_202 = bits(_out_frontSel_T_1, 202, 202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_203 = bits(_out_frontSel_T_1, 203, 203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_204 = bits(_out_frontSel_T_1, 204, 204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_205 = bits(_out_frontSel_T_1, 205, 205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_206 = bits(_out_frontSel_T_1, 206, 206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_207 = bits(_out_frontSel_T_1, 207, 207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_208 = bits(_out_frontSel_T_1, 208, 208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_209 = bits(_out_frontSel_T_1, 209, 209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_210 = bits(_out_frontSel_T_1, 210, 210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_211 = bits(_out_frontSel_T_1, 211, 211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_212 = bits(_out_frontSel_T_1, 212, 212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_213 = bits(_out_frontSel_T_1, 213, 213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_214 = bits(_out_frontSel_T_1, 214, 214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_215 = bits(_out_frontSel_T_1, 215, 215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_216 = bits(_out_frontSel_T_1, 216, 216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_217 = bits(_out_frontSel_T_1, 217, 217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_218 = bits(_out_frontSel_T_1, 218, 218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_219 = bits(_out_frontSel_T_1, 219, 219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_220 = bits(_out_frontSel_T_1, 220, 220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_221 = bits(_out_frontSel_T_1, 221, 221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_222 = bits(_out_frontSel_T_1, 222, 222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_223 = bits(_out_frontSel_T_1, 223, 223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_224 = bits(_out_frontSel_T_1, 224, 224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_225 = bits(_out_frontSel_T_1, 225, 225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_226 = bits(_out_frontSel_T_1, 226, 226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_227 = bits(_out_frontSel_T_1, 227, 227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_228 = bits(_out_frontSel_T_1, 228, 228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_229 = bits(_out_frontSel_T_1, 229, 229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_230 = bits(_out_frontSel_T_1, 230, 230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_231 = bits(_out_frontSel_T_1, 231, 231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_232 = bits(_out_frontSel_T_1, 232, 232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_233 = bits(_out_frontSel_T_1, 233, 233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_234 = bits(_out_frontSel_T_1, 234, 234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_235 = bits(_out_frontSel_T_1, 235, 235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_236 = bits(_out_frontSel_T_1, 236, 236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_237 = bits(_out_frontSel_T_1, 237, 237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_238 = bits(_out_frontSel_T_1, 238, 238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_239 = bits(_out_frontSel_T_1, 239, 239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_240 = bits(_out_frontSel_T_1, 240, 240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_241 = bits(_out_frontSel_T_1, 241, 241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_242 = bits(_out_frontSel_T_1, 242, 242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_243 = bits(_out_frontSel_T_1, 243, 243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_244 = bits(_out_frontSel_T_1, 244, 244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_245 = bits(_out_frontSel_T_1, 245, 245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_246 = bits(_out_frontSel_T_1, 246, 246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_247 = bits(_out_frontSel_T_1, 247, 247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_248 = bits(_out_frontSel_T_1, 248, 248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_249 = bits(_out_frontSel_T_1, 249, 249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_250 = bits(_out_frontSel_T_1, 250, 250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_251 = bits(_out_frontSel_T_1, 251, 251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_252 = bits(_out_frontSel_T_1, 252, 252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_253 = bits(_out_frontSel_T_1, 253, 253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_254 = bits(_out_frontSel_T_1, 254, 254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_255 = bits(_out_frontSel_T_1, 255, 255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backSel_T_1 = dshl(UInt<1>(0h1), out_oindex_1) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node out_backSel_0_1 = bits(_out_backSel_T_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_1_1 = bits(_out_backSel_T_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_2_1 = bits(_out_backSel_T_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_3_1 = bits(_out_backSel_T_1, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_4_1 = bits(_out_backSel_T_1, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_5_1 = bits(_out_backSel_T_1, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_6_1 = bits(_out_backSel_T_1, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_7_1 = bits(_out_backSel_T_1, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_8_1 = bits(_out_backSel_T_1, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_9_1 = bits(_out_backSel_T_1, 9, 9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_10_1 = bits(_out_backSel_T_1, 10, 10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_11_1 = bits(_out_backSel_T_1, 11, 11) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_12_1 = bits(_out_backSel_T_1, 12, 12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_13_1 = bits(_out_backSel_T_1, 13, 13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_14_1 = bits(_out_backSel_T_1, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_15_1 = bits(_out_backSel_T_1, 15, 15) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_16_1 = bits(_out_backSel_T_1, 16, 16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_17_1 = bits(_out_backSel_T_1, 17, 17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_18_1 = bits(_out_backSel_T_1, 18, 18) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_19_1 = bits(_out_backSel_T_1, 19, 19) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_20_1 = bits(_out_backSel_T_1, 20, 20) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_21_1 = bits(_out_backSel_T_1, 21, 21) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_22_1 = bits(_out_backSel_T_1, 22, 22) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_23_1 = bits(_out_backSel_T_1, 23, 23) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_24_1 = bits(_out_backSel_T_1, 24, 24) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_25_1 = bits(_out_backSel_T_1, 25, 25) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_26_1 = bits(_out_backSel_T_1, 26, 26) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_27_1 = bits(_out_backSel_T_1, 27, 27) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_28_1 = bits(_out_backSel_T_1, 28, 28) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_29_1 = bits(_out_backSel_T_1, 29, 29) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_30_1 = bits(_out_backSel_T_1, 30, 30) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_31_1 = bits(_out_backSel_T_1, 31, 31) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_32_1 = bits(_out_backSel_T_1, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_33_1 = bits(_out_backSel_T_1, 33, 33) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_34_1 = bits(_out_backSel_T_1, 34, 34) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_35_1 = bits(_out_backSel_T_1, 35, 35) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_36_1 = bits(_out_backSel_T_1, 36, 36) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_37_1 = bits(_out_backSel_T_1, 37, 37) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_38_1 = bits(_out_backSel_T_1, 38, 38) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_39_1 = bits(_out_backSel_T_1, 39, 39) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_40_1 = bits(_out_backSel_T_1, 40, 40) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_41_1 = bits(_out_backSel_T_1, 41, 41) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_42_1 = bits(_out_backSel_T_1, 42, 42) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_43_1 = bits(_out_backSel_T_1, 43, 43) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_44_1 = bits(_out_backSel_T_1, 44, 44) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_45_1 = bits(_out_backSel_T_1, 45, 45) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_46_1 = bits(_out_backSel_T_1, 46, 46) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_47_1 = bits(_out_backSel_T_1, 47, 47) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_48_1 = bits(_out_backSel_T_1, 48, 48) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_49_1 = bits(_out_backSel_T_1, 49, 49) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_50_1 = bits(_out_backSel_T_1, 50, 50) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_51_1 = bits(_out_backSel_T_1, 51, 51) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_52_1 = bits(_out_backSel_T_1, 52, 52) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_53_1 = bits(_out_backSel_T_1, 53, 53) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_54_1 = bits(_out_backSel_T_1, 54, 54) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_55_1 = bits(_out_backSel_T_1, 55, 55) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_56_1 = bits(_out_backSel_T_1, 56, 56) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_57_1 = bits(_out_backSel_T_1, 57, 57) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_58_1 = bits(_out_backSel_T_1, 58, 58) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_59_1 = bits(_out_backSel_T_1, 59, 59) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_60_1 = bits(_out_backSel_T_1, 60, 60) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_61_1 = bits(_out_backSel_T_1, 61, 61) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_62_1 = bits(_out_backSel_T_1, 62, 62) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_63_1 = bits(_out_backSel_T_1, 63, 63) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_64 = bits(_out_backSel_T_1, 64, 64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_65 = bits(_out_backSel_T_1, 65, 65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_66 = bits(_out_backSel_T_1, 66, 66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_67 = bits(_out_backSel_T_1, 67, 67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_68 = bits(_out_backSel_T_1, 68, 68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_69 = bits(_out_backSel_T_1, 69, 69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_70 = bits(_out_backSel_T_1, 70, 70) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_71 = bits(_out_backSel_T_1, 71, 71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_72 = bits(_out_backSel_T_1, 72, 72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_73 = bits(_out_backSel_T_1, 73, 73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_74 = bits(_out_backSel_T_1, 74, 74) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_75 = bits(_out_backSel_T_1, 75, 75) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_76 = bits(_out_backSel_T_1, 76, 76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_77 = bits(_out_backSel_T_1, 77, 77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_78 = bits(_out_backSel_T_1, 78, 78) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_79 = bits(_out_backSel_T_1, 79, 79) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_80 = bits(_out_backSel_T_1, 80, 80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_81 = bits(_out_backSel_T_1, 81, 81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_82 = bits(_out_backSel_T_1, 82, 82) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_83 = bits(_out_backSel_T_1, 83, 83) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_84 = bits(_out_backSel_T_1, 84, 84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_85 = bits(_out_backSel_T_1, 85, 85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_86 = bits(_out_backSel_T_1, 86, 86) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_87 = bits(_out_backSel_T_1, 87, 87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_88 = bits(_out_backSel_T_1, 88, 88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_89 = bits(_out_backSel_T_1, 89, 89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_90 = bits(_out_backSel_T_1, 90, 90) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_91 = bits(_out_backSel_T_1, 91, 91) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_92 = bits(_out_backSel_T_1, 92, 92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_93 = bits(_out_backSel_T_1, 93, 93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_94 = bits(_out_backSel_T_1, 94, 94) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_95 = bits(_out_backSel_T_1, 95, 95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_96 = bits(_out_backSel_T_1, 96, 96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_97 = bits(_out_backSel_T_1, 97, 97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_98 = bits(_out_backSel_T_1, 98, 98) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_99 = bits(_out_backSel_T_1, 99, 99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_100 = bits(_out_backSel_T_1, 100, 100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_101 = bits(_out_backSel_T_1, 101, 101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_102 = bits(_out_backSel_T_1, 102, 102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_103 = bits(_out_backSel_T_1, 103, 103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_104 = bits(_out_backSel_T_1, 104, 104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_105 = bits(_out_backSel_T_1, 105, 105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_106 = bits(_out_backSel_T_1, 106, 106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_107 = bits(_out_backSel_T_1, 107, 107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_108 = bits(_out_backSel_T_1, 108, 108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_109 = bits(_out_backSel_T_1, 109, 109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_110 = bits(_out_backSel_T_1, 110, 110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_111 = bits(_out_backSel_T_1, 111, 111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_112 = bits(_out_backSel_T_1, 112, 112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_113 = bits(_out_backSel_T_1, 113, 113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_114 = bits(_out_backSel_T_1, 114, 114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_115 = bits(_out_backSel_T_1, 115, 115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_116 = bits(_out_backSel_T_1, 116, 116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_117 = bits(_out_backSel_T_1, 117, 117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_118 = bits(_out_backSel_T_1, 118, 118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_119 = bits(_out_backSel_T_1, 119, 119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_120 = bits(_out_backSel_T_1, 120, 120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_121 = bits(_out_backSel_T_1, 121, 121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_122 = bits(_out_backSel_T_1, 122, 122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_123 = bits(_out_backSel_T_1, 123, 123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_124 = bits(_out_backSel_T_1, 124, 124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_125 = bits(_out_backSel_T_1, 125, 125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_126 = bits(_out_backSel_T_1, 126, 126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_127 = bits(_out_backSel_T_1, 127, 127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_128 = bits(_out_backSel_T_1, 128, 128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_129 = bits(_out_backSel_T_1, 129, 129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_130 = bits(_out_backSel_T_1, 130, 130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_131 = bits(_out_backSel_T_1, 131, 131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_132 = bits(_out_backSel_T_1, 132, 132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_133 = bits(_out_backSel_T_1, 133, 133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_134 = bits(_out_backSel_T_1, 134, 134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_135 = bits(_out_backSel_T_1, 135, 135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_136 = bits(_out_backSel_T_1, 136, 136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_137 = bits(_out_backSel_T_1, 137, 137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_138 = bits(_out_backSel_T_1, 138, 138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_139 = bits(_out_backSel_T_1, 139, 139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_140 = bits(_out_backSel_T_1, 140, 140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_141 = bits(_out_backSel_T_1, 141, 141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_142 = bits(_out_backSel_T_1, 142, 142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_143 = bits(_out_backSel_T_1, 143, 143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_144 = bits(_out_backSel_T_1, 144, 144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_145 = bits(_out_backSel_T_1, 145, 145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_146 = bits(_out_backSel_T_1, 146, 146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_147 = bits(_out_backSel_T_1, 147, 147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_148 = bits(_out_backSel_T_1, 148, 148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_149 = bits(_out_backSel_T_1, 149, 149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_150 = bits(_out_backSel_T_1, 150, 150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_151 = bits(_out_backSel_T_1, 151, 151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_152 = bits(_out_backSel_T_1, 152, 152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_153 = bits(_out_backSel_T_1, 153, 153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_154 = bits(_out_backSel_T_1, 154, 154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_155 = bits(_out_backSel_T_1, 155, 155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_156 = bits(_out_backSel_T_1, 156, 156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_157 = bits(_out_backSel_T_1, 157, 157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_158 = bits(_out_backSel_T_1, 158, 158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_159 = bits(_out_backSel_T_1, 159, 159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_160 = bits(_out_backSel_T_1, 160, 160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_161 = bits(_out_backSel_T_1, 161, 161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_162 = bits(_out_backSel_T_1, 162, 162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_163 = bits(_out_backSel_T_1, 163, 163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_164 = bits(_out_backSel_T_1, 164, 164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_165 = bits(_out_backSel_T_1, 165, 165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_166 = bits(_out_backSel_T_1, 166, 166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_167 = bits(_out_backSel_T_1, 167, 167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_168 = bits(_out_backSel_T_1, 168, 168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_169 = bits(_out_backSel_T_1, 169, 169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_170 = bits(_out_backSel_T_1, 170, 170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_171 = bits(_out_backSel_T_1, 171, 171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_172 = bits(_out_backSel_T_1, 172, 172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_173 = bits(_out_backSel_T_1, 173, 173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_174 = bits(_out_backSel_T_1, 174, 174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_175 = bits(_out_backSel_T_1, 175, 175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_176 = bits(_out_backSel_T_1, 176, 176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_177 = bits(_out_backSel_T_1, 177, 177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_178 = bits(_out_backSel_T_1, 178, 178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_179 = bits(_out_backSel_T_1, 179, 179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_180 = bits(_out_backSel_T_1, 180, 180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_181 = bits(_out_backSel_T_1, 181, 181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_182 = bits(_out_backSel_T_1, 182, 182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_183 = bits(_out_backSel_T_1, 183, 183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_184 = bits(_out_backSel_T_1, 184, 184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_185 = bits(_out_backSel_T_1, 185, 185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_186 = bits(_out_backSel_T_1, 186, 186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_187 = bits(_out_backSel_T_1, 187, 187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_188 = bits(_out_backSel_T_1, 188, 188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_189 = bits(_out_backSel_T_1, 189, 189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_190 = bits(_out_backSel_T_1, 190, 190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_191 = bits(_out_backSel_T_1, 191, 191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_192 = bits(_out_backSel_T_1, 192, 192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_193 = bits(_out_backSel_T_1, 193, 193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_194 = bits(_out_backSel_T_1, 194, 194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_195 = bits(_out_backSel_T_1, 195, 195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_196 = bits(_out_backSel_T_1, 196, 196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_197 = bits(_out_backSel_T_1, 197, 197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_198 = bits(_out_backSel_T_1, 198, 198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_199 = bits(_out_backSel_T_1, 199, 199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_200 = bits(_out_backSel_T_1, 200, 200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_201 = bits(_out_backSel_T_1, 201, 201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_202 = bits(_out_backSel_T_1, 202, 202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_203 = bits(_out_backSel_T_1, 203, 203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_204 = bits(_out_backSel_T_1, 204, 204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_205 = bits(_out_backSel_T_1, 205, 205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_206 = bits(_out_backSel_T_1, 206, 206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_207 = bits(_out_backSel_T_1, 207, 207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_208 = bits(_out_backSel_T_1, 208, 208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_209 = bits(_out_backSel_T_1, 209, 209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_210 = bits(_out_backSel_T_1, 210, 210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_211 = bits(_out_backSel_T_1, 211, 211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_212 = bits(_out_backSel_T_1, 212, 212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_213 = bits(_out_backSel_T_1, 213, 213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_214 = bits(_out_backSel_T_1, 214, 214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_215 = bits(_out_backSel_T_1, 215, 215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_216 = bits(_out_backSel_T_1, 216, 216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_217 = bits(_out_backSel_T_1, 217, 217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_218 = bits(_out_backSel_T_1, 218, 218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_219 = bits(_out_backSel_T_1, 219, 219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_220 = bits(_out_backSel_T_1, 220, 220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_221 = bits(_out_backSel_T_1, 221, 221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_222 = bits(_out_backSel_T_1, 222, 222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_223 = bits(_out_backSel_T_1, 223, 223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_224 = bits(_out_backSel_T_1, 224, 224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_225 = bits(_out_backSel_T_1, 225, 225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_226 = bits(_out_backSel_T_1, 226, 226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_227 = bits(_out_backSel_T_1, 227, 227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_228 = bits(_out_backSel_T_1, 228, 228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_229 = bits(_out_backSel_T_1, 229, 229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_230 = bits(_out_backSel_T_1, 230, 230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_231 = bits(_out_backSel_T_1, 231, 231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_232 = bits(_out_backSel_T_1, 232, 232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_233 = bits(_out_backSel_T_1, 233, 233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_234 = bits(_out_backSel_T_1, 234, 234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_235 = bits(_out_backSel_T_1, 235, 235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_236 = bits(_out_backSel_T_1, 236, 236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_237 = bits(_out_backSel_T_1, 237, 237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_238 = bits(_out_backSel_T_1, 238, 238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_239 = bits(_out_backSel_T_1, 239, 239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_240 = bits(_out_backSel_T_1, 240, 240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_241 = bits(_out_backSel_T_1, 241, 241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_242 = bits(_out_backSel_T_1, 242, 242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_243 = bits(_out_backSel_T_1, 243, 243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_244 = bits(_out_backSel_T_1, 244, 244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_245 = bits(_out_backSel_T_1, 245, 245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_246 = bits(_out_backSel_T_1, 246, 246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_247 = bits(_out_backSel_T_1, 247, 247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_248 = bits(_out_backSel_T_1, 248, 248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_249 = bits(_out_backSel_T_1, 249, 249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_250 = bits(_out_backSel_T_1, 250, 250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_251 = bits(_out_backSel_T_1, 251, 251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_252 = bits(_out_backSel_T_1, 252, 252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_253 = bits(_out_backSel_T_1, 253, 253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_254 = bits(_out_backSel_T_1, 254, 254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_255 = bits(_out_backSel_T_1, 255, 255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_259 = and(in_1.valid, out_front_1.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_260 = and(_out_rifireMux_T_259, out_front_1.bits.read) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_64 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_261 = and(_out_rifireMux_T_260, out_frontSel_0_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_262 = and(_out_rifireMux_T_261, _out_T_1438) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_64, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[450], _out_rifireMux_T_262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[449], _out_rifireMux_T_262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[448], _out_rifireMux_T_262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[447], _out_rifireMux_T_262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[446], _out_rifireMux_T_262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[445], _out_rifireMux_T_262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[444], _out_rifireMux_T_262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[443], _out_rifireMux_T_262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_263 = eq(_out_T_1438, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_264 = or(out_rifireMux_out_64, _out_rifireMux_T_263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_65 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_265 = and(_out_rifireMux_T_260, out_frontSel_1_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_266 = and(_out_rifireMux_T_265, _out_T_1346) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_65, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[95], _out_rifireMux_T_266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[94], _out_rifireMux_T_266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[93], _out_rifireMux_T_266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[92], _out_rifireMux_T_266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[91], _out_rifireMux_T_266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[90], _out_rifireMux_T_266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[89], _out_rifireMux_T_266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[88], _out_rifireMux_T_266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_267 = eq(_out_T_1346, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_268 = or(out_rifireMux_out_65, _out_rifireMux_T_267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_66 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_269 = and(_out_rifireMux_T_260, out_frontSel_2_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_270 = and(_out_rifireMux_T_269, _out_T_1566) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_66, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[946], _out_rifireMux_T_270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[945], _out_rifireMux_T_270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[944], _out_rifireMux_T_270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[943], _out_rifireMux_T_270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[942], _out_rifireMux_T_270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[941], _out_rifireMux_T_270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[940], _out_rifireMux_T_270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[939], _out_rifireMux_T_270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_271 = eq(_out_T_1566, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_272 = or(out_rifireMux_out_66, _out_rifireMux_T_271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_67 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_273 = and(_out_rifireMux_T_260, out_frontSel_3_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_274 = and(_out_rifireMux_T_273, _out_T_1478) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_67, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[600], _out_rifireMux_T_274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[599], _out_rifireMux_T_274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[598], _out_rifireMux_T_274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[597], _out_rifireMux_T_274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[596], _out_rifireMux_T_274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[595], _out_rifireMux_T_274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[594], _out_rifireMux_T_274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[593], _out_rifireMux_T_274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_275 = eq(_out_T_1478, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_276 = or(out_rifireMux_out_67, _out_rifireMux_T_275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_68 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_277 = and(_out_rifireMux_T_260, out_frontSel_4_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_278 = and(_out_rifireMux_T_277, _out_T_1400) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_68, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[311], _out_rifireMux_T_278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[310], _out_rifireMux_T_278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[309], _out_rifireMux_T_278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[308], _out_rifireMux_T_278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[307], _out_rifireMux_T_278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[306], _out_rifireMux_T_278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[305], _out_rifireMux_T_278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[304], _out_rifireMux_T_278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_279 = eq(_out_T_1400, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_280 = or(out_rifireMux_out_68, _out_rifireMux_T_279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_69 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_281 = and(_out_rifireMux_T_260, out_frontSel_5_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_282 = and(_out_rifireMux_T_281, _out_T_1362) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_69, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[159], _out_rifireMux_T_282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[158], _out_rifireMux_T_282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[157], _out_rifireMux_T_282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[156], _out_rifireMux_T_282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[155], _out_rifireMux_T_282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[154], _out_rifireMux_T_282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[153], _out_rifireMux_T_282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[152], _out_rifireMux_T_282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_283 = eq(_out_T_1362, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_284 = or(out_rifireMux_out_69, _out_rifireMux_T_283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_70 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_285 = and(_out_rifireMux_T_260, out_frontSel_6_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_286 = and(_out_rifireMux_T_285, _out_T_1594) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_70, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1058], _out_rifireMux_T_286 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1057], _out_rifireMux_T_286 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1056], _out_rifireMux_T_286 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1055], _out_rifireMux_T_286 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1054], _out_rifireMux_T_286 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1053], _out_rifireMux_T_286 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1052], _out_rifireMux_T_286 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1051], _out_rifireMux_T_286 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_287 = eq(_out_T_1594, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_288 = or(out_rifireMux_out_70, _out_rifireMux_T_287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_71 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_289 = and(_out_rifireMux_T_260, out_frontSel_7_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_290 = and(_out_rifireMux_T_289, _out_T_1542) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_71, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[850], _out_rifireMux_T_290 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[849], _out_rifireMux_T_290 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[848], _out_rifireMux_T_290 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[847], _out_rifireMux_T_290 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[846], _out_rifireMux_T_290 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[845], _out_rifireMux_T_290 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[844], _out_rifireMux_T_290 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[843], _out_rifireMux_T_290 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_291 = eq(_out_T_1542, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_292 = or(out_rifireMux_out_71, _out_rifireMux_T_291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_72 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_293 = and(_out_rifireMux_T_260, out_frontSel_8_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_294 = and(_out_rifireMux_T_293, _out_T_1464) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_72, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[544], _out_rifireMux_T_294 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[543], _out_rifireMux_T_294 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[542], _out_rifireMux_T_294 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[541], _out_rifireMux_T_294 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[540], _out_rifireMux_T_294 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[539], _out_rifireMux_T_294 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[538], _out_rifireMux_T_294 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[537], _out_rifireMux_T_294 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_295 = eq(_out_T_1464, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_296 = or(out_rifireMux_out_72, _out_rifireMux_T_295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_73 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_297 = and(_out_rifireMux_T_260, out_frontSel_9_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_298 = and(_out_rifireMux_T_297, _out_T_1388) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_73, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[263], _out_rifireMux_T_298 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[262], _out_rifireMux_T_298 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[261], _out_rifireMux_T_298 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[260], _out_rifireMux_T_298 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[259], _out_rifireMux_T_298 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[258], _out_rifireMux_T_298 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[257], _out_rifireMux_T_298 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[256], _out_rifireMux_T_298 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_299 = eq(_out_T_1388, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_300 = or(out_rifireMux_out_73, _out_rifireMux_T_299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_74 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_301 = and(_out_rifireMux_T_260, out_frontSel_10_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_302 = and(_out_rifireMux_T_301, _out_T_1446) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_74, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[478], _out_rifireMux_T_302 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[477], _out_rifireMux_T_302 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[476], _out_rifireMux_T_302 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[475], _out_rifireMux_T_302 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_303 = eq(_out_T_1446, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_304 = or(out_rifireMux_out_74, _out_rifireMux_T_303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_75 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_305 = and(_out_rifireMux_T_260, out_frontSel_11_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_306 = and(_out_rifireMux_T_305, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_75, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_307 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_308 = or(out_rifireMux_out_75, _out_rifireMux_T_307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_76 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_309 = and(_out_rifireMux_T_260, out_frontSel_12_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_310 = and(_out_rifireMux_T_309, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_76, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_311 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_312 = or(out_rifireMux_out_76, _out_rifireMux_T_311) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_77 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_313 = and(_out_rifireMux_T_260, out_frontSel_13_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_314 = and(_out_rifireMux_T_313, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_77, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_315 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_316 = or(out_rifireMux_out_77, _out_rifireMux_T_315) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_78 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_317 = and(_out_rifireMux_T_260, out_frontSel_14_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_318 = and(_out_rifireMux_T_317, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_78, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_319 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_320 = or(out_rifireMux_out_78, _out_rifireMux_T_319) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_79 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_321 = and(_out_rifireMux_T_260, out_frontSel_15_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_322 = and(_out_rifireMux_T_321, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_79, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_323 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_324 = or(out_rifireMux_out_79, _out_rifireMux_T_323) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_80 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_325 = and(_out_rifireMux_T_260, out_frontSel_16_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_326 = and(_out_rifireMux_T_325, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_80, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_327 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_328 = or(out_rifireMux_out_80, _out_rifireMux_T_327) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_81 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_329 = and(_out_rifireMux_T_260, out_frontSel_17_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_330 = and(_out_rifireMux_T_329, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_81, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_331 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_332 = or(out_rifireMux_out_81, _out_rifireMux_T_331) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_82 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_333 = and(_out_rifireMux_T_260, out_frontSel_18_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_334 = and(_out_rifireMux_T_333, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_82, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_335 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_336 = or(out_rifireMux_out_82, _out_rifireMux_T_335) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_83 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_337 = and(_out_rifireMux_T_260, out_frontSel_19_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_338 = and(_out_rifireMux_T_337, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_83, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_339 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_340 = or(out_rifireMux_out_83, _out_rifireMux_T_339) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_84 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_341 = and(_out_rifireMux_T_260, out_frontSel_20_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_342 = and(_out_rifireMux_T_341, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_84, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_343 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_344 = or(out_rifireMux_out_84, _out_rifireMux_T_343) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_85 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_345 = and(_out_rifireMux_T_260, out_frontSel_21_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_346 = and(_out_rifireMux_T_345, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_85, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_347 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_348 = or(out_rifireMux_out_85, _out_rifireMux_T_347) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_86 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_349 = and(_out_rifireMux_T_260, out_frontSel_22_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_350 = and(_out_rifireMux_T_349, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_86, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_351 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_352 = or(out_rifireMux_out_86, _out_rifireMux_T_351) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_87 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_353 = and(_out_rifireMux_T_260, out_frontSel_23_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_354 = and(_out_rifireMux_T_353, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_87, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_355 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_356 = or(out_rifireMux_out_87, _out_rifireMux_T_355) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_88 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_357 = and(_out_rifireMux_T_260, out_frontSel_24_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_358 = and(_out_rifireMux_T_357, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_88, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_359 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_360 = or(out_rifireMux_out_88, _out_rifireMux_T_359) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_89 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_361 = and(_out_rifireMux_T_260, out_frontSel_25_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_362 = and(_out_rifireMux_T_361, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_89, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_363 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_364 = or(out_rifireMux_out_89, _out_rifireMux_T_363) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_90 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_365 = and(_out_rifireMux_T_260, out_frontSel_26_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_366 = and(_out_rifireMux_T_365, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_90, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_367 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_368 = or(out_rifireMux_out_90, _out_rifireMux_T_367) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_91 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_369 = and(_out_rifireMux_T_260, out_frontSel_27_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_370 = and(_out_rifireMux_T_369, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_91, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_371 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_372 = or(out_rifireMux_out_91, _out_rifireMux_T_371) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_92 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_373 = and(_out_rifireMux_T_260, out_frontSel_28_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_374 = and(_out_rifireMux_T_373, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_92, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_375 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_376 = or(out_rifireMux_out_92, _out_rifireMux_T_375) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_93 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_377 = and(_out_rifireMux_T_260, out_frontSel_29_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_378 = and(_out_rifireMux_T_377, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_93, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_379 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_380 = or(out_rifireMux_out_93, _out_rifireMux_T_379) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_94 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_381 = and(_out_rifireMux_T_260, out_frontSel_30_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_382 = and(_out_rifireMux_T_381, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_94, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_383 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_384 = or(out_rifireMux_out_94, _out_rifireMux_T_383) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_95 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_385 = and(_out_rifireMux_T_260, out_frontSel_31_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_386 = and(_out_rifireMux_T_385, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_95, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_387 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_388 = or(out_rifireMux_out_95, _out_rifireMux_T_387) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_96 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_389 = and(_out_rifireMux_T_260, out_frontSel_32_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_390 = and(_out_rifireMux_T_389, _out_T_1460) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_96, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[528], _out_rifireMux_T_390 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[527], _out_rifireMux_T_390 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_391 = eq(_out_T_1460, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_392 = or(out_rifireMux_out_96, _out_rifireMux_T_391) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_97 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_393 = and(_out_rifireMux_T_260, out_frontSel_33_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_394 = and(_out_rifireMux_T_393, _out_T_1410) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_97, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[345], _out_rifireMux_T_394 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[344], _out_rifireMux_T_394 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_395 = eq(_out_T_1410, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_396 = or(out_rifireMux_out_97, _out_rifireMux_T_395) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_98 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_397 = and(_out_rifireMux_T_260, out_frontSel_34_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_398 = and(_out_rifireMux_T_397, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_98, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_399 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_400 = or(out_rifireMux_out_98, _out_rifireMux_T_399) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_99 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_401 = and(_out_rifireMux_T_260, out_frontSel_35_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_402 = and(_out_rifireMux_T_401, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_99, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_403 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_404 = or(out_rifireMux_out_99, _out_rifireMux_T_403) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_100 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_405 = and(_out_rifireMux_T_260, out_frontSel_36_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_406 = and(_out_rifireMux_T_405, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_100, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_407 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_408 = or(out_rifireMux_out_100, _out_rifireMux_T_407) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_101 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_409 = and(_out_rifireMux_T_260, out_frontSel_37_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_410 = and(_out_rifireMux_T_409, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_101, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_411 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_412 = or(out_rifireMux_out_101, _out_rifireMux_T_411) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_102 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_413 = and(_out_rifireMux_T_260, out_frontSel_38_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_414 = and(_out_rifireMux_T_413, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_102, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_415 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_416 = or(out_rifireMux_out_102, _out_rifireMux_T_415) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_103 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_417 = and(_out_rifireMux_T_260, out_frontSel_39_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_418 = and(_out_rifireMux_T_417, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_103, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_419 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_420 = or(out_rifireMux_out_103, _out_rifireMux_T_419) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_104 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_421 = and(_out_rifireMux_T_260, out_frontSel_40_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_422 = and(_out_rifireMux_T_421, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_104, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_423 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_424 = or(out_rifireMux_out_104, _out_rifireMux_T_423) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_105 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_425 = and(_out_rifireMux_T_260, out_frontSel_41_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_426 = and(_out_rifireMux_T_425, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_105, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_427 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_428 = or(out_rifireMux_out_105, _out_rifireMux_T_427) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_106 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_429 = and(_out_rifireMux_T_260, out_frontSel_42_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_430 = and(_out_rifireMux_T_429, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_106, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_431 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_432 = or(out_rifireMux_out_106, _out_rifireMux_T_431) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_107 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_433 = and(_out_rifireMux_T_260, out_frontSel_43_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_434 = and(_out_rifireMux_T_433, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_107, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_435 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_436 = or(out_rifireMux_out_107, _out_rifireMux_T_435) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_108 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_437 = and(_out_rifireMux_T_260, out_frontSel_44_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_438 = and(_out_rifireMux_T_437, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_108, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_439 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_440 = or(out_rifireMux_out_108, _out_rifireMux_T_439) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_109 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_441 = and(_out_rifireMux_T_260, out_frontSel_45_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_442 = and(_out_rifireMux_T_441, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_109, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_443 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_444 = or(out_rifireMux_out_109, _out_rifireMux_T_443) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_110 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_445 = and(_out_rifireMux_T_260, out_frontSel_46_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_446 = and(_out_rifireMux_T_445, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_110, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_447 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_448 = or(out_rifireMux_out_110, _out_rifireMux_T_447) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_111 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_449 = and(_out_rifireMux_T_260, out_frontSel_47_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_450 = and(_out_rifireMux_T_449, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_111, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_451 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_452 = or(out_rifireMux_out_111, _out_rifireMux_T_451) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_112 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_453 = and(_out_rifireMux_T_260, out_frontSel_48_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_454 = and(_out_rifireMux_T_453, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_112, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_455 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_456 = or(out_rifireMux_out_112, _out_rifireMux_T_455) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_113 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_457 = and(_out_rifireMux_T_260, out_frontSel_49_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_458 = and(_out_rifireMux_T_457, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_113, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_459 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_460 = or(out_rifireMux_out_113, _out_rifireMux_T_459) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_114 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_461 = and(_out_rifireMux_T_260, out_frontSel_50_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_462 = and(_out_rifireMux_T_461, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_114, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_463 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_464 = or(out_rifireMux_out_114, _out_rifireMux_T_463) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_115 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_465 = and(_out_rifireMux_T_260, out_frontSel_51_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_466 = and(_out_rifireMux_T_465, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_115, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_467 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_468 = or(out_rifireMux_out_115, _out_rifireMux_T_467) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_116 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_469 = and(_out_rifireMux_T_260, out_frontSel_52_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_470 = and(_out_rifireMux_T_469, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_116, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_471 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_472 = or(out_rifireMux_out_116, _out_rifireMux_T_471) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_117 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_473 = and(_out_rifireMux_T_260, out_frontSel_53_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_474 = and(_out_rifireMux_T_473, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_117, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_475 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_476 = or(out_rifireMux_out_117, _out_rifireMux_T_475) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_118 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_477 = and(_out_rifireMux_T_260, out_frontSel_54_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_478 = and(_out_rifireMux_T_477, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_118, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_479 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_480 = or(out_rifireMux_out_118, _out_rifireMux_T_479) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_119 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_481 = and(_out_rifireMux_T_260, out_frontSel_55_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_482 = and(_out_rifireMux_T_481, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_119, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_483 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_484 = or(out_rifireMux_out_119, _out_rifireMux_T_483) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_120 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_485 = and(_out_rifireMux_T_260, out_frontSel_56_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_486 = and(_out_rifireMux_T_485, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_120, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_487 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_488 = or(out_rifireMux_out_120, _out_rifireMux_T_487) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_121 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_489 = and(_out_rifireMux_T_260, out_frontSel_57_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_490 = and(_out_rifireMux_T_489, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_121, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_491 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_492 = or(out_rifireMux_out_121, _out_rifireMux_T_491) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_122 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_493 = and(_out_rifireMux_T_260, out_frontSel_58_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_494 = and(_out_rifireMux_T_493, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_122, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_495 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_496 = or(out_rifireMux_out_122, _out_rifireMux_T_495) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_123 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_497 = and(_out_rifireMux_T_260, out_frontSel_59_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_498 = and(_out_rifireMux_T_497, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_123, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_499 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_500 = or(out_rifireMux_out_123, _out_rifireMux_T_499) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_124 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_501 = and(_out_rifireMux_T_260, out_frontSel_60_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_502 = and(_out_rifireMux_T_501, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_124, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_503 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_504 = or(out_rifireMux_out_124, _out_rifireMux_T_503) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_125 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_505 = and(_out_rifireMux_T_260, out_frontSel_61_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_506 = and(_out_rifireMux_T_505, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_125, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_507 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_508 = or(out_rifireMux_out_125, _out_rifireMux_T_507) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_126 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_509 = and(_out_rifireMux_T_260, out_frontSel_62_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_510 = and(_out_rifireMux_T_509, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_126, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_511 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_512 = or(out_rifireMux_out_126, _out_rifireMux_T_511) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_127 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_513 = and(_out_rifireMux_T_260, out_frontSel_63_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_514 = and(_out_rifireMux_T_513, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_127, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_515 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_516 = or(out_rifireMux_out_127, _out_rifireMux_T_515) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_128 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_517 = and(_out_rifireMux_T_260, out_frontSel_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_518 = and(_out_rifireMux_T_517, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_128, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_519 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_520 = or(out_rifireMux_out_128, _out_rifireMux_T_519) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_129 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_521 = and(_out_rifireMux_T_260, out_frontSel_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_522 = and(_out_rifireMux_T_521, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_129, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_523 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_524 = or(out_rifireMux_out_129, _out_rifireMux_T_523) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_130 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_525 = and(_out_rifireMux_T_260, out_frontSel_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_526 = and(_out_rifireMux_T_525, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_130, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_527 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_528 = or(out_rifireMux_out_130, _out_rifireMux_T_527) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_131 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_529 = and(_out_rifireMux_T_260, out_frontSel_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_530 = and(_out_rifireMux_T_529, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_131, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_531 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_532 = or(out_rifireMux_out_131, _out_rifireMux_T_531) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_132 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_533 = and(_out_rifireMux_T_260, out_frontSel_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_534 = and(_out_rifireMux_T_533, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_132, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_535 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_536 = or(out_rifireMux_out_132, _out_rifireMux_T_535) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_133 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_537 = and(_out_rifireMux_T_260, out_frontSel_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_538 = and(_out_rifireMux_T_537, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_133, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_539 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_540 = or(out_rifireMux_out_133, _out_rifireMux_T_539) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_134 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_541 = and(_out_rifireMux_T_260, out_frontSel_70) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_542 = and(_out_rifireMux_T_541, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_134, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_543 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_544 = or(out_rifireMux_out_134, _out_rifireMux_T_543) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_135 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_545 = and(_out_rifireMux_T_260, out_frontSel_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_546 = and(_out_rifireMux_T_545, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_135, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_547 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_548 = or(out_rifireMux_out_135, _out_rifireMux_T_547) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_136 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_549 = and(_out_rifireMux_T_260, out_frontSel_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_550 = and(_out_rifireMux_T_549, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_136, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_551 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_552 = or(out_rifireMux_out_136, _out_rifireMux_T_551) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_137 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_553 = and(_out_rifireMux_T_260, out_frontSel_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_554 = and(_out_rifireMux_T_553, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_137, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_555 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_556 = or(out_rifireMux_out_137, _out_rifireMux_T_555) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_138 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_557 = and(_out_rifireMux_T_260, out_frontSel_74) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_558 = and(_out_rifireMux_T_557, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_138, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_559 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_560 = or(out_rifireMux_out_138, _out_rifireMux_T_559) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_139 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_561 = and(_out_rifireMux_T_260, out_frontSel_75) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_562 = and(_out_rifireMux_T_561, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_139, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_563 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_564 = or(out_rifireMux_out_139, _out_rifireMux_T_563) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_140 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_565 = and(_out_rifireMux_T_260, out_frontSel_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_566 = and(_out_rifireMux_T_565, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_140, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_567 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_568 = or(out_rifireMux_out_140, _out_rifireMux_T_567) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_141 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_569 = and(_out_rifireMux_T_260, out_frontSel_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_570 = and(_out_rifireMux_T_569, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_141, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_571 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_572 = or(out_rifireMux_out_141, _out_rifireMux_T_571) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_142 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_573 = and(_out_rifireMux_T_260, out_frontSel_78) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_574 = and(_out_rifireMux_T_573, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_142, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_575 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_576 = or(out_rifireMux_out_142, _out_rifireMux_T_575) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_143 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_577 = and(_out_rifireMux_T_260, out_frontSel_79) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_578 = and(_out_rifireMux_T_577, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_143, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_579 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_580 = or(out_rifireMux_out_143, _out_rifireMux_T_579) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_144 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_581 = and(_out_rifireMux_T_260, out_frontSel_80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_582 = and(_out_rifireMux_T_581, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_144, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_583 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_584 = or(out_rifireMux_out_144, _out_rifireMux_T_583) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_145 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_585 = and(_out_rifireMux_T_260, out_frontSel_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_586 = and(_out_rifireMux_T_585, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_145, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_587 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_588 = or(out_rifireMux_out_145, _out_rifireMux_T_587) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_146 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_589 = and(_out_rifireMux_T_260, out_frontSel_82) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_590 = and(_out_rifireMux_T_589, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_146, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_591 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_592 = or(out_rifireMux_out_146, _out_rifireMux_T_591) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_147 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_593 = and(_out_rifireMux_T_260, out_frontSel_83) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_594 = and(_out_rifireMux_T_593, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_147, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_595 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_596 = or(out_rifireMux_out_147, _out_rifireMux_T_595) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_148 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_597 = and(_out_rifireMux_T_260, out_frontSel_84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_598 = and(_out_rifireMux_T_597, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_148, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_599 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_600 = or(out_rifireMux_out_148, _out_rifireMux_T_599) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_149 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_601 = and(_out_rifireMux_T_260, out_frontSel_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_602 = and(_out_rifireMux_T_601, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_149, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_603 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_604 = or(out_rifireMux_out_149, _out_rifireMux_T_603) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_150 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_605 = and(_out_rifireMux_T_260, out_frontSel_86) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_606 = and(_out_rifireMux_T_605, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_150, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_607 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_608 = or(out_rifireMux_out_150, _out_rifireMux_T_607) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_151 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_609 = and(_out_rifireMux_T_260, out_frontSel_87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_610 = and(_out_rifireMux_T_609, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_151, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_611 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_612 = or(out_rifireMux_out_151, _out_rifireMux_T_611) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_152 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_613 = and(_out_rifireMux_T_260, out_frontSel_88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_614 = and(_out_rifireMux_T_613, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_152, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_615 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_616 = or(out_rifireMux_out_152, _out_rifireMux_T_615) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_153 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_617 = and(_out_rifireMux_T_260, out_frontSel_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_618 = and(_out_rifireMux_T_617, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_153, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_619 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_620 = or(out_rifireMux_out_153, _out_rifireMux_T_619) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_154 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_621 = and(_out_rifireMux_T_260, out_frontSel_90) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_622 = and(_out_rifireMux_T_621, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_154, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_623 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_624 = or(out_rifireMux_out_154, _out_rifireMux_T_623) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_155 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_625 = and(_out_rifireMux_T_260, out_frontSel_91) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_626 = and(_out_rifireMux_T_625, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_155, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_627 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_628 = or(out_rifireMux_out_155, _out_rifireMux_T_627) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_156 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_629 = and(_out_rifireMux_T_260, out_frontSel_92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_630 = and(_out_rifireMux_T_629, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_156, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_631 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_632 = or(out_rifireMux_out_156, _out_rifireMux_T_631) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_157 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_633 = and(_out_rifireMux_T_260, out_frontSel_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_634 = and(_out_rifireMux_T_633, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_157, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_635 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_636 = or(out_rifireMux_out_157, _out_rifireMux_T_635) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_158 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_637 = and(_out_rifireMux_T_260, out_frontSel_94) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_638 = and(_out_rifireMux_T_637, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_158, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_639 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_640 = or(out_rifireMux_out_158, _out_rifireMux_T_639) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_159 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_641 = and(_out_rifireMux_T_260, out_frontSel_95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_642 = and(_out_rifireMux_T_641, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_159, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_643 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_644 = or(out_rifireMux_out_159, _out_rifireMux_T_643) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_160 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_645 = and(_out_rifireMux_T_260, out_frontSel_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_646 = and(_out_rifireMux_T_645, _out_T_1434) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_160, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[434], _out_rifireMux_T_646 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_647 = eq(_out_T_1434, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_648 = or(out_rifireMux_out_160, _out_rifireMux_T_647) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_161 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_649 = and(_out_rifireMux_T_260, out_frontSel_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_650 = and(_out_rifireMux_T_649, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_161, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_651 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_652 = or(out_rifireMux_out_161, _out_rifireMux_T_651) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_162 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_653 = and(_out_rifireMux_T_260, out_frontSel_98) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_654 = and(_out_rifireMux_T_653, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_162, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_655 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_656 = or(out_rifireMux_out_162, _out_rifireMux_T_655) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_163 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_657 = and(_out_rifireMux_T_260, out_frontSel_99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_658 = and(_out_rifireMux_T_657, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_163, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_659 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_660 = or(out_rifireMux_out_163, _out_rifireMux_T_659) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_164 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_661 = and(_out_rifireMux_T_260, out_frontSel_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_662 = and(_out_rifireMux_T_661, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_164, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_663 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_664 = or(out_rifireMux_out_164, _out_rifireMux_T_663) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_165 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_665 = and(_out_rifireMux_T_260, out_frontSel_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_666 = and(_out_rifireMux_T_665, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_165, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_667 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_668 = or(out_rifireMux_out_165, _out_rifireMux_T_667) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_166 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_669 = and(_out_rifireMux_T_260, out_frontSel_102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_670 = and(_out_rifireMux_T_669, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_166, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_671 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_672 = or(out_rifireMux_out_166, _out_rifireMux_T_671) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_167 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_673 = and(_out_rifireMux_T_260, out_frontSel_103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_674 = and(_out_rifireMux_T_673, _out_T_1500) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_167, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[682], _out_rifireMux_T_674 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[681], _out_rifireMux_T_674 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_675 = eq(_out_T_1500, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_676 = or(out_rifireMux_out_167, _out_rifireMux_T_675) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_168 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_677 = and(_out_rifireMux_T_260, out_frontSel_104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_678 = and(_out_rifireMux_T_677, _out_T_1560) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_168, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[922], _out_rifireMux_T_678 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[921], _out_rifireMux_T_678 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[920], _out_rifireMux_T_678 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[919], _out_rifireMux_T_678 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[918], _out_rifireMux_T_678 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[917], _out_rifireMux_T_678 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[916], _out_rifireMux_T_678 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[915], _out_rifireMux_T_678 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_679 = eq(_out_T_1560, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_680 = or(out_rifireMux_out_168, _out_rifireMux_T_679) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_169 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_681 = and(_out_rifireMux_T_260, out_frontSel_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_682 = and(_out_rifireMux_T_681, _out_T_1454) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_169, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[510], _out_rifireMux_T_682 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[509], _out_rifireMux_T_682 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[508], _out_rifireMux_T_682 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[507], _out_rifireMux_T_682 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[506], _out_rifireMux_T_682 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[505], _out_rifireMux_T_682 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[504], _out_rifireMux_T_682 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[503], _out_rifireMux_T_682 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_683 = eq(_out_T_1454, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_684 = or(out_rifireMux_out_169, _out_rifireMux_T_683) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_170 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_685 = and(_out_rifireMux_T_260, out_frontSel_106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_686 = and(_out_rifireMux_T_685, _out_T_1370) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_170, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[191], _out_rifireMux_T_686 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[190], _out_rifireMux_T_686 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[189], _out_rifireMux_T_686 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[188], _out_rifireMux_T_686 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[187], _out_rifireMux_T_686 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[186], _out_rifireMux_T_686 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[185], _out_rifireMux_T_686 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[184], _out_rifireMux_T_686 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_687 = eq(_out_T_1370, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_688 = or(out_rifireMux_out_170, _out_rifireMux_T_687) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_171 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_689 = and(_out_rifireMux_T_260, out_frontSel_107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_690 = and(_out_rifireMux_T_689, _out_T_1598) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_171, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1074], _out_rifireMux_T_690 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1073], _out_rifireMux_T_690 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1072], _out_rifireMux_T_690 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1071], _out_rifireMux_T_690 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1070], _out_rifireMux_T_690 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1069], _out_rifireMux_T_690 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1068], _out_rifireMux_T_690 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1067], _out_rifireMux_T_690 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_691 = eq(_out_T_1598, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_692 = or(out_rifireMux_out_171, _out_rifireMux_T_691) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_172 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_693 = and(_out_rifireMux_T_260, out_frontSel_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_694 = and(_out_rifireMux_T_693, _out_T_1510) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_172, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[722], _out_rifireMux_T_694 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[721], _out_rifireMux_T_694 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[720], _out_rifireMux_T_694 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[719], _out_rifireMux_T_694 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[718], _out_rifireMux_T_694 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[717], _out_rifireMux_T_694 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[716], _out_rifireMux_T_694 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[715], _out_rifireMux_T_694 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_695 = eq(_out_T_1510, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_696 = or(out_rifireMux_out_172, _out_rifireMux_T_695) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_173 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_697 = and(_out_rifireMux_T_260, out_frontSel_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_698 = and(_out_rifireMux_T_697, _out_T_1436) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_173, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[442], _out_rifireMux_T_698 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[441], _out_rifireMux_T_698 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[440], _out_rifireMux_T_698 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[439], _out_rifireMux_T_698 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[438], _out_rifireMux_T_698 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[437], _out_rifireMux_T_698 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[436], _out_rifireMux_T_698 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[435], _out_rifireMux_T_698 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_699 = eq(_out_T_1436, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_700 = or(out_rifireMux_out_173, _out_rifireMux_T_699) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_174 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_701 = and(_out_rifireMux_T_260, out_frontSel_110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_702 = and(_out_rifireMux_T_701, _out_T_1350) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_174, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[111], _out_rifireMux_T_702 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[110], _out_rifireMux_T_702 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[109], _out_rifireMux_T_702 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[108], _out_rifireMux_T_702 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[107], _out_rifireMux_T_702 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[106], _out_rifireMux_T_702 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[105], _out_rifireMux_T_702 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[104], _out_rifireMux_T_702 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_703 = eq(_out_T_1350, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_704 = or(out_rifireMux_out_174, _out_rifireMux_T_703) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_175 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_705 = and(_out_rifireMux_T_260, out_frontSel_111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_706 = and(_out_rifireMux_T_705, _out_T_1616) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_175, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1146], _out_rifireMux_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1145], _out_rifireMux_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1144], _out_rifireMux_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1143], _out_rifireMux_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1142], _out_rifireMux_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1141], _out_rifireMux_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1140], _out_rifireMux_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1139], _out_rifireMux_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_707 = eq(_out_T_1616, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_708 = or(out_rifireMux_out_175, _out_rifireMux_T_707) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_176 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_709 = and(_out_rifireMux_T_260, out_frontSel_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_710 = and(_out_rifireMux_T_709, _out_T_1534) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_176, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[818], _out_rifireMux_T_710 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[817], _out_rifireMux_T_710 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[816], _out_rifireMux_T_710 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[815], _out_rifireMux_T_710 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[814], _out_rifireMux_T_710 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[813], _out_rifireMux_T_710 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[812], _out_rifireMux_T_710 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[811], _out_rifireMux_T_710 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_711 = eq(_out_T_1534, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_712 = or(out_rifireMux_out_176, _out_rifireMux_T_711) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_177 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_713 = and(_out_rifireMux_T_260, out_frontSel_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_714 = and(_out_rifireMux_T_713, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_177, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_715 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_716 = or(out_rifireMux_out_177, _out_rifireMux_T_715) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_178 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_717 = and(_out_rifireMux_T_260, out_frontSel_114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_718 = and(_out_rifireMux_T_717, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_178, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_719 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_720 = or(out_rifireMux_out_178, _out_rifireMux_T_719) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_179 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_721 = and(_out_rifireMux_T_260, out_frontSel_115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_722 = and(_out_rifireMux_T_721, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_179, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_723 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_724 = or(out_rifireMux_out_179, _out_rifireMux_T_723) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_180 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_725 = and(_out_rifireMux_T_260, out_frontSel_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_726 = and(_out_rifireMux_T_725, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_180, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_727 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_728 = or(out_rifireMux_out_180, _out_rifireMux_T_727) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_181 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_729 = and(_out_rifireMux_T_260, out_frontSel_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_730 = and(_out_rifireMux_T_729, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_181, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_731 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_732 = or(out_rifireMux_out_181, _out_rifireMux_T_731) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_182 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_733 = and(_out_rifireMux_T_260, out_frontSel_118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_734 = and(_out_rifireMux_T_733, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_182, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_735 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_736 = or(out_rifireMux_out_182, _out_rifireMux_T_735) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_183 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_737 = and(_out_rifireMux_T_260, out_frontSel_119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_738 = and(_out_rifireMux_T_737, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_183, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_739 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_740 = or(out_rifireMux_out_183, _out_rifireMux_T_739) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_184 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_741 = and(_out_rifireMux_T_260, out_frontSel_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_742 = and(_out_rifireMux_T_741, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_184, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_743 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_744 = or(out_rifireMux_out_184, _out_rifireMux_T_743) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_185 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_745 = and(_out_rifireMux_T_260, out_frontSel_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_746 = and(_out_rifireMux_T_745, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_185, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_747 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_748 = or(out_rifireMux_out_185, _out_rifireMux_T_747) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_186 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_749 = and(_out_rifireMux_T_260, out_frontSel_122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_750 = and(_out_rifireMux_T_749, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_186, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_751 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_752 = or(out_rifireMux_out_186, _out_rifireMux_T_751) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_187 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_753 = and(_out_rifireMux_T_260, out_frontSel_123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_754 = and(_out_rifireMux_T_753, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_187, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_755 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_756 = or(out_rifireMux_out_187, _out_rifireMux_T_755) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_188 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_757 = and(_out_rifireMux_T_260, out_frontSel_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_758 = and(_out_rifireMux_T_757, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_188, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_759 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_760 = or(out_rifireMux_out_188, _out_rifireMux_T_759) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_189 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_761 = and(_out_rifireMux_T_260, out_frontSel_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_762 = and(_out_rifireMux_T_761, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_189, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_763 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_764 = or(out_rifireMux_out_189, _out_rifireMux_T_763) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_190 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_765 = and(_out_rifireMux_T_260, out_frontSel_126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_766 = and(_out_rifireMux_T_765, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_190, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_767 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_768 = or(out_rifireMux_out_190, _out_rifireMux_T_767) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_191 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_769 = and(_out_rifireMux_T_260, out_frontSel_127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_770 = and(_out_rifireMux_T_769, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_191, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_771 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_772 = or(out_rifireMux_out_191, _out_rifireMux_T_771) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_192 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_773 = and(_out_rifireMux_T_260, out_frontSel_128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_774 = and(_out_rifireMux_T_773, _out_T_1450) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_192, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[494], _out_rifireMux_T_774 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[493], _out_rifireMux_T_774 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[492], _out_rifireMux_T_774 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[491], _out_rifireMux_T_774 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[490], _out_rifireMux_T_774 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[489], _out_rifireMux_T_774 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[488], _out_rifireMux_T_774 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[487], _out_rifireMux_T_774 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_775 = eq(_out_T_1450, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_776 = or(out_rifireMux_out_192, _out_rifireMux_T_775) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_193 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_777 = and(_out_rifireMux_T_260, out_frontSel_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_778 = and(_out_rifireMux_T_777, _out_T_1442) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_193, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[466], _out_rifireMux_T_778 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[465], _out_rifireMux_T_778 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[464], _out_rifireMux_T_778 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[463], _out_rifireMux_T_778 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[462], _out_rifireMux_T_778 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[461], _out_rifireMux_T_778 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[460], _out_rifireMux_T_778 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[459], _out_rifireMux_T_778 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_779 = eq(_out_T_1442, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_780 = or(out_rifireMux_out_193, _out_rifireMux_T_779) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_194 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_781 = and(_out_rifireMux_T_260, out_frontSel_130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_782 = and(_out_rifireMux_T_781, _out_T_1516) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_194, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[746], _out_rifireMux_T_782 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[745], _out_rifireMux_T_782 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[744], _out_rifireMux_T_782 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[743], _out_rifireMux_T_782 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[742], _out_rifireMux_T_782 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[741], _out_rifireMux_T_782 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[740], _out_rifireMux_T_782 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[739], _out_rifireMux_T_782 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_783 = eq(_out_T_1516, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_784 = or(out_rifireMux_out_194, _out_rifireMux_T_783) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_195 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_785 = and(_out_rifireMux_T_260, out_frontSel_131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_786 = and(_out_rifireMux_T_785, _out_T_1608) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_195, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1114], _out_rifireMux_T_786 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1113], _out_rifireMux_T_786 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1112], _out_rifireMux_T_786 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1111], _out_rifireMux_T_786 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1110], _out_rifireMux_T_786 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1109], _out_rifireMux_T_786 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1108], _out_rifireMux_T_786 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1107], _out_rifireMux_T_786 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_787 = eq(_out_T_1608, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_788 = or(out_rifireMux_out_195, _out_rifireMux_T_787) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_196 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_789 = and(_out_rifireMux_T_260, out_frontSel_132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_790 = and(_out_rifireMux_T_789, _out_T_1382) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_196, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[239], _out_rifireMux_T_790 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[238], _out_rifireMux_T_790 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[237], _out_rifireMux_T_790 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[236], _out_rifireMux_T_790 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[235], _out_rifireMux_T_790 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[234], _out_rifireMux_T_790 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[233], _out_rifireMux_T_790 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[232], _out_rifireMux_T_790 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_791 = eq(_out_T_1382, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_792 = or(out_rifireMux_out_196, _out_rifireMux_T_791) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_197 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_793 = and(_out_rifireMux_T_260, out_frontSel_133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_794 = and(_out_rifireMux_T_793, _out_T_1384) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_197, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[247], _out_rifireMux_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[246], _out_rifireMux_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[245], _out_rifireMux_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[244], _out_rifireMux_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[243], _out_rifireMux_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[242], _out_rifireMux_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[241], _out_rifireMux_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[240], _out_rifireMux_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_795 = eq(_out_T_1384, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_796 = or(out_rifireMux_out_197, _out_rifireMux_T_795) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_198 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_797 = and(_out_rifireMux_T_260, out_frontSel_134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_798 = and(_out_rifireMux_T_797, _out_T_1444) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_198, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[474], _out_rifireMux_T_798 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[473], _out_rifireMux_T_798 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[472], _out_rifireMux_T_798 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[471], _out_rifireMux_T_798 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[470], _out_rifireMux_T_798 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[469], _out_rifireMux_T_798 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[468], _out_rifireMux_T_798 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[467], _out_rifireMux_T_798 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_799 = eq(_out_T_1444, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_800 = or(out_rifireMux_out_198, _out_rifireMux_T_799) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_199 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_801 = and(_out_rifireMux_T_260, out_frontSel_135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_802 = and(_out_rifireMux_T_801, _out_T_1520) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_199, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[762], _out_rifireMux_T_802 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[761], _out_rifireMux_T_802 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[760], _out_rifireMux_T_802 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[759], _out_rifireMux_T_802 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[758], _out_rifireMux_T_802 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[757], _out_rifireMux_T_802 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[756], _out_rifireMux_T_802 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[755], _out_rifireMux_T_802 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_803 = eq(_out_T_1520, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_804 = or(out_rifireMux_out_199, _out_rifireMux_T_803) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_200 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_805 = and(_out_rifireMux_T_260, out_frontSel_136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_806 = and(_out_rifireMux_T_805, _out_T_1600) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_200, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1082], _out_rifireMux_T_806 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1081], _out_rifireMux_T_806 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1080], _out_rifireMux_T_806 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1079], _out_rifireMux_T_806 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1078], _out_rifireMux_T_806 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1077], _out_rifireMux_T_806 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1076], _out_rifireMux_T_806 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1075], _out_rifireMux_T_806 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_807 = eq(_out_T_1600, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_808 = or(out_rifireMux_out_200, _out_rifireMux_T_807) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_201 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_809 = and(_out_rifireMux_T_260, out_frontSel_137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_810 = and(_out_rifireMux_T_809, _out_T_1406) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_201, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[335], _out_rifireMux_T_810 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[334], _out_rifireMux_T_810 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[333], _out_rifireMux_T_810 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[332], _out_rifireMux_T_810 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[331], _out_rifireMux_T_810 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[330], _out_rifireMux_T_810 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[329], _out_rifireMux_T_810 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[328], _out_rifireMux_T_810 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_811 = eq(_out_T_1406, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_812 = or(out_rifireMux_out_201, _out_rifireMux_T_811) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_202 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_813 = and(_out_rifireMux_T_260, out_frontSel_138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_814 = and(_out_rifireMux_T_813, _out_T_1324) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_202, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[7], _out_rifireMux_T_814 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[6], _out_rifireMux_T_814 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[5], _out_rifireMux_T_814 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[4], _out_rifireMux_T_814 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[3], _out_rifireMux_T_814 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[2], _out_rifireMux_T_814 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1], _out_rifireMux_T_814 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[0], _out_rifireMux_T_814 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_815 = eq(_out_T_1324, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_816 = or(out_rifireMux_out_202, _out_rifireMux_T_815) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_203 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_817 = and(_out_rifireMux_T_260, out_frontSel_139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_818 = and(_out_rifireMux_T_817, _out_T_1574) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_203, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[978], _out_rifireMux_T_818 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[977], _out_rifireMux_T_818 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[976], _out_rifireMux_T_818 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[975], _out_rifireMux_T_818 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[974], _out_rifireMux_T_818 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[973], _out_rifireMux_T_818 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[972], _out_rifireMux_T_818 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[971], _out_rifireMux_T_818 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_819 = eq(_out_T_1574, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_820 = or(out_rifireMux_out_203, _out_rifireMux_T_819) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_204 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_821 = and(_out_rifireMux_T_260, out_frontSel_140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_822 = and(_out_rifireMux_T_821, _out_T_1502) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_204, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[690], _out_rifireMux_T_822 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[689], _out_rifireMux_T_822 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[688], _out_rifireMux_T_822 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[687], _out_rifireMux_T_822 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[686], _out_rifireMux_T_822 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[685], _out_rifireMux_T_822 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[684], _out_rifireMux_T_822 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[683], _out_rifireMux_T_822 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_823 = eq(_out_T_1502, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_824 = or(out_rifireMux_out_204, _out_rifireMux_T_823) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_205 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_825 = and(_out_rifireMux_T_260, out_frontSel_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_826 = and(_out_rifireMux_T_825, _out_T_1426) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_205, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[409], _out_rifireMux_T_826 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[408], _out_rifireMux_T_826 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[407], _out_rifireMux_T_826 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[406], _out_rifireMux_T_826 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[405], _out_rifireMux_T_826 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[404], _out_rifireMux_T_826 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[403], _out_rifireMux_T_826 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[402], _out_rifireMux_T_826 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_827 = eq(_out_T_1426, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_828 = or(out_rifireMux_out_205, _out_rifireMux_T_827) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_206 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_829 = and(_out_rifireMux_T_260, out_frontSel_142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_830 = and(_out_rifireMux_T_829, _out_T_1338) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_206, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[63], _out_rifireMux_T_830 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[62], _out_rifireMux_T_830 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[61], _out_rifireMux_T_830 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[60], _out_rifireMux_T_830 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[59], _out_rifireMux_T_830 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[58], _out_rifireMux_T_830 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[57], _out_rifireMux_T_830 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[56], _out_rifireMux_T_830 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_831 = eq(_out_T_1338, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_832 = or(out_rifireMux_out_206, _out_rifireMux_T_831) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_207 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_833 = and(_out_rifireMux_T_260, out_frontSel_143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_834 = and(_out_rifireMux_T_833, _out_T_1554) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_207, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[898], _out_rifireMux_T_834 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[897], _out_rifireMux_T_834 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[896], _out_rifireMux_T_834 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[895], _out_rifireMux_T_834 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[894], _out_rifireMux_T_834 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[893], _out_rifireMux_T_834 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[892], _out_rifireMux_T_834 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[891], _out_rifireMux_T_834 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_835 = eq(_out_T_1554, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_836 = or(out_rifireMux_out_207, _out_rifireMux_T_835) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_208 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_837 = and(_out_rifireMux_T_260, out_frontSel_144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_838 = and(_out_rifireMux_T_837, _out_T_1480) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_208, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[608], _out_rifireMux_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[607], _out_rifireMux_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[606], _out_rifireMux_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[605], _out_rifireMux_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[604], _out_rifireMux_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[603], _out_rifireMux_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[602], _out_rifireMux_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[601], _out_rifireMux_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_839 = eq(_out_T_1480, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_840 = or(out_rifireMux_out_208, _out_rifireMux_T_839) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_209 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_841 = and(_out_rifireMux_T_260, out_frontSel_145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_842 = and(_out_rifireMux_T_841, _out_T_1538) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_209, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[834], _out_rifireMux_T_842 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[833], _out_rifireMux_T_842 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[832], _out_rifireMux_T_842 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[831], _out_rifireMux_T_842 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[830], _out_rifireMux_T_842 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[829], _out_rifireMux_T_842 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[828], _out_rifireMux_T_842 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[827], _out_rifireMux_T_842 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_843 = eq(_out_T_1538, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_844 = or(out_rifireMux_out_209, _out_rifireMux_T_843) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_210 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_845 = and(_out_rifireMux_T_260, out_frontSel_146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_846 = and(_out_rifireMux_T_845, _out_T_1586) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_210, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1026], _out_rifireMux_T_846 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1025], _out_rifireMux_T_846 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1024], _out_rifireMux_T_846 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1023], _out_rifireMux_T_846 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1022], _out_rifireMux_T_846 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1021], _out_rifireMux_T_846 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1020], _out_rifireMux_T_846 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1019], _out_rifireMux_T_846 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_847 = eq(_out_T_1586, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_848 = or(out_rifireMux_out_210, _out_rifireMux_T_847) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_211 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_849 = and(_out_rifireMux_T_260, out_frontSel_147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_850 = and(_out_rifireMux_T_849, _out_T_1378) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_211, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[223], _out_rifireMux_T_850 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[222], _out_rifireMux_T_850 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[221], _out_rifireMux_T_850 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[220], _out_rifireMux_T_850 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[219], _out_rifireMux_T_850 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[218], _out_rifireMux_T_850 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[217], _out_rifireMux_T_850 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[216], _out_rifireMux_T_850 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_851 = eq(_out_T_1378, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_852 = or(out_rifireMux_out_211, _out_rifireMux_T_851) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_212 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_853 = and(_out_rifireMux_T_260, out_frontSel_148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_854 = and(_out_rifireMux_T_853, _out_T_1462) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_212, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[536], _out_rifireMux_T_854 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[535], _out_rifireMux_T_854 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[534], _out_rifireMux_T_854 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[533], _out_rifireMux_T_854 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[532], _out_rifireMux_T_854 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[531], _out_rifireMux_T_854 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[530], _out_rifireMux_T_854 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[529], _out_rifireMux_T_854 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_855 = eq(_out_T_1462, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_856 = or(out_rifireMux_out_212, _out_rifireMux_T_855) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_213 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_857 = and(_out_rifireMux_T_260, out_frontSel_149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_858 = and(_out_rifireMux_T_857, _out_T_1470) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_213, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[568], _out_rifireMux_T_858 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[567], _out_rifireMux_T_858 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[566], _out_rifireMux_T_858 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[565], _out_rifireMux_T_858 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[564], _out_rifireMux_T_858 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[563], _out_rifireMux_T_858 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[562], _out_rifireMux_T_858 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[561], _out_rifireMux_T_858 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_859 = eq(_out_T_1470, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_860 = or(out_rifireMux_out_213, _out_rifireMux_T_859) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_214 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_861 = and(_out_rifireMux_T_260, out_frontSel_150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_862 = and(_out_rifireMux_T_861, _out_T_1540) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_214, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[842], _out_rifireMux_T_862 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[841], _out_rifireMux_T_862 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[840], _out_rifireMux_T_862 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[839], _out_rifireMux_T_862 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[838], _out_rifireMux_T_862 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[837], _out_rifireMux_T_862 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[836], _out_rifireMux_T_862 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[835], _out_rifireMux_T_862 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_863 = eq(_out_T_1540, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_864 = or(out_rifireMux_out_214, _out_rifireMux_T_863) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_215 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_865 = and(_out_rifireMux_T_260, out_frontSel_151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_866 = and(_out_rifireMux_T_865, _out_T_1584) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_215, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1018], _out_rifireMux_T_866 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1017], _out_rifireMux_T_866 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1016], _out_rifireMux_T_866 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1015], _out_rifireMux_T_866 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1014], _out_rifireMux_T_866 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1013], _out_rifireMux_T_866 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1012], _out_rifireMux_T_866 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1011], _out_rifireMux_T_866 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_867 = eq(_out_T_1584, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_868 = or(out_rifireMux_out_215, _out_rifireMux_T_867) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_216 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_869 = and(_out_rifireMux_T_260, out_frontSel_152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_870 = and(_out_rifireMux_T_869, _out_T_1358) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_216, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[143], _out_rifireMux_T_870 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[142], _out_rifireMux_T_870 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[141], _out_rifireMux_T_870 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[140], _out_rifireMux_T_870 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[139], _out_rifireMux_T_870 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[138], _out_rifireMux_T_870 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[137], _out_rifireMux_T_870 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[136], _out_rifireMux_T_870 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_871 = eq(_out_T_1358, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_872 = or(out_rifireMux_out_216, _out_rifireMux_T_871) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_217 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_873 = and(_out_rifireMux_T_260, out_frontSel_153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_874 = and(_out_rifireMux_T_873, _out_T_1340) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_217, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[71], _out_rifireMux_T_874 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[70], _out_rifireMux_T_874 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[69], _out_rifireMux_T_874 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[68], _out_rifireMux_T_874 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[67], _out_rifireMux_T_874 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[66], _out_rifireMux_T_874 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[65], _out_rifireMux_T_874 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[64], _out_rifireMux_T_874 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_875 = eq(_out_T_1340, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_876 = or(out_rifireMux_out_217, _out_rifireMux_T_875) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_218 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_877 = and(_out_rifireMux_T_260, out_frontSel_154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_878 = and(_out_rifireMux_T_877, _out_T_1550) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_218, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[882], _out_rifireMux_T_878 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[881], _out_rifireMux_T_878 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[880], _out_rifireMux_T_878 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[879], _out_rifireMux_T_878 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[878], _out_rifireMux_T_878 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[877], _out_rifireMux_T_878 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[876], _out_rifireMux_T_878 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[875], _out_rifireMux_T_878 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_879 = eq(_out_T_1550, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_880 = or(out_rifireMux_out_218, _out_rifireMux_T_879) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_219 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_881 = and(_out_rifireMux_T_260, out_frontSel_155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_882 = and(_out_rifireMux_T_881, _out_T_1506) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_219, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[706], _out_rifireMux_T_882 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[705], _out_rifireMux_T_882 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[704], _out_rifireMux_T_882 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[703], _out_rifireMux_T_882 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[702], _out_rifireMux_T_882 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[701], _out_rifireMux_T_882 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[700], _out_rifireMux_T_882 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[699], _out_rifireMux_T_882 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_883 = eq(_out_T_1506, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_884 = or(out_rifireMux_out_219, _out_rifireMux_T_883) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_220 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_885 = and(_out_rifireMux_T_260, out_frontSel_156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_886 = and(_out_rifireMux_T_885, _out_T_1420) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_220, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[385], _out_rifireMux_T_886 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[384], _out_rifireMux_T_886 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[383], _out_rifireMux_T_886 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[382], _out_rifireMux_T_886 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[381], _out_rifireMux_T_886 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[380], _out_rifireMux_T_886 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[379], _out_rifireMux_T_886 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[378], _out_rifireMux_T_886 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_887 = eq(_out_T_1420, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_888 = or(out_rifireMux_out_220, _out_rifireMux_T_887) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_221 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_889 = and(_out_rifireMux_T_260, out_frontSel_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_890 = and(_out_rifireMux_T_889, _out_T_1354) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_221, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[127], _out_rifireMux_T_890 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[126], _out_rifireMux_T_890 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[125], _out_rifireMux_T_890 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[124], _out_rifireMux_T_890 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[123], _out_rifireMux_T_890 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[122], _out_rifireMux_T_890 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[121], _out_rifireMux_T_890 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[120], _out_rifireMux_T_890 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_891 = eq(_out_T_1354, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_892 = or(out_rifireMux_out_221, _out_rifireMux_T_891) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_222 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_893 = and(_out_rifireMux_T_260, out_frontSel_158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_894 = and(_out_rifireMux_T_893, _out_T_1568) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_222, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[954], _out_rifireMux_T_894 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[953], _out_rifireMux_T_894 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[952], _out_rifireMux_T_894 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[951], _out_rifireMux_T_894 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[950], _out_rifireMux_T_894 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[949], _out_rifireMux_T_894 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[948], _out_rifireMux_T_894 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[947], _out_rifireMux_T_894 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_895 = eq(_out_T_1568, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_896 = or(out_rifireMux_out_222, _out_rifireMux_T_895) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_223 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_897 = and(_out_rifireMux_T_260, out_frontSel_159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_898 = and(_out_rifireMux_T_897, _out_T_1486) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_223, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[632], _out_rifireMux_T_898 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[631], _out_rifireMux_T_898 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[630], _out_rifireMux_T_898 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[629], _out_rifireMux_T_898 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[628], _out_rifireMux_T_898 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[627], _out_rifireMux_T_898 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[626], _out_rifireMux_T_898 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[625], _out_rifireMux_T_898 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_899 = eq(_out_T_1486, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_900 = or(out_rifireMux_out_223, _out_rifireMux_T_899) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_224 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_901 = and(_out_rifireMux_T_260, out_frontSel_160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_902 = and(_out_rifireMux_T_901, _out_T_1402) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_224, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[319], _out_rifireMux_T_902 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[318], _out_rifireMux_T_902 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[317], _out_rifireMux_T_902 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[316], _out_rifireMux_T_902 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[315], _out_rifireMux_T_902 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[314], _out_rifireMux_T_902 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[313], _out_rifireMux_T_902 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[312], _out_rifireMux_T_902 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_903 = eq(_out_T_1402, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_904 = or(out_rifireMux_out_224, _out_rifireMux_T_903) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_225 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_905 = and(_out_rifireMux_T_260, out_frontSel_161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_906 = and(_out_rifireMux_T_905, _out_T_1466) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_225, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[552], _out_rifireMux_T_906 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[551], _out_rifireMux_T_906 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[550], _out_rifireMux_T_906 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[549], _out_rifireMux_T_906 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[548], _out_rifireMux_T_906 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[547], _out_rifireMux_T_906 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[546], _out_rifireMux_T_906 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[545], _out_rifireMux_T_906 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_907 = eq(_out_T_1466, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_908 = or(out_rifireMux_out_225, _out_rifireMux_T_907) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_226 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_909 = and(_out_rifireMux_T_260, out_frontSel_162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_910 = and(_out_rifireMux_T_909, _out_T_1528) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_226, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[794], _out_rifireMux_T_910 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[793], _out_rifireMux_T_910 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[792], _out_rifireMux_T_910 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[791], _out_rifireMux_T_910 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[790], _out_rifireMux_T_910 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[789], _out_rifireMux_T_910 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[788], _out_rifireMux_T_910 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[787], _out_rifireMux_T_910 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_911 = eq(_out_T_1528, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_912 = or(out_rifireMux_out_226, _out_rifireMux_T_911) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_227 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_913 = and(_out_rifireMux_T_260, out_frontSel_163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_914 = and(_out_rifireMux_T_913, _out_T_1612) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_227, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1130], _out_rifireMux_T_914 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1129], _out_rifireMux_T_914 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1128], _out_rifireMux_T_914 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1127], _out_rifireMux_T_914 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1126], _out_rifireMux_T_914 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1125], _out_rifireMux_T_914 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1124], _out_rifireMux_T_914 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1123], _out_rifireMux_T_914 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_915 = eq(_out_T_1612, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_916 = or(out_rifireMux_out_227, _out_rifireMux_T_915) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_228 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_917 = and(_out_rifireMux_T_260, out_frontSel_164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_918 = and(_out_rifireMux_T_917, _out_T_1366) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_228, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[175], _out_rifireMux_T_918 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[174], _out_rifireMux_T_918 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[173], _out_rifireMux_T_918 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[172], _out_rifireMux_T_918 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[171], _out_rifireMux_T_918 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[170], _out_rifireMux_T_918 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[169], _out_rifireMux_T_918 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[168], _out_rifireMux_T_918 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_919 = eq(_out_T_1366, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_920 = or(out_rifireMux_out_228, _out_rifireMux_T_919) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_229 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_921 = and(_out_rifireMux_T_260, out_frontSel_165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_922 = and(_out_rifireMux_T_921, _out_T_1408) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_229, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[343], _out_rifireMux_T_922 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[342], _out_rifireMux_T_922 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[341], _out_rifireMux_T_922 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[340], _out_rifireMux_T_922 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[339], _out_rifireMux_T_922 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[338], _out_rifireMux_T_922 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[337], _out_rifireMux_T_922 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[336], _out_rifireMux_T_922 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_923 = eq(_out_T_1408, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_924 = or(out_rifireMux_out_229, _out_rifireMux_T_923) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_230 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_925 = and(_out_rifireMux_T_260, out_frontSel_166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_926 = and(_out_rifireMux_T_925, _out_T_1458) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_230, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[526], _out_rifireMux_T_926 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[525], _out_rifireMux_T_926 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[524], _out_rifireMux_T_926 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[523], _out_rifireMux_T_926 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[522], _out_rifireMux_T_926 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[521], _out_rifireMux_T_926 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[520], _out_rifireMux_T_926 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[519], _out_rifireMux_T_926 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_927 = eq(_out_T_1458, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_928 = or(out_rifireMux_out_230, _out_rifireMux_T_927) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_231 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_929 = and(_out_rifireMux_T_260, out_frontSel_167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_930 = and(_out_rifireMux_T_929, _out_T_1526) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_231, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[786], _out_rifireMux_T_930 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[785], _out_rifireMux_T_930 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[784], _out_rifireMux_T_930 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[783], _out_rifireMux_T_930 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[782], _out_rifireMux_T_930 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[781], _out_rifireMux_T_930 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[780], _out_rifireMux_T_930 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[779], _out_rifireMux_T_930 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_931 = eq(_out_T_1526, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_932 = or(out_rifireMux_out_231, _out_rifireMux_T_931) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_232 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_933 = and(_out_rifireMux_T_260, out_frontSel_168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_934 = and(_out_rifireMux_T_933, _out_T_1592) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_232, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1050], _out_rifireMux_T_934 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1049], _out_rifireMux_T_934 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1048], _out_rifireMux_T_934 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1047], _out_rifireMux_T_934 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1046], _out_rifireMux_T_934 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1045], _out_rifireMux_T_934 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1044], _out_rifireMux_T_934 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1043], _out_rifireMux_T_934 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_935 = eq(_out_T_1592, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_936 = or(out_rifireMux_out_232, _out_rifireMux_T_935) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_233 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_937 = and(_out_rifireMux_T_260, out_frontSel_169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_938 = and(_out_rifireMux_T_937, _out_T_1424) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_233, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[401], _out_rifireMux_T_938 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[400], _out_rifireMux_T_938 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[399], _out_rifireMux_T_938 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[398], _out_rifireMux_T_938 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[397], _out_rifireMux_T_938 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[396], _out_rifireMux_T_938 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[395], _out_rifireMux_T_938 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[394], _out_rifireMux_T_938 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_939 = eq(_out_T_1424, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_940 = or(out_rifireMux_out_233, _out_rifireMux_T_939) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_234 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_941 = and(_out_rifireMux_T_260, out_frontSel_170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_942 = and(_out_rifireMux_T_941, _out_T_1330) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_234, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[31], _out_rifireMux_T_942 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[30], _out_rifireMux_T_942 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[29], _out_rifireMux_T_942 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[28], _out_rifireMux_T_942 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[27], _out_rifireMux_T_942 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[26], _out_rifireMux_T_942 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[25], _out_rifireMux_T_942 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[24], _out_rifireMux_T_942 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_943 = eq(_out_T_1330, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_944 = or(out_rifireMux_out_234, _out_rifireMux_T_943) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_235 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_945 = and(_out_rifireMux_T_260, out_frontSel_171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_946 = and(_out_rifireMux_T_945, _out_T_1572) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_235, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[970], _out_rifireMux_T_946 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[969], _out_rifireMux_T_946 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[968], _out_rifireMux_T_946 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[967], _out_rifireMux_T_946 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[966], _out_rifireMux_T_946 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[965], _out_rifireMux_T_946 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[964], _out_rifireMux_T_946 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[963], _out_rifireMux_T_946 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_947 = eq(_out_T_1572, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_948 = or(out_rifireMux_out_235, _out_rifireMux_T_947) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_236 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_949 = and(_out_rifireMux_T_260, out_frontSel_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_950 = and(_out_rifireMux_T_949, _out_T_1490) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_236, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[648], _out_rifireMux_T_950 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[647], _out_rifireMux_T_950 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[646], _out_rifireMux_T_950 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[645], _out_rifireMux_T_950 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[644], _out_rifireMux_T_950 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[643], _out_rifireMux_T_950 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[642], _out_rifireMux_T_950 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[641], _out_rifireMux_T_950 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_951 = eq(_out_T_1490, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_952 = or(out_rifireMux_out_236, _out_rifireMux_T_951) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_237 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_953 = and(_out_rifireMux_T_260, out_frontSel_173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_954 = and(_out_rifireMux_T_953, _out_T_1440) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_237, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[458], _out_rifireMux_T_954 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[457], _out_rifireMux_T_954 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[456], _out_rifireMux_T_954 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[455], _out_rifireMux_T_954 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[454], _out_rifireMux_T_954 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[453], _out_rifireMux_T_954 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[452], _out_rifireMux_T_954 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[451], _out_rifireMux_T_954 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_955 = eq(_out_T_1440, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_956 = or(out_rifireMux_out_237, _out_rifireMux_T_955) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_238 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_957 = and(_out_rifireMux_T_260, out_frontSel_174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_958 = and(_out_rifireMux_T_957, _out_T_1342) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_238, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[79], _out_rifireMux_T_958 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[78], _out_rifireMux_T_958 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[77], _out_rifireMux_T_958 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[76], _out_rifireMux_T_958 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[75], _out_rifireMux_T_958 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[74], _out_rifireMux_T_958 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[73], _out_rifireMux_T_958 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[72], _out_rifireMux_T_958 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_959 = eq(_out_T_1342, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_960 = or(out_rifireMux_out_238, _out_rifireMux_T_959) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_239 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_961 = and(_out_rifireMux_T_260, out_frontSel_175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_962 = and(_out_rifireMux_T_961, _out_T_1552) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_239, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[890], _out_rifireMux_T_962 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[889], _out_rifireMux_T_962 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[888], _out_rifireMux_T_962 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[887], _out_rifireMux_T_962 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[886], _out_rifireMux_T_962 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[885], _out_rifireMux_T_962 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[884], _out_rifireMux_T_962 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[883], _out_rifireMux_T_962 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_963 = eq(_out_T_1552, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_964 = or(out_rifireMux_out_239, _out_rifireMux_T_963) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_240 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_965 = and(_out_rifireMux_T_260, out_frontSel_176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_966 = and(_out_rifireMux_T_965, _out_T_1472) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_240, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[576], _out_rifireMux_T_966 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[575], _out_rifireMux_T_966 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[574], _out_rifireMux_T_966 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[573], _out_rifireMux_T_966 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[572], _out_rifireMux_T_966 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[571], _out_rifireMux_T_966 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[570], _out_rifireMux_T_966 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[569], _out_rifireMux_T_966 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_967 = eq(_out_T_1472, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_968 = or(out_rifireMux_out_240, _out_rifireMux_T_967) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_241 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_969 = and(_out_rifireMux_T_260, out_frontSel_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_970 = and(_out_rifireMux_T_969, _out_T_1546) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_241, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[866], _out_rifireMux_T_970 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[865], _out_rifireMux_T_970 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[864], _out_rifireMux_T_970 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[863], _out_rifireMux_T_970 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[862], _out_rifireMux_T_970 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[861], _out_rifireMux_T_970 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[860], _out_rifireMux_T_970 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[859], _out_rifireMux_T_970 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_971 = eq(_out_T_1546, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_972 = or(out_rifireMux_out_241, _out_rifireMux_T_971) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_242 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_973 = and(_out_rifireMux_T_260, out_frontSel_178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_974 = and(_out_rifireMux_T_973, _out_T_1610) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_242, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1122], _out_rifireMux_T_974 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1121], _out_rifireMux_T_974 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1120], _out_rifireMux_T_974 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1119], _out_rifireMux_T_974 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1118], _out_rifireMux_T_974 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1117], _out_rifireMux_T_974 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1116], _out_rifireMux_T_974 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1115], _out_rifireMux_T_974 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_975 = eq(_out_T_1610, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_976 = or(out_rifireMux_out_242, _out_rifireMux_T_975) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_243 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_977 = and(_out_rifireMux_T_260, out_frontSel_179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_978 = and(_out_rifireMux_T_977, _out_T_1368) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_243, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[183], _out_rifireMux_T_978 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[182], _out_rifireMux_T_978 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[181], _out_rifireMux_T_978 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[180], _out_rifireMux_T_978 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[179], _out_rifireMux_T_978 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[178], _out_rifireMux_T_978 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[177], _out_rifireMux_T_978 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[176], _out_rifireMux_T_978 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_979 = eq(_out_T_1368, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_980 = or(out_rifireMux_out_243, _out_rifireMux_T_979) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_244 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_981 = and(_out_rifireMux_T_260, out_frontSel_180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_982 = and(_out_rifireMux_T_981, _out_T_1468) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_244, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[560], _out_rifireMux_T_982 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[559], _out_rifireMux_T_982 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[558], _out_rifireMux_T_982 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[557], _out_rifireMux_T_982 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[556], _out_rifireMux_T_982 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[555], _out_rifireMux_T_982 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[554], _out_rifireMux_T_982 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[553], _out_rifireMux_T_982 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_983 = eq(_out_T_1468, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_984 = or(out_rifireMux_out_244, _out_rifireMux_T_983) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_245 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_985 = and(_out_rifireMux_T_260, out_frontSel_181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_986 = and(_out_rifireMux_T_985, _out_T_1484) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_245, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[624], _out_rifireMux_T_986 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[623], _out_rifireMux_T_986 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[622], _out_rifireMux_T_986 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[621], _out_rifireMux_T_986 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[620], _out_rifireMux_T_986 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[619], _out_rifireMux_T_986 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[618], _out_rifireMux_T_986 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[617], _out_rifireMux_T_986 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_987 = eq(_out_T_1484, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_988 = or(out_rifireMux_out_245, _out_rifireMux_T_987) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_246 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_989 = and(_out_rifireMux_T_260, out_frontSel_182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_990 = and(_out_rifireMux_T_989, _out_T_1548) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_246, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[874], _out_rifireMux_T_990 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[873], _out_rifireMux_T_990 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[872], _out_rifireMux_T_990 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[871], _out_rifireMux_T_990 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[870], _out_rifireMux_T_990 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[869], _out_rifireMux_T_990 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[868], _out_rifireMux_T_990 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[867], _out_rifireMux_T_990 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_991 = eq(_out_T_1548, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_992 = or(out_rifireMux_out_246, _out_rifireMux_T_991) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_247 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_993 = and(_out_rifireMux_T_260, out_frontSel_183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_994 = and(_out_rifireMux_T_993, _out_T_1590) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_247, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1042], _out_rifireMux_T_994 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1041], _out_rifireMux_T_994 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1040], _out_rifireMux_T_994 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1039], _out_rifireMux_T_994 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1038], _out_rifireMux_T_994 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1037], _out_rifireMux_T_994 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1036], _out_rifireMux_T_994 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1035], _out_rifireMux_T_994 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_995 = eq(_out_T_1590, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_996 = or(out_rifireMux_out_247, _out_rifireMux_T_995) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_248 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_997 = and(_out_rifireMux_T_260, out_frontSel_184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_998 = and(_out_rifireMux_T_997, _out_T_1348) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_248, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[103], _out_rifireMux_T_998 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[102], _out_rifireMux_T_998 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[101], _out_rifireMux_T_998 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[100], _out_rifireMux_T_998 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[99], _out_rifireMux_T_998 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[98], _out_rifireMux_T_998 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[97], _out_rifireMux_T_998 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[96], _out_rifireMux_T_998 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_999 = eq(_out_T_1348, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1000 = or(out_rifireMux_out_248, _out_rifireMux_T_999) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_249 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1001 = and(_out_rifireMux_T_260, out_frontSel_185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1002 = and(_out_rifireMux_T_1001, _out_T_1344) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_249, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[87], _out_rifireMux_T_1002 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[86], _out_rifireMux_T_1002 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[85], _out_rifireMux_T_1002 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[84], _out_rifireMux_T_1002 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[83], _out_rifireMux_T_1002 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[82], _out_rifireMux_T_1002 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[81], _out_rifireMux_T_1002 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[80], _out_rifireMux_T_1002 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1003 = eq(_out_T_1344, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1004 = or(out_rifireMux_out_249, _out_rifireMux_T_1003) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_250 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1005 = and(_out_rifireMux_T_260, out_frontSel_186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1006 = and(_out_rifireMux_T_1005, _out_T_1570) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_250, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[962], _out_rifireMux_T_1006 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[961], _out_rifireMux_T_1006 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[960], _out_rifireMux_T_1006 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[959], _out_rifireMux_T_1006 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[958], _out_rifireMux_T_1006 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[957], _out_rifireMux_T_1006 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[956], _out_rifireMux_T_1006 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[955], _out_rifireMux_T_1006 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1007 = eq(_out_T_1570, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1008 = or(out_rifireMux_out_250, _out_rifireMux_T_1007) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_251 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1009 = and(_out_rifireMux_T_260, out_frontSel_187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1010 = and(_out_rifireMux_T_1009, _out_T_1488) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_251, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[640], _out_rifireMux_T_1010 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[639], _out_rifireMux_T_1010 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[638], _out_rifireMux_T_1010 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[637], _out_rifireMux_T_1010 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[636], _out_rifireMux_T_1010 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[635], _out_rifireMux_T_1010 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[634], _out_rifireMux_T_1010 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[633], _out_rifireMux_T_1010 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1011 = eq(_out_T_1488, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1012 = or(out_rifireMux_out_251, _out_rifireMux_T_1011) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_252 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1013 = and(_out_rifireMux_T_260, out_frontSel_188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1014 = and(_out_rifireMux_T_1013, _out_T_1422) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_252, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[393], _out_rifireMux_T_1014 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[392], _out_rifireMux_T_1014 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[391], _out_rifireMux_T_1014 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[390], _out_rifireMux_T_1014 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[389], _out_rifireMux_T_1014 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[388], _out_rifireMux_T_1014 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[387], _out_rifireMux_T_1014 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[386], _out_rifireMux_T_1014 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1015 = eq(_out_T_1422, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1016 = or(out_rifireMux_out_252, _out_rifireMux_T_1015) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_253 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1017 = and(_out_rifireMux_T_260, out_frontSel_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1018 = and(_out_rifireMux_T_1017, _out_T_1356) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_253, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[135], _out_rifireMux_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[134], _out_rifireMux_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[133], _out_rifireMux_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[132], _out_rifireMux_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[131], _out_rifireMux_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[130], _out_rifireMux_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[129], _out_rifireMux_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[128], _out_rifireMux_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1019 = eq(_out_T_1356, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1020 = or(out_rifireMux_out_253, _out_rifireMux_T_1019) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_254 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1021 = and(_out_rifireMux_T_260, out_frontSel_190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1022 = and(_out_rifireMux_T_1021, _out_T_1588) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_254, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1034], _out_rifireMux_T_1022 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1033], _out_rifireMux_T_1022 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1032], _out_rifireMux_T_1022 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1031], _out_rifireMux_T_1022 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1030], _out_rifireMux_T_1022 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1029], _out_rifireMux_T_1022 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1028], _out_rifireMux_T_1022 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1027], _out_rifireMux_T_1022 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1023 = eq(_out_T_1588, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1024 = or(out_rifireMux_out_254, _out_rifireMux_T_1023) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_255 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1025 = and(_out_rifireMux_T_260, out_frontSel_191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1026 = and(_out_rifireMux_T_1025, _out_T_1474) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_255, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[584], _out_rifireMux_T_1026 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[583], _out_rifireMux_T_1026 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[582], _out_rifireMux_T_1026 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[581], _out_rifireMux_T_1026 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[580], _out_rifireMux_T_1026 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[579], _out_rifireMux_T_1026 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[578], _out_rifireMux_T_1026 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[577], _out_rifireMux_T_1026 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1027 = eq(_out_T_1474, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1028 = or(out_rifireMux_out_255, _out_rifireMux_T_1027) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_256 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1029 = and(_out_rifireMux_T_260, out_frontSel_192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1030 = and(_out_rifireMux_T_1029, _out_T_1404) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_256, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[327], _out_rifireMux_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[326], _out_rifireMux_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[325], _out_rifireMux_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[324], _out_rifireMux_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[323], _out_rifireMux_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[322], _out_rifireMux_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[321], _out_rifireMux_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[320], _out_rifireMux_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1031 = eq(_out_T_1404, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1032 = or(out_rifireMux_out_256, _out_rifireMux_T_1031) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_257 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1033 = and(_out_rifireMux_T_260, out_frontSel_193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1034 = and(_out_rifireMux_T_1033, _out_T_1430) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_257, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[425], _out_rifireMux_T_1034 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[424], _out_rifireMux_T_1034 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[423], _out_rifireMux_T_1034 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[422], _out_rifireMux_T_1034 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[421], _out_rifireMux_T_1034 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[420], _out_rifireMux_T_1034 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[419], _out_rifireMux_T_1034 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[418], _out_rifireMux_T_1034 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1035 = eq(_out_T_1430, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1036 = or(out_rifireMux_out_257, _out_rifireMux_T_1035) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_258 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1037 = and(_out_rifireMux_T_260, out_frontSel_194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1038 = and(_out_rifireMux_T_1037, _out_T_1536) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_258, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[826], _out_rifireMux_T_1038 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[825], _out_rifireMux_T_1038 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[824], _out_rifireMux_T_1038 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[823], _out_rifireMux_T_1038 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[822], _out_rifireMux_T_1038 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[821], _out_rifireMux_T_1038 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[820], _out_rifireMux_T_1038 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[819], _out_rifireMux_T_1038 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1039 = eq(_out_T_1536, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1040 = or(out_rifireMux_out_258, _out_rifireMux_T_1039) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_259 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1041 = and(_out_rifireMux_T_260, out_frontSel_195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1042 = and(_out_rifireMux_T_1041, _out_T_1602) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_259, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1090], _out_rifireMux_T_1042 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1089], _out_rifireMux_T_1042 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1088], _out_rifireMux_T_1042 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1087], _out_rifireMux_T_1042 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1086], _out_rifireMux_T_1042 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1085], _out_rifireMux_T_1042 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1084], _out_rifireMux_T_1042 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1083], _out_rifireMux_T_1042 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1043 = eq(_out_T_1602, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1044 = or(out_rifireMux_out_259, _out_rifireMux_T_1043) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_260 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1045 = and(_out_rifireMux_T_260, out_frontSel_196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1046 = and(_out_rifireMux_T_1045, _out_T_1352) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_260, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[119], _out_rifireMux_T_1046 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[118], _out_rifireMux_T_1046 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[117], _out_rifireMux_T_1046 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[116], _out_rifireMux_T_1046 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[115], _out_rifireMux_T_1046 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[114], _out_rifireMux_T_1046 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[113], _out_rifireMux_T_1046 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[112], _out_rifireMux_T_1046 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1047 = eq(_out_T_1352, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1048 = or(out_rifireMux_out_260, _out_rifireMux_T_1047) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_261 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1049 = and(_out_rifireMux_T_260, out_frontSel_197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1050 = and(_out_rifireMux_T_1049, _out_T_1416) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_261, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[369], _out_rifireMux_T_1050 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[368], _out_rifireMux_T_1050 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[367], _out_rifireMux_T_1050 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[366], _out_rifireMux_T_1050 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[365], _out_rifireMux_T_1050 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[364], _out_rifireMux_T_1050 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[363], _out_rifireMux_T_1050 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[362], _out_rifireMux_T_1050 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1051 = eq(_out_T_1416, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1052 = or(out_rifireMux_out_261, _out_rifireMux_T_1051) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_262 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1053 = and(_out_rifireMux_T_260, out_frontSel_198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1054 = and(_out_rifireMux_T_1053, _out_T_1508) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_262, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[714], _out_rifireMux_T_1054 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[713], _out_rifireMux_T_1054 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[712], _out_rifireMux_T_1054 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[711], _out_rifireMux_T_1054 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[710], _out_rifireMux_T_1054 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[709], _out_rifireMux_T_1054 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[708], _out_rifireMux_T_1054 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[707], _out_rifireMux_T_1054 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1055 = eq(_out_T_1508, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1056 = or(out_rifireMux_out_262, _out_rifireMux_T_1055) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_263 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1057 = and(_out_rifireMux_T_260, out_frontSel_199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1058 = and(_out_rifireMux_T_1057, _out_T_1544) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_263, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[858], _out_rifireMux_T_1058 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[857], _out_rifireMux_T_1058 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[856], _out_rifireMux_T_1058 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[855], _out_rifireMux_T_1058 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[854], _out_rifireMux_T_1058 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[853], _out_rifireMux_T_1058 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[852], _out_rifireMux_T_1058 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[851], _out_rifireMux_T_1058 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1059 = eq(_out_T_1544, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1060 = or(out_rifireMux_out_263, _out_rifireMux_T_1059) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_264 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1061 = and(_out_rifireMux_T_260, out_frontSel_200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1062 = and(_out_rifireMux_T_1061, _out_T_1614) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_264, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1138], _out_rifireMux_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1137], _out_rifireMux_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1136], _out_rifireMux_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1135], _out_rifireMux_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1134], _out_rifireMux_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1133], _out_rifireMux_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1132], _out_rifireMux_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1131], _out_rifireMux_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1063 = eq(_out_T_1614, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1064 = or(out_rifireMux_out_264, _out_rifireMux_T_1063) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_265 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1065 = and(_out_rifireMux_T_260, out_frontSel_201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1066 = and(_out_rifireMux_T_1065, _out_T_1396) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_265, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[295], _out_rifireMux_T_1066 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[294], _out_rifireMux_T_1066 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[293], _out_rifireMux_T_1066 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[292], _out_rifireMux_T_1066 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[291], _out_rifireMux_T_1066 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[290], _out_rifireMux_T_1066 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[289], _out_rifireMux_T_1066 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[288], _out_rifireMux_T_1066 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1067 = eq(_out_T_1396, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1068 = or(out_rifireMux_out_265, _out_rifireMux_T_1067) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_266 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1069 = and(_out_rifireMux_T_260, out_frontSel_202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1070 = and(_out_rifireMux_T_1069, _out_T_1336) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_266, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[55], _out_rifireMux_T_1070 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[54], _out_rifireMux_T_1070 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[53], _out_rifireMux_T_1070 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[52], _out_rifireMux_T_1070 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[51], _out_rifireMux_T_1070 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[50], _out_rifireMux_T_1070 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[49], _out_rifireMux_T_1070 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[48], _out_rifireMux_T_1070 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1071 = eq(_out_T_1336, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1072 = or(out_rifireMux_out_266, _out_rifireMux_T_1071) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_267 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1073 = and(_out_rifireMux_T_260, out_frontSel_203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1074 = and(_out_rifireMux_T_1073, _out_T_1556) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_267, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[906], _out_rifireMux_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[905], _out_rifireMux_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[904], _out_rifireMux_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[903], _out_rifireMux_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[902], _out_rifireMux_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[901], _out_rifireMux_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[900], _out_rifireMux_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[899], _out_rifireMux_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1075 = eq(_out_T_1556, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1076 = or(out_rifireMux_out_267, _out_rifireMux_T_1075) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_268 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1077 = and(_out_rifireMux_T_260, out_frontSel_204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1078 = and(_out_rifireMux_T_1077, _out_T_1476) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_268, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[592], _out_rifireMux_T_1078 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[591], _out_rifireMux_T_1078 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[590], _out_rifireMux_T_1078 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[589], _out_rifireMux_T_1078 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[588], _out_rifireMux_T_1078 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[587], _out_rifireMux_T_1078 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[586], _out_rifireMux_T_1078 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[585], _out_rifireMux_T_1078 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1079 = eq(_out_T_1476, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1080 = or(out_rifireMux_out_268, _out_rifireMux_T_1079) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_269 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1081 = and(_out_rifireMux_T_260, out_frontSel_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1082 = and(_out_rifireMux_T_1081, _out_T_1448) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_269, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[486], _out_rifireMux_T_1082 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[485], _out_rifireMux_T_1082 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[484], _out_rifireMux_T_1082 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[483], _out_rifireMux_T_1082 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[482], _out_rifireMux_T_1082 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[481], _out_rifireMux_T_1082 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[480], _out_rifireMux_T_1082 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[479], _out_rifireMux_T_1082 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1083 = eq(_out_T_1448, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1084 = or(out_rifireMux_out_269, _out_rifireMux_T_1083) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_270 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1085 = and(_out_rifireMux_T_260, out_frontSel_206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1086 = and(_out_rifireMux_T_1085, _out_T_1390) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_270, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[271], _out_rifireMux_T_1086 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[270], _out_rifireMux_T_1086 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[269], _out_rifireMux_T_1086 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[268], _out_rifireMux_T_1086 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[267], _out_rifireMux_T_1086 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[266], _out_rifireMux_T_1086 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[265], _out_rifireMux_T_1086 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[264], _out_rifireMux_T_1086 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1087 = eq(_out_T_1390, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1088 = or(out_rifireMux_out_270, _out_rifireMux_T_1087) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_271 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1089 = and(_out_rifireMux_T_260, out_frontSel_207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1090 = and(_out_rifireMux_T_1089, _out_T_1576) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_271, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[986], _out_rifireMux_T_1090 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[985], _out_rifireMux_T_1090 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[984], _out_rifireMux_T_1090 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[983], _out_rifireMux_T_1090 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[982], _out_rifireMux_T_1090 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[981], _out_rifireMux_T_1090 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[980], _out_rifireMux_T_1090 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[979], _out_rifireMux_T_1090 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1091 = eq(_out_T_1576, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1092 = or(out_rifireMux_out_271, _out_rifireMux_T_1091) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_272 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1093 = and(_out_rifireMux_T_260, out_frontSel_208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1094 = and(_out_rifireMux_T_1093, _out_T_1498) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_272, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[680], _out_rifireMux_T_1094 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[679], _out_rifireMux_T_1094 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[678], _out_rifireMux_T_1094 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[677], _out_rifireMux_T_1094 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[676], _out_rifireMux_T_1094 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[675], _out_rifireMux_T_1094 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[674], _out_rifireMux_T_1094 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[673], _out_rifireMux_T_1094 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1095 = eq(_out_T_1498, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1096 = or(out_rifireMux_out_272, _out_rifireMux_T_1095) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_273 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1097 = and(_out_rifireMux_T_260, out_frontSel_209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1098 = and(_out_rifireMux_T_1097, _out_T_1532) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_273, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[810], _out_rifireMux_T_1098 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[809], _out_rifireMux_T_1098 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[808], _out_rifireMux_T_1098 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[807], _out_rifireMux_T_1098 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[806], _out_rifireMux_T_1098 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[805], _out_rifireMux_T_1098 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[804], _out_rifireMux_T_1098 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[803], _out_rifireMux_T_1098 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1099 = eq(_out_T_1532, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1100 = or(out_rifireMux_out_273, _out_rifireMux_T_1099) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_274 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1101 = and(_out_rifireMux_T_260, out_frontSel_210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1102 = and(_out_rifireMux_T_1101, _out_T_1596) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_274, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1066], _out_rifireMux_T_1102 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1065], _out_rifireMux_T_1102 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1064], _out_rifireMux_T_1102 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1063], _out_rifireMux_T_1102 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1062], _out_rifireMux_T_1102 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1061], _out_rifireMux_T_1102 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1060], _out_rifireMux_T_1102 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1059], _out_rifireMux_T_1102 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1103 = eq(_out_T_1596, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1104 = or(out_rifireMux_out_274, _out_rifireMux_T_1103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_275 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1105 = and(_out_rifireMux_T_260, out_frontSel_211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1106 = and(_out_rifireMux_T_1105, _out_T_1374) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_275, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[207], _out_rifireMux_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[206], _out_rifireMux_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[205], _out_rifireMux_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[204], _out_rifireMux_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[203], _out_rifireMux_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[202], _out_rifireMux_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[201], _out_rifireMux_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[200], _out_rifireMux_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1107 = eq(_out_T_1374, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1108 = or(out_rifireMux_out_275, _out_rifireMux_T_1107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_276 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1109 = and(_out_rifireMux_T_260, out_frontSel_212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1110 = and(_out_rifireMux_T_1109, _out_T_1432) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_276, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[433], _out_rifireMux_T_1110 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[432], _out_rifireMux_T_1110 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[431], _out_rifireMux_T_1110 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[430], _out_rifireMux_T_1110 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[429], _out_rifireMux_T_1110 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[428], _out_rifireMux_T_1110 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[427], _out_rifireMux_T_1110 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[426], _out_rifireMux_T_1110 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1111 = eq(_out_T_1432, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1112 = or(out_rifireMux_out_276, _out_rifireMux_T_1111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_277 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1113 = and(_out_rifireMux_T_260, out_frontSel_213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1114 = and(_out_rifireMux_T_1113, _out_T_1504) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_277, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[698], _out_rifireMux_T_1114 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[697], _out_rifireMux_T_1114 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[696], _out_rifireMux_T_1114 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[695], _out_rifireMux_T_1114 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[694], _out_rifireMux_T_1114 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[693], _out_rifireMux_T_1114 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[692], _out_rifireMux_T_1114 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[691], _out_rifireMux_T_1114 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1115 = eq(_out_T_1504, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1116 = or(out_rifireMux_out_277, _out_rifireMux_T_1115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_278 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1117 = and(_out_rifireMux_T_260, out_frontSel_214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1118 = and(_out_rifireMux_T_1117, _out_T_1578) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_278, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[994], _out_rifireMux_T_1118 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[993], _out_rifireMux_T_1118 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[992], _out_rifireMux_T_1118 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[991], _out_rifireMux_T_1118 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[990], _out_rifireMux_T_1118 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[989], _out_rifireMux_T_1118 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[988], _out_rifireMux_T_1118 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[987], _out_rifireMux_T_1118 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1119 = eq(_out_T_1578, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1120 = or(out_rifireMux_out_278, _out_rifireMux_T_1119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_279 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1121 = and(_out_rifireMux_T_260, out_frontSel_215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1122 = and(_out_rifireMux_T_1121, _out_T_1618) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_279, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1154], _out_rifireMux_T_1122 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1153], _out_rifireMux_T_1122 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1152], _out_rifireMux_T_1122 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1151], _out_rifireMux_T_1122 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1150], _out_rifireMux_T_1122 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1149], _out_rifireMux_T_1122 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1148], _out_rifireMux_T_1122 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1147], _out_rifireMux_T_1122 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1123 = eq(_out_T_1618, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1124 = or(out_rifireMux_out_279, _out_rifireMux_T_1123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_280 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1125 = and(_out_rifireMux_T_260, out_frontSel_216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1126 = and(_out_rifireMux_T_1125, _out_T_1364) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_280, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[167], _out_rifireMux_T_1126 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[166], _out_rifireMux_T_1126 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[165], _out_rifireMux_T_1126 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[164], _out_rifireMux_T_1126 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[163], _out_rifireMux_T_1126 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[162], _out_rifireMux_T_1126 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[161], _out_rifireMux_T_1126 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[160], _out_rifireMux_T_1126 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1127 = eq(_out_T_1364, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1128 = or(out_rifireMux_out_280, _out_rifireMux_T_1127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_281 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1129 = and(_out_rifireMux_T_260, out_frontSel_217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1130 = and(_out_rifireMux_T_1129, _out_T_1332) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_281, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[39], _out_rifireMux_T_1130 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[38], _out_rifireMux_T_1130 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[37], _out_rifireMux_T_1130 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[36], _out_rifireMux_T_1130 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[35], _out_rifireMux_T_1130 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[34], _out_rifireMux_T_1130 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[33], _out_rifireMux_T_1130 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[32], _out_rifireMux_T_1130 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1131 = eq(_out_T_1332, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1132 = or(out_rifireMux_out_281, _out_rifireMux_T_1131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_282 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1133 = and(_out_rifireMux_T_260, out_frontSel_218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1134 = and(_out_rifireMux_T_1133, _out_T_1558) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_282, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[914], _out_rifireMux_T_1134 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[913], _out_rifireMux_T_1134 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[912], _out_rifireMux_T_1134 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[911], _out_rifireMux_T_1134 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[910], _out_rifireMux_T_1134 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[909], _out_rifireMux_T_1134 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[908], _out_rifireMux_T_1134 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[907], _out_rifireMux_T_1134 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1135 = eq(_out_T_1558, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1136 = or(out_rifireMux_out_282, _out_rifireMux_T_1135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_283 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1137 = and(_out_rifireMux_T_260, out_frontSel_219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1138 = and(_out_rifireMux_T_1137, _out_T_1492) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_283, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[656], _out_rifireMux_T_1138 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[655], _out_rifireMux_T_1138 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[654], _out_rifireMux_T_1138 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[653], _out_rifireMux_T_1138 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[652], _out_rifireMux_T_1138 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[651], _out_rifireMux_T_1138 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[650], _out_rifireMux_T_1138 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[649], _out_rifireMux_T_1138 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1139 = eq(_out_T_1492, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1140 = or(out_rifireMux_out_283, _out_rifireMux_T_1139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_284 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1141 = and(_out_rifireMux_T_260, out_frontSel_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1142 = and(_out_rifireMux_T_1141, _out_T_1398) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_284, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[303], _out_rifireMux_T_1142 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[302], _out_rifireMux_T_1142 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[301], _out_rifireMux_T_1142 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[300], _out_rifireMux_T_1142 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[299], _out_rifireMux_T_1142 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[298], _out_rifireMux_T_1142 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[297], _out_rifireMux_T_1142 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[296], _out_rifireMux_T_1142 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1143 = eq(_out_T_1398, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1144 = or(out_rifireMux_out_284, _out_rifireMux_T_1143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_285 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1145 = and(_out_rifireMux_T_260, out_frontSel_221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1146 = and(_out_rifireMux_T_1145, _out_T_1380) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_285, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[231], _out_rifireMux_T_1146 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[230], _out_rifireMux_T_1146 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[229], _out_rifireMux_T_1146 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[228], _out_rifireMux_T_1146 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[227], _out_rifireMux_T_1146 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[226], _out_rifireMux_T_1146 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[225], _out_rifireMux_T_1146 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[224], _out_rifireMux_T_1146 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1147 = eq(_out_T_1380, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1148 = or(out_rifireMux_out_285, _out_rifireMux_T_1147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_286 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1149 = and(_out_rifireMux_T_260, out_frontSel_222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1150 = and(_out_rifireMux_T_1149, _out_T_1620) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_286, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1162], _out_rifireMux_T_1150 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1161], _out_rifireMux_T_1150 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1160], _out_rifireMux_T_1150 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1159], _out_rifireMux_T_1150 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1158], _out_rifireMux_T_1150 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1157], _out_rifireMux_T_1150 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1156], _out_rifireMux_T_1150 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1155], _out_rifireMux_T_1150 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1151 = eq(_out_T_1620, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1152 = or(out_rifireMux_out_286, _out_rifireMux_T_1151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_287 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1153 = and(_out_rifireMux_T_260, out_frontSel_223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1154 = and(_out_rifireMux_T_1153, _out_T_1518) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_287, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[754], _out_rifireMux_T_1154 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[753], _out_rifireMux_T_1154 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[752], _out_rifireMux_T_1154 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[751], _out_rifireMux_T_1154 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[750], _out_rifireMux_T_1154 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[749], _out_rifireMux_T_1154 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[748], _out_rifireMux_T_1154 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[747], _out_rifireMux_T_1154 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1155 = eq(_out_T_1518, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1156 = or(out_rifireMux_out_287, _out_rifireMux_T_1155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_288 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1157 = and(_out_rifireMux_T_260, out_frontSel_224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1158 = and(_out_rifireMux_T_1157, _out_T_1418) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_288, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[377], _out_rifireMux_T_1158 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[376], _out_rifireMux_T_1158 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[375], _out_rifireMux_T_1158 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[374], _out_rifireMux_T_1158 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[373], _out_rifireMux_T_1158 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[372], _out_rifireMux_T_1158 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[371], _out_rifireMux_T_1158 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[370], _out_rifireMux_T_1158 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1159 = eq(_out_T_1418, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1160 = or(out_rifireMux_out_288, _out_rifireMux_T_1159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_289 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1161 = and(_out_rifireMux_T_260, out_frontSel_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1162 = and(_out_rifireMux_T_1161, _out_T_1428) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_289, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[417], _out_rifireMux_T_1162 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[416], _out_rifireMux_T_1162 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[415], _out_rifireMux_T_1162 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[414], _out_rifireMux_T_1162 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[413], _out_rifireMux_T_1162 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[412], _out_rifireMux_T_1162 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[411], _out_rifireMux_T_1162 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[410], _out_rifireMux_T_1162 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1163 = eq(_out_T_1428, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1164 = or(out_rifireMux_out_289, _out_rifireMux_T_1163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_290 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1165 = and(_out_rifireMux_T_260, out_frontSel_226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1166 = and(_out_rifireMux_T_1165, _out_T_1522) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_290, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[770], _out_rifireMux_T_1166 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[769], _out_rifireMux_T_1166 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[768], _out_rifireMux_T_1166 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[767], _out_rifireMux_T_1166 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[766], _out_rifireMux_T_1166 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[765], _out_rifireMux_T_1166 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[764], _out_rifireMux_T_1166 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[763], _out_rifireMux_T_1166 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1167 = eq(_out_T_1522, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1168 = or(out_rifireMux_out_290, _out_rifireMux_T_1167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_291 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1169 = and(_out_rifireMux_T_260, out_frontSel_227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1170 = and(_out_rifireMux_T_1169, _out_T_1626) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_291, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1186], _out_rifireMux_T_1170 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1185], _out_rifireMux_T_1170 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1184], _out_rifireMux_T_1170 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1183], _out_rifireMux_T_1170 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1182], _out_rifireMux_T_1170 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1181], _out_rifireMux_T_1170 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1180], _out_rifireMux_T_1170 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1179], _out_rifireMux_T_1170 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1171 = eq(_out_T_1626, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1172 = or(out_rifireMux_out_291, _out_rifireMux_T_1171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_292 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1173 = and(_out_rifireMux_T_260, out_frontSel_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1174 = and(_out_rifireMux_T_1173, _out_T_1360) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_292, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[151], _out_rifireMux_T_1174 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[150], _out_rifireMux_T_1174 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[149], _out_rifireMux_T_1174 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[148], _out_rifireMux_T_1174 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[147], _out_rifireMux_T_1174 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[146], _out_rifireMux_T_1174 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[145], _out_rifireMux_T_1174 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[144], _out_rifireMux_T_1174 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1175 = eq(_out_T_1360, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1176 = or(out_rifireMux_out_292, _out_rifireMux_T_1175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_293 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1177 = and(_out_rifireMux_T_260, out_frontSel_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1178 = and(_out_rifireMux_T_1177, _out_T_1412) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_293, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[353], _out_rifireMux_T_1178 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[352], _out_rifireMux_T_1178 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[351], _out_rifireMux_T_1178 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[350], _out_rifireMux_T_1178 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[349], _out_rifireMux_T_1178 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[348], _out_rifireMux_T_1178 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[347], _out_rifireMux_T_1178 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[346], _out_rifireMux_T_1178 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1179 = eq(_out_T_1412, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1180 = or(out_rifireMux_out_293, _out_rifireMux_T_1179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_294 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1181 = and(_out_rifireMux_T_260, out_frontSel_230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1182 = and(_out_rifireMux_T_1181, _out_T_1494) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_294, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[664], _out_rifireMux_T_1182 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[663], _out_rifireMux_T_1182 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[662], _out_rifireMux_T_1182 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[661], _out_rifireMux_T_1182 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[660], _out_rifireMux_T_1182 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[659], _out_rifireMux_T_1182 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[658], _out_rifireMux_T_1182 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[657], _out_rifireMux_T_1182 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1183 = eq(_out_T_1494, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1184 = or(out_rifireMux_out_294, _out_rifireMux_T_1183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_295 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1185 = and(_out_rifireMux_T_260, out_frontSel_231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1186 = and(_out_rifireMux_T_1185, _out_T_1564) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_295, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[938], _out_rifireMux_T_1186 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[937], _out_rifireMux_T_1186 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[936], _out_rifireMux_T_1186 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[935], _out_rifireMux_T_1186 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[934], _out_rifireMux_T_1186 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[933], _out_rifireMux_T_1186 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[932], _out_rifireMux_T_1186 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[931], _out_rifireMux_T_1186 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1187 = eq(_out_T_1564, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1188 = or(out_rifireMux_out_295, _out_rifireMux_T_1187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_296 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1189 = and(_out_rifireMux_T_260, out_frontSel_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1190 = and(_out_rifireMux_T_1189, _out_T_1622) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_296, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1170], _out_rifireMux_T_1190 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1169], _out_rifireMux_T_1190 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1168], _out_rifireMux_T_1190 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1167], _out_rifireMux_T_1190 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1166], _out_rifireMux_T_1190 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1165], _out_rifireMux_T_1190 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1164], _out_rifireMux_T_1190 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1163], _out_rifireMux_T_1190 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1191 = eq(_out_T_1622, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1192 = or(out_rifireMux_out_296, _out_rifireMux_T_1191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_297 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1193 = and(_out_rifireMux_T_260, out_frontSel_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1194 = and(_out_rifireMux_T_1193, _out_T_1392) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_297, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[279], _out_rifireMux_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[278], _out_rifireMux_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[277], _out_rifireMux_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[276], _out_rifireMux_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[275], _out_rifireMux_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[274], _out_rifireMux_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[273], _out_rifireMux_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[272], _out_rifireMux_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1195 = eq(_out_T_1392, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1196 = or(out_rifireMux_out_297, _out_rifireMux_T_1195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_298 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1197 = and(_out_rifireMux_T_260, out_frontSel_234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1198 = and(_out_rifireMux_T_1197, _out_T_1328) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_298, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[23], _out_rifireMux_T_1198 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[22], _out_rifireMux_T_1198 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[21], _out_rifireMux_T_1198 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[20], _out_rifireMux_T_1198 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[19], _out_rifireMux_T_1198 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[18], _out_rifireMux_T_1198 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[17], _out_rifireMux_T_1198 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[16], _out_rifireMux_T_1198 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1199 = eq(_out_T_1328, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1200 = or(out_rifireMux_out_298, _out_rifireMux_T_1199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_299 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1201 = and(_out_rifireMux_T_260, out_frontSel_235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1202 = and(_out_rifireMux_T_1201, _out_T_1580) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_299, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1002], _out_rifireMux_T_1202 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1001], _out_rifireMux_T_1202 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1000], _out_rifireMux_T_1202 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[999], _out_rifireMux_T_1202 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[998], _out_rifireMux_T_1202 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[997], _out_rifireMux_T_1202 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[996], _out_rifireMux_T_1202 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[995], _out_rifireMux_T_1202 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1203 = eq(_out_T_1580, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1204 = or(out_rifireMux_out_299, _out_rifireMux_T_1203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_300 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1205 = and(_out_rifireMux_T_260, out_frontSel_236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1206 = and(_out_rifireMux_T_1205, _out_T_1482) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_300, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[616], _out_rifireMux_T_1206 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[615], _out_rifireMux_T_1206 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[614], _out_rifireMux_T_1206 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[613], _out_rifireMux_T_1206 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[612], _out_rifireMux_T_1206 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[611], _out_rifireMux_T_1206 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[610], _out_rifireMux_T_1206 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[609], _out_rifireMux_T_1206 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1207 = eq(_out_T_1482, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1208 = or(out_rifireMux_out_300, _out_rifireMux_T_1207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_301 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1209 = and(_out_rifireMux_T_260, out_frontSel_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1210 = and(_out_rifireMux_T_1209, _out_T_1452) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_301, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[502], _out_rifireMux_T_1210 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[501], _out_rifireMux_T_1210 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[500], _out_rifireMux_T_1210 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[499], _out_rifireMux_T_1210 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[498], _out_rifireMux_T_1210 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[497], _out_rifireMux_T_1210 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[496], _out_rifireMux_T_1210 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[495], _out_rifireMux_T_1210 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1211 = eq(_out_T_1452, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1212 = or(out_rifireMux_out_301, _out_rifireMux_T_1211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_302 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1213 = and(_out_rifireMux_T_260, out_frontSel_238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1214 = and(_out_rifireMux_T_1213, _out_T_1372) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_302, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[199], _out_rifireMux_T_1214 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[198], _out_rifireMux_T_1214 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[197], _out_rifireMux_T_1214 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[196], _out_rifireMux_T_1214 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[195], _out_rifireMux_T_1214 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[194], _out_rifireMux_T_1214 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[193], _out_rifireMux_T_1214 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[192], _out_rifireMux_T_1214 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1215 = eq(_out_T_1372, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1216 = or(out_rifireMux_out_302, _out_rifireMux_T_1215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_303 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1217 = and(_out_rifireMux_T_260, out_frontSel_239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1218 = and(_out_rifireMux_T_1217, _out_T_1604) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_303, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1098], _out_rifireMux_T_1218 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1097], _out_rifireMux_T_1218 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1096], _out_rifireMux_T_1218 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1095], _out_rifireMux_T_1218 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1094], _out_rifireMux_T_1218 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1093], _out_rifireMux_T_1218 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1092], _out_rifireMux_T_1218 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1091], _out_rifireMux_T_1218 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1219 = eq(_out_T_1604, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1220 = or(out_rifireMux_out_303, _out_rifireMux_T_1219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_304 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1221 = and(_out_rifireMux_T_260, out_frontSel_240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1222 = and(_out_rifireMux_T_1221, _out_T_1512) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_304, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[730], _out_rifireMux_T_1222 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[729], _out_rifireMux_T_1222 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[728], _out_rifireMux_T_1222 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[727], _out_rifireMux_T_1222 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[726], _out_rifireMux_T_1222 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[725], _out_rifireMux_T_1222 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[724], _out_rifireMux_T_1222 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[723], _out_rifireMux_T_1222 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1223 = eq(_out_T_1512, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1224 = or(out_rifireMux_out_304, _out_rifireMux_T_1223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_305 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1225 = and(_out_rifireMux_T_260, out_frontSel_241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1226 = and(_out_rifireMux_T_1225, _out_T_1524) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_305, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[778], _out_rifireMux_T_1226 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[777], _out_rifireMux_T_1226 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[776], _out_rifireMux_T_1226 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[775], _out_rifireMux_T_1226 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[774], _out_rifireMux_T_1226 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[773], _out_rifireMux_T_1226 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[772], _out_rifireMux_T_1226 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[771], _out_rifireMux_T_1226 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1227 = eq(_out_T_1524, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1228 = or(out_rifireMux_out_305, _out_rifireMux_T_1227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_306 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1229 = and(_out_rifireMux_T_260, out_frontSel_242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1230 = and(_out_rifireMux_T_1229, _out_T_1606) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_306, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1106], _out_rifireMux_T_1230 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1105], _out_rifireMux_T_1230 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1104], _out_rifireMux_T_1230 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1103], _out_rifireMux_T_1230 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1102], _out_rifireMux_T_1230 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1101], _out_rifireMux_T_1230 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1100], _out_rifireMux_T_1230 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1099], _out_rifireMux_T_1230 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1231 = eq(_out_T_1606, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1232 = or(out_rifireMux_out_306, _out_rifireMux_T_1231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_307 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1233 = and(_out_rifireMux_T_260, out_frontSel_243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1234 = and(_out_rifireMux_T_1233, _out_T_1386) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_307, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[255], _out_rifireMux_T_1234 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[254], _out_rifireMux_T_1234 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[253], _out_rifireMux_T_1234 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[252], _out_rifireMux_T_1234 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[251], _out_rifireMux_T_1234 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[250], _out_rifireMux_T_1234 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[249], _out_rifireMux_T_1234 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[248], _out_rifireMux_T_1234 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1235 = eq(_out_T_1386, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1236 = or(out_rifireMux_out_307, _out_rifireMux_T_1235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_308 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1237 = and(_out_rifireMux_T_260, out_frontSel_244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1238 = and(_out_rifireMux_T_1237, _out_T_1456) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_308, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[518], _out_rifireMux_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[517], _out_rifireMux_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[516], _out_rifireMux_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[515], _out_rifireMux_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[514], _out_rifireMux_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[513], _out_rifireMux_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[512], _out_rifireMux_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[511], _out_rifireMux_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1239 = eq(_out_T_1456, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1240 = or(out_rifireMux_out_308, _out_rifireMux_T_1239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_309 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1241 = and(_out_rifireMux_T_260, out_frontSel_245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1242 = and(_out_rifireMux_T_1241, _out_T_1496) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_309, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[672], _out_rifireMux_T_1242 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[671], _out_rifireMux_T_1242 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[670], _out_rifireMux_T_1242 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[669], _out_rifireMux_T_1242 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[668], _out_rifireMux_T_1242 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[667], _out_rifireMux_T_1242 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[666], _out_rifireMux_T_1242 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[665], _out_rifireMux_T_1242 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1243 = eq(_out_T_1496, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1244 = or(out_rifireMux_out_309, _out_rifireMux_T_1243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_310 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1245 = and(_out_rifireMux_T_260, out_frontSel_246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1246 = and(_out_rifireMux_T_1245, _out_T_1582) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_310, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1010], _out_rifireMux_T_1246 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1009], _out_rifireMux_T_1246 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1008], _out_rifireMux_T_1246 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1007], _out_rifireMux_T_1246 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1006], _out_rifireMux_T_1246 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1005], _out_rifireMux_T_1246 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1004], _out_rifireMux_T_1246 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1003], _out_rifireMux_T_1246 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1247 = eq(_out_T_1582, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1248 = or(out_rifireMux_out_310, _out_rifireMux_T_1247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_311 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1249 = and(_out_rifireMux_T_260, out_frontSel_247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1250 = and(_out_rifireMux_T_1249, _out_T_1334) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_311, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[47], _out_rifireMux_T_1250 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[46], _out_rifireMux_T_1250 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[45], _out_rifireMux_T_1250 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[44], _out_rifireMux_T_1250 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[43], _out_rifireMux_T_1250 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[42], _out_rifireMux_T_1250 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[41], _out_rifireMux_T_1250 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[40], _out_rifireMux_T_1250 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1251 = eq(_out_T_1334, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1252 = or(out_rifireMux_out_311, _out_rifireMux_T_1251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_312 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1253 = and(_out_rifireMux_T_260, out_frontSel_248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1254 = and(_out_rifireMux_T_1253, _out_T_1394) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_312, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[287], _out_rifireMux_T_1254 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[286], _out_rifireMux_T_1254 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[285], _out_rifireMux_T_1254 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[284], _out_rifireMux_T_1254 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[283], _out_rifireMux_T_1254 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[282], _out_rifireMux_T_1254 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[281], _out_rifireMux_T_1254 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[280], _out_rifireMux_T_1254 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1255 = eq(_out_T_1394, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1256 = or(out_rifireMux_out_312, _out_rifireMux_T_1255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_313 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1257 = and(_out_rifireMux_T_260, out_frontSel_249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1258 = and(_out_rifireMux_T_1257, _out_T_1326) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_313, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[15], _out_rifireMux_T_1258 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[14], _out_rifireMux_T_1258 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[13], _out_rifireMux_T_1258 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[12], _out_rifireMux_T_1258 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[11], _out_rifireMux_T_1258 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[10], _out_rifireMux_T_1258 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[9], _out_rifireMux_T_1258 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[8], _out_rifireMux_T_1258 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1259 = eq(_out_T_1326, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1260 = or(out_rifireMux_out_313, _out_rifireMux_T_1259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_314 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1261 = and(_out_rifireMux_T_260, out_frontSel_250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1262 = and(_out_rifireMux_T_1261, _out_T_1562) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_314, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[930], _out_rifireMux_T_1262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[929], _out_rifireMux_T_1262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[928], _out_rifireMux_T_1262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[927], _out_rifireMux_T_1262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[926], _out_rifireMux_T_1262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[925], _out_rifireMux_T_1262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[924], _out_rifireMux_T_1262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[923], _out_rifireMux_T_1262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1263 = eq(_out_T_1562, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1264 = or(out_rifireMux_out_314, _out_rifireMux_T_1263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_315 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1265 = and(_out_rifireMux_T_260, out_frontSel_251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1266 = and(_out_rifireMux_T_1265, _out_T_1514) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_315, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[738], _out_rifireMux_T_1266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[737], _out_rifireMux_T_1266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[736], _out_rifireMux_T_1266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[735], _out_rifireMux_T_1266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[734], _out_rifireMux_T_1266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[733], _out_rifireMux_T_1266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[732], _out_rifireMux_T_1266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[731], _out_rifireMux_T_1266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1267 = eq(_out_T_1514, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1268 = or(out_rifireMux_out_315, _out_rifireMux_T_1267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_316 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1269 = and(_out_rifireMux_T_260, out_frontSel_252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1270 = and(_out_rifireMux_T_1269, _out_T_1414) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_316, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[361], _out_rifireMux_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[360], _out_rifireMux_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[359], _out_rifireMux_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[358], _out_rifireMux_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[357], _out_rifireMux_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[356], _out_rifireMux_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[355], _out_rifireMux_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[354], _out_rifireMux_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1271 = eq(_out_T_1414, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1272 = or(out_rifireMux_out_316, _out_rifireMux_T_1271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_317 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1273 = and(_out_rifireMux_T_260, out_frontSel_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1274 = and(_out_rifireMux_T_1273, _out_T_1376) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_317, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[215], _out_rifireMux_T_1274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[214], _out_rifireMux_T_1274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[213], _out_rifireMux_T_1274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[212], _out_rifireMux_T_1274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[211], _out_rifireMux_T_1274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[210], _out_rifireMux_T_1274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[209], _out_rifireMux_T_1274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[208], _out_rifireMux_T_1274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1275 = eq(_out_T_1376, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1276 = or(out_rifireMux_out_317, _out_rifireMux_T_1275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_318 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1277 = and(_out_rifireMux_T_260, out_frontSel_254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1278 = and(_out_rifireMux_T_1277, _out_T_1624) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_318, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1178], _out_rifireMux_T_1278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1177], _out_rifireMux_T_1278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1176], _out_rifireMux_T_1278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1175], _out_rifireMux_T_1278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1174], _out_rifireMux_T_1278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1173], _out_rifireMux_T_1278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1172], _out_rifireMux_T_1278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[1171], _out_rifireMux_T_1278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1279 = eq(_out_T_1624, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1280 = or(out_rifireMux_out_318, _out_rifireMux_T_1279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_319 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1281 = and(_out_rifireMux_T_260, out_frontSel_255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1282 = and(_out_rifireMux_T_1281, _out_T_1530) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_319, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[802], _out_rifireMux_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[801], _out_rifireMux_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[800], _out_rifireMux_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[799], _out_rifireMux_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[798], _out_rifireMux_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[797], _out_rifireMux_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[796], _out_rifireMux_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid_1[795], _out_rifireMux_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_1283 = eq(_out_T_1530, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1284 = or(out_rifireMux_out_319, _out_rifireMux_T_1283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1285 = geq(out_iindex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_rifireMux_WIRE_1 : UInt<1>[256] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[0], _out_rifireMux_T_264 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[1], _out_rifireMux_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[2], _out_rifireMux_T_272 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[3], _out_rifireMux_T_276 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[4], _out_rifireMux_T_280 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[5], _out_rifireMux_T_284 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[6], _out_rifireMux_T_288 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[7], _out_rifireMux_T_292 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[8], _out_rifireMux_T_296 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[9], _out_rifireMux_T_300 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[10], _out_rifireMux_T_304 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[11], _out_rifireMux_T_308 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[12], _out_rifireMux_T_312 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[13], _out_rifireMux_T_316 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[14], _out_rifireMux_T_320 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[15], _out_rifireMux_T_324 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[16], _out_rifireMux_T_328 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[17], _out_rifireMux_T_332 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[18], _out_rifireMux_T_336 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[19], _out_rifireMux_T_340 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[20], _out_rifireMux_T_344 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[21], _out_rifireMux_T_348 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[22], _out_rifireMux_T_352 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[23], _out_rifireMux_T_356 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[24], _out_rifireMux_T_360 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[25], _out_rifireMux_T_364 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[26], _out_rifireMux_T_368 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[27], _out_rifireMux_T_372 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[28], _out_rifireMux_T_376 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[29], _out_rifireMux_T_380 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[30], _out_rifireMux_T_384 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[31], _out_rifireMux_T_388 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[32], _out_rifireMux_T_392 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[33], _out_rifireMux_T_396 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[34], _out_rifireMux_T_400 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[35], _out_rifireMux_T_404 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[36], _out_rifireMux_T_408 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[37], _out_rifireMux_T_412 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[38], _out_rifireMux_T_416 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[39], _out_rifireMux_T_420 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[40], _out_rifireMux_T_424 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[41], _out_rifireMux_T_428 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[42], _out_rifireMux_T_432 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[43], _out_rifireMux_T_436 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[44], _out_rifireMux_T_440 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[45], _out_rifireMux_T_444 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[46], _out_rifireMux_T_448 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[47], _out_rifireMux_T_452 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[48], _out_rifireMux_T_456 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[49], _out_rifireMux_T_460 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[50], _out_rifireMux_T_464 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[51], _out_rifireMux_T_468 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[52], _out_rifireMux_T_472 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[53], _out_rifireMux_T_476 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[54], _out_rifireMux_T_480 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[55], _out_rifireMux_T_484 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[56], _out_rifireMux_T_488 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[57], _out_rifireMux_T_492 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[58], _out_rifireMux_T_496 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[59], _out_rifireMux_T_500 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[60], _out_rifireMux_T_504 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[61], _out_rifireMux_T_508 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[62], _out_rifireMux_T_512 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[63], _out_rifireMux_T_516 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[64], _out_rifireMux_T_520 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[65], _out_rifireMux_T_524 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[66], _out_rifireMux_T_528 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[67], _out_rifireMux_T_532 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[68], _out_rifireMux_T_536 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[69], _out_rifireMux_T_540 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[70], _out_rifireMux_T_544 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[71], _out_rifireMux_T_548 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[72], _out_rifireMux_T_552 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[73], _out_rifireMux_T_556 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[74], _out_rifireMux_T_560 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[75], _out_rifireMux_T_564 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[76], _out_rifireMux_T_568 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[77], _out_rifireMux_T_572 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[78], _out_rifireMux_T_576 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[79], _out_rifireMux_T_580 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[80], _out_rifireMux_T_584 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[81], _out_rifireMux_T_588 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[82], _out_rifireMux_T_592 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[83], _out_rifireMux_T_596 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[84], _out_rifireMux_T_600 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[85], _out_rifireMux_T_604 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[86], _out_rifireMux_T_608 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[87], _out_rifireMux_T_612 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[88], _out_rifireMux_T_616 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[89], _out_rifireMux_T_620 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[90], _out_rifireMux_T_624 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[91], _out_rifireMux_T_628 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[92], _out_rifireMux_T_632 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[93], _out_rifireMux_T_636 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[94], _out_rifireMux_T_640 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[95], _out_rifireMux_T_644 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[96], _out_rifireMux_T_648 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[97], _out_rifireMux_T_652 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[98], _out_rifireMux_T_656 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[99], _out_rifireMux_T_660 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[100], _out_rifireMux_T_664 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[101], _out_rifireMux_T_668 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[102], _out_rifireMux_T_672 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[103], _out_rifireMux_T_676 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[104], _out_rifireMux_T_680 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[105], _out_rifireMux_T_684 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[106], _out_rifireMux_T_688 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[107], _out_rifireMux_T_692 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[108], _out_rifireMux_T_696 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[109], _out_rifireMux_T_700 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[110], _out_rifireMux_T_704 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[111], _out_rifireMux_T_708 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[112], _out_rifireMux_T_712 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[113], _out_rifireMux_T_716 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[114], _out_rifireMux_T_720 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[115], _out_rifireMux_T_724 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[116], _out_rifireMux_T_728 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[117], _out_rifireMux_T_732 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[118], _out_rifireMux_T_736 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[119], _out_rifireMux_T_740 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[120], _out_rifireMux_T_744 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[121], _out_rifireMux_T_748 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[122], _out_rifireMux_T_752 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[123], _out_rifireMux_T_756 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[124], _out_rifireMux_T_760 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[125], _out_rifireMux_T_764 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[126], _out_rifireMux_T_768 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[127], _out_rifireMux_T_772 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[128], _out_rifireMux_T_776 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[129], _out_rifireMux_T_780 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[130], _out_rifireMux_T_784 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[131], _out_rifireMux_T_788 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[132], _out_rifireMux_T_792 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[133], _out_rifireMux_T_796 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[134], _out_rifireMux_T_800 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[135], _out_rifireMux_T_804 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[136], _out_rifireMux_T_808 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[137], _out_rifireMux_T_812 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[138], _out_rifireMux_T_816 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[139], _out_rifireMux_T_820 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[140], _out_rifireMux_T_824 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[141], _out_rifireMux_T_828 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[142], _out_rifireMux_T_832 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[143], _out_rifireMux_T_836 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[144], _out_rifireMux_T_840 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[145], _out_rifireMux_T_844 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[146], _out_rifireMux_T_848 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[147], _out_rifireMux_T_852 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[148], _out_rifireMux_T_856 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[149], _out_rifireMux_T_860 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[150], _out_rifireMux_T_864 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[151], _out_rifireMux_T_868 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[152], _out_rifireMux_T_872 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[153], _out_rifireMux_T_876 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[154], _out_rifireMux_T_880 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[155], _out_rifireMux_T_884 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[156], _out_rifireMux_T_888 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[157], _out_rifireMux_T_892 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[158], _out_rifireMux_T_896 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[159], _out_rifireMux_T_900 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[160], _out_rifireMux_T_904 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[161], _out_rifireMux_T_908 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[162], _out_rifireMux_T_912 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[163], _out_rifireMux_T_916 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[164], _out_rifireMux_T_920 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[165], _out_rifireMux_T_924 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[166], _out_rifireMux_T_928 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[167], _out_rifireMux_T_932 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[168], _out_rifireMux_T_936 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[169], _out_rifireMux_T_940 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[170], _out_rifireMux_T_944 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[171], _out_rifireMux_T_948 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[172], _out_rifireMux_T_952 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[173], _out_rifireMux_T_956 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[174], _out_rifireMux_T_960 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[175], _out_rifireMux_T_964 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[176], _out_rifireMux_T_968 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[177], _out_rifireMux_T_972 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[178], _out_rifireMux_T_976 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[179], _out_rifireMux_T_980 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[180], _out_rifireMux_T_984 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[181], _out_rifireMux_T_988 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[182], _out_rifireMux_T_992 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[183], _out_rifireMux_T_996 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[184], _out_rifireMux_T_1000 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[185], _out_rifireMux_T_1004 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[186], _out_rifireMux_T_1008 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[187], _out_rifireMux_T_1012 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[188], _out_rifireMux_T_1016 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[189], _out_rifireMux_T_1020 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[190], _out_rifireMux_T_1024 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[191], _out_rifireMux_T_1028 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[192], _out_rifireMux_T_1032 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[193], _out_rifireMux_T_1036 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[194], _out_rifireMux_T_1040 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[195], _out_rifireMux_T_1044 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[196], _out_rifireMux_T_1048 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[197], _out_rifireMux_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[198], _out_rifireMux_T_1056 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[199], _out_rifireMux_T_1060 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[200], _out_rifireMux_T_1064 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[201], _out_rifireMux_T_1068 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[202], _out_rifireMux_T_1072 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[203], _out_rifireMux_T_1076 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[204], _out_rifireMux_T_1080 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[205], _out_rifireMux_T_1084 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[206], _out_rifireMux_T_1088 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[207], _out_rifireMux_T_1092 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[208], _out_rifireMux_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[209], _out_rifireMux_T_1100 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[210], _out_rifireMux_T_1104 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[211], _out_rifireMux_T_1108 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[212], _out_rifireMux_T_1112 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[213], _out_rifireMux_T_1116 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[214], _out_rifireMux_T_1120 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[215], _out_rifireMux_T_1124 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[216], _out_rifireMux_T_1128 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[217], _out_rifireMux_T_1132 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[218], _out_rifireMux_T_1136 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[219], _out_rifireMux_T_1140 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[220], _out_rifireMux_T_1144 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[221], _out_rifireMux_T_1148 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[222], _out_rifireMux_T_1152 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[223], _out_rifireMux_T_1156 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[224], _out_rifireMux_T_1160 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[225], _out_rifireMux_T_1164 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[226], _out_rifireMux_T_1168 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[227], _out_rifireMux_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[228], _out_rifireMux_T_1176 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[229], _out_rifireMux_T_1180 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[230], _out_rifireMux_T_1184 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[231], _out_rifireMux_T_1188 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[232], _out_rifireMux_T_1192 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[233], _out_rifireMux_T_1196 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[234], _out_rifireMux_T_1200 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[235], _out_rifireMux_T_1204 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[236], _out_rifireMux_T_1208 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[237], _out_rifireMux_T_1212 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[238], _out_rifireMux_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[239], _out_rifireMux_T_1220 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[240], _out_rifireMux_T_1224 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[241], _out_rifireMux_T_1228 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[242], _out_rifireMux_T_1232 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[243], _out_rifireMux_T_1236 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[244], _out_rifireMux_T_1240 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[245], _out_rifireMux_T_1244 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[246], _out_rifireMux_T_1248 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[247], _out_rifireMux_T_1252 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[248], _out_rifireMux_T_1256 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[249], _out_rifireMux_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[250], _out_rifireMux_T_1264 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[251], _out_rifireMux_T_1268 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[252], _out_rifireMux_T_1272 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[253], _out_rifireMux_T_1276 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[254], _out_rifireMux_T_1280 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE_1[255], _out_rifireMux_T_1284 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_rifireMux_1 = mux(_out_rifireMux_T_1285, UInt<1>(0h1), _out_rifireMux_WIRE_1[out_iindex_1]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_wifireMux_T_260 = and(in_1.valid, out_front_1.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_261 = eq(out_front_1.bits.read, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_262 = and(_out_wifireMux_T_260, _out_wifireMux_T_261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_64 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_263 = and(_out_wifireMux_T_262, out_frontSel_0_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_264 = and(_out_wifireMux_T_263, _out_T_1438) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_64, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[450], _out_wifireMux_T_264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[449], _out_wifireMux_T_264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[448], _out_wifireMux_T_264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[447], _out_wifireMux_T_264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[446], _out_wifireMux_T_264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[445], _out_wifireMux_T_264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[444], _out_wifireMux_T_264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[443], _out_wifireMux_T_264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_265 = eq(_out_T_1438, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_266 = or(out_wifireMux_out_64, _out_wifireMux_T_265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_65 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_267 = and(_out_wifireMux_T_262, out_frontSel_1_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_268 = and(_out_wifireMux_T_267, _out_T_1346) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_65, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[95], _out_wifireMux_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[94], _out_wifireMux_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[93], _out_wifireMux_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[92], _out_wifireMux_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[91], _out_wifireMux_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[90], _out_wifireMux_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[89], _out_wifireMux_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[88], _out_wifireMux_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_269 = eq(_out_T_1346, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_270 = or(out_wifireMux_out_65, _out_wifireMux_T_269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_66 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_271 = and(_out_wifireMux_T_262, out_frontSel_2_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_272 = and(_out_wifireMux_T_271, _out_T_1566) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_66, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[946], _out_wifireMux_T_272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[945], _out_wifireMux_T_272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[944], _out_wifireMux_T_272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[943], _out_wifireMux_T_272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[942], _out_wifireMux_T_272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[941], _out_wifireMux_T_272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[940], _out_wifireMux_T_272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[939], _out_wifireMux_T_272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_273 = eq(_out_T_1566, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_274 = or(out_wifireMux_out_66, _out_wifireMux_T_273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_67 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_275 = and(_out_wifireMux_T_262, out_frontSel_3_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_276 = and(_out_wifireMux_T_275, _out_T_1478) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_67, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[600], _out_wifireMux_T_276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[599], _out_wifireMux_T_276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[598], _out_wifireMux_T_276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[597], _out_wifireMux_T_276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[596], _out_wifireMux_T_276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[595], _out_wifireMux_T_276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[594], _out_wifireMux_T_276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[593], _out_wifireMux_T_276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_277 = eq(_out_T_1478, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_278 = or(out_wifireMux_out_67, _out_wifireMux_T_277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_68 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_279 = and(_out_wifireMux_T_262, out_frontSel_4_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_280 = and(_out_wifireMux_T_279, _out_T_1400) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_68, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[311], _out_wifireMux_T_280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[310], _out_wifireMux_T_280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[309], _out_wifireMux_T_280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[308], _out_wifireMux_T_280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[307], _out_wifireMux_T_280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[306], _out_wifireMux_T_280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[305], _out_wifireMux_T_280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[304], _out_wifireMux_T_280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_281 = eq(_out_T_1400, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_282 = or(out_wifireMux_out_68, _out_wifireMux_T_281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_69 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_283 = and(_out_wifireMux_T_262, out_frontSel_5_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_284 = and(_out_wifireMux_T_283, _out_T_1362) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_69, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[159], _out_wifireMux_T_284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[158], _out_wifireMux_T_284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[157], _out_wifireMux_T_284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[156], _out_wifireMux_T_284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[155], _out_wifireMux_T_284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[154], _out_wifireMux_T_284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[153], _out_wifireMux_T_284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[152], _out_wifireMux_T_284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_285 = eq(_out_T_1362, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_286 = or(out_wifireMux_out_69, _out_wifireMux_T_285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_70 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_287 = and(_out_wifireMux_T_262, out_frontSel_6_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_288 = and(_out_wifireMux_T_287, _out_T_1594) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_70, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1058], _out_wifireMux_T_288 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1057], _out_wifireMux_T_288 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1056], _out_wifireMux_T_288 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1055], _out_wifireMux_T_288 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1054], _out_wifireMux_T_288 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1053], _out_wifireMux_T_288 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1052], _out_wifireMux_T_288 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1051], _out_wifireMux_T_288 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_289 = eq(_out_T_1594, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_290 = or(out_wifireMux_out_70, _out_wifireMux_T_289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_71 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_291 = and(_out_wifireMux_T_262, out_frontSel_7_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_292 = and(_out_wifireMux_T_291, _out_T_1542) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_71, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[850], _out_wifireMux_T_292 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[849], _out_wifireMux_T_292 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[848], _out_wifireMux_T_292 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[847], _out_wifireMux_T_292 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[846], _out_wifireMux_T_292 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[845], _out_wifireMux_T_292 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[844], _out_wifireMux_T_292 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[843], _out_wifireMux_T_292 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_293 = eq(_out_T_1542, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_294 = or(out_wifireMux_out_71, _out_wifireMux_T_293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_72 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_295 = and(_out_wifireMux_T_262, out_frontSel_8_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_296 = and(_out_wifireMux_T_295, _out_T_1464) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_72, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[544], _out_wifireMux_T_296 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[543], _out_wifireMux_T_296 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[542], _out_wifireMux_T_296 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[541], _out_wifireMux_T_296 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[540], _out_wifireMux_T_296 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[539], _out_wifireMux_T_296 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[538], _out_wifireMux_T_296 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[537], _out_wifireMux_T_296 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_297 = eq(_out_T_1464, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_298 = or(out_wifireMux_out_72, _out_wifireMux_T_297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_73 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_299 = and(_out_wifireMux_T_262, out_frontSel_9_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_300 = and(_out_wifireMux_T_299, _out_T_1388) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_73, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[263], _out_wifireMux_T_300 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[262], _out_wifireMux_T_300 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[261], _out_wifireMux_T_300 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[260], _out_wifireMux_T_300 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[259], _out_wifireMux_T_300 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[258], _out_wifireMux_T_300 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[257], _out_wifireMux_T_300 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[256], _out_wifireMux_T_300 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_301 = eq(_out_T_1388, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_302 = or(out_wifireMux_out_73, _out_wifireMux_T_301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_74 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_303 = and(_out_wifireMux_T_262, out_frontSel_10_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_304 = and(_out_wifireMux_T_303, _out_T_1446) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_74, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[478], _out_wifireMux_T_304 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[477], _out_wifireMux_T_304 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[476], _out_wifireMux_T_304 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[475], _out_wifireMux_T_304 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_305 = eq(_out_T_1446, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_306 = or(out_wifireMux_out_74, _out_wifireMux_T_305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_75 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_307 = and(_out_wifireMux_T_262, out_frontSel_11_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_308 = and(_out_wifireMux_T_307, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_75, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_309 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_310 = or(out_wifireMux_out_75, _out_wifireMux_T_309) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_76 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_311 = and(_out_wifireMux_T_262, out_frontSel_12_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_312 = and(_out_wifireMux_T_311, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_76, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_313 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_314 = or(out_wifireMux_out_76, _out_wifireMux_T_313) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_77 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_315 = and(_out_wifireMux_T_262, out_frontSel_13_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_316 = and(_out_wifireMux_T_315, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_77, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_317 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_318 = or(out_wifireMux_out_77, _out_wifireMux_T_317) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_78 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_319 = and(_out_wifireMux_T_262, out_frontSel_14_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_320 = and(_out_wifireMux_T_319, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_78, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_321 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_322 = or(out_wifireMux_out_78, _out_wifireMux_T_321) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_79 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_323 = and(_out_wifireMux_T_262, out_frontSel_15_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_324 = and(_out_wifireMux_T_323, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_79, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_325 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_326 = or(out_wifireMux_out_79, _out_wifireMux_T_325) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_80 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_327 = and(_out_wifireMux_T_262, out_frontSel_16_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_328 = and(_out_wifireMux_T_327, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_80, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_329 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_330 = or(out_wifireMux_out_80, _out_wifireMux_T_329) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_81 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_331 = and(_out_wifireMux_T_262, out_frontSel_17_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_332 = and(_out_wifireMux_T_331, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_81, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_333 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_334 = or(out_wifireMux_out_81, _out_wifireMux_T_333) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_82 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_335 = and(_out_wifireMux_T_262, out_frontSel_18_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_336 = and(_out_wifireMux_T_335, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_82, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_337 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_338 = or(out_wifireMux_out_82, _out_wifireMux_T_337) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_83 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_339 = and(_out_wifireMux_T_262, out_frontSel_19_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_340 = and(_out_wifireMux_T_339, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_83, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_341 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_342 = or(out_wifireMux_out_83, _out_wifireMux_T_341) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_84 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_343 = and(_out_wifireMux_T_262, out_frontSel_20_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_344 = and(_out_wifireMux_T_343, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_84, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_345 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_346 = or(out_wifireMux_out_84, _out_wifireMux_T_345) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_85 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_347 = and(_out_wifireMux_T_262, out_frontSel_21_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_348 = and(_out_wifireMux_T_347, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_85, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_349 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_350 = or(out_wifireMux_out_85, _out_wifireMux_T_349) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_86 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_351 = and(_out_wifireMux_T_262, out_frontSel_22_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_352 = and(_out_wifireMux_T_351, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_86, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_353 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_354 = or(out_wifireMux_out_86, _out_wifireMux_T_353) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_87 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_355 = and(_out_wifireMux_T_262, out_frontSel_23_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_356 = and(_out_wifireMux_T_355, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_87, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_357 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_358 = or(out_wifireMux_out_87, _out_wifireMux_T_357) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_88 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_359 = and(_out_wifireMux_T_262, out_frontSel_24_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_360 = and(_out_wifireMux_T_359, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_88, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_361 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_362 = or(out_wifireMux_out_88, _out_wifireMux_T_361) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_89 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_363 = and(_out_wifireMux_T_262, out_frontSel_25_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_364 = and(_out_wifireMux_T_363, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_89, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_365 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_366 = or(out_wifireMux_out_89, _out_wifireMux_T_365) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_90 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_367 = and(_out_wifireMux_T_262, out_frontSel_26_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_368 = and(_out_wifireMux_T_367, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_90, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_369 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_370 = or(out_wifireMux_out_90, _out_wifireMux_T_369) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_91 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_371 = and(_out_wifireMux_T_262, out_frontSel_27_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_372 = and(_out_wifireMux_T_371, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_91, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_373 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_374 = or(out_wifireMux_out_91, _out_wifireMux_T_373) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_92 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_375 = and(_out_wifireMux_T_262, out_frontSel_28_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_376 = and(_out_wifireMux_T_375, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_92, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_377 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_378 = or(out_wifireMux_out_92, _out_wifireMux_T_377) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_93 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_379 = and(_out_wifireMux_T_262, out_frontSel_29_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_380 = and(_out_wifireMux_T_379, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_93, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_381 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_382 = or(out_wifireMux_out_93, _out_wifireMux_T_381) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_94 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_383 = and(_out_wifireMux_T_262, out_frontSel_30_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_384 = and(_out_wifireMux_T_383, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_94, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_385 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_386 = or(out_wifireMux_out_94, _out_wifireMux_T_385) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_95 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_387 = and(_out_wifireMux_T_262, out_frontSel_31_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_388 = and(_out_wifireMux_T_387, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_95, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_389 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_390 = or(out_wifireMux_out_95, _out_wifireMux_T_389) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_96 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_391 = and(_out_wifireMux_T_262, out_frontSel_32_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_392 = and(_out_wifireMux_T_391, _out_T_1460) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_96, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[528], _out_wifireMux_T_392 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[527], _out_wifireMux_T_392 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_393 = eq(_out_T_1460, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_394 = or(out_wifireMux_out_96, _out_wifireMux_T_393) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_97 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_395 = and(_out_wifireMux_T_262, out_frontSel_33_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_396 = and(_out_wifireMux_T_395, _out_T_1410) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_97, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[345], _out_wifireMux_T_396 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[344], _out_wifireMux_T_396 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_397 = eq(_out_T_1410, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_398 = or(out_wifireMux_out_97, _out_wifireMux_T_397) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_98 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_399 = and(_out_wifireMux_T_262, out_frontSel_34_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_400 = and(_out_wifireMux_T_399, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_98, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_401 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_402 = or(out_wifireMux_out_98, _out_wifireMux_T_401) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_99 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_403 = and(_out_wifireMux_T_262, out_frontSel_35_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_404 = and(_out_wifireMux_T_403, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_99, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_405 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_406 = or(out_wifireMux_out_99, _out_wifireMux_T_405) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_100 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_407 = and(_out_wifireMux_T_262, out_frontSel_36_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_408 = and(_out_wifireMux_T_407, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_100, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_409 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_410 = or(out_wifireMux_out_100, _out_wifireMux_T_409) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_101 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_411 = and(_out_wifireMux_T_262, out_frontSel_37_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_412 = and(_out_wifireMux_T_411, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_101, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_413 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_414 = or(out_wifireMux_out_101, _out_wifireMux_T_413) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_102 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_415 = and(_out_wifireMux_T_262, out_frontSel_38_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_416 = and(_out_wifireMux_T_415, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_102, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_417 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_418 = or(out_wifireMux_out_102, _out_wifireMux_T_417) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_103 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_419 = and(_out_wifireMux_T_262, out_frontSel_39_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_420 = and(_out_wifireMux_T_419, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_103, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_421 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_422 = or(out_wifireMux_out_103, _out_wifireMux_T_421) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_104 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_423 = and(_out_wifireMux_T_262, out_frontSel_40_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_424 = and(_out_wifireMux_T_423, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_104, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_425 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_426 = or(out_wifireMux_out_104, _out_wifireMux_T_425) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_105 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_427 = and(_out_wifireMux_T_262, out_frontSel_41_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_428 = and(_out_wifireMux_T_427, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_105, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_429 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_430 = or(out_wifireMux_out_105, _out_wifireMux_T_429) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_106 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_431 = and(_out_wifireMux_T_262, out_frontSel_42_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_432 = and(_out_wifireMux_T_431, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_106, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_433 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_434 = or(out_wifireMux_out_106, _out_wifireMux_T_433) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_107 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_435 = and(_out_wifireMux_T_262, out_frontSel_43_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_436 = and(_out_wifireMux_T_435, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_107, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_437 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_438 = or(out_wifireMux_out_107, _out_wifireMux_T_437) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_108 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_439 = and(_out_wifireMux_T_262, out_frontSel_44_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_440 = and(_out_wifireMux_T_439, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_108, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_441 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_442 = or(out_wifireMux_out_108, _out_wifireMux_T_441) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_109 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_443 = and(_out_wifireMux_T_262, out_frontSel_45_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_444 = and(_out_wifireMux_T_443, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_109, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_445 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_446 = or(out_wifireMux_out_109, _out_wifireMux_T_445) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_110 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_447 = and(_out_wifireMux_T_262, out_frontSel_46_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_448 = and(_out_wifireMux_T_447, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_110, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_449 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_450 = or(out_wifireMux_out_110, _out_wifireMux_T_449) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_111 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_451 = and(_out_wifireMux_T_262, out_frontSel_47_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_452 = and(_out_wifireMux_T_451, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_111, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_453 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_454 = or(out_wifireMux_out_111, _out_wifireMux_T_453) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_112 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_455 = and(_out_wifireMux_T_262, out_frontSel_48_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_456 = and(_out_wifireMux_T_455, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_112, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_457 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_458 = or(out_wifireMux_out_112, _out_wifireMux_T_457) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_113 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_459 = and(_out_wifireMux_T_262, out_frontSel_49_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_460 = and(_out_wifireMux_T_459, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_113, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_461 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_462 = or(out_wifireMux_out_113, _out_wifireMux_T_461) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_114 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_463 = and(_out_wifireMux_T_262, out_frontSel_50_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_464 = and(_out_wifireMux_T_463, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_114, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_465 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_466 = or(out_wifireMux_out_114, _out_wifireMux_T_465) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_115 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_467 = and(_out_wifireMux_T_262, out_frontSel_51_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_468 = and(_out_wifireMux_T_467, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_115, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_469 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_470 = or(out_wifireMux_out_115, _out_wifireMux_T_469) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_116 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_471 = and(_out_wifireMux_T_262, out_frontSel_52_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_472 = and(_out_wifireMux_T_471, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_116, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_473 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_474 = or(out_wifireMux_out_116, _out_wifireMux_T_473) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_117 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_475 = and(_out_wifireMux_T_262, out_frontSel_53_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_476 = and(_out_wifireMux_T_475, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_117, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_477 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_478 = or(out_wifireMux_out_117, _out_wifireMux_T_477) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_118 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_479 = and(_out_wifireMux_T_262, out_frontSel_54_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_480 = and(_out_wifireMux_T_479, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_118, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_481 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_482 = or(out_wifireMux_out_118, _out_wifireMux_T_481) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_119 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_483 = and(_out_wifireMux_T_262, out_frontSel_55_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_484 = and(_out_wifireMux_T_483, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_119, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_485 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_486 = or(out_wifireMux_out_119, _out_wifireMux_T_485) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_120 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_487 = and(_out_wifireMux_T_262, out_frontSel_56_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_488 = and(_out_wifireMux_T_487, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_120, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_489 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_490 = or(out_wifireMux_out_120, _out_wifireMux_T_489) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_121 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_491 = and(_out_wifireMux_T_262, out_frontSel_57_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_492 = and(_out_wifireMux_T_491, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_121, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_493 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_494 = or(out_wifireMux_out_121, _out_wifireMux_T_493) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_122 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_495 = and(_out_wifireMux_T_262, out_frontSel_58_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_496 = and(_out_wifireMux_T_495, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_122, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_497 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_498 = or(out_wifireMux_out_122, _out_wifireMux_T_497) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_123 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_499 = and(_out_wifireMux_T_262, out_frontSel_59_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_500 = and(_out_wifireMux_T_499, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_123, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_501 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_502 = or(out_wifireMux_out_123, _out_wifireMux_T_501) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_124 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_503 = and(_out_wifireMux_T_262, out_frontSel_60_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_504 = and(_out_wifireMux_T_503, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_124, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_505 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_506 = or(out_wifireMux_out_124, _out_wifireMux_T_505) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_125 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_507 = and(_out_wifireMux_T_262, out_frontSel_61_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_508 = and(_out_wifireMux_T_507, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_125, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_509 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_510 = or(out_wifireMux_out_125, _out_wifireMux_T_509) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_126 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_511 = and(_out_wifireMux_T_262, out_frontSel_62_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_512 = and(_out_wifireMux_T_511, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_126, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_513 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_514 = or(out_wifireMux_out_126, _out_wifireMux_T_513) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_127 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_515 = and(_out_wifireMux_T_262, out_frontSel_63_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_516 = and(_out_wifireMux_T_515, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_127, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_517 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_518 = or(out_wifireMux_out_127, _out_wifireMux_T_517) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_128 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_519 = and(_out_wifireMux_T_262, out_frontSel_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_520 = and(_out_wifireMux_T_519, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_128, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_521 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_522 = or(out_wifireMux_out_128, _out_wifireMux_T_521) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_129 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_523 = and(_out_wifireMux_T_262, out_frontSel_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_524 = and(_out_wifireMux_T_523, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_129, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_525 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_526 = or(out_wifireMux_out_129, _out_wifireMux_T_525) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_130 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_527 = and(_out_wifireMux_T_262, out_frontSel_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_528 = and(_out_wifireMux_T_527, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_130, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_529 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_530 = or(out_wifireMux_out_130, _out_wifireMux_T_529) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_131 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_531 = and(_out_wifireMux_T_262, out_frontSel_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_532 = and(_out_wifireMux_T_531, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_131, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_533 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_534 = or(out_wifireMux_out_131, _out_wifireMux_T_533) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_132 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_535 = and(_out_wifireMux_T_262, out_frontSel_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_536 = and(_out_wifireMux_T_535, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_132, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_537 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_538 = or(out_wifireMux_out_132, _out_wifireMux_T_537) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_133 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_539 = and(_out_wifireMux_T_262, out_frontSel_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_540 = and(_out_wifireMux_T_539, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_133, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_541 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_542 = or(out_wifireMux_out_133, _out_wifireMux_T_541) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_134 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_543 = and(_out_wifireMux_T_262, out_frontSel_70) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_544 = and(_out_wifireMux_T_543, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_134, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_545 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_546 = or(out_wifireMux_out_134, _out_wifireMux_T_545) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_135 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_547 = and(_out_wifireMux_T_262, out_frontSel_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_548 = and(_out_wifireMux_T_547, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_135, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_549 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_550 = or(out_wifireMux_out_135, _out_wifireMux_T_549) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_136 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_551 = and(_out_wifireMux_T_262, out_frontSel_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_552 = and(_out_wifireMux_T_551, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_136, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_553 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_554 = or(out_wifireMux_out_136, _out_wifireMux_T_553) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_137 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_555 = and(_out_wifireMux_T_262, out_frontSel_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_556 = and(_out_wifireMux_T_555, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_137, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_557 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_558 = or(out_wifireMux_out_137, _out_wifireMux_T_557) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_138 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_559 = and(_out_wifireMux_T_262, out_frontSel_74) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_560 = and(_out_wifireMux_T_559, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_138, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_561 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_562 = or(out_wifireMux_out_138, _out_wifireMux_T_561) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_139 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_563 = and(_out_wifireMux_T_262, out_frontSel_75) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_564 = and(_out_wifireMux_T_563, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_139, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_565 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_566 = or(out_wifireMux_out_139, _out_wifireMux_T_565) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_140 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_567 = and(_out_wifireMux_T_262, out_frontSel_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_568 = and(_out_wifireMux_T_567, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_140, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_569 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_570 = or(out_wifireMux_out_140, _out_wifireMux_T_569) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_141 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_571 = and(_out_wifireMux_T_262, out_frontSel_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_572 = and(_out_wifireMux_T_571, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_141, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_573 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_574 = or(out_wifireMux_out_141, _out_wifireMux_T_573) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_142 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_575 = and(_out_wifireMux_T_262, out_frontSel_78) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_576 = and(_out_wifireMux_T_575, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_142, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_577 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_578 = or(out_wifireMux_out_142, _out_wifireMux_T_577) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_143 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_579 = and(_out_wifireMux_T_262, out_frontSel_79) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_580 = and(_out_wifireMux_T_579, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_143, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_581 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_582 = or(out_wifireMux_out_143, _out_wifireMux_T_581) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_144 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_583 = and(_out_wifireMux_T_262, out_frontSel_80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_584 = and(_out_wifireMux_T_583, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_144, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_585 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_586 = or(out_wifireMux_out_144, _out_wifireMux_T_585) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_145 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_587 = and(_out_wifireMux_T_262, out_frontSel_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_588 = and(_out_wifireMux_T_587, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_145, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_589 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_590 = or(out_wifireMux_out_145, _out_wifireMux_T_589) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_146 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_591 = and(_out_wifireMux_T_262, out_frontSel_82) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_592 = and(_out_wifireMux_T_591, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_146, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_593 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_594 = or(out_wifireMux_out_146, _out_wifireMux_T_593) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_147 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_595 = and(_out_wifireMux_T_262, out_frontSel_83) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_596 = and(_out_wifireMux_T_595, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_147, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_597 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_598 = or(out_wifireMux_out_147, _out_wifireMux_T_597) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_148 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_599 = and(_out_wifireMux_T_262, out_frontSel_84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_600 = and(_out_wifireMux_T_599, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_148, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_601 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_602 = or(out_wifireMux_out_148, _out_wifireMux_T_601) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_149 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_603 = and(_out_wifireMux_T_262, out_frontSel_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_604 = and(_out_wifireMux_T_603, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_149, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_605 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_606 = or(out_wifireMux_out_149, _out_wifireMux_T_605) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_150 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_607 = and(_out_wifireMux_T_262, out_frontSel_86) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_608 = and(_out_wifireMux_T_607, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_150, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_609 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_610 = or(out_wifireMux_out_150, _out_wifireMux_T_609) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_151 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_611 = and(_out_wifireMux_T_262, out_frontSel_87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_612 = and(_out_wifireMux_T_611, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_151, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_613 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_614 = or(out_wifireMux_out_151, _out_wifireMux_T_613) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_152 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_615 = and(_out_wifireMux_T_262, out_frontSel_88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_616 = and(_out_wifireMux_T_615, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_152, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_617 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_618 = or(out_wifireMux_out_152, _out_wifireMux_T_617) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_153 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_619 = and(_out_wifireMux_T_262, out_frontSel_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_620 = and(_out_wifireMux_T_619, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_153, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_621 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_622 = or(out_wifireMux_out_153, _out_wifireMux_T_621) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_154 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_623 = and(_out_wifireMux_T_262, out_frontSel_90) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_624 = and(_out_wifireMux_T_623, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_154, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_625 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_626 = or(out_wifireMux_out_154, _out_wifireMux_T_625) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_155 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_627 = and(_out_wifireMux_T_262, out_frontSel_91) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_628 = and(_out_wifireMux_T_627, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_155, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_629 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_630 = or(out_wifireMux_out_155, _out_wifireMux_T_629) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_156 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_631 = and(_out_wifireMux_T_262, out_frontSel_92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_632 = and(_out_wifireMux_T_631, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_156, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_633 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_634 = or(out_wifireMux_out_156, _out_wifireMux_T_633) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_157 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_635 = and(_out_wifireMux_T_262, out_frontSel_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_636 = and(_out_wifireMux_T_635, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_157, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_637 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_638 = or(out_wifireMux_out_157, _out_wifireMux_T_637) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_158 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_639 = and(_out_wifireMux_T_262, out_frontSel_94) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_640 = and(_out_wifireMux_T_639, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_158, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_641 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_642 = or(out_wifireMux_out_158, _out_wifireMux_T_641) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_159 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_643 = and(_out_wifireMux_T_262, out_frontSel_95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_644 = and(_out_wifireMux_T_643, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_159, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_645 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_646 = or(out_wifireMux_out_159, _out_wifireMux_T_645) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_160 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_647 = and(_out_wifireMux_T_262, out_frontSel_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_648 = and(_out_wifireMux_T_647, _out_T_1434) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_160, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[434], _out_wifireMux_T_648 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_649 = eq(_out_T_1434, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_650 = or(out_wifireMux_out_160, _out_wifireMux_T_649) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_161 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_651 = and(_out_wifireMux_T_262, out_frontSel_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_652 = and(_out_wifireMux_T_651, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_161, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_653 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_654 = or(out_wifireMux_out_161, _out_wifireMux_T_653) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_162 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_655 = and(_out_wifireMux_T_262, out_frontSel_98) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_656 = and(_out_wifireMux_T_655, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_162, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_657 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_658 = or(out_wifireMux_out_162, _out_wifireMux_T_657) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_163 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_659 = and(_out_wifireMux_T_262, out_frontSel_99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_660 = and(_out_wifireMux_T_659, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_163, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_661 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_662 = or(out_wifireMux_out_163, _out_wifireMux_T_661) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_164 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_663 = and(_out_wifireMux_T_262, out_frontSel_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_664 = and(_out_wifireMux_T_663, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_164, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_665 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_666 = or(out_wifireMux_out_164, _out_wifireMux_T_665) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_165 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_667 = and(_out_wifireMux_T_262, out_frontSel_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_668 = and(_out_wifireMux_T_667, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_165, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_669 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_670 = or(out_wifireMux_out_165, _out_wifireMux_T_669) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_166 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_671 = and(_out_wifireMux_T_262, out_frontSel_102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_672 = and(_out_wifireMux_T_671, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_166, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_673 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_674 = or(out_wifireMux_out_166, _out_wifireMux_T_673) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_167 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_675 = and(_out_wifireMux_T_262, out_frontSel_103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_676 = and(_out_wifireMux_T_675, _out_T_1500) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_167, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[682], _out_wifireMux_T_676 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[681], _out_wifireMux_T_676 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_677 = eq(_out_T_1500, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_678 = or(out_wifireMux_out_167, _out_wifireMux_T_677) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_168 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_679 = and(_out_wifireMux_T_262, out_frontSel_104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_680 = and(_out_wifireMux_T_679, _out_T_1560) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_168, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[922], _out_wifireMux_T_680 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[921], _out_wifireMux_T_680 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[920], _out_wifireMux_T_680 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[919], _out_wifireMux_T_680 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[918], _out_wifireMux_T_680 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[917], _out_wifireMux_T_680 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[916], _out_wifireMux_T_680 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[915], _out_wifireMux_T_680 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_681 = eq(_out_T_1560, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_682 = or(out_wifireMux_out_168, _out_wifireMux_T_681) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_169 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_683 = and(_out_wifireMux_T_262, out_frontSel_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_684 = and(_out_wifireMux_T_683, _out_T_1454) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_169, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[510], _out_wifireMux_T_684 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[509], _out_wifireMux_T_684 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[508], _out_wifireMux_T_684 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[507], _out_wifireMux_T_684 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[506], _out_wifireMux_T_684 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[505], _out_wifireMux_T_684 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[504], _out_wifireMux_T_684 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[503], _out_wifireMux_T_684 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_685 = eq(_out_T_1454, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_686 = or(out_wifireMux_out_169, _out_wifireMux_T_685) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_170 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_687 = and(_out_wifireMux_T_262, out_frontSel_106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_688 = and(_out_wifireMux_T_687, _out_T_1370) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_170, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[191], _out_wifireMux_T_688 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[190], _out_wifireMux_T_688 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[189], _out_wifireMux_T_688 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[188], _out_wifireMux_T_688 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[187], _out_wifireMux_T_688 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[186], _out_wifireMux_T_688 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[185], _out_wifireMux_T_688 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[184], _out_wifireMux_T_688 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_689 = eq(_out_T_1370, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_690 = or(out_wifireMux_out_170, _out_wifireMux_T_689) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_171 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_691 = and(_out_wifireMux_T_262, out_frontSel_107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_692 = and(_out_wifireMux_T_691, _out_T_1598) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_171, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1074], _out_wifireMux_T_692 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1073], _out_wifireMux_T_692 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1072], _out_wifireMux_T_692 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1071], _out_wifireMux_T_692 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1070], _out_wifireMux_T_692 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1069], _out_wifireMux_T_692 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1068], _out_wifireMux_T_692 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1067], _out_wifireMux_T_692 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_693 = eq(_out_T_1598, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_694 = or(out_wifireMux_out_171, _out_wifireMux_T_693) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_172 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_695 = and(_out_wifireMux_T_262, out_frontSel_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_696 = and(_out_wifireMux_T_695, _out_T_1510) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_172, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[722], _out_wifireMux_T_696 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[721], _out_wifireMux_T_696 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[720], _out_wifireMux_T_696 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[719], _out_wifireMux_T_696 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[718], _out_wifireMux_T_696 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[717], _out_wifireMux_T_696 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[716], _out_wifireMux_T_696 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[715], _out_wifireMux_T_696 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_697 = eq(_out_T_1510, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_698 = or(out_wifireMux_out_172, _out_wifireMux_T_697) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_173 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_699 = and(_out_wifireMux_T_262, out_frontSel_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_700 = and(_out_wifireMux_T_699, _out_T_1436) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_173, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[442], _out_wifireMux_T_700 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[441], _out_wifireMux_T_700 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[440], _out_wifireMux_T_700 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[439], _out_wifireMux_T_700 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[438], _out_wifireMux_T_700 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[437], _out_wifireMux_T_700 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[436], _out_wifireMux_T_700 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[435], _out_wifireMux_T_700 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_701 = eq(_out_T_1436, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_702 = or(out_wifireMux_out_173, _out_wifireMux_T_701) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_174 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_703 = and(_out_wifireMux_T_262, out_frontSel_110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_704 = and(_out_wifireMux_T_703, _out_T_1350) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_174, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[111], _out_wifireMux_T_704 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[110], _out_wifireMux_T_704 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[109], _out_wifireMux_T_704 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[108], _out_wifireMux_T_704 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[107], _out_wifireMux_T_704 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[106], _out_wifireMux_T_704 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[105], _out_wifireMux_T_704 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[104], _out_wifireMux_T_704 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_705 = eq(_out_T_1350, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_706 = or(out_wifireMux_out_174, _out_wifireMux_T_705) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_175 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_707 = and(_out_wifireMux_T_262, out_frontSel_111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_708 = and(_out_wifireMux_T_707, _out_T_1616) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_175, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1146], _out_wifireMux_T_708 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1145], _out_wifireMux_T_708 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1144], _out_wifireMux_T_708 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1143], _out_wifireMux_T_708 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1142], _out_wifireMux_T_708 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1141], _out_wifireMux_T_708 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1140], _out_wifireMux_T_708 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1139], _out_wifireMux_T_708 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_709 = eq(_out_T_1616, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_710 = or(out_wifireMux_out_175, _out_wifireMux_T_709) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_176 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_711 = and(_out_wifireMux_T_262, out_frontSel_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_712 = and(_out_wifireMux_T_711, _out_T_1534) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_176, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[818], _out_wifireMux_T_712 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[817], _out_wifireMux_T_712 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[816], _out_wifireMux_T_712 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[815], _out_wifireMux_T_712 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[814], _out_wifireMux_T_712 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[813], _out_wifireMux_T_712 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[812], _out_wifireMux_T_712 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[811], _out_wifireMux_T_712 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_713 = eq(_out_T_1534, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_714 = or(out_wifireMux_out_176, _out_wifireMux_T_713) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_177 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_715 = and(_out_wifireMux_T_262, out_frontSel_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_716 = and(_out_wifireMux_T_715, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_177, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_717 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_718 = or(out_wifireMux_out_177, _out_wifireMux_T_717) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_178 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_719 = and(_out_wifireMux_T_262, out_frontSel_114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_720 = and(_out_wifireMux_T_719, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_178, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_721 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_722 = or(out_wifireMux_out_178, _out_wifireMux_T_721) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_179 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_723 = and(_out_wifireMux_T_262, out_frontSel_115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_724 = and(_out_wifireMux_T_723, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_179, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_725 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_726 = or(out_wifireMux_out_179, _out_wifireMux_T_725) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_180 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_727 = and(_out_wifireMux_T_262, out_frontSel_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_728 = and(_out_wifireMux_T_727, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_180, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_729 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_730 = or(out_wifireMux_out_180, _out_wifireMux_T_729) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_181 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_731 = and(_out_wifireMux_T_262, out_frontSel_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_732 = and(_out_wifireMux_T_731, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_181, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_733 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_734 = or(out_wifireMux_out_181, _out_wifireMux_T_733) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_182 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_735 = and(_out_wifireMux_T_262, out_frontSel_118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_736 = and(_out_wifireMux_T_735, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_182, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_737 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_738 = or(out_wifireMux_out_182, _out_wifireMux_T_737) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_183 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_739 = and(_out_wifireMux_T_262, out_frontSel_119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_740 = and(_out_wifireMux_T_739, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_183, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_741 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_742 = or(out_wifireMux_out_183, _out_wifireMux_T_741) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_184 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_743 = and(_out_wifireMux_T_262, out_frontSel_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_744 = and(_out_wifireMux_T_743, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_184, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_745 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_746 = or(out_wifireMux_out_184, _out_wifireMux_T_745) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_185 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_747 = and(_out_wifireMux_T_262, out_frontSel_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_748 = and(_out_wifireMux_T_747, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_185, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_749 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_750 = or(out_wifireMux_out_185, _out_wifireMux_T_749) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_186 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_751 = and(_out_wifireMux_T_262, out_frontSel_122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_752 = and(_out_wifireMux_T_751, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_186, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_753 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_754 = or(out_wifireMux_out_186, _out_wifireMux_T_753) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_187 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_755 = and(_out_wifireMux_T_262, out_frontSel_123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_756 = and(_out_wifireMux_T_755, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_187, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_757 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_758 = or(out_wifireMux_out_187, _out_wifireMux_T_757) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_188 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_759 = and(_out_wifireMux_T_262, out_frontSel_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_760 = and(_out_wifireMux_T_759, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_188, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_761 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_762 = or(out_wifireMux_out_188, _out_wifireMux_T_761) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_189 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_763 = and(_out_wifireMux_T_262, out_frontSel_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_764 = and(_out_wifireMux_T_763, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_189, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_765 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_766 = or(out_wifireMux_out_189, _out_wifireMux_T_765) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_190 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_767 = and(_out_wifireMux_T_262, out_frontSel_126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_768 = and(_out_wifireMux_T_767, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_190, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_769 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_770 = or(out_wifireMux_out_190, _out_wifireMux_T_769) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_191 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_771 = and(_out_wifireMux_T_262, out_frontSel_127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_772 = and(_out_wifireMux_T_771, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_191, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_773 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_774 = or(out_wifireMux_out_191, _out_wifireMux_T_773) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_192 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_775 = and(_out_wifireMux_T_262, out_frontSel_128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_776 = and(_out_wifireMux_T_775, _out_T_1450) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_192, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[494], _out_wifireMux_T_776 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[493], _out_wifireMux_T_776 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[492], _out_wifireMux_T_776 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[491], _out_wifireMux_T_776 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[490], _out_wifireMux_T_776 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[489], _out_wifireMux_T_776 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[488], _out_wifireMux_T_776 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[487], _out_wifireMux_T_776 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_777 = eq(_out_T_1450, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_778 = or(out_wifireMux_out_192, _out_wifireMux_T_777) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_193 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_779 = and(_out_wifireMux_T_262, out_frontSel_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_780 = and(_out_wifireMux_T_779, _out_T_1442) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_193, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[466], _out_wifireMux_T_780 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[465], _out_wifireMux_T_780 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[464], _out_wifireMux_T_780 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[463], _out_wifireMux_T_780 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[462], _out_wifireMux_T_780 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[461], _out_wifireMux_T_780 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[460], _out_wifireMux_T_780 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[459], _out_wifireMux_T_780 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_781 = eq(_out_T_1442, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_782 = or(out_wifireMux_out_193, _out_wifireMux_T_781) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_194 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_783 = and(_out_wifireMux_T_262, out_frontSel_130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_784 = and(_out_wifireMux_T_783, _out_T_1516) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_194, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[746], _out_wifireMux_T_784 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[745], _out_wifireMux_T_784 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[744], _out_wifireMux_T_784 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[743], _out_wifireMux_T_784 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[742], _out_wifireMux_T_784 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[741], _out_wifireMux_T_784 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[740], _out_wifireMux_T_784 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[739], _out_wifireMux_T_784 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_785 = eq(_out_T_1516, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_786 = or(out_wifireMux_out_194, _out_wifireMux_T_785) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_195 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_787 = and(_out_wifireMux_T_262, out_frontSel_131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_788 = and(_out_wifireMux_T_787, _out_T_1608) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_195, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1114], _out_wifireMux_T_788 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1113], _out_wifireMux_T_788 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1112], _out_wifireMux_T_788 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1111], _out_wifireMux_T_788 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1110], _out_wifireMux_T_788 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1109], _out_wifireMux_T_788 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1108], _out_wifireMux_T_788 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1107], _out_wifireMux_T_788 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_789 = eq(_out_T_1608, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_790 = or(out_wifireMux_out_195, _out_wifireMux_T_789) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_196 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_791 = and(_out_wifireMux_T_262, out_frontSel_132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_792 = and(_out_wifireMux_T_791, _out_T_1382) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_196, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[239], _out_wifireMux_T_792 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[238], _out_wifireMux_T_792 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[237], _out_wifireMux_T_792 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[236], _out_wifireMux_T_792 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[235], _out_wifireMux_T_792 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[234], _out_wifireMux_T_792 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[233], _out_wifireMux_T_792 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[232], _out_wifireMux_T_792 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_793 = eq(_out_T_1382, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_794 = or(out_wifireMux_out_196, _out_wifireMux_T_793) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_197 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_795 = and(_out_wifireMux_T_262, out_frontSel_133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_796 = and(_out_wifireMux_T_795, _out_T_1384) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_197, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[247], _out_wifireMux_T_796 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[246], _out_wifireMux_T_796 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[245], _out_wifireMux_T_796 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[244], _out_wifireMux_T_796 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[243], _out_wifireMux_T_796 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[242], _out_wifireMux_T_796 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[241], _out_wifireMux_T_796 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[240], _out_wifireMux_T_796 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_797 = eq(_out_T_1384, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_798 = or(out_wifireMux_out_197, _out_wifireMux_T_797) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_198 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_799 = and(_out_wifireMux_T_262, out_frontSel_134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_800 = and(_out_wifireMux_T_799, _out_T_1444) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_198, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[474], _out_wifireMux_T_800 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[473], _out_wifireMux_T_800 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[472], _out_wifireMux_T_800 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[471], _out_wifireMux_T_800 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[470], _out_wifireMux_T_800 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[469], _out_wifireMux_T_800 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[468], _out_wifireMux_T_800 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[467], _out_wifireMux_T_800 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_801 = eq(_out_T_1444, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_802 = or(out_wifireMux_out_198, _out_wifireMux_T_801) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_199 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_803 = and(_out_wifireMux_T_262, out_frontSel_135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_804 = and(_out_wifireMux_T_803, _out_T_1520) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_199, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[762], _out_wifireMux_T_804 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[761], _out_wifireMux_T_804 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[760], _out_wifireMux_T_804 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[759], _out_wifireMux_T_804 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[758], _out_wifireMux_T_804 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[757], _out_wifireMux_T_804 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[756], _out_wifireMux_T_804 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[755], _out_wifireMux_T_804 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_805 = eq(_out_T_1520, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_806 = or(out_wifireMux_out_199, _out_wifireMux_T_805) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_200 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_807 = and(_out_wifireMux_T_262, out_frontSel_136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_808 = and(_out_wifireMux_T_807, _out_T_1600) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_200, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1082], _out_wifireMux_T_808 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1081], _out_wifireMux_T_808 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1080], _out_wifireMux_T_808 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1079], _out_wifireMux_T_808 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1078], _out_wifireMux_T_808 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1077], _out_wifireMux_T_808 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1076], _out_wifireMux_T_808 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1075], _out_wifireMux_T_808 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_809 = eq(_out_T_1600, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_810 = or(out_wifireMux_out_200, _out_wifireMux_T_809) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_201 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_811 = and(_out_wifireMux_T_262, out_frontSel_137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_812 = and(_out_wifireMux_T_811, _out_T_1406) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_201, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[335], _out_wifireMux_T_812 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[334], _out_wifireMux_T_812 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[333], _out_wifireMux_T_812 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[332], _out_wifireMux_T_812 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[331], _out_wifireMux_T_812 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[330], _out_wifireMux_T_812 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[329], _out_wifireMux_T_812 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[328], _out_wifireMux_T_812 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_813 = eq(_out_T_1406, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_814 = or(out_wifireMux_out_201, _out_wifireMux_T_813) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_202 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_815 = and(_out_wifireMux_T_262, out_frontSel_138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_816 = and(_out_wifireMux_T_815, _out_T_1324) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_202, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[7], _out_wifireMux_T_816 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[6], _out_wifireMux_T_816 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[5], _out_wifireMux_T_816 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[4], _out_wifireMux_T_816 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[3], _out_wifireMux_T_816 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[2], _out_wifireMux_T_816 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1], _out_wifireMux_T_816 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[0], _out_wifireMux_T_816 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_817 = eq(_out_T_1324, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_818 = or(out_wifireMux_out_202, _out_wifireMux_T_817) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_203 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_819 = and(_out_wifireMux_T_262, out_frontSel_139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_820 = and(_out_wifireMux_T_819, _out_T_1574) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_203, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[978], _out_wifireMux_T_820 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[977], _out_wifireMux_T_820 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[976], _out_wifireMux_T_820 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[975], _out_wifireMux_T_820 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[974], _out_wifireMux_T_820 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[973], _out_wifireMux_T_820 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[972], _out_wifireMux_T_820 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[971], _out_wifireMux_T_820 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_821 = eq(_out_T_1574, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_822 = or(out_wifireMux_out_203, _out_wifireMux_T_821) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_204 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_823 = and(_out_wifireMux_T_262, out_frontSel_140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_824 = and(_out_wifireMux_T_823, _out_T_1502) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_204, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[690], _out_wifireMux_T_824 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[689], _out_wifireMux_T_824 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[688], _out_wifireMux_T_824 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[687], _out_wifireMux_T_824 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[686], _out_wifireMux_T_824 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[685], _out_wifireMux_T_824 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[684], _out_wifireMux_T_824 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[683], _out_wifireMux_T_824 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_825 = eq(_out_T_1502, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_826 = or(out_wifireMux_out_204, _out_wifireMux_T_825) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_205 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_827 = and(_out_wifireMux_T_262, out_frontSel_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_828 = and(_out_wifireMux_T_827, _out_T_1426) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_205, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[409], _out_wifireMux_T_828 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[408], _out_wifireMux_T_828 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[407], _out_wifireMux_T_828 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[406], _out_wifireMux_T_828 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[405], _out_wifireMux_T_828 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[404], _out_wifireMux_T_828 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[403], _out_wifireMux_T_828 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[402], _out_wifireMux_T_828 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_829 = eq(_out_T_1426, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_830 = or(out_wifireMux_out_205, _out_wifireMux_T_829) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_206 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_831 = and(_out_wifireMux_T_262, out_frontSel_142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_832 = and(_out_wifireMux_T_831, _out_T_1338) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_206, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[63], _out_wifireMux_T_832 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[62], _out_wifireMux_T_832 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[61], _out_wifireMux_T_832 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[60], _out_wifireMux_T_832 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[59], _out_wifireMux_T_832 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[58], _out_wifireMux_T_832 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[57], _out_wifireMux_T_832 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[56], _out_wifireMux_T_832 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_833 = eq(_out_T_1338, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_834 = or(out_wifireMux_out_206, _out_wifireMux_T_833) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_207 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_835 = and(_out_wifireMux_T_262, out_frontSel_143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_836 = and(_out_wifireMux_T_835, _out_T_1554) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_207, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[898], _out_wifireMux_T_836 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[897], _out_wifireMux_T_836 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[896], _out_wifireMux_T_836 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[895], _out_wifireMux_T_836 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[894], _out_wifireMux_T_836 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[893], _out_wifireMux_T_836 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[892], _out_wifireMux_T_836 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[891], _out_wifireMux_T_836 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_837 = eq(_out_T_1554, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_838 = or(out_wifireMux_out_207, _out_wifireMux_T_837) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_208 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_839 = and(_out_wifireMux_T_262, out_frontSel_144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_840 = and(_out_wifireMux_T_839, _out_T_1480) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_208, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[608], _out_wifireMux_T_840 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[607], _out_wifireMux_T_840 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[606], _out_wifireMux_T_840 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[605], _out_wifireMux_T_840 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[604], _out_wifireMux_T_840 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[603], _out_wifireMux_T_840 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[602], _out_wifireMux_T_840 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[601], _out_wifireMux_T_840 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_841 = eq(_out_T_1480, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_842 = or(out_wifireMux_out_208, _out_wifireMux_T_841) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_209 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_843 = and(_out_wifireMux_T_262, out_frontSel_145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_844 = and(_out_wifireMux_T_843, _out_T_1538) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_209, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[834], _out_wifireMux_T_844 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[833], _out_wifireMux_T_844 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[832], _out_wifireMux_T_844 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[831], _out_wifireMux_T_844 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[830], _out_wifireMux_T_844 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[829], _out_wifireMux_T_844 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[828], _out_wifireMux_T_844 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[827], _out_wifireMux_T_844 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_845 = eq(_out_T_1538, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_846 = or(out_wifireMux_out_209, _out_wifireMux_T_845) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_210 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_847 = and(_out_wifireMux_T_262, out_frontSel_146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_848 = and(_out_wifireMux_T_847, _out_T_1586) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_210, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1026], _out_wifireMux_T_848 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1025], _out_wifireMux_T_848 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1024], _out_wifireMux_T_848 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1023], _out_wifireMux_T_848 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1022], _out_wifireMux_T_848 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1021], _out_wifireMux_T_848 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1020], _out_wifireMux_T_848 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1019], _out_wifireMux_T_848 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_849 = eq(_out_T_1586, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_850 = or(out_wifireMux_out_210, _out_wifireMux_T_849) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_211 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_851 = and(_out_wifireMux_T_262, out_frontSel_147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_852 = and(_out_wifireMux_T_851, _out_T_1378) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_211, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[223], _out_wifireMux_T_852 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[222], _out_wifireMux_T_852 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[221], _out_wifireMux_T_852 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[220], _out_wifireMux_T_852 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[219], _out_wifireMux_T_852 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[218], _out_wifireMux_T_852 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[217], _out_wifireMux_T_852 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[216], _out_wifireMux_T_852 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_853 = eq(_out_T_1378, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_854 = or(out_wifireMux_out_211, _out_wifireMux_T_853) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_212 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_855 = and(_out_wifireMux_T_262, out_frontSel_148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_856 = and(_out_wifireMux_T_855, _out_T_1462) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_212, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[536], _out_wifireMux_T_856 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[535], _out_wifireMux_T_856 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[534], _out_wifireMux_T_856 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[533], _out_wifireMux_T_856 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[532], _out_wifireMux_T_856 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[531], _out_wifireMux_T_856 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[530], _out_wifireMux_T_856 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[529], _out_wifireMux_T_856 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_857 = eq(_out_T_1462, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_858 = or(out_wifireMux_out_212, _out_wifireMux_T_857) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_213 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_859 = and(_out_wifireMux_T_262, out_frontSel_149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_860 = and(_out_wifireMux_T_859, _out_T_1470) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_213, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[568], _out_wifireMux_T_860 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[567], _out_wifireMux_T_860 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[566], _out_wifireMux_T_860 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[565], _out_wifireMux_T_860 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[564], _out_wifireMux_T_860 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[563], _out_wifireMux_T_860 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[562], _out_wifireMux_T_860 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[561], _out_wifireMux_T_860 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_861 = eq(_out_T_1470, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_862 = or(out_wifireMux_out_213, _out_wifireMux_T_861) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_214 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_863 = and(_out_wifireMux_T_262, out_frontSel_150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_864 = and(_out_wifireMux_T_863, _out_T_1540) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_214, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[842], _out_wifireMux_T_864 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[841], _out_wifireMux_T_864 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[840], _out_wifireMux_T_864 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[839], _out_wifireMux_T_864 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[838], _out_wifireMux_T_864 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[837], _out_wifireMux_T_864 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[836], _out_wifireMux_T_864 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[835], _out_wifireMux_T_864 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_865 = eq(_out_T_1540, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_866 = or(out_wifireMux_out_214, _out_wifireMux_T_865) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_215 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_867 = and(_out_wifireMux_T_262, out_frontSel_151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_868 = and(_out_wifireMux_T_867, _out_T_1584) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_215, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1018], _out_wifireMux_T_868 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1017], _out_wifireMux_T_868 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1016], _out_wifireMux_T_868 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1015], _out_wifireMux_T_868 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1014], _out_wifireMux_T_868 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1013], _out_wifireMux_T_868 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1012], _out_wifireMux_T_868 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1011], _out_wifireMux_T_868 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_869 = eq(_out_T_1584, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_870 = or(out_wifireMux_out_215, _out_wifireMux_T_869) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_216 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_871 = and(_out_wifireMux_T_262, out_frontSel_152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_872 = and(_out_wifireMux_T_871, _out_T_1358) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_216, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[143], _out_wifireMux_T_872 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[142], _out_wifireMux_T_872 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[141], _out_wifireMux_T_872 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[140], _out_wifireMux_T_872 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[139], _out_wifireMux_T_872 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[138], _out_wifireMux_T_872 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[137], _out_wifireMux_T_872 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[136], _out_wifireMux_T_872 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_873 = eq(_out_T_1358, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_874 = or(out_wifireMux_out_216, _out_wifireMux_T_873) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_217 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_875 = and(_out_wifireMux_T_262, out_frontSel_153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_876 = and(_out_wifireMux_T_875, _out_T_1340) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_217, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[71], _out_wifireMux_T_876 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[70], _out_wifireMux_T_876 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[69], _out_wifireMux_T_876 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[68], _out_wifireMux_T_876 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[67], _out_wifireMux_T_876 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[66], _out_wifireMux_T_876 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[65], _out_wifireMux_T_876 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[64], _out_wifireMux_T_876 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_877 = eq(_out_T_1340, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_878 = or(out_wifireMux_out_217, _out_wifireMux_T_877) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_218 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_879 = and(_out_wifireMux_T_262, out_frontSel_154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_880 = and(_out_wifireMux_T_879, _out_T_1550) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_218, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[882], _out_wifireMux_T_880 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[881], _out_wifireMux_T_880 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[880], _out_wifireMux_T_880 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[879], _out_wifireMux_T_880 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[878], _out_wifireMux_T_880 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[877], _out_wifireMux_T_880 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[876], _out_wifireMux_T_880 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[875], _out_wifireMux_T_880 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_881 = eq(_out_T_1550, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_882 = or(out_wifireMux_out_218, _out_wifireMux_T_881) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_219 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_883 = and(_out_wifireMux_T_262, out_frontSel_155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_884 = and(_out_wifireMux_T_883, _out_T_1506) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_219, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[706], _out_wifireMux_T_884 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[705], _out_wifireMux_T_884 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[704], _out_wifireMux_T_884 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[703], _out_wifireMux_T_884 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[702], _out_wifireMux_T_884 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[701], _out_wifireMux_T_884 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[700], _out_wifireMux_T_884 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[699], _out_wifireMux_T_884 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_885 = eq(_out_T_1506, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_886 = or(out_wifireMux_out_219, _out_wifireMux_T_885) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_220 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_887 = and(_out_wifireMux_T_262, out_frontSel_156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_888 = and(_out_wifireMux_T_887, _out_T_1420) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_220, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[385], _out_wifireMux_T_888 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[384], _out_wifireMux_T_888 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[383], _out_wifireMux_T_888 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[382], _out_wifireMux_T_888 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[381], _out_wifireMux_T_888 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[380], _out_wifireMux_T_888 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[379], _out_wifireMux_T_888 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[378], _out_wifireMux_T_888 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_889 = eq(_out_T_1420, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_890 = or(out_wifireMux_out_220, _out_wifireMux_T_889) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_221 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_891 = and(_out_wifireMux_T_262, out_frontSel_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_892 = and(_out_wifireMux_T_891, _out_T_1354) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_221, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[127], _out_wifireMux_T_892 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[126], _out_wifireMux_T_892 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[125], _out_wifireMux_T_892 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[124], _out_wifireMux_T_892 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[123], _out_wifireMux_T_892 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[122], _out_wifireMux_T_892 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[121], _out_wifireMux_T_892 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[120], _out_wifireMux_T_892 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_893 = eq(_out_T_1354, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_894 = or(out_wifireMux_out_221, _out_wifireMux_T_893) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_222 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_895 = and(_out_wifireMux_T_262, out_frontSel_158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_896 = and(_out_wifireMux_T_895, _out_T_1568) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_222, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[954], _out_wifireMux_T_896 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[953], _out_wifireMux_T_896 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[952], _out_wifireMux_T_896 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[951], _out_wifireMux_T_896 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[950], _out_wifireMux_T_896 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[949], _out_wifireMux_T_896 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[948], _out_wifireMux_T_896 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[947], _out_wifireMux_T_896 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_897 = eq(_out_T_1568, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_898 = or(out_wifireMux_out_222, _out_wifireMux_T_897) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_223 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_899 = and(_out_wifireMux_T_262, out_frontSel_159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_900 = and(_out_wifireMux_T_899, _out_T_1486) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_223, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[632], _out_wifireMux_T_900 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[631], _out_wifireMux_T_900 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[630], _out_wifireMux_T_900 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[629], _out_wifireMux_T_900 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[628], _out_wifireMux_T_900 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[627], _out_wifireMux_T_900 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[626], _out_wifireMux_T_900 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[625], _out_wifireMux_T_900 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_901 = eq(_out_T_1486, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_902 = or(out_wifireMux_out_223, _out_wifireMux_T_901) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_224 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_903 = and(_out_wifireMux_T_262, out_frontSel_160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_904 = and(_out_wifireMux_T_903, _out_T_1402) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_224, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[319], _out_wifireMux_T_904 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[318], _out_wifireMux_T_904 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[317], _out_wifireMux_T_904 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[316], _out_wifireMux_T_904 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[315], _out_wifireMux_T_904 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[314], _out_wifireMux_T_904 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[313], _out_wifireMux_T_904 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[312], _out_wifireMux_T_904 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_905 = eq(_out_T_1402, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_906 = or(out_wifireMux_out_224, _out_wifireMux_T_905) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_225 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_907 = and(_out_wifireMux_T_262, out_frontSel_161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_908 = and(_out_wifireMux_T_907, _out_T_1466) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_225, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[552], _out_wifireMux_T_908 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[551], _out_wifireMux_T_908 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[550], _out_wifireMux_T_908 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[549], _out_wifireMux_T_908 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[548], _out_wifireMux_T_908 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[547], _out_wifireMux_T_908 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[546], _out_wifireMux_T_908 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[545], _out_wifireMux_T_908 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_909 = eq(_out_T_1466, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_910 = or(out_wifireMux_out_225, _out_wifireMux_T_909) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_226 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_911 = and(_out_wifireMux_T_262, out_frontSel_162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_912 = and(_out_wifireMux_T_911, _out_T_1528) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_226, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[794], _out_wifireMux_T_912 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[793], _out_wifireMux_T_912 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[792], _out_wifireMux_T_912 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[791], _out_wifireMux_T_912 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[790], _out_wifireMux_T_912 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[789], _out_wifireMux_T_912 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[788], _out_wifireMux_T_912 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[787], _out_wifireMux_T_912 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_913 = eq(_out_T_1528, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_914 = or(out_wifireMux_out_226, _out_wifireMux_T_913) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_227 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_915 = and(_out_wifireMux_T_262, out_frontSel_163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_916 = and(_out_wifireMux_T_915, _out_T_1612) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_227, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1130], _out_wifireMux_T_916 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1129], _out_wifireMux_T_916 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1128], _out_wifireMux_T_916 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1127], _out_wifireMux_T_916 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1126], _out_wifireMux_T_916 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1125], _out_wifireMux_T_916 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1124], _out_wifireMux_T_916 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1123], _out_wifireMux_T_916 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_917 = eq(_out_T_1612, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_918 = or(out_wifireMux_out_227, _out_wifireMux_T_917) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_228 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_919 = and(_out_wifireMux_T_262, out_frontSel_164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_920 = and(_out_wifireMux_T_919, _out_T_1366) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_228, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[175], _out_wifireMux_T_920 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[174], _out_wifireMux_T_920 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[173], _out_wifireMux_T_920 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[172], _out_wifireMux_T_920 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[171], _out_wifireMux_T_920 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[170], _out_wifireMux_T_920 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[169], _out_wifireMux_T_920 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[168], _out_wifireMux_T_920 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_921 = eq(_out_T_1366, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_922 = or(out_wifireMux_out_228, _out_wifireMux_T_921) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_229 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_923 = and(_out_wifireMux_T_262, out_frontSel_165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_924 = and(_out_wifireMux_T_923, _out_T_1408) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_229, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[343], _out_wifireMux_T_924 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[342], _out_wifireMux_T_924 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[341], _out_wifireMux_T_924 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[340], _out_wifireMux_T_924 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[339], _out_wifireMux_T_924 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[338], _out_wifireMux_T_924 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[337], _out_wifireMux_T_924 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[336], _out_wifireMux_T_924 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_925 = eq(_out_T_1408, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_926 = or(out_wifireMux_out_229, _out_wifireMux_T_925) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_230 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_927 = and(_out_wifireMux_T_262, out_frontSel_166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_928 = and(_out_wifireMux_T_927, _out_T_1458) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_230, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[526], _out_wifireMux_T_928 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[525], _out_wifireMux_T_928 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[524], _out_wifireMux_T_928 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[523], _out_wifireMux_T_928 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[522], _out_wifireMux_T_928 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[521], _out_wifireMux_T_928 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[520], _out_wifireMux_T_928 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[519], _out_wifireMux_T_928 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_929 = eq(_out_T_1458, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_930 = or(out_wifireMux_out_230, _out_wifireMux_T_929) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_231 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_931 = and(_out_wifireMux_T_262, out_frontSel_167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_932 = and(_out_wifireMux_T_931, _out_T_1526) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_231, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[786], _out_wifireMux_T_932 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[785], _out_wifireMux_T_932 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[784], _out_wifireMux_T_932 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[783], _out_wifireMux_T_932 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[782], _out_wifireMux_T_932 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[781], _out_wifireMux_T_932 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[780], _out_wifireMux_T_932 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[779], _out_wifireMux_T_932 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_933 = eq(_out_T_1526, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_934 = or(out_wifireMux_out_231, _out_wifireMux_T_933) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_232 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_935 = and(_out_wifireMux_T_262, out_frontSel_168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_936 = and(_out_wifireMux_T_935, _out_T_1592) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_232, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1050], _out_wifireMux_T_936 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1049], _out_wifireMux_T_936 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1048], _out_wifireMux_T_936 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1047], _out_wifireMux_T_936 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1046], _out_wifireMux_T_936 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1045], _out_wifireMux_T_936 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1044], _out_wifireMux_T_936 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1043], _out_wifireMux_T_936 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_937 = eq(_out_T_1592, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_938 = or(out_wifireMux_out_232, _out_wifireMux_T_937) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_233 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_939 = and(_out_wifireMux_T_262, out_frontSel_169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_940 = and(_out_wifireMux_T_939, _out_T_1424) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_233, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[401], _out_wifireMux_T_940 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[400], _out_wifireMux_T_940 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[399], _out_wifireMux_T_940 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[398], _out_wifireMux_T_940 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[397], _out_wifireMux_T_940 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[396], _out_wifireMux_T_940 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[395], _out_wifireMux_T_940 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[394], _out_wifireMux_T_940 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_941 = eq(_out_T_1424, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_942 = or(out_wifireMux_out_233, _out_wifireMux_T_941) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_234 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_943 = and(_out_wifireMux_T_262, out_frontSel_170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_944 = and(_out_wifireMux_T_943, _out_T_1330) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_234, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[31], _out_wifireMux_T_944 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[30], _out_wifireMux_T_944 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[29], _out_wifireMux_T_944 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[28], _out_wifireMux_T_944 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[27], _out_wifireMux_T_944 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[26], _out_wifireMux_T_944 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[25], _out_wifireMux_T_944 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[24], _out_wifireMux_T_944 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_945 = eq(_out_T_1330, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_946 = or(out_wifireMux_out_234, _out_wifireMux_T_945) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_235 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_947 = and(_out_wifireMux_T_262, out_frontSel_171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_948 = and(_out_wifireMux_T_947, _out_T_1572) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_235, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[970], _out_wifireMux_T_948 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[969], _out_wifireMux_T_948 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[968], _out_wifireMux_T_948 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[967], _out_wifireMux_T_948 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[966], _out_wifireMux_T_948 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[965], _out_wifireMux_T_948 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[964], _out_wifireMux_T_948 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[963], _out_wifireMux_T_948 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_949 = eq(_out_T_1572, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_950 = or(out_wifireMux_out_235, _out_wifireMux_T_949) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_236 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_951 = and(_out_wifireMux_T_262, out_frontSel_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_952 = and(_out_wifireMux_T_951, _out_T_1490) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_236, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[648], _out_wifireMux_T_952 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[647], _out_wifireMux_T_952 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[646], _out_wifireMux_T_952 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[645], _out_wifireMux_T_952 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[644], _out_wifireMux_T_952 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[643], _out_wifireMux_T_952 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[642], _out_wifireMux_T_952 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[641], _out_wifireMux_T_952 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_953 = eq(_out_T_1490, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_954 = or(out_wifireMux_out_236, _out_wifireMux_T_953) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_237 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_955 = and(_out_wifireMux_T_262, out_frontSel_173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_956 = and(_out_wifireMux_T_955, _out_T_1440) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_237, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[458], _out_wifireMux_T_956 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[457], _out_wifireMux_T_956 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[456], _out_wifireMux_T_956 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[455], _out_wifireMux_T_956 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[454], _out_wifireMux_T_956 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[453], _out_wifireMux_T_956 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[452], _out_wifireMux_T_956 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[451], _out_wifireMux_T_956 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_957 = eq(_out_T_1440, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_958 = or(out_wifireMux_out_237, _out_wifireMux_T_957) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_238 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_959 = and(_out_wifireMux_T_262, out_frontSel_174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_960 = and(_out_wifireMux_T_959, _out_T_1342) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_238, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[79], _out_wifireMux_T_960 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[78], _out_wifireMux_T_960 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[77], _out_wifireMux_T_960 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[76], _out_wifireMux_T_960 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[75], _out_wifireMux_T_960 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[74], _out_wifireMux_T_960 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[73], _out_wifireMux_T_960 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[72], _out_wifireMux_T_960 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_961 = eq(_out_T_1342, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_962 = or(out_wifireMux_out_238, _out_wifireMux_T_961) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_239 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_963 = and(_out_wifireMux_T_262, out_frontSel_175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_964 = and(_out_wifireMux_T_963, _out_T_1552) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_239, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[890], _out_wifireMux_T_964 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[889], _out_wifireMux_T_964 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[888], _out_wifireMux_T_964 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[887], _out_wifireMux_T_964 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[886], _out_wifireMux_T_964 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[885], _out_wifireMux_T_964 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[884], _out_wifireMux_T_964 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[883], _out_wifireMux_T_964 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_965 = eq(_out_T_1552, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_966 = or(out_wifireMux_out_239, _out_wifireMux_T_965) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_240 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_967 = and(_out_wifireMux_T_262, out_frontSel_176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_968 = and(_out_wifireMux_T_967, _out_T_1472) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_240, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[576], _out_wifireMux_T_968 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[575], _out_wifireMux_T_968 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[574], _out_wifireMux_T_968 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[573], _out_wifireMux_T_968 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[572], _out_wifireMux_T_968 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[571], _out_wifireMux_T_968 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[570], _out_wifireMux_T_968 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[569], _out_wifireMux_T_968 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_969 = eq(_out_T_1472, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_970 = or(out_wifireMux_out_240, _out_wifireMux_T_969) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_241 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_971 = and(_out_wifireMux_T_262, out_frontSel_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_972 = and(_out_wifireMux_T_971, _out_T_1546) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_241, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[866], _out_wifireMux_T_972 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[865], _out_wifireMux_T_972 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[864], _out_wifireMux_T_972 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[863], _out_wifireMux_T_972 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[862], _out_wifireMux_T_972 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[861], _out_wifireMux_T_972 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[860], _out_wifireMux_T_972 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[859], _out_wifireMux_T_972 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_973 = eq(_out_T_1546, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_974 = or(out_wifireMux_out_241, _out_wifireMux_T_973) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_242 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_975 = and(_out_wifireMux_T_262, out_frontSel_178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_976 = and(_out_wifireMux_T_975, _out_T_1610) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_242, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1122], _out_wifireMux_T_976 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1121], _out_wifireMux_T_976 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1120], _out_wifireMux_T_976 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1119], _out_wifireMux_T_976 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1118], _out_wifireMux_T_976 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1117], _out_wifireMux_T_976 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1116], _out_wifireMux_T_976 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1115], _out_wifireMux_T_976 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_977 = eq(_out_T_1610, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_978 = or(out_wifireMux_out_242, _out_wifireMux_T_977) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_243 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_979 = and(_out_wifireMux_T_262, out_frontSel_179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_980 = and(_out_wifireMux_T_979, _out_T_1368) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_243, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[183], _out_wifireMux_T_980 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[182], _out_wifireMux_T_980 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[181], _out_wifireMux_T_980 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[180], _out_wifireMux_T_980 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[179], _out_wifireMux_T_980 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[178], _out_wifireMux_T_980 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[177], _out_wifireMux_T_980 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[176], _out_wifireMux_T_980 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_981 = eq(_out_T_1368, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_982 = or(out_wifireMux_out_243, _out_wifireMux_T_981) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_244 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_983 = and(_out_wifireMux_T_262, out_frontSel_180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_984 = and(_out_wifireMux_T_983, _out_T_1468) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_244, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[560], _out_wifireMux_T_984 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[559], _out_wifireMux_T_984 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[558], _out_wifireMux_T_984 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[557], _out_wifireMux_T_984 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[556], _out_wifireMux_T_984 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[555], _out_wifireMux_T_984 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[554], _out_wifireMux_T_984 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[553], _out_wifireMux_T_984 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_985 = eq(_out_T_1468, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_986 = or(out_wifireMux_out_244, _out_wifireMux_T_985) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_245 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_987 = and(_out_wifireMux_T_262, out_frontSel_181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_988 = and(_out_wifireMux_T_987, _out_T_1484) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_245, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[624], _out_wifireMux_T_988 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[623], _out_wifireMux_T_988 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[622], _out_wifireMux_T_988 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[621], _out_wifireMux_T_988 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[620], _out_wifireMux_T_988 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[619], _out_wifireMux_T_988 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[618], _out_wifireMux_T_988 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[617], _out_wifireMux_T_988 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_989 = eq(_out_T_1484, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_990 = or(out_wifireMux_out_245, _out_wifireMux_T_989) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_246 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_991 = and(_out_wifireMux_T_262, out_frontSel_182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_992 = and(_out_wifireMux_T_991, _out_T_1548) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_246, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[874], _out_wifireMux_T_992 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[873], _out_wifireMux_T_992 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[872], _out_wifireMux_T_992 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[871], _out_wifireMux_T_992 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[870], _out_wifireMux_T_992 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[869], _out_wifireMux_T_992 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[868], _out_wifireMux_T_992 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[867], _out_wifireMux_T_992 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_993 = eq(_out_T_1548, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_994 = or(out_wifireMux_out_246, _out_wifireMux_T_993) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_247 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_995 = and(_out_wifireMux_T_262, out_frontSel_183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_996 = and(_out_wifireMux_T_995, _out_T_1590) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_247, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1042], _out_wifireMux_T_996 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1041], _out_wifireMux_T_996 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1040], _out_wifireMux_T_996 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1039], _out_wifireMux_T_996 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1038], _out_wifireMux_T_996 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1037], _out_wifireMux_T_996 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1036], _out_wifireMux_T_996 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1035], _out_wifireMux_T_996 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_997 = eq(_out_T_1590, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_998 = or(out_wifireMux_out_247, _out_wifireMux_T_997) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_248 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_999 = and(_out_wifireMux_T_262, out_frontSel_184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1000 = and(_out_wifireMux_T_999, _out_T_1348) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_248, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[103], _out_wifireMux_T_1000 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[102], _out_wifireMux_T_1000 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[101], _out_wifireMux_T_1000 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[100], _out_wifireMux_T_1000 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[99], _out_wifireMux_T_1000 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[98], _out_wifireMux_T_1000 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[97], _out_wifireMux_T_1000 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[96], _out_wifireMux_T_1000 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1001 = eq(_out_T_1348, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1002 = or(out_wifireMux_out_248, _out_wifireMux_T_1001) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_249 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1003 = and(_out_wifireMux_T_262, out_frontSel_185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1004 = and(_out_wifireMux_T_1003, _out_T_1344) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_249, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[87], _out_wifireMux_T_1004 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[86], _out_wifireMux_T_1004 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[85], _out_wifireMux_T_1004 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[84], _out_wifireMux_T_1004 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[83], _out_wifireMux_T_1004 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[82], _out_wifireMux_T_1004 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[81], _out_wifireMux_T_1004 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[80], _out_wifireMux_T_1004 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1005 = eq(_out_T_1344, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1006 = or(out_wifireMux_out_249, _out_wifireMux_T_1005) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_250 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1007 = and(_out_wifireMux_T_262, out_frontSel_186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1008 = and(_out_wifireMux_T_1007, _out_T_1570) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_250, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[962], _out_wifireMux_T_1008 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[961], _out_wifireMux_T_1008 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[960], _out_wifireMux_T_1008 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[959], _out_wifireMux_T_1008 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[958], _out_wifireMux_T_1008 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[957], _out_wifireMux_T_1008 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[956], _out_wifireMux_T_1008 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[955], _out_wifireMux_T_1008 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1009 = eq(_out_T_1570, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1010 = or(out_wifireMux_out_250, _out_wifireMux_T_1009) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_251 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1011 = and(_out_wifireMux_T_262, out_frontSel_187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1012 = and(_out_wifireMux_T_1011, _out_T_1488) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_251, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[640], _out_wifireMux_T_1012 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[639], _out_wifireMux_T_1012 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[638], _out_wifireMux_T_1012 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[637], _out_wifireMux_T_1012 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[636], _out_wifireMux_T_1012 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[635], _out_wifireMux_T_1012 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[634], _out_wifireMux_T_1012 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[633], _out_wifireMux_T_1012 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1013 = eq(_out_T_1488, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1014 = or(out_wifireMux_out_251, _out_wifireMux_T_1013) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_252 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1015 = and(_out_wifireMux_T_262, out_frontSel_188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1016 = and(_out_wifireMux_T_1015, _out_T_1422) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_252, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[393], _out_wifireMux_T_1016 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[392], _out_wifireMux_T_1016 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[391], _out_wifireMux_T_1016 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[390], _out_wifireMux_T_1016 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[389], _out_wifireMux_T_1016 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[388], _out_wifireMux_T_1016 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[387], _out_wifireMux_T_1016 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[386], _out_wifireMux_T_1016 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1017 = eq(_out_T_1422, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1018 = or(out_wifireMux_out_252, _out_wifireMux_T_1017) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_253 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1019 = and(_out_wifireMux_T_262, out_frontSel_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1020 = and(_out_wifireMux_T_1019, _out_T_1356) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_253, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[135], _out_wifireMux_T_1020 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[134], _out_wifireMux_T_1020 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[133], _out_wifireMux_T_1020 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[132], _out_wifireMux_T_1020 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[131], _out_wifireMux_T_1020 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[130], _out_wifireMux_T_1020 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[129], _out_wifireMux_T_1020 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[128], _out_wifireMux_T_1020 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1021 = eq(_out_T_1356, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1022 = or(out_wifireMux_out_253, _out_wifireMux_T_1021) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_254 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1023 = and(_out_wifireMux_T_262, out_frontSel_190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1024 = and(_out_wifireMux_T_1023, _out_T_1588) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_254, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1034], _out_wifireMux_T_1024 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1033], _out_wifireMux_T_1024 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1032], _out_wifireMux_T_1024 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1031], _out_wifireMux_T_1024 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1030], _out_wifireMux_T_1024 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1029], _out_wifireMux_T_1024 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1028], _out_wifireMux_T_1024 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1027], _out_wifireMux_T_1024 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1025 = eq(_out_T_1588, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1026 = or(out_wifireMux_out_254, _out_wifireMux_T_1025) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_255 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1027 = and(_out_wifireMux_T_262, out_frontSel_191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1028 = and(_out_wifireMux_T_1027, _out_T_1474) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_255, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[584], _out_wifireMux_T_1028 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[583], _out_wifireMux_T_1028 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[582], _out_wifireMux_T_1028 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[581], _out_wifireMux_T_1028 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[580], _out_wifireMux_T_1028 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[579], _out_wifireMux_T_1028 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[578], _out_wifireMux_T_1028 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[577], _out_wifireMux_T_1028 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1029 = eq(_out_T_1474, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1030 = or(out_wifireMux_out_255, _out_wifireMux_T_1029) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_256 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1031 = and(_out_wifireMux_T_262, out_frontSel_192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1032 = and(_out_wifireMux_T_1031, _out_T_1404) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_256, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[327], _out_wifireMux_T_1032 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[326], _out_wifireMux_T_1032 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[325], _out_wifireMux_T_1032 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[324], _out_wifireMux_T_1032 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[323], _out_wifireMux_T_1032 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[322], _out_wifireMux_T_1032 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[321], _out_wifireMux_T_1032 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[320], _out_wifireMux_T_1032 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1033 = eq(_out_T_1404, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1034 = or(out_wifireMux_out_256, _out_wifireMux_T_1033) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_257 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1035 = and(_out_wifireMux_T_262, out_frontSel_193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1036 = and(_out_wifireMux_T_1035, _out_T_1430) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_257, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[425], _out_wifireMux_T_1036 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[424], _out_wifireMux_T_1036 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[423], _out_wifireMux_T_1036 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[422], _out_wifireMux_T_1036 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[421], _out_wifireMux_T_1036 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[420], _out_wifireMux_T_1036 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[419], _out_wifireMux_T_1036 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[418], _out_wifireMux_T_1036 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1037 = eq(_out_T_1430, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1038 = or(out_wifireMux_out_257, _out_wifireMux_T_1037) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_258 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1039 = and(_out_wifireMux_T_262, out_frontSel_194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1040 = and(_out_wifireMux_T_1039, _out_T_1536) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_258, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[826], _out_wifireMux_T_1040 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[825], _out_wifireMux_T_1040 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[824], _out_wifireMux_T_1040 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[823], _out_wifireMux_T_1040 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[822], _out_wifireMux_T_1040 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[821], _out_wifireMux_T_1040 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[820], _out_wifireMux_T_1040 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[819], _out_wifireMux_T_1040 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1041 = eq(_out_T_1536, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1042 = or(out_wifireMux_out_258, _out_wifireMux_T_1041) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_259 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1043 = and(_out_wifireMux_T_262, out_frontSel_195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1044 = and(_out_wifireMux_T_1043, _out_T_1602) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_259, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1090], _out_wifireMux_T_1044 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1089], _out_wifireMux_T_1044 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1088], _out_wifireMux_T_1044 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1087], _out_wifireMux_T_1044 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1086], _out_wifireMux_T_1044 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1085], _out_wifireMux_T_1044 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1084], _out_wifireMux_T_1044 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1083], _out_wifireMux_T_1044 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1045 = eq(_out_T_1602, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1046 = or(out_wifireMux_out_259, _out_wifireMux_T_1045) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_260 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1047 = and(_out_wifireMux_T_262, out_frontSel_196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1048 = and(_out_wifireMux_T_1047, _out_T_1352) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_260, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[119], _out_wifireMux_T_1048 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[118], _out_wifireMux_T_1048 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[117], _out_wifireMux_T_1048 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[116], _out_wifireMux_T_1048 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[115], _out_wifireMux_T_1048 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[114], _out_wifireMux_T_1048 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[113], _out_wifireMux_T_1048 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[112], _out_wifireMux_T_1048 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1049 = eq(_out_T_1352, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1050 = or(out_wifireMux_out_260, _out_wifireMux_T_1049) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_261 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1051 = and(_out_wifireMux_T_262, out_frontSel_197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1052 = and(_out_wifireMux_T_1051, _out_T_1416) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_261, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[369], _out_wifireMux_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[368], _out_wifireMux_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[367], _out_wifireMux_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[366], _out_wifireMux_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[365], _out_wifireMux_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[364], _out_wifireMux_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[363], _out_wifireMux_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[362], _out_wifireMux_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1053 = eq(_out_T_1416, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1054 = or(out_wifireMux_out_261, _out_wifireMux_T_1053) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_262 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1055 = and(_out_wifireMux_T_262, out_frontSel_198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1056 = and(_out_wifireMux_T_1055, _out_T_1508) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_262, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[714], _out_wifireMux_T_1056 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[713], _out_wifireMux_T_1056 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[712], _out_wifireMux_T_1056 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[711], _out_wifireMux_T_1056 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[710], _out_wifireMux_T_1056 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[709], _out_wifireMux_T_1056 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[708], _out_wifireMux_T_1056 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[707], _out_wifireMux_T_1056 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1057 = eq(_out_T_1508, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1058 = or(out_wifireMux_out_262, _out_wifireMux_T_1057) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_263 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1059 = and(_out_wifireMux_T_262, out_frontSel_199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1060 = and(_out_wifireMux_T_1059, _out_T_1544) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_263, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[858], _out_wifireMux_T_1060 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[857], _out_wifireMux_T_1060 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[856], _out_wifireMux_T_1060 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[855], _out_wifireMux_T_1060 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[854], _out_wifireMux_T_1060 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[853], _out_wifireMux_T_1060 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[852], _out_wifireMux_T_1060 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[851], _out_wifireMux_T_1060 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1061 = eq(_out_T_1544, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1062 = or(out_wifireMux_out_263, _out_wifireMux_T_1061) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_264 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1063 = and(_out_wifireMux_T_262, out_frontSel_200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1064 = and(_out_wifireMux_T_1063, _out_T_1614) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_264, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1138], _out_wifireMux_T_1064 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1137], _out_wifireMux_T_1064 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1136], _out_wifireMux_T_1064 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1135], _out_wifireMux_T_1064 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1134], _out_wifireMux_T_1064 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1133], _out_wifireMux_T_1064 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1132], _out_wifireMux_T_1064 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1131], _out_wifireMux_T_1064 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1065 = eq(_out_T_1614, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1066 = or(out_wifireMux_out_264, _out_wifireMux_T_1065) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_265 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1067 = and(_out_wifireMux_T_262, out_frontSel_201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1068 = and(_out_wifireMux_T_1067, _out_T_1396) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_265, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[295], _out_wifireMux_T_1068 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[294], _out_wifireMux_T_1068 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[293], _out_wifireMux_T_1068 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[292], _out_wifireMux_T_1068 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[291], _out_wifireMux_T_1068 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[290], _out_wifireMux_T_1068 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[289], _out_wifireMux_T_1068 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[288], _out_wifireMux_T_1068 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1069 = eq(_out_T_1396, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1070 = or(out_wifireMux_out_265, _out_wifireMux_T_1069) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_266 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1071 = and(_out_wifireMux_T_262, out_frontSel_202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1072 = and(_out_wifireMux_T_1071, _out_T_1336) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_266, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[55], _out_wifireMux_T_1072 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[54], _out_wifireMux_T_1072 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[53], _out_wifireMux_T_1072 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[52], _out_wifireMux_T_1072 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[51], _out_wifireMux_T_1072 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[50], _out_wifireMux_T_1072 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[49], _out_wifireMux_T_1072 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[48], _out_wifireMux_T_1072 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1073 = eq(_out_T_1336, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1074 = or(out_wifireMux_out_266, _out_wifireMux_T_1073) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_267 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1075 = and(_out_wifireMux_T_262, out_frontSel_203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1076 = and(_out_wifireMux_T_1075, _out_T_1556) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_267, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[906], _out_wifireMux_T_1076 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[905], _out_wifireMux_T_1076 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[904], _out_wifireMux_T_1076 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[903], _out_wifireMux_T_1076 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[902], _out_wifireMux_T_1076 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[901], _out_wifireMux_T_1076 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[900], _out_wifireMux_T_1076 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[899], _out_wifireMux_T_1076 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1077 = eq(_out_T_1556, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1078 = or(out_wifireMux_out_267, _out_wifireMux_T_1077) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_268 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1079 = and(_out_wifireMux_T_262, out_frontSel_204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1080 = and(_out_wifireMux_T_1079, _out_T_1476) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_268, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[592], _out_wifireMux_T_1080 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[591], _out_wifireMux_T_1080 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[590], _out_wifireMux_T_1080 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[589], _out_wifireMux_T_1080 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[588], _out_wifireMux_T_1080 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[587], _out_wifireMux_T_1080 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[586], _out_wifireMux_T_1080 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[585], _out_wifireMux_T_1080 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1081 = eq(_out_T_1476, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1082 = or(out_wifireMux_out_268, _out_wifireMux_T_1081) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_269 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1083 = and(_out_wifireMux_T_262, out_frontSel_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1084 = and(_out_wifireMux_T_1083, _out_T_1448) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_269, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[486], _out_wifireMux_T_1084 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[485], _out_wifireMux_T_1084 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[484], _out_wifireMux_T_1084 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[483], _out_wifireMux_T_1084 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[482], _out_wifireMux_T_1084 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[481], _out_wifireMux_T_1084 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[480], _out_wifireMux_T_1084 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[479], _out_wifireMux_T_1084 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1085 = eq(_out_T_1448, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1086 = or(out_wifireMux_out_269, _out_wifireMux_T_1085) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_270 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1087 = and(_out_wifireMux_T_262, out_frontSel_206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1088 = and(_out_wifireMux_T_1087, _out_T_1390) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_270, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[271], _out_wifireMux_T_1088 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[270], _out_wifireMux_T_1088 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[269], _out_wifireMux_T_1088 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[268], _out_wifireMux_T_1088 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[267], _out_wifireMux_T_1088 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[266], _out_wifireMux_T_1088 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[265], _out_wifireMux_T_1088 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[264], _out_wifireMux_T_1088 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1089 = eq(_out_T_1390, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1090 = or(out_wifireMux_out_270, _out_wifireMux_T_1089) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_271 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1091 = and(_out_wifireMux_T_262, out_frontSel_207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1092 = and(_out_wifireMux_T_1091, _out_T_1576) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_271, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[986], _out_wifireMux_T_1092 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[985], _out_wifireMux_T_1092 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[984], _out_wifireMux_T_1092 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[983], _out_wifireMux_T_1092 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[982], _out_wifireMux_T_1092 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[981], _out_wifireMux_T_1092 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[980], _out_wifireMux_T_1092 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[979], _out_wifireMux_T_1092 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1093 = eq(_out_T_1576, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1094 = or(out_wifireMux_out_271, _out_wifireMux_T_1093) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_272 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1095 = and(_out_wifireMux_T_262, out_frontSel_208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1096 = and(_out_wifireMux_T_1095, _out_T_1498) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_272, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[680], _out_wifireMux_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[679], _out_wifireMux_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[678], _out_wifireMux_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[677], _out_wifireMux_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[676], _out_wifireMux_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[675], _out_wifireMux_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[674], _out_wifireMux_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[673], _out_wifireMux_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1097 = eq(_out_T_1498, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1098 = or(out_wifireMux_out_272, _out_wifireMux_T_1097) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_273 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1099 = and(_out_wifireMux_T_262, out_frontSel_209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1100 = and(_out_wifireMux_T_1099, _out_T_1532) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_273, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[810], _out_wifireMux_T_1100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[809], _out_wifireMux_T_1100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[808], _out_wifireMux_T_1100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[807], _out_wifireMux_T_1100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[806], _out_wifireMux_T_1100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[805], _out_wifireMux_T_1100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[804], _out_wifireMux_T_1100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[803], _out_wifireMux_T_1100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1101 = eq(_out_T_1532, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1102 = or(out_wifireMux_out_273, _out_wifireMux_T_1101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_274 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1103 = and(_out_wifireMux_T_262, out_frontSel_210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1104 = and(_out_wifireMux_T_1103, _out_T_1596) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_274, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1066], _out_wifireMux_T_1104 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1065], _out_wifireMux_T_1104 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1064], _out_wifireMux_T_1104 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1063], _out_wifireMux_T_1104 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1062], _out_wifireMux_T_1104 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1061], _out_wifireMux_T_1104 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1060], _out_wifireMux_T_1104 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1059], _out_wifireMux_T_1104 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1105 = eq(_out_T_1596, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1106 = or(out_wifireMux_out_274, _out_wifireMux_T_1105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_275 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1107 = and(_out_wifireMux_T_262, out_frontSel_211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1108 = and(_out_wifireMux_T_1107, _out_T_1374) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_275, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[207], _out_wifireMux_T_1108 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[206], _out_wifireMux_T_1108 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[205], _out_wifireMux_T_1108 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[204], _out_wifireMux_T_1108 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[203], _out_wifireMux_T_1108 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[202], _out_wifireMux_T_1108 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[201], _out_wifireMux_T_1108 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[200], _out_wifireMux_T_1108 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1109 = eq(_out_T_1374, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1110 = or(out_wifireMux_out_275, _out_wifireMux_T_1109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_276 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1111 = and(_out_wifireMux_T_262, out_frontSel_212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1112 = and(_out_wifireMux_T_1111, _out_T_1432) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_276, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[433], _out_wifireMux_T_1112 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[432], _out_wifireMux_T_1112 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[431], _out_wifireMux_T_1112 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[430], _out_wifireMux_T_1112 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[429], _out_wifireMux_T_1112 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[428], _out_wifireMux_T_1112 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[427], _out_wifireMux_T_1112 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[426], _out_wifireMux_T_1112 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1113 = eq(_out_T_1432, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1114 = or(out_wifireMux_out_276, _out_wifireMux_T_1113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_277 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1115 = and(_out_wifireMux_T_262, out_frontSel_213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1116 = and(_out_wifireMux_T_1115, _out_T_1504) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_277, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[698], _out_wifireMux_T_1116 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[697], _out_wifireMux_T_1116 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[696], _out_wifireMux_T_1116 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[695], _out_wifireMux_T_1116 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[694], _out_wifireMux_T_1116 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[693], _out_wifireMux_T_1116 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[692], _out_wifireMux_T_1116 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[691], _out_wifireMux_T_1116 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1117 = eq(_out_T_1504, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1118 = or(out_wifireMux_out_277, _out_wifireMux_T_1117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_278 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1119 = and(_out_wifireMux_T_262, out_frontSel_214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1120 = and(_out_wifireMux_T_1119, _out_T_1578) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_278, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[994], _out_wifireMux_T_1120 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[993], _out_wifireMux_T_1120 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[992], _out_wifireMux_T_1120 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[991], _out_wifireMux_T_1120 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[990], _out_wifireMux_T_1120 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[989], _out_wifireMux_T_1120 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[988], _out_wifireMux_T_1120 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[987], _out_wifireMux_T_1120 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1121 = eq(_out_T_1578, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1122 = or(out_wifireMux_out_278, _out_wifireMux_T_1121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_279 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1123 = and(_out_wifireMux_T_262, out_frontSel_215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1124 = and(_out_wifireMux_T_1123, _out_T_1618) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_279, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1154], _out_wifireMux_T_1124 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1153], _out_wifireMux_T_1124 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1152], _out_wifireMux_T_1124 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1151], _out_wifireMux_T_1124 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1150], _out_wifireMux_T_1124 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1149], _out_wifireMux_T_1124 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1148], _out_wifireMux_T_1124 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1147], _out_wifireMux_T_1124 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1125 = eq(_out_T_1618, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1126 = or(out_wifireMux_out_279, _out_wifireMux_T_1125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_280 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1127 = and(_out_wifireMux_T_262, out_frontSel_216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1128 = and(_out_wifireMux_T_1127, _out_T_1364) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_280, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[167], _out_wifireMux_T_1128 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[166], _out_wifireMux_T_1128 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[165], _out_wifireMux_T_1128 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[164], _out_wifireMux_T_1128 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[163], _out_wifireMux_T_1128 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[162], _out_wifireMux_T_1128 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[161], _out_wifireMux_T_1128 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[160], _out_wifireMux_T_1128 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1129 = eq(_out_T_1364, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1130 = or(out_wifireMux_out_280, _out_wifireMux_T_1129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_281 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1131 = and(_out_wifireMux_T_262, out_frontSel_217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1132 = and(_out_wifireMux_T_1131, _out_T_1332) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_281, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[39], _out_wifireMux_T_1132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[38], _out_wifireMux_T_1132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[37], _out_wifireMux_T_1132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[36], _out_wifireMux_T_1132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[35], _out_wifireMux_T_1132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[34], _out_wifireMux_T_1132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[33], _out_wifireMux_T_1132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[32], _out_wifireMux_T_1132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1133 = eq(_out_T_1332, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1134 = or(out_wifireMux_out_281, _out_wifireMux_T_1133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_282 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1135 = and(_out_wifireMux_T_262, out_frontSel_218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1136 = and(_out_wifireMux_T_1135, _out_T_1558) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_282, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[914], _out_wifireMux_T_1136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[913], _out_wifireMux_T_1136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[912], _out_wifireMux_T_1136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[911], _out_wifireMux_T_1136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[910], _out_wifireMux_T_1136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[909], _out_wifireMux_T_1136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[908], _out_wifireMux_T_1136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[907], _out_wifireMux_T_1136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1137 = eq(_out_T_1558, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1138 = or(out_wifireMux_out_282, _out_wifireMux_T_1137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_283 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1139 = and(_out_wifireMux_T_262, out_frontSel_219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1140 = and(_out_wifireMux_T_1139, _out_T_1492) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_283, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[656], _out_wifireMux_T_1140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[655], _out_wifireMux_T_1140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[654], _out_wifireMux_T_1140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[653], _out_wifireMux_T_1140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[652], _out_wifireMux_T_1140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[651], _out_wifireMux_T_1140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[650], _out_wifireMux_T_1140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[649], _out_wifireMux_T_1140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1141 = eq(_out_T_1492, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1142 = or(out_wifireMux_out_283, _out_wifireMux_T_1141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_284 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1143 = and(_out_wifireMux_T_262, out_frontSel_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1144 = and(_out_wifireMux_T_1143, _out_T_1398) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_284, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[303], _out_wifireMux_T_1144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[302], _out_wifireMux_T_1144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[301], _out_wifireMux_T_1144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[300], _out_wifireMux_T_1144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[299], _out_wifireMux_T_1144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[298], _out_wifireMux_T_1144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[297], _out_wifireMux_T_1144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[296], _out_wifireMux_T_1144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1145 = eq(_out_T_1398, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1146 = or(out_wifireMux_out_284, _out_wifireMux_T_1145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_285 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1147 = and(_out_wifireMux_T_262, out_frontSel_221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1148 = and(_out_wifireMux_T_1147, _out_T_1380) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_285, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[231], _out_wifireMux_T_1148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[230], _out_wifireMux_T_1148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[229], _out_wifireMux_T_1148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[228], _out_wifireMux_T_1148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[227], _out_wifireMux_T_1148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[226], _out_wifireMux_T_1148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[225], _out_wifireMux_T_1148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[224], _out_wifireMux_T_1148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1149 = eq(_out_T_1380, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1150 = or(out_wifireMux_out_285, _out_wifireMux_T_1149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_286 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1151 = and(_out_wifireMux_T_262, out_frontSel_222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1152 = and(_out_wifireMux_T_1151, _out_T_1620) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_286, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1162], _out_wifireMux_T_1152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1161], _out_wifireMux_T_1152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1160], _out_wifireMux_T_1152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1159], _out_wifireMux_T_1152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1158], _out_wifireMux_T_1152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1157], _out_wifireMux_T_1152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1156], _out_wifireMux_T_1152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1155], _out_wifireMux_T_1152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1153 = eq(_out_T_1620, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1154 = or(out_wifireMux_out_286, _out_wifireMux_T_1153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_287 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1155 = and(_out_wifireMux_T_262, out_frontSel_223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1156 = and(_out_wifireMux_T_1155, _out_T_1518) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_287, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[754], _out_wifireMux_T_1156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[753], _out_wifireMux_T_1156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[752], _out_wifireMux_T_1156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[751], _out_wifireMux_T_1156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[750], _out_wifireMux_T_1156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[749], _out_wifireMux_T_1156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[748], _out_wifireMux_T_1156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[747], _out_wifireMux_T_1156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1157 = eq(_out_T_1518, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1158 = or(out_wifireMux_out_287, _out_wifireMux_T_1157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_288 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1159 = and(_out_wifireMux_T_262, out_frontSel_224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1160 = and(_out_wifireMux_T_1159, _out_T_1418) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_288, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[377], _out_wifireMux_T_1160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[376], _out_wifireMux_T_1160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[375], _out_wifireMux_T_1160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[374], _out_wifireMux_T_1160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[373], _out_wifireMux_T_1160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[372], _out_wifireMux_T_1160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[371], _out_wifireMux_T_1160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[370], _out_wifireMux_T_1160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1161 = eq(_out_T_1418, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1162 = or(out_wifireMux_out_288, _out_wifireMux_T_1161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_289 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1163 = and(_out_wifireMux_T_262, out_frontSel_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1164 = and(_out_wifireMux_T_1163, _out_T_1428) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_289, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[417], _out_wifireMux_T_1164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[416], _out_wifireMux_T_1164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[415], _out_wifireMux_T_1164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[414], _out_wifireMux_T_1164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[413], _out_wifireMux_T_1164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[412], _out_wifireMux_T_1164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[411], _out_wifireMux_T_1164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[410], _out_wifireMux_T_1164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1165 = eq(_out_T_1428, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1166 = or(out_wifireMux_out_289, _out_wifireMux_T_1165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_290 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1167 = and(_out_wifireMux_T_262, out_frontSel_226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1168 = and(_out_wifireMux_T_1167, _out_T_1522) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_290, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[770], _out_wifireMux_T_1168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[769], _out_wifireMux_T_1168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[768], _out_wifireMux_T_1168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[767], _out_wifireMux_T_1168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[766], _out_wifireMux_T_1168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[765], _out_wifireMux_T_1168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[764], _out_wifireMux_T_1168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[763], _out_wifireMux_T_1168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1169 = eq(_out_T_1522, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1170 = or(out_wifireMux_out_290, _out_wifireMux_T_1169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_291 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1171 = and(_out_wifireMux_T_262, out_frontSel_227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1172 = and(_out_wifireMux_T_1171, _out_T_1626) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_291, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1186], _out_wifireMux_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1185], _out_wifireMux_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1184], _out_wifireMux_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1183], _out_wifireMux_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1182], _out_wifireMux_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1181], _out_wifireMux_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1180], _out_wifireMux_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1179], _out_wifireMux_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1173 = eq(_out_T_1626, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1174 = or(out_wifireMux_out_291, _out_wifireMux_T_1173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_292 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1175 = and(_out_wifireMux_T_262, out_frontSel_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1176 = and(_out_wifireMux_T_1175, _out_T_1360) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_292, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[151], _out_wifireMux_T_1176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[150], _out_wifireMux_T_1176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[149], _out_wifireMux_T_1176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[148], _out_wifireMux_T_1176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[147], _out_wifireMux_T_1176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[146], _out_wifireMux_T_1176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[145], _out_wifireMux_T_1176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[144], _out_wifireMux_T_1176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1177 = eq(_out_T_1360, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1178 = or(out_wifireMux_out_292, _out_wifireMux_T_1177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_293 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1179 = and(_out_wifireMux_T_262, out_frontSel_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1180 = and(_out_wifireMux_T_1179, _out_T_1412) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_293, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[353], _out_wifireMux_T_1180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[352], _out_wifireMux_T_1180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[351], _out_wifireMux_T_1180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[350], _out_wifireMux_T_1180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[349], _out_wifireMux_T_1180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[348], _out_wifireMux_T_1180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[347], _out_wifireMux_T_1180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[346], _out_wifireMux_T_1180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1181 = eq(_out_T_1412, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1182 = or(out_wifireMux_out_293, _out_wifireMux_T_1181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_294 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1183 = and(_out_wifireMux_T_262, out_frontSel_230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1184 = and(_out_wifireMux_T_1183, _out_T_1494) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_294, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[664], _out_wifireMux_T_1184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[663], _out_wifireMux_T_1184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[662], _out_wifireMux_T_1184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[661], _out_wifireMux_T_1184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[660], _out_wifireMux_T_1184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[659], _out_wifireMux_T_1184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[658], _out_wifireMux_T_1184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[657], _out_wifireMux_T_1184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1185 = eq(_out_T_1494, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1186 = or(out_wifireMux_out_294, _out_wifireMux_T_1185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_295 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1187 = and(_out_wifireMux_T_262, out_frontSel_231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1188 = and(_out_wifireMux_T_1187, _out_T_1564) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_295, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[938], _out_wifireMux_T_1188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[937], _out_wifireMux_T_1188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[936], _out_wifireMux_T_1188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[935], _out_wifireMux_T_1188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[934], _out_wifireMux_T_1188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[933], _out_wifireMux_T_1188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[932], _out_wifireMux_T_1188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[931], _out_wifireMux_T_1188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1189 = eq(_out_T_1564, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1190 = or(out_wifireMux_out_295, _out_wifireMux_T_1189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_296 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1191 = and(_out_wifireMux_T_262, out_frontSel_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1192 = and(_out_wifireMux_T_1191, _out_T_1622) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_296, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1170], _out_wifireMux_T_1192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1169], _out_wifireMux_T_1192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1168], _out_wifireMux_T_1192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1167], _out_wifireMux_T_1192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1166], _out_wifireMux_T_1192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1165], _out_wifireMux_T_1192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1164], _out_wifireMux_T_1192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1163], _out_wifireMux_T_1192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1193 = eq(_out_T_1622, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1194 = or(out_wifireMux_out_296, _out_wifireMux_T_1193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_297 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1195 = and(_out_wifireMux_T_262, out_frontSel_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1196 = and(_out_wifireMux_T_1195, _out_T_1392) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_297, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[279], _out_wifireMux_T_1196 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[278], _out_wifireMux_T_1196 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[277], _out_wifireMux_T_1196 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[276], _out_wifireMux_T_1196 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[275], _out_wifireMux_T_1196 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[274], _out_wifireMux_T_1196 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[273], _out_wifireMux_T_1196 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[272], _out_wifireMux_T_1196 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1197 = eq(_out_T_1392, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1198 = or(out_wifireMux_out_297, _out_wifireMux_T_1197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_298 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1199 = and(_out_wifireMux_T_262, out_frontSel_234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1200 = and(_out_wifireMux_T_1199, _out_T_1328) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_298, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[23], _out_wifireMux_T_1200 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[22], _out_wifireMux_T_1200 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[21], _out_wifireMux_T_1200 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[20], _out_wifireMux_T_1200 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[19], _out_wifireMux_T_1200 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[18], _out_wifireMux_T_1200 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[17], _out_wifireMux_T_1200 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[16], _out_wifireMux_T_1200 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1201 = eq(_out_T_1328, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1202 = or(out_wifireMux_out_298, _out_wifireMux_T_1201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_299 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1203 = and(_out_wifireMux_T_262, out_frontSel_235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1204 = and(_out_wifireMux_T_1203, _out_T_1580) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_299, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1002], _out_wifireMux_T_1204 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1001], _out_wifireMux_T_1204 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1000], _out_wifireMux_T_1204 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[999], _out_wifireMux_T_1204 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[998], _out_wifireMux_T_1204 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[997], _out_wifireMux_T_1204 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[996], _out_wifireMux_T_1204 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[995], _out_wifireMux_T_1204 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1205 = eq(_out_T_1580, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1206 = or(out_wifireMux_out_299, _out_wifireMux_T_1205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_300 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1207 = and(_out_wifireMux_T_262, out_frontSel_236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1208 = and(_out_wifireMux_T_1207, _out_T_1482) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_300, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[616], _out_wifireMux_T_1208 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[615], _out_wifireMux_T_1208 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[614], _out_wifireMux_T_1208 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[613], _out_wifireMux_T_1208 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[612], _out_wifireMux_T_1208 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[611], _out_wifireMux_T_1208 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[610], _out_wifireMux_T_1208 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[609], _out_wifireMux_T_1208 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1209 = eq(_out_T_1482, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1210 = or(out_wifireMux_out_300, _out_wifireMux_T_1209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_301 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1211 = and(_out_wifireMux_T_262, out_frontSel_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1212 = and(_out_wifireMux_T_1211, _out_T_1452) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_301, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[502], _out_wifireMux_T_1212 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[501], _out_wifireMux_T_1212 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[500], _out_wifireMux_T_1212 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[499], _out_wifireMux_T_1212 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[498], _out_wifireMux_T_1212 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[497], _out_wifireMux_T_1212 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[496], _out_wifireMux_T_1212 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[495], _out_wifireMux_T_1212 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1213 = eq(_out_T_1452, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1214 = or(out_wifireMux_out_301, _out_wifireMux_T_1213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_302 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1215 = and(_out_wifireMux_T_262, out_frontSel_238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1216 = and(_out_wifireMux_T_1215, _out_T_1372) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_302, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[199], _out_wifireMux_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[198], _out_wifireMux_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[197], _out_wifireMux_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[196], _out_wifireMux_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[195], _out_wifireMux_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[194], _out_wifireMux_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[193], _out_wifireMux_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[192], _out_wifireMux_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1217 = eq(_out_T_1372, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1218 = or(out_wifireMux_out_302, _out_wifireMux_T_1217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_303 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1219 = and(_out_wifireMux_T_262, out_frontSel_239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1220 = and(_out_wifireMux_T_1219, _out_T_1604) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_303, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1098], _out_wifireMux_T_1220 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1097], _out_wifireMux_T_1220 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1096], _out_wifireMux_T_1220 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1095], _out_wifireMux_T_1220 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1094], _out_wifireMux_T_1220 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1093], _out_wifireMux_T_1220 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1092], _out_wifireMux_T_1220 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1091], _out_wifireMux_T_1220 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1221 = eq(_out_T_1604, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1222 = or(out_wifireMux_out_303, _out_wifireMux_T_1221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_304 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1223 = and(_out_wifireMux_T_262, out_frontSel_240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1224 = and(_out_wifireMux_T_1223, _out_T_1512) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_304, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[730], _out_wifireMux_T_1224 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[729], _out_wifireMux_T_1224 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[728], _out_wifireMux_T_1224 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[727], _out_wifireMux_T_1224 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[726], _out_wifireMux_T_1224 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[725], _out_wifireMux_T_1224 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[724], _out_wifireMux_T_1224 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[723], _out_wifireMux_T_1224 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1225 = eq(_out_T_1512, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1226 = or(out_wifireMux_out_304, _out_wifireMux_T_1225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_305 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1227 = and(_out_wifireMux_T_262, out_frontSel_241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1228 = and(_out_wifireMux_T_1227, _out_T_1524) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_305, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[778], _out_wifireMux_T_1228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[777], _out_wifireMux_T_1228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[776], _out_wifireMux_T_1228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[775], _out_wifireMux_T_1228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[774], _out_wifireMux_T_1228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[773], _out_wifireMux_T_1228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[772], _out_wifireMux_T_1228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[771], _out_wifireMux_T_1228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1229 = eq(_out_T_1524, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1230 = or(out_wifireMux_out_305, _out_wifireMux_T_1229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_306 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1231 = and(_out_wifireMux_T_262, out_frontSel_242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1232 = and(_out_wifireMux_T_1231, _out_T_1606) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_306, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1106], _out_wifireMux_T_1232 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1105], _out_wifireMux_T_1232 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1104], _out_wifireMux_T_1232 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1103], _out_wifireMux_T_1232 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1102], _out_wifireMux_T_1232 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1101], _out_wifireMux_T_1232 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1100], _out_wifireMux_T_1232 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1099], _out_wifireMux_T_1232 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1233 = eq(_out_T_1606, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1234 = or(out_wifireMux_out_306, _out_wifireMux_T_1233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_307 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1235 = and(_out_wifireMux_T_262, out_frontSel_243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1236 = and(_out_wifireMux_T_1235, _out_T_1386) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_307, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[255], _out_wifireMux_T_1236 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[254], _out_wifireMux_T_1236 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[253], _out_wifireMux_T_1236 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[252], _out_wifireMux_T_1236 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[251], _out_wifireMux_T_1236 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[250], _out_wifireMux_T_1236 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[249], _out_wifireMux_T_1236 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[248], _out_wifireMux_T_1236 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1237 = eq(_out_T_1386, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1238 = or(out_wifireMux_out_307, _out_wifireMux_T_1237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_308 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1239 = and(_out_wifireMux_T_262, out_frontSel_244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1240 = and(_out_wifireMux_T_1239, _out_T_1456) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_308, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[518], _out_wifireMux_T_1240 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[517], _out_wifireMux_T_1240 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[516], _out_wifireMux_T_1240 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[515], _out_wifireMux_T_1240 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[514], _out_wifireMux_T_1240 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[513], _out_wifireMux_T_1240 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[512], _out_wifireMux_T_1240 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[511], _out_wifireMux_T_1240 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1241 = eq(_out_T_1456, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1242 = or(out_wifireMux_out_308, _out_wifireMux_T_1241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_309 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1243 = and(_out_wifireMux_T_262, out_frontSel_245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1244 = and(_out_wifireMux_T_1243, _out_T_1496) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_309, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[672], _out_wifireMux_T_1244 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[671], _out_wifireMux_T_1244 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[670], _out_wifireMux_T_1244 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[669], _out_wifireMux_T_1244 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[668], _out_wifireMux_T_1244 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[667], _out_wifireMux_T_1244 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[666], _out_wifireMux_T_1244 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[665], _out_wifireMux_T_1244 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1245 = eq(_out_T_1496, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1246 = or(out_wifireMux_out_309, _out_wifireMux_T_1245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_310 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1247 = and(_out_wifireMux_T_262, out_frontSel_246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1248 = and(_out_wifireMux_T_1247, _out_T_1582) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_310, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1010], _out_wifireMux_T_1248 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1009], _out_wifireMux_T_1248 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1008], _out_wifireMux_T_1248 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1007], _out_wifireMux_T_1248 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1006], _out_wifireMux_T_1248 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1005], _out_wifireMux_T_1248 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1004], _out_wifireMux_T_1248 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1003], _out_wifireMux_T_1248 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1249 = eq(_out_T_1582, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1250 = or(out_wifireMux_out_310, _out_wifireMux_T_1249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_311 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1251 = and(_out_wifireMux_T_262, out_frontSel_247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1252 = and(_out_wifireMux_T_1251, _out_T_1334) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_311, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[47], _out_wifireMux_T_1252 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[46], _out_wifireMux_T_1252 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[45], _out_wifireMux_T_1252 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[44], _out_wifireMux_T_1252 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[43], _out_wifireMux_T_1252 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[42], _out_wifireMux_T_1252 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[41], _out_wifireMux_T_1252 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[40], _out_wifireMux_T_1252 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1253 = eq(_out_T_1334, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1254 = or(out_wifireMux_out_311, _out_wifireMux_T_1253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_312 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1255 = and(_out_wifireMux_T_262, out_frontSel_248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1256 = and(_out_wifireMux_T_1255, _out_T_1394) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_312, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[287], _out_wifireMux_T_1256 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[286], _out_wifireMux_T_1256 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[285], _out_wifireMux_T_1256 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[284], _out_wifireMux_T_1256 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[283], _out_wifireMux_T_1256 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[282], _out_wifireMux_T_1256 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[281], _out_wifireMux_T_1256 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[280], _out_wifireMux_T_1256 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1257 = eq(_out_T_1394, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1258 = or(out_wifireMux_out_312, _out_wifireMux_T_1257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_313 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1259 = and(_out_wifireMux_T_262, out_frontSel_249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1260 = and(_out_wifireMux_T_1259, _out_T_1326) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_313, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[15], _out_wifireMux_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[14], _out_wifireMux_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[13], _out_wifireMux_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[12], _out_wifireMux_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[11], _out_wifireMux_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[10], _out_wifireMux_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[9], _out_wifireMux_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[8], _out_wifireMux_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1261 = eq(_out_T_1326, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1262 = or(out_wifireMux_out_313, _out_wifireMux_T_1261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_314 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1263 = and(_out_wifireMux_T_262, out_frontSel_250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1264 = and(_out_wifireMux_T_1263, _out_T_1562) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_314, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[930], _out_wifireMux_T_1264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[929], _out_wifireMux_T_1264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[928], _out_wifireMux_T_1264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[927], _out_wifireMux_T_1264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[926], _out_wifireMux_T_1264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[925], _out_wifireMux_T_1264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[924], _out_wifireMux_T_1264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[923], _out_wifireMux_T_1264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1265 = eq(_out_T_1562, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1266 = or(out_wifireMux_out_314, _out_wifireMux_T_1265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_315 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1267 = and(_out_wifireMux_T_262, out_frontSel_251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1268 = and(_out_wifireMux_T_1267, _out_T_1514) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_315, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[738], _out_wifireMux_T_1268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[737], _out_wifireMux_T_1268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[736], _out_wifireMux_T_1268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[735], _out_wifireMux_T_1268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[734], _out_wifireMux_T_1268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[733], _out_wifireMux_T_1268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[732], _out_wifireMux_T_1268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[731], _out_wifireMux_T_1268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1269 = eq(_out_T_1514, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1270 = or(out_wifireMux_out_315, _out_wifireMux_T_1269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_316 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1271 = and(_out_wifireMux_T_262, out_frontSel_252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1272 = and(_out_wifireMux_T_1271, _out_T_1414) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_316, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[361], _out_wifireMux_T_1272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[360], _out_wifireMux_T_1272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[359], _out_wifireMux_T_1272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[358], _out_wifireMux_T_1272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[357], _out_wifireMux_T_1272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[356], _out_wifireMux_T_1272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[355], _out_wifireMux_T_1272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[354], _out_wifireMux_T_1272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1273 = eq(_out_T_1414, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1274 = or(out_wifireMux_out_316, _out_wifireMux_T_1273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_317 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1275 = and(_out_wifireMux_T_262, out_frontSel_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1276 = and(_out_wifireMux_T_1275, _out_T_1376) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_317, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[215], _out_wifireMux_T_1276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[214], _out_wifireMux_T_1276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[213], _out_wifireMux_T_1276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[212], _out_wifireMux_T_1276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[211], _out_wifireMux_T_1276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[210], _out_wifireMux_T_1276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[209], _out_wifireMux_T_1276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[208], _out_wifireMux_T_1276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1277 = eq(_out_T_1376, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1278 = or(out_wifireMux_out_317, _out_wifireMux_T_1277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_318 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1279 = and(_out_wifireMux_T_262, out_frontSel_254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1280 = and(_out_wifireMux_T_1279, _out_T_1624) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_318, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1178], _out_wifireMux_T_1280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1177], _out_wifireMux_T_1280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1176], _out_wifireMux_T_1280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1175], _out_wifireMux_T_1280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1174], _out_wifireMux_T_1280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1173], _out_wifireMux_T_1280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1172], _out_wifireMux_T_1280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[1171], _out_wifireMux_T_1280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1281 = eq(_out_T_1624, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1282 = or(out_wifireMux_out_318, _out_wifireMux_T_1281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_319 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1283 = and(_out_wifireMux_T_262, out_frontSel_255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1284 = and(_out_wifireMux_T_1283, _out_T_1530) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_319, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[802], _out_wifireMux_T_1284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[801], _out_wifireMux_T_1284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[800], _out_wifireMux_T_1284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[799], _out_wifireMux_T_1284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[798], _out_wifireMux_T_1284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[797], _out_wifireMux_T_1284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[796], _out_wifireMux_T_1284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid_1[795], _out_wifireMux_T_1284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_1285 = eq(_out_T_1530, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1286 = or(out_wifireMux_out_319, _out_wifireMux_T_1285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1287 = geq(out_iindex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_wifireMux_WIRE_1 : UInt<1>[256] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[0], _out_wifireMux_T_266 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[1], _out_wifireMux_T_270 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[2], _out_wifireMux_T_274 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[3], _out_wifireMux_T_278 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[4], _out_wifireMux_T_282 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[5], _out_wifireMux_T_286 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[6], _out_wifireMux_T_290 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[7], _out_wifireMux_T_294 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[8], _out_wifireMux_T_298 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[9], _out_wifireMux_T_302 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[10], _out_wifireMux_T_306 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[11], _out_wifireMux_T_310 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[12], _out_wifireMux_T_314 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[13], _out_wifireMux_T_318 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[14], _out_wifireMux_T_322 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[15], _out_wifireMux_T_326 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[16], _out_wifireMux_T_330 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[17], _out_wifireMux_T_334 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[18], _out_wifireMux_T_338 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[19], _out_wifireMux_T_342 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[20], _out_wifireMux_T_346 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[21], _out_wifireMux_T_350 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[22], _out_wifireMux_T_354 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[23], _out_wifireMux_T_358 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[24], _out_wifireMux_T_362 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[25], _out_wifireMux_T_366 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[26], _out_wifireMux_T_370 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[27], _out_wifireMux_T_374 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[28], _out_wifireMux_T_378 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[29], _out_wifireMux_T_382 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[30], _out_wifireMux_T_386 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[31], _out_wifireMux_T_390 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[32], _out_wifireMux_T_394 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[33], _out_wifireMux_T_398 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[34], _out_wifireMux_T_402 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[35], _out_wifireMux_T_406 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[36], _out_wifireMux_T_410 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[37], _out_wifireMux_T_414 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[38], _out_wifireMux_T_418 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[39], _out_wifireMux_T_422 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[40], _out_wifireMux_T_426 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[41], _out_wifireMux_T_430 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[42], _out_wifireMux_T_434 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[43], _out_wifireMux_T_438 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[44], _out_wifireMux_T_442 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[45], _out_wifireMux_T_446 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[46], _out_wifireMux_T_450 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[47], _out_wifireMux_T_454 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[48], _out_wifireMux_T_458 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[49], _out_wifireMux_T_462 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[50], _out_wifireMux_T_466 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[51], _out_wifireMux_T_470 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[52], _out_wifireMux_T_474 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[53], _out_wifireMux_T_478 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[54], _out_wifireMux_T_482 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[55], _out_wifireMux_T_486 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[56], _out_wifireMux_T_490 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[57], _out_wifireMux_T_494 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[58], _out_wifireMux_T_498 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[59], _out_wifireMux_T_502 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[60], _out_wifireMux_T_506 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[61], _out_wifireMux_T_510 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[62], _out_wifireMux_T_514 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[63], _out_wifireMux_T_518 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[64], _out_wifireMux_T_522 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[65], _out_wifireMux_T_526 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[66], _out_wifireMux_T_530 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[67], _out_wifireMux_T_534 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[68], _out_wifireMux_T_538 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[69], _out_wifireMux_T_542 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[70], _out_wifireMux_T_546 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[71], _out_wifireMux_T_550 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[72], _out_wifireMux_T_554 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[73], _out_wifireMux_T_558 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[74], _out_wifireMux_T_562 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[75], _out_wifireMux_T_566 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[76], _out_wifireMux_T_570 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[77], _out_wifireMux_T_574 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[78], _out_wifireMux_T_578 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[79], _out_wifireMux_T_582 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[80], _out_wifireMux_T_586 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[81], _out_wifireMux_T_590 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[82], _out_wifireMux_T_594 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[83], _out_wifireMux_T_598 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[84], _out_wifireMux_T_602 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[85], _out_wifireMux_T_606 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[86], _out_wifireMux_T_610 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[87], _out_wifireMux_T_614 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[88], _out_wifireMux_T_618 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[89], _out_wifireMux_T_622 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[90], _out_wifireMux_T_626 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[91], _out_wifireMux_T_630 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[92], _out_wifireMux_T_634 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[93], _out_wifireMux_T_638 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[94], _out_wifireMux_T_642 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[95], _out_wifireMux_T_646 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[96], _out_wifireMux_T_650 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[97], _out_wifireMux_T_654 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[98], _out_wifireMux_T_658 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[99], _out_wifireMux_T_662 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[100], _out_wifireMux_T_666 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[101], _out_wifireMux_T_670 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[102], _out_wifireMux_T_674 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[103], _out_wifireMux_T_678 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[104], _out_wifireMux_T_682 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[105], _out_wifireMux_T_686 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[106], _out_wifireMux_T_690 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[107], _out_wifireMux_T_694 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[108], _out_wifireMux_T_698 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[109], _out_wifireMux_T_702 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[110], _out_wifireMux_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[111], _out_wifireMux_T_710 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[112], _out_wifireMux_T_714 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[113], _out_wifireMux_T_718 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[114], _out_wifireMux_T_722 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[115], _out_wifireMux_T_726 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[116], _out_wifireMux_T_730 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[117], _out_wifireMux_T_734 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[118], _out_wifireMux_T_738 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[119], _out_wifireMux_T_742 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[120], _out_wifireMux_T_746 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[121], _out_wifireMux_T_750 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[122], _out_wifireMux_T_754 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[123], _out_wifireMux_T_758 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[124], _out_wifireMux_T_762 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[125], _out_wifireMux_T_766 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[126], _out_wifireMux_T_770 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[127], _out_wifireMux_T_774 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[128], _out_wifireMux_T_778 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[129], _out_wifireMux_T_782 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[130], _out_wifireMux_T_786 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[131], _out_wifireMux_T_790 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[132], _out_wifireMux_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[133], _out_wifireMux_T_798 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[134], _out_wifireMux_T_802 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[135], _out_wifireMux_T_806 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[136], _out_wifireMux_T_810 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[137], _out_wifireMux_T_814 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[138], _out_wifireMux_T_818 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[139], _out_wifireMux_T_822 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[140], _out_wifireMux_T_826 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[141], _out_wifireMux_T_830 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[142], _out_wifireMux_T_834 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[143], _out_wifireMux_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[144], _out_wifireMux_T_842 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[145], _out_wifireMux_T_846 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[146], _out_wifireMux_T_850 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[147], _out_wifireMux_T_854 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[148], _out_wifireMux_T_858 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[149], _out_wifireMux_T_862 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[150], _out_wifireMux_T_866 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[151], _out_wifireMux_T_870 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[152], _out_wifireMux_T_874 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[153], _out_wifireMux_T_878 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[154], _out_wifireMux_T_882 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[155], _out_wifireMux_T_886 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[156], _out_wifireMux_T_890 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[157], _out_wifireMux_T_894 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[158], _out_wifireMux_T_898 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[159], _out_wifireMux_T_902 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[160], _out_wifireMux_T_906 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[161], _out_wifireMux_T_910 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[162], _out_wifireMux_T_914 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[163], _out_wifireMux_T_918 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[164], _out_wifireMux_T_922 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[165], _out_wifireMux_T_926 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[166], _out_wifireMux_T_930 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[167], _out_wifireMux_T_934 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[168], _out_wifireMux_T_938 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[169], _out_wifireMux_T_942 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[170], _out_wifireMux_T_946 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[171], _out_wifireMux_T_950 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[172], _out_wifireMux_T_954 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[173], _out_wifireMux_T_958 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[174], _out_wifireMux_T_962 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[175], _out_wifireMux_T_966 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[176], _out_wifireMux_T_970 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[177], _out_wifireMux_T_974 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[178], _out_wifireMux_T_978 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[179], _out_wifireMux_T_982 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[180], _out_wifireMux_T_986 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[181], _out_wifireMux_T_990 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[182], _out_wifireMux_T_994 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[183], _out_wifireMux_T_998 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[184], _out_wifireMux_T_1002 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[185], _out_wifireMux_T_1006 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[186], _out_wifireMux_T_1010 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[187], _out_wifireMux_T_1014 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[188], _out_wifireMux_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[189], _out_wifireMux_T_1022 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[190], _out_wifireMux_T_1026 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[191], _out_wifireMux_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[192], _out_wifireMux_T_1034 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[193], _out_wifireMux_T_1038 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[194], _out_wifireMux_T_1042 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[195], _out_wifireMux_T_1046 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[196], _out_wifireMux_T_1050 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[197], _out_wifireMux_T_1054 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[198], _out_wifireMux_T_1058 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[199], _out_wifireMux_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[200], _out_wifireMux_T_1066 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[201], _out_wifireMux_T_1070 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[202], _out_wifireMux_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[203], _out_wifireMux_T_1078 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[204], _out_wifireMux_T_1082 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[205], _out_wifireMux_T_1086 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[206], _out_wifireMux_T_1090 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[207], _out_wifireMux_T_1094 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[208], _out_wifireMux_T_1098 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[209], _out_wifireMux_T_1102 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[210], _out_wifireMux_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[211], _out_wifireMux_T_1110 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[212], _out_wifireMux_T_1114 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[213], _out_wifireMux_T_1118 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[214], _out_wifireMux_T_1122 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[215], _out_wifireMux_T_1126 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[216], _out_wifireMux_T_1130 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[217], _out_wifireMux_T_1134 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[218], _out_wifireMux_T_1138 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[219], _out_wifireMux_T_1142 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[220], _out_wifireMux_T_1146 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[221], _out_wifireMux_T_1150 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[222], _out_wifireMux_T_1154 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[223], _out_wifireMux_T_1158 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[224], _out_wifireMux_T_1162 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[225], _out_wifireMux_T_1166 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[226], _out_wifireMux_T_1170 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[227], _out_wifireMux_T_1174 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[228], _out_wifireMux_T_1178 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[229], _out_wifireMux_T_1182 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[230], _out_wifireMux_T_1186 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[231], _out_wifireMux_T_1190 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[232], _out_wifireMux_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[233], _out_wifireMux_T_1198 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[234], _out_wifireMux_T_1202 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[235], _out_wifireMux_T_1206 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[236], _out_wifireMux_T_1210 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[237], _out_wifireMux_T_1214 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[238], _out_wifireMux_T_1218 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[239], _out_wifireMux_T_1222 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[240], _out_wifireMux_T_1226 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[241], _out_wifireMux_T_1230 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[242], _out_wifireMux_T_1234 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[243], _out_wifireMux_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[244], _out_wifireMux_T_1242 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[245], _out_wifireMux_T_1246 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[246], _out_wifireMux_T_1250 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[247], _out_wifireMux_T_1254 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[248], _out_wifireMux_T_1258 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[249], _out_wifireMux_T_1262 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[250], _out_wifireMux_T_1266 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[251], _out_wifireMux_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[252], _out_wifireMux_T_1274 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[253], _out_wifireMux_T_1278 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[254], _out_wifireMux_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE_1[255], _out_wifireMux_T_1286 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_wifireMux_1 = mux(_out_wifireMux_T_1287, UInt<1>(0h1), _out_wifireMux_WIRE_1[out_iindex_1]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_rofireMux_T_259 = and(out_front_1.valid, out_1.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_260 = and(_out_rofireMux_T_259, out_front_1.bits.read) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_64 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_261 = and(_out_rofireMux_T_260, out_backSel_0_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_262 = and(_out_rofireMux_T_261, _out_T_1439) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_64, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[450], _out_rofireMux_T_262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[449], _out_rofireMux_T_262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[448], _out_rofireMux_T_262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[447], _out_rofireMux_T_262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[446], _out_rofireMux_T_262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[445], _out_rofireMux_T_262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[444], _out_rofireMux_T_262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[443], _out_rofireMux_T_262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_263 = eq(_out_T_1439, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_264 = or(out_rofireMux_out_64, _out_rofireMux_T_263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_65 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_265 = and(_out_rofireMux_T_260, out_backSel_1_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_266 = and(_out_rofireMux_T_265, _out_T_1347) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_65, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[95], _out_rofireMux_T_266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[94], _out_rofireMux_T_266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[93], _out_rofireMux_T_266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[92], _out_rofireMux_T_266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[91], _out_rofireMux_T_266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[90], _out_rofireMux_T_266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[89], _out_rofireMux_T_266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[88], _out_rofireMux_T_266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_267 = eq(_out_T_1347, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_268 = or(out_rofireMux_out_65, _out_rofireMux_T_267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_66 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_269 = and(_out_rofireMux_T_260, out_backSel_2_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_270 = and(_out_rofireMux_T_269, _out_T_1567) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_66, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[946], _out_rofireMux_T_270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[945], _out_rofireMux_T_270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[944], _out_rofireMux_T_270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[943], _out_rofireMux_T_270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[942], _out_rofireMux_T_270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[941], _out_rofireMux_T_270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[940], _out_rofireMux_T_270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[939], _out_rofireMux_T_270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_271 = eq(_out_T_1567, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_272 = or(out_rofireMux_out_66, _out_rofireMux_T_271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_67 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_273 = and(_out_rofireMux_T_260, out_backSel_3_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_274 = and(_out_rofireMux_T_273, _out_T_1479) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_67, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[600], _out_rofireMux_T_274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[599], _out_rofireMux_T_274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[598], _out_rofireMux_T_274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[597], _out_rofireMux_T_274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[596], _out_rofireMux_T_274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[595], _out_rofireMux_T_274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[594], _out_rofireMux_T_274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[593], _out_rofireMux_T_274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_275 = eq(_out_T_1479, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_276 = or(out_rofireMux_out_67, _out_rofireMux_T_275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_68 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_277 = and(_out_rofireMux_T_260, out_backSel_4_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_278 = and(_out_rofireMux_T_277, _out_T_1401) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_68, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[311], _out_rofireMux_T_278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[310], _out_rofireMux_T_278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[309], _out_rofireMux_T_278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[308], _out_rofireMux_T_278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[307], _out_rofireMux_T_278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[306], _out_rofireMux_T_278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[305], _out_rofireMux_T_278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[304], _out_rofireMux_T_278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_279 = eq(_out_T_1401, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_280 = or(out_rofireMux_out_68, _out_rofireMux_T_279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_69 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_281 = and(_out_rofireMux_T_260, out_backSel_5_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_282 = and(_out_rofireMux_T_281, _out_T_1363) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_69, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[159], _out_rofireMux_T_282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[158], _out_rofireMux_T_282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[157], _out_rofireMux_T_282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[156], _out_rofireMux_T_282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[155], _out_rofireMux_T_282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[154], _out_rofireMux_T_282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[153], _out_rofireMux_T_282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[152], _out_rofireMux_T_282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_283 = eq(_out_T_1363, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_284 = or(out_rofireMux_out_69, _out_rofireMux_T_283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_70 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_285 = and(_out_rofireMux_T_260, out_backSel_6_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_286 = and(_out_rofireMux_T_285, _out_T_1595) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_70, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1058], _out_rofireMux_T_286 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1057], _out_rofireMux_T_286 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1056], _out_rofireMux_T_286 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1055], _out_rofireMux_T_286 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1054], _out_rofireMux_T_286 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1053], _out_rofireMux_T_286 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1052], _out_rofireMux_T_286 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1051], _out_rofireMux_T_286 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_287 = eq(_out_T_1595, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_288 = or(out_rofireMux_out_70, _out_rofireMux_T_287) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_71 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_289 = and(_out_rofireMux_T_260, out_backSel_7_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_290 = and(_out_rofireMux_T_289, _out_T_1543) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_71, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[850], _out_rofireMux_T_290 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[849], _out_rofireMux_T_290 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[848], _out_rofireMux_T_290 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[847], _out_rofireMux_T_290 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[846], _out_rofireMux_T_290 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[845], _out_rofireMux_T_290 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[844], _out_rofireMux_T_290 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[843], _out_rofireMux_T_290 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_291 = eq(_out_T_1543, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_292 = or(out_rofireMux_out_71, _out_rofireMux_T_291) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_72 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_293 = and(_out_rofireMux_T_260, out_backSel_8_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_294 = and(_out_rofireMux_T_293, _out_T_1465) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_72, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[544], _out_rofireMux_T_294 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[543], _out_rofireMux_T_294 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[542], _out_rofireMux_T_294 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[541], _out_rofireMux_T_294 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[540], _out_rofireMux_T_294 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[539], _out_rofireMux_T_294 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[538], _out_rofireMux_T_294 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[537], _out_rofireMux_T_294 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_295 = eq(_out_T_1465, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_296 = or(out_rofireMux_out_72, _out_rofireMux_T_295) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_73 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_297 = and(_out_rofireMux_T_260, out_backSel_9_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_298 = and(_out_rofireMux_T_297, _out_T_1389) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_73, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[263], _out_rofireMux_T_298 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[262], _out_rofireMux_T_298 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[261], _out_rofireMux_T_298 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[260], _out_rofireMux_T_298 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[259], _out_rofireMux_T_298 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[258], _out_rofireMux_T_298 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[257], _out_rofireMux_T_298 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[256], _out_rofireMux_T_298 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_299 = eq(_out_T_1389, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_300 = or(out_rofireMux_out_73, _out_rofireMux_T_299) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_74 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_301 = and(_out_rofireMux_T_260, out_backSel_10_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_302 = and(_out_rofireMux_T_301, _out_T_1447) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_74, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[478], _out_rofireMux_T_302 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[477], _out_rofireMux_T_302 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[476], _out_rofireMux_T_302 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[475], _out_rofireMux_T_302 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_303 = eq(_out_T_1447, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_304 = or(out_rofireMux_out_74, _out_rofireMux_T_303) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_75 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_305 = and(_out_rofireMux_T_260, out_backSel_11_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_306 = and(_out_rofireMux_T_305, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_75, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_307 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_308 = or(out_rofireMux_out_75, _out_rofireMux_T_307) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_76 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_309 = and(_out_rofireMux_T_260, out_backSel_12_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_310 = and(_out_rofireMux_T_309, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_76, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_311 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_312 = or(out_rofireMux_out_76, _out_rofireMux_T_311) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_77 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_313 = and(_out_rofireMux_T_260, out_backSel_13_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_314 = and(_out_rofireMux_T_313, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_77, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_315 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_316 = or(out_rofireMux_out_77, _out_rofireMux_T_315) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_78 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_317 = and(_out_rofireMux_T_260, out_backSel_14_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_318 = and(_out_rofireMux_T_317, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_78, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_319 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_320 = or(out_rofireMux_out_78, _out_rofireMux_T_319) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_79 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_321 = and(_out_rofireMux_T_260, out_backSel_15_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_322 = and(_out_rofireMux_T_321, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_79, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_323 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_324 = or(out_rofireMux_out_79, _out_rofireMux_T_323) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_80 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_325 = and(_out_rofireMux_T_260, out_backSel_16_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_326 = and(_out_rofireMux_T_325, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_80, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_327 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_328 = or(out_rofireMux_out_80, _out_rofireMux_T_327) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_81 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_329 = and(_out_rofireMux_T_260, out_backSel_17_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_330 = and(_out_rofireMux_T_329, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_81, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_331 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_332 = or(out_rofireMux_out_81, _out_rofireMux_T_331) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_82 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_333 = and(_out_rofireMux_T_260, out_backSel_18_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_334 = and(_out_rofireMux_T_333, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_82, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_335 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_336 = or(out_rofireMux_out_82, _out_rofireMux_T_335) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_83 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_337 = and(_out_rofireMux_T_260, out_backSel_19_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_338 = and(_out_rofireMux_T_337, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_83, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_339 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_340 = or(out_rofireMux_out_83, _out_rofireMux_T_339) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_84 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_341 = and(_out_rofireMux_T_260, out_backSel_20_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_342 = and(_out_rofireMux_T_341, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_84, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_343 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_344 = or(out_rofireMux_out_84, _out_rofireMux_T_343) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_85 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_345 = and(_out_rofireMux_T_260, out_backSel_21_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_346 = and(_out_rofireMux_T_345, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_85, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_347 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_348 = or(out_rofireMux_out_85, _out_rofireMux_T_347) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_86 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_349 = and(_out_rofireMux_T_260, out_backSel_22_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_350 = and(_out_rofireMux_T_349, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_86, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_351 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_352 = or(out_rofireMux_out_86, _out_rofireMux_T_351) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_87 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_353 = and(_out_rofireMux_T_260, out_backSel_23_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_354 = and(_out_rofireMux_T_353, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_87, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_355 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_356 = or(out_rofireMux_out_87, _out_rofireMux_T_355) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_88 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_357 = and(_out_rofireMux_T_260, out_backSel_24_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_358 = and(_out_rofireMux_T_357, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_88, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_359 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_360 = or(out_rofireMux_out_88, _out_rofireMux_T_359) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_89 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_361 = and(_out_rofireMux_T_260, out_backSel_25_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_362 = and(_out_rofireMux_T_361, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_89, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_363 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_364 = or(out_rofireMux_out_89, _out_rofireMux_T_363) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_90 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_365 = and(_out_rofireMux_T_260, out_backSel_26_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_366 = and(_out_rofireMux_T_365, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_90, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_367 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_368 = or(out_rofireMux_out_90, _out_rofireMux_T_367) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_91 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_369 = and(_out_rofireMux_T_260, out_backSel_27_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_370 = and(_out_rofireMux_T_369, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_91, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_371 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_372 = or(out_rofireMux_out_91, _out_rofireMux_T_371) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_92 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_373 = and(_out_rofireMux_T_260, out_backSel_28_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_374 = and(_out_rofireMux_T_373, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_92, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_375 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_376 = or(out_rofireMux_out_92, _out_rofireMux_T_375) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_93 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_377 = and(_out_rofireMux_T_260, out_backSel_29_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_378 = and(_out_rofireMux_T_377, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_93, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_379 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_380 = or(out_rofireMux_out_93, _out_rofireMux_T_379) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_94 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_381 = and(_out_rofireMux_T_260, out_backSel_30_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_382 = and(_out_rofireMux_T_381, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_94, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_383 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_384 = or(out_rofireMux_out_94, _out_rofireMux_T_383) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_95 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_385 = and(_out_rofireMux_T_260, out_backSel_31_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_386 = and(_out_rofireMux_T_385, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_95, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_387 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_388 = or(out_rofireMux_out_95, _out_rofireMux_T_387) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_96 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_389 = and(_out_rofireMux_T_260, out_backSel_32_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_390 = and(_out_rofireMux_T_389, _out_T_1461) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_96, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[528], _out_rofireMux_T_390 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[527], _out_rofireMux_T_390 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_391 = eq(_out_T_1461, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_392 = or(out_rofireMux_out_96, _out_rofireMux_T_391) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_97 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_393 = and(_out_rofireMux_T_260, out_backSel_33_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_394 = and(_out_rofireMux_T_393, _out_T_1411) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_97, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[345], _out_rofireMux_T_394 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[344], _out_rofireMux_T_394 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_395 = eq(_out_T_1411, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_396 = or(out_rofireMux_out_97, _out_rofireMux_T_395) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_98 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_397 = and(_out_rofireMux_T_260, out_backSel_34_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_398 = and(_out_rofireMux_T_397, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_98, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_399 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_400 = or(out_rofireMux_out_98, _out_rofireMux_T_399) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_99 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_401 = and(_out_rofireMux_T_260, out_backSel_35_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_402 = and(_out_rofireMux_T_401, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_99, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_403 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_404 = or(out_rofireMux_out_99, _out_rofireMux_T_403) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_100 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_405 = and(_out_rofireMux_T_260, out_backSel_36_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_406 = and(_out_rofireMux_T_405, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_100, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_407 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_408 = or(out_rofireMux_out_100, _out_rofireMux_T_407) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_101 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_409 = and(_out_rofireMux_T_260, out_backSel_37_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_410 = and(_out_rofireMux_T_409, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_101, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_411 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_412 = or(out_rofireMux_out_101, _out_rofireMux_T_411) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_102 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_413 = and(_out_rofireMux_T_260, out_backSel_38_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_414 = and(_out_rofireMux_T_413, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_102, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_415 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_416 = or(out_rofireMux_out_102, _out_rofireMux_T_415) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_103 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_417 = and(_out_rofireMux_T_260, out_backSel_39_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_418 = and(_out_rofireMux_T_417, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_103, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_419 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_420 = or(out_rofireMux_out_103, _out_rofireMux_T_419) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_104 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_421 = and(_out_rofireMux_T_260, out_backSel_40_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_422 = and(_out_rofireMux_T_421, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_104, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_423 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_424 = or(out_rofireMux_out_104, _out_rofireMux_T_423) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_105 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_425 = and(_out_rofireMux_T_260, out_backSel_41_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_426 = and(_out_rofireMux_T_425, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_105, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_427 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_428 = or(out_rofireMux_out_105, _out_rofireMux_T_427) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_106 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_429 = and(_out_rofireMux_T_260, out_backSel_42_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_430 = and(_out_rofireMux_T_429, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_106, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_431 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_432 = or(out_rofireMux_out_106, _out_rofireMux_T_431) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_107 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_433 = and(_out_rofireMux_T_260, out_backSel_43_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_434 = and(_out_rofireMux_T_433, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_107, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_435 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_436 = or(out_rofireMux_out_107, _out_rofireMux_T_435) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_108 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_437 = and(_out_rofireMux_T_260, out_backSel_44_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_438 = and(_out_rofireMux_T_437, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_108, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_439 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_440 = or(out_rofireMux_out_108, _out_rofireMux_T_439) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_109 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_441 = and(_out_rofireMux_T_260, out_backSel_45_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_442 = and(_out_rofireMux_T_441, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_109, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_443 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_444 = or(out_rofireMux_out_109, _out_rofireMux_T_443) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_110 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_445 = and(_out_rofireMux_T_260, out_backSel_46_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_446 = and(_out_rofireMux_T_445, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_110, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_447 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_448 = or(out_rofireMux_out_110, _out_rofireMux_T_447) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_111 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_449 = and(_out_rofireMux_T_260, out_backSel_47_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_450 = and(_out_rofireMux_T_449, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_111, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_451 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_452 = or(out_rofireMux_out_111, _out_rofireMux_T_451) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_112 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_453 = and(_out_rofireMux_T_260, out_backSel_48_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_454 = and(_out_rofireMux_T_453, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_112, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_455 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_456 = or(out_rofireMux_out_112, _out_rofireMux_T_455) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_113 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_457 = and(_out_rofireMux_T_260, out_backSel_49_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_458 = and(_out_rofireMux_T_457, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_113, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_459 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_460 = or(out_rofireMux_out_113, _out_rofireMux_T_459) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_114 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_461 = and(_out_rofireMux_T_260, out_backSel_50_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_462 = and(_out_rofireMux_T_461, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_114, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_463 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_464 = or(out_rofireMux_out_114, _out_rofireMux_T_463) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_115 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_465 = and(_out_rofireMux_T_260, out_backSel_51_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_466 = and(_out_rofireMux_T_465, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_115, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_467 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_468 = or(out_rofireMux_out_115, _out_rofireMux_T_467) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_116 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_469 = and(_out_rofireMux_T_260, out_backSel_52_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_470 = and(_out_rofireMux_T_469, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_116, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_471 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_472 = or(out_rofireMux_out_116, _out_rofireMux_T_471) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_117 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_473 = and(_out_rofireMux_T_260, out_backSel_53_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_474 = and(_out_rofireMux_T_473, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_117, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_475 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_476 = or(out_rofireMux_out_117, _out_rofireMux_T_475) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_118 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_477 = and(_out_rofireMux_T_260, out_backSel_54_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_478 = and(_out_rofireMux_T_477, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_118, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_479 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_480 = or(out_rofireMux_out_118, _out_rofireMux_T_479) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_119 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_481 = and(_out_rofireMux_T_260, out_backSel_55_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_482 = and(_out_rofireMux_T_481, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_119, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_483 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_484 = or(out_rofireMux_out_119, _out_rofireMux_T_483) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_120 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_485 = and(_out_rofireMux_T_260, out_backSel_56_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_486 = and(_out_rofireMux_T_485, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_120, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_487 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_488 = or(out_rofireMux_out_120, _out_rofireMux_T_487) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_121 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_489 = and(_out_rofireMux_T_260, out_backSel_57_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_490 = and(_out_rofireMux_T_489, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_121, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_491 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_492 = or(out_rofireMux_out_121, _out_rofireMux_T_491) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_122 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_493 = and(_out_rofireMux_T_260, out_backSel_58_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_494 = and(_out_rofireMux_T_493, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_122, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_495 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_496 = or(out_rofireMux_out_122, _out_rofireMux_T_495) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_123 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_497 = and(_out_rofireMux_T_260, out_backSel_59_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_498 = and(_out_rofireMux_T_497, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_123, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_499 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_500 = or(out_rofireMux_out_123, _out_rofireMux_T_499) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_124 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_501 = and(_out_rofireMux_T_260, out_backSel_60_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_502 = and(_out_rofireMux_T_501, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_124, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_503 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_504 = or(out_rofireMux_out_124, _out_rofireMux_T_503) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_125 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_505 = and(_out_rofireMux_T_260, out_backSel_61_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_506 = and(_out_rofireMux_T_505, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_125, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_507 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_508 = or(out_rofireMux_out_125, _out_rofireMux_T_507) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_126 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_509 = and(_out_rofireMux_T_260, out_backSel_62_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_510 = and(_out_rofireMux_T_509, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_126, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_511 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_512 = or(out_rofireMux_out_126, _out_rofireMux_T_511) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_127 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_513 = and(_out_rofireMux_T_260, out_backSel_63_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_514 = and(_out_rofireMux_T_513, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_127, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_515 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_516 = or(out_rofireMux_out_127, _out_rofireMux_T_515) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_128 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_517 = and(_out_rofireMux_T_260, out_backSel_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_518 = and(_out_rofireMux_T_517, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_128, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_519 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_520 = or(out_rofireMux_out_128, _out_rofireMux_T_519) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_129 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_521 = and(_out_rofireMux_T_260, out_backSel_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_522 = and(_out_rofireMux_T_521, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_129, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_523 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_524 = or(out_rofireMux_out_129, _out_rofireMux_T_523) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_130 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_525 = and(_out_rofireMux_T_260, out_backSel_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_526 = and(_out_rofireMux_T_525, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_130, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_527 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_528 = or(out_rofireMux_out_130, _out_rofireMux_T_527) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_131 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_529 = and(_out_rofireMux_T_260, out_backSel_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_530 = and(_out_rofireMux_T_529, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_131, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_531 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_532 = or(out_rofireMux_out_131, _out_rofireMux_T_531) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_132 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_533 = and(_out_rofireMux_T_260, out_backSel_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_534 = and(_out_rofireMux_T_533, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_132, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_535 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_536 = or(out_rofireMux_out_132, _out_rofireMux_T_535) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_133 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_537 = and(_out_rofireMux_T_260, out_backSel_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_538 = and(_out_rofireMux_T_537, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_133, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_539 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_540 = or(out_rofireMux_out_133, _out_rofireMux_T_539) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_134 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_541 = and(_out_rofireMux_T_260, out_backSel_70) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_542 = and(_out_rofireMux_T_541, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_134, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_543 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_544 = or(out_rofireMux_out_134, _out_rofireMux_T_543) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_135 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_545 = and(_out_rofireMux_T_260, out_backSel_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_546 = and(_out_rofireMux_T_545, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_135, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_547 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_548 = or(out_rofireMux_out_135, _out_rofireMux_T_547) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_136 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_549 = and(_out_rofireMux_T_260, out_backSel_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_550 = and(_out_rofireMux_T_549, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_136, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_551 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_552 = or(out_rofireMux_out_136, _out_rofireMux_T_551) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_137 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_553 = and(_out_rofireMux_T_260, out_backSel_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_554 = and(_out_rofireMux_T_553, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_137, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_555 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_556 = or(out_rofireMux_out_137, _out_rofireMux_T_555) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_138 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_557 = and(_out_rofireMux_T_260, out_backSel_74) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_558 = and(_out_rofireMux_T_557, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_138, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_559 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_560 = or(out_rofireMux_out_138, _out_rofireMux_T_559) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_139 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_561 = and(_out_rofireMux_T_260, out_backSel_75) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_562 = and(_out_rofireMux_T_561, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_139, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_563 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_564 = or(out_rofireMux_out_139, _out_rofireMux_T_563) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_140 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_565 = and(_out_rofireMux_T_260, out_backSel_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_566 = and(_out_rofireMux_T_565, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_140, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_567 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_568 = or(out_rofireMux_out_140, _out_rofireMux_T_567) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_141 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_569 = and(_out_rofireMux_T_260, out_backSel_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_570 = and(_out_rofireMux_T_569, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_141, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_571 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_572 = or(out_rofireMux_out_141, _out_rofireMux_T_571) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_142 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_573 = and(_out_rofireMux_T_260, out_backSel_78) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_574 = and(_out_rofireMux_T_573, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_142, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_575 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_576 = or(out_rofireMux_out_142, _out_rofireMux_T_575) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_143 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_577 = and(_out_rofireMux_T_260, out_backSel_79) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_578 = and(_out_rofireMux_T_577, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_143, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_579 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_580 = or(out_rofireMux_out_143, _out_rofireMux_T_579) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_144 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_581 = and(_out_rofireMux_T_260, out_backSel_80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_582 = and(_out_rofireMux_T_581, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_144, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_583 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_584 = or(out_rofireMux_out_144, _out_rofireMux_T_583) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_145 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_585 = and(_out_rofireMux_T_260, out_backSel_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_586 = and(_out_rofireMux_T_585, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_145, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_587 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_588 = or(out_rofireMux_out_145, _out_rofireMux_T_587) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_146 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_589 = and(_out_rofireMux_T_260, out_backSel_82) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_590 = and(_out_rofireMux_T_589, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_146, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_591 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_592 = or(out_rofireMux_out_146, _out_rofireMux_T_591) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_147 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_593 = and(_out_rofireMux_T_260, out_backSel_83) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_594 = and(_out_rofireMux_T_593, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_147, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_595 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_596 = or(out_rofireMux_out_147, _out_rofireMux_T_595) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_148 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_597 = and(_out_rofireMux_T_260, out_backSel_84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_598 = and(_out_rofireMux_T_597, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_148, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_599 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_600 = or(out_rofireMux_out_148, _out_rofireMux_T_599) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_149 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_601 = and(_out_rofireMux_T_260, out_backSel_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_602 = and(_out_rofireMux_T_601, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_149, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_603 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_604 = or(out_rofireMux_out_149, _out_rofireMux_T_603) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_150 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_605 = and(_out_rofireMux_T_260, out_backSel_86) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_606 = and(_out_rofireMux_T_605, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_150, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_607 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_608 = or(out_rofireMux_out_150, _out_rofireMux_T_607) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_151 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_609 = and(_out_rofireMux_T_260, out_backSel_87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_610 = and(_out_rofireMux_T_609, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_151, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_611 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_612 = or(out_rofireMux_out_151, _out_rofireMux_T_611) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_152 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_613 = and(_out_rofireMux_T_260, out_backSel_88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_614 = and(_out_rofireMux_T_613, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_152, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_615 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_616 = or(out_rofireMux_out_152, _out_rofireMux_T_615) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_153 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_617 = and(_out_rofireMux_T_260, out_backSel_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_618 = and(_out_rofireMux_T_617, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_153, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_619 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_620 = or(out_rofireMux_out_153, _out_rofireMux_T_619) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_154 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_621 = and(_out_rofireMux_T_260, out_backSel_90) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_622 = and(_out_rofireMux_T_621, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_154, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_623 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_624 = or(out_rofireMux_out_154, _out_rofireMux_T_623) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_155 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_625 = and(_out_rofireMux_T_260, out_backSel_91) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_626 = and(_out_rofireMux_T_625, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_155, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_627 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_628 = or(out_rofireMux_out_155, _out_rofireMux_T_627) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_156 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_629 = and(_out_rofireMux_T_260, out_backSel_92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_630 = and(_out_rofireMux_T_629, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_156, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_631 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_632 = or(out_rofireMux_out_156, _out_rofireMux_T_631) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_157 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_633 = and(_out_rofireMux_T_260, out_backSel_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_634 = and(_out_rofireMux_T_633, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_157, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_635 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_636 = or(out_rofireMux_out_157, _out_rofireMux_T_635) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_158 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_637 = and(_out_rofireMux_T_260, out_backSel_94) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_638 = and(_out_rofireMux_T_637, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_158, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_639 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_640 = or(out_rofireMux_out_158, _out_rofireMux_T_639) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_159 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_641 = and(_out_rofireMux_T_260, out_backSel_95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_642 = and(_out_rofireMux_T_641, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_159, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_643 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_644 = or(out_rofireMux_out_159, _out_rofireMux_T_643) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_160 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_645 = and(_out_rofireMux_T_260, out_backSel_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_646 = and(_out_rofireMux_T_645, _out_T_1435) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_160, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[434], _out_rofireMux_T_646 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_647 = eq(_out_T_1435, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_648 = or(out_rofireMux_out_160, _out_rofireMux_T_647) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_161 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_649 = and(_out_rofireMux_T_260, out_backSel_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_650 = and(_out_rofireMux_T_649, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_161, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_651 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_652 = or(out_rofireMux_out_161, _out_rofireMux_T_651) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_162 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_653 = and(_out_rofireMux_T_260, out_backSel_98) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_654 = and(_out_rofireMux_T_653, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_162, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_655 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_656 = or(out_rofireMux_out_162, _out_rofireMux_T_655) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_163 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_657 = and(_out_rofireMux_T_260, out_backSel_99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_658 = and(_out_rofireMux_T_657, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_163, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_659 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_660 = or(out_rofireMux_out_163, _out_rofireMux_T_659) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_164 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_661 = and(_out_rofireMux_T_260, out_backSel_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_662 = and(_out_rofireMux_T_661, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_164, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_663 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_664 = or(out_rofireMux_out_164, _out_rofireMux_T_663) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_165 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_665 = and(_out_rofireMux_T_260, out_backSel_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_666 = and(_out_rofireMux_T_665, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_165, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_667 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_668 = or(out_rofireMux_out_165, _out_rofireMux_T_667) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_166 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_669 = and(_out_rofireMux_T_260, out_backSel_102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_670 = and(_out_rofireMux_T_669, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_166, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_671 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_672 = or(out_rofireMux_out_166, _out_rofireMux_T_671) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_167 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_673 = and(_out_rofireMux_T_260, out_backSel_103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_674 = and(_out_rofireMux_T_673, _out_T_1501) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_167, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[682], _out_rofireMux_T_674 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[681], _out_rofireMux_T_674 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_675 = eq(_out_T_1501, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_676 = or(out_rofireMux_out_167, _out_rofireMux_T_675) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_168 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_677 = and(_out_rofireMux_T_260, out_backSel_104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_678 = and(_out_rofireMux_T_677, _out_T_1561) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_168, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[922], _out_rofireMux_T_678 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[921], _out_rofireMux_T_678 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[920], _out_rofireMux_T_678 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[919], _out_rofireMux_T_678 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[918], _out_rofireMux_T_678 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[917], _out_rofireMux_T_678 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[916], _out_rofireMux_T_678 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[915], _out_rofireMux_T_678 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_679 = eq(_out_T_1561, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_680 = or(out_rofireMux_out_168, _out_rofireMux_T_679) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_169 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_681 = and(_out_rofireMux_T_260, out_backSel_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_682 = and(_out_rofireMux_T_681, _out_T_1455) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_169, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[510], _out_rofireMux_T_682 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[509], _out_rofireMux_T_682 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[508], _out_rofireMux_T_682 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[507], _out_rofireMux_T_682 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[506], _out_rofireMux_T_682 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[505], _out_rofireMux_T_682 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[504], _out_rofireMux_T_682 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[503], _out_rofireMux_T_682 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_683 = eq(_out_T_1455, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_684 = or(out_rofireMux_out_169, _out_rofireMux_T_683) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_170 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_685 = and(_out_rofireMux_T_260, out_backSel_106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_686 = and(_out_rofireMux_T_685, _out_T_1371) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_170, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[191], _out_rofireMux_T_686 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[190], _out_rofireMux_T_686 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[189], _out_rofireMux_T_686 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[188], _out_rofireMux_T_686 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[187], _out_rofireMux_T_686 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[186], _out_rofireMux_T_686 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[185], _out_rofireMux_T_686 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[184], _out_rofireMux_T_686 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_687 = eq(_out_T_1371, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_688 = or(out_rofireMux_out_170, _out_rofireMux_T_687) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_171 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_689 = and(_out_rofireMux_T_260, out_backSel_107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_690 = and(_out_rofireMux_T_689, _out_T_1599) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_171, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1074], _out_rofireMux_T_690 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1073], _out_rofireMux_T_690 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1072], _out_rofireMux_T_690 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1071], _out_rofireMux_T_690 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1070], _out_rofireMux_T_690 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1069], _out_rofireMux_T_690 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1068], _out_rofireMux_T_690 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1067], _out_rofireMux_T_690 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_691 = eq(_out_T_1599, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_692 = or(out_rofireMux_out_171, _out_rofireMux_T_691) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_172 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_693 = and(_out_rofireMux_T_260, out_backSel_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_694 = and(_out_rofireMux_T_693, _out_T_1511) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_172, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[722], _out_rofireMux_T_694 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[721], _out_rofireMux_T_694 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[720], _out_rofireMux_T_694 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[719], _out_rofireMux_T_694 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[718], _out_rofireMux_T_694 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[717], _out_rofireMux_T_694 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[716], _out_rofireMux_T_694 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[715], _out_rofireMux_T_694 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_695 = eq(_out_T_1511, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_696 = or(out_rofireMux_out_172, _out_rofireMux_T_695) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_173 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_697 = and(_out_rofireMux_T_260, out_backSel_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_698 = and(_out_rofireMux_T_697, _out_T_1437) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_173, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[442], _out_rofireMux_T_698 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[441], _out_rofireMux_T_698 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[440], _out_rofireMux_T_698 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[439], _out_rofireMux_T_698 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[438], _out_rofireMux_T_698 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[437], _out_rofireMux_T_698 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[436], _out_rofireMux_T_698 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[435], _out_rofireMux_T_698 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_699 = eq(_out_T_1437, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_700 = or(out_rofireMux_out_173, _out_rofireMux_T_699) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_174 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_701 = and(_out_rofireMux_T_260, out_backSel_110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_702 = and(_out_rofireMux_T_701, _out_T_1351) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_174, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[111], _out_rofireMux_T_702 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[110], _out_rofireMux_T_702 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[109], _out_rofireMux_T_702 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[108], _out_rofireMux_T_702 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[107], _out_rofireMux_T_702 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[106], _out_rofireMux_T_702 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[105], _out_rofireMux_T_702 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[104], _out_rofireMux_T_702 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_703 = eq(_out_T_1351, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_704 = or(out_rofireMux_out_174, _out_rofireMux_T_703) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_175 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_705 = and(_out_rofireMux_T_260, out_backSel_111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_706 = and(_out_rofireMux_T_705, _out_T_1617) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_175, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1146], _out_rofireMux_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1145], _out_rofireMux_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1144], _out_rofireMux_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1143], _out_rofireMux_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1142], _out_rofireMux_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1141], _out_rofireMux_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1140], _out_rofireMux_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1139], _out_rofireMux_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_707 = eq(_out_T_1617, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_708 = or(out_rofireMux_out_175, _out_rofireMux_T_707) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_176 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_709 = and(_out_rofireMux_T_260, out_backSel_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_710 = and(_out_rofireMux_T_709, _out_T_1535) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_176, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[818], _out_rofireMux_T_710 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[817], _out_rofireMux_T_710 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[816], _out_rofireMux_T_710 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[815], _out_rofireMux_T_710 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[814], _out_rofireMux_T_710 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[813], _out_rofireMux_T_710 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[812], _out_rofireMux_T_710 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[811], _out_rofireMux_T_710 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_711 = eq(_out_T_1535, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_712 = or(out_rofireMux_out_176, _out_rofireMux_T_711) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_177 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_713 = and(_out_rofireMux_T_260, out_backSel_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_714 = and(_out_rofireMux_T_713, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_177, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_715 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_716 = or(out_rofireMux_out_177, _out_rofireMux_T_715) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_178 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_717 = and(_out_rofireMux_T_260, out_backSel_114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_718 = and(_out_rofireMux_T_717, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_178, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_719 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_720 = or(out_rofireMux_out_178, _out_rofireMux_T_719) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_179 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_721 = and(_out_rofireMux_T_260, out_backSel_115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_722 = and(_out_rofireMux_T_721, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_179, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_723 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_724 = or(out_rofireMux_out_179, _out_rofireMux_T_723) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_180 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_725 = and(_out_rofireMux_T_260, out_backSel_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_726 = and(_out_rofireMux_T_725, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_180, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_727 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_728 = or(out_rofireMux_out_180, _out_rofireMux_T_727) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_181 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_729 = and(_out_rofireMux_T_260, out_backSel_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_730 = and(_out_rofireMux_T_729, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_181, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_731 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_732 = or(out_rofireMux_out_181, _out_rofireMux_T_731) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_182 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_733 = and(_out_rofireMux_T_260, out_backSel_118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_734 = and(_out_rofireMux_T_733, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_182, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_735 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_736 = or(out_rofireMux_out_182, _out_rofireMux_T_735) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_183 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_737 = and(_out_rofireMux_T_260, out_backSel_119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_738 = and(_out_rofireMux_T_737, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_183, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_739 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_740 = or(out_rofireMux_out_183, _out_rofireMux_T_739) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_184 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_741 = and(_out_rofireMux_T_260, out_backSel_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_742 = and(_out_rofireMux_T_741, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_184, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_743 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_744 = or(out_rofireMux_out_184, _out_rofireMux_T_743) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_185 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_745 = and(_out_rofireMux_T_260, out_backSel_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_746 = and(_out_rofireMux_T_745, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_185, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_747 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_748 = or(out_rofireMux_out_185, _out_rofireMux_T_747) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_186 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_749 = and(_out_rofireMux_T_260, out_backSel_122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_750 = and(_out_rofireMux_T_749, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_186, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_751 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_752 = or(out_rofireMux_out_186, _out_rofireMux_T_751) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_187 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_753 = and(_out_rofireMux_T_260, out_backSel_123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_754 = and(_out_rofireMux_T_753, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_187, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_755 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_756 = or(out_rofireMux_out_187, _out_rofireMux_T_755) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_188 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_757 = and(_out_rofireMux_T_260, out_backSel_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_758 = and(_out_rofireMux_T_757, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_188, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_759 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_760 = or(out_rofireMux_out_188, _out_rofireMux_T_759) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_189 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_761 = and(_out_rofireMux_T_260, out_backSel_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_762 = and(_out_rofireMux_T_761, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_189, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_763 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_764 = or(out_rofireMux_out_189, _out_rofireMux_T_763) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_190 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_765 = and(_out_rofireMux_T_260, out_backSel_126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_766 = and(_out_rofireMux_T_765, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_190, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_767 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_768 = or(out_rofireMux_out_190, _out_rofireMux_T_767) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_191 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_769 = and(_out_rofireMux_T_260, out_backSel_127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_770 = and(_out_rofireMux_T_769, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_191, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_771 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_772 = or(out_rofireMux_out_191, _out_rofireMux_T_771) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_192 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_773 = and(_out_rofireMux_T_260, out_backSel_128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_774 = and(_out_rofireMux_T_773, _out_T_1451) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_192, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[494], _out_rofireMux_T_774 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[493], _out_rofireMux_T_774 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[492], _out_rofireMux_T_774 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[491], _out_rofireMux_T_774 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[490], _out_rofireMux_T_774 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[489], _out_rofireMux_T_774 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[488], _out_rofireMux_T_774 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[487], _out_rofireMux_T_774 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_775 = eq(_out_T_1451, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_776 = or(out_rofireMux_out_192, _out_rofireMux_T_775) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_193 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_777 = and(_out_rofireMux_T_260, out_backSel_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_778 = and(_out_rofireMux_T_777, _out_T_1443) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_193, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[466], _out_rofireMux_T_778 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[465], _out_rofireMux_T_778 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[464], _out_rofireMux_T_778 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[463], _out_rofireMux_T_778 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[462], _out_rofireMux_T_778 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[461], _out_rofireMux_T_778 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[460], _out_rofireMux_T_778 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[459], _out_rofireMux_T_778 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_779 = eq(_out_T_1443, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_780 = or(out_rofireMux_out_193, _out_rofireMux_T_779) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_194 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_781 = and(_out_rofireMux_T_260, out_backSel_130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_782 = and(_out_rofireMux_T_781, _out_T_1517) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_194, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[746], _out_rofireMux_T_782 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[745], _out_rofireMux_T_782 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[744], _out_rofireMux_T_782 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[743], _out_rofireMux_T_782 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[742], _out_rofireMux_T_782 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[741], _out_rofireMux_T_782 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[740], _out_rofireMux_T_782 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[739], _out_rofireMux_T_782 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_783 = eq(_out_T_1517, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_784 = or(out_rofireMux_out_194, _out_rofireMux_T_783) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_195 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_785 = and(_out_rofireMux_T_260, out_backSel_131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_786 = and(_out_rofireMux_T_785, _out_T_1609) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_195, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1114], _out_rofireMux_T_786 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1113], _out_rofireMux_T_786 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1112], _out_rofireMux_T_786 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1111], _out_rofireMux_T_786 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1110], _out_rofireMux_T_786 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1109], _out_rofireMux_T_786 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1108], _out_rofireMux_T_786 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1107], _out_rofireMux_T_786 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_787 = eq(_out_T_1609, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_788 = or(out_rofireMux_out_195, _out_rofireMux_T_787) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_196 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_789 = and(_out_rofireMux_T_260, out_backSel_132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_790 = and(_out_rofireMux_T_789, _out_T_1383) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_196, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[239], _out_rofireMux_T_790 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[238], _out_rofireMux_T_790 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[237], _out_rofireMux_T_790 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[236], _out_rofireMux_T_790 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[235], _out_rofireMux_T_790 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[234], _out_rofireMux_T_790 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[233], _out_rofireMux_T_790 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[232], _out_rofireMux_T_790 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_791 = eq(_out_T_1383, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_792 = or(out_rofireMux_out_196, _out_rofireMux_T_791) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_197 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_793 = and(_out_rofireMux_T_260, out_backSel_133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_794 = and(_out_rofireMux_T_793, _out_T_1385) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_197, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[247], _out_rofireMux_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[246], _out_rofireMux_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[245], _out_rofireMux_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[244], _out_rofireMux_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[243], _out_rofireMux_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[242], _out_rofireMux_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[241], _out_rofireMux_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[240], _out_rofireMux_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_795 = eq(_out_T_1385, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_796 = or(out_rofireMux_out_197, _out_rofireMux_T_795) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_198 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_797 = and(_out_rofireMux_T_260, out_backSel_134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_798 = and(_out_rofireMux_T_797, _out_T_1445) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_198, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[474], _out_rofireMux_T_798 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[473], _out_rofireMux_T_798 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[472], _out_rofireMux_T_798 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[471], _out_rofireMux_T_798 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[470], _out_rofireMux_T_798 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[469], _out_rofireMux_T_798 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[468], _out_rofireMux_T_798 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[467], _out_rofireMux_T_798 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_799 = eq(_out_T_1445, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_800 = or(out_rofireMux_out_198, _out_rofireMux_T_799) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_199 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_801 = and(_out_rofireMux_T_260, out_backSel_135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_802 = and(_out_rofireMux_T_801, _out_T_1521) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_199, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[762], _out_rofireMux_T_802 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[761], _out_rofireMux_T_802 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[760], _out_rofireMux_T_802 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[759], _out_rofireMux_T_802 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[758], _out_rofireMux_T_802 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[757], _out_rofireMux_T_802 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[756], _out_rofireMux_T_802 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[755], _out_rofireMux_T_802 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_803 = eq(_out_T_1521, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_804 = or(out_rofireMux_out_199, _out_rofireMux_T_803) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_200 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_805 = and(_out_rofireMux_T_260, out_backSel_136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_806 = and(_out_rofireMux_T_805, _out_T_1601) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_200, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1082], _out_rofireMux_T_806 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1081], _out_rofireMux_T_806 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1080], _out_rofireMux_T_806 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1079], _out_rofireMux_T_806 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1078], _out_rofireMux_T_806 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1077], _out_rofireMux_T_806 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1076], _out_rofireMux_T_806 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1075], _out_rofireMux_T_806 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_807 = eq(_out_T_1601, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_808 = or(out_rofireMux_out_200, _out_rofireMux_T_807) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_201 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_809 = and(_out_rofireMux_T_260, out_backSel_137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_810 = and(_out_rofireMux_T_809, _out_T_1407) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_201, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[335], _out_rofireMux_T_810 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[334], _out_rofireMux_T_810 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[333], _out_rofireMux_T_810 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[332], _out_rofireMux_T_810 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[331], _out_rofireMux_T_810 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[330], _out_rofireMux_T_810 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[329], _out_rofireMux_T_810 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[328], _out_rofireMux_T_810 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_811 = eq(_out_T_1407, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_812 = or(out_rofireMux_out_201, _out_rofireMux_T_811) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_202 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_813 = and(_out_rofireMux_T_260, out_backSel_138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_814 = and(_out_rofireMux_T_813, _out_T_1325) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_202, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[7], _out_rofireMux_T_814 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[6], _out_rofireMux_T_814 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[5], _out_rofireMux_T_814 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[4], _out_rofireMux_T_814 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[3], _out_rofireMux_T_814 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[2], _out_rofireMux_T_814 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1], _out_rofireMux_T_814 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[0], _out_rofireMux_T_814 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_815 = eq(_out_T_1325, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_816 = or(out_rofireMux_out_202, _out_rofireMux_T_815) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_203 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_817 = and(_out_rofireMux_T_260, out_backSel_139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_818 = and(_out_rofireMux_T_817, _out_T_1575) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_203, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[978], _out_rofireMux_T_818 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[977], _out_rofireMux_T_818 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[976], _out_rofireMux_T_818 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[975], _out_rofireMux_T_818 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[974], _out_rofireMux_T_818 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[973], _out_rofireMux_T_818 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[972], _out_rofireMux_T_818 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[971], _out_rofireMux_T_818 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_819 = eq(_out_T_1575, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_820 = or(out_rofireMux_out_203, _out_rofireMux_T_819) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_204 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_821 = and(_out_rofireMux_T_260, out_backSel_140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_822 = and(_out_rofireMux_T_821, _out_T_1503) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_204, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[690], _out_rofireMux_T_822 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[689], _out_rofireMux_T_822 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[688], _out_rofireMux_T_822 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[687], _out_rofireMux_T_822 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[686], _out_rofireMux_T_822 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[685], _out_rofireMux_T_822 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[684], _out_rofireMux_T_822 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[683], _out_rofireMux_T_822 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_823 = eq(_out_T_1503, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_824 = or(out_rofireMux_out_204, _out_rofireMux_T_823) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_205 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_825 = and(_out_rofireMux_T_260, out_backSel_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_826 = and(_out_rofireMux_T_825, _out_T_1427) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_205, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[409], _out_rofireMux_T_826 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[408], _out_rofireMux_T_826 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[407], _out_rofireMux_T_826 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[406], _out_rofireMux_T_826 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[405], _out_rofireMux_T_826 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[404], _out_rofireMux_T_826 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[403], _out_rofireMux_T_826 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[402], _out_rofireMux_T_826 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_827 = eq(_out_T_1427, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_828 = or(out_rofireMux_out_205, _out_rofireMux_T_827) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_206 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_829 = and(_out_rofireMux_T_260, out_backSel_142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_830 = and(_out_rofireMux_T_829, _out_T_1339) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_206, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[63], _out_rofireMux_T_830 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[62], _out_rofireMux_T_830 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[61], _out_rofireMux_T_830 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[60], _out_rofireMux_T_830 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[59], _out_rofireMux_T_830 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[58], _out_rofireMux_T_830 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[57], _out_rofireMux_T_830 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[56], _out_rofireMux_T_830 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_831 = eq(_out_T_1339, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_832 = or(out_rofireMux_out_206, _out_rofireMux_T_831) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_207 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_833 = and(_out_rofireMux_T_260, out_backSel_143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_834 = and(_out_rofireMux_T_833, _out_T_1555) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_207, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[898], _out_rofireMux_T_834 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[897], _out_rofireMux_T_834 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[896], _out_rofireMux_T_834 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[895], _out_rofireMux_T_834 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[894], _out_rofireMux_T_834 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[893], _out_rofireMux_T_834 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[892], _out_rofireMux_T_834 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[891], _out_rofireMux_T_834 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_835 = eq(_out_T_1555, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_836 = or(out_rofireMux_out_207, _out_rofireMux_T_835) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_208 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_837 = and(_out_rofireMux_T_260, out_backSel_144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_838 = and(_out_rofireMux_T_837, _out_T_1481) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_208, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[608], _out_rofireMux_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[607], _out_rofireMux_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[606], _out_rofireMux_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[605], _out_rofireMux_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[604], _out_rofireMux_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[603], _out_rofireMux_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[602], _out_rofireMux_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[601], _out_rofireMux_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_839 = eq(_out_T_1481, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_840 = or(out_rofireMux_out_208, _out_rofireMux_T_839) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_209 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_841 = and(_out_rofireMux_T_260, out_backSel_145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_842 = and(_out_rofireMux_T_841, _out_T_1539) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_209, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[834], _out_rofireMux_T_842 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[833], _out_rofireMux_T_842 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[832], _out_rofireMux_T_842 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[831], _out_rofireMux_T_842 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[830], _out_rofireMux_T_842 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[829], _out_rofireMux_T_842 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[828], _out_rofireMux_T_842 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[827], _out_rofireMux_T_842 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_843 = eq(_out_T_1539, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_844 = or(out_rofireMux_out_209, _out_rofireMux_T_843) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_210 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_845 = and(_out_rofireMux_T_260, out_backSel_146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_846 = and(_out_rofireMux_T_845, _out_T_1587) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_210, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1026], _out_rofireMux_T_846 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1025], _out_rofireMux_T_846 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1024], _out_rofireMux_T_846 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1023], _out_rofireMux_T_846 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1022], _out_rofireMux_T_846 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1021], _out_rofireMux_T_846 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1020], _out_rofireMux_T_846 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1019], _out_rofireMux_T_846 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_847 = eq(_out_T_1587, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_848 = or(out_rofireMux_out_210, _out_rofireMux_T_847) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_211 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_849 = and(_out_rofireMux_T_260, out_backSel_147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_850 = and(_out_rofireMux_T_849, _out_T_1379) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_211, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[223], _out_rofireMux_T_850 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[222], _out_rofireMux_T_850 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[221], _out_rofireMux_T_850 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[220], _out_rofireMux_T_850 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[219], _out_rofireMux_T_850 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[218], _out_rofireMux_T_850 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[217], _out_rofireMux_T_850 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[216], _out_rofireMux_T_850 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_851 = eq(_out_T_1379, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_852 = or(out_rofireMux_out_211, _out_rofireMux_T_851) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_212 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_853 = and(_out_rofireMux_T_260, out_backSel_148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_854 = and(_out_rofireMux_T_853, _out_T_1463) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_212, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[536], _out_rofireMux_T_854 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[535], _out_rofireMux_T_854 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[534], _out_rofireMux_T_854 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[533], _out_rofireMux_T_854 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[532], _out_rofireMux_T_854 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[531], _out_rofireMux_T_854 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[530], _out_rofireMux_T_854 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[529], _out_rofireMux_T_854 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_855 = eq(_out_T_1463, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_856 = or(out_rofireMux_out_212, _out_rofireMux_T_855) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_213 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_857 = and(_out_rofireMux_T_260, out_backSel_149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_858 = and(_out_rofireMux_T_857, _out_T_1471) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_213, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[568], _out_rofireMux_T_858 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[567], _out_rofireMux_T_858 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[566], _out_rofireMux_T_858 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[565], _out_rofireMux_T_858 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[564], _out_rofireMux_T_858 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[563], _out_rofireMux_T_858 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[562], _out_rofireMux_T_858 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[561], _out_rofireMux_T_858 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_859 = eq(_out_T_1471, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_860 = or(out_rofireMux_out_213, _out_rofireMux_T_859) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_214 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_861 = and(_out_rofireMux_T_260, out_backSel_150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_862 = and(_out_rofireMux_T_861, _out_T_1541) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_214, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[842], _out_rofireMux_T_862 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[841], _out_rofireMux_T_862 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[840], _out_rofireMux_T_862 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[839], _out_rofireMux_T_862 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[838], _out_rofireMux_T_862 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[837], _out_rofireMux_T_862 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[836], _out_rofireMux_T_862 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[835], _out_rofireMux_T_862 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_863 = eq(_out_T_1541, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_864 = or(out_rofireMux_out_214, _out_rofireMux_T_863) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_215 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_865 = and(_out_rofireMux_T_260, out_backSel_151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_866 = and(_out_rofireMux_T_865, _out_T_1585) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_215, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1018], _out_rofireMux_T_866 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1017], _out_rofireMux_T_866 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1016], _out_rofireMux_T_866 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1015], _out_rofireMux_T_866 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1014], _out_rofireMux_T_866 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1013], _out_rofireMux_T_866 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1012], _out_rofireMux_T_866 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1011], _out_rofireMux_T_866 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_867 = eq(_out_T_1585, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_868 = or(out_rofireMux_out_215, _out_rofireMux_T_867) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_216 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_869 = and(_out_rofireMux_T_260, out_backSel_152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_870 = and(_out_rofireMux_T_869, _out_T_1359) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_216, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[143], _out_rofireMux_T_870 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[142], _out_rofireMux_T_870 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[141], _out_rofireMux_T_870 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[140], _out_rofireMux_T_870 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[139], _out_rofireMux_T_870 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[138], _out_rofireMux_T_870 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[137], _out_rofireMux_T_870 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[136], _out_rofireMux_T_870 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_871 = eq(_out_T_1359, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_872 = or(out_rofireMux_out_216, _out_rofireMux_T_871) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_217 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_873 = and(_out_rofireMux_T_260, out_backSel_153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_874 = and(_out_rofireMux_T_873, _out_T_1341) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_217, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[71], _out_rofireMux_T_874 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[70], _out_rofireMux_T_874 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[69], _out_rofireMux_T_874 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[68], _out_rofireMux_T_874 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[67], _out_rofireMux_T_874 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[66], _out_rofireMux_T_874 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[65], _out_rofireMux_T_874 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[64], _out_rofireMux_T_874 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_875 = eq(_out_T_1341, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_876 = or(out_rofireMux_out_217, _out_rofireMux_T_875) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_218 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_877 = and(_out_rofireMux_T_260, out_backSel_154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_878 = and(_out_rofireMux_T_877, _out_T_1551) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_218, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[882], _out_rofireMux_T_878 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[881], _out_rofireMux_T_878 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[880], _out_rofireMux_T_878 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[879], _out_rofireMux_T_878 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[878], _out_rofireMux_T_878 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[877], _out_rofireMux_T_878 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[876], _out_rofireMux_T_878 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[875], _out_rofireMux_T_878 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_879 = eq(_out_T_1551, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_880 = or(out_rofireMux_out_218, _out_rofireMux_T_879) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_219 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_881 = and(_out_rofireMux_T_260, out_backSel_155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_882 = and(_out_rofireMux_T_881, _out_T_1507) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_219, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[706], _out_rofireMux_T_882 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[705], _out_rofireMux_T_882 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[704], _out_rofireMux_T_882 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[703], _out_rofireMux_T_882 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[702], _out_rofireMux_T_882 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[701], _out_rofireMux_T_882 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[700], _out_rofireMux_T_882 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[699], _out_rofireMux_T_882 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_883 = eq(_out_T_1507, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_884 = or(out_rofireMux_out_219, _out_rofireMux_T_883) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_220 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_885 = and(_out_rofireMux_T_260, out_backSel_156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_886 = and(_out_rofireMux_T_885, _out_T_1421) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_220, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[385], _out_rofireMux_T_886 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[384], _out_rofireMux_T_886 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[383], _out_rofireMux_T_886 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[382], _out_rofireMux_T_886 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[381], _out_rofireMux_T_886 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[380], _out_rofireMux_T_886 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[379], _out_rofireMux_T_886 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[378], _out_rofireMux_T_886 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_887 = eq(_out_T_1421, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_888 = or(out_rofireMux_out_220, _out_rofireMux_T_887) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_221 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_889 = and(_out_rofireMux_T_260, out_backSel_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_890 = and(_out_rofireMux_T_889, _out_T_1355) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_221, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[127], _out_rofireMux_T_890 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[126], _out_rofireMux_T_890 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[125], _out_rofireMux_T_890 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[124], _out_rofireMux_T_890 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[123], _out_rofireMux_T_890 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[122], _out_rofireMux_T_890 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[121], _out_rofireMux_T_890 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[120], _out_rofireMux_T_890 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_891 = eq(_out_T_1355, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_892 = or(out_rofireMux_out_221, _out_rofireMux_T_891) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_222 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_893 = and(_out_rofireMux_T_260, out_backSel_158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_894 = and(_out_rofireMux_T_893, _out_T_1569) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_222, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[954], _out_rofireMux_T_894 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[953], _out_rofireMux_T_894 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[952], _out_rofireMux_T_894 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[951], _out_rofireMux_T_894 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[950], _out_rofireMux_T_894 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[949], _out_rofireMux_T_894 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[948], _out_rofireMux_T_894 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[947], _out_rofireMux_T_894 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_895 = eq(_out_T_1569, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_896 = or(out_rofireMux_out_222, _out_rofireMux_T_895) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_223 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_897 = and(_out_rofireMux_T_260, out_backSel_159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_898 = and(_out_rofireMux_T_897, _out_T_1487) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_223, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[632], _out_rofireMux_T_898 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[631], _out_rofireMux_T_898 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[630], _out_rofireMux_T_898 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[629], _out_rofireMux_T_898 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[628], _out_rofireMux_T_898 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[627], _out_rofireMux_T_898 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[626], _out_rofireMux_T_898 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[625], _out_rofireMux_T_898 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_899 = eq(_out_T_1487, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_900 = or(out_rofireMux_out_223, _out_rofireMux_T_899) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_224 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_901 = and(_out_rofireMux_T_260, out_backSel_160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_902 = and(_out_rofireMux_T_901, _out_T_1403) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_224, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[319], _out_rofireMux_T_902 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[318], _out_rofireMux_T_902 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[317], _out_rofireMux_T_902 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[316], _out_rofireMux_T_902 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[315], _out_rofireMux_T_902 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[314], _out_rofireMux_T_902 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[313], _out_rofireMux_T_902 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[312], _out_rofireMux_T_902 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_903 = eq(_out_T_1403, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_904 = or(out_rofireMux_out_224, _out_rofireMux_T_903) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_225 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_905 = and(_out_rofireMux_T_260, out_backSel_161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_906 = and(_out_rofireMux_T_905, _out_T_1467) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_225, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[552], _out_rofireMux_T_906 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[551], _out_rofireMux_T_906 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[550], _out_rofireMux_T_906 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[549], _out_rofireMux_T_906 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[548], _out_rofireMux_T_906 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[547], _out_rofireMux_T_906 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[546], _out_rofireMux_T_906 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[545], _out_rofireMux_T_906 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_907 = eq(_out_T_1467, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_908 = or(out_rofireMux_out_225, _out_rofireMux_T_907) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_226 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_909 = and(_out_rofireMux_T_260, out_backSel_162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_910 = and(_out_rofireMux_T_909, _out_T_1529) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_226, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[794], _out_rofireMux_T_910 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[793], _out_rofireMux_T_910 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[792], _out_rofireMux_T_910 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[791], _out_rofireMux_T_910 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[790], _out_rofireMux_T_910 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[789], _out_rofireMux_T_910 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[788], _out_rofireMux_T_910 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[787], _out_rofireMux_T_910 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_911 = eq(_out_T_1529, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_912 = or(out_rofireMux_out_226, _out_rofireMux_T_911) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_227 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_913 = and(_out_rofireMux_T_260, out_backSel_163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_914 = and(_out_rofireMux_T_913, _out_T_1613) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_227, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1130], _out_rofireMux_T_914 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1129], _out_rofireMux_T_914 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1128], _out_rofireMux_T_914 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1127], _out_rofireMux_T_914 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1126], _out_rofireMux_T_914 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1125], _out_rofireMux_T_914 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1124], _out_rofireMux_T_914 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1123], _out_rofireMux_T_914 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_915 = eq(_out_T_1613, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_916 = or(out_rofireMux_out_227, _out_rofireMux_T_915) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_228 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_917 = and(_out_rofireMux_T_260, out_backSel_164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_918 = and(_out_rofireMux_T_917, _out_T_1367) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_228, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[175], _out_rofireMux_T_918 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[174], _out_rofireMux_T_918 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[173], _out_rofireMux_T_918 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[172], _out_rofireMux_T_918 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[171], _out_rofireMux_T_918 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[170], _out_rofireMux_T_918 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[169], _out_rofireMux_T_918 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[168], _out_rofireMux_T_918 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_919 = eq(_out_T_1367, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_920 = or(out_rofireMux_out_228, _out_rofireMux_T_919) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_229 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_921 = and(_out_rofireMux_T_260, out_backSel_165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_922 = and(_out_rofireMux_T_921, _out_T_1409) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_229, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[343], _out_rofireMux_T_922 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[342], _out_rofireMux_T_922 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[341], _out_rofireMux_T_922 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[340], _out_rofireMux_T_922 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[339], _out_rofireMux_T_922 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[338], _out_rofireMux_T_922 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[337], _out_rofireMux_T_922 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[336], _out_rofireMux_T_922 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_923 = eq(_out_T_1409, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_924 = or(out_rofireMux_out_229, _out_rofireMux_T_923) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_230 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_925 = and(_out_rofireMux_T_260, out_backSel_166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_926 = and(_out_rofireMux_T_925, _out_T_1459) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_230, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[526], _out_rofireMux_T_926 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[525], _out_rofireMux_T_926 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[524], _out_rofireMux_T_926 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[523], _out_rofireMux_T_926 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[522], _out_rofireMux_T_926 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[521], _out_rofireMux_T_926 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[520], _out_rofireMux_T_926 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[519], _out_rofireMux_T_926 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_927 = eq(_out_T_1459, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_928 = or(out_rofireMux_out_230, _out_rofireMux_T_927) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_231 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_929 = and(_out_rofireMux_T_260, out_backSel_167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_930 = and(_out_rofireMux_T_929, _out_T_1527) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_231, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[786], _out_rofireMux_T_930 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[785], _out_rofireMux_T_930 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[784], _out_rofireMux_T_930 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[783], _out_rofireMux_T_930 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[782], _out_rofireMux_T_930 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[781], _out_rofireMux_T_930 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[780], _out_rofireMux_T_930 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[779], _out_rofireMux_T_930 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_931 = eq(_out_T_1527, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_932 = or(out_rofireMux_out_231, _out_rofireMux_T_931) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_232 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_933 = and(_out_rofireMux_T_260, out_backSel_168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_934 = and(_out_rofireMux_T_933, _out_T_1593) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_232, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1050], _out_rofireMux_T_934 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1049], _out_rofireMux_T_934 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1048], _out_rofireMux_T_934 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1047], _out_rofireMux_T_934 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1046], _out_rofireMux_T_934 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1045], _out_rofireMux_T_934 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1044], _out_rofireMux_T_934 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1043], _out_rofireMux_T_934 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_935 = eq(_out_T_1593, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_936 = or(out_rofireMux_out_232, _out_rofireMux_T_935) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_233 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_937 = and(_out_rofireMux_T_260, out_backSel_169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_938 = and(_out_rofireMux_T_937, _out_T_1425) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_233, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[401], _out_rofireMux_T_938 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[400], _out_rofireMux_T_938 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[399], _out_rofireMux_T_938 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[398], _out_rofireMux_T_938 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[397], _out_rofireMux_T_938 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[396], _out_rofireMux_T_938 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[395], _out_rofireMux_T_938 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[394], _out_rofireMux_T_938 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_939 = eq(_out_T_1425, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_940 = or(out_rofireMux_out_233, _out_rofireMux_T_939) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_234 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_941 = and(_out_rofireMux_T_260, out_backSel_170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_942 = and(_out_rofireMux_T_941, _out_T_1331) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_234, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[31], _out_rofireMux_T_942 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[30], _out_rofireMux_T_942 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[29], _out_rofireMux_T_942 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[28], _out_rofireMux_T_942 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[27], _out_rofireMux_T_942 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[26], _out_rofireMux_T_942 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[25], _out_rofireMux_T_942 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[24], _out_rofireMux_T_942 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_943 = eq(_out_T_1331, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_944 = or(out_rofireMux_out_234, _out_rofireMux_T_943) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_235 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_945 = and(_out_rofireMux_T_260, out_backSel_171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_946 = and(_out_rofireMux_T_945, _out_T_1573) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_235, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[970], _out_rofireMux_T_946 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[969], _out_rofireMux_T_946 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[968], _out_rofireMux_T_946 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[967], _out_rofireMux_T_946 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[966], _out_rofireMux_T_946 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[965], _out_rofireMux_T_946 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[964], _out_rofireMux_T_946 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[963], _out_rofireMux_T_946 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_947 = eq(_out_T_1573, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_948 = or(out_rofireMux_out_235, _out_rofireMux_T_947) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_236 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_949 = and(_out_rofireMux_T_260, out_backSel_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_950 = and(_out_rofireMux_T_949, _out_T_1491) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_236, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[648], _out_rofireMux_T_950 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[647], _out_rofireMux_T_950 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[646], _out_rofireMux_T_950 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[645], _out_rofireMux_T_950 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[644], _out_rofireMux_T_950 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[643], _out_rofireMux_T_950 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[642], _out_rofireMux_T_950 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[641], _out_rofireMux_T_950 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_951 = eq(_out_T_1491, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_952 = or(out_rofireMux_out_236, _out_rofireMux_T_951) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_237 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_953 = and(_out_rofireMux_T_260, out_backSel_173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_954 = and(_out_rofireMux_T_953, _out_T_1441) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_237, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[458], _out_rofireMux_T_954 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[457], _out_rofireMux_T_954 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[456], _out_rofireMux_T_954 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[455], _out_rofireMux_T_954 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[454], _out_rofireMux_T_954 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[453], _out_rofireMux_T_954 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[452], _out_rofireMux_T_954 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[451], _out_rofireMux_T_954 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_955 = eq(_out_T_1441, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_956 = or(out_rofireMux_out_237, _out_rofireMux_T_955) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_238 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_957 = and(_out_rofireMux_T_260, out_backSel_174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_958 = and(_out_rofireMux_T_957, _out_T_1343) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_238, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[79], _out_rofireMux_T_958 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[78], _out_rofireMux_T_958 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[77], _out_rofireMux_T_958 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[76], _out_rofireMux_T_958 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[75], _out_rofireMux_T_958 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[74], _out_rofireMux_T_958 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[73], _out_rofireMux_T_958 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[72], _out_rofireMux_T_958 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_959 = eq(_out_T_1343, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_960 = or(out_rofireMux_out_238, _out_rofireMux_T_959) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_239 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_961 = and(_out_rofireMux_T_260, out_backSel_175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_962 = and(_out_rofireMux_T_961, _out_T_1553) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_239, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[890], _out_rofireMux_T_962 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[889], _out_rofireMux_T_962 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[888], _out_rofireMux_T_962 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[887], _out_rofireMux_T_962 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[886], _out_rofireMux_T_962 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[885], _out_rofireMux_T_962 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[884], _out_rofireMux_T_962 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[883], _out_rofireMux_T_962 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_963 = eq(_out_T_1553, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_964 = or(out_rofireMux_out_239, _out_rofireMux_T_963) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_240 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_965 = and(_out_rofireMux_T_260, out_backSel_176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_966 = and(_out_rofireMux_T_965, _out_T_1473) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_240, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[576], _out_rofireMux_T_966 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[575], _out_rofireMux_T_966 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[574], _out_rofireMux_T_966 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[573], _out_rofireMux_T_966 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[572], _out_rofireMux_T_966 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[571], _out_rofireMux_T_966 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[570], _out_rofireMux_T_966 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[569], _out_rofireMux_T_966 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_967 = eq(_out_T_1473, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_968 = or(out_rofireMux_out_240, _out_rofireMux_T_967) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_241 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_969 = and(_out_rofireMux_T_260, out_backSel_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_970 = and(_out_rofireMux_T_969, _out_T_1547) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_241, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[866], _out_rofireMux_T_970 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[865], _out_rofireMux_T_970 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[864], _out_rofireMux_T_970 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[863], _out_rofireMux_T_970 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[862], _out_rofireMux_T_970 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[861], _out_rofireMux_T_970 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[860], _out_rofireMux_T_970 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[859], _out_rofireMux_T_970 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_971 = eq(_out_T_1547, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_972 = or(out_rofireMux_out_241, _out_rofireMux_T_971) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_242 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_973 = and(_out_rofireMux_T_260, out_backSel_178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_974 = and(_out_rofireMux_T_973, _out_T_1611) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_242, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1122], _out_rofireMux_T_974 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1121], _out_rofireMux_T_974 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1120], _out_rofireMux_T_974 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1119], _out_rofireMux_T_974 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1118], _out_rofireMux_T_974 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1117], _out_rofireMux_T_974 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1116], _out_rofireMux_T_974 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1115], _out_rofireMux_T_974 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_975 = eq(_out_T_1611, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_976 = or(out_rofireMux_out_242, _out_rofireMux_T_975) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_243 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_977 = and(_out_rofireMux_T_260, out_backSel_179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_978 = and(_out_rofireMux_T_977, _out_T_1369) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_243, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[183], _out_rofireMux_T_978 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[182], _out_rofireMux_T_978 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[181], _out_rofireMux_T_978 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[180], _out_rofireMux_T_978 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[179], _out_rofireMux_T_978 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[178], _out_rofireMux_T_978 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[177], _out_rofireMux_T_978 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[176], _out_rofireMux_T_978 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_979 = eq(_out_T_1369, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_980 = or(out_rofireMux_out_243, _out_rofireMux_T_979) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_244 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_981 = and(_out_rofireMux_T_260, out_backSel_180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_982 = and(_out_rofireMux_T_981, _out_T_1469) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_244, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[560], _out_rofireMux_T_982 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[559], _out_rofireMux_T_982 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[558], _out_rofireMux_T_982 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[557], _out_rofireMux_T_982 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[556], _out_rofireMux_T_982 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[555], _out_rofireMux_T_982 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[554], _out_rofireMux_T_982 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[553], _out_rofireMux_T_982 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_983 = eq(_out_T_1469, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_984 = or(out_rofireMux_out_244, _out_rofireMux_T_983) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_245 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_985 = and(_out_rofireMux_T_260, out_backSel_181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_986 = and(_out_rofireMux_T_985, _out_T_1485) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_245, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[624], _out_rofireMux_T_986 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[623], _out_rofireMux_T_986 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[622], _out_rofireMux_T_986 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[621], _out_rofireMux_T_986 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[620], _out_rofireMux_T_986 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[619], _out_rofireMux_T_986 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[618], _out_rofireMux_T_986 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[617], _out_rofireMux_T_986 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_987 = eq(_out_T_1485, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_988 = or(out_rofireMux_out_245, _out_rofireMux_T_987) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_246 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_989 = and(_out_rofireMux_T_260, out_backSel_182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_990 = and(_out_rofireMux_T_989, _out_T_1549) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_246, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[874], _out_rofireMux_T_990 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[873], _out_rofireMux_T_990 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[872], _out_rofireMux_T_990 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[871], _out_rofireMux_T_990 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[870], _out_rofireMux_T_990 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[869], _out_rofireMux_T_990 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[868], _out_rofireMux_T_990 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[867], _out_rofireMux_T_990 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_991 = eq(_out_T_1549, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_992 = or(out_rofireMux_out_246, _out_rofireMux_T_991) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_247 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_993 = and(_out_rofireMux_T_260, out_backSel_183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_994 = and(_out_rofireMux_T_993, _out_T_1591) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_247, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1042], _out_rofireMux_T_994 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1041], _out_rofireMux_T_994 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1040], _out_rofireMux_T_994 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1039], _out_rofireMux_T_994 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1038], _out_rofireMux_T_994 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1037], _out_rofireMux_T_994 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1036], _out_rofireMux_T_994 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1035], _out_rofireMux_T_994 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_995 = eq(_out_T_1591, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_996 = or(out_rofireMux_out_247, _out_rofireMux_T_995) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_248 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_997 = and(_out_rofireMux_T_260, out_backSel_184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_998 = and(_out_rofireMux_T_997, _out_T_1349) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_248, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[103], _out_rofireMux_T_998 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[102], _out_rofireMux_T_998 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[101], _out_rofireMux_T_998 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[100], _out_rofireMux_T_998 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[99], _out_rofireMux_T_998 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[98], _out_rofireMux_T_998 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[97], _out_rofireMux_T_998 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[96], _out_rofireMux_T_998 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_999 = eq(_out_T_1349, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1000 = or(out_rofireMux_out_248, _out_rofireMux_T_999) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_249 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1001 = and(_out_rofireMux_T_260, out_backSel_185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1002 = and(_out_rofireMux_T_1001, _out_T_1345) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_249, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[87], _out_rofireMux_T_1002 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[86], _out_rofireMux_T_1002 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[85], _out_rofireMux_T_1002 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[84], _out_rofireMux_T_1002 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[83], _out_rofireMux_T_1002 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[82], _out_rofireMux_T_1002 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[81], _out_rofireMux_T_1002 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[80], _out_rofireMux_T_1002 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1003 = eq(_out_T_1345, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1004 = or(out_rofireMux_out_249, _out_rofireMux_T_1003) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_250 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1005 = and(_out_rofireMux_T_260, out_backSel_186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1006 = and(_out_rofireMux_T_1005, _out_T_1571) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_250, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[962], _out_rofireMux_T_1006 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[961], _out_rofireMux_T_1006 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[960], _out_rofireMux_T_1006 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[959], _out_rofireMux_T_1006 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[958], _out_rofireMux_T_1006 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[957], _out_rofireMux_T_1006 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[956], _out_rofireMux_T_1006 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[955], _out_rofireMux_T_1006 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1007 = eq(_out_T_1571, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1008 = or(out_rofireMux_out_250, _out_rofireMux_T_1007) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_251 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1009 = and(_out_rofireMux_T_260, out_backSel_187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1010 = and(_out_rofireMux_T_1009, _out_T_1489) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_251, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[640], _out_rofireMux_T_1010 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[639], _out_rofireMux_T_1010 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[638], _out_rofireMux_T_1010 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[637], _out_rofireMux_T_1010 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[636], _out_rofireMux_T_1010 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[635], _out_rofireMux_T_1010 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[634], _out_rofireMux_T_1010 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[633], _out_rofireMux_T_1010 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1011 = eq(_out_T_1489, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1012 = or(out_rofireMux_out_251, _out_rofireMux_T_1011) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_252 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1013 = and(_out_rofireMux_T_260, out_backSel_188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1014 = and(_out_rofireMux_T_1013, _out_T_1423) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_252, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[393], _out_rofireMux_T_1014 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[392], _out_rofireMux_T_1014 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[391], _out_rofireMux_T_1014 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[390], _out_rofireMux_T_1014 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[389], _out_rofireMux_T_1014 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[388], _out_rofireMux_T_1014 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[387], _out_rofireMux_T_1014 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[386], _out_rofireMux_T_1014 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1015 = eq(_out_T_1423, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1016 = or(out_rofireMux_out_252, _out_rofireMux_T_1015) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_253 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1017 = and(_out_rofireMux_T_260, out_backSel_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1018 = and(_out_rofireMux_T_1017, _out_T_1357) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_253, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[135], _out_rofireMux_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[134], _out_rofireMux_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[133], _out_rofireMux_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[132], _out_rofireMux_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[131], _out_rofireMux_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[130], _out_rofireMux_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[129], _out_rofireMux_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[128], _out_rofireMux_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1019 = eq(_out_T_1357, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1020 = or(out_rofireMux_out_253, _out_rofireMux_T_1019) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_254 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1021 = and(_out_rofireMux_T_260, out_backSel_190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1022 = and(_out_rofireMux_T_1021, _out_T_1589) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_254, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1034], _out_rofireMux_T_1022 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1033], _out_rofireMux_T_1022 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1032], _out_rofireMux_T_1022 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1031], _out_rofireMux_T_1022 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1030], _out_rofireMux_T_1022 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1029], _out_rofireMux_T_1022 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1028], _out_rofireMux_T_1022 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1027], _out_rofireMux_T_1022 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1023 = eq(_out_T_1589, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1024 = or(out_rofireMux_out_254, _out_rofireMux_T_1023) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_255 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1025 = and(_out_rofireMux_T_260, out_backSel_191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1026 = and(_out_rofireMux_T_1025, _out_T_1475) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_255, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[584], _out_rofireMux_T_1026 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[583], _out_rofireMux_T_1026 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[582], _out_rofireMux_T_1026 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[581], _out_rofireMux_T_1026 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[580], _out_rofireMux_T_1026 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[579], _out_rofireMux_T_1026 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[578], _out_rofireMux_T_1026 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[577], _out_rofireMux_T_1026 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1027 = eq(_out_T_1475, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1028 = or(out_rofireMux_out_255, _out_rofireMux_T_1027) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_256 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1029 = and(_out_rofireMux_T_260, out_backSel_192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1030 = and(_out_rofireMux_T_1029, _out_T_1405) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_256, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[327], _out_rofireMux_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[326], _out_rofireMux_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[325], _out_rofireMux_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[324], _out_rofireMux_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[323], _out_rofireMux_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[322], _out_rofireMux_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[321], _out_rofireMux_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[320], _out_rofireMux_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1031 = eq(_out_T_1405, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1032 = or(out_rofireMux_out_256, _out_rofireMux_T_1031) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_257 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1033 = and(_out_rofireMux_T_260, out_backSel_193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1034 = and(_out_rofireMux_T_1033, _out_T_1431) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_257, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[425], _out_rofireMux_T_1034 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[424], _out_rofireMux_T_1034 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[423], _out_rofireMux_T_1034 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[422], _out_rofireMux_T_1034 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[421], _out_rofireMux_T_1034 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[420], _out_rofireMux_T_1034 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[419], _out_rofireMux_T_1034 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[418], _out_rofireMux_T_1034 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1035 = eq(_out_T_1431, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1036 = or(out_rofireMux_out_257, _out_rofireMux_T_1035) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_258 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1037 = and(_out_rofireMux_T_260, out_backSel_194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1038 = and(_out_rofireMux_T_1037, _out_T_1537) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_258, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[826], _out_rofireMux_T_1038 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[825], _out_rofireMux_T_1038 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[824], _out_rofireMux_T_1038 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[823], _out_rofireMux_T_1038 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[822], _out_rofireMux_T_1038 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[821], _out_rofireMux_T_1038 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[820], _out_rofireMux_T_1038 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[819], _out_rofireMux_T_1038 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1039 = eq(_out_T_1537, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1040 = or(out_rofireMux_out_258, _out_rofireMux_T_1039) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_259 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1041 = and(_out_rofireMux_T_260, out_backSel_195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1042 = and(_out_rofireMux_T_1041, _out_T_1603) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_259, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1090], _out_rofireMux_T_1042 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1089], _out_rofireMux_T_1042 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1088], _out_rofireMux_T_1042 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1087], _out_rofireMux_T_1042 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1086], _out_rofireMux_T_1042 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1085], _out_rofireMux_T_1042 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1084], _out_rofireMux_T_1042 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1083], _out_rofireMux_T_1042 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1043 = eq(_out_T_1603, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1044 = or(out_rofireMux_out_259, _out_rofireMux_T_1043) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_260 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1045 = and(_out_rofireMux_T_260, out_backSel_196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1046 = and(_out_rofireMux_T_1045, _out_T_1353) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_260, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[119], _out_rofireMux_T_1046 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[118], _out_rofireMux_T_1046 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[117], _out_rofireMux_T_1046 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[116], _out_rofireMux_T_1046 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[115], _out_rofireMux_T_1046 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[114], _out_rofireMux_T_1046 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[113], _out_rofireMux_T_1046 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[112], _out_rofireMux_T_1046 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1047 = eq(_out_T_1353, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1048 = or(out_rofireMux_out_260, _out_rofireMux_T_1047) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_261 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1049 = and(_out_rofireMux_T_260, out_backSel_197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1050 = and(_out_rofireMux_T_1049, _out_T_1417) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_261, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[369], _out_rofireMux_T_1050 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[368], _out_rofireMux_T_1050 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[367], _out_rofireMux_T_1050 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[366], _out_rofireMux_T_1050 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[365], _out_rofireMux_T_1050 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[364], _out_rofireMux_T_1050 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[363], _out_rofireMux_T_1050 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[362], _out_rofireMux_T_1050 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1051 = eq(_out_T_1417, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1052 = or(out_rofireMux_out_261, _out_rofireMux_T_1051) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_262 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1053 = and(_out_rofireMux_T_260, out_backSel_198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1054 = and(_out_rofireMux_T_1053, _out_T_1509) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_262, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[714], _out_rofireMux_T_1054 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[713], _out_rofireMux_T_1054 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[712], _out_rofireMux_T_1054 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[711], _out_rofireMux_T_1054 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[710], _out_rofireMux_T_1054 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[709], _out_rofireMux_T_1054 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[708], _out_rofireMux_T_1054 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[707], _out_rofireMux_T_1054 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1055 = eq(_out_T_1509, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1056 = or(out_rofireMux_out_262, _out_rofireMux_T_1055) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_263 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1057 = and(_out_rofireMux_T_260, out_backSel_199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1058 = and(_out_rofireMux_T_1057, _out_T_1545) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_263, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[858], _out_rofireMux_T_1058 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[857], _out_rofireMux_T_1058 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[856], _out_rofireMux_T_1058 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[855], _out_rofireMux_T_1058 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[854], _out_rofireMux_T_1058 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[853], _out_rofireMux_T_1058 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[852], _out_rofireMux_T_1058 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[851], _out_rofireMux_T_1058 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1059 = eq(_out_T_1545, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1060 = or(out_rofireMux_out_263, _out_rofireMux_T_1059) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_264 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1061 = and(_out_rofireMux_T_260, out_backSel_200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1062 = and(_out_rofireMux_T_1061, _out_T_1615) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_264, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1138], _out_rofireMux_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1137], _out_rofireMux_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1136], _out_rofireMux_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1135], _out_rofireMux_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1134], _out_rofireMux_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1133], _out_rofireMux_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1132], _out_rofireMux_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1131], _out_rofireMux_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1063 = eq(_out_T_1615, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1064 = or(out_rofireMux_out_264, _out_rofireMux_T_1063) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_265 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1065 = and(_out_rofireMux_T_260, out_backSel_201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1066 = and(_out_rofireMux_T_1065, _out_T_1397) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_265, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[295], _out_rofireMux_T_1066 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[294], _out_rofireMux_T_1066 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[293], _out_rofireMux_T_1066 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[292], _out_rofireMux_T_1066 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[291], _out_rofireMux_T_1066 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[290], _out_rofireMux_T_1066 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[289], _out_rofireMux_T_1066 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[288], _out_rofireMux_T_1066 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1067 = eq(_out_T_1397, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1068 = or(out_rofireMux_out_265, _out_rofireMux_T_1067) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_266 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1069 = and(_out_rofireMux_T_260, out_backSel_202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1070 = and(_out_rofireMux_T_1069, _out_T_1337) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_266, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[55], _out_rofireMux_T_1070 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[54], _out_rofireMux_T_1070 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[53], _out_rofireMux_T_1070 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[52], _out_rofireMux_T_1070 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[51], _out_rofireMux_T_1070 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[50], _out_rofireMux_T_1070 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[49], _out_rofireMux_T_1070 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[48], _out_rofireMux_T_1070 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1071 = eq(_out_T_1337, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1072 = or(out_rofireMux_out_266, _out_rofireMux_T_1071) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_267 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1073 = and(_out_rofireMux_T_260, out_backSel_203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1074 = and(_out_rofireMux_T_1073, _out_T_1557) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_267, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[906], _out_rofireMux_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[905], _out_rofireMux_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[904], _out_rofireMux_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[903], _out_rofireMux_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[902], _out_rofireMux_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[901], _out_rofireMux_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[900], _out_rofireMux_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[899], _out_rofireMux_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1075 = eq(_out_T_1557, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1076 = or(out_rofireMux_out_267, _out_rofireMux_T_1075) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_268 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1077 = and(_out_rofireMux_T_260, out_backSel_204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1078 = and(_out_rofireMux_T_1077, _out_T_1477) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_268, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[592], _out_rofireMux_T_1078 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[591], _out_rofireMux_T_1078 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[590], _out_rofireMux_T_1078 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[589], _out_rofireMux_T_1078 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[588], _out_rofireMux_T_1078 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[587], _out_rofireMux_T_1078 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[586], _out_rofireMux_T_1078 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[585], _out_rofireMux_T_1078 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1079 = eq(_out_T_1477, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1080 = or(out_rofireMux_out_268, _out_rofireMux_T_1079) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_269 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1081 = and(_out_rofireMux_T_260, out_backSel_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1082 = and(_out_rofireMux_T_1081, _out_T_1449) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_269, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[486], _out_rofireMux_T_1082 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[485], _out_rofireMux_T_1082 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[484], _out_rofireMux_T_1082 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[483], _out_rofireMux_T_1082 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[482], _out_rofireMux_T_1082 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[481], _out_rofireMux_T_1082 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[480], _out_rofireMux_T_1082 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[479], _out_rofireMux_T_1082 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1083 = eq(_out_T_1449, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1084 = or(out_rofireMux_out_269, _out_rofireMux_T_1083) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_270 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1085 = and(_out_rofireMux_T_260, out_backSel_206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1086 = and(_out_rofireMux_T_1085, _out_T_1391) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_270, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[271], _out_rofireMux_T_1086 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[270], _out_rofireMux_T_1086 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[269], _out_rofireMux_T_1086 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[268], _out_rofireMux_T_1086 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[267], _out_rofireMux_T_1086 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[266], _out_rofireMux_T_1086 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[265], _out_rofireMux_T_1086 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[264], _out_rofireMux_T_1086 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1087 = eq(_out_T_1391, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1088 = or(out_rofireMux_out_270, _out_rofireMux_T_1087) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_271 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1089 = and(_out_rofireMux_T_260, out_backSel_207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1090 = and(_out_rofireMux_T_1089, _out_T_1577) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_271, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[986], _out_rofireMux_T_1090 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[985], _out_rofireMux_T_1090 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[984], _out_rofireMux_T_1090 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[983], _out_rofireMux_T_1090 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[982], _out_rofireMux_T_1090 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[981], _out_rofireMux_T_1090 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[980], _out_rofireMux_T_1090 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[979], _out_rofireMux_T_1090 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1091 = eq(_out_T_1577, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1092 = or(out_rofireMux_out_271, _out_rofireMux_T_1091) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_272 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1093 = and(_out_rofireMux_T_260, out_backSel_208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1094 = and(_out_rofireMux_T_1093, _out_T_1499) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_272, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[680], _out_rofireMux_T_1094 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[679], _out_rofireMux_T_1094 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[678], _out_rofireMux_T_1094 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[677], _out_rofireMux_T_1094 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[676], _out_rofireMux_T_1094 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[675], _out_rofireMux_T_1094 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[674], _out_rofireMux_T_1094 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[673], _out_rofireMux_T_1094 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1095 = eq(_out_T_1499, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1096 = or(out_rofireMux_out_272, _out_rofireMux_T_1095) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_273 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1097 = and(_out_rofireMux_T_260, out_backSel_209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1098 = and(_out_rofireMux_T_1097, _out_T_1533) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_273, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[810], _out_rofireMux_T_1098 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[809], _out_rofireMux_T_1098 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[808], _out_rofireMux_T_1098 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[807], _out_rofireMux_T_1098 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[806], _out_rofireMux_T_1098 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[805], _out_rofireMux_T_1098 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[804], _out_rofireMux_T_1098 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[803], _out_rofireMux_T_1098 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1099 = eq(_out_T_1533, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1100 = or(out_rofireMux_out_273, _out_rofireMux_T_1099) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_274 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1101 = and(_out_rofireMux_T_260, out_backSel_210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1102 = and(_out_rofireMux_T_1101, _out_T_1597) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_274, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1066], _out_rofireMux_T_1102 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1065], _out_rofireMux_T_1102 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1064], _out_rofireMux_T_1102 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1063], _out_rofireMux_T_1102 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1062], _out_rofireMux_T_1102 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1061], _out_rofireMux_T_1102 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1060], _out_rofireMux_T_1102 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1059], _out_rofireMux_T_1102 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1103 = eq(_out_T_1597, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1104 = or(out_rofireMux_out_274, _out_rofireMux_T_1103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_275 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1105 = and(_out_rofireMux_T_260, out_backSel_211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1106 = and(_out_rofireMux_T_1105, _out_T_1375) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_275, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[207], _out_rofireMux_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[206], _out_rofireMux_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[205], _out_rofireMux_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[204], _out_rofireMux_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[203], _out_rofireMux_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[202], _out_rofireMux_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[201], _out_rofireMux_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[200], _out_rofireMux_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1107 = eq(_out_T_1375, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1108 = or(out_rofireMux_out_275, _out_rofireMux_T_1107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_276 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1109 = and(_out_rofireMux_T_260, out_backSel_212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1110 = and(_out_rofireMux_T_1109, _out_T_1433) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_276, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[433], _out_rofireMux_T_1110 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[432], _out_rofireMux_T_1110 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[431], _out_rofireMux_T_1110 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[430], _out_rofireMux_T_1110 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[429], _out_rofireMux_T_1110 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[428], _out_rofireMux_T_1110 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[427], _out_rofireMux_T_1110 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[426], _out_rofireMux_T_1110 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1111 = eq(_out_T_1433, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1112 = or(out_rofireMux_out_276, _out_rofireMux_T_1111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_277 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1113 = and(_out_rofireMux_T_260, out_backSel_213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1114 = and(_out_rofireMux_T_1113, _out_T_1505) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_277, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[698], _out_rofireMux_T_1114 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[697], _out_rofireMux_T_1114 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[696], _out_rofireMux_T_1114 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[695], _out_rofireMux_T_1114 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[694], _out_rofireMux_T_1114 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[693], _out_rofireMux_T_1114 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[692], _out_rofireMux_T_1114 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[691], _out_rofireMux_T_1114 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1115 = eq(_out_T_1505, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1116 = or(out_rofireMux_out_277, _out_rofireMux_T_1115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_278 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1117 = and(_out_rofireMux_T_260, out_backSel_214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1118 = and(_out_rofireMux_T_1117, _out_T_1579) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_278, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[994], _out_rofireMux_T_1118 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[993], _out_rofireMux_T_1118 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[992], _out_rofireMux_T_1118 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[991], _out_rofireMux_T_1118 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[990], _out_rofireMux_T_1118 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[989], _out_rofireMux_T_1118 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[988], _out_rofireMux_T_1118 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[987], _out_rofireMux_T_1118 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1119 = eq(_out_T_1579, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1120 = or(out_rofireMux_out_278, _out_rofireMux_T_1119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_279 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1121 = and(_out_rofireMux_T_260, out_backSel_215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1122 = and(_out_rofireMux_T_1121, _out_T_1619) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_279, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1154], _out_rofireMux_T_1122 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1153], _out_rofireMux_T_1122 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1152], _out_rofireMux_T_1122 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1151], _out_rofireMux_T_1122 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1150], _out_rofireMux_T_1122 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1149], _out_rofireMux_T_1122 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1148], _out_rofireMux_T_1122 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1147], _out_rofireMux_T_1122 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1123 = eq(_out_T_1619, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1124 = or(out_rofireMux_out_279, _out_rofireMux_T_1123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_280 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1125 = and(_out_rofireMux_T_260, out_backSel_216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1126 = and(_out_rofireMux_T_1125, _out_T_1365) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_280, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[167], _out_rofireMux_T_1126 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[166], _out_rofireMux_T_1126 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[165], _out_rofireMux_T_1126 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[164], _out_rofireMux_T_1126 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[163], _out_rofireMux_T_1126 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[162], _out_rofireMux_T_1126 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[161], _out_rofireMux_T_1126 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[160], _out_rofireMux_T_1126 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1127 = eq(_out_T_1365, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1128 = or(out_rofireMux_out_280, _out_rofireMux_T_1127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_281 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1129 = and(_out_rofireMux_T_260, out_backSel_217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1130 = and(_out_rofireMux_T_1129, _out_T_1333) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_281, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[39], _out_rofireMux_T_1130 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[38], _out_rofireMux_T_1130 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[37], _out_rofireMux_T_1130 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[36], _out_rofireMux_T_1130 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[35], _out_rofireMux_T_1130 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[34], _out_rofireMux_T_1130 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[33], _out_rofireMux_T_1130 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[32], _out_rofireMux_T_1130 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1131 = eq(_out_T_1333, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1132 = or(out_rofireMux_out_281, _out_rofireMux_T_1131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_282 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1133 = and(_out_rofireMux_T_260, out_backSel_218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1134 = and(_out_rofireMux_T_1133, _out_T_1559) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_282, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[914], _out_rofireMux_T_1134 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[913], _out_rofireMux_T_1134 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[912], _out_rofireMux_T_1134 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[911], _out_rofireMux_T_1134 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[910], _out_rofireMux_T_1134 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[909], _out_rofireMux_T_1134 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[908], _out_rofireMux_T_1134 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[907], _out_rofireMux_T_1134 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1135 = eq(_out_T_1559, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1136 = or(out_rofireMux_out_282, _out_rofireMux_T_1135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_283 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1137 = and(_out_rofireMux_T_260, out_backSel_219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1138 = and(_out_rofireMux_T_1137, _out_T_1493) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_283, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[656], _out_rofireMux_T_1138 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[655], _out_rofireMux_T_1138 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[654], _out_rofireMux_T_1138 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[653], _out_rofireMux_T_1138 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[652], _out_rofireMux_T_1138 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[651], _out_rofireMux_T_1138 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[650], _out_rofireMux_T_1138 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[649], _out_rofireMux_T_1138 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1139 = eq(_out_T_1493, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1140 = or(out_rofireMux_out_283, _out_rofireMux_T_1139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_284 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1141 = and(_out_rofireMux_T_260, out_backSel_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1142 = and(_out_rofireMux_T_1141, _out_T_1399) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_284, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[303], _out_rofireMux_T_1142 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[302], _out_rofireMux_T_1142 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[301], _out_rofireMux_T_1142 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[300], _out_rofireMux_T_1142 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[299], _out_rofireMux_T_1142 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[298], _out_rofireMux_T_1142 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[297], _out_rofireMux_T_1142 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[296], _out_rofireMux_T_1142 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1143 = eq(_out_T_1399, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1144 = or(out_rofireMux_out_284, _out_rofireMux_T_1143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_285 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1145 = and(_out_rofireMux_T_260, out_backSel_221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1146 = and(_out_rofireMux_T_1145, _out_T_1381) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_285, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[231], _out_rofireMux_T_1146 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[230], _out_rofireMux_T_1146 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[229], _out_rofireMux_T_1146 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[228], _out_rofireMux_T_1146 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[227], _out_rofireMux_T_1146 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[226], _out_rofireMux_T_1146 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[225], _out_rofireMux_T_1146 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[224], _out_rofireMux_T_1146 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1147 = eq(_out_T_1381, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1148 = or(out_rofireMux_out_285, _out_rofireMux_T_1147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_286 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1149 = and(_out_rofireMux_T_260, out_backSel_222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1150 = and(_out_rofireMux_T_1149, _out_T_1621) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_286, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1162], _out_rofireMux_T_1150 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1161], _out_rofireMux_T_1150 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1160], _out_rofireMux_T_1150 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1159], _out_rofireMux_T_1150 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1158], _out_rofireMux_T_1150 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1157], _out_rofireMux_T_1150 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1156], _out_rofireMux_T_1150 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1155], _out_rofireMux_T_1150 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1151 = eq(_out_T_1621, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1152 = or(out_rofireMux_out_286, _out_rofireMux_T_1151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_287 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1153 = and(_out_rofireMux_T_260, out_backSel_223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1154 = and(_out_rofireMux_T_1153, _out_T_1519) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_287, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[754], _out_rofireMux_T_1154 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[753], _out_rofireMux_T_1154 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[752], _out_rofireMux_T_1154 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[751], _out_rofireMux_T_1154 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[750], _out_rofireMux_T_1154 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[749], _out_rofireMux_T_1154 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[748], _out_rofireMux_T_1154 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[747], _out_rofireMux_T_1154 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1155 = eq(_out_T_1519, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1156 = or(out_rofireMux_out_287, _out_rofireMux_T_1155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_288 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1157 = and(_out_rofireMux_T_260, out_backSel_224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1158 = and(_out_rofireMux_T_1157, _out_T_1419) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_288, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[377], _out_rofireMux_T_1158 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[376], _out_rofireMux_T_1158 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[375], _out_rofireMux_T_1158 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[374], _out_rofireMux_T_1158 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[373], _out_rofireMux_T_1158 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[372], _out_rofireMux_T_1158 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[371], _out_rofireMux_T_1158 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[370], _out_rofireMux_T_1158 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1159 = eq(_out_T_1419, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1160 = or(out_rofireMux_out_288, _out_rofireMux_T_1159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_289 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1161 = and(_out_rofireMux_T_260, out_backSel_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1162 = and(_out_rofireMux_T_1161, _out_T_1429) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_289, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[417], _out_rofireMux_T_1162 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[416], _out_rofireMux_T_1162 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[415], _out_rofireMux_T_1162 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[414], _out_rofireMux_T_1162 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[413], _out_rofireMux_T_1162 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[412], _out_rofireMux_T_1162 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[411], _out_rofireMux_T_1162 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[410], _out_rofireMux_T_1162 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1163 = eq(_out_T_1429, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1164 = or(out_rofireMux_out_289, _out_rofireMux_T_1163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_290 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1165 = and(_out_rofireMux_T_260, out_backSel_226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1166 = and(_out_rofireMux_T_1165, _out_T_1523) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_290, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[770], _out_rofireMux_T_1166 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[769], _out_rofireMux_T_1166 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[768], _out_rofireMux_T_1166 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[767], _out_rofireMux_T_1166 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[766], _out_rofireMux_T_1166 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[765], _out_rofireMux_T_1166 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[764], _out_rofireMux_T_1166 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[763], _out_rofireMux_T_1166 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1167 = eq(_out_T_1523, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1168 = or(out_rofireMux_out_290, _out_rofireMux_T_1167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_291 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1169 = and(_out_rofireMux_T_260, out_backSel_227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1170 = and(_out_rofireMux_T_1169, _out_T_1627) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_291, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1186], _out_rofireMux_T_1170 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1185], _out_rofireMux_T_1170 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1184], _out_rofireMux_T_1170 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1183], _out_rofireMux_T_1170 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1182], _out_rofireMux_T_1170 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1181], _out_rofireMux_T_1170 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1180], _out_rofireMux_T_1170 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1179], _out_rofireMux_T_1170 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1171 = eq(_out_T_1627, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1172 = or(out_rofireMux_out_291, _out_rofireMux_T_1171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_292 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1173 = and(_out_rofireMux_T_260, out_backSel_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1174 = and(_out_rofireMux_T_1173, _out_T_1361) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_292, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[151], _out_rofireMux_T_1174 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[150], _out_rofireMux_T_1174 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[149], _out_rofireMux_T_1174 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[148], _out_rofireMux_T_1174 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[147], _out_rofireMux_T_1174 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[146], _out_rofireMux_T_1174 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[145], _out_rofireMux_T_1174 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[144], _out_rofireMux_T_1174 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1175 = eq(_out_T_1361, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1176 = or(out_rofireMux_out_292, _out_rofireMux_T_1175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_293 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1177 = and(_out_rofireMux_T_260, out_backSel_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1178 = and(_out_rofireMux_T_1177, _out_T_1413) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_293, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[353], _out_rofireMux_T_1178 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[352], _out_rofireMux_T_1178 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[351], _out_rofireMux_T_1178 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[350], _out_rofireMux_T_1178 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[349], _out_rofireMux_T_1178 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[348], _out_rofireMux_T_1178 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[347], _out_rofireMux_T_1178 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[346], _out_rofireMux_T_1178 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1179 = eq(_out_T_1413, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1180 = or(out_rofireMux_out_293, _out_rofireMux_T_1179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_294 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1181 = and(_out_rofireMux_T_260, out_backSel_230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1182 = and(_out_rofireMux_T_1181, _out_T_1495) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_294, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[664], _out_rofireMux_T_1182 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[663], _out_rofireMux_T_1182 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[662], _out_rofireMux_T_1182 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[661], _out_rofireMux_T_1182 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[660], _out_rofireMux_T_1182 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[659], _out_rofireMux_T_1182 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[658], _out_rofireMux_T_1182 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[657], _out_rofireMux_T_1182 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1183 = eq(_out_T_1495, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1184 = or(out_rofireMux_out_294, _out_rofireMux_T_1183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_295 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1185 = and(_out_rofireMux_T_260, out_backSel_231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1186 = and(_out_rofireMux_T_1185, _out_T_1565) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_295, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[938], _out_rofireMux_T_1186 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[937], _out_rofireMux_T_1186 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[936], _out_rofireMux_T_1186 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[935], _out_rofireMux_T_1186 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[934], _out_rofireMux_T_1186 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[933], _out_rofireMux_T_1186 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[932], _out_rofireMux_T_1186 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[931], _out_rofireMux_T_1186 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1187 = eq(_out_T_1565, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1188 = or(out_rofireMux_out_295, _out_rofireMux_T_1187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_296 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1189 = and(_out_rofireMux_T_260, out_backSel_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1190 = and(_out_rofireMux_T_1189, _out_T_1623) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_296, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1170], _out_rofireMux_T_1190 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1169], _out_rofireMux_T_1190 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1168], _out_rofireMux_T_1190 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1167], _out_rofireMux_T_1190 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1166], _out_rofireMux_T_1190 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1165], _out_rofireMux_T_1190 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1164], _out_rofireMux_T_1190 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1163], _out_rofireMux_T_1190 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1191 = eq(_out_T_1623, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1192 = or(out_rofireMux_out_296, _out_rofireMux_T_1191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_297 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1193 = and(_out_rofireMux_T_260, out_backSel_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1194 = and(_out_rofireMux_T_1193, _out_T_1393) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_297, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[279], _out_rofireMux_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[278], _out_rofireMux_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[277], _out_rofireMux_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[276], _out_rofireMux_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[275], _out_rofireMux_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[274], _out_rofireMux_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[273], _out_rofireMux_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[272], _out_rofireMux_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1195 = eq(_out_T_1393, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1196 = or(out_rofireMux_out_297, _out_rofireMux_T_1195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_298 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1197 = and(_out_rofireMux_T_260, out_backSel_234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1198 = and(_out_rofireMux_T_1197, _out_T_1329) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_298, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[23], _out_rofireMux_T_1198 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[22], _out_rofireMux_T_1198 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[21], _out_rofireMux_T_1198 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[20], _out_rofireMux_T_1198 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[19], _out_rofireMux_T_1198 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[18], _out_rofireMux_T_1198 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[17], _out_rofireMux_T_1198 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[16], _out_rofireMux_T_1198 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1199 = eq(_out_T_1329, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1200 = or(out_rofireMux_out_298, _out_rofireMux_T_1199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_299 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1201 = and(_out_rofireMux_T_260, out_backSel_235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1202 = and(_out_rofireMux_T_1201, _out_T_1581) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_299, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1002], _out_rofireMux_T_1202 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1001], _out_rofireMux_T_1202 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1000], _out_rofireMux_T_1202 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[999], _out_rofireMux_T_1202 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[998], _out_rofireMux_T_1202 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[997], _out_rofireMux_T_1202 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[996], _out_rofireMux_T_1202 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[995], _out_rofireMux_T_1202 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1203 = eq(_out_T_1581, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1204 = or(out_rofireMux_out_299, _out_rofireMux_T_1203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_300 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1205 = and(_out_rofireMux_T_260, out_backSel_236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1206 = and(_out_rofireMux_T_1205, _out_T_1483) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_300, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[616], _out_rofireMux_T_1206 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[615], _out_rofireMux_T_1206 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[614], _out_rofireMux_T_1206 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[613], _out_rofireMux_T_1206 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[612], _out_rofireMux_T_1206 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[611], _out_rofireMux_T_1206 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[610], _out_rofireMux_T_1206 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[609], _out_rofireMux_T_1206 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1207 = eq(_out_T_1483, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1208 = or(out_rofireMux_out_300, _out_rofireMux_T_1207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_301 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1209 = and(_out_rofireMux_T_260, out_backSel_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1210 = and(_out_rofireMux_T_1209, _out_T_1453) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_301, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[502], _out_rofireMux_T_1210 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[501], _out_rofireMux_T_1210 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[500], _out_rofireMux_T_1210 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[499], _out_rofireMux_T_1210 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[498], _out_rofireMux_T_1210 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[497], _out_rofireMux_T_1210 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[496], _out_rofireMux_T_1210 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[495], _out_rofireMux_T_1210 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1211 = eq(_out_T_1453, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1212 = or(out_rofireMux_out_301, _out_rofireMux_T_1211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_302 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1213 = and(_out_rofireMux_T_260, out_backSel_238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1214 = and(_out_rofireMux_T_1213, _out_T_1373) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_302, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[199], _out_rofireMux_T_1214 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[198], _out_rofireMux_T_1214 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[197], _out_rofireMux_T_1214 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[196], _out_rofireMux_T_1214 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[195], _out_rofireMux_T_1214 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[194], _out_rofireMux_T_1214 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[193], _out_rofireMux_T_1214 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[192], _out_rofireMux_T_1214 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1215 = eq(_out_T_1373, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1216 = or(out_rofireMux_out_302, _out_rofireMux_T_1215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_303 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1217 = and(_out_rofireMux_T_260, out_backSel_239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1218 = and(_out_rofireMux_T_1217, _out_T_1605) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_303, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1098], _out_rofireMux_T_1218 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1097], _out_rofireMux_T_1218 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1096], _out_rofireMux_T_1218 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1095], _out_rofireMux_T_1218 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1094], _out_rofireMux_T_1218 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1093], _out_rofireMux_T_1218 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1092], _out_rofireMux_T_1218 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1091], _out_rofireMux_T_1218 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1219 = eq(_out_T_1605, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1220 = or(out_rofireMux_out_303, _out_rofireMux_T_1219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_304 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1221 = and(_out_rofireMux_T_260, out_backSel_240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1222 = and(_out_rofireMux_T_1221, _out_T_1513) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_304, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[730], _out_rofireMux_T_1222 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[729], _out_rofireMux_T_1222 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[728], _out_rofireMux_T_1222 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[727], _out_rofireMux_T_1222 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[726], _out_rofireMux_T_1222 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[725], _out_rofireMux_T_1222 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[724], _out_rofireMux_T_1222 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[723], _out_rofireMux_T_1222 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1223 = eq(_out_T_1513, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1224 = or(out_rofireMux_out_304, _out_rofireMux_T_1223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_305 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1225 = and(_out_rofireMux_T_260, out_backSel_241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1226 = and(_out_rofireMux_T_1225, _out_T_1525) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_305, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[778], _out_rofireMux_T_1226 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[777], _out_rofireMux_T_1226 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[776], _out_rofireMux_T_1226 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[775], _out_rofireMux_T_1226 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[774], _out_rofireMux_T_1226 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[773], _out_rofireMux_T_1226 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[772], _out_rofireMux_T_1226 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[771], _out_rofireMux_T_1226 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1227 = eq(_out_T_1525, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1228 = or(out_rofireMux_out_305, _out_rofireMux_T_1227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_306 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1229 = and(_out_rofireMux_T_260, out_backSel_242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1230 = and(_out_rofireMux_T_1229, _out_T_1607) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_306, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1106], _out_rofireMux_T_1230 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1105], _out_rofireMux_T_1230 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1104], _out_rofireMux_T_1230 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1103], _out_rofireMux_T_1230 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1102], _out_rofireMux_T_1230 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1101], _out_rofireMux_T_1230 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1100], _out_rofireMux_T_1230 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1099], _out_rofireMux_T_1230 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1231 = eq(_out_T_1607, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1232 = or(out_rofireMux_out_306, _out_rofireMux_T_1231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_307 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1233 = and(_out_rofireMux_T_260, out_backSel_243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1234 = and(_out_rofireMux_T_1233, _out_T_1387) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_307, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[255], _out_rofireMux_T_1234 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[254], _out_rofireMux_T_1234 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[253], _out_rofireMux_T_1234 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[252], _out_rofireMux_T_1234 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[251], _out_rofireMux_T_1234 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[250], _out_rofireMux_T_1234 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[249], _out_rofireMux_T_1234 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[248], _out_rofireMux_T_1234 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1235 = eq(_out_T_1387, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1236 = or(out_rofireMux_out_307, _out_rofireMux_T_1235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_308 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1237 = and(_out_rofireMux_T_260, out_backSel_244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1238 = and(_out_rofireMux_T_1237, _out_T_1457) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_308, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[518], _out_rofireMux_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[517], _out_rofireMux_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[516], _out_rofireMux_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[515], _out_rofireMux_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[514], _out_rofireMux_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[513], _out_rofireMux_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[512], _out_rofireMux_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[511], _out_rofireMux_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1239 = eq(_out_T_1457, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1240 = or(out_rofireMux_out_308, _out_rofireMux_T_1239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_309 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1241 = and(_out_rofireMux_T_260, out_backSel_245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1242 = and(_out_rofireMux_T_1241, _out_T_1497) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_309, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[672], _out_rofireMux_T_1242 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[671], _out_rofireMux_T_1242 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[670], _out_rofireMux_T_1242 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[669], _out_rofireMux_T_1242 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[668], _out_rofireMux_T_1242 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[667], _out_rofireMux_T_1242 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[666], _out_rofireMux_T_1242 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[665], _out_rofireMux_T_1242 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1243 = eq(_out_T_1497, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1244 = or(out_rofireMux_out_309, _out_rofireMux_T_1243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_310 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1245 = and(_out_rofireMux_T_260, out_backSel_246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1246 = and(_out_rofireMux_T_1245, _out_T_1583) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_310, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1010], _out_rofireMux_T_1246 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1009], _out_rofireMux_T_1246 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1008], _out_rofireMux_T_1246 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1007], _out_rofireMux_T_1246 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1006], _out_rofireMux_T_1246 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1005], _out_rofireMux_T_1246 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1004], _out_rofireMux_T_1246 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1003], _out_rofireMux_T_1246 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1247 = eq(_out_T_1583, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1248 = or(out_rofireMux_out_310, _out_rofireMux_T_1247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_311 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1249 = and(_out_rofireMux_T_260, out_backSel_247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1250 = and(_out_rofireMux_T_1249, _out_T_1335) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_311, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[47], _out_rofireMux_T_1250 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[46], _out_rofireMux_T_1250 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[45], _out_rofireMux_T_1250 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[44], _out_rofireMux_T_1250 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[43], _out_rofireMux_T_1250 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[42], _out_rofireMux_T_1250 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[41], _out_rofireMux_T_1250 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[40], _out_rofireMux_T_1250 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1251 = eq(_out_T_1335, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1252 = or(out_rofireMux_out_311, _out_rofireMux_T_1251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_312 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1253 = and(_out_rofireMux_T_260, out_backSel_248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1254 = and(_out_rofireMux_T_1253, _out_T_1395) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_312, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[287], _out_rofireMux_T_1254 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[286], _out_rofireMux_T_1254 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[285], _out_rofireMux_T_1254 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[284], _out_rofireMux_T_1254 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[283], _out_rofireMux_T_1254 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[282], _out_rofireMux_T_1254 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[281], _out_rofireMux_T_1254 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[280], _out_rofireMux_T_1254 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1255 = eq(_out_T_1395, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1256 = or(out_rofireMux_out_312, _out_rofireMux_T_1255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_313 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1257 = and(_out_rofireMux_T_260, out_backSel_249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1258 = and(_out_rofireMux_T_1257, _out_T_1327) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_313, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[15], _out_rofireMux_T_1258 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[14], _out_rofireMux_T_1258 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[13], _out_rofireMux_T_1258 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[12], _out_rofireMux_T_1258 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[11], _out_rofireMux_T_1258 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[10], _out_rofireMux_T_1258 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[9], _out_rofireMux_T_1258 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[8], _out_rofireMux_T_1258 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1259 = eq(_out_T_1327, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1260 = or(out_rofireMux_out_313, _out_rofireMux_T_1259) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_314 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1261 = and(_out_rofireMux_T_260, out_backSel_250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1262 = and(_out_rofireMux_T_1261, _out_T_1563) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_314, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[930], _out_rofireMux_T_1262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[929], _out_rofireMux_T_1262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[928], _out_rofireMux_T_1262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[927], _out_rofireMux_T_1262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[926], _out_rofireMux_T_1262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[925], _out_rofireMux_T_1262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[924], _out_rofireMux_T_1262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[923], _out_rofireMux_T_1262 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1263 = eq(_out_T_1563, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1264 = or(out_rofireMux_out_314, _out_rofireMux_T_1263) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_315 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1265 = and(_out_rofireMux_T_260, out_backSel_251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1266 = and(_out_rofireMux_T_1265, _out_T_1515) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_315, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[738], _out_rofireMux_T_1266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[737], _out_rofireMux_T_1266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[736], _out_rofireMux_T_1266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[735], _out_rofireMux_T_1266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[734], _out_rofireMux_T_1266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[733], _out_rofireMux_T_1266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[732], _out_rofireMux_T_1266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[731], _out_rofireMux_T_1266 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1267 = eq(_out_T_1515, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1268 = or(out_rofireMux_out_315, _out_rofireMux_T_1267) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_316 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1269 = and(_out_rofireMux_T_260, out_backSel_252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1270 = and(_out_rofireMux_T_1269, _out_T_1415) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_316, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[361], _out_rofireMux_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[360], _out_rofireMux_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[359], _out_rofireMux_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[358], _out_rofireMux_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[357], _out_rofireMux_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[356], _out_rofireMux_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[355], _out_rofireMux_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[354], _out_rofireMux_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1271 = eq(_out_T_1415, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1272 = or(out_rofireMux_out_316, _out_rofireMux_T_1271) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_317 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1273 = and(_out_rofireMux_T_260, out_backSel_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1274 = and(_out_rofireMux_T_1273, _out_T_1377) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_317, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[215], _out_rofireMux_T_1274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[214], _out_rofireMux_T_1274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[213], _out_rofireMux_T_1274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[212], _out_rofireMux_T_1274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[211], _out_rofireMux_T_1274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[210], _out_rofireMux_T_1274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[209], _out_rofireMux_T_1274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[208], _out_rofireMux_T_1274 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1275 = eq(_out_T_1377, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1276 = or(out_rofireMux_out_317, _out_rofireMux_T_1275) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_318 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1277 = and(_out_rofireMux_T_260, out_backSel_254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1278 = and(_out_rofireMux_T_1277, _out_T_1625) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_318, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1178], _out_rofireMux_T_1278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1177], _out_rofireMux_T_1278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1176], _out_rofireMux_T_1278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1175], _out_rofireMux_T_1278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1174], _out_rofireMux_T_1278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1173], _out_rofireMux_T_1278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1172], _out_rofireMux_T_1278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[1171], _out_rofireMux_T_1278 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1279 = eq(_out_T_1625, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1280 = or(out_rofireMux_out_318, _out_rofireMux_T_1279) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_319 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1281 = and(_out_rofireMux_T_260, out_backSel_255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1282 = and(_out_rofireMux_T_1281, _out_T_1531) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_319, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[802], _out_rofireMux_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[801], _out_rofireMux_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[800], _out_rofireMux_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[799], _out_rofireMux_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[798], _out_rofireMux_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[797], _out_rofireMux_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[796], _out_rofireMux_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready_1[795], _out_rofireMux_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_1283 = eq(_out_T_1531, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1284 = or(out_rofireMux_out_319, _out_rofireMux_T_1283) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1285 = geq(out_oindex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_rofireMux_WIRE_1 : UInt<1>[256] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[0], _out_rofireMux_T_264 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[1], _out_rofireMux_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[2], _out_rofireMux_T_272 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[3], _out_rofireMux_T_276 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[4], _out_rofireMux_T_280 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[5], _out_rofireMux_T_284 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[6], _out_rofireMux_T_288 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[7], _out_rofireMux_T_292 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[8], _out_rofireMux_T_296 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[9], _out_rofireMux_T_300 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[10], _out_rofireMux_T_304 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[11], _out_rofireMux_T_308 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[12], _out_rofireMux_T_312 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[13], _out_rofireMux_T_316 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[14], _out_rofireMux_T_320 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[15], _out_rofireMux_T_324 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[16], _out_rofireMux_T_328 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[17], _out_rofireMux_T_332 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[18], _out_rofireMux_T_336 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[19], _out_rofireMux_T_340 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[20], _out_rofireMux_T_344 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[21], _out_rofireMux_T_348 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[22], _out_rofireMux_T_352 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[23], _out_rofireMux_T_356 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[24], _out_rofireMux_T_360 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[25], _out_rofireMux_T_364 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[26], _out_rofireMux_T_368 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[27], _out_rofireMux_T_372 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[28], _out_rofireMux_T_376 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[29], _out_rofireMux_T_380 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[30], _out_rofireMux_T_384 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[31], _out_rofireMux_T_388 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[32], _out_rofireMux_T_392 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[33], _out_rofireMux_T_396 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[34], _out_rofireMux_T_400 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[35], _out_rofireMux_T_404 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[36], _out_rofireMux_T_408 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[37], _out_rofireMux_T_412 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[38], _out_rofireMux_T_416 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[39], _out_rofireMux_T_420 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[40], _out_rofireMux_T_424 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[41], _out_rofireMux_T_428 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[42], _out_rofireMux_T_432 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[43], _out_rofireMux_T_436 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[44], _out_rofireMux_T_440 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[45], _out_rofireMux_T_444 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[46], _out_rofireMux_T_448 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[47], _out_rofireMux_T_452 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[48], _out_rofireMux_T_456 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[49], _out_rofireMux_T_460 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[50], _out_rofireMux_T_464 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[51], _out_rofireMux_T_468 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[52], _out_rofireMux_T_472 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[53], _out_rofireMux_T_476 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[54], _out_rofireMux_T_480 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[55], _out_rofireMux_T_484 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[56], _out_rofireMux_T_488 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[57], _out_rofireMux_T_492 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[58], _out_rofireMux_T_496 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[59], _out_rofireMux_T_500 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[60], _out_rofireMux_T_504 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[61], _out_rofireMux_T_508 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[62], _out_rofireMux_T_512 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[63], _out_rofireMux_T_516 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[64], _out_rofireMux_T_520 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[65], _out_rofireMux_T_524 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[66], _out_rofireMux_T_528 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[67], _out_rofireMux_T_532 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[68], _out_rofireMux_T_536 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[69], _out_rofireMux_T_540 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[70], _out_rofireMux_T_544 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[71], _out_rofireMux_T_548 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[72], _out_rofireMux_T_552 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[73], _out_rofireMux_T_556 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[74], _out_rofireMux_T_560 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[75], _out_rofireMux_T_564 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[76], _out_rofireMux_T_568 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[77], _out_rofireMux_T_572 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[78], _out_rofireMux_T_576 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[79], _out_rofireMux_T_580 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[80], _out_rofireMux_T_584 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[81], _out_rofireMux_T_588 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[82], _out_rofireMux_T_592 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[83], _out_rofireMux_T_596 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[84], _out_rofireMux_T_600 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[85], _out_rofireMux_T_604 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[86], _out_rofireMux_T_608 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[87], _out_rofireMux_T_612 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[88], _out_rofireMux_T_616 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[89], _out_rofireMux_T_620 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[90], _out_rofireMux_T_624 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[91], _out_rofireMux_T_628 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[92], _out_rofireMux_T_632 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[93], _out_rofireMux_T_636 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[94], _out_rofireMux_T_640 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[95], _out_rofireMux_T_644 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[96], _out_rofireMux_T_648 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[97], _out_rofireMux_T_652 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[98], _out_rofireMux_T_656 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[99], _out_rofireMux_T_660 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[100], _out_rofireMux_T_664 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[101], _out_rofireMux_T_668 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[102], _out_rofireMux_T_672 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[103], _out_rofireMux_T_676 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[104], _out_rofireMux_T_680 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[105], _out_rofireMux_T_684 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[106], _out_rofireMux_T_688 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[107], _out_rofireMux_T_692 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[108], _out_rofireMux_T_696 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[109], _out_rofireMux_T_700 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[110], _out_rofireMux_T_704 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[111], _out_rofireMux_T_708 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[112], _out_rofireMux_T_712 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[113], _out_rofireMux_T_716 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[114], _out_rofireMux_T_720 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[115], _out_rofireMux_T_724 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[116], _out_rofireMux_T_728 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[117], _out_rofireMux_T_732 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[118], _out_rofireMux_T_736 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[119], _out_rofireMux_T_740 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[120], _out_rofireMux_T_744 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[121], _out_rofireMux_T_748 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[122], _out_rofireMux_T_752 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[123], _out_rofireMux_T_756 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[124], _out_rofireMux_T_760 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[125], _out_rofireMux_T_764 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[126], _out_rofireMux_T_768 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[127], _out_rofireMux_T_772 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[128], _out_rofireMux_T_776 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[129], _out_rofireMux_T_780 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[130], _out_rofireMux_T_784 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[131], _out_rofireMux_T_788 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[132], _out_rofireMux_T_792 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[133], _out_rofireMux_T_796 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[134], _out_rofireMux_T_800 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[135], _out_rofireMux_T_804 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[136], _out_rofireMux_T_808 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[137], _out_rofireMux_T_812 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[138], _out_rofireMux_T_816 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[139], _out_rofireMux_T_820 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[140], _out_rofireMux_T_824 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[141], _out_rofireMux_T_828 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[142], _out_rofireMux_T_832 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[143], _out_rofireMux_T_836 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[144], _out_rofireMux_T_840 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[145], _out_rofireMux_T_844 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[146], _out_rofireMux_T_848 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[147], _out_rofireMux_T_852 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[148], _out_rofireMux_T_856 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[149], _out_rofireMux_T_860 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[150], _out_rofireMux_T_864 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[151], _out_rofireMux_T_868 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[152], _out_rofireMux_T_872 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[153], _out_rofireMux_T_876 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[154], _out_rofireMux_T_880 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[155], _out_rofireMux_T_884 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[156], _out_rofireMux_T_888 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[157], _out_rofireMux_T_892 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[158], _out_rofireMux_T_896 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[159], _out_rofireMux_T_900 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[160], _out_rofireMux_T_904 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[161], _out_rofireMux_T_908 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[162], _out_rofireMux_T_912 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[163], _out_rofireMux_T_916 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[164], _out_rofireMux_T_920 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[165], _out_rofireMux_T_924 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[166], _out_rofireMux_T_928 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[167], _out_rofireMux_T_932 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[168], _out_rofireMux_T_936 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[169], _out_rofireMux_T_940 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[170], _out_rofireMux_T_944 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[171], _out_rofireMux_T_948 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[172], _out_rofireMux_T_952 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[173], _out_rofireMux_T_956 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[174], _out_rofireMux_T_960 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[175], _out_rofireMux_T_964 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[176], _out_rofireMux_T_968 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[177], _out_rofireMux_T_972 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[178], _out_rofireMux_T_976 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[179], _out_rofireMux_T_980 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[180], _out_rofireMux_T_984 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[181], _out_rofireMux_T_988 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[182], _out_rofireMux_T_992 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[183], _out_rofireMux_T_996 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[184], _out_rofireMux_T_1000 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[185], _out_rofireMux_T_1004 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[186], _out_rofireMux_T_1008 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[187], _out_rofireMux_T_1012 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[188], _out_rofireMux_T_1016 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[189], _out_rofireMux_T_1020 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[190], _out_rofireMux_T_1024 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[191], _out_rofireMux_T_1028 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[192], _out_rofireMux_T_1032 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[193], _out_rofireMux_T_1036 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[194], _out_rofireMux_T_1040 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[195], _out_rofireMux_T_1044 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[196], _out_rofireMux_T_1048 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[197], _out_rofireMux_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[198], _out_rofireMux_T_1056 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[199], _out_rofireMux_T_1060 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[200], _out_rofireMux_T_1064 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[201], _out_rofireMux_T_1068 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[202], _out_rofireMux_T_1072 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[203], _out_rofireMux_T_1076 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[204], _out_rofireMux_T_1080 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[205], _out_rofireMux_T_1084 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[206], _out_rofireMux_T_1088 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[207], _out_rofireMux_T_1092 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[208], _out_rofireMux_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[209], _out_rofireMux_T_1100 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[210], _out_rofireMux_T_1104 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[211], _out_rofireMux_T_1108 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[212], _out_rofireMux_T_1112 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[213], _out_rofireMux_T_1116 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[214], _out_rofireMux_T_1120 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[215], _out_rofireMux_T_1124 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[216], _out_rofireMux_T_1128 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[217], _out_rofireMux_T_1132 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[218], _out_rofireMux_T_1136 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[219], _out_rofireMux_T_1140 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[220], _out_rofireMux_T_1144 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[221], _out_rofireMux_T_1148 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[222], _out_rofireMux_T_1152 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[223], _out_rofireMux_T_1156 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[224], _out_rofireMux_T_1160 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[225], _out_rofireMux_T_1164 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[226], _out_rofireMux_T_1168 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[227], _out_rofireMux_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[228], _out_rofireMux_T_1176 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[229], _out_rofireMux_T_1180 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[230], _out_rofireMux_T_1184 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[231], _out_rofireMux_T_1188 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[232], _out_rofireMux_T_1192 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[233], _out_rofireMux_T_1196 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[234], _out_rofireMux_T_1200 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[235], _out_rofireMux_T_1204 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[236], _out_rofireMux_T_1208 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[237], _out_rofireMux_T_1212 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[238], _out_rofireMux_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[239], _out_rofireMux_T_1220 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[240], _out_rofireMux_T_1224 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[241], _out_rofireMux_T_1228 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[242], _out_rofireMux_T_1232 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[243], _out_rofireMux_T_1236 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[244], _out_rofireMux_T_1240 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[245], _out_rofireMux_T_1244 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[246], _out_rofireMux_T_1248 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[247], _out_rofireMux_T_1252 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[248], _out_rofireMux_T_1256 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[249], _out_rofireMux_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[250], _out_rofireMux_T_1264 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[251], _out_rofireMux_T_1268 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[252], _out_rofireMux_T_1272 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[253], _out_rofireMux_T_1276 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[254], _out_rofireMux_T_1280 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE_1[255], _out_rofireMux_T_1284 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_rofireMux_1 = mux(_out_rofireMux_T_1285, UInt<1>(0h1), _out_rofireMux_WIRE_1[out_oindex_1]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_wofireMux_T_260 = and(out_front_1.valid, out_1.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_261 = eq(out_front_1.bits.read, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_262 = and(_out_wofireMux_T_260, _out_wofireMux_T_261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_64 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_263 = and(_out_wofireMux_T_262, out_backSel_0_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_264 = and(_out_wofireMux_T_263, _out_T_1439) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_64, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[450], _out_wofireMux_T_264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[449], _out_wofireMux_T_264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[448], _out_wofireMux_T_264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[447], _out_wofireMux_T_264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[446], _out_wofireMux_T_264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[445], _out_wofireMux_T_264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[444], _out_wofireMux_T_264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[443], _out_wofireMux_T_264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_265 = eq(_out_T_1439, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_266 = or(out_wofireMux_out_64, _out_wofireMux_T_265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_65 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_267 = and(_out_wofireMux_T_262, out_backSel_1_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_268 = and(_out_wofireMux_T_267, _out_T_1347) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_65, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[95], _out_wofireMux_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[94], _out_wofireMux_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[93], _out_wofireMux_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[92], _out_wofireMux_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[91], _out_wofireMux_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[90], _out_wofireMux_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[89], _out_wofireMux_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[88], _out_wofireMux_T_268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_269 = eq(_out_T_1347, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_270 = or(out_wofireMux_out_65, _out_wofireMux_T_269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_66 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_271 = and(_out_wofireMux_T_262, out_backSel_2_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_272 = and(_out_wofireMux_T_271, _out_T_1567) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_66, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[946], _out_wofireMux_T_272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[945], _out_wofireMux_T_272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[944], _out_wofireMux_T_272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[943], _out_wofireMux_T_272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[942], _out_wofireMux_T_272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[941], _out_wofireMux_T_272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[940], _out_wofireMux_T_272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[939], _out_wofireMux_T_272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_273 = eq(_out_T_1567, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_274 = or(out_wofireMux_out_66, _out_wofireMux_T_273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_67 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_275 = and(_out_wofireMux_T_262, out_backSel_3_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_276 = and(_out_wofireMux_T_275, _out_T_1479) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_67, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[600], _out_wofireMux_T_276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[599], _out_wofireMux_T_276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[598], _out_wofireMux_T_276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[597], _out_wofireMux_T_276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[596], _out_wofireMux_T_276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[595], _out_wofireMux_T_276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[594], _out_wofireMux_T_276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[593], _out_wofireMux_T_276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_277 = eq(_out_T_1479, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_278 = or(out_wofireMux_out_67, _out_wofireMux_T_277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_68 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_279 = and(_out_wofireMux_T_262, out_backSel_4_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_280 = and(_out_wofireMux_T_279, _out_T_1401) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_68, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[311], _out_wofireMux_T_280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[310], _out_wofireMux_T_280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[309], _out_wofireMux_T_280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[308], _out_wofireMux_T_280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[307], _out_wofireMux_T_280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[306], _out_wofireMux_T_280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[305], _out_wofireMux_T_280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[304], _out_wofireMux_T_280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_281 = eq(_out_T_1401, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_282 = or(out_wofireMux_out_68, _out_wofireMux_T_281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_69 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_283 = and(_out_wofireMux_T_262, out_backSel_5_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_284 = and(_out_wofireMux_T_283, _out_T_1363) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_69, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[159], _out_wofireMux_T_284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[158], _out_wofireMux_T_284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[157], _out_wofireMux_T_284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[156], _out_wofireMux_T_284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[155], _out_wofireMux_T_284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[154], _out_wofireMux_T_284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[153], _out_wofireMux_T_284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[152], _out_wofireMux_T_284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_285 = eq(_out_T_1363, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_286 = or(out_wofireMux_out_69, _out_wofireMux_T_285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_70 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_287 = and(_out_wofireMux_T_262, out_backSel_6_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_288 = and(_out_wofireMux_T_287, _out_T_1595) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_70, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1058], _out_wofireMux_T_288 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1057], _out_wofireMux_T_288 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1056], _out_wofireMux_T_288 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1055], _out_wofireMux_T_288 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1054], _out_wofireMux_T_288 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1053], _out_wofireMux_T_288 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1052], _out_wofireMux_T_288 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1051], _out_wofireMux_T_288 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_289 = eq(_out_T_1595, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_290 = or(out_wofireMux_out_70, _out_wofireMux_T_289) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_71 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_291 = and(_out_wofireMux_T_262, out_backSel_7_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_292 = and(_out_wofireMux_T_291, _out_T_1543) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_71, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[850], _out_wofireMux_T_292 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[849], _out_wofireMux_T_292 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[848], _out_wofireMux_T_292 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[847], _out_wofireMux_T_292 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[846], _out_wofireMux_T_292 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[845], _out_wofireMux_T_292 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[844], _out_wofireMux_T_292 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[843], _out_wofireMux_T_292 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_293 = eq(_out_T_1543, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_294 = or(out_wofireMux_out_71, _out_wofireMux_T_293) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_72 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_295 = and(_out_wofireMux_T_262, out_backSel_8_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_296 = and(_out_wofireMux_T_295, _out_T_1465) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_72, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[544], _out_wofireMux_T_296 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[543], _out_wofireMux_T_296 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[542], _out_wofireMux_T_296 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[541], _out_wofireMux_T_296 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[540], _out_wofireMux_T_296 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[539], _out_wofireMux_T_296 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[538], _out_wofireMux_T_296 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[537], _out_wofireMux_T_296 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_297 = eq(_out_T_1465, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_298 = or(out_wofireMux_out_72, _out_wofireMux_T_297) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_73 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_299 = and(_out_wofireMux_T_262, out_backSel_9_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_300 = and(_out_wofireMux_T_299, _out_T_1389) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_73, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[263], _out_wofireMux_T_300 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[262], _out_wofireMux_T_300 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[261], _out_wofireMux_T_300 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[260], _out_wofireMux_T_300 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[259], _out_wofireMux_T_300 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[258], _out_wofireMux_T_300 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[257], _out_wofireMux_T_300 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[256], _out_wofireMux_T_300 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_301 = eq(_out_T_1389, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_302 = or(out_wofireMux_out_73, _out_wofireMux_T_301) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_74 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_303 = and(_out_wofireMux_T_262, out_backSel_10_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_304 = and(_out_wofireMux_T_303, _out_T_1447) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_74, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[478], _out_wofireMux_T_304 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[477], _out_wofireMux_T_304 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[476], _out_wofireMux_T_304 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[475], _out_wofireMux_T_304 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_305 = eq(_out_T_1447, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_306 = or(out_wofireMux_out_74, _out_wofireMux_T_305) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_75 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_307 = and(_out_wofireMux_T_262, out_backSel_11_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_308 = and(_out_wofireMux_T_307, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_75, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_309 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_310 = or(out_wofireMux_out_75, _out_wofireMux_T_309) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_76 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_311 = and(_out_wofireMux_T_262, out_backSel_12_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_312 = and(_out_wofireMux_T_311, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_76, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_313 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_314 = or(out_wofireMux_out_76, _out_wofireMux_T_313) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_77 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_315 = and(_out_wofireMux_T_262, out_backSel_13_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_316 = and(_out_wofireMux_T_315, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_77, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_317 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_318 = or(out_wofireMux_out_77, _out_wofireMux_T_317) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_78 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_319 = and(_out_wofireMux_T_262, out_backSel_14_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_320 = and(_out_wofireMux_T_319, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_78, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_321 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_322 = or(out_wofireMux_out_78, _out_wofireMux_T_321) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_79 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_323 = and(_out_wofireMux_T_262, out_backSel_15_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_324 = and(_out_wofireMux_T_323, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_79, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_325 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_326 = or(out_wofireMux_out_79, _out_wofireMux_T_325) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_80 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_327 = and(_out_wofireMux_T_262, out_backSel_16_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_328 = and(_out_wofireMux_T_327, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_80, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_329 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_330 = or(out_wofireMux_out_80, _out_wofireMux_T_329) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_81 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_331 = and(_out_wofireMux_T_262, out_backSel_17_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_332 = and(_out_wofireMux_T_331, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_81, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_333 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_334 = or(out_wofireMux_out_81, _out_wofireMux_T_333) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_82 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_335 = and(_out_wofireMux_T_262, out_backSel_18_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_336 = and(_out_wofireMux_T_335, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_82, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_337 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_338 = or(out_wofireMux_out_82, _out_wofireMux_T_337) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_83 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_339 = and(_out_wofireMux_T_262, out_backSel_19_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_340 = and(_out_wofireMux_T_339, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_83, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_341 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_342 = or(out_wofireMux_out_83, _out_wofireMux_T_341) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_84 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_343 = and(_out_wofireMux_T_262, out_backSel_20_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_344 = and(_out_wofireMux_T_343, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_84, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_345 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_346 = or(out_wofireMux_out_84, _out_wofireMux_T_345) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_85 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_347 = and(_out_wofireMux_T_262, out_backSel_21_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_348 = and(_out_wofireMux_T_347, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_85, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_349 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_350 = or(out_wofireMux_out_85, _out_wofireMux_T_349) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_86 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_351 = and(_out_wofireMux_T_262, out_backSel_22_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_352 = and(_out_wofireMux_T_351, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_86, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_353 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_354 = or(out_wofireMux_out_86, _out_wofireMux_T_353) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_87 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_355 = and(_out_wofireMux_T_262, out_backSel_23_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_356 = and(_out_wofireMux_T_355, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_87, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_357 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_358 = or(out_wofireMux_out_87, _out_wofireMux_T_357) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_88 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_359 = and(_out_wofireMux_T_262, out_backSel_24_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_360 = and(_out_wofireMux_T_359, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_88, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_361 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_362 = or(out_wofireMux_out_88, _out_wofireMux_T_361) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_89 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_363 = and(_out_wofireMux_T_262, out_backSel_25_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_364 = and(_out_wofireMux_T_363, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_89, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_365 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_366 = or(out_wofireMux_out_89, _out_wofireMux_T_365) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_90 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_367 = and(_out_wofireMux_T_262, out_backSel_26_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_368 = and(_out_wofireMux_T_367, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_90, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_369 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_370 = or(out_wofireMux_out_90, _out_wofireMux_T_369) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_91 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_371 = and(_out_wofireMux_T_262, out_backSel_27_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_372 = and(_out_wofireMux_T_371, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_91, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_373 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_374 = or(out_wofireMux_out_91, _out_wofireMux_T_373) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_92 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_375 = and(_out_wofireMux_T_262, out_backSel_28_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_376 = and(_out_wofireMux_T_375, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_92, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_377 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_378 = or(out_wofireMux_out_92, _out_wofireMux_T_377) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_93 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_379 = and(_out_wofireMux_T_262, out_backSel_29_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_380 = and(_out_wofireMux_T_379, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_93, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_381 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_382 = or(out_wofireMux_out_93, _out_wofireMux_T_381) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_94 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_383 = and(_out_wofireMux_T_262, out_backSel_30_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_384 = and(_out_wofireMux_T_383, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_94, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_385 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_386 = or(out_wofireMux_out_94, _out_wofireMux_T_385) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_95 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_387 = and(_out_wofireMux_T_262, out_backSel_31_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_388 = and(_out_wofireMux_T_387, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_95, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_389 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_390 = or(out_wofireMux_out_95, _out_wofireMux_T_389) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_96 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_391 = and(_out_wofireMux_T_262, out_backSel_32_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_392 = and(_out_wofireMux_T_391, _out_T_1461) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_96, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[528], _out_wofireMux_T_392 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[527], _out_wofireMux_T_392 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_393 = eq(_out_T_1461, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_394 = or(out_wofireMux_out_96, _out_wofireMux_T_393) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_97 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_395 = and(_out_wofireMux_T_262, out_backSel_33_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_396 = and(_out_wofireMux_T_395, _out_T_1411) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_97, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[345], _out_wofireMux_T_396 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[344], _out_wofireMux_T_396 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_397 = eq(_out_T_1411, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_398 = or(out_wofireMux_out_97, _out_wofireMux_T_397) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_98 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_399 = and(_out_wofireMux_T_262, out_backSel_34_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_400 = and(_out_wofireMux_T_399, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_98, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_401 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_402 = or(out_wofireMux_out_98, _out_wofireMux_T_401) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_99 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_403 = and(_out_wofireMux_T_262, out_backSel_35_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_404 = and(_out_wofireMux_T_403, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_99, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_405 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_406 = or(out_wofireMux_out_99, _out_wofireMux_T_405) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_100 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_407 = and(_out_wofireMux_T_262, out_backSel_36_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_408 = and(_out_wofireMux_T_407, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_100, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_409 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_410 = or(out_wofireMux_out_100, _out_wofireMux_T_409) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_101 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_411 = and(_out_wofireMux_T_262, out_backSel_37_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_412 = and(_out_wofireMux_T_411, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_101, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_413 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_414 = or(out_wofireMux_out_101, _out_wofireMux_T_413) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_102 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_415 = and(_out_wofireMux_T_262, out_backSel_38_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_416 = and(_out_wofireMux_T_415, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_102, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_417 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_418 = or(out_wofireMux_out_102, _out_wofireMux_T_417) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_103 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_419 = and(_out_wofireMux_T_262, out_backSel_39_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_420 = and(_out_wofireMux_T_419, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_103, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_421 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_422 = or(out_wofireMux_out_103, _out_wofireMux_T_421) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_104 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_423 = and(_out_wofireMux_T_262, out_backSel_40_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_424 = and(_out_wofireMux_T_423, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_104, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_425 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_426 = or(out_wofireMux_out_104, _out_wofireMux_T_425) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_105 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_427 = and(_out_wofireMux_T_262, out_backSel_41_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_428 = and(_out_wofireMux_T_427, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_105, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_429 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_430 = or(out_wofireMux_out_105, _out_wofireMux_T_429) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_106 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_431 = and(_out_wofireMux_T_262, out_backSel_42_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_432 = and(_out_wofireMux_T_431, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_106, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_433 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_434 = or(out_wofireMux_out_106, _out_wofireMux_T_433) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_107 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_435 = and(_out_wofireMux_T_262, out_backSel_43_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_436 = and(_out_wofireMux_T_435, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_107, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_437 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_438 = or(out_wofireMux_out_107, _out_wofireMux_T_437) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_108 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_439 = and(_out_wofireMux_T_262, out_backSel_44_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_440 = and(_out_wofireMux_T_439, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_108, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_441 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_442 = or(out_wofireMux_out_108, _out_wofireMux_T_441) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_109 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_443 = and(_out_wofireMux_T_262, out_backSel_45_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_444 = and(_out_wofireMux_T_443, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_109, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_445 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_446 = or(out_wofireMux_out_109, _out_wofireMux_T_445) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_110 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_447 = and(_out_wofireMux_T_262, out_backSel_46_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_448 = and(_out_wofireMux_T_447, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_110, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_449 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_450 = or(out_wofireMux_out_110, _out_wofireMux_T_449) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_111 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_451 = and(_out_wofireMux_T_262, out_backSel_47_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_452 = and(_out_wofireMux_T_451, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_111, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_453 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_454 = or(out_wofireMux_out_111, _out_wofireMux_T_453) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_112 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_455 = and(_out_wofireMux_T_262, out_backSel_48_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_456 = and(_out_wofireMux_T_455, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_112, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_457 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_458 = or(out_wofireMux_out_112, _out_wofireMux_T_457) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_113 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_459 = and(_out_wofireMux_T_262, out_backSel_49_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_460 = and(_out_wofireMux_T_459, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_113, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_461 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_462 = or(out_wofireMux_out_113, _out_wofireMux_T_461) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_114 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_463 = and(_out_wofireMux_T_262, out_backSel_50_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_464 = and(_out_wofireMux_T_463, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_114, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_465 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_466 = or(out_wofireMux_out_114, _out_wofireMux_T_465) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_115 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_467 = and(_out_wofireMux_T_262, out_backSel_51_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_468 = and(_out_wofireMux_T_467, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_115, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_469 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_470 = or(out_wofireMux_out_115, _out_wofireMux_T_469) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_116 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_471 = and(_out_wofireMux_T_262, out_backSel_52_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_472 = and(_out_wofireMux_T_471, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_116, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_473 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_474 = or(out_wofireMux_out_116, _out_wofireMux_T_473) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_117 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_475 = and(_out_wofireMux_T_262, out_backSel_53_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_476 = and(_out_wofireMux_T_475, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_117, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_477 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_478 = or(out_wofireMux_out_117, _out_wofireMux_T_477) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_118 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_479 = and(_out_wofireMux_T_262, out_backSel_54_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_480 = and(_out_wofireMux_T_479, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_118, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_481 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_482 = or(out_wofireMux_out_118, _out_wofireMux_T_481) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_119 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_483 = and(_out_wofireMux_T_262, out_backSel_55_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_484 = and(_out_wofireMux_T_483, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_119, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_485 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_486 = or(out_wofireMux_out_119, _out_wofireMux_T_485) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_120 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_487 = and(_out_wofireMux_T_262, out_backSel_56_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_488 = and(_out_wofireMux_T_487, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_120, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_489 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_490 = or(out_wofireMux_out_120, _out_wofireMux_T_489) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_121 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_491 = and(_out_wofireMux_T_262, out_backSel_57_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_492 = and(_out_wofireMux_T_491, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_121, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_493 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_494 = or(out_wofireMux_out_121, _out_wofireMux_T_493) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_122 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_495 = and(_out_wofireMux_T_262, out_backSel_58_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_496 = and(_out_wofireMux_T_495, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_122, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_497 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_498 = or(out_wofireMux_out_122, _out_wofireMux_T_497) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_123 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_499 = and(_out_wofireMux_T_262, out_backSel_59_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_500 = and(_out_wofireMux_T_499, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_123, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_501 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_502 = or(out_wofireMux_out_123, _out_wofireMux_T_501) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_124 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_503 = and(_out_wofireMux_T_262, out_backSel_60_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_504 = and(_out_wofireMux_T_503, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_124, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_505 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_506 = or(out_wofireMux_out_124, _out_wofireMux_T_505) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_125 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_507 = and(_out_wofireMux_T_262, out_backSel_61_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_508 = and(_out_wofireMux_T_507, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_125, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_509 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_510 = or(out_wofireMux_out_125, _out_wofireMux_T_509) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_126 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_511 = and(_out_wofireMux_T_262, out_backSel_62_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_512 = and(_out_wofireMux_T_511, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_126, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_513 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_514 = or(out_wofireMux_out_126, _out_wofireMux_T_513) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_127 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_515 = and(_out_wofireMux_T_262, out_backSel_63_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_516 = and(_out_wofireMux_T_515, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_127, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_517 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_518 = or(out_wofireMux_out_127, _out_wofireMux_T_517) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_128 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_519 = and(_out_wofireMux_T_262, out_backSel_64) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_520 = and(_out_wofireMux_T_519, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_128, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_521 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_522 = or(out_wofireMux_out_128, _out_wofireMux_T_521) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_129 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_523 = and(_out_wofireMux_T_262, out_backSel_65) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_524 = and(_out_wofireMux_T_523, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_129, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_525 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_526 = or(out_wofireMux_out_129, _out_wofireMux_T_525) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_130 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_527 = and(_out_wofireMux_T_262, out_backSel_66) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_528 = and(_out_wofireMux_T_527, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_130, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_529 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_530 = or(out_wofireMux_out_130, _out_wofireMux_T_529) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_131 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_531 = and(_out_wofireMux_T_262, out_backSel_67) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_532 = and(_out_wofireMux_T_531, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_131, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_533 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_534 = or(out_wofireMux_out_131, _out_wofireMux_T_533) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_132 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_535 = and(_out_wofireMux_T_262, out_backSel_68) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_536 = and(_out_wofireMux_T_535, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_132, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_537 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_538 = or(out_wofireMux_out_132, _out_wofireMux_T_537) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_133 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_539 = and(_out_wofireMux_T_262, out_backSel_69) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_540 = and(_out_wofireMux_T_539, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_133, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_541 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_542 = or(out_wofireMux_out_133, _out_wofireMux_T_541) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_134 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_543 = and(_out_wofireMux_T_262, out_backSel_70) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_544 = and(_out_wofireMux_T_543, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_134, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_545 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_546 = or(out_wofireMux_out_134, _out_wofireMux_T_545) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_135 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_547 = and(_out_wofireMux_T_262, out_backSel_71) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_548 = and(_out_wofireMux_T_547, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_135, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_549 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_550 = or(out_wofireMux_out_135, _out_wofireMux_T_549) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_136 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_551 = and(_out_wofireMux_T_262, out_backSel_72) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_552 = and(_out_wofireMux_T_551, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_136, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_553 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_554 = or(out_wofireMux_out_136, _out_wofireMux_T_553) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_137 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_555 = and(_out_wofireMux_T_262, out_backSel_73) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_556 = and(_out_wofireMux_T_555, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_137, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_557 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_558 = or(out_wofireMux_out_137, _out_wofireMux_T_557) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_138 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_559 = and(_out_wofireMux_T_262, out_backSel_74) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_560 = and(_out_wofireMux_T_559, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_138, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_561 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_562 = or(out_wofireMux_out_138, _out_wofireMux_T_561) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_139 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_563 = and(_out_wofireMux_T_262, out_backSel_75) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_564 = and(_out_wofireMux_T_563, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_139, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_565 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_566 = or(out_wofireMux_out_139, _out_wofireMux_T_565) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_140 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_567 = and(_out_wofireMux_T_262, out_backSel_76) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_568 = and(_out_wofireMux_T_567, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_140, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_569 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_570 = or(out_wofireMux_out_140, _out_wofireMux_T_569) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_141 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_571 = and(_out_wofireMux_T_262, out_backSel_77) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_572 = and(_out_wofireMux_T_571, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_141, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_573 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_574 = or(out_wofireMux_out_141, _out_wofireMux_T_573) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_142 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_575 = and(_out_wofireMux_T_262, out_backSel_78) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_576 = and(_out_wofireMux_T_575, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_142, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_577 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_578 = or(out_wofireMux_out_142, _out_wofireMux_T_577) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_143 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_579 = and(_out_wofireMux_T_262, out_backSel_79) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_580 = and(_out_wofireMux_T_579, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_143, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_581 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_582 = or(out_wofireMux_out_143, _out_wofireMux_T_581) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_144 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_583 = and(_out_wofireMux_T_262, out_backSel_80) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_584 = and(_out_wofireMux_T_583, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_144, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_585 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_586 = or(out_wofireMux_out_144, _out_wofireMux_T_585) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_145 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_587 = and(_out_wofireMux_T_262, out_backSel_81) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_588 = and(_out_wofireMux_T_587, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_145, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_589 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_590 = or(out_wofireMux_out_145, _out_wofireMux_T_589) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_146 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_591 = and(_out_wofireMux_T_262, out_backSel_82) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_592 = and(_out_wofireMux_T_591, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_146, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_593 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_594 = or(out_wofireMux_out_146, _out_wofireMux_T_593) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_147 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_595 = and(_out_wofireMux_T_262, out_backSel_83) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_596 = and(_out_wofireMux_T_595, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_147, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_597 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_598 = or(out_wofireMux_out_147, _out_wofireMux_T_597) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_148 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_599 = and(_out_wofireMux_T_262, out_backSel_84) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_600 = and(_out_wofireMux_T_599, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_148, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_601 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_602 = or(out_wofireMux_out_148, _out_wofireMux_T_601) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_149 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_603 = and(_out_wofireMux_T_262, out_backSel_85) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_604 = and(_out_wofireMux_T_603, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_149, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_605 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_606 = or(out_wofireMux_out_149, _out_wofireMux_T_605) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_150 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_607 = and(_out_wofireMux_T_262, out_backSel_86) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_608 = and(_out_wofireMux_T_607, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_150, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_609 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_610 = or(out_wofireMux_out_150, _out_wofireMux_T_609) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_151 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_611 = and(_out_wofireMux_T_262, out_backSel_87) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_612 = and(_out_wofireMux_T_611, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_151, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_613 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_614 = or(out_wofireMux_out_151, _out_wofireMux_T_613) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_152 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_615 = and(_out_wofireMux_T_262, out_backSel_88) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_616 = and(_out_wofireMux_T_615, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_152, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_617 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_618 = or(out_wofireMux_out_152, _out_wofireMux_T_617) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_153 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_619 = and(_out_wofireMux_T_262, out_backSel_89) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_620 = and(_out_wofireMux_T_619, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_153, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_621 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_622 = or(out_wofireMux_out_153, _out_wofireMux_T_621) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_154 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_623 = and(_out_wofireMux_T_262, out_backSel_90) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_624 = and(_out_wofireMux_T_623, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_154, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_625 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_626 = or(out_wofireMux_out_154, _out_wofireMux_T_625) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_155 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_627 = and(_out_wofireMux_T_262, out_backSel_91) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_628 = and(_out_wofireMux_T_627, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_155, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_629 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_630 = or(out_wofireMux_out_155, _out_wofireMux_T_629) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_156 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_631 = and(_out_wofireMux_T_262, out_backSel_92) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_632 = and(_out_wofireMux_T_631, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_156, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_633 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_634 = or(out_wofireMux_out_156, _out_wofireMux_T_633) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_157 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_635 = and(_out_wofireMux_T_262, out_backSel_93) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_636 = and(_out_wofireMux_T_635, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_157, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_637 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_638 = or(out_wofireMux_out_157, _out_wofireMux_T_637) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_158 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_639 = and(_out_wofireMux_T_262, out_backSel_94) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_640 = and(_out_wofireMux_T_639, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_158, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_641 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_642 = or(out_wofireMux_out_158, _out_wofireMux_T_641) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_159 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_643 = and(_out_wofireMux_T_262, out_backSel_95) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_644 = and(_out_wofireMux_T_643, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_159, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_645 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_646 = or(out_wofireMux_out_159, _out_wofireMux_T_645) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_160 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_647 = and(_out_wofireMux_T_262, out_backSel_96) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_648 = and(_out_wofireMux_T_647, _out_T_1435) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_160, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[434], _out_wofireMux_T_648 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_649 = eq(_out_T_1435, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_650 = or(out_wofireMux_out_160, _out_wofireMux_T_649) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_161 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_651 = and(_out_wofireMux_T_262, out_backSel_97) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_652 = and(_out_wofireMux_T_651, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_161, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_653 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_654 = or(out_wofireMux_out_161, _out_wofireMux_T_653) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_162 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_655 = and(_out_wofireMux_T_262, out_backSel_98) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_656 = and(_out_wofireMux_T_655, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_162, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_657 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_658 = or(out_wofireMux_out_162, _out_wofireMux_T_657) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_163 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_659 = and(_out_wofireMux_T_262, out_backSel_99) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_660 = and(_out_wofireMux_T_659, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_163, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_661 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_662 = or(out_wofireMux_out_163, _out_wofireMux_T_661) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_164 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_663 = and(_out_wofireMux_T_262, out_backSel_100) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_664 = and(_out_wofireMux_T_663, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_164, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_665 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_666 = or(out_wofireMux_out_164, _out_wofireMux_T_665) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_165 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_667 = and(_out_wofireMux_T_262, out_backSel_101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_668 = and(_out_wofireMux_T_667, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_165, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_669 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_670 = or(out_wofireMux_out_165, _out_wofireMux_T_669) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_166 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_671 = and(_out_wofireMux_T_262, out_backSel_102) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_672 = and(_out_wofireMux_T_671, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_166, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_673 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_674 = or(out_wofireMux_out_166, _out_wofireMux_T_673) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_167 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_675 = and(_out_wofireMux_T_262, out_backSel_103) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_676 = and(_out_wofireMux_T_675, _out_T_1501) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_167, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[682], _out_wofireMux_T_676 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[681], _out_wofireMux_T_676 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_677 = eq(_out_T_1501, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_678 = or(out_wofireMux_out_167, _out_wofireMux_T_677) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_168 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_679 = and(_out_wofireMux_T_262, out_backSel_104) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_680 = and(_out_wofireMux_T_679, _out_T_1561) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_168, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[922], _out_wofireMux_T_680 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[921], _out_wofireMux_T_680 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[920], _out_wofireMux_T_680 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[919], _out_wofireMux_T_680 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[918], _out_wofireMux_T_680 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[917], _out_wofireMux_T_680 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[916], _out_wofireMux_T_680 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[915], _out_wofireMux_T_680 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_681 = eq(_out_T_1561, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_682 = or(out_wofireMux_out_168, _out_wofireMux_T_681) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_169 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_683 = and(_out_wofireMux_T_262, out_backSel_105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_684 = and(_out_wofireMux_T_683, _out_T_1455) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_169, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[510], _out_wofireMux_T_684 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[509], _out_wofireMux_T_684 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[508], _out_wofireMux_T_684 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[507], _out_wofireMux_T_684 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[506], _out_wofireMux_T_684 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[505], _out_wofireMux_T_684 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[504], _out_wofireMux_T_684 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[503], _out_wofireMux_T_684 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_685 = eq(_out_T_1455, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_686 = or(out_wofireMux_out_169, _out_wofireMux_T_685) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_170 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_687 = and(_out_wofireMux_T_262, out_backSel_106) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_688 = and(_out_wofireMux_T_687, _out_T_1371) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_170, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[191], _out_wofireMux_T_688 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[190], _out_wofireMux_T_688 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[189], _out_wofireMux_T_688 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[188], _out_wofireMux_T_688 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[187], _out_wofireMux_T_688 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[186], _out_wofireMux_T_688 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[185], _out_wofireMux_T_688 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[184], _out_wofireMux_T_688 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_689 = eq(_out_T_1371, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_690 = or(out_wofireMux_out_170, _out_wofireMux_T_689) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_171 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_691 = and(_out_wofireMux_T_262, out_backSel_107) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_692 = and(_out_wofireMux_T_691, _out_T_1599) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_171, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1074], _out_wofireMux_T_692 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1073], _out_wofireMux_T_692 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1072], _out_wofireMux_T_692 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1071], _out_wofireMux_T_692 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1070], _out_wofireMux_T_692 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1069], _out_wofireMux_T_692 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1068], _out_wofireMux_T_692 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1067], _out_wofireMux_T_692 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_693 = eq(_out_T_1599, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_694 = or(out_wofireMux_out_171, _out_wofireMux_T_693) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_172 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_695 = and(_out_wofireMux_T_262, out_backSel_108) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_696 = and(_out_wofireMux_T_695, _out_T_1511) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_172, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[722], _out_wofireMux_T_696 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[721], _out_wofireMux_T_696 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[720], _out_wofireMux_T_696 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[719], _out_wofireMux_T_696 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[718], _out_wofireMux_T_696 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[717], _out_wofireMux_T_696 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[716], _out_wofireMux_T_696 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[715], _out_wofireMux_T_696 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_697 = eq(_out_T_1511, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_698 = or(out_wofireMux_out_172, _out_wofireMux_T_697) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_173 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_699 = and(_out_wofireMux_T_262, out_backSel_109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_700 = and(_out_wofireMux_T_699, _out_T_1437) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_173, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[442], _out_wofireMux_T_700 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[441], _out_wofireMux_T_700 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[440], _out_wofireMux_T_700 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[439], _out_wofireMux_T_700 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[438], _out_wofireMux_T_700 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[437], _out_wofireMux_T_700 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[436], _out_wofireMux_T_700 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[435], _out_wofireMux_T_700 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_701 = eq(_out_T_1437, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_702 = or(out_wofireMux_out_173, _out_wofireMux_T_701) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_174 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_703 = and(_out_wofireMux_T_262, out_backSel_110) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_704 = and(_out_wofireMux_T_703, _out_T_1351) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_174, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[111], _out_wofireMux_T_704 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[110], _out_wofireMux_T_704 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[109], _out_wofireMux_T_704 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[108], _out_wofireMux_T_704 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[107], _out_wofireMux_T_704 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[106], _out_wofireMux_T_704 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[105], _out_wofireMux_T_704 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[104], _out_wofireMux_T_704 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_705 = eq(_out_T_1351, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_706 = or(out_wofireMux_out_174, _out_wofireMux_T_705) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_175 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_707 = and(_out_wofireMux_T_262, out_backSel_111) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_708 = and(_out_wofireMux_T_707, _out_T_1617) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_175, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1146], _out_wofireMux_T_708 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1145], _out_wofireMux_T_708 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1144], _out_wofireMux_T_708 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1143], _out_wofireMux_T_708 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1142], _out_wofireMux_T_708 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1141], _out_wofireMux_T_708 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1140], _out_wofireMux_T_708 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1139], _out_wofireMux_T_708 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_709 = eq(_out_T_1617, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_710 = or(out_wofireMux_out_175, _out_wofireMux_T_709) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_176 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_711 = and(_out_wofireMux_T_262, out_backSel_112) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_712 = and(_out_wofireMux_T_711, _out_T_1535) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_176, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[818], _out_wofireMux_T_712 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[817], _out_wofireMux_T_712 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[816], _out_wofireMux_T_712 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[815], _out_wofireMux_T_712 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[814], _out_wofireMux_T_712 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[813], _out_wofireMux_T_712 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[812], _out_wofireMux_T_712 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[811], _out_wofireMux_T_712 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_713 = eq(_out_T_1535, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_714 = or(out_wofireMux_out_176, _out_wofireMux_T_713) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_177 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_715 = and(_out_wofireMux_T_262, out_backSel_113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_716 = and(_out_wofireMux_T_715, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_177, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_717 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_718 = or(out_wofireMux_out_177, _out_wofireMux_T_717) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_178 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_719 = and(_out_wofireMux_T_262, out_backSel_114) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_720 = and(_out_wofireMux_T_719, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_178, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_721 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_722 = or(out_wofireMux_out_178, _out_wofireMux_T_721) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_179 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_723 = and(_out_wofireMux_T_262, out_backSel_115) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_724 = and(_out_wofireMux_T_723, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_179, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_725 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_726 = or(out_wofireMux_out_179, _out_wofireMux_T_725) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_180 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_727 = and(_out_wofireMux_T_262, out_backSel_116) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_728 = and(_out_wofireMux_T_727, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_180, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_729 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_730 = or(out_wofireMux_out_180, _out_wofireMux_T_729) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_181 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_731 = and(_out_wofireMux_T_262, out_backSel_117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_732 = and(_out_wofireMux_T_731, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_181, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_733 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_734 = or(out_wofireMux_out_181, _out_wofireMux_T_733) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_182 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_735 = and(_out_wofireMux_T_262, out_backSel_118) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_736 = and(_out_wofireMux_T_735, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_182, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_737 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_738 = or(out_wofireMux_out_182, _out_wofireMux_T_737) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_183 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_739 = and(_out_wofireMux_T_262, out_backSel_119) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_740 = and(_out_wofireMux_T_739, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_183, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_741 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_742 = or(out_wofireMux_out_183, _out_wofireMux_T_741) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_184 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_743 = and(_out_wofireMux_T_262, out_backSel_120) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_744 = and(_out_wofireMux_T_743, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_184, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_745 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_746 = or(out_wofireMux_out_184, _out_wofireMux_T_745) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_185 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_747 = and(_out_wofireMux_T_262, out_backSel_121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_748 = and(_out_wofireMux_T_747, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_185, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_749 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_750 = or(out_wofireMux_out_185, _out_wofireMux_T_749) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_186 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_751 = and(_out_wofireMux_T_262, out_backSel_122) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_752 = and(_out_wofireMux_T_751, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_186, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_753 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_754 = or(out_wofireMux_out_186, _out_wofireMux_T_753) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_187 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_755 = and(_out_wofireMux_T_262, out_backSel_123) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_756 = and(_out_wofireMux_T_755, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_187, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_757 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_758 = or(out_wofireMux_out_187, _out_wofireMux_T_757) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_188 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_759 = and(_out_wofireMux_T_262, out_backSel_124) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_760 = and(_out_wofireMux_T_759, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_188, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_761 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_762 = or(out_wofireMux_out_188, _out_wofireMux_T_761) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_189 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_763 = and(_out_wofireMux_T_262, out_backSel_125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_764 = and(_out_wofireMux_T_763, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_189, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_765 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_766 = or(out_wofireMux_out_189, _out_wofireMux_T_765) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_190 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_767 = and(_out_wofireMux_T_262, out_backSel_126) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_768 = and(_out_wofireMux_T_767, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_190, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_769 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_770 = or(out_wofireMux_out_190, _out_wofireMux_T_769) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_191 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_771 = and(_out_wofireMux_T_262, out_backSel_127) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_772 = and(_out_wofireMux_T_771, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_191, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_773 = eq(UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_774 = or(out_wofireMux_out_191, _out_wofireMux_T_773) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_192 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_775 = and(_out_wofireMux_T_262, out_backSel_128) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_776 = and(_out_wofireMux_T_775, _out_T_1451) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_192, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[494], _out_wofireMux_T_776 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[493], _out_wofireMux_T_776 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[492], _out_wofireMux_T_776 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[491], _out_wofireMux_T_776 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[490], _out_wofireMux_T_776 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[489], _out_wofireMux_T_776 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[488], _out_wofireMux_T_776 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[487], _out_wofireMux_T_776 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_777 = eq(_out_T_1451, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_778 = or(out_wofireMux_out_192, _out_wofireMux_T_777) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_193 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_779 = and(_out_wofireMux_T_262, out_backSel_129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_780 = and(_out_wofireMux_T_779, _out_T_1443) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_193, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[466], _out_wofireMux_T_780 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[465], _out_wofireMux_T_780 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[464], _out_wofireMux_T_780 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[463], _out_wofireMux_T_780 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[462], _out_wofireMux_T_780 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[461], _out_wofireMux_T_780 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[460], _out_wofireMux_T_780 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[459], _out_wofireMux_T_780 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_781 = eq(_out_T_1443, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_782 = or(out_wofireMux_out_193, _out_wofireMux_T_781) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_194 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_783 = and(_out_wofireMux_T_262, out_backSel_130) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_784 = and(_out_wofireMux_T_783, _out_T_1517) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_194, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[746], _out_wofireMux_T_784 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[745], _out_wofireMux_T_784 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[744], _out_wofireMux_T_784 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[743], _out_wofireMux_T_784 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[742], _out_wofireMux_T_784 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[741], _out_wofireMux_T_784 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[740], _out_wofireMux_T_784 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[739], _out_wofireMux_T_784 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_785 = eq(_out_T_1517, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_786 = or(out_wofireMux_out_194, _out_wofireMux_T_785) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_195 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_787 = and(_out_wofireMux_T_262, out_backSel_131) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_788 = and(_out_wofireMux_T_787, _out_T_1609) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_195, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1114], _out_wofireMux_T_788 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1113], _out_wofireMux_T_788 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1112], _out_wofireMux_T_788 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1111], _out_wofireMux_T_788 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1110], _out_wofireMux_T_788 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1109], _out_wofireMux_T_788 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1108], _out_wofireMux_T_788 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1107], _out_wofireMux_T_788 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_789 = eq(_out_T_1609, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_790 = or(out_wofireMux_out_195, _out_wofireMux_T_789) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_196 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_791 = and(_out_wofireMux_T_262, out_backSel_132) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_792 = and(_out_wofireMux_T_791, _out_T_1383) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_196, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[239], _out_wofireMux_T_792 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[238], _out_wofireMux_T_792 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[237], _out_wofireMux_T_792 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[236], _out_wofireMux_T_792 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[235], _out_wofireMux_T_792 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[234], _out_wofireMux_T_792 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[233], _out_wofireMux_T_792 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[232], _out_wofireMux_T_792 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_793 = eq(_out_T_1383, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_794 = or(out_wofireMux_out_196, _out_wofireMux_T_793) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_197 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_795 = and(_out_wofireMux_T_262, out_backSel_133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_796 = and(_out_wofireMux_T_795, _out_T_1385) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_197, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[247], _out_wofireMux_T_796 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[246], _out_wofireMux_T_796 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[245], _out_wofireMux_T_796 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[244], _out_wofireMux_T_796 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[243], _out_wofireMux_T_796 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[242], _out_wofireMux_T_796 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[241], _out_wofireMux_T_796 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[240], _out_wofireMux_T_796 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_797 = eq(_out_T_1385, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_798 = or(out_wofireMux_out_197, _out_wofireMux_T_797) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_198 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_799 = and(_out_wofireMux_T_262, out_backSel_134) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_800 = and(_out_wofireMux_T_799, _out_T_1445) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_198, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[474], _out_wofireMux_T_800 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[473], _out_wofireMux_T_800 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[472], _out_wofireMux_T_800 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[471], _out_wofireMux_T_800 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[470], _out_wofireMux_T_800 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[469], _out_wofireMux_T_800 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[468], _out_wofireMux_T_800 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[467], _out_wofireMux_T_800 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_801 = eq(_out_T_1445, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_802 = or(out_wofireMux_out_198, _out_wofireMux_T_801) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_199 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_803 = and(_out_wofireMux_T_262, out_backSel_135) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_804 = and(_out_wofireMux_T_803, _out_T_1521) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_199, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[762], _out_wofireMux_T_804 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[761], _out_wofireMux_T_804 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[760], _out_wofireMux_T_804 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[759], _out_wofireMux_T_804 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[758], _out_wofireMux_T_804 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[757], _out_wofireMux_T_804 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[756], _out_wofireMux_T_804 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[755], _out_wofireMux_T_804 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_805 = eq(_out_T_1521, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_806 = or(out_wofireMux_out_199, _out_wofireMux_T_805) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_200 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_807 = and(_out_wofireMux_T_262, out_backSel_136) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_808 = and(_out_wofireMux_T_807, _out_T_1601) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_200, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1082], _out_wofireMux_T_808 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1081], _out_wofireMux_T_808 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1080], _out_wofireMux_T_808 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1079], _out_wofireMux_T_808 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1078], _out_wofireMux_T_808 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1077], _out_wofireMux_T_808 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1076], _out_wofireMux_T_808 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1075], _out_wofireMux_T_808 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_809 = eq(_out_T_1601, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_810 = or(out_wofireMux_out_200, _out_wofireMux_T_809) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_201 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_811 = and(_out_wofireMux_T_262, out_backSel_137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_812 = and(_out_wofireMux_T_811, _out_T_1407) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_201, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[335], _out_wofireMux_T_812 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[334], _out_wofireMux_T_812 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[333], _out_wofireMux_T_812 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[332], _out_wofireMux_T_812 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[331], _out_wofireMux_T_812 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[330], _out_wofireMux_T_812 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[329], _out_wofireMux_T_812 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[328], _out_wofireMux_T_812 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_813 = eq(_out_T_1407, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_814 = or(out_wofireMux_out_201, _out_wofireMux_T_813) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_202 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_815 = and(_out_wofireMux_T_262, out_backSel_138) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_816 = and(_out_wofireMux_T_815, _out_T_1325) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_202, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[7], _out_wofireMux_T_816 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[6], _out_wofireMux_T_816 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[5], _out_wofireMux_T_816 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[4], _out_wofireMux_T_816 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[3], _out_wofireMux_T_816 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[2], _out_wofireMux_T_816 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1], _out_wofireMux_T_816 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[0], _out_wofireMux_T_816 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_817 = eq(_out_T_1325, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_818 = or(out_wofireMux_out_202, _out_wofireMux_T_817) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_203 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_819 = and(_out_wofireMux_T_262, out_backSel_139) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_820 = and(_out_wofireMux_T_819, _out_T_1575) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_203, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[978], _out_wofireMux_T_820 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[977], _out_wofireMux_T_820 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[976], _out_wofireMux_T_820 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[975], _out_wofireMux_T_820 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[974], _out_wofireMux_T_820 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[973], _out_wofireMux_T_820 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[972], _out_wofireMux_T_820 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[971], _out_wofireMux_T_820 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_821 = eq(_out_T_1575, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_822 = or(out_wofireMux_out_203, _out_wofireMux_T_821) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_204 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_823 = and(_out_wofireMux_T_262, out_backSel_140) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_824 = and(_out_wofireMux_T_823, _out_T_1503) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_204, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[690], _out_wofireMux_T_824 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[689], _out_wofireMux_T_824 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[688], _out_wofireMux_T_824 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[687], _out_wofireMux_T_824 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[686], _out_wofireMux_T_824 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[685], _out_wofireMux_T_824 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[684], _out_wofireMux_T_824 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[683], _out_wofireMux_T_824 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_825 = eq(_out_T_1503, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_826 = or(out_wofireMux_out_204, _out_wofireMux_T_825) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_205 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_827 = and(_out_wofireMux_T_262, out_backSel_141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_828 = and(_out_wofireMux_T_827, _out_T_1427) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_205, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[409], _out_wofireMux_T_828 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[408], _out_wofireMux_T_828 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[407], _out_wofireMux_T_828 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[406], _out_wofireMux_T_828 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[405], _out_wofireMux_T_828 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[404], _out_wofireMux_T_828 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[403], _out_wofireMux_T_828 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[402], _out_wofireMux_T_828 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_829 = eq(_out_T_1427, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_830 = or(out_wofireMux_out_205, _out_wofireMux_T_829) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_206 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_831 = and(_out_wofireMux_T_262, out_backSel_142) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_832 = and(_out_wofireMux_T_831, _out_T_1339) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_206, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[63], _out_wofireMux_T_832 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[62], _out_wofireMux_T_832 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[61], _out_wofireMux_T_832 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[60], _out_wofireMux_T_832 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[59], _out_wofireMux_T_832 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[58], _out_wofireMux_T_832 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[57], _out_wofireMux_T_832 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[56], _out_wofireMux_T_832 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_833 = eq(_out_T_1339, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_834 = or(out_wofireMux_out_206, _out_wofireMux_T_833) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_207 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_835 = and(_out_wofireMux_T_262, out_backSel_143) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_836 = and(_out_wofireMux_T_835, _out_T_1555) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_207, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[898], _out_wofireMux_T_836 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[897], _out_wofireMux_T_836 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[896], _out_wofireMux_T_836 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[895], _out_wofireMux_T_836 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[894], _out_wofireMux_T_836 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[893], _out_wofireMux_T_836 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[892], _out_wofireMux_T_836 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[891], _out_wofireMux_T_836 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_837 = eq(_out_T_1555, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_838 = or(out_wofireMux_out_207, _out_wofireMux_T_837) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_208 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_839 = and(_out_wofireMux_T_262, out_backSel_144) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_840 = and(_out_wofireMux_T_839, _out_T_1481) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_208, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[608], _out_wofireMux_T_840 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[607], _out_wofireMux_T_840 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[606], _out_wofireMux_T_840 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[605], _out_wofireMux_T_840 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[604], _out_wofireMux_T_840 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[603], _out_wofireMux_T_840 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[602], _out_wofireMux_T_840 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[601], _out_wofireMux_T_840 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_841 = eq(_out_T_1481, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_842 = or(out_wofireMux_out_208, _out_wofireMux_T_841) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_209 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_843 = and(_out_wofireMux_T_262, out_backSel_145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_844 = and(_out_wofireMux_T_843, _out_T_1539) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_209, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[834], _out_wofireMux_T_844 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[833], _out_wofireMux_T_844 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[832], _out_wofireMux_T_844 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[831], _out_wofireMux_T_844 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[830], _out_wofireMux_T_844 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[829], _out_wofireMux_T_844 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[828], _out_wofireMux_T_844 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[827], _out_wofireMux_T_844 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_845 = eq(_out_T_1539, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_846 = or(out_wofireMux_out_209, _out_wofireMux_T_845) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_210 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_847 = and(_out_wofireMux_T_262, out_backSel_146) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_848 = and(_out_wofireMux_T_847, _out_T_1587) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_210, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1026], _out_wofireMux_T_848 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1025], _out_wofireMux_T_848 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1024], _out_wofireMux_T_848 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1023], _out_wofireMux_T_848 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1022], _out_wofireMux_T_848 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1021], _out_wofireMux_T_848 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1020], _out_wofireMux_T_848 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1019], _out_wofireMux_T_848 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_849 = eq(_out_T_1587, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_850 = or(out_wofireMux_out_210, _out_wofireMux_T_849) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_211 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_851 = and(_out_wofireMux_T_262, out_backSel_147) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_852 = and(_out_wofireMux_T_851, _out_T_1379) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_211, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[223], _out_wofireMux_T_852 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[222], _out_wofireMux_T_852 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[221], _out_wofireMux_T_852 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[220], _out_wofireMux_T_852 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[219], _out_wofireMux_T_852 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[218], _out_wofireMux_T_852 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[217], _out_wofireMux_T_852 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[216], _out_wofireMux_T_852 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_853 = eq(_out_T_1379, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_854 = or(out_wofireMux_out_211, _out_wofireMux_T_853) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_212 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_855 = and(_out_wofireMux_T_262, out_backSel_148) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_856 = and(_out_wofireMux_T_855, _out_T_1463) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_212, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[536], _out_wofireMux_T_856 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[535], _out_wofireMux_T_856 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[534], _out_wofireMux_T_856 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[533], _out_wofireMux_T_856 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[532], _out_wofireMux_T_856 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[531], _out_wofireMux_T_856 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[530], _out_wofireMux_T_856 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[529], _out_wofireMux_T_856 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_857 = eq(_out_T_1463, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_858 = or(out_wofireMux_out_212, _out_wofireMux_T_857) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_213 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_859 = and(_out_wofireMux_T_262, out_backSel_149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_860 = and(_out_wofireMux_T_859, _out_T_1471) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_213, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[568], _out_wofireMux_T_860 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[567], _out_wofireMux_T_860 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[566], _out_wofireMux_T_860 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[565], _out_wofireMux_T_860 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[564], _out_wofireMux_T_860 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[563], _out_wofireMux_T_860 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[562], _out_wofireMux_T_860 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[561], _out_wofireMux_T_860 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_861 = eq(_out_T_1471, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_862 = or(out_wofireMux_out_213, _out_wofireMux_T_861) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_214 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_863 = and(_out_wofireMux_T_262, out_backSel_150) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_864 = and(_out_wofireMux_T_863, _out_T_1541) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_214, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[842], _out_wofireMux_T_864 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[841], _out_wofireMux_T_864 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[840], _out_wofireMux_T_864 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[839], _out_wofireMux_T_864 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[838], _out_wofireMux_T_864 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[837], _out_wofireMux_T_864 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[836], _out_wofireMux_T_864 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[835], _out_wofireMux_T_864 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_865 = eq(_out_T_1541, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_866 = or(out_wofireMux_out_214, _out_wofireMux_T_865) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_215 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_867 = and(_out_wofireMux_T_262, out_backSel_151) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_868 = and(_out_wofireMux_T_867, _out_T_1585) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_215, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1018], _out_wofireMux_T_868 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1017], _out_wofireMux_T_868 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1016], _out_wofireMux_T_868 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1015], _out_wofireMux_T_868 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1014], _out_wofireMux_T_868 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1013], _out_wofireMux_T_868 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1012], _out_wofireMux_T_868 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1011], _out_wofireMux_T_868 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_869 = eq(_out_T_1585, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_870 = or(out_wofireMux_out_215, _out_wofireMux_T_869) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_216 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_871 = and(_out_wofireMux_T_262, out_backSel_152) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_872 = and(_out_wofireMux_T_871, _out_T_1359) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_216, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[143], _out_wofireMux_T_872 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[142], _out_wofireMux_T_872 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[141], _out_wofireMux_T_872 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[140], _out_wofireMux_T_872 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[139], _out_wofireMux_T_872 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[138], _out_wofireMux_T_872 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[137], _out_wofireMux_T_872 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[136], _out_wofireMux_T_872 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_873 = eq(_out_T_1359, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_874 = or(out_wofireMux_out_216, _out_wofireMux_T_873) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_217 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_875 = and(_out_wofireMux_T_262, out_backSel_153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_876 = and(_out_wofireMux_T_875, _out_T_1341) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_217, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[71], _out_wofireMux_T_876 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[70], _out_wofireMux_T_876 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[69], _out_wofireMux_T_876 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[68], _out_wofireMux_T_876 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[67], _out_wofireMux_T_876 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[66], _out_wofireMux_T_876 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[65], _out_wofireMux_T_876 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[64], _out_wofireMux_T_876 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_877 = eq(_out_T_1341, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_878 = or(out_wofireMux_out_217, _out_wofireMux_T_877) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_218 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_879 = and(_out_wofireMux_T_262, out_backSel_154) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_880 = and(_out_wofireMux_T_879, _out_T_1551) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_218, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[882], _out_wofireMux_T_880 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[881], _out_wofireMux_T_880 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[880], _out_wofireMux_T_880 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[879], _out_wofireMux_T_880 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[878], _out_wofireMux_T_880 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[877], _out_wofireMux_T_880 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[876], _out_wofireMux_T_880 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[875], _out_wofireMux_T_880 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_881 = eq(_out_T_1551, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_882 = or(out_wofireMux_out_218, _out_wofireMux_T_881) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_219 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_883 = and(_out_wofireMux_T_262, out_backSel_155) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_884 = and(_out_wofireMux_T_883, _out_T_1507) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_219, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[706], _out_wofireMux_T_884 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[705], _out_wofireMux_T_884 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[704], _out_wofireMux_T_884 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[703], _out_wofireMux_T_884 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[702], _out_wofireMux_T_884 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[701], _out_wofireMux_T_884 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[700], _out_wofireMux_T_884 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[699], _out_wofireMux_T_884 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_885 = eq(_out_T_1507, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_886 = or(out_wofireMux_out_219, _out_wofireMux_T_885) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_220 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_887 = and(_out_wofireMux_T_262, out_backSel_156) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_888 = and(_out_wofireMux_T_887, _out_T_1421) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_220, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[385], _out_wofireMux_T_888 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[384], _out_wofireMux_T_888 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[383], _out_wofireMux_T_888 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[382], _out_wofireMux_T_888 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[381], _out_wofireMux_T_888 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[380], _out_wofireMux_T_888 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[379], _out_wofireMux_T_888 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[378], _out_wofireMux_T_888 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_889 = eq(_out_T_1421, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_890 = or(out_wofireMux_out_220, _out_wofireMux_T_889) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_221 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_891 = and(_out_wofireMux_T_262, out_backSel_157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_892 = and(_out_wofireMux_T_891, _out_T_1355) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_221, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[127], _out_wofireMux_T_892 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[126], _out_wofireMux_T_892 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[125], _out_wofireMux_T_892 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[124], _out_wofireMux_T_892 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[123], _out_wofireMux_T_892 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[122], _out_wofireMux_T_892 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[121], _out_wofireMux_T_892 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[120], _out_wofireMux_T_892 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_893 = eq(_out_T_1355, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_894 = or(out_wofireMux_out_221, _out_wofireMux_T_893) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_222 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_895 = and(_out_wofireMux_T_262, out_backSel_158) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_896 = and(_out_wofireMux_T_895, _out_T_1569) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_222, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[954], _out_wofireMux_T_896 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[953], _out_wofireMux_T_896 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[952], _out_wofireMux_T_896 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[951], _out_wofireMux_T_896 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[950], _out_wofireMux_T_896 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[949], _out_wofireMux_T_896 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[948], _out_wofireMux_T_896 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[947], _out_wofireMux_T_896 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_897 = eq(_out_T_1569, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_898 = or(out_wofireMux_out_222, _out_wofireMux_T_897) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_223 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_899 = and(_out_wofireMux_T_262, out_backSel_159) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_900 = and(_out_wofireMux_T_899, _out_T_1487) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_223, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[632], _out_wofireMux_T_900 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[631], _out_wofireMux_T_900 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[630], _out_wofireMux_T_900 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[629], _out_wofireMux_T_900 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[628], _out_wofireMux_T_900 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[627], _out_wofireMux_T_900 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[626], _out_wofireMux_T_900 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[625], _out_wofireMux_T_900 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_901 = eq(_out_T_1487, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_902 = or(out_wofireMux_out_223, _out_wofireMux_T_901) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_224 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_903 = and(_out_wofireMux_T_262, out_backSel_160) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_904 = and(_out_wofireMux_T_903, _out_T_1403) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_224, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[319], _out_wofireMux_T_904 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[318], _out_wofireMux_T_904 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[317], _out_wofireMux_T_904 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[316], _out_wofireMux_T_904 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[315], _out_wofireMux_T_904 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[314], _out_wofireMux_T_904 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[313], _out_wofireMux_T_904 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[312], _out_wofireMux_T_904 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_905 = eq(_out_T_1403, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_906 = or(out_wofireMux_out_224, _out_wofireMux_T_905) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_225 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_907 = and(_out_wofireMux_T_262, out_backSel_161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_908 = and(_out_wofireMux_T_907, _out_T_1467) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_225, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[552], _out_wofireMux_T_908 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[551], _out_wofireMux_T_908 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[550], _out_wofireMux_T_908 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[549], _out_wofireMux_T_908 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[548], _out_wofireMux_T_908 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[547], _out_wofireMux_T_908 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[546], _out_wofireMux_T_908 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[545], _out_wofireMux_T_908 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_909 = eq(_out_T_1467, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_910 = or(out_wofireMux_out_225, _out_wofireMux_T_909) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_226 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_911 = and(_out_wofireMux_T_262, out_backSel_162) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_912 = and(_out_wofireMux_T_911, _out_T_1529) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_226, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[794], _out_wofireMux_T_912 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[793], _out_wofireMux_T_912 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[792], _out_wofireMux_T_912 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[791], _out_wofireMux_T_912 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[790], _out_wofireMux_T_912 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[789], _out_wofireMux_T_912 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[788], _out_wofireMux_T_912 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[787], _out_wofireMux_T_912 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_913 = eq(_out_T_1529, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_914 = or(out_wofireMux_out_226, _out_wofireMux_T_913) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_227 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_915 = and(_out_wofireMux_T_262, out_backSel_163) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_916 = and(_out_wofireMux_T_915, _out_T_1613) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_227, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1130], _out_wofireMux_T_916 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1129], _out_wofireMux_T_916 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1128], _out_wofireMux_T_916 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1127], _out_wofireMux_T_916 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1126], _out_wofireMux_T_916 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1125], _out_wofireMux_T_916 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1124], _out_wofireMux_T_916 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1123], _out_wofireMux_T_916 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_917 = eq(_out_T_1613, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_918 = or(out_wofireMux_out_227, _out_wofireMux_T_917) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_228 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_919 = and(_out_wofireMux_T_262, out_backSel_164) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_920 = and(_out_wofireMux_T_919, _out_T_1367) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_228, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[175], _out_wofireMux_T_920 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[174], _out_wofireMux_T_920 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[173], _out_wofireMux_T_920 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[172], _out_wofireMux_T_920 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[171], _out_wofireMux_T_920 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[170], _out_wofireMux_T_920 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[169], _out_wofireMux_T_920 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[168], _out_wofireMux_T_920 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_921 = eq(_out_T_1367, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_922 = or(out_wofireMux_out_228, _out_wofireMux_T_921) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_229 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_923 = and(_out_wofireMux_T_262, out_backSel_165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_924 = and(_out_wofireMux_T_923, _out_T_1409) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_229, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[343], _out_wofireMux_T_924 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[342], _out_wofireMux_T_924 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[341], _out_wofireMux_T_924 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[340], _out_wofireMux_T_924 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[339], _out_wofireMux_T_924 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[338], _out_wofireMux_T_924 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[337], _out_wofireMux_T_924 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[336], _out_wofireMux_T_924 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_925 = eq(_out_T_1409, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_926 = or(out_wofireMux_out_229, _out_wofireMux_T_925) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_230 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_927 = and(_out_wofireMux_T_262, out_backSel_166) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_928 = and(_out_wofireMux_T_927, _out_T_1459) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_230, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[526], _out_wofireMux_T_928 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[525], _out_wofireMux_T_928 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[524], _out_wofireMux_T_928 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[523], _out_wofireMux_T_928 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[522], _out_wofireMux_T_928 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[521], _out_wofireMux_T_928 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[520], _out_wofireMux_T_928 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[519], _out_wofireMux_T_928 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_929 = eq(_out_T_1459, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_930 = or(out_wofireMux_out_230, _out_wofireMux_T_929) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_231 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_931 = and(_out_wofireMux_T_262, out_backSel_167) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_932 = and(_out_wofireMux_T_931, _out_T_1527) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_231, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[786], _out_wofireMux_T_932 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[785], _out_wofireMux_T_932 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[784], _out_wofireMux_T_932 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[783], _out_wofireMux_T_932 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[782], _out_wofireMux_T_932 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[781], _out_wofireMux_T_932 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[780], _out_wofireMux_T_932 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[779], _out_wofireMux_T_932 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_933 = eq(_out_T_1527, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_934 = or(out_wofireMux_out_231, _out_wofireMux_T_933) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_232 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_935 = and(_out_wofireMux_T_262, out_backSel_168) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_936 = and(_out_wofireMux_T_935, _out_T_1593) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_232, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1050], _out_wofireMux_T_936 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1049], _out_wofireMux_T_936 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1048], _out_wofireMux_T_936 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1047], _out_wofireMux_T_936 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1046], _out_wofireMux_T_936 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1045], _out_wofireMux_T_936 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1044], _out_wofireMux_T_936 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1043], _out_wofireMux_T_936 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_937 = eq(_out_T_1593, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_938 = or(out_wofireMux_out_232, _out_wofireMux_T_937) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_233 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_939 = and(_out_wofireMux_T_262, out_backSel_169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_940 = and(_out_wofireMux_T_939, _out_T_1425) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_233, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[401], _out_wofireMux_T_940 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[400], _out_wofireMux_T_940 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[399], _out_wofireMux_T_940 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[398], _out_wofireMux_T_940 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[397], _out_wofireMux_T_940 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[396], _out_wofireMux_T_940 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[395], _out_wofireMux_T_940 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[394], _out_wofireMux_T_940 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_941 = eq(_out_T_1425, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_942 = or(out_wofireMux_out_233, _out_wofireMux_T_941) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_234 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_943 = and(_out_wofireMux_T_262, out_backSel_170) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_944 = and(_out_wofireMux_T_943, _out_T_1331) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_234, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[31], _out_wofireMux_T_944 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[30], _out_wofireMux_T_944 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[29], _out_wofireMux_T_944 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[28], _out_wofireMux_T_944 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[27], _out_wofireMux_T_944 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[26], _out_wofireMux_T_944 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[25], _out_wofireMux_T_944 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[24], _out_wofireMux_T_944 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_945 = eq(_out_T_1331, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_946 = or(out_wofireMux_out_234, _out_wofireMux_T_945) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_235 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_947 = and(_out_wofireMux_T_262, out_backSel_171) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_948 = and(_out_wofireMux_T_947, _out_T_1573) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_235, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[970], _out_wofireMux_T_948 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[969], _out_wofireMux_T_948 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[968], _out_wofireMux_T_948 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[967], _out_wofireMux_T_948 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[966], _out_wofireMux_T_948 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[965], _out_wofireMux_T_948 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[964], _out_wofireMux_T_948 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[963], _out_wofireMux_T_948 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_949 = eq(_out_T_1573, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_950 = or(out_wofireMux_out_235, _out_wofireMux_T_949) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_236 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_951 = and(_out_wofireMux_T_262, out_backSel_172) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_952 = and(_out_wofireMux_T_951, _out_T_1491) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_236, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[648], _out_wofireMux_T_952 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[647], _out_wofireMux_T_952 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[646], _out_wofireMux_T_952 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[645], _out_wofireMux_T_952 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[644], _out_wofireMux_T_952 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[643], _out_wofireMux_T_952 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[642], _out_wofireMux_T_952 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[641], _out_wofireMux_T_952 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_953 = eq(_out_T_1491, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_954 = or(out_wofireMux_out_236, _out_wofireMux_T_953) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_237 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_955 = and(_out_wofireMux_T_262, out_backSel_173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_956 = and(_out_wofireMux_T_955, _out_T_1441) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_237, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[458], _out_wofireMux_T_956 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[457], _out_wofireMux_T_956 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[456], _out_wofireMux_T_956 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[455], _out_wofireMux_T_956 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[454], _out_wofireMux_T_956 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[453], _out_wofireMux_T_956 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[452], _out_wofireMux_T_956 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[451], _out_wofireMux_T_956 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_957 = eq(_out_T_1441, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_958 = or(out_wofireMux_out_237, _out_wofireMux_T_957) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_238 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_959 = and(_out_wofireMux_T_262, out_backSel_174) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_960 = and(_out_wofireMux_T_959, _out_T_1343) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_238, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[79], _out_wofireMux_T_960 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[78], _out_wofireMux_T_960 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[77], _out_wofireMux_T_960 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[76], _out_wofireMux_T_960 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[75], _out_wofireMux_T_960 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[74], _out_wofireMux_T_960 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[73], _out_wofireMux_T_960 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[72], _out_wofireMux_T_960 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_961 = eq(_out_T_1343, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_962 = or(out_wofireMux_out_238, _out_wofireMux_T_961) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_239 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_963 = and(_out_wofireMux_T_262, out_backSel_175) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_964 = and(_out_wofireMux_T_963, _out_T_1553) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_239, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[890], _out_wofireMux_T_964 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[889], _out_wofireMux_T_964 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[888], _out_wofireMux_T_964 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[887], _out_wofireMux_T_964 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[886], _out_wofireMux_T_964 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[885], _out_wofireMux_T_964 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[884], _out_wofireMux_T_964 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[883], _out_wofireMux_T_964 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_965 = eq(_out_T_1553, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_966 = or(out_wofireMux_out_239, _out_wofireMux_T_965) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_240 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_967 = and(_out_wofireMux_T_262, out_backSel_176) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_968 = and(_out_wofireMux_T_967, _out_T_1473) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_240, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[576], _out_wofireMux_T_968 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[575], _out_wofireMux_T_968 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[574], _out_wofireMux_T_968 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[573], _out_wofireMux_T_968 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[572], _out_wofireMux_T_968 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[571], _out_wofireMux_T_968 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[570], _out_wofireMux_T_968 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[569], _out_wofireMux_T_968 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_969 = eq(_out_T_1473, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_970 = or(out_wofireMux_out_240, _out_wofireMux_T_969) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_241 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_971 = and(_out_wofireMux_T_262, out_backSel_177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_972 = and(_out_wofireMux_T_971, _out_T_1547) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_241, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[866], _out_wofireMux_T_972 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[865], _out_wofireMux_T_972 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[864], _out_wofireMux_T_972 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[863], _out_wofireMux_T_972 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[862], _out_wofireMux_T_972 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[861], _out_wofireMux_T_972 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[860], _out_wofireMux_T_972 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[859], _out_wofireMux_T_972 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_973 = eq(_out_T_1547, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_974 = or(out_wofireMux_out_241, _out_wofireMux_T_973) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_242 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_975 = and(_out_wofireMux_T_262, out_backSel_178) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_976 = and(_out_wofireMux_T_975, _out_T_1611) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_242, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1122], _out_wofireMux_T_976 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1121], _out_wofireMux_T_976 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1120], _out_wofireMux_T_976 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1119], _out_wofireMux_T_976 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1118], _out_wofireMux_T_976 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1117], _out_wofireMux_T_976 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1116], _out_wofireMux_T_976 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1115], _out_wofireMux_T_976 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_977 = eq(_out_T_1611, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_978 = or(out_wofireMux_out_242, _out_wofireMux_T_977) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_243 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_979 = and(_out_wofireMux_T_262, out_backSel_179) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_980 = and(_out_wofireMux_T_979, _out_T_1369) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_243, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[183], _out_wofireMux_T_980 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[182], _out_wofireMux_T_980 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[181], _out_wofireMux_T_980 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[180], _out_wofireMux_T_980 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[179], _out_wofireMux_T_980 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[178], _out_wofireMux_T_980 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[177], _out_wofireMux_T_980 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[176], _out_wofireMux_T_980 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_981 = eq(_out_T_1369, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_982 = or(out_wofireMux_out_243, _out_wofireMux_T_981) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_244 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_983 = and(_out_wofireMux_T_262, out_backSel_180) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_984 = and(_out_wofireMux_T_983, _out_T_1469) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_244, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[560], _out_wofireMux_T_984 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[559], _out_wofireMux_T_984 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[558], _out_wofireMux_T_984 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[557], _out_wofireMux_T_984 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[556], _out_wofireMux_T_984 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[555], _out_wofireMux_T_984 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[554], _out_wofireMux_T_984 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[553], _out_wofireMux_T_984 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_985 = eq(_out_T_1469, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_986 = or(out_wofireMux_out_244, _out_wofireMux_T_985) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_245 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_987 = and(_out_wofireMux_T_262, out_backSel_181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_988 = and(_out_wofireMux_T_987, _out_T_1485) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_245, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[624], _out_wofireMux_T_988 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[623], _out_wofireMux_T_988 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[622], _out_wofireMux_T_988 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[621], _out_wofireMux_T_988 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[620], _out_wofireMux_T_988 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[619], _out_wofireMux_T_988 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[618], _out_wofireMux_T_988 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[617], _out_wofireMux_T_988 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_989 = eq(_out_T_1485, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_990 = or(out_wofireMux_out_245, _out_wofireMux_T_989) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_246 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_991 = and(_out_wofireMux_T_262, out_backSel_182) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_992 = and(_out_wofireMux_T_991, _out_T_1549) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_246, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[874], _out_wofireMux_T_992 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[873], _out_wofireMux_T_992 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[872], _out_wofireMux_T_992 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[871], _out_wofireMux_T_992 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[870], _out_wofireMux_T_992 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[869], _out_wofireMux_T_992 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[868], _out_wofireMux_T_992 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[867], _out_wofireMux_T_992 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_993 = eq(_out_T_1549, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_994 = or(out_wofireMux_out_246, _out_wofireMux_T_993) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_247 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_995 = and(_out_wofireMux_T_262, out_backSel_183) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_996 = and(_out_wofireMux_T_995, _out_T_1591) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_247, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1042], _out_wofireMux_T_996 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1041], _out_wofireMux_T_996 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1040], _out_wofireMux_T_996 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1039], _out_wofireMux_T_996 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1038], _out_wofireMux_T_996 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1037], _out_wofireMux_T_996 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1036], _out_wofireMux_T_996 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1035], _out_wofireMux_T_996 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_997 = eq(_out_T_1591, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_998 = or(out_wofireMux_out_247, _out_wofireMux_T_997) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_248 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_999 = and(_out_wofireMux_T_262, out_backSel_184) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1000 = and(_out_wofireMux_T_999, _out_T_1349) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_248, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[103], _out_wofireMux_T_1000 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[102], _out_wofireMux_T_1000 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[101], _out_wofireMux_T_1000 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[100], _out_wofireMux_T_1000 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[99], _out_wofireMux_T_1000 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[98], _out_wofireMux_T_1000 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[97], _out_wofireMux_T_1000 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[96], _out_wofireMux_T_1000 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1001 = eq(_out_T_1349, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1002 = or(out_wofireMux_out_248, _out_wofireMux_T_1001) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_249 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1003 = and(_out_wofireMux_T_262, out_backSel_185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1004 = and(_out_wofireMux_T_1003, _out_T_1345) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_249, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[87], _out_wofireMux_T_1004 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[86], _out_wofireMux_T_1004 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[85], _out_wofireMux_T_1004 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[84], _out_wofireMux_T_1004 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[83], _out_wofireMux_T_1004 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[82], _out_wofireMux_T_1004 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[81], _out_wofireMux_T_1004 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[80], _out_wofireMux_T_1004 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1005 = eq(_out_T_1345, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1006 = or(out_wofireMux_out_249, _out_wofireMux_T_1005) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_250 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1007 = and(_out_wofireMux_T_262, out_backSel_186) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1008 = and(_out_wofireMux_T_1007, _out_T_1571) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_250, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[962], _out_wofireMux_T_1008 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[961], _out_wofireMux_T_1008 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[960], _out_wofireMux_T_1008 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[959], _out_wofireMux_T_1008 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[958], _out_wofireMux_T_1008 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[957], _out_wofireMux_T_1008 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[956], _out_wofireMux_T_1008 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[955], _out_wofireMux_T_1008 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1009 = eq(_out_T_1571, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1010 = or(out_wofireMux_out_250, _out_wofireMux_T_1009) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_251 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1011 = and(_out_wofireMux_T_262, out_backSel_187) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1012 = and(_out_wofireMux_T_1011, _out_T_1489) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_251, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[640], _out_wofireMux_T_1012 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[639], _out_wofireMux_T_1012 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[638], _out_wofireMux_T_1012 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[637], _out_wofireMux_T_1012 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[636], _out_wofireMux_T_1012 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[635], _out_wofireMux_T_1012 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[634], _out_wofireMux_T_1012 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[633], _out_wofireMux_T_1012 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1013 = eq(_out_T_1489, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1014 = or(out_wofireMux_out_251, _out_wofireMux_T_1013) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_252 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1015 = and(_out_wofireMux_T_262, out_backSel_188) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1016 = and(_out_wofireMux_T_1015, _out_T_1423) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_252, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[393], _out_wofireMux_T_1016 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[392], _out_wofireMux_T_1016 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[391], _out_wofireMux_T_1016 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[390], _out_wofireMux_T_1016 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[389], _out_wofireMux_T_1016 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[388], _out_wofireMux_T_1016 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[387], _out_wofireMux_T_1016 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[386], _out_wofireMux_T_1016 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1017 = eq(_out_T_1423, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1018 = or(out_wofireMux_out_252, _out_wofireMux_T_1017) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_253 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1019 = and(_out_wofireMux_T_262, out_backSel_189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1020 = and(_out_wofireMux_T_1019, _out_T_1357) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_253, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[135], _out_wofireMux_T_1020 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[134], _out_wofireMux_T_1020 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[133], _out_wofireMux_T_1020 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[132], _out_wofireMux_T_1020 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[131], _out_wofireMux_T_1020 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[130], _out_wofireMux_T_1020 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[129], _out_wofireMux_T_1020 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[128], _out_wofireMux_T_1020 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1021 = eq(_out_T_1357, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1022 = or(out_wofireMux_out_253, _out_wofireMux_T_1021) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_254 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1023 = and(_out_wofireMux_T_262, out_backSel_190) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1024 = and(_out_wofireMux_T_1023, _out_T_1589) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_254, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1034], _out_wofireMux_T_1024 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1033], _out_wofireMux_T_1024 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1032], _out_wofireMux_T_1024 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1031], _out_wofireMux_T_1024 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1030], _out_wofireMux_T_1024 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1029], _out_wofireMux_T_1024 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1028], _out_wofireMux_T_1024 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1027], _out_wofireMux_T_1024 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1025 = eq(_out_T_1589, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1026 = or(out_wofireMux_out_254, _out_wofireMux_T_1025) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_255 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1027 = and(_out_wofireMux_T_262, out_backSel_191) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1028 = and(_out_wofireMux_T_1027, _out_T_1475) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_255, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[584], _out_wofireMux_T_1028 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[583], _out_wofireMux_T_1028 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[582], _out_wofireMux_T_1028 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[581], _out_wofireMux_T_1028 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[580], _out_wofireMux_T_1028 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[579], _out_wofireMux_T_1028 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[578], _out_wofireMux_T_1028 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[577], _out_wofireMux_T_1028 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1029 = eq(_out_T_1475, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1030 = or(out_wofireMux_out_255, _out_wofireMux_T_1029) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_256 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1031 = and(_out_wofireMux_T_262, out_backSel_192) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1032 = and(_out_wofireMux_T_1031, _out_T_1405) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_256, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[327], _out_wofireMux_T_1032 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[326], _out_wofireMux_T_1032 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[325], _out_wofireMux_T_1032 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[324], _out_wofireMux_T_1032 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[323], _out_wofireMux_T_1032 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[322], _out_wofireMux_T_1032 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[321], _out_wofireMux_T_1032 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[320], _out_wofireMux_T_1032 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1033 = eq(_out_T_1405, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1034 = or(out_wofireMux_out_256, _out_wofireMux_T_1033) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_257 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1035 = and(_out_wofireMux_T_262, out_backSel_193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1036 = and(_out_wofireMux_T_1035, _out_T_1431) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_257, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[425], _out_wofireMux_T_1036 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[424], _out_wofireMux_T_1036 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[423], _out_wofireMux_T_1036 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[422], _out_wofireMux_T_1036 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[421], _out_wofireMux_T_1036 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[420], _out_wofireMux_T_1036 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[419], _out_wofireMux_T_1036 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[418], _out_wofireMux_T_1036 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1037 = eq(_out_T_1431, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1038 = or(out_wofireMux_out_257, _out_wofireMux_T_1037) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_258 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1039 = and(_out_wofireMux_T_262, out_backSel_194) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1040 = and(_out_wofireMux_T_1039, _out_T_1537) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_258, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[826], _out_wofireMux_T_1040 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[825], _out_wofireMux_T_1040 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[824], _out_wofireMux_T_1040 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[823], _out_wofireMux_T_1040 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[822], _out_wofireMux_T_1040 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[821], _out_wofireMux_T_1040 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[820], _out_wofireMux_T_1040 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[819], _out_wofireMux_T_1040 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1041 = eq(_out_T_1537, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1042 = or(out_wofireMux_out_258, _out_wofireMux_T_1041) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_259 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1043 = and(_out_wofireMux_T_262, out_backSel_195) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1044 = and(_out_wofireMux_T_1043, _out_T_1603) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_259, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1090], _out_wofireMux_T_1044 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1089], _out_wofireMux_T_1044 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1088], _out_wofireMux_T_1044 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1087], _out_wofireMux_T_1044 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1086], _out_wofireMux_T_1044 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1085], _out_wofireMux_T_1044 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1084], _out_wofireMux_T_1044 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1083], _out_wofireMux_T_1044 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1045 = eq(_out_T_1603, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1046 = or(out_wofireMux_out_259, _out_wofireMux_T_1045) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_260 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1047 = and(_out_wofireMux_T_262, out_backSel_196) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1048 = and(_out_wofireMux_T_1047, _out_T_1353) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_260, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[119], _out_wofireMux_T_1048 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[118], _out_wofireMux_T_1048 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[117], _out_wofireMux_T_1048 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[116], _out_wofireMux_T_1048 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[115], _out_wofireMux_T_1048 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[114], _out_wofireMux_T_1048 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[113], _out_wofireMux_T_1048 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[112], _out_wofireMux_T_1048 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1049 = eq(_out_T_1353, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1050 = or(out_wofireMux_out_260, _out_wofireMux_T_1049) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_261 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1051 = and(_out_wofireMux_T_262, out_backSel_197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1052 = and(_out_wofireMux_T_1051, _out_T_1417) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_261, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[369], _out_wofireMux_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[368], _out_wofireMux_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[367], _out_wofireMux_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[366], _out_wofireMux_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[365], _out_wofireMux_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[364], _out_wofireMux_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[363], _out_wofireMux_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[362], _out_wofireMux_T_1052 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1053 = eq(_out_T_1417, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1054 = or(out_wofireMux_out_261, _out_wofireMux_T_1053) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_262 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1055 = and(_out_wofireMux_T_262, out_backSel_198) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1056 = and(_out_wofireMux_T_1055, _out_T_1509) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_262, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[714], _out_wofireMux_T_1056 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[713], _out_wofireMux_T_1056 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[712], _out_wofireMux_T_1056 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[711], _out_wofireMux_T_1056 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[710], _out_wofireMux_T_1056 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[709], _out_wofireMux_T_1056 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[708], _out_wofireMux_T_1056 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[707], _out_wofireMux_T_1056 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1057 = eq(_out_T_1509, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1058 = or(out_wofireMux_out_262, _out_wofireMux_T_1057) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_263 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1059 = and(_out_wofireMux_T_262, out_backSel_199) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1060 = and(_out_wofireMux_T_1059, _out_T_1545) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_263, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[858], _out_wofireMux_T_1060 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[857], _out_wofireMux_T_1060 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[856], _out_wofireMux_T_1060 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[855], _out_wofireMux_T_1060 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[854], _out_wofireMux_T_1060 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[853], _out_wofireMux_T_1060 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[852], _out_wofireMux_T_1060 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[851], _out_wofireMux_T_1060 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1061 = eq(_out_T_1545, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1062 = or(out_wofireMux_out_263, _out_wofireMux_T_1061) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_264 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1063 = and(_out_wofireMux_T_262, out_backSel_200) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1064 = and(_out_wofireMux_T_1063, _out_T_1615) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_264, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1138], _out_wofireMux_T_1064 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1137], _out_wofireMux_T_1064 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1136], _out_wofireMux_T_1064 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1135], _out_wofireMux_T_1064 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1134], _out_wofireMux_T_1064 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1133], _out_wofireMux_T_1064 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1132], _out_wofireMux_T_1064 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1131], _out_wofireMux_T_1064 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1065 = eq(_out_T_1615, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1066 = or(out_wofireMux_out_264, _out_wofireMux_T_1065) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_265 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1067 = and(_out_wofireMux_T_262, out_backSel_201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1068 = and(_out_wofireMux_T_1067, _out_T_1397) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_265, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[295], _out_wofireMux_T_1068 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[294], _out_wofireMux_T_1068 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[293], _out_wofireMux_T_1068 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[292], _out_wofireMux_T_1068 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[291], _out_wofireMux_T_1068 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[290], _out_wofireMux_T_1068 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[289], _out_wofireMux_T_1068 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[288], _out_wofireMux_T_1068 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1069 = eq(_out_T_1397, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1070 = or(out_wofireMux_out_265, _out_wofireMux_T_1069) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_266 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1071 = and(_out_wofireMux_T_262, out_backSel_202) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1072 = and(_out_wofireMux_T_1071, _out_T_1337) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_266, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[55], _out_wofireMux_T_1072 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[54], _out_wofireMux_T_1072 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[53], _out_wofireMux_T_1072 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[52], _out_wofireMux_T_1072 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[51], _out_wofireMux_T_1072 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[50], _out_wofireMux_T_1072 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[49], _out_wofireMux_T_1072 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[48], _out_wofireMux_T_1072 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1073 = eq(_out_T_1337, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1074 = or(out_wofireMux_out_266, _out_wofireMux_T_1073) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_267 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1075 = and(_out_wofireMux_T_262, out_backSel_203) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1076 = and(_out_wofireMux_T_1075, _out_T_1557) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_267, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[906], _out_wofireMux_T_1076 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[905], _out_wofireMux_T_1076 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[904], _out_wofireMux_T_1076 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[903], _out_wofireMux_T_1076 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[902], _out_wofireMux_T_1076 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[901], _out_wofireMux_T_1076 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[900], _out_wofireMux_T_1076 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[899], _out_wofireMux_T_1076 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1077 = eq(_out_T_1557, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1078 = or(out_wofireMux_out_267, _out_wofireMux_T_1077) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_268 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1079 = and(_out_wofireMux_T_262, out_backSel_204) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1080 = and(_out_wofireMux_T_1079, _out_T_1477) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_268, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[592], _out_wofireMux_T_1080 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[591], _out_wofireMux_T_1080 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[590], _out_wofireMux_T_1080 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[589], _out_wofireMux_T_1080 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[588], _out_wofireMux_T_1080 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[587], _out_wofireMux_T_1080 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[586], _out_wofireMux_T_1080 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[585], _out_wofireMux_T_1080 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1081 = eq(_out_T_1477, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1082 = or(out_wofireMux_out_268, _out_wofireMux_T_1081) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_269 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1083 = and(_out_wofireMux_T_262, out_backSel_205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1084 = and(_out_wofireMux_T_1083, _out_T_1449) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_269, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[486], _out_wofireMux_T_1084 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[485], _out_wofireMux_T_1084 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[484], _out_wofireMux_T_1084 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[483], _out_wofireMux_T_1084 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[482], _out_wofireMux_T_1084 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[481], _out_wofireMux_T_1084 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[480], _out_wofireMux_T_1084 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[479], _out_wofireMux_T_1084 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1085 = eq(_out_T_1449, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1086 = or(out_wofireMux_out_269, _out_wofireMux_T_1085) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_270 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1087 = and(_out_wofireMux_T_262, out_backSel_206) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1088 = and(_out_wofireMux_T_1087, _out_T_1391) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_270, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[271], _out_wofireMux_T_1088 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[270], _out_wofireMux_T_1088 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[269], _out_wofireMux_T_1088 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[268], _out_wofireMux_T_1088 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[267], _out_wofireMux_T_1088 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[266], _out_wofireMux_T_1088 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[265], _out_wofireMux_T_1088 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[264], _out_wofireMux_T_1088 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1089 = eq(_out_T_1391, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1090 = or(out_wofireMux_out_270, _out_wofireMux_T_1089) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_271 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1091 = and(_out_wofireMux_T_262, out_backSel_207) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1092 = and(_out_wofireMux_T_1091, _out_T_1577) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_271, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[986], _out_wofireMux_T_1092 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[985], _out_wofireMux_T_1092 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[984], _out_wofireMux_T_1092 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[983], _out_wofireMux_T_1092 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[982], _out_wofireMux_T_1092 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[981], _out_wofireMux_T_1092 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[980], _out_wofireMux_T_1092 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[979], _out_wofireMux_T_1092 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1093 = eq(_out_T_1577, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1094 = or(out_wofireMux_out_271, _out_wofireMux_T_1093) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_272 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1095 = and(_out_wofireMux_T_262, out_backSel_208) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1096 = and(_out_wofireMux_T_1095, _out_T_1499) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_272, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[680], _out_wofireMux_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[679], _out_wofireMux_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[678], _out_wofireMux_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[677], _out_wofireMux_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[676], _out_wofireMux_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[675], _out_wofireMux_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[674], _out_wofireMux_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[673], _out_wofireMux_T_1096 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1097 = eq(_out_T_1499, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1098 = or(out_wofireMux_out_272, _out_wofireMux_T_1097) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_273 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1099 = and(_out_wofireMux_T_262, out_backSel_209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1100 = and(_out_wofireMux_T_1099, _out_T_1533) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_273, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[810], _out_wofireMux_T_1100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[809], _out_wofireMux_T_1100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[808], _out_wofireMux_T_1100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[807], _out_wofireMux_T_1100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[806], _out_wofireMux_T_1100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[805], _out_wofireMux_T_1100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[804], _out_wofireMux_T_1100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[803], _out_wofireMux_T_1100 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1101 = eq(_out_T_1533, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1102 = or(out_wofireMux_out_273, _out_wofireMux_T_1101) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_274 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1103 = and(_out_wofireMux_T_262, out_backSel_210) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1104 = and(_out_wofireMux_T_1103, _out_T_1597) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_274, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1066], _out_wofireMux_T_1104 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1065], _out_wofireMux_T_1104 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1064], _out_wofireMux_T_1104 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1063], _out_wofireMux_T_1104 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1062], _out_wofireMux_T_1104 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1061], _out_wofireMux_T_1104 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1060], _out_wofireMux_T_1104 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1059], _out_wofireMux_T_1104 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1105 = eq(_out_T_1597, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1106 = or(out_wofireMux_out_274, _out_wofireMux_T_1105) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_275 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1107 = and(_out_wofireMux_T_262, out_backSel_211) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1108 = and(_out_wofireMux_T_1107, _out_T_1375) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_275, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[207], _out_wofireMux_T_1108 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[206], _out_wofireMux_T_1108 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[205], _out_wofireMux_T_1108 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[204], _out_wofireMux_T_1108 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[203], _out_wofireMux_T_1108 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[202], _out_wofireMux_T_1108 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[201], _out_wofireMux_T_1108 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[200], _out_wofireMux_T_1108 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1109 = eq(_out_T_1375, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1110 = or(out_wofireMux_out_275, _out_wofireMux_T_1109) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_276 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1111 = and(_out_wofireMux_T_262, out_backSel_212) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1112 = and(_out_wofireMux_T_1111, _out_T_1433) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_276, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[433], _out_wofireMux_T_1112 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[432], _out_wofireMux_T_1112 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[431], _out_wofireMux_T_1112 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[430], _out_wofireMux_T_1112 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[429], _out_wofireMux_T_1112 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[428], _out_wofireMux_T_1112 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[427], _out_wofireMux_T_1112 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[426], _out_wofireMux_T_1112 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1113 = eq(_out_T_1433, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1114 = or(out_wofireMux_out_276, _out_wofireMux_T_1113) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_277 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1115 = and(_out_wofireMux_T_262, out_backSel_213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1116 = and(_out_wofireMux_T_1115, _out_T_1505) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_277, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[698], _out_wofireMux_T_1116 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[697], _out_wofireMux_T_1116 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[696], _out_wofireMux_T_1116 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[695], _out_wofireMux_T_1116 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[694], _out_wofireMux_T_1116 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[693], _out_wofireMux_T_1116 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[692], _out_wofireMux_T_1116 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[691], _out_wofireMux_T_1116 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1117 = eq(_out_T_1505, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1118 = or(out_wofireMux_out_277, _out_wofireMux_T_1117) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_278 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1119 = and(_out_wofireMux_T_262, out_backSel_214) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1120 = and(_out_wofireMux_T_1119, _out_T_1579) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_278, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[994], _out_wofireMux_T_1120 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[993], _out_wofireMux_T_1120 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[992], _out_wofireMux_T_1120 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[991], _out_wofireMux_T_1120 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[990], _out_wofireMux_T_1120 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[989], _out_wofireMux_T_1120 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[988], _out_wofireMux_T_1120 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[987], _out_wofireMux_T_1120 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1121 = eq(_out_T_1579, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1122 = or(out_wofireMux_out_278, _out_wofireMux_T_1121) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_279 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1123 = and(_out_wofireMux_T_262, out_backSel_215) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1124 = and(_out_wofireMux_T_1123, _out_T_1619) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_279, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1154], _out_wofireMux_T_1124 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1153], _out_wofireMux_T_1124 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1152], _out_wofireMux_T_1124 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1151], _out_wofireMux_T_1124 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1150], _out_wofireMux_T_1124 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1149], _out_wofireMux_T_1124 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1148], _out_wofireMux_T_1124 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1147], _out_wofireMux_T_1124 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1125 = eq(_out_T_1619, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1126 = or(out_wofireMux_out_279, _out_wofireMux_T_1125) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_280 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1127 = and(_out_wofireMux_T_262, out_backSel_216) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1128 = and(_out_wofireMux_T_1127, _out_T_1365) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_280, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[167], _out_wofireMux_T_1128 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[166], _out_wofireMux_T_1128 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[165], _out_wofireMux_T_1128 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[164], _out_wofireMux_T_1128 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[163], _out_wofireMux_T_1128 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[162], _out_wofireMux_T_1128 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[161], _out_wofireMux_T_1128 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[160], _out_wofireMux_T_1128 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1129 = eq(_out_T_1365, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1130 = or(out_wofireMux_out_280, _out_wofireMux_T_1129) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_281 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1131 = and(_out_wofireMux_T_262, out_backSel_217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1132 = and(_out_wofireMux_T_1131, _out_T_1333) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_281, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[39], _out_wofireMux_T_1132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[38], _out_wofireMux_T_1132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[37], _out_wofireMux_T_1132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[36], _out_wofireMux_T_1132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[35], _out_wofireMux_T_1132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[34], _out_wofireMux_T_1132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[33], _out_wofireMux_T_1132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[32], _out_wofireMux_T_1132 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1133 = eq(_out_T_1333, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1134 = or(out_wofireMux_out_281, _out_wofireMux_T_1133) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_282 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1135 = and(_out_wofireMux_T_262, out_backSel_218) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1136 = and(_out_wofireMux_T_1135, _out_T_1559) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_282, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[914], _out_wofireMux_T_1136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[913], _out_wofireMux_T_1136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[912], _out_wofireMux_T_1136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[911], _out_wofireMux_T_1136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[910], _out_wofireMux_T_1136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[909], _out_wofireMux_T_1136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[908], _out_wofireMux_T_1136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[907], _out_wofireMux_T_1136 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1137 = eq(_out_T_1559, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1138 = or(out_wofireMux_out_282, _out_wofireMux_T_1137) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_283 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1139 = and(_out_wofireMux_T_262, out_backSel_219) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1140 = and(_out_wofireMux_T_1139, _out_T_1493) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_283, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[656], _out_wofireMux_T_1140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[655], _out_wofireMux_T_1140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[654], _out_wofireMux_T_1140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[653], _out_wofireMux_T_1140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[652], _out_wofireMux_T_1140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[651], _out_wofireMux_T_1140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[650], _out_wofireMux_T_1140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[649], _out_wofireMux_T_1140 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1141 = eq(_out_T_1493, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1142 = or(out_wofireMux_out_283, _out_wofireMux_T_1141) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_284 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1143 = and(_out_wofireMux_T_262, out_backSel_220) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1144 = and(_out_wofireMux_T_1143, _out_T_1399) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_284, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[303], _out_wofireMux_T_1144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[302], _out_wofireMux_T_1144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[301], _out_wofireMux_T_1144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[300], _out_wofireMux_T_1144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[299], _out_wofireMux_T_1144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[298], _out_wofireMux_T_1144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[297], _out_wofireMux_T_1144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[296], _out_wofireMux_T_1144 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1145 = eq(_out_T_1399, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1146 = or(out_wofireMux_out_284, _out_wofireMux_T_1145) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_285 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1147 = and(_out_wofireMux_T_262, out_backSel_221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1148 = and(_out_wofireMux_T_1147, _out_T_1381) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_285, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[231], _out_wofireMux_T_1148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[230], _out_wofireMux_T_1148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[229], _out_wofireMux_T_1148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[228], _out_wofireMux_T_1148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[227], _out_wofireMux_T_1148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[226], _out_wofireMux_T_1148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[225], _out_wofireMux_T_1148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[224], _out_wofireMux_T_1148 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1149 = eq(_out_T_1381, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1150 = or(out_wofireMux_out_285, _out_wofireMux_T_1149) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_286 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1151 = and(_out_wofireMux_T_262, out_backSel_222) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1152 = and(_out_wofireMux_T_1151, _out_T_1621) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_286, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1162], _out_wofireMux_T_1152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1161], _out_wofireMux_T_1152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1160], _out_wofireMux_T_1152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1159], _out_wofireMux_T_1152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1158], _out_wofireMux_T_1152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1157], _out_wofireMux_T_1152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1156], _out_wofireMux_T_1152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1155], _out_wofireMux_T_1152 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1153 = eq(_out_T_1621, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1154 = or(out_wofireMux_out_286, _out_wofireMux_T_1153) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_287 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1155 = and(_out_wofireMux_T_262, out_backSel_223) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1156 = and(_out_wofireMux_T_1155, _out_T_1519) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_287, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[754], _out_wofireMux_T_1156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[753], _out_wofireMux_T_1156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[752], _out_wofireMux_T_1156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[751], _out_wofireMux_T_1156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[750], _out_wofireMux_T_1156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[749], _out_wofireMux_T_1156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[748], _out_wofireMux_T_1156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[747], _out_wofireMux_T_1156 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1157 = eq(_out_T_1519, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1158 = or(out_wofireMux_out_287, _out_wofireMux_T_1157) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_288 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1159 = and(_out_wofireMux_T_262, out_backSel_224) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1160 = and(_out_wofireMux_T_1159, _out_T_1419) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_288, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[377], _out_wofireMux_T_1160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[376], _out_wofireMux_T_1160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[375], _out_wofireMux_T_1160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[374], _out_wofireMux_T_1160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[373], _out_wofireMux_T_1160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[372], _out_wofireMux_T_1160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[371], _out_wofireMux_T_1160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[370], _out_wofireMux_T_1160 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1161 = eq(_out_T_1419, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1162 = or(out_wofireMux_out_288, _out_wofireMux_T_1161) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_289 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1163 = and(_out_wofireMux_T_262, out_backSel_225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1164 = and(_out_wofireMux_T_1163, _out_T_1429) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_289, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[417], _out_wofireMux_T_1164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[416], _out_wofireMux_T_1164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[415], _out_wofireMux_T_1164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[414], _out_wofireMux_T_1164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[413], _out_wofireMux_T_1164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[412], _out_wofireMux_T_1164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[411], _out_wofireMux_T_1164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[410], _out_wofireMux_T_1164 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1165 = eq(_out_T_1429, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1166 = or(out_wofireMux_out_289, _out_wofireMux_T_1165) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_290 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1167 = and(_out_wofireMux_T_262, out_backSel_226) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1168 = and(_out_wofireMux_T_1167, _out_T_1523) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_290, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[770], _out_wofireMux_T_1168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[769], _out_wofireMux_T_1168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[768], _out_wofireMux_T_1168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[767], _out_wofireMux_T_1168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[766], _out_wofireMux_T_1168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[765], _out_wofireMux_T_1168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[764], _out_wofireMux_T_1168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[763], _out_wofireMux_T_1168 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1169 = eq(_out_T_1523, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1170 = or(out_wofireMux_out_290, _out_wofireMux_T_1169) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_291 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1171 = and(_out_wofireMux_T_262, out_backSel_227) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1172 = and(_out_wofireMux_T_1171, _out_T_1627) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_291, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1186], _out_wofireMux_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1185], _out_wofireMux_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1184], _out_wofireMux_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1183], _out_wofireMux_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1182], _out_wofireMux_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1181], _out_wofireMux_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1180], _out_wofireMux_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1179], _out_wofireMux_T_1172 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1173 = eq(_out_T_1627, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1174 = or(out_wofireMux_out_291, _out_wofireMux_T_1173) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_292 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1175 = and(_out_wofireMux_T_262, out_backSel_228) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1176 = and(_out_wofireMux_T_1175, _out_T_1361) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_292, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[151], _out_wofireMux_T_1176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[150], _out_wofireMux_T_1176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[149], _out_wofireMux_T_1176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[148], _out_wofireMux_T_1176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[147], _out_wofireMux_T_1176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[146], _out_wofireMux_T_1176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[145], _out_wofireMux_T_1176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[144], _out_wofireMux_T_1176 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1177 = eq(_out_T_1361, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1178 = or(out_wofireMux_out_292, _out_wofireMux_T_1177) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_293 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1179 = and(_out_wofireMux_T_262, out_backSel_229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1180 = and(_out_wofireMux_T_1179, _out_T_1413) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_293, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[353], _out_wofireMux_T_1180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[352], _out_wofireMux_T_1180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[351], _out_wofireMux_T_1180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[350], _out_wofireMux_T_1180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[349], _out_wofireMux_T_1180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[348], _out_wofireMux_T_1180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[347], _out_wofireMux_T_1180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[346], _out_wofireMux_T_1180 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1181 = eq(_out_T_1413, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1182 = or(out_wofireMux_out_293, _out_wofireMux_T_1181) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_294 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1183 = and(_out_wofireMux_T_262, out_backSel_230) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1184 = and(_out_wofireMux_T_1183, _out_T_1495) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_294, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[664], _out_wofireMux_T_1184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[663], _out_wofireMux_T_1184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[662], _out_wofireMux_T_1184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[661], _out_wofireMux_T_1184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[660], _out_wofireMux_T_1184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[659], _out_wofireMux_T_1184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[658], _out_wofireMux_T_1184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[657], _out_wofireMux_T_1184 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1185 = eq(_out_T_1495, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1186 = or(out_wofireMux_out_294, _out_wofireMux_T_1185) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_295 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1187 = and(_out_wofireMux_T_262, out_backSel_231) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1188 = and(_out_wofireMux_T_1187, _out_T_1565) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_295, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[938], _out_wofireMux_T_1188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[937], _out_wofireMux_T_1188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[936], _out_wofireMux_T_1188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[935], _out_wofireMux_T_1188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[934], _out_wofireMux_T_1188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[933], _out_wofireMux_T_1188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[932], _out_wofireMux_T_1188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[931], _out_wofireMux_T_1188 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1189 = eq(_out_T_1565, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1190 = or(out_wofireMux_out_295, _out_wofireMux_T_1189) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_296 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1191 = and(_out_wofireMux_T_262, out_backSel_232) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1192 = and(_out_wofireMux_T_1191, _out_T_1623) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_296, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1170], _out_wofireMux_T_1192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1169], _out_wofireMux_T_1192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1168], _out_wofireMux_T_1192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1167], _out_wofireMux_T_1192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1166], _out_wofireMux_T_1192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1165], _out_wofireMux_T_1192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1164], _out_wofireMux_T_1192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1163], _out_wofireMux_T_1192 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1193 = eq(_out_T_1623, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1194 = or(out_wofireMux_out_296, _out_wofireMux_T_1193) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_297 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1195 = and(_out_wofireMux_T_262, out_backSel_233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1196 = and(_out_wofireMux_T_1195, _out_T_1393) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_297, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[279], _out_wofireMux_T_1196 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[278], _out_wofireMux_T_1196 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[277], _out_wofireMux_T_1196 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[276], _out_wofireMux_T_1196 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[275], _out_wofireMux_T_1196 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[274], _out_wofireMux_T_1196 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[273], _out_wofireMux_T_1196 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[272], _out_wofireMux_T_1196 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1197 = eq(_out_T_1393, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1198 = or(out_wofireMux_out_297, _out_wofireMux_T_1197) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_298 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1199 = and(_out_wofireMux_T_262, out_backSel_234) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1200 = and(_out_wofireMux_T_1199, _out_T_1329) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_298, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[23], _out_wofireMux_T_1200 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[22], _out_wofireMux_T_1200 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[21], _out_wofireMux_T_1200 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[20], _out_wofireMux_T_1200 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[19], _out_wofireMux_T_1200 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[18], _out_wofireMux_T_1200 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[17], _out_wofireMux_T_1200 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[16], _out_wofireMux_T_1200 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1201 = eq(_out_T_1329, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1202 = or(out_wofireMux_out_298, _out_wofireMux_T_1201) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_299 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1203 = and(_out_wofireMux_T_262, out_backSel_235) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1204 = and(_out_wofireMux_T_1203, _out_T_1581) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_299, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1002], _out_wofireMux_T_1204 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1001], _out_wofireMux_T_1204 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1000], _out_wofireMux_T_1204 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[999], _out_wofireMux_T_1204 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[998], _out_wofireMux_T_1204 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[997], _out_wofireMux_T_1204 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[996], _out_wofireMux_T_1204 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[995], _out_wofireMux_T_1204 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1205 = eq(_out_T_1581, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1206 = or(out_wofireMux_out_299, _out_wofireMux_T_1205) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_300 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1207 = and(_out_wofireMux_T_262, out_backSel_236) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1208 = and(_out_wofireMux_T_1207, _out_T_1483) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_300, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[616], _out_wofireMux_T_1208 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[615], _out_wofireMux_T_1208 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[614], _out_wofireMux_T_1208 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[613], _out_wofireMux_T_1208 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[612], _out_wofireMux_T_1208 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[611], _out_wofireMux_T_1208 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[610], _out_wofireMux_T_1208 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[609], _out_wofireMux_T_1208 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1209 = eq(_out_T_1483, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1210 = or(out_wofireMux_out_300, _out_wofireMux_T_1209) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_301 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1211 = and(_out_wofireMux_T_262, out_backSel_237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1212 = and(_out_wofireMux_T_1211, _out_T_1453) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_301, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[502], _out_wofireMux_T_1212 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[501], _out_wofireMux_T_1212 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[500], _out_wofireMux_T_1212 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[499], _out_wofireMux_T_1212 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[498], _out_wofireMux_T_1212 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[497], _out_wofireMux_T_1212 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[496], _out_wofireMux_T_1212 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[495], _out_wofireMux_T_1212 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1213 = eq(_out_T_1453, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1214 = or(out_wofireMux_out_301, _out_wofireMux_T_1213) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_302 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1215 = and(_out_wofireMux_T_262, out_backSel_238) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1216 = and(_out_wofireMux_T_1215, _out_T_1373) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_302, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[199], _out_wofireMux_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[198], _out_wofireMux_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[197], _out_wofireMux_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[196], _out_wofireMux_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[195], _out_wofireMux_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[194], _out_wofireMux_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[193], _out_wofireMux_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[192], _out_wofireMux_T_1216 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1217 = eq(_out_T_1373, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1218 = or(out_wofireMux_out_302, _out_wofireMux_T_1217) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_303 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1219 = and(_out_wofireMux_T_262, out_backSel_239) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1220 = and(_out_wofireMux_T_1219, _out_T_1605) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_303, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1098], _out_wofireMux_T_1220 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1097], _out_wofireMux_T_1220 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1096], _out_wofireMux_T_1220 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1095], _out_wofireMux_T_1220 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1094], _out_wofireMux_T_1220 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1093], _out_wofireMux_T_1220 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1092], _out_wofireMux_T_1220 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1091], _out_wofireMux_T_1220 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1221 = eq(_out_T_1605, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1222 = or(out_wofireMux_out_303, _out_wofireMux_T_1221) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_304 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1223 = and(_out_wofireMux_T_262, out_backSel_240) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1224 = and(_out_wofireMux_T_1223, _out_T_1513) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_304, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[730], _out_wofireMux_T_1224 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[729], _out_wofireMux_T_1224 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[728], _out_wofireMux_T_1224 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[727], _out_wofireMux_T_1224 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[726], _out_wofireMux_T_1224 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[725], _out_wofireMux_T_1224 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[724], _out_wofireMux_T_1224 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[723], _out_wofireMux_T_1224 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1225 = eq(_out_T_1513, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1226 = or(out_wofireMux_out_304, _out_wofireMux_T_1225) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_305 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1227 = and(_out_wofireMux_T_262, out_backSel_241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1228 = and(_out_wofireMux_T_1227, _out_T_1525) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_305, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[778], _out_wofireMux_T_1228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[777], _out_wofireMux_T_1228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[776], _out_wofireMux_T_1228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[775], _out_wofireMux_T_1228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[774], _out_wofireMux_T_1228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[773], _out_wofireMux_T_1228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[772], _out_wofireMux_T_1228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[771], _out_wofireMux_T_1228 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1229 = eq(_out_T_1525, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1230 = or(out_wofireMux_out_305, _out_wofireMux_T_1229) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_306 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1231 = and(_out_wofireMux_T_262, out_backSel_242) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1232 = and(_out_wofireMux_T_1231, _out_T_1607) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_306, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1106], _out_wofireMux_T_1232 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1105], _out_wofireMux_T_1232 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1104], _out_wofireMux_T_1232 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1103], _out_wofireMux_T_1232 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1102], _out_wofireMux_T_1232 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1101], _out_wofireMux_T_1232 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1100], _out_wofireMux_T_1232 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1099], _out_wofireMux_T_1232 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1233 = eq(_out_T_1607, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1234 = or(out_wofireMux_out_306, _out_wofireMux_T_1233) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_307 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1235 = and(_out_wofireMux_T_262, out_backSel_243) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1236 = and(_out_wofireMux_T_1235, _out_T_1387) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_307, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[255], _out_wofireMux_T_1236 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[254], _out_wofireMux_T_1236 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[253], _out_wofireMux_T_1236 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[252], _out_wofireMux_T_1236 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[251], _out_wofireMux_T_1236 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[250], _out_wofireMux_T_1236 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[249], _out_wofireMux_T_1236 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[248], _out_wofireMux_T_1236 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1237 = eq(_out_T_1387, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1238 = or(out_wofireMux_out_307, _out_wofireMux_T_1237) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_308 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1239 = and(_out_wofireMux_T_262, out_backSel_244) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1240 = and(_out_wofireMux_T_1239, _out_T_1457) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_308, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[518], _out_wofireMux_T_1240 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[517], _out_wofireMux_T_1240 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[516], _out_wofireMux_T_1240 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[515], _out_wofireMux_T_1240 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[514], _out_wofireMux_T_1240 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[513], _out_wofireMux_T_1240 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[512], _out_wofireMux_T_1240 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[511], _out_wofireMux_T_1240 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1241 = eq(_out_T_1457, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1242 = or(out_wofireMux_out_308, _out_wofireMux_T_1241) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_309 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1243 = and(_out_wofireMux_T_262, out_backSel_245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1244 = and(_out_wofireMux_T_1243, _out_T_1497) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_309, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[672], _out_wofireMux_T_1244 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[671], _out_wofireMux_T_1244 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[670], _out_wofireMux_T_1244 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[669], _out_wofireMux_T_1244 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[668], _out_wofireMux_T_1244 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[667], _out_wofireMux_T_1244 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[666], _out_wofireMux_T_1244 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[665], _out_wofireMux_T_1244 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1245 = eq(_out_T_1497, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1246 = or(out_wofireMux_out_309, _out_wofireMux_T_1245) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_310 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1247 = and(_out_wofireMux_T_262, out_backSel_246) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1248 = and(_out_wofireMux_T_1247, _out_T_1583) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_310, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1010], _out_wofireMux_T_1248 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1009], _out_wofireMux_T_1248 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1008], _out_wofireMux_T_1248 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1007], _out_wofireMux_T_1248 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1006], _out_wofireMux_T_1248 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1005], _out_wofireMux_T_1248 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1004], _out_wofireMux_T_1248 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1003], _out_wofireMux_T_1248 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1249 = eq(_out_T_1583, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1250 = or(out_wofireMux_out_310, _out_wofireMux_T_1249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_311 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1251 = and(_out_wofireMux_T_262, out_backSel_247) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1252 = and(_out_wofireMux_T_1251, _out_T_1335) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_311, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[47], _out_wofireMux_T_1252 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[46], _out_wofireMux_T_1252 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[45], _out_wofireMux_T_1252 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[44], _out_wofireMux_T_1252 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[43], _out_wofireMux_T_1252 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[42], _out_wofireMux_T_1252 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[41], _out_wofireMux_T_1252 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[40], _out_wofireMux_T_1252 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1253 = eq(_out_T_1335, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1254 = or(out_wofireMux_out_311, _out_wofireMux_T_1253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_312 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1255 = and(_out_wofireMux_T_262, out_backSel_248) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1256 = and(_out_wofireMux_T_1255, _out_T_1395) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_312, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[287], _out_wofireMux_T_1256 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[286], _out_wofireMux_T_1256 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[285], _out_wofireMux_T_1256 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[284], _out_wofireMux_T_1256 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[283], _out_wofireMux_T_1256 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[282], _out_wofireMux_T_1256 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[281], _out_wofireMux_T_1256 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[280], _out_wofireMux_T_1256 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1257 = eq(_out_T_1395, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1258 = or(out_wofireMux_out_312, _out_wofireMux_T_1257) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_313 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1259 = and(_out_wofireMux_T_262, out_backSel_249) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1260 = and(_out_wofireMux_T_1259, _out_T_1327) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_313, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[15], _out_wofireMux_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[14], _out_wofireMux_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[13], _out_wofireMux_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[12], _out_wofireMux_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[11], _out_wofireMux_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[10], _out_wofireMux_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[9], _out_wofireMux_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[8], _out_wofireMux_T_1260 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1261 = eq(_out_T_1327, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1262 = or(out_wofireMux_out_313, _out_wofireMux_T_1261) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_314 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1263 = and(_out_wofireMux_T_262, out_backSel_250) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1264 = and(_out_wofireMux_T_1263, _out_T_1563) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_314, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[930], _out_wofireMux_T_1264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[929], _out_wofireMux_T_1264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[928], _out_wofireMux_T_1264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[927], _out_wofireMux_T_1264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[926], _out_wofireMux_T_1264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[925], _out_wofireMux_T_1264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[924], _out_wofireMux_T_1264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[923], _out_wofireMux_T_1264 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1265 = eq(_out_T_1563, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1266 = or(out_wofireMux_out_314, _out_wofireMux_T_1265) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_315 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1267 = and(_out_wofireMux_T_262, out_backSel_251) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1268 = and(_out_wofireMux_T_1267, _out_T_1515) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_315, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[738], _out_wofireMux_T_1268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[737], _out_wofireMux_T_1268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[736], _out_wofireMux_T_1268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[735], _out_wofireMux_T_1268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[734], _out_wofireMux_T_1268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[733], _out_wofireMux_T_1268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[732], _out_wofireMux_T_1268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[731], _out_wofireMux_T_1268 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1269 = eq(_out_T_1515, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1270 = or(out_wofireMux_out_315, _out_wofireMux_T_1269) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_316 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1271 = and(_out_wofireMux_T_262, out_backSel_252) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1272 = and(_out_wofireMux_T_1271, _out_T_1415) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_316, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[361], _out_wofireMux_T_1272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[360], _out_wofireMux_T_1272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[359], _out_wofireMux_T_1272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[358], _out_wofireMux_T_1272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[357], _out_wofireMux_T_1272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[356], _out_wofireMux_T_1272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[355], _out_wofireMux_T_1272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[354], _out_wofireMux_T_1272 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1273 = eq(_out_T_1415, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1274 = or(out_wofireMux_out_316, _out_wofireMux_T_1273) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_317 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1275 = and(_out_wofireMux_T_262, out_backSel_253) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1276 = and(_out_wofireMux_T_1275, _out_T_1377) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_317, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[215], _out_wofireMux_T_1276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[214], _out_wofireMux_T_1276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[213], _out_wofireMux_T_1276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[212], _out_wofireMux_T_1276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[211], _out_wofireMux_T_1276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[210], _out_wofireMux_T_1276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[209], _out_wofireMux_T_1276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[208], _out_wofireMux_T_1276 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1277 = eq(_out_T_1377, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1278 = or(out_wofireMux_out_317, _out_wofireMux_T_1277) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_318 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1279 = and(_out_wofireMux_T_262, out_backSel_254) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1280 = and(_out_wofireMux_T_1279, _out_T_1625) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_318, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1178], _out_wofireMux_T_1280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1177], _out_wofireMux_T_1280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1176], _out_wofireMux_T_1280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1175], _out_wofireMux_T_1280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1174], _out_wofireMux_T_1280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1173], _out_wofireMux_T_1280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1172], _out_wofireMux_T_1280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[1171], _out_wofireMux_T_1280 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1281 = eq(_out_T_1625, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1282 = or(out_wofireMux_out_318, _out_wofireMux_T_1281) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_319 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1283 = and(_out_wofireMux_T_262, out_backSel_255) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1284 = and(_out_wofireMux_T_1283, _out_T_1531) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_319, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[802], _out_wofireMux_T_1284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[801], _out_wofireMux_T_1284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[800], _out_wofireMux_T_1284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[799], _out_wofireMux_T_1284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[798], _out_wofireMux_T_1284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[797], _out_wofireMux_T_1284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[796], _out_wofireMux_T_1284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready_1[795], _out_wofireMux_T_1284 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_1285 = eq(_out_T_1531, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1286 = or(out_wofireMux_out_319, _out_wofireMux_T_1285) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1287 = geq(out_oindex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_wofireMux_WIRE_1 : UInt<1>[256] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[0], _out_wofireMux_T_266 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[1], _out_wofireMux_T_270 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[2], _out_wofireMux_T_274 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[3], _out_wofireMux_T_278 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[4], _out_wofireMux_T_282 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[5], _out_wofireMux_T_286 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[6], _out_wofireMux_T_290 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[7], _out_wofireMux_T_294 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[8], _out_wofireMux_T_298 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[9], _out_wofireMux_T_302 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[10], _out_wofireMux_T_306 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[11], _out_wofireMux_T_310 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[12], _out_wofireMux_T_314 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[13], _out_wofireMux_T_318 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[14], _out_wofireMux_T_322 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[15], _out_wofireMux_T_326 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[16], _out_wofireMux_T_330 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[17], _out_wofireMux_T_334 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[18], _out_wofireMux_T_338 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[19], _out_wofireMux_T_342 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[20], _out_wofireMux_T_346 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[21], _out_wofireMux_T_350 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[22], _out_wofireMux_T_354 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[23], _out_wofireMux_T_358 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[24], _out_wofireMux_T_362 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[25], _out_wofireMux_T_366 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[26], _out_wofireMux_T_370 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[27], _out_wofireMux_T_374 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[28], _out_wofireMux_T_378 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[29], _out_wofireMux_T_382 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[30], _out_wofireMux_T_386 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[31], _out_wofireMux_T_390 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[32], _out_wofireMux_T_394 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[33], _out_wofireMux_T_398 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[34], _out_wofireMux_T_402 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[35], _out_wofireMux_T_406 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[36], _out_wofireMux_T_410 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[37], _out_wofireMux_T_414 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[38], _out_wofireMux_T_418 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[39], _out_wofireMux_T_422 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[40], _out_wofireMux_T_426 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[41], _out_wofireMux_T_430 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[42], _out_wofireMux_T_434 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[43], _out_wofireMux_T_438 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[44], _out_wofireMux_T_442 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[45], _out_wofireMux_T_446 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[46], _out_wofireMux_T_450 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[47], _out_wofireMux_T_454 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[48], _out_wofireMux_T_458 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[49], _out_wofireMux_T_462 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[50], _out_wofireMux_T_466 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[51], _out_wofireMux_T_470 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[52], _out_wofireMux_T_474 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[53], _out_wofireMux_T_478 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[54], _out_wofireMux_T_482 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[55], _out_wofireMux_T_486 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[56], _out_wofireMux_T_490 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[57], _out_wofireMux_T_494 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[58], _out_wofireMux_T_498 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[59], _out_wofireMux_T_502 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[60], _out_wofireMux_T_506 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[61], _out_wofireMux_T_510 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[62], _out_wofireMux_T_514 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[63], _out_wofireMux_T_518 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[64], _out_wofireMux_T_522 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[65], _out_wofireMux_T_526 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[66], _out_wofireMux_T_530 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[67], _out_wofireMux_T_534 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[68], _out_wofireMux_T_538 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[69], _out_wofireMux_T_542 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[70], _out_wofireMux_T_546 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[71], _out_wofireMux_T_550 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[72], _out_wofireMux_T_554 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[73], _out_wofireMux_T_558 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[74], _out_wofireMux_T_562 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[75], _out_wofireMux_T_566 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[76], _out_wofireMux_T_570 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[77], _out_wofireMux_T_574 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[78], _out_wofireMux_T_578 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[79], _out_wofireMux_T_582 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[80], _out_wofireMux_T_586 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[81], _out_wofireMux_T_590 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[82], _out_wofireMux_T_594 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[83], _out_wofireMux_T_598 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[84], _out_wofireMux_T_602 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[85], _out_wofireMux_T_606 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[86], _out_wofireMux_T_610 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[87], _out_wofireMux_T_614 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[88], _out_wofireMux_T_618 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[89], _out_wofireMux_T_622 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[90], _out_wofireMux_T_626 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[91], _out_wofireMux_T_630 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[92], _out_wofireMux_T_634 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[93], _out_wofireMux_T_638 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[94], _out_wofireMux_T_642 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[95], _out_wofireMux_T_646 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[96], _out_wofireMux_T_650 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[97], _out_wofireMux_T_654 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[98], _out_wofireMux_T_658 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[99], _out_wofireMux_T_662 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[100], _out_wofireMux_T_666 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[101], _out_wofireMux_T_670 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[102], _out_wofireMux_T_674 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[103], _out_wofireMux_T_678 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[104], _out_wofireMux_T_682 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[105], _out_wofireMux_T_686 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[106], _out_wofireMux_T_690 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[107], _out_wofireMux_T_694 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[108], _out_wofireMux_T_698 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[109], _out_wofireMux_T_702 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[110], _out_wofireMux_T_706 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[111], _out_wofireMux_T_710 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[112], _out_wofireMux_T_714 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[113], _out_wofireMux_T_718 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[114], _out_wofireMux_T_722 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[115], _out_wofireMux_T_726 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[116], _out_wofireMux_T_730 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[117], _out_wofireMux_T_734 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[118], _out_wofireMux_T_738 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[119], _out_wofireMux_T_742 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[120], _out_wofireMux_T_746 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[121], _out_wofireMux_T_750 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[122], _out_wofireMux_T_754 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[123], _out_wofireMux_T_758 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[124], _out_wofireMux_T_762 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[125], _out_wofireMux_T_766 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[126], _out_wofireMux_T_770 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[127], _out_wofireMux_T_774 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[128], _out_wofireMux_T_778 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[129], _out_wofireMux_T_782 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[130], _out_wofireMux_T_786 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[131], _out_wofireMux_T_790 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[132], _out_wofireMux_T_794 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[133], _out_wofireMux_T_798 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[134], _out_wofireMux_T_802 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[135], _out_wofireMux_T_806 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[136], _out_wofireMux_T_810 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[137], _out_wofireMux_T_814 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[138], _out_wofireMux_T_818 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[139], _out_wofireMux_T_822 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[140], _out_wofireMux_T_826 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[141], _out_wofireMux_T_830 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[142], _out_wofireMux_T_834 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[143], _out_wofireMux_T_838 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[144], _out_wofireMux_T_842 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[145], _out_wofireMux_T_846 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[146], _out_wofireMux_T_850 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[147], _out_wofireMux_T_854 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[148], _out_wofireMux_T_858 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[149], _out_wofireMux_T_862 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[150], _out_wofireMux_T_866 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[151], _out_wofireMux_T_870 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[152], _out_wofireMux_T_874 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[153], _out_wofireMux_T_878 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[154], _out_wofireMux_T_882 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[155], _out_wofireMux_T_886 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[156], _out_wofireMux_T_890 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[157], _out_wofireMux_T_894 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[158], _out_wofireMux_T_898 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[159], _out_wofireMux_T_902 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[160], _out_wofireMux_T_906 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[161], _out_wofireMux_T_910 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[162], _out_wofireMux_T_914 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[163], _out_wofireMux_T_918 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[164], _out_wofireMux_T_922 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[165], _out_wofireMux_T_926 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[166], _out_wofireMux_T_930 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[167], _out_wofireMux_T_934 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[168], _out_wofireMux_T_938 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[169], _out_wofireMux_T_942 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[170], _out_wofireMux_T_946 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[171], _out_wofireMux_T_950 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[172], _out_wofireMux_T_954 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[173], _out_wofireMux_T_958 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[174], _out_wofireMux_T_962 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[175], _out_wofireMux_T_966 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[176], _out_wofireMux_T_970 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[177], _out_wofireMux_T_974 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[178], _out_wofireMux_T_978 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[179], _out_wofireMux_T_982 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[180], _out_wofireMux_T_986 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[181], _out_wofireMux_T_990 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[182], _out_wofireMux_T_994 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[183], _out_wofireMux_T_998 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[184], _out_wofireMux_T_1002 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[185], _out_wofireMux_T_1006 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[186], _out_wofireMux_T_1010 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[187], _out_wofireMux_T_1014 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[188], _out_wofireMux_T_1018 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[189], _out_wofireMux_T_1022 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[190], _out_wofireMux_T_1026 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[191], _out_wofireMux_T_1030 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[192], _out_wofireMux_T_1034 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[193], _out_wofireMux_T_1038 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[194], _out_wofireMux_T_1042 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[195], _out_wofireMux_T_1046 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[196], _out_wofireMux_T_1050 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[197], _out_wofireMux_T_1054 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[198], _out_wofireMux_T_1058 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[199], _out_wofireMux_T_1062 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[200], _out_wofireMux_T_1066 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[201], _out_wofireMux_T_1070 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[202], _out_wofireMux_T_1074 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[203], _out_wofireMux_T_1078 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[204], _out_wofireMux_T_1082 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[205], _out_wofireMux_T_1086 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[206], _out_wofireMux_T_1090 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[207], _out_wofireMux_T_1094 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[208], _out_wofireMux_T_1098 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[209], _out_wofireMux_T_1102 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[210], _out_wofireMux_T_1106 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[211], _out_wofireMux_T_1110 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[212], _out_wofireMux_T_1114 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[213], _out_wofireMux_T_1118 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[214], _out_wofireMux_T_1122 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[215], _out_wofireMux_T_1126 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[216], _out_wofireMux_T_1130 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[217], _out_wofireMux_T_1134 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[218], _out_wofireMux_T_1138 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[219], _out_wofireMux_T_1142 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[220], _out_wofireMux_T_1146 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[221], _out_wofireMux_T_1150 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[222], _out_wofireMux_T_1154 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[223], _out_wofireMux_T_1158 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[224], _out_wofireMux_T_1162 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[225], _out_wofireMux_T_1166 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[226], _out_wofireMux_T_1170 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[227], _out_wofireMux_T_1174 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[228], _out_wofireMux_T_1178 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[229], _out_wofireMux_T_1182 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[230], _out_wofireMux_T_1186 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[231], _out_wofireMux_T_1190 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[232], _out_wofireMux_T_1194 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[233], _out_wofireMux_T_1198 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[234], _out_wofireMux_T_1202 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[235], _out_wofireMux_T_1206 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[236], _out_wofireMux_T_1210 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[237], _out_wofireMux_T_1214 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[238], _out_wofireMux_T_1218 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[239], _out_wofireMux_T_1222 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[240], _out_wofireMux_T_1226 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[241], _out_wofireMux_T_1230 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[242], _out_wofireMux_T_1234 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[243], _out_wofireMux_T_1238 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[244], _out_wofireMux_T_1242 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[245], _out_wofireMux_T_1246 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[246], _out_wofireMux_T_1250 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[247], _out_wofireMux_T_1254 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[248], _out_wofireMux_T_1258 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[249], _out_wofireMux_T_1262 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[250], _out_wofireMux_T_1266 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[251], _out_wofireMux_T_1270 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[252], _out_wofireMux_T_1274 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[253], _out_wofireMux_T_1278 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[254], _out_wofireMux_T_1282 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE_1[255], _out_wofireMux_T_1286 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_wofireMux_1 = mux(_out_wofireMux_T_1287, UInt<1>(0h1), _out_wofireMux_WIRE_1[out_oindex_1]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node out_iready_1 = mux(out_front_1.bits.read, out_rifireMux_1, out_wifireMux_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oready_1 = mux(out_front_1.bits.read, out_rofireMux_1, out_wofireMux_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_in_ready_T_1 = and(out_front_1.ready, out_iready_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect in_1.ready, _out_in_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_front_valid_T_1 = and(in_1.valid, out_iready_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front_1.valid, _out_front_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_front_ready_T_1 = and(out_1.ready, out_oready_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front_1.ready, _out_front_ready_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_out_valid_T_1 = and(out_front_1.valid, out_oready_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_1.valid, _out_out_valid_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_1.bits.read, out_front_1.bits.read @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_out_bits_data_T_57 = geq(out_oindex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_out_bits_data_WIRE : UInt<1>[256] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[0], _out_T_1439 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[1], _out_T_1347 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[2], _out_T_1567 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[3], _out_T_1479 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[4], _out_T_1401 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[5], _out_T_1363 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[6], _out_T_1595 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[7], _out_T_1543 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[8], _out_T_1465 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[9], _out_T_1389 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[10], _out_T_1447 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[11], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[12], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[13], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[14], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[15], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[16], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[17], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[18], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[19], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[20], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[21], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[22], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[23], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[24], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[25], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[26], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[27], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[28], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[29], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[30], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[31], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[32], _out_T_1461 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[33], _out_T_1411 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[34], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[35], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[36], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[37], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[38], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[39], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[40], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[41], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[42], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[43], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[44], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[45], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[46], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[47], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[48], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[49], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[50], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[51], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[52], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[53], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[54], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[55], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[56], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[57], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[58], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[59], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[60], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[61], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[62], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[63], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[64], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[65], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[66], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[67], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[68], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[69], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[70], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[71], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[72], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[73], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[74], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[75], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[76], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[77], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[78], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[79], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[80], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[81], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[82], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[83], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[84], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[85], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[86], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[87], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[88], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[89], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[90], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[91], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[92], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[93], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[94], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[95], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[96], _out_T_1435 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[97], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[98], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[99], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[100], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[101], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[102], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[103], _out_T_1501 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[104], _out_T_1561 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[105], _out_T_1455 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[106], _out_T_1371 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[107], _out_T_1599 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[108], _out_T_1511 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[109], _out_T_1437 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[110], _out_T_1351 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[111], _out_T_1617 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[112], _out_T_1535 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[113], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[114], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[115], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[116], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[117], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[118], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[119], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[120], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[121], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[122], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[123], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[124], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[125], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[126], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[127], UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[128], _out_T_1451 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[129], _out_T_1443 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[130], _out_T_1517 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[131], _out_T_1609 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[132], _out_T_1383 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[133], _out_T_1385 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[134], _out_T_1445 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[135], _out_T_1521 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[136], _out_T_1601 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[137], _out_T_1407 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[138], _out_T_1325 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[139], _out_T_1575 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[140], _out_T_1503 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[141], _out_T_1427 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[142], _out_T_1339 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[143], _out_T_1555 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[144], _out_T_1481 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[145], _out_T_1539 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[146], _out_T_1587 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[147], _out_T_1379 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[148], _out_T_1463 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[149], _out_T_1471 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[150], _out_T_1541 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[151], _out_T_1585 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[152], _out_T_1359 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[153], _out_T_1341 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[154], _out_T_1551 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[155], _out_T_1507 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[156], _out_T_1421 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[157], _out_T_1355 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[158], _out_T_1569 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[159], _out_T_1487 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[160], _out_T_1403 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[161], _out_T_1467 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[162], _out_T_1529 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[163], _out_T_1613 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[164], _out_T_1367 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[165], _out_T_1409 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[166], _out_T_1459 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[167], _out_T_1527 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[168], _out_T_1593 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[169], _out_T_1425 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[170], _out_T_1331 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[171], _out_T_1573 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[172], _out_T_1491 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[173], _out_T_1441 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[174], _out_T_1343 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[175], _out_T_1553 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[176], _out_T_1473 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[177], _out_T_1547 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[178], _out_T_1611 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[179], _out_T_1369 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[180], _out_T_1469 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[181], _out_T_1485 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[182], _out_T_1549 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[183], _out_T_1591 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[184], _out_T_1349 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[185], _out_T_1345 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[186], _out_T_1571 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[187], _out_T_1489 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[188], _out_T_1423 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[189], _out_T_1357 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[190], _out_T_1589 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[191], _out_T_1475 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[192], _out_T_1405 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[193], _out_T_1431 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[194], _out_T_1537 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[195], _out_T_1603 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[196], _out_T_1353 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[197], _out_T_1417 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[198], _out_T_1509 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[199], _out_T_1545 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[200], _out_T_1615 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[201], _out_T_1397 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[202], _out_T_1337 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[203], _out_T_1557 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[204], _out_T_1477 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[205], _out_T_1449 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[206], _out_T_1391 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[207], _out_T_1577 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[208], _out_T_1499 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[209], _out_T_1533 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[210], _out_T_1597 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[211], _out_T_1375 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[212], _out_T_1433 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[213], _out_T_1505 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[214], _out_T_1579 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[215], _out_T_1619 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[216], _out_T_1365 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[217], _out_T_1333 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[218], _out_T_1559 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[219], _out_T_1493 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[220], _out_T_1399 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[221], _out_T_1381 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[222], _out_T_1621 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[223], _out_T_1519 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[224], _out_T_1419 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[225], _out_T_1429 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[226], _out_T_1523 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[227], _out_T_1627 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[228], _out_T_1361 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[229], _out_T_1413 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[230], _out_T_1495 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[231], _out_T_1565 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[232], _out_T_1623 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[233], _out_T_1393 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[234], _out_T_1329 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[235], _out_T_1581 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[236], _out_T_1483 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[237], _out_T_1453 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[238], _out_T_1373 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[239], _out_T_1605 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[240], _out_T_1513 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[241], _out_T_1525 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[242], _out_T_1607 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[243], _out_T_1387 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[244], _out_T_1457 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[245], _out_T_1497 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[246], _out_T_1583 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[247], _out_T_1335 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[248], _out_T_1395 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[249], _out_T_1327 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[250], _out_T_1563 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[251], _out_T_1515 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[252], _out_T_1415 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[253], _out_T_1377 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[254], _out_T_1625 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[255], _out_T_1531 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node _out_out_bits_data_T_58 = mux(_out_out_bits_data_T_57, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex_1]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_out_bits_data_T_59 = geq(out_oindex_1, UInt<9>(0h100)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_out_bits_data_WIRE_1 : UInt<64>[256] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[0], _out_T_5734 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[1], _out_T_2491 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[2], _out_T_10262 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[3], _out_T_7100 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[4], _out_T_4467 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[5], _out_T_3083 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[6], _out_T_11270 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[7], _out_T_9382 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[8], _out_T_6596 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[9], _out_T_4035 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[10], _out_T_5986 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[11], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[12], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[13], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[14], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[15], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[16], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[17], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[18], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[19], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[20], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[21], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[22], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[23], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[24], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[25], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[26], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[27], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[28], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[29], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[30], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[31], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[32], _out_T_6452 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[33], _out_T_4773 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[34], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[35], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[36], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[37], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[38], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[39], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[40], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[41], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[42], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[43], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[44], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[45], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[46], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[47], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[48], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[49], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[50], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[51], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[52], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[53], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[54], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[55], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[56], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[57], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[58], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[59], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[60], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[61], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[62], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[63], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[64], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[65], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[66], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[67], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[68], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[69], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[70], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[71], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[72], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[73], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[74], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[75], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[76], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[77], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[78], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[79], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[80], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[81], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[82], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[83], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[84], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[85], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[86], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[87], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[88], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[89], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[90], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[91], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[92], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[93], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[94], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[95], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[96], _out_T_5574 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[97], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[98], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[99], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[100], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[101], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[102], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[103], _out_T_7838 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[104], _out_T_10046 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[105], _out_T_6290 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[106], _out_T_3387 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[107], _out_T_11430 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[108], _out_T_8214 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[109], _out_T_5662 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[110], _out_T_2651 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[111], _out_T_12094 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[112], _out_T_9094 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[113], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[114], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[115], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[116], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[117], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[118], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[119], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[120], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[121], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[122], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[123], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[124], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[125], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[126], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[127], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[128], _out_T_6130 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[129], _out_T_5878 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[130], _out_T_8430 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[131], _out_T_11790 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[132], _out_T_3819 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[133], _out_T_3891 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[134], _out_T_5950 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[135], _out_T_8574 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[136], _out_T_11502 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[137], _out_T_4683 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[138], _out_T_1699 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[139], _out_T_10550 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[140], _out_T_7910 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[141], _out_T_5349 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[142], _out_T_2203 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[143], _out_T_9814 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[144], _out_T_7172 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[145], _out_T_9238 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[146], _out_T_10982 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[147], _out_T_3675 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[148], _out_T_6524 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[149], _out_T_6812 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[150], _out_T_9310 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[151], _out_T_10910 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[152], _out_T_2939 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[153], _out_T_2275 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[154], _out_T_9670 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[155], _out_T_8054 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[156], _out_T_5133 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[157], _out_T_2795 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[158], _out_T_10334 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[159], _out_T_7388 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[160], _out_T_4539 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[161], _out_T_6668 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[162], _out_T_8862 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[163], _out_T_11934 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[164], _out_T_3227 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[165], _out_T_4755 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[166], _out_T_6434 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[167], _out_T_8790 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[168], _out_T_11198 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[169], _out_T_5277 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[170], _out_T_1915 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[171], _out_T_10478 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[172], _out_T_7532 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[173], _out_T_5806 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[174], _out_T_2347 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[175], _out_T_9742 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[176], _out_T_6884 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[177], _out_T_9526 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[178], _out_T_11862 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[179], _out_T_3299 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[180], _out_T_6740 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[181], _out_T_7316 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[182], _out_T_9598 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[183], _out_T_11126 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[184], _out_T_2563 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[185], _out_T_2419 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[186], _out_T_10406 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[187], _out_T_7460 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[188], _out_T_5205 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[189], _out_T_2867 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[190], _out_T_11054 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[191], _out_T_6956 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[192], _out_T_4611 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[193], _out_T_5493 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[194], _out_T_9166 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[195], _out_T_11574 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[196], _out_T_2723 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[197], _out_T_4989 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[198], _out_T_8126 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[199], _out_T_9454 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[200], _out_T_12006 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[201], _out_T_4323 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[202], _out_T_2131 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[203], _out_T_9886 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[204], _out_T_7028 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[205], _out_T_6058 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[206], _out_T_4107 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[207], _out_T_10622 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[208], _out_T_7820 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[209], _out_T_9006 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[210], _out_T_11342 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[211], _out_T_3531 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[212], _out_T_5565 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[213], _out_T_7982 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[214], _out_T_10694 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[215], _out_T_12166 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[216], _out_T_3155 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[217], _out_T_1987 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[218], _out_T_9958 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[219], _out_T_7604 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[220], _out_T_4395 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[221], _out_T_3747 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[222], _out_T_12238 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[223], _out_T_8502 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[224], _out_T_5061 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[225], _out_T_5421 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[226], _out_T_8646 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[227], _out_T_12454 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[228], _out_T_3011 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[229], _out_T_4845 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[230], _out_T_7676 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[231], _out_T_10190 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[232], _out_T_12310 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[233], _out_T_4179 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[234], _out_T_1843 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[235], _out_T_10766 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[236], _out_T_7244 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[237], _out_T_6202 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[238], _out_T_3459 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[239], _out_T_11646 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[240], _out_T_8286 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[241], _out_T_8718 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[242], _out_T_11718 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[243], _out_T_3963 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[244], _out_T_6362 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[245], _out_T_7748 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[246], _out_T_10838 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[247], _out_T_2059 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[248], _out_T_4251 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[249], _out_T_1771 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[250], _out_T_10118 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[251], _out_T_8358 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[252], _out_T_4917 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[253], _out_T_3603 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[254], _out_T_12382 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[255], _out_T_8934 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node _out_out_bits_data_T_60 = mux(_out_out_bits_data_T_59, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex_1]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_out_bits_data_T_61 = mux(_out_out_bits_data_T_58, _out_out_bits_data_T_60, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_1.bits.data, _out_out_bits_data_T_61 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_1.bits.extra, out_front_1.bits.extra @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect in_1.valid, tlNodeIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 90:15] connect tlNodeIn.a.ready, in_1.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 91:15] connect tlNodeIn.d.valid, out_1.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 92:15] connect out_1.ready, tlNodeIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 93:15] wire tlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 792:17] connect tlNodeIn_d_bits_d.opcode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 793:15] connect tlNodeIn_d_bits_d.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 794:15] connect tlNodeIn_d_bits_d.size, out_1.bits.extra.tlrr_extra.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 795:15] connect tlNodeIn_d_bits_d.source, out_1.bits.extra.tlrr_extra.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 796:15] connect tlNodeIn_d_bits_d.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 797:15] connect tlNodeIn_d_bits_d.denied, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 798:15] invalidate tlNodeIn_d_bits_d.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 801:15] connect tlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 802:15] connect tlNodeIn.d.bits.corrupt, tlNodeIn_d_bits_d.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect tlNodeIn.d.bits.data, tlNodeIn_d_bits_d.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect tlNodeIn.d.bits.denied, tlNodeIn_d_bits_d.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect tlNodeIn.d.bits.sink, tlNodeIn_d_bits_d.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect tlNodeIn.d.bits.source, tlNodeIn_d_bits_d.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect tlNodeIn.d.bits.size, tlNodeIn_d_bits_d.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect tlNodeIn.d.bits.param, tlNodeIn_d_bits_d.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect tlNodeIn.d.bits.opcode, tlNodeIn_d_bits_d.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect tlNodeIn.d.bits.data, out_1.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 100:17] node _tlNodeIn_d_bits_opcode_T = mux(out_1.bits.read, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 105:25] connect tlNodeIn.d.bits.opcode, _tlNodeIn_d_bits_opcode_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 105:19] wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.address, UInt<12>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE_6.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.bits, _WIRE_6.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, _WIRE_6.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.ready, _WIRE_6.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_7.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 108:22] wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.address, UInt<12>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_8.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.bits, _WIRE_8.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.valid, _WIRE_8.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, _WIRE_8.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_9.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 109:22] wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_10.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.bits, _WIRE_10.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.valid, _WIRE_10.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, _WIRE_10.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_11.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 110:22] node _T_1466 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1711:11] when _T_1466 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1711:24] connect abstractDataMem[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1712:40] connect abstractDataMem[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1712:40] connect abstractDataMem[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1712:40] connect abstractDataMem[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1712:40] connect abstractDataMem[4], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1712:40] connect abstractDataMem[5], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1712:40] connect abstractDataMem[6], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1712:40] connect abstractDataMem[7], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1712:40] connect programBufferMem[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[1], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[2], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[3], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[4], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[5], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[6], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[7], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[8], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[9], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[10], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[11], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[12], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[13], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[14], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[15], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[16], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[17], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[18], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[19], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[20], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[21], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[22], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[23], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[24], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[25], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[26], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[27], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[28], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[29], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[30], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[31], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[32], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[33], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[34], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[35], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[36], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[37], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[38], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[39], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[40], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[41], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[42], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[43], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[44], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[45], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[46], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[47], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[48], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[49], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[50], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[51], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[52], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[53], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[54], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[55], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[56], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[57], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[58], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[59], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[60], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[61], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[62], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] connect programBufferMem[63], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1713:40] reg ctrlStateReg : UInt<2>, clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1731:27] node _hartHalted_T = dshr(haltedBitRegs, UInt<0>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1733:37] node hartHalted = bits(_hartHalted_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1733:37] wire ctrlStateNxt : UInt @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1734:32] connect ctrlStateNxt, ctrlStateReg @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1734:32] node _abstractCommandBusy_T = neq(ctrlStateReg, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1739:42] connect abstractCommandBusy, _abstractCommandBusy_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1739:25] node _ABSTRACTCSWrEnLegal_T = eq(ctrlStateReg, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1741:44] connect ABSTRACTCSWrEnLegal, _ABSTRACTCSWrEnLegal_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1741:27] node _COMMANDWrEnLegal_T = eq(ctrlStateReg, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1742:44] connect COMMANDWrEnLegal, _COMMANDWrEnLegal_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1742:27] node _ABSTRACTAUTOWrEnLegal_T = eq(ctrlStateReg, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1743:44] connect ABSTRACTAUTOWrEnLegal, _ABSTRACTAUTOWrEnLegal_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1743:27] node _dmiAbstractDataAccessLegal_T = eq(ctrlStateReg, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1744:50] connect dmiAbstractDataAccessLegal, _dmiAbstractDataAccessLegal_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1744:33] node _dmiProgramBufferAccessLegal_T = eq(ctrlStateReg, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1745:50] connect dmiProgramBufferAccessLegal, _dmiProgramBufferAccessLegal_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1745:33] node _errorBusy_T = not(ABSTRACTCSWrEnLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1747:45] node _errorBusy_T_1 = and(ABSTRACTCSWrEnMaybe, _errorBusy_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1747:42] node _errorBusy_T_2 = not(ABSTRACTAUTOWrEnLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1748:45] node _errorBusy_T_3 = and(autoexecdataWrEnMaybe, _errorBusy_T_2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1748:42] node _errorBusy_T_4 = or(_errorBusy_T_1, _errorBusy_T_3) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1747:74] node _errorBusy_T_5 = not(ABSTRACTAUTOWrEnLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1749:47] node _errorBusy_T_6 = and(autoexecprogbufWrEnMaybe, _errorBusy_T_5) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1749:44] node _errorBusy_T_7 = or(_errorBusy_T_4, _errorBusy_T_6) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1748:74] node _errorBusy_T_8 = not(COMMANDWrEnLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1750:45] node _errorBusy_T_9 = and(COMMANDWrEnMaybe, _errorBusy_T_8) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1750:42] node _errorBusy_T_10 = or(_errorBusy_T_7, _errorBusy_T_9) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1749:74] node _errorBusy_T_11 = not(dmiAbstractDataAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1751:45] node _errorBusy_T_12 = and(dmiAbstractDataAccess, _errorBusy_T_11) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1751:42] node _errorBusy_T_13 = or(_errorBusy_T_10, _errorBusy_T_12) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1750:74] node _errorBusy_T_14 = not(dmiProgramBufferAccessLegal) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1752:45] node _errorBusy_T_15 = and(dmiProgramBufferAccess, _errorBusy_T_14) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1752:42] node _errorBusy_T_16 = or(_errorBusy_T_13, _errorBusy_T_15) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1751:74] connect errorBusy, _errorBusy_T_16 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1747:15] node commandWrIsAccessRegister = eq(COMMANDWrData.cmdtype, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1755:60] node commandRegIsAccessRegister = eq(COMMANDReg.cmdtype, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1756:58] node _commandWrIsUnsupported_T = eq(commandWrIsAccessRegister, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1758:49] node commandWrIsUnsupported = and(COMMANDWrEn, _commandWrIsUnsupported_T) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1758:46] wire commandRegIsUnsupported : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1760:43] connect commandRegIsUnsupported, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1760:43] wire commandRegBadHaltResume : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1761:43] connect commandRegBadHaltResume, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1761:43] node _accessRegIsLegalSize_T = eq(accessRegisterCommandReg.size, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1764:63] node _accessRegIsLegalSize_T_1 = eq(accessRegisterCommandReg.size, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1764:106] node accessRegIsLegalSize = or(_accessRegIsLegalSize_T, _accessRegIsLegalSize_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1764:72] node _accessRegIsGPR_T = geq(accessRegisterCommandReg.regno, UInt<13>(0h1000)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1765:58] node _accessRegIsGPR_T_1 = leq(accessRegisterCommandReg.regno, UInt<13>(0h101f)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1765:104] node _accessRegIsGPR_T_2 = and(_accessRegIsGPR_T, _accessRegIsGPR_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1765:70] node accessRegIsGPR = and(_accessRegIsGPR_T_2, accessRegIsLegalSize) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1765:117] when commandRegIsAccessRegister : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1772:39] node _T_1467 = and(UInt<1>(0h0), accessRegisterCommandReg.transfer) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1773:31] node _T_1468 = eq(accessRegisterCommandReg.write, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1773:102] node _T_1469 = and(_T_1467, _T_1468) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1773:68] when _T_1469 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1773:115] connect commandRegIsUnsupported, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1774:33] else : node _T_1470 = eq(accessRegisterCommandReg.transfer, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1775:19] node _T_1471 = or(_T_1470, accessRegIsGPR) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1775:54] when _T_1471 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1775:73] connect commandRegIsUnsupported, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1776:33] node _commandRegBadHaltResume_T = not(hartHalted) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1777:36] connect commandRegBadHaltResume, _commandRegBadHaltResume_T @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1777:33] node _wrAccessRegisterCommand_T = and(COMMANDWrEn, commandWrIsAccessRegister) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1781:48] node _wrAccessRegisterCommand_T_1 = eq(ABSTRACTCSReg.cmderr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1781:103] node wrAccessRegisterCommand = and(_wrAccessRegisterCommand_T, _wrAccessRegisterCommand_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1781:78] node _regAccessRegisterCommand_T = and(autoexec, commandRegIsAccessRegister) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1782:48] node _regAccessRegisterCommand_T_1 = eq(ABSTRACTCSReg.cmderr, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1782:103] node regAccessRegisterCommand = and(_regAccessRegisterCommand_T, _regAccessRegisterCommand_T_1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1782:78] node _T_1472 = eq(ctrlStateReg, UInt<2>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1788:24] when _T_1472 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1788:47] node _T_1473 = or(wrAccessRegisterCommand, regAccessRegisterCommand) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1789:37] when _T_1473 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1789:66] connect ctrlStateNxt, UInt<2>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1790:22] else : when commandWrIsUnsupported : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1791:43] connect errorUnsupported, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1792:26] else : node _T_1474 = and(autoexec, commandRegIsUnsupported) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1793:28] when _T_1474 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1793:56] connect errorUnsupported, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1794:26] else : node _T_1475 = eq(ctrlStateReg, UInt<2>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1796:30] when _T_1475 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1796:59] when commandRegIsUnsupported : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1803:38] connect errorUnsupported, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1804:26] connect ctrlStateNxt, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1805:22] else : when commandRegBadHaltResume : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1806:43] connect errorHaltResume, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1807:25] connect ctrlStateNxt, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1808:22] else : when UInt<1>(0h0) : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1810:33] connect ctrlStateNxt, UInt<2>(0h3) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1811:24] else : connect ctrlStateNxt, UInt<2>(0h2) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1813:24] connect goAbstract, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1814:22] else : node _T_1476 = eq(ctrlStateReg, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1817:30] when _T_1476 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1817:51] node _T_1477 = eq(goReg, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1822:18] node _T_1478 = and(_T_1477, hartHaltedWrEn) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1822:30] node _T_1479 = eq(UInt<1>(0h0), selectedHartReg) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1822:95] node _T_1480 = and(_T_1478, _T_1479) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1822:48] when _T_1480 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1822:116] connect ctrlStateNxt, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1823:22] when hartExceptionWrEn : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1825:31] node _T_1481 = eq(hartExceptionId, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1826:32] node _T_1482 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1826:15] node _T_1483 = eq(_T_1482, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1826:15] when _T_1483 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1826:15] node _T_1484 = eq(_T_1481, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1826:15] when _T_1484 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1826:15] printf(clock, UInt<1>(0h1), "Assertion failed: Unexpected 'EXCEPTION' hart\n at Debug.scala:1826 assert(hartExceptionId === 0.U, \"Unexpected 'EXCEPTION' hart\")//Chisel3 #540, %%%%x, expected %%%%x\", hartExceptionId, 0.U)\n") : printf_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1826:15] assert(clock, _T_1481, UInt<1>(0h1), "") : assert_2 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1826:15] connect ctrlStateNxt, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1827:24] connect errorException, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1828:24] else : node _T_1485 = eq(ctrlStateReg, UInt<2>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1830:30] when _T_1485 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1830:53] node _T_1486 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1831:13] node _T_1487 = eq(_T_1486, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1831:13] when _T_1487 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1831:13] node _T_1488 = eq(UInt<1>(0h0), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1831:13] when _T_1488 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1831:13] printf(clock, UInt<1>(0h1), "Assertion failed: Should not be in custom state unless we need it.\n at Debug.scala:1831 assert(needCustom.B, \"Should not be in custom state unless we need it.\")\n") : printf_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1831:13] assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_3 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1831:13] connect goCustom, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1832:16] node _T_1489 = and(customNodeIn.ready, customNodeIn.valid) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1834:26] when _T_1489 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1834:43] connect ctrlStateNxt, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1835:22] node _T_1490 = not(io.dmactive) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1839:11] node _T_1491 = not(UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1839:27] node _T_1492 = or(_T_1490, _T_1491) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1839:24] when _T_1492 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1839:45] connect ctrlStateReg, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1840:20] else : connect ctrlStateReg, ctrlStateNxt @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1842:20] node _T_1493 = eq(io.dmactive, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1844:14] node _T_1494 = eq(hartExceptionWrEn, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1844:30] node _T_1495 = or(_T_1493, _T_1494) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1844:27] node _T_1496 = eq(ctrlStateReg, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1844:65] node _T_1497 = or(_T_1495, _T_1496) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1844:49] node _T_1498 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1844:12] node _T_1499 = eq(_T_1498, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1844:12] when _T_1499 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1844:12] node _T_1500 = eq(_T_1497, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1844:12] when _T_1500 : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1844:12] printf(clock, UInt<1>(0h1), "Assertion failed: Unexpected EXCEPTION write: should only get it in Debug Module EXEC state\n at Debug.scala:1844 assert ((!io.dmactive || !hartExceptionWrEn || ctrlStateReg === CtrlState(Exec)),\n") : printf_4 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1844:12] assert(clock, _T_1497, UInt<1>(0h1), "") : assert_4 @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1844:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_17 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_17 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_17 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module ClockCrossingReg_w55 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 191:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 191:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 191:7] output io : { flip d : UInt<55>, q : UInt<55>, flip en : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 195:14] reg cdc_reg : UInt<55>, clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 201:76] when io.en : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 201:76] connect cdc_reg, io.d @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 201:76] connect io.q, cdc_reg @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 202:8] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_18 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_18 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_18 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_12 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_18 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_sink_valid_0.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_19 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_19 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_19 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_13 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_19 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_sink_valid_1.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_20 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_20 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_20 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_14 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_20 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_source_extend.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_21 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_21 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_21 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_15 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_21 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_source_valid.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncQueueSink_TLBundleA_a9d32s1k1z2u : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 136:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 136:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 136:7] output io : { deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip async : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 139:14] wire source_ready : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 147:30] connect source_ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 147:30] node _ridx_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 148:30] node _ridx_T_1 = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _ridx_T_2 = eq(source_ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 148:77] wire ridx_incremented : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 51:27] regreset ridx_ridx_bin : UInt, clock, _ridx_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 52:25] connect ridx_ridx_bin, ridx_incremented @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 52:25] node _ridx_incremented_T = add(ridx_ridx_bin, _ridx_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:43] node _ridx_incremented_T_1 = tail(_ridx_incremented_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:43] node _ridx_incremented_T_2 = mux(_ridx_T_2, UInt<1>(0h0), _ridx_incremented_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:23] connect ridx_incremented, _ridx_incremented_T_2 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:17] node _ridx_T_3 = shr(ridx_incremented, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 54:32] node ridx = xor(ridx_incremented, _ridx_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 54:17] inst widx_widx_gray of AsyncResetSynchronizerShiftReg_w1_d3_i0_17 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect widx_widx_gray.clock, clock connect widx_widx_gray.reset, reset connect widx_widx_gray.io.d, io.async.widx @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire widx : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect widx, widx_widx_gray.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] node _valid_T = neq(ridx, widx) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 150:36] node valid = and(source_ready, _valid_T) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 150:28] inst io_deq_bits_deq_bits_reg of ClockCrossingReg_w55 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 207:25] connect io_deq_bits_deq_bits_reg.clock, clock connect io_deq_bits_deq_bits_reg.reset, reset node io_deq_bits_deq_bits_reg_io_d_lo_lo = cat(io.async.mem[0].data, io.async.mem[0].corrupt) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node io_deq_bits_deq_bits_reg_io_d_lo_hi_hi = cat(UInt<0>(0h0), UInt<0>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node io_deq_bits_deq_bits_reg_io_d_lo_hi = cat(io_deq_bits_deq_bits_reg_io_d_lo_hi_hi, io.async.mem[0].mask) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node io_deq_bits_deq_bits_reg_io_d_lo = cat(io_deq_bits_deq_bits_reg_io_d_lo_hi, io_deq_bits_deq_bits_reg_io_d_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node io_deq_bits_deq_bits_reg_io_d_hi_lo = cat(io.async.mem[0].source, io.async.mem[0].address) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node io_deq_bits_deq_bits_reg_io_d_hi_hi_hi = cat(io.async.mem[0].opcode, io.async.mem[0].param) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node io_deq_bits_deq_bits_reg_io_d_hi_hi = cat(io_deq_bits_deq_bits_reg_io_d_hi_hi_hi, io.async.mem[0].size) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node io_deq_bits_deq_bits_reg_io_d_hi = cat(io_deq_bits_deq_bits_reg_io_d_hi_hi, io_deq_bits_deq_bits_reg_io_d_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node _io_deq_bits_deq_bits_reg_io_d_T = cat(io_deq_bits_deq_bits_reg_io_d_hi, io_deq_bits_deq_bits_reg_io_d_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] connect io_deq_bits_deq_bits_reg.io.d, _io_deq_bits_deq_bits_reg_io_d_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:18] connect io_deq_bits_deq_bits_reg.io.en, valid @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 210:19] wire _io_deq_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] wire _io_deq_bits_WIRE_1 : UInt<55> @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE_1, io_deq_bits_deq_bits_reg.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T = bits(_io_deq_bits_WIRE_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.corrupt, _io_deq_bits_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_1 = bits(_io_deq_bits_WIRE_1, 32, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.data, _io_deq_bits_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_2 = bits(_io_deq_bits_WIRE_1, 36, 33) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.mask, _io_deq_bits_T_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_3 = bits(_io_deq_bits_WIRE_1, 45, 37) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.address, _io_deq_bits_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_4 = bits(_io_deq_bits_WIRE_1, 46, 46) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.source, _io_deq_bits_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_5 = bits(_io_deq_bits_WIRE_1, 48, 47) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.size, _io_deq_bits_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_6 = bits(_io_deq_bits_WIRE_1, 51, 49) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.param, _io_deq_bits_T_6 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_7 = bits(_io_deq_bits_WIRE_1, 54, 52) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.opcode, _io_deq_bits_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect io.deq.bits, _io_deq_bits_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 163:15] node _valid_reg_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 165:35] regreset valid_reg : UInt<1>, clock, _valid_reg_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 165:56] connect valid_reg, valid @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 165:56] node _io_deq_valid_T = and(valid_reg, source_ready) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 166:29] connect io.deq.valid, _io_deq_valid_T @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 166:16] node _ridx_reg_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 168:34] regreset ridx_gray : UInt, clock, _ridx_reg_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 168:55] connect ridx_gray, ridx @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 168:55] connect io.async.ridx, ridx_gray @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 169:17] inst sink_valid_0 of AsyncValidSync_12 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 172:33] inst sink_valid_1 of AsyncValidSync_13 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 173:33] inst source_extend of AsyncValidSync_14 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 175:31] inst source_valid of AsyncValidSync_15 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 176:31] node _sink_valid_0_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 177:35] node _sink_valid_0_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 177:45] node _sink_valid_0_reset_T_2 = or(_sink_valid_0_reset_T, _sink_valid_0_reset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 177:42] node _sink_valid_0_reset_T_3 = asAsyncReset(_sink_valid_0_reset_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 177:66] connect sink_valid_0.reset, _sink_valid_0_reset_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 177:25] node _sink_valid_1_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 178:35] node _sink_valid_1_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 178:45] node _sink_valid_1_reset_T_2 = or(_sink_valid_1_reset_T, _sink_valid_1_reset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 178:42] node _sink_valid_1_reset_T_3 = asAsyncReset(_sink_valid_1_reset_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 178:66] connect sink_valid_1.reset, _sink_valid_1_reset_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 178:25] node _source_extend_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 179:35] node _source_extend_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 179:45] node _source_extend_reset_T_2 = or(_source_extend_reset_T, _source_extend_reset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 179:42] node _source_extend_reset_T_3 = asAsyncReset(_source_extend_reset_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 179:66] connect source_extend.reset, _source_extend_reset_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 179:25] node _source_valid_reset_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 180:34] connect source_valid.reset, _source_valid_reset_T @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 180:25] connect sink_valid_0.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 182:25] connect sink_valid_1.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 183:25] connect source_extend.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 184:25] connect source_valid.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 185:25] connect sink_valid_0.io.in, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 187:24] connect sink_valid_1.io.in, sink_valid_0.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 188:24] connect io.async.safe.ridx_valid, sink_valid_1.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 189:20] connect source_extend.io.in, io.async.safe.widx_valid @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 190:25] connect source_valid.io.in, source_extend.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 191:24] connect source_ready, source_valid.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 192:18] node _io_async_safe_sink_reset_n_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 193:32] node _io_async_safe_sink_reset_n_T_1 = eq(_io_async_safe_sink_reset_n_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 193:25] connect io.async.safe.sink_reset_n, _io_async_safe_sink_reset_n_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 193:22] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_22 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_22 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_22 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_23 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_23 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_23 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_16 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_23 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_source_valid_0.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_24 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_24 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_24 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_17 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_24 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_source_valid_1.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_25 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_25 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_25 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_18 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_25 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_sink_extend.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_26 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_26 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_26 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_19 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_26 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_sink_valid.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncQueueSource_TLBundleD_a9d32s1k1z2u : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 70:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 70:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 70:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}, async : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 73:14] wire sink_ready : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 81:28] connect sink_ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 81:28] reg mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 82:16] node _widx_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 83:30] node _widx_T_1 = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _widx_T_2 = eq(sink_ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 83:77] wire widx_incremented : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 51:27] regreset widx_widx_bin : UInt, clock, _widx_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 52:25] connect widx_widx_bin, widx_incremented @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 52:25] node _widx_incremented_T = add(widx_widx_bin, _widx_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:43] node _widx_incremented_T_1 = tail(_widx_incremented_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:43] node _widx_incremented_T_2 = mux(_widx_T_2, UInt<1>(0h0), _widx_incremented_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:23] connect widx_incremented, _widx_incremented_T_2 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:17] node _widx_T_3 = shr(widx_incremented, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 54:32] node widx = xor(widx_incremented, _widx_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 54:17] inst ridx_ridx_gray of AsyncResetSynchronizerShiftReg_w1_d3_i0_22 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect ridx_ridx_gray.clock, clock connect ridx_ridx_gray.reset, reset connect ridx_ridx_gray.io.d, io.async.ridx @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire ridx : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect ridx, ridx_ridx_gray.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] node _ready_T = xor(ridx, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 85:44] node _ready_T_1 = neq(widx, _ready_T) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 85:34] node ready = and(sink_ready, _ready_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 85:26] node _T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 88:22] connect mem[0], io.enq.bits @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 88:35] node _ready_reg_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 90:35] regreset ready_reg : UInt<1>, clock, _ready_reg_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 90:56] connect ready_reg, ready @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 90:56] node _io_enq_ready_T = and(ready_reg, sink_ready) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 91:29] connect io.enq.ready, _io_enq_ready_T @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 91:16] node _widx_reg_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 93:34] regreset widx_gray : UInt, clock, _widx_reg_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 93:55] connect widx_gray, widx @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 93:55] connect io.async.widx, widx_gray @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 94:17] connect io.async.mem, mem @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 98:31] inst source_valid_0 of AsyncValidSync_16 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 102:32] inst source_valid_1 of AsyncValidSync_17 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 103:32] inst sink_extend of AsyncValidSync_18 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 105:30] inst sink_valid of AsyncValidSync_19 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 106:30] node _source_valid_0_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 107:36] node _source_valid_0_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 107:46] node _source_valid_0_reset_T_2 = or(_source_valid_0_reset_T, _source_valid_0_reset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 107:43] node _source_valid_0_reset_T_3 = asAsyncReset(_source_valid_0_reset_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 107:65] connect source_valid_0.reset, _source_valid_0_reset_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 107:26] node _source_valid_1_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 108:36] node _source_valid_1_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 108:46] node _source_valid_1_reset_T_2 = or(_source_valid_1_reset_T, _source_valid_1_reset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 108:43] node _source_valid_1_reset_T_3 = asAsyncReset(_source_valid_1_reset_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 108:65] connect source_valid_1.reset, _source_valid_1_reset_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 108:26] node _sink_extend_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 109:36] node _sink_extend_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 109:46] node _sink_extend_reset_T_2 = or(_sink_extend_reset_T, _sink_extend_reset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 109:43] node _sink_extend_reset_T_3 = asAsyncReset(_sink_extend_reset_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 109:65] connect sink_extend.reset, _sink_extend_reset_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 109:26] node _sink_valid_reset_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 110:35] connect sink_valid.reset, _sink_valid_reset_T @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 110:26] connect source_valid_0.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 112:26] connect source_valid_1.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 113:26] connect sink_extend.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 114:26] connect sink_valid.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 115:26] connect source_valid_0.io.in, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 117:26] connect source_valid_1.io.in, source_valid_0.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 118:26] connect io.async.safe.widx_valid, source_valid_1.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 119:20] connect sink_extend.io.in, io.async.safe.ridx_valid @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 120:23] connect sink_valid.io.in, sink_extend.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 121:22] connect sink_ready, sink_valid.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 122:16] node _io_async_safe_source_reset_n_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 123:34] node _io_async_safe_source_reset_n_T_1 = eq(_io_async_safe_source_reset_n_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 123:27] connect io.async.safe.source_reset_n, _io_async_safe_source_reset_n_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 123:24] module TLAsyncCrossingSink_a9d32s1k1z2u : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 59:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 59:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 59:9] output auto : { flip in : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.e.safe.sink_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.e.safe.source_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.e.safe.widx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.e.safe.ridx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.e.widx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.e.ridx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.e.mem[0].sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.safe.sink_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.safe.source_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.safe.widx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.safe.ridx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.widx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ridx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.mem[0].corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.mem[0].data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.mem[0].denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.mem[0].sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.mem[0].source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.mem[0].size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.mem[0].param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.mem[0].opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.c.safe.sink_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.c.safe.source_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.c.safe.widx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.c.safe.ridx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.c.widx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.c.ridx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.c.mem[0].corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.c.mem[0].data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.c.mem[0].address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.c.mem[0].source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.c.mem[0].size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.c.mem[0].param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.c.mem[0].opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.b.safe.sink_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.b.safe.source_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.b.safe.widx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.b.safe.ridx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.b.widx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.b.ridx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.b.mem[0].corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.b.mem[0].data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.b.mem[0].mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.b.mem[0].address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.b.mem[0].source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.b.mem[0].size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.b.mem[0].param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.b.mem[0].opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.safe.sink_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.safe.source_reset_n @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.safe.widx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.safe.ridx_valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.widx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ridx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.mem[0].corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.mem[0].data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.mem[0].mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.mem[0].address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.mem[0].source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.mem[0].size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.mem[0].param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.mem[0].opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] inst nodeOut_a_sink of AsyncQueueSink_TLBundleA_a9d32s1k1z2u @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 211:22] connect nodeOut_a_sink.clock, clock connect nodeOut_a_sink.reset, reset connect nodeOut_a_sink.io.async, nodeIn.a @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 212:19] connect nodeOut.a.bits, nodeOut_a_sink.io.deq.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 64:13] connect nodeOut.a.valid, nodeOut_a_sink.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 64:13] connect nodeOut_a_sink.io.deq.ready, nodeOut.a.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 64:13] inst nodeIn_d_source of AsyncQueueSource_TLBundleD_a9d32s1k1z2u @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 220:24] connect nodeIn_d_source.clock, clock connect nodeIn_d_source.reset, reset connect nodeIn_d_source.io.enq, nodeOut.d @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 221:19] connect nodeIn_d_source.io.async.safe.sink_reset_n, nodeIn.d.safe.sink_reset_n @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 65:12] connect nodeIn.d.safe.source_reset_n, nodeIn_d_source.io.async.safe.source_reset_n @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 65:12] connect nodeIn.d.safe.widx_valid, nodeIn_d_source.io.async.safe.widx_valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 65:12] connect nodeIn_d_source.io.async.safe.ridx_valid, nodeIn.d.safe.ridx_valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 65:12] connect nodeIn.d.widx, nodeIn_d_source.io.async.widx @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 65:12] connect nodeIn_d_source.io.async.ridx, nodeIn.d.ridx @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 65:12] connect nodeIn.d.mem, nodeIn_d_source.io.async.mem @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 65:12] node _T = and(nodeOut.a.valid, nodeOut.a.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 66:21] node _T_1 = eq(nodeOut.a.ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 66:21] node _T_2 = and(nodeOut.a.valid, _T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 66:21] node _T_3 = eq(nodeOut.a.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 66:21] node _T_4 = and(_T_3, nodeOut.a.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 66:21] node _T_5 = eq(nodeOut.a.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 66:21] node _T_6 = eq(nodeOut.a.ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 66:21] node _T_7 = and(_T_5, _T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 66:21] node _T_8 = and(nodeOut.d.valid, nodeOut.d.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 67:21] node _T_9 = eq(nodeOut.d.ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 67:21] node _T_10 = and(nodeOut.d.valid, _T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 67:21] node _T_11 = eq(nodeOut.d.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 67:21] node _T_12 = and(_T_11, nodeOut.d.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 67:21] node _T_13 = eq(nodeOut.d.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 67:21] node _T_14 = eq(nodeOut.d.ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 67:21] node _T_15 = and(_T_13, _T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 67:21] connect nodeIn.b.widx, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 77:19] connect nodeIn.c.ridx, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 78:19] connect nodeIn.e.ridx, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 79:19] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 80:21] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<9>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 81:21] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/AsyncCrossing.scala 82:21] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_27 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_27 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_27 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_28 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_28 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_28 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module ClockCrossingReg_w15 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 191:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 191:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 191:7] output io : { flip d : UInt<15>, q : UInt<15>, flip en : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 195:14] reg cdc_reg : UInt<15>, clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 201:76] when io.en : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 201:76] connect cdc_reg, io.d @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 201:76] connect io.q, cdc_reg @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 202:8] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_29 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_29 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_29 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_20 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_29 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_sink_valid_0.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_30 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_30 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_30 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_21 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_30 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_sink_valid_1.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_31 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_31 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_31 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_22 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_31 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_source_extend.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_32 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_32 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_32 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module AsyncValidSync_23 : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 58:7] output io : { flip in : UInt<1>, out : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 59:14] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 63:17] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 64:17] inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_32 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_out_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_out_WIRE, io_out_source_valid.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.out, _io_out_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 66:12] module AsyncQueueSink_DebugInternalBundle : @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 136:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 136:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 136:7] output io : { deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[1], hrmask : UInt<1>[1]}}, flip async : { mem : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[1], hrmask : UInt<1>[1]}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 139:14] wire source_ready : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 147:30] connect source_ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 147:30] node _ridx_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 148:30] node _ridx_T_1 = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] node _ridx_T_2 = eq(source_ready, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 148:77] wire ridx_incremented : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 51:27] regreset ridx_ridx_bin : UInt, clock, _ridx_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 52:25] connect ridx_ridx_bin, ridx_incremented @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 52:25] node _ridx_incremented_T = add(ridx_ridx_bin, _ridx_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:43] node _ridx_incremented_T_1 = tail(_ridx_incremented_T, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:43] node _ridx_incremented_T_2 = mux(_ridx_T_2, UInt<1>(0h0), _ridx_incremented_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:23] connect ridx_incremented, _ridx_incremented_T_2 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 53:17] node _ridx_T_3 = shr(ridx_incremented, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 54:32] node ridx = xor(ridx_incremented, _ridx_T_3) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 54:17] inst widx_widx_gray of AsyncResetSynchronizerShiftReg_w1_d3_i0_28 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect widx_widx_gray.clock, clock connect widx_widx_gray.reset, reset connect widx_widx_gray.io.d, io.async.widx @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire widx : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect widx, widx_widx_gray.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] node _valid_T = neq(ridx, widx) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 150:36] node valid = and(source_ready, _valid_T) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 150:28] inst io_deq_bits_deq_bits_reg of ClockCrossingReg_w15 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 207:25] connect io_deq_bits_deq_bits_reg.clock, clock connect io_deq_bits_deq_bits_reg.reset, reset node io_deq_bits_deq_bits_reg_io_d_lo_hi = cat(io.async.mem[0].hasel, io.async.mem[0].hamask[0]) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node io_deq_bits_deq_bits_reg_io_d_lo = cat(io_deq_bits_deq_bits_reg_io_d_lo_hi, io.async.mem[0].hrmask[0]) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node io_deq_bits_deq_bits_reg_io_d_hi_hi = cat(io.async.mem[0].resumereq, io.async.mem[0].hartsel) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node io_deq_bits_deq_bits_reg_io_d_hi = cat(io_deq_bits_deq_bits_reg_io_d_hi_hi, io.async.mem[0].ackhavereset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] node _io_deq_bits_deq_bits_reg_io_d_T = cat(io_deq_bits_deq_bits_reg_io_d_hi, io_deq_bits_deq_bits_reg_io_d_lo) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:24] connect io_deq_bits_deq_bits_reg.io.d, _io_deq_bits_deq_bits_reg_io_d_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 209:18] connect io_deq_bits_deq_bits_reg.io.en, valid @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 210:19] wire _io_deq_bits_WIRE : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[1], hrmask : UInt<1>[1]} @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] wire _io_deq_bits_WIRE_1 : UInt<15> @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE_1, io_deq_bits_deq_bits_reg.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T = bits(_io_deq_bits_WIRE_1, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.hrmask[0], _io_deq_bits_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_1 = bits(_io_deq_bits_WIRE_1, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.hamask[0], _io_deq_bits_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_2 = bits(_io_deq_bits_WIRE_1, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.hasel, _io_deq_bits_T_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_3 = bits(_io_deq_bits_WIRE_1, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.ackhavereset, _io_deq_bits_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_4 = bits(_io_deq_bits_WIRE_1, 13, 4) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.hartsel, _io_deq_bits_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] node _io_deq_bits_T_5 = bits(_io_deq_bits_WIRE_1, 14, 14) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect _io_deq_bits_WIRE.resumereq, _io_deq_bits_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 211:26] connect io.deq.bits, _io_deq_bits_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 163:15] node _valid_reg_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 165:35] regreset valid_reg : UInt<1>, clock, _valid_reg_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 165:56] connect valid_reg, valid @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 165:56] node _io_deq_valid_T = and(valid_reg, source_ready) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 166:29] connect io.deq.valid, _io_deq_valid_T @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 166:16] node _ridx_reg_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 168:34] regreset ridx_gray : UInt, clock, _ridx_reg_T, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 168:55] connect ridx_gray, ridx @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 168:55] connect io.async.ridx, ridx_gray @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 169:17] inst sink_valid_0 of AsyncValidSync_20 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 172:33] inst sink_valid_1 of AsyncValidSync_21 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 173:33] inst source_extend of AsyncValidSync_22 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 175:31] inst source_valid of AsyncValidSync_23 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 176:31] node _sink_valid_0_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 177:35] node _sink_valid_0_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 177:45] node _sink_valid_0_reset_T_2 = or(_sink_valid_0_reset_T, _sink_valid_0_reset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 177:42] node _sink_valid_0_reset_T_3 = asAsyncReset(_sink_valid_0_reset_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 177:66] connect sink_valid_0.reset, _sink_valid_0_reset_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 177:25] node _sink_valid_1_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 178:35] node _sink_valid_1_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 178:45] node _sink_valid_1_reset_T_2 = or(_sink_valid_1_reset_T, _sink_valid_1_reset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 178:42] node _sink_valid_1_reset_T_3 = asAsyncReset(_sink_valid_1_reset_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 178:66] connect sink_valid_1.reset, _sink_valid_1_reset_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 178:25] node _source_extend_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 179:35] node _source_extend_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 179:45] node _source_extend_reset_T_2 = or(_source_extend_reset_T, _source_extend_reset_T_1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 179:42] node _source_extend_reset_T_3 = asAsyncReset(_source_extend_reset_T_2) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 179:66] connect source_extend.reset, _source_extend_reset_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 179:25] node _source_valid_reset_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 180:34] connect source_valid.reset, _source_valid_reset_T @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 180:25] connect sink_valid_0.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 182:25] connect sink_valid_1.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 183:25] connect source_extend.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 184:25] connect source_valid.clock, clock @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 185:25] connect sink_valid_0.io.in, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 187:24] connect sink_valid_1.io.in, sink_valid_0.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 188:24] connect io.async.safe.ridx_valid, sink_valid_1.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 189:20] connect source_extend.io.in, io.async.safe.widx_valid @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 190:25] connect source_valid.io.in, source_extend.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 191:24] connect source_ready, source_valid.io.out @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 192:18] node _io_async_safe_sink_reset_n_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 193:32] node _io_async_safe_sink_reset_n_T_1 = eq(_io_async_safe_sink_reset_n_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 193:25] connect io.async.safe.sink_reset_n, _io_async_safe_sink_reset_n_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 193:22] module TLDebugModuleInnerAsync : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1870:9] output auto : { flip dmiXing_in : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}, dmInner_sb2tlOpt_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, flip dmInner_custom_in : { flip addr : UInt<1>, data : UInt<0>, ready : UInt<1>, flip valid : UInt<1>}, flip dmInner_tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output io : { flip debug_clock : Clock, flip debug_reset : Reset, flip tl_clock : Clock, flip tl_reset : Reset, flip dmactive : UInt<1>, flip innerCtrl : { mem : { resumereq : UInt<1>, hartsel : UInt<10>, ackhavereset : UInt<1>, hasel : UInt<1>, hamask : UInt<1>[1], hrmask : UInt<1>[1]}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip debugUnavail : UInt<1>[1], hgDebugInt : UInt<1>[1], flip hartIsInReset : UInt<1>[1]} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1876:16] input rf_reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1903:22] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] inst dmInner of TLDebugModuleInner @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1856:27] connect dmInner.clock, childClock connect dmInner.reset, childReset inst dmiXing of TLAsyncCrossingSink_a9d32s1k1z2u @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1857:27] connect dmiXing.clock, childClock connect dmiXing.reset, childReset connect dmInner.auto.dmi_in, dmiXing.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect dmInner.auto.tl_in, auto.dmInner_tl_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect dmInner.auto.custom_in, auto.dmInner_custom_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect dmInner.auto.sb2tlOpt_out.d, auto.dmInner_sb2tlOpt_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.dmInner_sb2tlOpt_out.a.bits, dmInner.auto.sb2tlOpt_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.dmInner_sb2tlOpt_out.a.valid, dmInner.auto.sb2tlOpt_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect dmInner.auto.sb2tlOpt_out.a.ready, auto.dmInner_sb2tlOpt_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect dmiXing.auto.in, auto.dmiXing_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect childClock, io.debug_clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1905:16] connect childReset, io.debug_reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1906:16] inst dmactive_synced_dmactive_synced_dmactiveSync of AsyncResetSynchronizerShiftReg_w1_d3_i0_27 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect dmactive_synced_dmactive_synced_dmactiveSync.clock, childClock connect dmactive_synced_dmactive_synced_dmactiveSync.reset, childReset connect dmactive_synced_dmactive_synced_dmactiveSync.io.d, io.dmactive @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire dmactive_synced : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect dmactive_synced, dmactive_synced_dmactive_synced_dmactiveSync.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect dmInner.clock, io.debug_clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1911:28] connect dmInner.reset, io.debug_reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1912:28] connect dmInner.io.tl_clock, io.tl_clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1913:34] connect dmInner.io.tl_reset, io.tl_reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1914:34] connect dmInner.io.dmactive, dmactive_synced @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1915:34] inst dmactive_synced_dmInner_io_innerCtrl_sink of AsyncQueueSink_DebugInternalBundle @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 211:22] connect dmactive_synced_dmInner_io_innerCtrl_sink.clock, childClock connect dmactive_synced_dmInner_io_innerCtrl_sink.reset, childReset connect dmactive_synced_dmInner_io_innerCtrl_sink.io.async, io.innerCtrl @[hardware/upstream/rocket-chip/src/main/scala/util/AsyncQueue.scala 212:19] connect dmInner.io.innerCtrl, dmactive_synced_dmInner_io_innerCtrl_sink.io.deq @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1916:35] connect dmInner.io.debugUnavail[0], io.debugUnavail[0] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1917:38] connect io.hgDebugInt, dmInner.io.hgDebugInt @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1918:21] connect dmInner.io.hartIsInReset[0], io.hartIsInReset[0] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1920:39] module TLDebugModule : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1958:9] output auto : { dmInner_dmInner_sb2tlOpt_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, flip dmInner_dmInner_custom_in : { flip addr : UInt<1>, data : UInt<0>, ready : UInt<1>, flip valid : UInt<1>}, flip dmInner_dmInner_tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, dmOuter_int_out : { sync : UInt<1>[1]}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output io : { flip debug_clock : Clock, flip debug_reset : Reset, flip tl_clock : Clock, flip tl_reset : Reset, ctrl : { flip debugUnavail : UInt<1>[1], ndreset : UInt<1>, dmactive : UInt<1>, flip dmactiveAck : UInt<1>}, flip dmi : { dmi : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<32>, op : UInt<2>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<32>, resp : UInt<2>}}}, dmiClock : Clock, dmiReset : Reset}, flip hartIsInReset : UInt<1>[1]} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1967:16] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] inst dmOuter of TLDebugModuleOuterAsync @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1948:53] inst dmInner of TLDebugModuleInnerAsync @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1949:53] connect dmInner.auto.dmiXing_in, dmOuter.auto.asource_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect auto.dmOuter_int_out, dmOuter.auto.int_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect dmInner.auto.dmInner_tl_in, auto.dmInner_dmInner_tl_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect dmInner.auto.dmInner_custom_in, auto.dmInner_dmInner_custom_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect dmInner.auto.dmInner_sb2tlOpt_out.d, auto.dmInner_dmInner_sb2tlOpt_out.d @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.dmInner_dmInner_sb2tlOpt_out.a.bits, dmInner.auto.dmInner_sb2tlOpt_out.a.bits @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.dmInner_dmInner_sb2tlOpt_out.a.valid, dmInner.auto.dmInner_sb2tlOpt_out.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect dmInner.auto.dmInner_sb2tlOpt_out.a.ready, auto.dmInner_dmInner_sb2tlOpt_out.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect childClock, io.tl_clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1994:16] connect childReset, io.tl_reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1995:16] connect dmOuter.io.dmi, io.dmi.dmi @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 1999:18] connect dmOuter.io.dmi_reset, io.dmi.dmiReset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 2000:35] connect dmOuter.io.dmi_clock, io.dmi.dmiClock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 2001:35] connect dmOuter.rf_reset, io.dmi.dmiReset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 2002:31] connect dmInner.rf_reset, io.debug_reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 2011:29] connect dmInner.io.debug_clock, io.debug_clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 2012:35] connect dmInner.io.debug_reset, io.debug_reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 2013:35] connect dmInner.io.tl_clock, io.tl_clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 2014:32] connect dmInner.io.tl_reset, io.tl_reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 2015:32] connect dmInner.io.innerCtrl, dmOuter.io.innerCtrl @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 2016:36] connect dmInner.io.dmactive, dmOuter.io.ctrl.dmactive @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 2017:36] connect dmInner.io.debugUnavail[0], io.ctrl.debugUnavail[0] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 2018:36] connect dmOuter.io.hgDebugInt[0], dmInner.io.hgDebugInt[0] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 2019:36] connect dmOuter.io.ctrl.dmactiveAck, io.ctrl.dmactiveAck @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 2021:13] connect io.ctrl.dmactive, dmOuter.io.ctrl.dmactive @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 2021:13] connect io.ctrl.ndreset, dmOuter.io.ctrl.ndreset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 2021:13] connect dmOuter.io.ctrl.debugUnavail[0], io.ctrl.debugUnavail[0] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 2021:13] connect dmInner.io.hartIsInReset[0], io.hartIsInReset[0] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Debug.scala 2023:37] module DebugCustomXbar : @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Custom.scala 73:9] output auto : { out : { flip addr : UInt<1>, data : UInt<0>, ready : UInt<1>, flip valid : UInt<1>}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeOut : { flip addr : UInt<1>, data : UInt<0>, ready : UInt<1>, flip valid : UInt<1>} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.addr @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeOut.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Custom.scala 86:16] connect nodeOut.data, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Custom.scala 87:15] module BundleBridgeNexus_TraceBundle : @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 21:9] output auto : { flip in : { insns : { valid : UInt<1>, iaddr : UInt<34>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<34>}[1], time : UInt<64>}, out : { insns : { valid : UInt<1>, iaddr : UInt<34>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<34>}[1], time : UInt<64>}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeIn : { insns : { valid : UInt<1>, iaddr : UInt<34>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<34>}[1], time : UInt<64>} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.time @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.insns[0].tval @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.insns[0].cause @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.insns[0].interrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.insns[0].exception @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.insns[0].priv @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.insns[0].insn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.insns[0].iaddr @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.insns[0].valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { insns : { valid : UInt<1>, iaddr : UInt<34>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<34>}[1], time : UInt<64>} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.time @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.insns[0].tval @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.insns[0].cause @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.insns[0].interrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.insns[0].exception @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.insns[0].priv @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.insns[0].insn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.insns[0].iaddr @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.insns[0].valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut, nodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 59:67] module BundleBridgeNexus_TraceCoreInterface : @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 21:9] output auto : { flip in : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, ctx : UInt<32>, tval : UInt<32>, cause : UInt<32>, time : UInt<32>}, out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, ctx : UInt<32>, tval : UInt<32>, cause : UInt<32>, time : UInt<32>}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] wire nodeIn : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, ctx : UInt<32>, tval : UInt<32>, cause : UInt<32>, time : UInt<32>} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.time @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.cause @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.tval @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.ctx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.priv @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.group[0].ilastsize @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.group[0].itype @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.group[0].iaddr @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.group[0].iretire @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, ctx : UInt<32>, tval : UInt<32>, cause : UInt<32>, time : UInt<32>} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.time @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.cause @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.tval @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.ctx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.priv @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.group[0].ilastsize @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.group[0].itype @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.group[0].iaddr @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.group[0].iretire @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect nodeOut, nodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeNexus.scala 59:67] module TLROM : @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 46:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 46:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 46:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] wire rom : UInt<64>[256] @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[0], UInt<64>(0he301819300001197) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[1], UInt<64>(0h11373002a0736299) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[2], UInt<64>(0h1528011011b0000) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[3], UInt<64>(0h4d03839300000397) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[4], UInt<64>(0h83b3030003b283) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[5], UInt<64>(0h2b0230062f663) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[6], UInt<64>(0h25e000efbfdd02a1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[7], UInt<64>(0h5a5a02b70b6000ef) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[8], UInt<64>(0h3405107300556533) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[9], UInt<64>(0h105000730ff0000f) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[10], UInt<64>(0hec26f0227179bff5) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[11], UInt<64>(0h89aaf406e44ee84a) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[12], UInt<64>(0h913000009174471) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[13], UInt<64>(0h89d7bb54f15b69) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[14], UInt<64>(0h7c50397ca8bbd) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[15], UInt<64>(0h17e322a000ef3471) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[16], UInt<64>(0h64e2740270a2fe94) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[17], UInt<64>(0h8082614569a26942) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[18], UInt<64>(0h842ae406e0221141) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[19], UInt<64>(0h60a2e50900044503) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[20], UInt<64>(0h405808201416402) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[21], UInt<64>(0h1101b7f51fc000ef) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[22], UInt<64>(0h517842ae822) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[23], UInt<64>(0he42eec0644450513) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[24], UInt<64>(0hf0ef8522fd1ff0ef) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[25], UInt<64>(0h51300000517fcbf) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[26], UInt<64>(0h6522fbfff0ef4465) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[27], UInt<64>(0h517f7bff0ef) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[28], UInt<64>(0hfadff0ef45450513) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[29], UInt<64>(0h715dbff510500073) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[30], UInt<64>(0h4285051300000517) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[31], UInt<64>(0hf95ff0efe0a2e486) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[32], UInt<64>(0h4385051300000517) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[33], UInt<64>(0h1800537f89ff0ef) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[34], UInt<64>(0h517f43ff0ef) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[35], UInt<64>(0hf75ff0ef41c50513) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[36], UInt<64>(0h28c000ef286000ef) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[37], UInt<64>(0h517842a2e2000ef) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[38], UInt<64>(0hf0ef422505130000) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[39], UInt<64>(0hf17ff0ef8522f5bf) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[40], UInt<64>(0h3f05051300000517) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[41], UInt<64>(0h537858af49ff0ef) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[42], UInt<64>(0hef040006130180) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[43], UInt<64>(0h544257b7458230e0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[44], UInt<64>(0h51765278793) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[45], UInt<64>(0hf59f6340450513) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[46], UInt<64>(0hf5976347854592) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[47], UInt<64>(0h863040007934722) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[48], UInt<64>(0h5130000051700f7) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[49], UInt<64>(0h47f2f25ff0ef3f65) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[50], UInt<64>(0hfff7869b000f0737) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[51], UInt<64>(0h51785be00e6e863) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[52], UInt<64>(0hb7d53fa505130000) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[53], UInt<64>(0h9fad0005d76345d2) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[54], UInt<64>(0hf7776380100737) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[55], UInt<64>(0h3f05051300000517) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[56], UInt<64>(0h51300000517b7e9) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[57], UInt<64>(0h4542ec7ff0ef3fe5) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[58], UInt<64>(0h517e83ff0ef) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[59], UInt<64>(0heb5ff0ef3fc50513) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[60], UInt<64>(0h517e71ff0ef4552) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[61], UInt<64>(0hf0ef3fa505130000) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[62], UInt<64>(0he5fff0ef4572ea3f) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[63], UInt<64>(0h3385051300000517) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[64], UInt<64>(0h65834672e91ff0ef) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[65], UInt<64>(0h258000ef45420141) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[66], UInt<64>(0hedb8873745724652) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[67], UInt<64>(0h55fd938102061793) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[68], UInt<64>(0h40c786bb32070713) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[69], UInt<64>(0hc593578204a6e463) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[70], UInt<64>(0h51300000517fff5) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[71], UInt<64>(0h517f4b798e33be5) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[72], UInt<64>(0hf0ef3c2505130000) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[73], UInt<64>(0he07ff0ef4562e4bf) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[74], UInt<64>(0h2e05051300000517) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[75], UInt<64>(0h100fe39ff0ef) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[76], UInt<64>(0h60a6978201816783) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[77], UInt<64>(0h8082616145016406) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[78], UInt<64>(0h46a18db50007c683) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[79], UInt<64>(0h15d81b03f59893) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[80], UInt<64>(0h36fd8df943f8d593) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[81], UInt<64>(0h785f6f500b845b3) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[82], UInt<64>(0hf537000715b7bf51) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[83], UInt<64>(0h5138005859302fa) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[84], UInt<64>(0he0221141a8990805) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[85], UInt<64>(0h1563842a47a9e406) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[86], UInt<64>(0hff1ff0ef453500f5) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[87], UInt<64>(0h431c072110013737) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[88], UInt<64>(0h100137b7dff58b85) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[89], UInt<64>(0h1416402c38060a2) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[90], UInt<64>(0h47dc100137b78082) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[91], UInt<64>(0h37b7c7918b85557d) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[92], UInt<64>(0hff5751343c81001) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[93], UInt<64>(0h721100137378082) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[94], UInt<64>(0h8082dff58b85431c) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[95], UInt<64>(0h15d79bcd0dcd95) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[96], UInt<64>(0h110102b7d7bb9fa9) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[97], UInt<64>(0h843e4709ec06e822) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[98], UInt<64>(0he42e843a00e7f363) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[99], UInt<64>(0h6502fd1ff0efe02a) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[100], UInt<64>(0hcb88100137b765a2) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[101], UInt<64>(0h6442cf8060e2cbcc) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[102], UInt<64>(0h37b7808280826105) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[103], UInt<64>(0h37b780824b881001) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[104], UInt<64>(0h37b780824bc81001) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[105], UInt<64>(0h114180824f881001) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[106], UInt<64>(0ha7e46347b2c602) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[107], UInt<64>(0h278547b280820141) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[108], UInt<64>(0h10014737bfc5c63e) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[109], UInt<64>(0hdff58b85431c0731) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[110], UInt<64>(0h8b85431c10014737) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[111], UInt<64>(0hec0611018082fff5) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[112], UInt<64>(0h6522fe3ff0efe42a) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[113], UInt<64>(0h185151b100147b7) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[114], UInt<64>(0h47b7fd3ff0efc3c8) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[115], UInt<64>(0h751360e247881001) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[116], UInt<64>(0h47b7808261050ff5) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[117], UInt<64>(0h8082c39847091001) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[118], UInt<64>(0h4437e426e8221101) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[119], UInt<64>(0hf0efec0644891001) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[120], UInt<64>(0hfa1ff0efc004fa7f) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[121], UInt<64>(0h4202306600513) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[122], UInt<64>(0hf91ff0effadff0ef) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[123], UInt<64>(0hf0efc0043e800513) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[124], UInt<64>(0h513f83ff0eff71f) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[125], UInt<64>(0hf0ef000420230990) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[126], UInt<64>(0hc004f73ff0eff8ff) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[127], UInt<64>(0h153764a260e26442) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[128], UInt<64>(0h6105d40505130003) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[129], UInt<64>(0hf022f4067179b799) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[130], UInt<64>(0h10014437e84aec26) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[131], UInt<64>(0h9f00513f4dff0ef) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[132], UInt<64>(0hf59ff0ef00042023) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[133], UInt<64>(0h84aaf53ff0ef4501) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[134], UInt<64>(0h892af4bff0ef4501) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[135], UInt<64>(0h171bf43ff0ef4501) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[136], UInt<64>(0h8fd90104979b0089) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[137], UInt<64>(0hf0efe42a25018d5d) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[138], UInt<64>(0hc01c70a24789f17f) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[139], UInt<64>(0h694264e265227402) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[140], UInt<64>(0hec06110180826145) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[141], UInt<64>(0h84ae842ae426e822) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[142], UInt<64>(0hef1ff0ef8932e04a) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[143], UInt<64>(0h7a023100147b7) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[144], UInt<64>(0h551befbff0ef454d) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[145], UInt<64>(0h551bef3ff0ef0184) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[146], UInt<64>(0hf0ef0ff575130104) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[147], UInt<64>(0h75130084551bee7f) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[148], UInt<64>(0h7513edbff0ef0ff5) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[149], UInt<64>(0h4401ed3ff0ef0ff4) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[150], UInt<64>(0h127ee630004079b) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[151], UInt<64>(0h644260e2eadff0ef) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[152], UInt<64>(0hc3984709100147b7) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[153], UInt<64>(0h80826105690264a2) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[154], UInt<64>(0h87b3eabff0ef4501) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[155], UInt<64>(0h40500a780230084) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[156], UInt<64>(0hbfc1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[157], UInt<64>(0h80000000) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[158], UInt<64>(0h80000000) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[159], UInt<64>(0h52524520544f4f42) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[160], UInt<64>(0h203a524f) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[161], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[162], UInt<64>(0h783020) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[163], UInt<64>(0h2074656b636f520a) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[164], UInt<64>(0h6f62206873616c66) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[165], UInt<64>(0h726564616f6c746f) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[166], UInt<64>(0ha) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[167], UInt<64>(0h6f20726564616548) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[168], UInt<64>(0h30203a7465736666) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[169], UInt<64>(0h78) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[170], UInt<64>(0h454a206873616c46) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[171], UInt<64>(0h203a444920434544) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[172], UInt<64>(0h7830) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[173], UInt<64>(0h67616d6920646162) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[174], UInt<64>(0h636967616d2065) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[175], UInt<64>(0h67616d6920646162) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[176], UInt<64>(0h6f69737265762065) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[177], UInt<64>(0h7265646165682f6e) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[178], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[179], UInt<64>(0h67616d6920646162) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[180], UInt<64>(0h657a69732065) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[181], UInt<64>(0h756f206567616d69) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[182], UInt<64>(0h5444206564697374) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[183], UInt<64>(0h4d49) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[184], UInt<64>(0h6c66203a64616f4c) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[185], UInt<64>(0h783020687361) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[186], UInt<64>(0h206d656d203e2d20) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[187], UInt<64>(0h7830) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[188], UInt<64>(0h3020657a6973202c) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[189], UInt<64>(0h78) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[190], UInt<64>(0h6d73696d20637263) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[191], UInt<64>(0h68637461) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[192], UInt<64>(0h202c6b6f20435243) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[193], UInt<64>(0h20676e69706d756a) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[194], UInt<64>(0h7830) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[195], UInt<64>(0h3736353433323130) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[196], UInt<64>(0h6665646362613938) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[197], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[198], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[199], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[200], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[201], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[202], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[203], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[204], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[205], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[206], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[207], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[208], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[209], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[210], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[211], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[212], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[213], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[214], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[215], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[216], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[217], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[218], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[219], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[220], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[221], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[222], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[223], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[224], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[225], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[226], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[227], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[228], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[229], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[230], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[231], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[232], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[233], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[234], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[235], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[236], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[237], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[238], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[239], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[240], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[241], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[242], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[243], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[244], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[245], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[246], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[247], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[248], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[249], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[250], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[251], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[252], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[253], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[254], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect rom[255], UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 55:22] connect nodeIn.d.valid, nodeIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 57:16] connect nodeIn.a.ready, nodeIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 58:16] node index = bits(nodeIn.a.bits.address, 10, 3) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 60:34] node high = bits(nodeIn.a.bits.address, 15, 11) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 61:64] node _nodeIn_d_bits_T = orr(high) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 62:53] node _nodeIn_d_bits_T_1 = mux(_nodeIn_d_bits_T, UInt<1>(0h0), rom[index]) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 62:47] wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 810:17] connect nodeIn_d_bits_d.opcode, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 811:15] connect nodeIn_d_bits_d.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 812:15] connect nodeIn_d_bits_d.size, nodeIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 813:15] connect nodeIn_d_bits_d.source, nodeIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 814:15] connect nodeIn_d_bits_d.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 815:15] connect nodeIn_d_bits_d.denied, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 816:15] connect nodeIn_d_bits_d.data, _nodeIn_d_bits_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 819:15] connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 820:15] connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 62:15] connect nodeIn.d.bits.data, nodeIn_d_bits_d.data @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 62:15] connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 62:15] connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 62:15] connect nodeIn.d.bits.source, nodeIn_d_bits_d.source @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 62:15] connect nodeIn.d.bits.size, nodeIn_d_bits_d.size @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 62:15] connect nodeIn.d.bits.param, nodeIn_d_bits_d.param @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 62:15] connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 62:15] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<17>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 65:16] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<17>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 66:16] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 67:16] module bootromClockSinkDomain : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 14:9] output auto : { flip bootrom_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_in : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 21:19] output reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 22:19] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] inst bootrom of TLROM @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 102:17] connect bootrom.clock, childClock connect bootrom.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate clockNodeIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate clockNodeIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect clockNodeIn, auto.clock_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect bootrom.auto.in, auto.bootrom_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect childClock, clockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 15:16] connect childReset, clockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 16:16] connect clock, clockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 23:11] connect reset, clockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 24:11] module Queue1_RegMapperInput_i9_m8 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegMapper.scala 71:32] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegMapper.scala 71:32] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegMapper.scala 71:32] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}}, count : UInt<1>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}} [1] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] wire enq_ptr_value : UInt @[src/main/scala/chisel3/util/Counter.scala 61:73] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:73] wire deq_ptr_value : UInt @[src/main/scala/chisel3/util/Counter.scala 61:73] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:73] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] wire _WIRE : UInt @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect _WIRE, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 270:8] infer mport MPORT = ram[_WIRE], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT.extra, io.enq.bits.extra @[src/main/scala/chisel3/util/Decoupled.scala 270:24] connect MPORT.mask, io.enq.bits.mask @[src/main/scala/chisel3/util/Decoupled.scala 270:24] connect MPORT.data, io.enq.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 270:24] connect MPORT.index, io.enq.bits.index @[src/main/scala/chisel3/util/Decoupled.scala 270:24] connect MPORT.read, io.enq.bits.read @[src/main/scala/chisel3/util/Decoupled.scala 270:24] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] skip node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] wire _io_deq_bits_WIRE : UInt @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect _io_deq_bits_WIRE, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 293:23] infer mport io_deq_bits_MPORT = ram[_io_deq_bits_WIRE], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module TLFpgaUART : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 64:9] input clock : Clock @[hardware/soc/scala/fpga/VCU118Peripherals.scala 64:9] input reset : Reset @[hardware/soc/scala/fpga/VCU118Peripherals.scala 64:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, txd_out : UInt<1>, flip rxd_in : UInt<1>} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire rxdNodeIn : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate rxdNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire txdNodeOut : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate txdNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect rxdNodeIn, auto.rxd_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.txd_out, txdNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] wire txd : UInt<1> @[hardware/soc/scala/fpga/VCU118Peripherals.scala 66:19] connect txdNodeOut, txd @[hardware/soc/scala/fpga/VCU118Peripherals.scala 67:20] regreset clockFrequency : UInt<32>, clock, reset, UInt<32>(0h5f5e100) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 70:33] regreset baudRate : UInt<32>, clock, reset, UInt<32>(0h1c200) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 71:27] regreset divisor : UInt<32>, clock, reset, UInt<32>(0h364) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 72:26] node _divisorMinusOne_T = leq(divisor, UInt<1>(0h1)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 73:39] node _divisorMinusOne_T_1 = sub(divisor, UInt<1>(0h1)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 73:60] node _divisorMinusOne_T_2 = tail(_divisorMinusOne_T_1, 1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 73:60] node divisorMinusOne = mux(_divisorMinusOne_T, UInt<1>(0h1), _divisorMinusOne_T_2) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 73:30] node _rxStartDelay_T = leq(divisor, UInt<1>(0h1)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 74:36] node _rxStartDelay_T_1 = shr(divisor, 1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 74:68] node _rxStartDelay_T_2 = add(divisor, _rxStartDelay_T_1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 74:57] node _rxStartDelay_T_3 = tail(_rxStartDelay_T_2, 1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 74:57] node _rxStartDelay_T_4 = sub(_rxStartDelay_T_3, UInt<1>(0h1)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 74:74] node _rxStartDelay_T_5 = tail(_rxStartDelay_T_4, 1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 74:74] node rxStartDelay = mux(_rxStartDelay_T, UInt<1>(0h1), _rxStartDelay_T_5) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 74:27] regreset txReg : UInt<10>, clock, reset, UInt<10>(0h1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 76:24] regreset txBusy : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 77:25] regreset txDiv : UInt<32>, clock, reset, UInt<32>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 78:24] regreset txCount : UInt<4>, clock, reset, UInt<4>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 79:26] node _txd_T = bits(txReg, 0, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 81:17] connect txd, _txd_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 81:9] when txBusy : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 83:18] node _T = eq(txDiv, divisorMinusOne) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 84:18] when _T : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 84:39] connect txDiv, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 85:15] node _txReg_T = bits(txReg, 9, 1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 86:37] node _txReg_T_1 = cat(UInt<1>(0h1), _txReg_T) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 86:21] connect txReg, _txReg_T_1 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 86:15] node _T_1 = eq(txCount, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 87:22] when _T_1 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 87:31] connect txBusy, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 88:18] node _txReg_T_2 = mux(UInt<1>(0h1), UInt<10>(0h3ff), UInt<10>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 89:24] connect txReg, _txReg_T_2 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 89:17] else : node _txCount_T = sub(txCount, UInt<1>(0h1)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 91:30] node _txCount_T_1 = tail(_txCount_T, 1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 91:30] connect txCount, _txCount_T_1 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 91:19] else : node _txDiv_T = add(txDiv, UInt<1>(0h1)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 94:24] node _txDiv_T_1 = tail(_txDiv_T, 1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 94:24] connect txDiv, _txDiv_T_1 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 94:15] regreset rxSync_REG : UInt<1>, clock, reset, UInt<1>(0h1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 98:33] connect rxSync_REG, rxdNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 98:33] regreset rxSync : UInt<1>, clock, reset, UInt<1>(0h1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 98:25] connect rxSync, rxSync_REG @[hardware/soc/scala/fpga/VCU118Peripherals.scala 98:25] regreset rxPrev : UInt<1>, clock, reset, UInt<1>(0h1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 99:25] connect rxPrev, rxSync @[hardware/soc/scala/fpga/VCU118Peripherals.scala 99:25] regreset rxBusy : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 100:25] regreset rxDiv : UInt<32>, clock, reset, UInt<32>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 101:24] regreset rxCount : UInt<4>, clock, reset, UInt<4>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 102:26] regreset rxShift : UInt<8>, clock, reset, UInt<8>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 103:26] regreset rxData : UInt<8>, clock, reset, UInt<8>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 104:25] regreset rxValid : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 105:26] node _T_2 = eq(rxBusy, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 107:10] node _T_3 = and(_T_2, rxPrev) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 107:18] node _T_4 = eq(rxSync, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 107:31] node _T_5 = and(_T_3, _T_4) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 107:28] when _T_5 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 107:40] connect rxBusy, UInt<1>(0h1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 108:14] connect rxDiv, rxStartDelay @[hardware/soc/scala/fpga/VCU118Peripherals.scala 109:13] connect rxCount, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 110:15] else : when rxBusy : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 111:24] node _T_6 = eq(rxDiv, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 112:18] when _T_6 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 112:27] connect rxDiv, divisorMinusOne @[hardware/soc/scala/fpga/VCU118Peripherals.scala 113:15] node _T_7 = lt(rxCount, UInt<4>(0h8)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 114:22] when _T_7 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 114:29] node _rxShift_T = bits(rxShift, 7, 1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 115:41] node _rxShift_T_1 = cat(rxSync, _rxShift_T) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 115:25] connect rxShift, _rxShift_T_1 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 115:19] node _rxCount_T = add(rxCount, UInt<1>(0h1)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 116:30] node _rxCount_T_1 = tail(_rxCount_T, 1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 116:30] connect rxCount, _rxCount_T_1 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 116:19] else : connect rxBusy, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 118:18] when rxSync : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 119:24] connect rxData, rxShift @[hardware/soc/scala/fpga/VCU118Peripherals.scala 120:20] connect rxValid, UInt<1>(0h1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 121:21] else : node _rxDiv_T = sub(rxDiv, UInt<1>(0h1)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 125:24] node _rxDiv_T_1 = tail(_rxDiv_T, 1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 125:24] connect rxDiv, _rxDiv_T_1 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 125:15] node _T_8 = eq(txBusy, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 147:33] wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 73:18] node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 74:36] connect in.bits.read, _in_bits_read_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 74:19] node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 192:34] connect in.bits.index, _in_bits_index_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 75:19] connect in.bits.data, nodeIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 76:19] connect in.bits.mask, nodeIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 77:19] connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 83:20] connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 84:20] wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front.bits, in.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] inst out_back_front_q of Queue1_RegMapperInput_i9_m8 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_back_front_q.clock, clock connect out_back_front_q.reset, reset connect out_back_front_q.io.enq, out_front @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_maskMatch = not(UInt<9>(0h3)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_findex = and(out_front.bits.index, out_maskMatch) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_bindex = and(out_back_front_q.io.deq.bits.index, out_maskMatch) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T = eq(out_findex, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2 = eq(out_findex, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4 = eq(out_findex, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5 = eq(out_bindex, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_6 = eq(out_findex, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_7 = eq(out_bindex, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rivalid : UInt<1>[7] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wivalid : UInt<1>[7] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_roready : UInt<1>[7] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_woready : UInt<1>[7] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T = bits(out_back_front_q.io.deq.bits.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_1 = bits(out_back_front_q.io.deq.bits.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_2 = bits(out_back_front_q.io.deq.bits.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_3 = bits(out_back_front_q.io.deq.bits.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_4 = bits(out_back_front_q.io.deq.bits.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_5 = bits(out_back_front_q.io.deq.bits.mask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_6 = bits(out_back_front_q.io.deq.bits.mask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_7 = bits(out_back_front_q.io.deq.bits.mask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask = cat(out_backMask_hi, out_backMask_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask = orr(_out_rimask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T = bits(out_frontMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask = andr(_out_wimask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask = orr(_out_romask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T = bits(out_backMask, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask = andr(_out_womask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid = and(out_rivalid[0], out_rimask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready = and(out_roready[0], out_romask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid = and(out_wivalid[0], out_wimask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready = and(out_woready[0], out_womask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8 = bits(out_back_front_q.io.deq.bits.data, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9 = eq(txBusy, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 130:21] node _out_T_10 = and(out_f_woready, _out_T_9) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 130:18] when _out_T_10 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 130:30] node _out_txReg_T = bits(_out_T_8, 7, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 131:36] node out_txReg_hi = cat(UInt<1>(0h1), _out_txReg_T) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 131:21] node _out_txReg_T_1 = cat(out_txReg_hi, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 131:21] connect txReg, _out_txReg_T_1 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 131:15] connect txBusy, UInt<1>(0h1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 132:16] connect txDiv, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 133:15] connect txCount, UInt<4>(0h9) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 134:17] node _out_T_11 = and(out_f_wivalid, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12 = and(UInt<1>(0h1), out_f_woready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_13 = eq(out_rimask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_14 = eq(out_wimask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_15 = eq(out_romask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_16 = eq(out_womask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_17 = or(UInt<1>(0h0), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_18 = bits(_out_T_17, 7, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1 = bits(out_frontMask, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1 = orr(_out_rimask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1 = bits(out_frontMask, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1 = andr(_out_wimask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1 = bits(out_backMask, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1 = orr(_out_romask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1 = bits(out_backMask, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1 = andr(_out_womask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1 = and(out_roready[1], out_romask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1 = and(out_woready[1], out_womask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_roready_1 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 140:19] connect rxValid, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 140:29] node _out_T_19 = bits(out_back_front_q.io.deq.bits.data, 39, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_20 = and(out_f_rivalid_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_21 = and(UInt<1>(0h1), out_f_roready_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_22 = eq(out_rimask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_23 = eq(out_wimask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_24 = eq(out_romask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_25 = eq(out_womask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T = or(_out_T_18, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend = cat(rxData, _out_prepend_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_26 = or(out_prepend, UInt<40>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_27 = bits(_out_T_26, 39, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_2 = bits(out_frontMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_2 = orr(_out_rimask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_2 = bits(out_frontMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_2 = andr(_out_wimask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_2 = bits(out_backMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_2 = orr(_out_romask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_2 = bits(out_backMask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_2 = andr(_out_womask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_2 = and(out_roready[2], out_romask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_2 = and(out_woready[2], out_womask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_28 = bits(out_back_front_q.io.deq.bits.data, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_29 = and(out_f_rivalid_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_30 = and(UInt<1>(0h1), out_f_roready_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_31 = eq(out_rimask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_32 = eq(out_wimask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_33 = eq(out_romask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_34 = eq(out_womask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_35 = or(_T_8, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_36 = bits(_out_T_35, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_3 = bits(out_frontMask, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_3 = orr(_out_rimask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_3 = bits(out_frontMask, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_3 = andr(_out_wimask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_3 = bits(out_backMask, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_3 = orr(_out_romask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_3 = bits(out_backMask, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_3 = andr(_out_womask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_3 = and(out_roready[3], out_romask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_3 = and(out_woready[3], out_womask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_37 = bits(out_back_front_q.io.deq.bits.data, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_38 = and(out_f_rivalid_3, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_39 = and(UInt<1>(0h1), out_f_roready_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_40 = eq(out_rimask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_41 = eq(out_wimask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_42 = eq(out_romask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_43 = eq(out_womask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1 = or(_out_T_36, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1 = cat(rxValid, _out_prepend_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_44 = or(out_prepend_1, UInt<33>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_45 = bits(_out_T_44, 32, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_4 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_4 = orr(_out_rimask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_4 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_4 = andr(_out_wimask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_4 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_4 = orr(_out_romask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_4 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_4 = andr(_out_womask_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_4 = and(out_roready[4], out_romask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_4 = and(out_woready[4], out_womask_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_46 = bits(out_back_front_q.io.deq.bits.data, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_4 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect clockFrequency, _out_T_46 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_47 = and(out_f_rivalid_4, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_48 = and(UInt<1>(0h1), out_f_roready_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_49 = and(out_f_wivalid_4, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_50 = and(UInt<1>(0h1), out_f_woready_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_51 = eq(out_rimask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_52 = eq(out_wimask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_53 = eq(out_romask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_54 = eq(out_womask_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_55 = or(clockFrequency, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_56 = bits(_out_T_55, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_5 = bits(out_frontMask, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_5 = orr(_out_rimask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_5 = bits(out_frontMask, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_5 = andr(_out_wimask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_5 = bits(out_backMask, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_5 = orr(_out_romask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_5 = bits(out_backMask, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_5 = andr(_out_womask_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_5 = and(out_roready[5], out_romask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_5 = and(out_woready[5], out_womask_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_57 = bits(out_back_front_q.io.deq.bits.data, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_5 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect baudRate, _out_T_57 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_58 = and(out_f_rivalid_5, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_59 = and(UInt<1>(0h1), out_f_roready_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_60 = and(out_f_wivalid_5, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_61 = and(UInt<1>(0h1), out_f_woready_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_62 = eq(out_rimask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_63 = eq(out_wimask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_64 = eq(out_romask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_65 = eq(out_womask_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_2 = or(_out_T_56, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_2 = cat(baudRate, _out_prepend_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_66 = or(out_prepend_2, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_67 = bits(_out_T_66, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_6 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_6 = orr(_out_rimask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_6 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_6 = andr(_out_wimask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_6 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_6 = orr(_out_romask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_6 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_6 = andr(_out_womask_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_6 = and(out_roready[6], out_romask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_6 = and(out_woready[6], out_womask_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_68 = bits(out_back_front_q.io.deq.bits.data, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] when out_f_woready_6 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:88] connect divisor, _out_T_68 @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegField.scala 76:92] node _out_T_69 = and(out_f_rivalid_6, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_70 = and(UInt<1>(0h1), out_f_roready_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_71 = and(out_f_wivalid_6, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_72 = and(UInt<1>(0h1), out_f_woready_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_73 = eq(out_rimask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_74 = eq(out_wimask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_75 = eq(out_romask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_76 = eq(out_womask_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_77 = or(divisor, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_78 = bits(_out_T_77, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T = bits(out_front.bits.index, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex = cat(_out_iindex_T_1, _out_iindex_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T = bits(out_back_front_q.io.deq.bits.index, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_1 = bits(out_back_front_q.io.deq.bits.index, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_2 = bits(out_back_front_q.io.deq.bits.index, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_3 = bits(out_back_front_q.io.deq.bits.index, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_4 = bits(out_back_front_q.io.deq.bits.index, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_5 = bits(out_back_front_q.io.deq.bits.index, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_6 = bits(out_back_front_q.io.deq.bits.index, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_7 = bits(out_back_front_q.io.deq.bits.index, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_8 = bits(out_back_front_q.io.deq.bits.index, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex = cat(_out_oindex_T_1, _out_oindex_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node out_backSel_0 = bits(_out_backSel_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_1 = bits(_out_backSel_T, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_2 = bits(_out_backSel_T, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_3 = bits(_out_backSel_T, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T = and(in.valid, out_front.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[1], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[0], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[3], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[2], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_2 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_2, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[5], _out_rifireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[4], _out_rifireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_12 = eq(_out_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_3 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_3, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[6], _out_rifireMux_T_15 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_16 = eq(_out_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_rifireMux_WIRE : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_wifireMux_T = and(in.valid, out_front.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[1], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[0], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[3], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[2], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_2 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_2, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[5], _out_wifireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[4], _out_wifireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_13 = eq(_out_T_4, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_3 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_3, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[6], _out_wifireMux_T_16 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_17 = eq(_out_T_6, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_wifireMux_WIRE : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_rofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_back_front_q.io.deq.bits.read) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[1], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[0], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[3], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[2], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_2 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_2, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[5], _out_rofireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[4], _out_rofireMux_T_11 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_12 = eq(_out_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_3 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_3, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[6], _out_rofireMux_T_15 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_16 = eq(_out_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_rofireMux_WIRE : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_wofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1 = eq(out_back_front_q.io.deq.bits.read, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[1], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[0], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[3], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[2], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_2 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_2, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[5], _out_wofireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[4], _out_wofireMux_T_12 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_13 = eq(_out_T_5, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_3 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_3, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[6], _out_wofireMux_T_16 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_17 = eq(_out_T_7, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_wofireMux_WIRE : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oready = mux(out_back_front_q.io.deq.bits.read, out_rofireMux, out_wofireMux) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_in_ready_T = and(out_front.ready, out_iready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect in.ready, _out_in_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_front_valid_T = and(in.valid, out_iready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front.valid, _out_front_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_front_q_io_deq_ready_T = and(out.ready, out_oready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_back_front_q.io.deq.ready, _out_front_q_io_deq_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_out_valid_T = and(out_back_front_q.io.deq.valid, out_oready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.valid, _out_out_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.read, out_back_front_q.io.deq.bits.read @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_out_bits_data_WIRE : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[0], _out_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[1], _out_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[2], _out_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[3], _out_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_out_bits_data_WIRE_1 : UInt<64>[4] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[0], _out_T_27 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[1], _out_T_45 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[2], _out_T_67 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[3], _out_T_78 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.data, _out_out_bits_data_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.extra, out_back_front_q.io.deq.bits.extra @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect in.valid, nodeIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 90:15] connect nodeIn.a.ready, in.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 91:15] connect nodeIn.d.valid, out.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 92:15] connect out.ready, nodeIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 93:15] wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 792:17] connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 793:15] connect nodeIn_d_bits_d.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 794:15] connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 795:15] connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 796:15] connect nodeIn_d_bits_d.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 797:15] connect nodeIn_d_bits_d.denied, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 798:15] invalidate nodeIn_d_bits_d.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 801:15] connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 802:15] connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.data, nodeIn_d_bits_d.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.source, nodeIn_d_bits_d.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.size, nodeIn_d_bits_d.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.param, nodeIn_d_bits_d.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.data, out.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 100:17] node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 105:25] connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 105:19] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 108:22] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 109:22] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 110:22] module FPGAUARTClockSinkDomain : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 14:9] output auto : { flip dev_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, dev_txd_out : UInt<1>, flip dev_rxd_in : UInt<1>, flip clock_in : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 21:19] output reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 22:19] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] inst dev of TLFpgaUART @[hardware/soc/scala/fpga/VCU118Peripherals.scala 617:34] connect dev.clock, childClock connect dev.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate clockNodeIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate clockNodeIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect clockNodeIn, auto.clock_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect dev.auto.rxd_in, auto.dev_rxd_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.dev_txd_out, dev.auto.txd_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect dev.auto.in, auto.dev_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect childClock, clockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 15:16] connect childReset, clockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 16:16] connect clock, clockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 23:11] connect reset, clockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 24:11] module Queue1_RegMapperInput_i9_m8_1 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegMapper.scala 71:32] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegMapper.scala 71:32] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegMapper.scala 71:32] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}}, count : UInt<1>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}} [1] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] wire enq_ptr_value : UInt @[src/main/scala/chisel3/util/Counter.scala 61:73] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:73] wire deq_ptr_value : UInt @[src/main/scala/chisel3/util/Counter.scala 61:73] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:73] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] wire _WIRE : UInt @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect _WIRE, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 270:8] infer mport MPORT = ram[_WIRE], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT.extra, io.enq.bits.extra @[src/main/scala/chisel3/util/Decoupled.scala 270:24] connect MPORT.mask, io.enq.bits.mask @[src/main/scala/chisel3/util/Decoupled.scala 270:24] connect MPORT.data, io.enq.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 270:24] connect MPORT.index, io.enq.bits.index @[src/main/scala/chisel3/util/Decoupled.scala 270:24] connect MPORT.read, io.enq.bits.read @[src/main/scala/chisel3/util/Decoupled.scala 270:24] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] skip node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] wire _io_deq_bits_WIRE : UInt @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect _io_deq_bits_WIRE, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 293:23] infer mport io_deq_bits_MPORT = ram[_io_deq_bits_WIRE], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module TLFpgaSPI : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 184:9] input clock : Clock @[hardware/soc/scala/fpga/VCU118Peripherals.scala 184:9] input reset : Reset @[hardware/soc/scala/fpga/VCU118Peripherals.scala 184:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, dq_oe_out : UInt<4>, dq_out_out : UInt<4>, flip dq_in_in : UInt<4>, csn_out : UInt<1>, sck_out : UInt<1>} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire sckNodeOut : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate sckNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire csnNodeOut : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate csnNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire dqInNodeIn : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate dqInNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire dqOutNodeOut : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate dqOutNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire dqOeNodeOut : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate dqOeNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.sck_out, sckNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.csn_out, csnNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect dqInNodeIn, auto.dq_in_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.dq_out_out, dqOutNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.dq_oe_out, dqOeNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] wire sck_o : UInt<1> @[hardware/soc/scala/fpga/VCU118Peripherals.scala 186:21] wire csn_o : UInt<1> @[hardware/soc/scala/fpga/VCU118Peripherals.scala 187:21] wire dq_o : UInt<4> @[hardware/soc/scala/fpga/VCU118Peripherals.scala 188:20] wire dq_oe : UInt<4> @[hardware/soc/scala/fpga/VCU118Peripherals.scala 189:21] connect sckNodeOut, sck_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 191:20] connect csnNodeOut, csn_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 192:20] connect dqOutNodeOut, dq_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 193:22] connect dqOeNodeOut, dq_oe @[hardware/soc/scala/fpga/VCU118Peripherals.scala 194:21] regreset csn : UInt<1>, clock, reset, UInt<1>(0h1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 196:22] regreset sck : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 197:22] regreset quad : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 198:23] regreset cpol : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 199:23] regreset cpha : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 200:23] regreset txShift : UInt<32>, clock, reset, UInt<32>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 201:26] regreset rxShift : UInt<32>, clock, reset, UInt<32>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 202:26] regreset bitsLeft : UInt<6>, clock, reset, UInt<6>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 203:27] regreset busy : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 204:23] regreset div : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 205:22] connect csn_o, csn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 207:11] connect sck_o, sck @[hardware/soc/scala/fpga/VCU118Peripherals.scala 208:11] node _dq_o_T = bits(txShift, 31, 28) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 209:30] node _dq_o_T_1 = bits(txShift, 31, 31) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 209:61] node _dq_o_T_2 = cat(UInt<3>(0h0), _dq_o_T_1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 209:43] node _dq_o_T_3 = mux(quad, _dq_o_T, _dq_o_T_2) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 209:16] connect dq_o, _dq_o_T_3 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 209:10] node _dq_oe_T = eq(busy, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 210:25] node _dq_oe_T_1 = or(csn, _dq_oe_T) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 210:22] node _dq_oe_T_2 = mux(quad, UInt<4>(0hf), UInt<1>(0h1)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 210:40] node _dq_oe_T_3 = mux(_dq_oe_T_1, UInt<1>(0h0), _dq_oe_T_2) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 210:17] connect dq_oe, _dq_oe_T_3 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 210:11] when busy : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 212:16] node _T = eq(div, UInt<3>(0h7)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 213:16] when _T : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 213:45] connect div, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 214:13] node _sck_T = not(sck) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 215:16] connect sck, _sck_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 215:13] node step = mux(quad, UInt<3>(0h4), UInt<1>(0h1)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 216:23] node leadingEdge = eq(sck, cpol) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 223:31] node _sampleEdge_T = eq(leadingEdge, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 224:36] node sampleEdge = mux(cpha, _sampleEdge_T, leadingEdge) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 224:29] when sampleEdge : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 225:26] node _rxShift_T = bits(rxShift, 27, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 226:43] node _rxShift_T_1 = cat(_rxShift_T, dqInNodeIn) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 226:35] node _rxShift_T_2 = bits(rxShift, 30, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 226:70] node _rxShift_T_3 = bits(dqInNodeIn, 1, 1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 226:83] node _rxShift_T_4 = cat(_rxShift_T_2, _rxShift_T_3) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 226:62] node _rxShift_T_5 = mux(quad, _rxShift_T_1, _rxShift_T_4) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 226:25] connect rxShift, _rxShift_T_5 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 226:19] node _advanceEdge_T = eq(sampleEdge, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 233:49] node advanceEdge = mux(cpha, sampleEdge, _advanceEdge_T) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 233:30] when advanceEdge : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 234:27] node _txShift_T = bits(txShift, 27, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 235:43] node _txShift_T_1 = cat(_txShift_T, UInt<4>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 235:35] node _txShift_T_2 = bits(txShift, 30, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 235:74] node _txShift_T_3 = cat(_txShift_T_2, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 235:66] node _txShift_T_4 = mux(quad, _txShift_T_1, _txShift_T_3) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 235:25] connect txShift, _txShift_T_4 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 235:19] node _T_1 = leq(bitsLeft, step) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 236:25] when _T_1 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 236:34] connect busy, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 237:18] connect sck, cpol @[hardware/soc/scala/fpga/VCU118Peripherals.scala 238:17] connect bitsLeft, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 239:22] else : node _bitsLeft_T = sub(bitsLeft, step) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 241:34] node _bitsLeft_T_1 = tail(_bitsLeft_T, 1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 241:34] connect bitsLeft, _bitsLeft_T_1 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 241:22] else : node _div_T = add(div, UInt<1>(0h1)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 245:20] node _div_T_1 = tail(_div_T, 1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 245:20] connect div, _div_T_1 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 245:13] wire ctrl : UInt<32> @[hardware/soc/scala/fpga/VCU118Peripherals.scala 249:20] node ctrl_lo_hi = cat(quad, csn) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 250:16] node ctrl_lo = cat(ctrl_lo_hi, busy) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 250:16] node ctrl_hi_hi = cat(UInt<27>(0h0), cpha) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 250:16] node ctrl_hi = cat(ctrl_hi_hi, cpol) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 250:16] node _ctrl_T = cat(ctrl_hi, ctrl_lo) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 250:16] connect ctrl, _ctrl_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 250:10] node _T_2 = eq(busy, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 279:33] wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 73:18] node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 74:36] connect in.bits.read, _in_bits_read_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 74:19] node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 192:34] connect in.bits.index, _in_bits_index_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 75:19] connect in.bits.data, nodeIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 76:19] connect in.bits.mask, nodeIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 77:19] connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 83:20] connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 84:20] wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front.bits, in.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] inst out_back_front_q of Queue1_RegMapperInput_i9_m8_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_back_front_q.clock, clock connect out_back_front_q.reset, reset connect out_back_front_q.io.enq, out_front @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_maskMatch = not(UInt<9>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_findex = and(out_front.bits.index, out_maskMatch) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_bindex = and(out_back_front_q.io.deq.bits.index, out_maskMatch) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T = eq(out_findex, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2 = eq(out_findex, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rivalid : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wivalid : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_roready : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_woready : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T = bits(out_back_front_q.io.deq.bits.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_1 = bits(out_back_front_q.io.deq.bits.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_2 = bits(out_back_front_q.io.deq.bits.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_3 = bits(out_back_front_q.io.deq.bits.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_4 = bits(out_back_front_q.io.deq.bits.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_5 = bits(out_back_front_q.io.deq.bits.mask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_6 = bits(out_back_front_q.io.deq.bits.mask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_7 = bits(out_back_front_q.io.deq.bits.mask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask = cat(out_backMask_hi, out_backMask_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask = orr(_out_rimask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask = andr(_out_wimask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask = orr(_out_romask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask = andr(_out_womask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid = and(out_rivalid[0], out_rimask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready = and(out_roready[0], out_romask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid = and(out_wivalid[0], out_wimask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready = and(out_woready[0], out_womask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4 = bits(out_back_front_q.io.deq.bits.data, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5 = eq(busy, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 253:21] node _out_T_6 = and(out_f_woready, _out_T_5) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 253:18] when _out_T_6 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 253:28] node _out_csn_T = bits(_out_T_4, 1, 1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 254:20] connect csn, _out_csn_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 254:13] node _out_quad_T = bits(_out_T_4, 2, 2) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 255:21] connect quad, _out_quad_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 255:14] node _out_cpol_T = bits(_out_T_4, 3, 3) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 256:21] connect cpol, _out_cpol_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 256:14] node _out_cpha_T = bits(_out_T_4, 4, 4) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 257:21] connect cpha, _out_cpha_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 257:14] node _out_sck_T = bits(_out_T_4, 3, 3) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 258:20] connect sck, _out_sck_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 258:13] node _out_T_7 = and(out_f_rivalid, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8 = and(UInt<1>(0h1), out_f_roready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9 = and(out_f_wivalid, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10 = and(UInt<1>(0h1), out_f_woready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11 = eq(out_rimask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12 = eq(out_wimask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_13 = eq(out_romask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_14 = eq(out_womask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_15 = or(ctrl, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_16 = bits(_out_T_15, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1 = bits(out_frontMask, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1 = orr(_out_rimask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1 = bits(out_frontMask, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1 = andr(_out_wimask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1 = bits(out_backMask, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1 = orr(_out_romask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1 = bits(out_backMask, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1 = andr(_out_womask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1 = and(out_roready[1], out_romask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1 = and(out_woready[1], out_womask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_17 = bits(out_back_front_q.io.deq.bits.data, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_18 = eq(busy, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 264:21] node _out_T_19 = and(out_f_woready_1, _out_T_18) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 264:18] when _out_T_19 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 264:28] connect txShift, _out_T_17 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 265:17] connect rxShift, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 266:17] node _out_bitsLeft_T = mux(quad, UInt<6>(0h20), UInt<4>(0h8)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 267:24] connect bitsLeft, _out_bitsLeft_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 267:18] connect busy, UInt<1>(0h1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 268:14] connect div, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 269:13] connect sck, cpol @[hardware/soc/scala/fpga/VCU118Peripherals.scala 270:13] node _out_T_20 = and(out_f_wivalid_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_21 = and(UInt<1>(0h1), out_f_woready_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_22 = eq(out_rimask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_23 = eq(out_wimask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_24 = eq(out_romask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_25 = eq(out_womask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T = or(_out_T_16, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend = cat(UInt<1>(0h0), _out_prepend_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_26 = or(out_prepend, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_27 = bits(_out_T_26, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_2 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_2 = orr(_out_rimask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_2 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_2 = andr(_out_wimask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_2 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_2 = orr(_out_romask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_2 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_2 = andr(_out_womask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_2 = and(out_roready[2], out_romask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_2 = and(out_woready[2], out_womask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_28 = bits(out_back_front_q.io.deq.bits.data, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_29 = and(out_f_rivalid_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_30 = and(UInt<1>(0h1), out_f_roready_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_31 = eq(out_rimask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_32 = eq(out_wimask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_33 = eq(out_romask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_34 = eq(out_womask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_35 = or(rxShift, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_36 = bits(_out_T_35, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_3 = bits(out_frontMask, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_3 = orr(_out_rimask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_3 = bits(out_frontMask, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_3 = andr(_out_wimask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_3 = bits(out_backMask, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_3 = orr(_out_romask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_3 = bits(out_backMask, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_3 = andr(_out_womask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_3 = and(out_roready[3], out_romask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_3 = and(out_woready[3], out_womask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_37 = bits(out_back_front_q.io.deq.bits.data, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_38 = and(out_f_rivalid_3, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_39 = and(UInt<1>(0h1), out_f_roready_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_40 = eq(out_rimask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_41 = eq(out_wimask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_42 = eq(out_romask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_43 = eq(out_womask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1 = or(_out_T_36, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1 = cat(_T_2, _out_prepend_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_44 = or(out_prepend_1, UInt<33>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_45 = bits(_out_T_44, 32, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex = bits(out_front.bits.index, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T = bits(out_front.bits.index, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_1 = bits(out_front.bits.index, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_2 = bits(out_front.bits.index, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_3 = bits(out_front.bits.index, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_4 = bits(out_front.bits.index, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_5 = bits(out_front.bits.index, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_6 = bits(out_front.bits.index, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_7 = bits(out_front.bits.index, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex = bits(out_back_front_q.io.deq.bits.index, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T = bits(out_back_front_q.io.deq.bits.index, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_1 = bits(out_back_front_q.io.deq.bits.index, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_2 = bits(out_back_front_q.io.deq.bits.index, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_3 = bits(out_back_front_q.io.deq.bits.index, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_4 = bits(out_back_front_q.io.deq.bits.index, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_5 = bits(out_back_front_q.io.deq.bits.index, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_6 = bits(out_back_front_q.io.deq.bits.index, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_7 = bits(out_back_front_q.io.deq.bits.index, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node out_backSel_0 = bits(_out_backSel_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_1 = bits(_out_backSel_T, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T = and(in.valid, out_front.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[1], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[0], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[3], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[2], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_10 = geq(out_iindex, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_rifireMux_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_rifireMux = mux(_out_rifireMux_T_10, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_wifireMux_T = and(in.valid, out_front.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[1], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[0], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[3], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[2], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_11 = geq(out_iindex, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_wifireMux_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_wifireMux = mux(_out_wifireMux_T_11, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_rofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_back_front_q.io.deq.bits.read) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[1], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[0], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[3], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[2], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_10 = geq(out_oindex, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_rofireMux_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_rofireMux = mux(_out_rofireMux_T_10, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_wofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1 = eq(out_back_front_q.io.deq.bits.read, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[1], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[0], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[3], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[2], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_11 = geq(out_oindex, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_wofireMux_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_wofireMux = mux(_out_wofireMux_T_11, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oready = mux(out_back_front_q.io.deq.bits.read, out_rofireMux, out_wofireMux) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_in_ready_T = and(out_front.ready, out_iready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect in.ready, _out_in_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_front_valid_T = and(in.valid, out_iready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front.valid, _out_front_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_front_q_io_deq_ready_T = and(out.ready, out_oready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_back_front_q.io.deq.ready, _out_front_q_io_deq_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_out_valid_T = and(out_back_front_q.io.deq.valid, out_oready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.valid, _out_out_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.read, out_back_front_q.io.deq.bits.read @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_out_bits_data_T = geq(out_oindex, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_out_bits_data_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[0], _out_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[1], _out_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_out_bits_data_T_2 = geq(out_oindex, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_out_bits_data_WIRE_1 : UInt<64>[2] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[0], _out_T_27 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[1], _out_T_45 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.data, _out_out_bits_data_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.extra, out_back_front_q.io.deq.bits.extra @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect in.valid, nodeIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 90:15] connect nodeIn.a.ready, in.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 91:15] connect nodeIn.d.valid, out.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 92:15] connect out.ready, nodeIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 93:15] wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 792:17] connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 793:15] connect nodeIn_d_bits_d.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 794:15] connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 795:15] connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 796:15] connect nodeIn_d_bits_d.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 797:15] connect nodeIn_d_bits_d.denied, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 798:15] invalidate nodeIn_d_bits_d.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 801:15] connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 802:15] connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.data, nodeIn_d_bits_d.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.source, nodeIn_d_bits_d.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.size, nodeIn_d_bits_d.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.param, nodeIn_d_bits_d.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.data, out.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 100:17] node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 105:25] connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 105:19] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 108:22] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 109:22] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 110:22] module FPGASPIClockSinkDomain : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 14:9] output auto : { flip dev_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, dev_dq_oe_out : UInt<4>, dev_dq_out_out : UInt<4>, flip dev_dq_in_in : UInt<4>, dev_csn_out : UInt<1>, dev_sck_out : UInt<1>, flip clock_in : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 21:19] output reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 22:19] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] inst dev of TLFpgaSPI @[hardware/soc/scala/fpga/VCU118Peripherals.scala 633:34] connect dev.clock, childClock connect dev.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate clockNodeIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate clockNodeIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect clockNodeIn, auto.clock_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.dev_sck_out, dev.auto.sck_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.dev_csn_out, dev.auto.csn_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect dev.auto.dq_in_in, auto.dev_dq_in_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.dev_dq_out_out, dev.auto.dq_out_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.dev_dq_oe_out, dev.auto.dq_oe_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect dev.auto.in, auto.dev_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect childClock, clockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 15:16] connect childReset, clockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 16:16] connect clock, clockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 23:11] connect reset, clockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 24:11] module Queue1_RegMapperInput_i9_m8_2 : @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegMapper.scala 71:32] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegMapper.scala 71:32] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/regmapper/RegMapper.scala 71:32] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}}, count : UInt<1>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}} [1] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] wire enq_ptr_value : UInt @[src/main/scala/chisel3/util/Counter.scala 61:73] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:73] wire deq_ptr_value : UInt @[src/main/scala/chisel3/util/Counter.scala 61:73] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:73] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] wire _WIRE : UInt @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect _WIRE, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 270:8] infer mport MPORT = ram[_WIRE], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT.extra, io.enq.bits.extra @[src/main/scala/chisel3/util/Decoupled.scala 270:24] connect MPORT.mask, io.enq.bits.mask @[src/main/scala/chisel3/util/Decoupled.scala 270:24] connect MPORT.data, io.enq.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 270:24] connect MPORT.index, io.enq.bits.index @[src/main/scala/chisel3/util/Decoupled.scala 270:24] connect MPORT.read, io.enq.bits.read @[src/main/scala/chisel3/util/Decoupled.scala 270:24] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] skip node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] wire _io_deq_bits_WIRE : UInt @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect _io_deq_bits_WIRE, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 293:23] infer mport io_deq_bits_MPORT = ram[_io_deq_bits_WIRE], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module TLFpgaSPI_1 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 184:9] input clock : Clock @[hardware/soc/scala/fpga/VCU118Peripherals.scala 184:9] input reset : Reset @[hardware/soc/scala/fpga/VCU118Peripherals.scala 184:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, dq_oe_out : UInt<4>, dq_out_out : UInt<4>, flip dq_in_in : UInt<4>, csn_out : UInt<1>, sck_out : UInt<1>} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire sckNodeOut : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate sckNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire csnNodeOut : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate csnNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire dqInNodeIn : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate dqInNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire dqOutNodeOut : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate dqOutNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire dqOeNodeOut : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate dqOeNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect auto.sck_out, sckNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.csn_out, csnNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect dqInNodeIn, auto.dq_in_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.dq_out_out, dqOutNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.dq_oe_out, dqOeNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] wire sck_o : UInt<1> @[hardware/soc/scala/fpga/VCU118Peripherals.scala 186:21] wire csn_o : UInt<1> @[hardware/soc/scala/fpga/VCU118Peripherals.scala 187:21] wire dq_o : UInt<4> @[hardware/soc/scala/fpga/VCU118Peripherals.scala 188:20] wire dq_oe : UInt<4> @[hardware/soc/scala/fpga/VCU118Peripherals.scala 189:21] connect sckNodeOut, sck_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 191:20] connect csnNodeOut, csn_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 192:20] connect dqOutNodeOut, dq_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 193:22] connect dqOeNodeOut, dq_oe @[hardware/soc/scala/fpga/VCU118Peripherals.scala 194:21] regreset csn : UInt<1>, clock, reset, UInt<1>(0h1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 196:22] regreset sck : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 197:22] regreset quad : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 198:23] regreset cpol : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 199:23] regreset cpha : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 200:23] regreset txShift : UInt<32>, clock, reset, UInt<32>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 201:26] regreset rxShift : UInt<32>, clock, reset, UInt<32>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 202:26] regreset bitsLeft : UInt<6>, clock, reset, UInt<6>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 203:27] regreset busy : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 204:23] regreset div : UInt<3>, clock, reset, UInt<3>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 205:22] connect csn_o, csn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 207:11] connect sck_o, sck @[hardware/soc/scala/fpga/VCU118Peripherals.scala 208:11] node _dq_o_T = bits(txShift, 31, 28) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 209:30] node _dq_o_T_1 = bits(txShift, 31, 31) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 209:61] node _dq_o_T_2 = cat(UInt<3>(0h0), _dq_o_T_1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 209:43] node _dq_o_T_3 = mux(quad, _dq_o_T, _dq_o_T_2) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 209:16] connect dq_o, _dq_o_T_3 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 209:10] node _dq_oe_T = eq(busy, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 210:25] node _dq_oe_T_1 = or(csn, _dq_oe_T) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 210:22] node _dq_oe_T_2 = mux(quad, UInt<4>(0hf), UInt<1>(0h1)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 210:40] node _dq_oe_T_3 = mux(_dq_oe_T_1, UInt<1>(0h0), _dq_oe_T_2) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 210:17] connect dq_oe, _dq_oe_T_3 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 210:11] when busy : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 212:16] node _T = eq(div, UInt<3>(0h7)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 213:16] when _T : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 213:45] connect div, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 214:13] node _sck_T = not(sck) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 215:16] connect sck, _sck_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 215:13] node step = mux(quad, UInt<3>(0h4), UInt<1>(0h1)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 216:23] node leadingEdge = eq(sck, cpol) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 223:31] node _sampleEdge_T = eq(leadingEdge, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 224:36] node sampleEdge = mux(cpha, _sampleEdge_T, leadingEdge) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 224:29] when sampleEdge : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 225:26] node _rxShift_T = bits(rxShift, 27, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 226:43] node _rxShift_T_1 = cat(_rxShift_T, dqInNodeIn) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 226:35] node _rxShift_T_2 = bits(rxShift, 30, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 226:70] node _rxShift_T_3 = bits(dqInNodeIn, 1, 1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 226:83] node _rxShift_T_4 = cat(_rxShift_T_2, _rxShift_T_3) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 226:62] node _rxShift_T_5 = mux(quad, _rxShift_T_1, _rxShift_T_4) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 226:25] connect rxShift, _rxShift_T_5 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 226:19] node _advanceEdge_T = eq(sampleEdge, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 233:49] node advanceEdge = mux(cpha, sampleEdge, _advanceEdge_T) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 233:30] when advanceEdge : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 234:27] node _txShift_T = bits(txShift, 27, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 235:43] node _txShift_T_1 = cat(_txShift_T, UInt<4>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 235:35] node _txShift_T_2 = bits(txShift, 30, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 235:74] node _txShift_T_3 = cat(_txShift_T_2, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 235:66] node _txShift_T_4 = mux(quad, _txShift_T_1, _txShift_T_3) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 235:25] connect txShift, _txShift_T_4 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 235:19] node _T_1 = leq(bitsLeft, step) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 236:25] when _T_1 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 236:34] connect busy, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 237:18] connect sck, cpol @[hardware/soc/scala/fpga/VCU118Peripherals.scala 238:17] connect bitsLeft, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 239:22] else : node _bitsLeft_T = sub(bitsLeft, step) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 241:34] node _bitsLeft_T_1 = tail(_bitsLeft_T, 1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 241:34] connect bitsLeft, _bitsLeft_T_1 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 241:22] else : node _div_T = add(div, UInt<1>(0h1)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 245:20] node _div_T_1 = tail(_div_T, 1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 245:20] connect div, _div_T_1 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 245:13] wire ctrl : UInt<32> @[hardware/soc/scala/fpga/VCU118Peripherals.scala 249:20] node ctrl_lo_hi = cat(quad, csn) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 250:16] node ctrl_lo = cat(ctrl_lo_hi, busy) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 250:16] node ctrl_hi_hi = cat(UInt<27>(0h0), cpha) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 250:16] node ctrl_hi = cat(ctrl_hi_hi, cpol) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 250:16] node _ctrl_T = cat(ctrl_hi, ctrl_lo) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 250:16] connect ctrl, _ctrl_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 250:10] node _T_2 = eq(busy, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 279:33] wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 73:18] node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 74:36] connect in.bits.read, _in_bits_read_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 74:19] node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 192:34] connect in.bits.index, _in_bits_index_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 75:19] connect in.bits.data, nodeIn.a.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 76:19] connect in.bits.mask, nodeIn.a.bits.mask @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 77:19] connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 83:20] connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 84:20] wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<6>, size : UInt<2>}}}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front.bits, in.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] inst out_back_front_q of Queue1_RegMapperInput_i9_m8_2 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_back_front_q.clock, clock connect out_back_front_q.reset, reset connect out_back_front_q.io.enq, out_front @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_maskMatch = not(UInt<9>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_findex = and(out_front.bits.index, out_maskMatch) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_bindex = and(out_back_front_q.io.deq.bits.index, out_maskMatch) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T = eq(out_findex, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_2 = eq(out_findex, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rivalid : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wivalid : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_roready : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_woready : UInt<1>[4] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T = bits(out_back_front_q.io.deq.bits.mask, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_1 = bits(out_back_front_q.io.deq.bits.mask, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_2 = bits(out_back_front_q.io.deq.bits.mask, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_3 = bits(out_back_front_q.io.deq.bits.mask, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_4 = bits(out_back_front_q.io.deq.bits.mask, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_5 = bits(out_back_front_q.io.deq.bits.mask, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_6 = bits(out_back_front_q.io.deq.bits.mask, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_7 = bits(out_back_front_q.io.deq.bits.mask, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backMask = cat(out_backMask_hi, out_backMask_lo) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask = orr(_out_rimask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask = andr(_out_wimask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask = orr(_out_romask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask = andr(_out_womask_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid = and(out_rivalid[0], out_rimask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready = and(out_roready[0], out_romask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid = and(out_wivalid[0], out_wimask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready = and(out_woready[0], out_womask) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_4 = bits(out_back_front_q.io.deq.bits.data, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_5 = eq(busy, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 253:21] node _out_T_6 = and(out_f_woready, _out_T_5) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 253:18] when _out_T_6 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 253:28] node _out_csn_T = bits(_out_T_4, 1, 1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 254:20] connect csn, _out_csn_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 254:13] node _out_quad_T = bits(_out_T_4, 2, 2) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 255:21] connect quad, _out_quad_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 255:14] node _out_cpol_T = bits(_out_T_4, 3, 3) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 256:21] connect cpol, _out_cpol_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 256:14] node _out_cpha_T = bits(_out_T_4, 4, 4) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 257:21] connect cpha, _out_cpha_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 257:14] node _out_sck_T = bits(_out_T_4, 3, 3) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 258:20] connect sck, _out_sck_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 258:13] node _out_T_7 = and(out_f_rivalid, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_8 = and(UInt<1>(0h1), out_f_roready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_9 = and(out_f_wivalid, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_10 = and(UInt<1>(0h1), out_f_woready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_11 = eq(out_rimask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_12 = eq(out_wimask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_13 = eq(out_romask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_14 = eq(out_womask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_15 = or(ctrl, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_16 = bits(_out_T_15, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_1 = bits(out_frontMask, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_1 = orr(_out_rimask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_1 = bits(out_frontMask, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_1 = andr(_out_wimask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_1 = bits(out_backMask, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_1 = orr(_out_romask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_1 = bits(out_backMask, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_1 = andr(_out_womask_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_1 = and(out_roready[1], out_romask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_1 = and(out_woready[1], out_womask_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_17 = bits(out_back_front_q.io.deq.bits.data, 63, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_18 = eq(busy, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 264:21] node _out_T_19 = and(out_f_woready_1, _out_T_18) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 264:18] when _out_T_19 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 264:28] connect txShift, _out_T_17 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 265:17] connect rxShift, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 266:17] node _out_bitsLeft_T = mux(quad, UInt<6>(0h20), UInt<4>(0h8)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 267:24] connect bitsLeft, _out_bitsLeft_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 267:18] connect busy, UInt<1>(0h1) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 268:14] connect div, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 269:13] connect sck, cpol @[hardware/soc/scala/fpga/VCU118Peripherals.scala 270:13] node _out_T_20 = and(out_f_wivalid_1, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_21 = and(UInt<1>(0h1), out_f_woready_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_22 = eq(out_rimask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_23 = eq(out_wimask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_24 = eq(out_romask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_25 = eq(out_womask_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T = or(_out_T_16, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend = cat(UInt<1>(0h0), _out_prepend_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_26 = or(out_prepend, UInt<64>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_27 = bits(_out_T_26, 63, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_2 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_2 = orr(_out_rimask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_2 = bits(out_frontMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_2 = andr(_out_wimask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_2 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_2 = orr(_out_romask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_2 = bits(out_backMask, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_2 = andr(_out_womask_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_2 = and(out_roready[2], out_romask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_2 = and(out_woready[2], out_womask_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_28 = bits(out_back_front_q.io.deq.bits.data, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_29 = and(out_f_rivalid_2, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_30 = and(UInt<1>(0h1), out_f_roready_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_31 = eq(out_rimask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_32 = eq(out_wimask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_33 = eq(out_romask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_34 = eq(out_womask_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_35 = or(rxShift, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_36 = bits(_out_T_35, 31, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rimask_T_3 = bits(out_frontMask, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_rimask_3 = orr(_out_rimask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wimask_T_3 = bits(out_frontMask, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_wimask_3 = andr(_out_wimask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_romask_T_3 = bits(out_backMask, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_romask_3 = orr(_out_romask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_womask_T_3 = bits(out_backMask, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_womask_3 = andr(_out_womask_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_roready_3 = and(out_roready[3], out_romask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_f_woready_3 = and(out_woready[3], out_womask_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_37 = bits(out_back_front_q.io.deq.bits.data, 32, 32) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_38 = and(out_f_rivalid_3, UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_39 = and(UInt<1>(0h1), out_f_roready_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_40 = eq(out_rimask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_41 = eq(out_wimask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_42 = eq(out_romask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_43 = eq(out_womask_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_prepend_T_1 = or(_out_T_36, UInt<32>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_prepend_1 = cat(_T_2, _out_prepend_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_44 = or(out_prepend_1, UInt<33>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_T_45 = bits(_out_T_44, 32, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_iindex = bits(out_front.bits.index, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T = bits(out_front.bits.index, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_1 = bits(out_front.bits.index, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_2 = bits(out_front.bits.index, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_3 = bits(out_front.bits.index, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_4 = bits(out_front.bits.index, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_5 = bits(out_front.bits.index, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_6 = bits(out_front.bits.index, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_iindex_T_7 = bits(out_front.bits.index, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oindex = bits(out_back_front_q.io.deq.bits.index, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T = bits(out_back_front_q.io.deq.bits.index, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_1 = bits(out_back_front_q.io.deq.bits.index, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_2 = bits(out_back_front_q.io.deq.bits.index, 3, 3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_3 = bits(out_back_front_q.io.deq.bits.index, 4, 4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_4 = bits(out_back_front_q.io.deq.bits.index, 5, 5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_5 = bits(out_back_front_q.io.deq.bits.index, 6, 6) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_6 = bits(out_back_front_q.io.deq.bits.index, 7, 7) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_oindex_T_7 = bits(out_back_front_q.io.deq.bits.index, 8, 8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) @[src/main/scala/chisel3/util/OneHot.scala 58:35] node out_backSel_0 = bits(_out_backSel_T, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_backSel_1 = bits(_out_backSel_T, 1, 1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T = and(in.valid, out_front.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[1], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[0], _out_rifireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rifireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rifireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[3], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_rivalid[2], _out_rifireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rifireMux_T_10 = geq(out_iindex, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_rifireMux_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_rifireMux = mux(_out_rifireMux_T_10, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_wifireMux_T = and(in.valid, out_front.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[1], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[0], _out_wifireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wifireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wifireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[3], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_wivalid[2], _out_wifireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wifireMux_T_11 = geq(out_iindex, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_wifireMux_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_wifireMux = mux(_out_wifireMux_T_11, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_rofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_back_front_q.io.deq.bits.read) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[1], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[0], _out_rofireMux_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_rofireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_rofireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[3], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_roready[2], _out_rofireMux_T_7 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_rofireMux_T_10 = geq(out_oindex, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_rofireMux_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_rofireMux = mux(_out_rofireMux_T_10, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_wofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_1 = eq(out_back_front_q.io.deq.bits.read, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[1], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[0], _out_wofireMux_T_4 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] wire out_wofireMux_out_1 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_wofireMux_out_1, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[3], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] connect out_woready[2], _out_wofireMux_T_8 @[hardware/upstream/rocket-chip/src/main/scala/util/ReduceOthers.scala 39:69] node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_wofireMux_T_11 = geq(out_oindex, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_wofireMux_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node out_wofireMux = mux(_out_wofireMux_T_11, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node out_oready = mux(out_back_front_q.io.deq.bits.read, out_rofireMux, out_wofireMux) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_in_ready_T = and(out_front.ready, out_iready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect in.ready, _out_in_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_front_valid_T = and(in.valid, out_iready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_front.valid, _out_front_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_front_q_io_deq_ready_T = and(out.ready, out_oready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out_back_front_q.io.deq.ready, _out_front_q_io_deq_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_out_valid_T = and(out_back_front_q.io.deq.valid, out_oready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.valid, _out_out_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.read, out_back_front_q.io.deq.bits.read @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] node _out_out_bits_data_T = geq(out_oindex, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_out_bits_data_WIRE : UInt<1>[2] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[0], _out_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE[1], _out_T_3 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_out_bits_data_T_2 = geq(out_oindex, UInt<2>(0h2)) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:17] wire _out_out_bits_data_WIRE_1 : UInt<64>[2] @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[0], _out_T_27 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] connect _out_out_bits_data_WIRE_1[1], _out_T_45 @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:48] node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) @[hardware/upstream/rocket-chip/src/main/scala/util/MuxLiteral.scala 49:10] node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.data, _out_out_bits_data_T_4 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect out.bits.extra, out_back_front_q.io.deq.bits.extra @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 87:24] connect in.valid, nodeIn.a.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 90:15] connect nodeIn.a.ready, in.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 91:15] connect nodeIn.d.valid, out.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 92:15] connect out.ready, nodeIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 93:15] wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 792:17] connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 793:15] connect nodeIn_d_bits_d.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 794:15] connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 795:15] connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 796:15] connect nodeIn_d_bits_d.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 797:15] connect nodeIn_d_bits_d.denied, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 798:15] invalidate nodeIn_d_bits_d.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 801:15] connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 802:15] connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.data, nodeIn_d_bits_d.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.source, nodeIn_d_bits_d.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.size, nodeIn_d_bits_d.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.param, nodeIn_d_bits_d.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 97:12] connect nodeIn.d.bits.data, out.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 100:17] node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 105:25] connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 105:19] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<8>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 108:22] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<64>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<6>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 109:22] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/RegisterRouter.scala 110:22] module FPGAPMODSPIClockSinkDomain : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 14:9] output auto : { flip dev_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, dev_dq_oe_out : UInt<4>, dev_dq_out_out : UInt<4>, flip dev_dq_in_in : UInt<4>, dev_csn_out : UInt<1>, dev_sck_out : UInt<1>, flip clock_in : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 21:19] output reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 22:19] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] inst dev of TLFpgaSPI_1 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 653:34] connect dev.clock, childClock connect dev.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate clockNodeIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate clockNodeIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect clockNodeIn, auto.clock_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.dev_sck_out, dev.auto.sck_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.dev_csn_out, dev.auto.csn_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect dev.auto.dq_in_in, auto.dev_dq_in_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.dev_dq_out_out, dev.auto.dq_out_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect auto.dev_dq_oe_out, dev.auto.dq_oe_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect dev.auto.in, auto.dev_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect childClock, clockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 15:16] connect childReset, clockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 16:16] connect clock, clockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 23:11] connect reset, clockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 24:11] extmodule acq_wrapper : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 314:7] input PCLK : Clock input PRESETN : UInt<1> input PADDR : UInt<12> input PSEL : UInt<1> input PENABLE : UInt<1> input PWRITE : UInt<1> input PWDATA : UInt<32> output PREADY : UInt<1> output PRDATA : UInt<32> output PSLVERR : UInt<1> output afe_start : UInt<1> output sample_counter_clear : UInt<1> input clk_80mhz : Clock input rf_clk : Clock input acq_resetn : UInt<1> input afe_resetn : UInt<1> input rf_data : UInt<4> input sample_align : UInt<1> input start_acq_manuel : UInt<1> output acq_intr : UInt<1> defname = acq_wrapper parameter ADDR_BUS_WIDTH = 12 parameter DATA_BUS_WIDTH = 32 parameter HIGH_ADDRESS = 4095 parameter LOW_ADDRESS = 0 extmodule afe_top : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 405:7] input afe_rstn : UInt<1> input trk_rstn : UInt<1> input afe_clk : Clock input trk_clk : Clock input start_i : UInt<1> input sample_counter_clear_i : UInt<1> output sample_align_o : UInt<1> output sample_counter_o : UInt<32> output rf_data_o : UInt<4> defname = afe_top extmodule tracking_wrapper : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 346:7] input PCLK : Clock input PRESETN : UInt<1> input PADDR : UInt<12> input PSEL : UInt<1> input PENABLE : UInt<1> input PWRITE : UInt<1> input PWDATA : UInt<32> output PREADY : UInt<1> output PRDATA : UInt<32> output PSLVERR : UInt<1> input trck_resetn : UInt<1> input afe_resetn : UInt<1> input trck_clk : Clock input afe_clk : Clock input afe_data : UInt<4> input sample_align : UInt<1> input sample_counter : UInt<32> output gps_frame_ready : UInt<1> output pps_capture : UInt<1> defname = tracking_wrapper parameter ADDR_BUS_WIDTH = 12 parameter DATA_BUS_WIDTH = 32 parameter HIGH_ADDRESS = 4095 parameter LOW_ADDRESS = 0 extmodule tracking_wrapper_1 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 346:7] input PCLK : Clock input PRESETN : UInt<1> input PADDR : UInt<12> input PSEL : UInt<1> input PENABLE : UInt<1> input PWRITE : UInt<1> input PWDATA : UInt<32> output PREADY : UInt<1> output PRDATA : UInt<32> output PSLVERR : UInt<1> input trck_resetn : UInt<1> input afe_resetn : UInt<1> input trck_clk : Clock input afe_clk : Clock input afe_data : UInt<4> input sample_align : UInt<1> input sample_counter : UInt<32> output gps_frame_ready : UInt<1> output pps_capture : UInt<1> defname = tracking_wrapper parameter ADDR_BUS_WIDTH = 12 parameter DATA_BUS_WIDTH = 32 parameter HIGH_ADDRESS = 4095 parameter LOW_ADDRESS = 0 extmodule tracking_wrapper_2 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 346:7] input PCLK : Clock input PRESETN : UInt<1> input PADDR : UInt<12> input PSEL : UInt<1> input PENABLE : UInt<1> input PWRITE : UInt<1> input PWDATA : UInt<32> output PREADY : UInt<1> output PRDATA : UInt<32> output PSLVERR : UInt<1> input trck_resetn : UInt<1> input afe_resetn : UInt<1> input trck_clk : Clock input afe_clk : Clock input afe_data : UInt<4> input sample_align : UInt<1> input sample_counter : UInt<32> output gps_frame_ready : UInt<1> output pps_capture : UInt<1> defname = tracking_wrapper parameter ADDR_BUS_WIDTH = 12 parameter DATA_BUS_WIDTH = 32 parameter HIGH_ADDRESS = 4095 parameter LOW_ADDRESS = 0 extmodule tracking_wrapper_3 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 346:7] input PCLK : Clock input PRESETN : UInt<1> input PADDR : UInt<12> input PSEL : UInt<1> input PENABLE : UInt<1> input PWRITE : UInt<1> input PWDATA : UInt<32> output PREADY : UInt<1> output PRDATA : UInt<32> output PSLVERR : UInt<1> input trck_resetn : UInt<1> input afe_resetn : UInt<1> input trck_clk : Clock input afe_clk : Clock input afe_data : UInt<4> input sample_align : UInt<1> input sample_counter : UInt<32> output gps_frame_ready : UInt<1> output pps_capture : UInt<1> defname = tracking_wrapper parameter ADDR_BUS_WIDTH = 12 parameter DATA_BUS_WIDTH = 32 parameter HIGH_ADDRESS = 4095 parameter LOW_ADDRESS = 0 extmodule tracking_wrapper_4 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 346:7] input PCLK : Clock input PRESETN : UInt<1> input PADDR : UInt<12> input PSEL : UInt<1> input PENABLE : UInt<1> input PWRITE : UInt<1> input PWDATA : UInt<32> output PREADY : UInt<1> output PRDATA : UInt<32> output PSLVERR : UInt<1> input trck_resetn : UInt<1> input afe_resetn : UInt<1> input trck_clk : Clock input afe_clk : Clock input afe_data : UInt<4> input sample_align : UInt<1> input sample_counter : UInt<32> output gps_frame_ready : UInt<1> output pps_capture : UInt<1> defname = tracking_wrapper parameter ADDR_BUS_WIDTH = 12 parameter DATA_BUS_WIDTH = 32 parameter HIGH_ADDRESS = 4095 parameter LOW_ADDRESS = 0 extmodule tracking_wrapper_5 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 346:7] input PCLK : Clock input PRESETN : UInt<1> input PADDR : UInt<12> input PSEL : UInt<1> input PENABLE : UInt<1> input PWRITE : UInt<1> input PWDATA : UInt<32> output PREADY : UInt<1> output PRDATA : UInt<32> output PSLVERR : UInt<1> input trck_resetn : UInt<1> input afe_resetn : UInt<1> input trck_clk : Clock input afe_clk : Clock input afe_data : UInt<4> input sample_align : UInt<1> input sample_counter : UInt<32> output gps_frame_ready : UInt<1> output pps_capture : UInt<1> defname = tracking_wrapper parameter ADDR_BUS_WIDTH = 12 parameter DATA_BUS_WIDTH = 32 parameter HIGH_ADDRESS = 4095 parameter LOW_ADDRESS = 0 extmodule tracking_wrapper_6 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 346:7] input PCLK : Clock input PRESETN : UInt<1> input PADDR : UInt<12> input PSEL : UInt<1> input PENABLE : UInt<1> input PWRITE : UInt<1> input PWDATA : UInt<32> output PREADY : UInt<1> output PRDATA : UInt<32> output PSLVERR : UInt<1> input trck_resetn : UInt<1> input afe_resetn : UInt<1> input trck_clk : Clock input afe_clk : Clock input afe_data : UInt<4> input sample_align : UInt<1> input sample_counter : UInt<32> output gps_frame_ready : UInt<1> output pps_capture : UInt<1> defname = tracking_wrapper parameter ADDR_BUS_WIDTH = 12 parameter DATA_BUS_WIDTH = 32 parameter HIGH_ADDRESS = 4095 parameter LOW_ADDRESS = 0 extmodule tracking_wrapper_7 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 346:7] input PCLK : Clock input PRESETN : UInt<1> input PADDR : UInt<12> input PSEL : UInt<1> input PENABLE : UInt<1> input PWRITE : UInt<1> input PWDATA : UInt<32> output PREADY : UInt<1> output PRDATA : UInt<32> output PSLVERR : UInt<1> input trck_resetn : UInt<1> input afe_resetn : UInt<1> input trck_clk : Clock input afe_clk : Clock input afe_data : UInt<4> input sample_align : UInt<1> input sample_counter : UInt<32> output gps_frame_ready : UInt<1> output pps_capture : UInt<1> defname = tracking_wrapper parameter ADDR_BUS_WIDTH = 12 parameter DATA_BUS_WIDTH = 32 parameter HIGH_ADDRESS = 4095 parameter LOW_ADDRESS = 0 extmodule tracking_wrapper_8 : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 346:7] input PCLK : Clock input PRESETN : UInt<1> input PADDR : UInt<12> input PSEL : UInt<1> input PENABLE : UInt<1> input PWRITE : UInt<1> input PWDATA : UInt<32> output PREADY : UInt<1> output PRDATA : UInt<32> output PSLVERR : UInt<1> input trck_resetn : UInt<1> input afe_resetn : UInt<1> input trck_clk : Clock input afe_clk : Clock input afe_data : UInt<4> input sample_align : UInt<1> input sample_counter : UInt<32> output gps_frame_ready : UInt<1> output pps_capture : UInt<1> defname = tracking_wrapper parameter ADDR_BUS_WIDTH = 12 parameter DATA_BUS_WIDTH = 32 parameter HIGH_ADDRESS = 4095 parameter LOW_ADDRESS = 0 extmodule pps_wrapper : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 377:7] input PCLK : Clock input PRESETN : UInt<1> input PADDR : UInt<12> input PSEL : UInt<1> input PENABLE : UInt<1> input PWRITE : UInt<1> input PWDATA : UInt<32> output PREADY : UInt<1> output PRDATA : UInt<32> output PSLVERR : UInt<1> input pps_clk : Clock input pps_resetn : UInt<1> input capture_i : UInt<9> output pps_out : UInt<1> output pps_valid : UInt<1> defname = pps_wrapper parameter ADDR_BUS_WIDTH = 12 parameter DATA_BUS_WIDTH = 32 parameter HIGH_ADDRESS = 4095 parameter LOW_ADDRESS = 0 parameter NUM_CAPTURE_CHANNELS = 9 module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_33 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_33 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_33 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module ResetCatchAndSync_d3 : @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 13:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 13:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 13:7] output io : { sync_reset : UInt<1>, flip psd : { test_mode : UInt<1>, test_mode_reset : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 17:14] node _post_psd_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 26:76] node post_psd_reset = mux(io.psd.test_mode, io.psd.test_mode_reset, _post_psd_reset_T) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 26:27] inst io_sync_reset_chain of AsyncResetSynchronizerShiftReg_w1_d3_i0_33 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_sync_reset_chain.clock, clock connect io_sync_reset_chain.reset, post_psd_reset connect io_sync_reset_chain.io.d, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_sync_reset_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_sync_reset_WIRE, io_sync_reset_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] node _io_sync_reset_T = not(_io_sync_reset_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 29:7] node _io_sync_reset_T_1 = mux(io.psd.test_mode, io.psd.test_mode_reset, _io_sync_reset_T) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 28:25] connect io.sync_reset, _io_sync_reset_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 28:19] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_34 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_34 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_34 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module ResetCatchAndSync_d3_1 : @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 13:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 13:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 13:7] output io : { sync_reset : UInt<1>, flip psd : { test_mode : UInt<1>, test_mode_reset : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 17:14] node _post_psd_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 26:76] node post_psd_reset = mux(io.psd.test_mode, io.psd.test_mode_reset, _post_psd_reset_T) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 26:27] inst io_sync_reset_chain of AsyncResetSynchronizerShiftReg_w1_d3_i0_34 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_sync_reset_chain.clock, clock connect io_sync_reset_chain.reset, post_psd_reset connect io_sync_reset_chain.io.d, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_sync_reset_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_sync_reset_WIRE, io_sync_reset_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] node _io_sync_reset_T = not(_io_sync_reset_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 29:7] node _io_sync_reset_T_1 = mux(io.psd.test_mode, io.psd.test_mode_reset, _io_sync_reset_T) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 28:25] connect io.sync_reset, _io_sync_reset_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 28:19] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_35 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_35 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module ResetCatchAndSync_d3_2 : @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 13:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 13:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 13:7] output io : { sync_reset : UInt<1>, flip psd : { test_mode : UInt<1>, test_mode_reset : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 17:14] node _post_psd_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 26:76] node post_psd_reset = mux(io.psd.test_mode, io.psd.test_mode_reset, _post_psd_reset_T) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 26:27] inst io_sync_reset_chain of AsyncResetSynchronizerShiftReg_w1_d3_i0_35 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_sync_reset_chain.clock, clock connect io_sync_reset_chain.reset, post_psd_reset connect io_sync_reset_chain.io.d, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_sync_reset_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_sync_reset_WIRE, io_sync_reset_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] node _io_sync_reset_T = not(_io_sync_reset_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 29:7] node _io_sync_reset_T_1 = mux(io.psd.test_mode, io.psd.test_mode_reset, _io_sync_reset_T) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 28:25] connect io.sync_reset, _io_sync_reset_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 28:19] module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_36 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] input reset : AsyncReset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 68:19] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 51:87] node _sync_2_T = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:22] connect sync_2, _sync_2_T @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 54:14] connect sync_0, sync_1 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect sync_1, sync_2 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 57:10] connect io.q, sync_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 59:8] module AsyncResetSynchronizerShiftReg_w1_d3_i0_36 : @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 80:7] output io : { flip d : UInt<1>, q : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 36:14] node _output_T = asAsyncReset(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 86:21] node _output_T_1 = bits(io.d, 0, 0) @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 87:41] inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire output_0 : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect output_0, output_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect io.q, output_0 @[hardware/upstream/rocket-chip/src/main/scala/util/SynchronizerReg.scala 90:8] module ResetCatchAndSync_d3_3 : @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 13:7] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 13:7] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 13:7] output io : { sync_reset : UInt<1>, flip psd : { test_mode : UInt<1>, test_mode_reset : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 17:14] node _post_psd_reset_T = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 26:76] node post_psd_reset = mux(io.psd.test_mode, io.psd.test_mode_reset, _post_psd_reset_T) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 26:27] inst io_sync_reset_chain of AsyncResetSynchronizerShiftReg_w1_d3_i0_36 @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 45:23] connect io_sync_reset_chain.clock, clock connect io_sync_reset_chain.reset, post_psd_reset connect io_sync_reset_chain.io.d, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 47:16] wire _io_sync_reset_WIRE : UInt<1> @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] connect _io_sync_reset_WIRE, io_sync_reset_chain.io.q @[hardware/upstream/rocket-chip/src/main/scala/util/ShiftReg.scala 48:24] node _io_sync_reset_T = not(_io_sync_reset_WIRE) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 29:7] node _io_sync_reset_T_1 = mux(io.psd.test_mode, io.psd.test_mode_reset, _io_sync_reset_T) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 28:25] connect io.sync_reset, _io_sync_reset_T_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 28:19] module APBGpsBlock : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 455:9] input clock : Clock @[hardware/soc/scala/fpga/VCU118Peripherals.scala 455:9] input reset : Reset @[hardware/soc/scala/fpga/VCU118Peripherals.scala 455:9] output auto : { pps_out_out : UInt<1>, flip rf_data_in : UInt<4>, flip afe_clock_in : Clock, flip tracking_clock_in : Clock, flip acq_clock_in : Clock, flip in : { psel : UInt<1>, penable : UInt<1>, pwrite : UInt<1>, paddr : UInt<29>, pprot : UInt<3>, pwdata : UInt<32>, pstrb : UInt<4>, pauser : { }, flip pready : UInt<1>, flip pslverr : UInt<1>, flip prdata : UInt<32>, pduser : { }}, int_out : UInt<1>[10]} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire intnodeOut : UInt<1>[10] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate intnodeOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate intnodeOut[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate intnodeOut[2] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate intnodeOut[3] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate intnodeOut[4] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate intnodeOut[5] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate intnodeOut[6] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate intnodeOut[7] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate intnodeOut[8] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate intnodeOut[9] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire nodeIn : { psel : UInt<1>, penable : UInt<1>, pwrite : UInt<1>, paddr : UInt<29>, pprot : UInt<3>, pwdata : UInt<32>, pstrb : UInt<4>, pauser : { }, flip pready : UInt<1>, flip pslverr : UInt<1>, flip prdata : UInt<32>, pduser : { }} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.prdata @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.pslverr @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.pready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.pstrb @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.pwdata @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.pprot @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.paddr @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.pwrite @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.penable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.psel @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire acqClockNodeIn : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate acqClockNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire trackingClockNodeIn : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate trackingClockNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire afeClockNodeIn : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate afeClockNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire rfDataNodeIn : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate rfDataNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire ppsOutNodeOut : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate ppsOutNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.int_out, intnodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect acqClockNodeIn, auto.acq_clock_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect trackingClockNodeIn, auto.tracking_clock_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect afeClockNodeIn, auto.afe_clock_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect rfDataNodeIn, auto.rf_data_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.pps_out_out, ppsOutNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] inst acq of acq_wrapper @[hardware/soc/scala/fpga/VCU118Peripherals.scala 457:21] inst afe of afe_top @[hardware/soc/scala/fpga/VCU118Peripherals.scala 458:21] inst tracking_0 of tracking_wrapper @[hardware/soc/scala/fpga/VCU118Peripherals.scala 459:66] inst tracking_1 of tracking_wrapper_1 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 459:66] inst tracking_2 of tracking_wrapper_2 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 459:66] inst tracking_3 of tracking_wrapper_3 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 459:66] inst tracking_4 of tracking_wrapper_4 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 459:66] inst tracking_5 of tracking_wrapper_5 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 459:66] inst tracking_6 of tracking_wrapper_6 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 459:66] inst tracking_7 of tracking_wrapper_7 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 459:66] inst tracking_8 of tracking_wrapper_8 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 459:66] inst pps of pps_wrapper @[hardware/soc/scala/fpga/VCU118Peripherals.scala 460:21] node localAddr = bits(nodeIn.paddr, 11, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 461:30] node _sel_T = xor(nodeIn.paddr, UInt<29>(0h10020000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _sel_T_1 = cvt(_sel_T) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _sel_T_2 = and(_sel_T_1, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_3 = asSInt(_sel_T_2) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_4 = eq(_sel_T_3, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _sel_T_5 = xor(nodeIn.paddr, UInt<29>(0h10021000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _sel_T_6 = cvt(_sel_T_5) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _sel_T_7 = and(_sel_T_6, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_8 = asSInt(_sel_T_7) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_9 = eq(_sel_T_8, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _sel_T_10 = xor(nodeIn.paddr, UInt<29>(0h10022000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _sel_T_11 = cvt(_sel_T_10) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _sel_T_12 = and(_sel_T_11, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_13 = asSInt(_sel_T_12) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_14 = eq(_sel_T_13, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _sel_T_15 = xor(nodeIn.paddr, UInt<29>(0h10023000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _sel_T_16 = cvt(_sel_T_15) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _sel_T_17 = and(_sel_T_16, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_18 = asSInt(_sel_T_17) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_19 = eq(_sel_T_18, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _sel_T_20 = xor(nodeIn.paddr, UInt<29>(0h10024000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _sel_T_21 = cvt(_sel_T_20) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _sel_T_22 = and(_sel_T_21, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_23 = asSInt(_sel_T_22) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_24 = eq(_sel_T_23, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _sel_T_25 = xor(nodeIn.paddr, UInt<29>(0h10025000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _sel_T_26 = cvt(_sel_T_25) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _sel_T_27 = and(_sel_T_26, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_28 = asSInt(_sel_T_27) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_29 = eq(_sel_T_28, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _sel_T_30 = xor(nodeIn.paddr, UInt<29>(0h10026000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _sel_T_31 = cvt(_sel_T_30) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _sel_T_32 = and(_sel_T_31, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_33 = asSInt(_sel_T_32) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_34 = eq(_sel_T_33, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _sel_T_35 = xor(nodeIn.paddr, UInt<29>(0h10027000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _sel_T_36 = cvt(_sel_T_35) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _sel_T_37 = and(_sel_T_36, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_38 = asSInt(_sel_T_37) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_39 = eq(_sel_T_38, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _sel_T_40 = xor(nodeIn.paddr, UInt<29>(0h10028000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _sel_T_41 = cvt(_sel_T_40) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _sel_T_42 = and(_sel_T_41, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_43 = asSInt(_sel_T_42) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_44 = eq(_sel_T_43, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _sel_T_45 = xor(nodeIn.paddr, UInt<29>(0h10029000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _sel_T_46 = cvt(_sel_T_45) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _sel_T_47 = and(_sel_T_46, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_48 = asSInt(_sel_T_47) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_49 = eq(_sel_T_48, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] node _sel_T_50 = xor(nodeIn.paddr, UInt<29>(0h1002a000)) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:31] node _sel_T_51 = cvt(_sel_T_50) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:41] node _sel_T_52 = and(_sel_T_51, asSInt(UInt<13>(0h1000))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_53 = asSInt(_sel_T_52) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:46] node _sel_T_54 = eq(_sel_T_53, asSInt(UInt<1>(0h0))) @[hardware/upstream/rocket-chip/src/main/scala/diplomacy/Parameters.scala 139:59] wire sel : UInt<1>[11] @[hardware/soc/scala/fpga/VCU118Peripherals.scala 462:22] connect sel[0], _sel_T_4 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 462:22] connect sel[1], _sel_T_9 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 462:22] connect sel[2], _sel_T_14 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 462:22] connect sel[3], _sel_T_19 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 462:22] connect sel[4], _sel_T_24 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 462:22] connect sel[5], _sel_T_29 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 462:22] connect sel[6], _sel_T_34 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 462:22] connect sel[7], _sel_T_39 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 462:22] connect sel[8], _sel_T_44 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 462:22] connect sel[9], _sel_T_49 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 462:22] connect sel[10], _sel_T_54 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 462:22] node hit_lo_lo = cat(sel[1], sel[0]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 463:19] node hit_lo_hi_hi = cat(sel[4], sel[3]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 463:19] node hit_lo_hi = cat(hit_lo_hi_hi, sel[2]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 463:19] node hit_lo = cat(hit_lo_hi, hit_lo_lo) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 463:19] node hit_hi_lo_hi = cat(sel[7], sel[6]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 463:19] node hit_hi_lo = cat(hit_hi_lo_hi, sel[5]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 463:19] node hit_hi_hi_hi = cat(sel[10], sel[9]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 463:19] node hit_hi_hi = cat(hit_hi_hi_hi, sel[8]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 463:19] node hit_hi = cat(hit_hi_hi, hit_hi_lo) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 463:19] node _hit_T = cat(hit_hi, hit_lo) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 463:19] node hit = orr(_hit_T) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 463:26] node _apbReset_T = asUInt(reset) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 467:51] inst apbReset_gps_apb_reset of ResetCatchAndSync_d3 @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 39:28] connect apbReset_gps_apb_reset.clock, clock connect apbReset_gps_apb_reset.reset, _apbReset_T wire _apbReset_gps_apb_reset_io_psd_WIRE : { test_mode : UInt<1>, test_mode_reset : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:63] connect _apbReset_gps_apb_reset_io_psd_WIRE.test_mode_reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:63] connect _apbReset_gps_apb_reset_io_psd_WIRE.test_mode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:63] wire _apbReset_gps_apb_reset_io_psd_WIRE_1 : { test_mode : UInt<1>, test_mode_reset : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:50] connect _apbReset_gps_apb_reset_io_psd_WIRE_1, _apbReset_gps_apb_reset_io_psd_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:50] connect apbReset_gps_apb_reset.io.psd, _apbReset_gps_apb_reset_io_psd_WIRE_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:22] node _acqReset_T = asUInt(reset) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 468:65] inst acqReset_gps_acq_reset of ResetCatchAndSync_d3_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 39:28] connect acqReset_gps_acq_reset.clock, acqClockNodeIn connect acqReset_gps_acq_reset.reset, _acqReset_T wire _acqReset_gps_acq_reset_io_psd_WIRE : { test_mode : UInt<1>, test_mode_reset : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:63] connect _acqReset_gps_acq_reset_io_psd_WIRE.test_mode_reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:63] connect _acqReset_gps_acq_reset_io_psd_WIRE.test_mode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:63] wire _acqReset_gps_acq_reset_io_psd_WIRE_1 : { test_mode : UInt<1>, test_mode_reset : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:50] connect _acqReset_gps_acq_reset_io_psd_WIRE_1, _acqReset_gps_acq_reset_io_psd_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:50] connect acqReset_gps_acq_reset.io.psd, _acqReset_gps_acq_reset_io_psd_WIRE_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:22] node _trckReset_T = asUInt(reset) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 469:71] inst trckReset_gps_trck_reset of ResetCatchAndSync_d3_2 @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 39:28] connect trckReset_gps_trck_reset.clock, trackingClockNodeIn connect trckReset_gps_trck_reset.reset, _trckReset_T wire _trckReset_gps_trck_reset_io_psd_WIRE : { test_mode : UInt<1>, test_mode_reset : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:63] connect _trckReset_gps_trck_reset_io_psd_WIRE.test_mode_reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:63] connect _trckReset_gps_trck_reset_io_psd_WIRE.test_mode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:63] wire _trckReset_gps_trck_reset_io_psd_WIRE_1 : { test_mode : UInt<1>, test_mode_reset : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:50] connect _trckReset_gps_trck_reset_io_psd_WIRE_1, _trckReset_gps_trck_reset_io_psd_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:50] connect trckReset_gps_trck_reset.io.psd, _trckReset_gps_trck_reset_io_psd_WIRE_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:22] node _afeReset_T = asUInt(reset) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 470:65] inst afeReset_gps_afe_reset of ResetCatchAndSync_d3_3 @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 39:28] connect afeReset_gps_afe_reset.clock, afeClockNodeIn connect afeReset_gps_afe_reset.reset, _afeReset_T wire _afeReset_gps_afe_reset_io_psd_WIRE : { test_mode : UInt<1>, test_mode_reset : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:63] connect _afeReset_gps_afe_reset_io_psd_WIRE.test_mode_reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:63] connect _afeReset_gps_afe_reset_io_psd_WIRE.test_mode, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:63] wire _afeReset_gps_afe_reset_io_psd_WIRE_1 : { test_mode : UInt<1>, test_mode_reset : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:50] connect _afeReset_gps_afe_reset_io_psd_WIRE_1, _afeReset_gps_afe_reset_io_psd_WIRE @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:50] connect afeReset_gps_afe_reset.io.psd, _afeReset_gps_afe_reset_io_psd_WIRE_1 @[hardware/upstream/rocket-chip/src/main/scala/util/ResetCatchAndSync.scala 41:22] node apbResetn = eq(apbReset_gps_apb_reset.io.sync_reset, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 472:21] node acqResetn = eq(acqReset_gps_acq_reset.io.sync_reset, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 473:21] node trckResetn = eq(trckReset_gps_trck_reset.io.sync_reset, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 474:22] node afeResetn = eq(afeReset_gps_afe_reset.io.sync_reset, UInt<1>(0h0)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 475:21] connect afe.afe_rstn, afeResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 477:21] connect afe.trk_rstn, trckResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 478:21] connect afe.afe_clk, afeClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 479:20] connect afe.trk_clk, trackingClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 480:20] connect afe.start_i, acq.afe_start @[hardware/soc/scala/fpga/VCU118Peripherals.scala 481:20] connect afe.sample_counter_clear_i, acq.sample_counter_clear @[hardware/soc/scala/fpga/VCU118Peripherals.scala 482:35] connect acq.PCLK, clock @[hardware/soc/scala/fpga/VCU118Peripherals.scala 484:17] connect acq.PRESETN, apbResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 485:20] connect acq.PADDR, localAddr @[hardware/soc/scala/fpga/VCU118Peripherals.scala 486:18] node _acq_io_PSEL_T = and(nodeIn.psel, sel[0]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 487:29] connect acq.PSEL, _acq_io_PSEL_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 487:17] connect acq.PENABLE, nodeIn.penable @[hardware/soc/scala/fpga/VCU118Peripherals.scala 488:20] connect acq.PWRITE, nodeIn.pwrite @[hardware/soc/scala/fpga/VCU118Peripherals.scala 489:19] node _acq_io_PWDATA_T = bits(nodeIn.pwdata, 31, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 490:32] connect acq.PWDATA, _acq_io_PWDATA_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 490:19] connect acq.clk_80mhz, acqClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 492:22] connect acq.rf_clk, afeClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 493:19] connect acq.acq_resetn, acqResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 494:23] connect acq.afe_resetn, afeResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 495:23] connect acq.rf_data, rfDataNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 496:20] connect acq.sample_align, afe.sample_align_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 497:25] connect acq.start_acq_manuel, UInt<1>(0h0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 498:29] connect tracking_0.PCLK, clock @[hardware/soc/scala/fpga/VCU118Peripherals.scala 501:20] connect tracking_0.PRESETN, apbResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 502:23] connect tracking_0.PADDR, localAddr @[hardware/soc/scala/fpga/VCU118Peripherals.scala 503:21] node _tracking_0_io_PSEL_T = and(nodeIn.psel, sel[1]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 504:32] connect tracking_0.PSEL, _tracking_0_io_PSEL_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 504:20] connect tracking_0.PENABLE, nodeIn.penable @[hardware/soc/scala/fpga/VCU118Peripherals.scala 505:23] connect tracking_0.PWRITE, nodeIn.pwrite @[hardware/soc/scala/fpga/VCU118Peripherals.scala 506:22] node _tracking_0_io_PWDATA_T = bits(nodeIn.pwdata, 31, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 507:35] connect tracking_0.PWDATA, _tracking_0_io_PWDATA_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 507:22] connect tracking_0.trck_resetn, trckResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 509:27] connect tracking_0.afe_resetn, afeResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 510:26] connect tracking_0.trck_clk, trackingClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 511:24] connect tracking_0.afe_clk, afeClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 512:23] connect tracking_0.afe_data, rfDataNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 513:24] connect tracking_0.sample_align, afe.sample_align_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 514:28] connect tracking_0.sample_counter, afe.sample_counter_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 515:30] connect tracking_1.PCLK, clock @[hardware/soc/scala/fpga/VCU118Peripherals.scala 501:20] connect tracking_1.PRESETN, apbResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 502:23] connect tracking_1.PADDR, localAddr @[hardware/soc/scala/fpga/VCU118Peripherals.scala 503:21] node _tracking_1_io_PSEL_T = and(nodeIn.psel, sel[2]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 504:32] connect tracking_1.PSEL, _tracking_1_io_PSEL_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 504:20] connect tracking_1.PENABLE, nodeIn.penable @[hardware/soc/scala/fpga/VCU118Peripherals.scala 505:23] connect tracking_1.PWRITE, nodeIn.pwrite @[hardware/soc/scala/fpga/VCU118Peripherals.scala 506:22] node _tracking_1_io_PWDATA_T = bits(nodeIn.pwdata, 31, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 507:35] connect tracking_1.PWDATA, _tracking_1_io_PWDATA_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 507:22] connect tracking_1.trck_resetn, trckResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 509:27] connect tracking_1.afe_resetn, afeResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 510:26] connect tracking_1.trck_clk, trackingClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 511:24] connect tracking_1.afe_clk, afeClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 512:23] connect tracking_1.afe_data, rfDataNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 513:24] connect tracking_1.sample_align, afe.sample_align_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 514:28] connect tracking_1.sample_counter, afe.sample_counter_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 515:30] connect tracking_2.PCLK, clock @[hardware/soc/scala/fpga/VCU118Peripherals.scala 501:20] connect tracking_2.PRESETN, apbResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 502:23] connect tracking_2.PADDR, localAddr @[hardware/soc/scala/fpga/VCU118Peripherals.scala 503:21] node _tracking_2_io_PSEL_T = and(nodeIn.psel, sel[3]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 504:32] connect tracking_2.PSEL, _tracking_2_io_PSEL_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 504:20] connect tracking_2.PENABLE, nodeIn.penable @[hardware/soc/scala/fpga/VCU118Peripherals.scala 505:23] connect tracking_2.PWRITE, nodeIn.pwrite @[hardware/soc/scala/fpga/VCU118Peripherals.scala 506:22] node _tracking_2_io_PWDATA_T = bits(nodeIn.pwdata, 31, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 507:35] connect tracking_2.PWDATA, _tracking_2_io_PWDATA_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 507:22] connect tracking_2.trck_resetn, trckResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 509:27] connect tracking_2.afe_resetn, afeResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 510:26] connect tracking_2.trck_clk, trackingClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 511:24] connect tracking_2.afe_clk, afeClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 512:23] connect tracking_2.afe_data, rfDataNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 513:24] connect tracking_2.sample_align, afe.sample_align_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 514:28] connect tracking_2.sample_counter, afe.sample_counter_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 515:30] connect tracking_3.PCLK, clock @[hardware/soc/scala/fpga/VCU118Peripherals.scala 501:20] connect tracking_3.PRESETN, apbResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 502:23] connect tracking_3.PADDR, localAddr @[hardware/soc/scala/fpga/VCU118Peripherals.scala 503:21] node _tracking_3_io_PSEL_T = and(nodeIn.psel, sel[4]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 504:32] connect tracking_3.PSEL, _tracking_3_io_PSEL_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 504:20] connect tracking_3.PENABLE, nodeIn.penable @[hardware/soc/scala/fpga/VCU118Peripherals.scala 505:23] connect tracking_3.PWRITE, nodeIn.pwrite @[hardware/soc/scala/fpga/VCU118Peripherals.scala 506:22] node _tracking_3_io_PWDATA_T = bits(nodeIn.pwdata, 31, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 507:35] connect tracking_3.PWDATA, _tracking_3_io_PWDATA_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 507:22] connect tracking_3.trck_resetn, trckResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 509:27] connect tracking_3.afe_resetn, afeResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 510:26] connect tracking_3.trck_clk, trackingClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 511:24] connect tracking_3.afe_clk, afeClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 512:23] connect tracking_3.afe_data, rfDataNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 513:24] connect tracking_3.sample_align, afe.sample_align_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 514:28] connect tracking_3.sample_counter, afe.sample_counter_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 515:30] connect tracking_4.PCLK, clock @[hardware/soc/scala/fpga/VCU118Peripherals.scala 501:20] connect tracking_4.PRESETN, apbResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 502:23] connect tracking_4.PADDR, localAddr @[hardware/soc/scala/fpga/VCU118Peripherals.scala 503:21] node _tracking_4_io_PSEL_T = and(nodeIn.psel, sel[5]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 504:32] connect tracking_4.PSEL, _tracking_4_io_PSEL_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 504:20] connect tracking_4.PENABLE, nodeIn.penable @[hardware/soc/scala/fpga/VCU118Peripherals.scala 505:23] connect tracking_4.PWRITE, nodeIn.pwrite @[hardware/soc/scala/fpga/VCU118Peripherals.scala 506:22] node _tracking_4_io_PWDATA_T = bits(nodeIn.pwdata, 31, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 507:35] connect tracking_4.PWDATA, _tracking_4_io_PWDATA_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 507:22] connect tracking_4.trck_resetn, trckResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 509:27] connect tracking_4.afe_resetn, afeResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 510:26] connect tracking_4.trck_clk, trackingClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 511:24] connect tracking_4.afe_clk, afeClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 512:23] connect tracking_4.afe_data, rfDataNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 513:24] connect tracking_4.sample_align, afe.sample_align_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 514:28] connect tracking_4.sample_counter, afe.sample_counter_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 515:30] connect tracking_5.PCLK, clock @[hardware/soc/scala/fpga/VCU118Peripherals.scala 501:20] connect tracking_5.PRESETN, apbResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 502:23] connect tracking_5.PADDR, localAddr @[hardware/soc/scala/fpga/VCU118Peripherals.scala 503:21] node _tracking_5_io_PSEL_T = and(nodeIn.psel, sel[6]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 504:32] connect tracking_5.PSEL, _tracking_5_io_PSEL_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 504:20] connect tracking_5.PENABLE, nodeIn.penable @[hardware/soc/scala/fpga/VCU118Peripherals.scala 505:23] connect tracking_5.PWRITE, nodeIn.pwrite @[hardware/soc/scala/fpga/VCU118Peripherals.scala 506:22] node _tracking_5_io_PWDATA_T = bits(nodeIn.pwdata, 31, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 507:35] connect tracking_5.PWDATA, _tracking_5_io_PWDATA_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 507:22] connect tracking_5.trck_resetn, trckResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 509:27] connect tracking_5.afe_resetn, afeResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 510:26] connect tracking_5.trck_clk, trackingClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 511:24] connect tracking_5.afe_clk, afeClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 512:23] connect tracking_5.afe_data, rfDataNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 513:24] connect tracking_5.sample_align, afe.sample_align_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 514:28] connect tracking_5.sample_counter, afe.sample_counter_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 515:30] connect tracking_6.PCLK, clock @[hardware/soc/scala/fpga/VCU118Peripherals.scala 501:20] connect tracking_6.PRESETN, apbResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 502:23] connect tracking_6.PADDR, localAddr @[hardware/soc/scala/fpga/VCU118Peripherals.scala 503:21] node _tracking_6_io_PSEL_T = and(nodeIn.psel, sel[7]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 504:32] connect tracking_6.PSEL, _tracking_6_io_PSEL_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 504:20] connect tracking_6.PENABLE, nodeIn.penable @[hardware/soc/scala/fpga/VCU118Peripherals.scala 505:23] connect tracking_6.PWRITE, nodeIn.pwrite @[hardware/soc/scala/fpga/VCU118Peripherals.scala 506:22] node _tracking_6_io_PWDATA_T = bits(nodeIn.pwdata, 31, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 507:35] connect tracking_6.PWDATA, _tracking_6_io_PWDATA_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 507:22] connect tracking_6.trck_resetn, trckResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 509:27] connect tracking_6.afe_resetn, afeResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 510:26] connect tracking_6.trck_clk, trackingClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 511:24] connect tracking_6.afe_clk, afeClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 512:23] connect tracking_6.afe_data, rfDataNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 513:24] connect tracking_6.sample_align, afe.sample_align_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 514:28] connect tracking_6.sample_counter, afe.sample_counter_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 515:30] connect tracking_7.PCLK, clock @[hardware/soc/scala/fpga/VCU118Peripherals.scala 501:20] connect tracking_7.PRESETN, apbResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 502:23] connect tracking_7.PADDR, localAddr @[hardware/soc/scala/fpga/VCU118Peripherals.scala 503:21] node _tracking_7_io_PSEL_T = and(nodeIn.psel, sel[8]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 504:32] connect tracking_7.PSEL, _tracking_7_io_PSEL_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 504:20] connect tracking_7.PENABLE, nodeIn.penable @[hardware/soc/scala/fpga/VCU118Peripherals.scala 505:23] connect tracking_7.PWRITE, nodeIn.pwrite @[hardware/soc/scala/fpga/VCU118Peripherals.scala 506:22] node _tracking_7_io_PWDATA_T = bits(nodeIn.pwdata, 31, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 507:35] connect tracking_7.PWDATA, _tracking_7_io_PWDATA_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 507:22] connect tracking_7.trck_resetn, trckResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 509:27] connect tracking_7.afe_resetn, afeResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 510:26] connect tracking_7.trck_clk, trackingClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 511:24] connect tracking_7.afe_clk, afeClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 512:23] connect tracking_7.afe_data, rfDataNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 513:24] connect tracking_7.sample_align, afe.sample_align_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 514:28] connect tracking_7.sample_counter, afe.sample_counter_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 515:30] connect tracking_8.PCLK, clock @[hardware/soc/scala/fpga/VCU118Peripherals.scala 501:20] connect tracking_8.PRESETN, apbResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 502:23] connect tracking_8.PADDR, localAddr @[hardware/soc/scala/fpga/VCU118Peripherals.scala 503:21] node _tracking_8_io_PSEL_T = and(nodeIn.psel, sel[9]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 504:32] connect tracking_8.PSEL, _tracking_8_io_PSEL_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 504:20] connect tracking_8.PENABLE, nodeIn.penable @[hardware/soc/scala/fpga/VCU118Peripherals.scala 505:23] connect tracking_8.PWRITE, nodeIn.pwrite @[hardware/soc/scala/fpga/VCU118Peripherals.scala 506:22] node _tracking_8_io_PWDATA_T = bits(nodeIn.pwdata, 31, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 507:35] connect tracking_8.PWDATA, _tracking_8_io_PWDATA_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 507:22] connect tracking_8.trck_resetn, trckResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 509:27] connect tracking_8.afe_resetn, afeResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 510:26] connect tracking_8.trck_clk, trackingClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 511:24] connect tracking_8.afe_clk, afeClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 512:23] connect tracking_8.afe_data, rfDataNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 513:24] connect tracking_8.sample_align, afe.sample_align_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 514:28] connect tracking_8.sample_counter, afe.sample_counter_o @[hardware/soc/scala/fpga/VCU118Peripherals.scala 515:30] connect pps.PCLK, clock @[hardware/soc/scala/fpga/VCU118Peripherals.scala 518:17] connect pps.PRESETN, apbResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 519:20] connect pps.PADDR, localAddr @[hardware/soc/scala/fpga/VCU118Peripherals.scala 520:18] node _pps_io_PSEL_T = and(nodeIn.psel, sel[10]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 521:29] connect pps.PSEL, _pps_io_PSEL_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 521:17] connect pps.PENABLE, nodeIn.penable @[hardware/soc/scala/fpga/VCU118Peripherals.scala 522:20] connect pps.PWRITE, nodeIn.pwrite @[hardware/soc/scala/fpga/VCU118Peripherals.scala 523:19] node _pps_io_PWDATA_T = bits(nodeIn.pwdata, 31, 0) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 524:32] connect pps.PWDATA, _pps_io_PWDATA_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 524:19] connect pps.pps_clk, trackingClockNodeIn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 525:20] connect pps.pps_resetn, trckResetn @[hardware/soc/scala/fpga/VCU118Peripherals.scala 526:23] wire _pps_io_capture_i_WIRE : UInt<1>[9] @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:32] connect _pps_io_capture_i_WIRE[0], tracking_0.pps_capture @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:32] connect _pps_io_capture_i_WIRE[1], tracking_1.pps_capture @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:32] connect _pps_io_capture_i_WIRE[2], tracking_2.pps_capture @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:32] connect _pps_io_capture_i_WIRE[3], tracking_3.pps_capture @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:32] connect _pps_io_capture_i_WIRE[4], tracking_4.pps_capture @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:32] connect _pps_io_capture_i_WIRE[5], tracking_5.pps_capture @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:32] connect _pps_io_capture_i_WIRE[6], tracking_6.pps_capture @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:32] connect _pps_io_capture_i_WIRE[7], tracking_7.pps_capture @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:32] connect _pps_io_capture_i_WIRE[8], tracking_8.pps_capture @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:32] node pps_io_capture_i_lo_lo = cat(_pps_io_capture_i_WIRE[1], _pps_io_capture_i_WIRE[0]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:65] node pps_io_capture_i_lo_hi = cat(_pps_io_capture_i_WIRE[3], _pps_io_capture_i_WIRE[2]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:65] node pps_io_capture_i_lo = cat(pps_io_capture_i_lo_hi, pps_io_capture_i_lo_lo) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:65] node pps_io_capture_i_hi_lo = cat(_pps_io_capture_i_WIRE[5], _pps_io_capture_i_WIRE[4]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:65] node pps_io_capture_i_hi_hi_hi = cat(_pps_io_capture_i_WIRE[8], _pps_io_capture_i_WIRE[7]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:65] node pps_io_capture_i_hi_hi = cat(pps_io_capture_i_hi_hi_hi, _pps_io_capture_i_WIRE[6]) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:65] node pps_io_capture_i_hi = cat(pps_io_capture_i_hi_hi, pps_io_capture_i_hi_lo) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:65] node _pps_io_capture_i_T = cat(pps_io_capture_i_hi, pps_io_capture_i_lo) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:65] connect pps.capture_i, _pps_io_capture_i_T @[hardware/soc/scala/fpga/VCU118Peripherals.scala 527:22] connect ppsOutNodeOut, pps.pps_out @[hardware/soc/scala/fpga/VCU118Peripherals.scala 528:23] node _nodeIn_pready_T = mux(sel[0], acq.PREADY, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_1 = mux(sel[1], tracking_0.PREADY, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_2 = mux(sel[2], tracking_1.PREADY, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_3 = mux(sel[3], tracking_2.PREADY, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_4 = mux(sel[4], tracking_3.PREADY, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_5 = mux(sel[5], tracking_4.PREADY, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_6 = mux(sel[6], tracking_5.PREADY, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_7 = mux(sel[7], tracking_6.PREADY, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_8 = mux(sel[8], tracking_7.PREADY, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_9 = mux(sel[9], tracking_8.PREADY, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_10 = mux(sel[10], pps.PREADY, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_11 = or(_nodeIn_pready_T, _nodeIn_pready_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_12 = or(_nodeIn_pready_T_11, _nodeIn_pready_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_13 = or(_nodeIn_pready_T_12, _nodeIn_pready_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_14 = or(_nodeIn_pready_T_13, _nodeIn_pready_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_15 = or(_nodeIn_pready_T_14, _nodeIn_pready_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_16 = or(_nodeIn_pready_T_15, _nodeIn_pready_T_6) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_17 = or(_nodeIn_pready_T_16, _nodeIn_pready_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_18 = or(_nodeIn_pready_T_17, _nodeIn_pready_T_8) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_19 = or(_nodeIn_pready_T_18, _nodeIn_pready_T_9) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_20 = or(_nodeIn_pready_T_19, _nodeIn_pready_T_10) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeIn_pready_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_pready_WIRE, _nodeIn_pready_T_20 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pready_T_21 = mux(hit, _nodeIn_pready_WIRE, UInt<1>(0h1)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 534:22] connect nodeIn.pready, _nodeIn_pready_T_21 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 534:16] node _nodeIn_prdata_T = mux(sel[0], acq.PRDATA, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_1 = mux(sel[1], tracking_0.PRDATA, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_2 = mux(sel[2], tracking_1.PRDATA, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_3 = mux(sel[3], tracking_2.PRDATA, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_4 = mux(sel[4], tracking_3.PRDATA, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_5 = mux(sel[5], tracking_4.PRDATA, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_6 = mux(sel[6], tracking_5.PRDATA, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_7 = mux(sel[7], tracking_6.PRDATA, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_8 = mux(sel[8], tracking_7.PRDATA, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_9 = mux(sel[9], tracking_8.PRDATA, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_10 = mux(sel[10], pps.PRDATA, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_11 = or(_nodeIn_prdata_T, _nodeIn_prdata_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_12 = or(_nodeIn_prdata_T_11, _nodeIn_prdata_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_13 = or(_nodeIn_prdata_T_12, _nodeIn_prdata_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_14 = or(_nodeIn_prdata_T_13, _nodeIn_prdata_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_15 = or(_nodeIn_prdata_T_14, _nodeIn_prdata_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_16 = or(_nodeIn_prdata_T_15, _nodeIn_prdata_T_6) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_17 = or(_nodeIn_prdata_T_16, _nodeIn_prdata_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_18 = or(_nodeIn_prdata_T_17, _nodeIn_prdata_T_8) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_19 = or(_nodeIn_prdata_T_18, _nodeIn_prdata_T_9) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_prdata_T_20 = or(_nodeIn_prdata_T_19, _nodeIn_prdata_T_10) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeIn_prdata_WIRE : UInt<32> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_prdata_WIRE, _nodeIn_prdata_T_20 @[src/main/scala/chisel3/util/Mux.scala 30:73] connect nodeIn.prdata, _nodeIn_prdata_WIRE @[hardware/soc/scala/fpga/VCU118Peripherals.scala 535:16] node _nodeIn_pslverr_T = mux(sel[0], acq.PSLVERR, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_1 = mux(sel[1], tracking_0.PSLVERR, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_2 = mux(sel[2], tracking_1.PSLVERR, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_3 = mux(sel[3], tracking_2.PSLVERR, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_4 = mux(sel[4], tracking_3.PSLVERR, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_5 = mux(sel[5], tracking_4.PSLVERR, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_6 = mux(sel[6], tracking_5.PSLVERR, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_7 = mux(sel[7], tracking_6.PSLVERR, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_8 = mux(sel[8], tracking_7.PSLVERR, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_9 = mux(sel[9], tracking_8.PSLVERR, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_10 = mux(sel[10], pps.PSLVERR, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_11 = or(_nodeIn_pslverr_T, _nodeIn_pslverr_T_1) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_12 = or(_nodeIn_pslverr_T_11, _nodeIn_pslverr_T_2) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_13 = or(_nodeIn_pslverr_T_12, _nodeIn_pslverr_T_3) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_14 = or(_nodeIn_pslverr_T_13, _nodeIn_pslverr_T_4) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_15 = or(_nodeIn_pslverr_T_14, _nodeIn_pslverr_T_5) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_16 = or(_nodeIn_pslverr_T_15, _nodeIn_pslverr_T_6) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_17 = or(_nodeIn_pslverr_T_16, _nodeIn_pslverr_T_7) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_18 = or(_nodeIn_pslverr_T_17, _nodeIn_pslverr_T_8) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_19 = or(_nodeIn_pslverr_T_18, _nodeIn_pslverr_T_9) @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_20 = or(_nodeIn_pslverr_T_19, _nodeIn_pslverr_T_10) @[src/main/scala/chisel3/util/Mux.scala 30:73] wire _nodeIn_pslverr_WIRE : UInt<1> @[src/main/scala/chisel3/util/Mux.scala 30:73] connect _nodeIn_pslverr_WIRE, _nodeIn_pslverr_T_20 @[src/main/scala/chisel3/util/Mux.scala 30:73] node _nodeIn_pslverr_T_21 = mux(hit, _nodeIn_pslverr_WIRE, UInt<1>(0h1)) @[hardware/soc/scala/fpga/VCU118Peripherals.scala 536:23] connect nodeIn.pslverr, _nodeIn_pslverr_T_21 @[hardware/soc/scala/fpga/VCU118Peripherals.scala 536:17] connect intnodeOut[0], acq.acq_intr @[hardware/soc/scala/fpga/VCU118Peripherals.scala 539:14] connect intnodeOut[1], tracking_0.gps_frame_ready @[hardware/soc/scala/fpga/VCU118Peripherals.scala 541:24] connect intnodeOut[2], tracking_1.gps_frame_ready @[hardware/soc/scala/fpga/VCU118Peripherals.scala 541:24] connect intnodeOut[3], tracking_2.gps_frame_ready @[hardware/soc/scala/fpga/VCU118Peripherals.scala 541:24] connect intnodeOut[4], tracking_3.gps_frame_ready @[hardware/soc/scala/fpga/VCU118Peripherals.scala 541:24] connect intnodeOut[5], tracking_4.gps_frame_ready @[hardware/soc/scala/fpga/VCU118Peripherals.scala 541:24] connect intnodeOut[6], tracking_5.gps_frame_ready @[hardware/soc/scala/fpga/VCU118Peripherals.scala 541:24] connect intnodeOut[7], tracking_6.gps_frame_ready @[hardware/soc/scala/fpga/VCU118Peripherals.scala 541:24] connect intnodeOut[8], tracking_7.gps_frame_ready @[hardware/soc/scala/fpga/VCU118Peripherals.scala 541:24] connect intnodeOut[9], tracking_8.gps_frame_ready @[hardware/soc/scala/fpga/VCU118Peripherals.scala 541:24] module Queue1_TLBundleD_a29d32s7k1z2u : @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input clock : Clock @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input reset : Reset @[src/main/scala/chisel3/util/Decoupled.scala 243:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}, count : UInt<1>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} [1] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] wire enq_ptr_value : UInt @[src/main/scala/chisel3/util/Counter.scala 61:73] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:73] wire deq_ptr_value : UInt @[src/main/scala/chisel3/util/Counter.scala 61:73] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:73] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] wire _WIRE : UInt @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect _WIRE, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 270:8] infer mport MPORT = ram[_WIRE], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 270:24] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] skip node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] wire _io_deq_bits_WIRE : UInt @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect _io_deq_bits_WIRE, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 293:23] infer mport io_deq_bits_MPORT = ram[_io_deq_bits_WIRE], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] when io.enq.valid : @[src/main/scala/chisel3/util/Decoupled.scala 297:24] connect io.deq.valid, UInt<1>(0h1) @[src/main/scala/chisel3/util/Decoupled.scala 297:39] when empty : @[src/main/scala/chisel3/util/Decoupled.scala 298:17] connect io.deq.bits, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 299:19] connect do_deq, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 300:14] when io.deq.ready : @[src/main/scala/chisel3/util/Decoupled.scala 301:26] connect do_enq, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 301:35] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module Queue1_TLBundleA_a29d32s7k1z2u : @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input clock : Clock @[src/main/scala/chisel3/util/Decoupled.scala 243:7] input reset : Reset @[src/main/scala/chisel3/util/Decoupled.scala 243:7] output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, count : UInt<1>} @[src/main/scala/chisel3/util/Decoupled.scala 255:14] cmem ram : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>} [1] @[src/main/scala/chisel3/util/Decoupled.scala 256:91] wire enq_ptr_value : UInt @[src/main/scala/chisel3/util/Counter.scala 61:73] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:73] wire deq_ptr_value : UInt @[src/main/scala/chisel3/util/Counter.scala 61:73] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:73] regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 259:27] node ptr_match = eq(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 260:33] node _empty_T = eq(maybe_full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 261:28] node empty = and(ptr_match, _empty_T) @[src/main/scala/chisel3/util/Decoupled.scala 261:25] node full = and(ptr_match, maybe_full) @[src/main/scala/chisel3/util/Decoupled.scala 262:24] node _do_enq_T = and(io.enq.ready, io.enq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_enq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 263:27] connect do_enq, _do_enq_T @[src/main/scala/chisel3/util/Decoupled.scala 263:27] node _do_deq_T = and(io.deq.ready, io.deq.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] wire do_deq : UInt<1> @[src/main/scala/chisel3/util/Decoupled.scala 264:27] connect do_deq, _do_deq_T @[src/main/scala/chisel3/util/Decoupled.scala 264:27] when do_enq : @[src/main/scala/chisel3/util/Decoupled.scala 269:16] wire _WIRE : UInt @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect _WIRE, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 270:8] infer mport MPORT = ram[_WIRE], clock @[src/main/scala/chisel3/util/Decoupled.scala 270:8] connect MPORT, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 270:24] when do_deq : @[src/main/scala/chisel3/util/Decoupled.scala 273:16] skip node _T = neq(do_enq, do_deq) @[src/main/scala/chisel3/util/Decoupled.scala 276:15] when _T : @[src/main/scala/chisel3/util/Decoupled.scala 276:27] connect maybe_full, do_enq @[src/main/scala/chisel3/util/Decoupled.scala 277:16] when UInt<1>(0h0) : @[src/main/scala/chisel3/util/Decoupled.scala 279:15] connect enq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect deq_ptr_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 98:11] connect maybe_full, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 282:16] node _io_deq_valid_T = eq(empty, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 285:19] connect io.deq.valid, _io_deq_valid_T @[src/main/scala/chisel3/util/Decoupled.scala 285:16] node _io_enq_ready_T = eq(full, UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 286:19] connect io.enq.ready, _io_enq_ready_T @[src/main/scala/chisel3/util/Decoupled.scala 286:16] wire _io_deq_bits_WIRE : UInt @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect _io_deq_bits_WIRE, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 293:23] infer mport io_deq_bits_MPORT = ram[_io_deq_bits_WIRE], clock @[src/main/scala/chisel3/util/Decoupled.scala 293:23] connect io.deq.bits, io_deq_bits_MPORT @[src/main/scala/chisel3/util/Decoupled.scala 293:17] when io.enq.valid : @[src/main/scala/chisel3/util/Decoupled.scala 297:24] connect io.deq.valid, UInt<1>(0h1) @[src/main/scala/chisel3/util/Decoupled.scala 297:39] when empty : @[src/main/scala/chisel3/util/Decoupled.scala 298:17] connect io.deq.bits, io.enq.bits @[src/main/scala/chisel3/util/Decoupled.scala 299:19] connect do_deq, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 300:14] when io.deq.ready : @[src/main/scala/chisel3/util/Decoupled.scala 301:26] connect do_enq, UInt<1>(0h0) @[src/main/scala/chisel3/util/Decoupled.scala 301:35] node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node ptr_diff = tail(_ptr_diff_T, 1) @[src/main/scala/chisel3/util/Decoupled.scala 309:32] node _io_count_T = and(maybe_full, ptr_match) @[src/main/scala/chisel3/util/Decoupled.scala 312:32] node _io_count_T_1 = mux(_io_count_T, UInt<1>(0h1), UInt<1>(0h0)) @[src/main/scala/chisel3/util/Decoupled.scala 312:20] node _io_count_T_2 = or(_io_count_T_1, ptr_diff) @[src/main/scala/chisel3/util/Decoupled.scala 312:62] connect io.count, _io_count_T_2 @[src/main/scala/chisel3/util/Decoupled.scala 312:14] module TLToAPB : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 55:9] input clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 55:9] input reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 55:9] output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out : { psel : UInt<1>, penable : UInt<1>, pwrite : UInt<1>, paddr : UInt<29>, pprot : UInt<3>, pwdata : UInt<32>, pstrb : UInt<4>, pauser : { }, flip pready : UInt<1>, flip pslverr : UInt<1>, flip prdata : UInt<32>, pduser : { }}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate nodeIn.d.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.denied @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.sink @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.d.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.corrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.data @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.mask @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.fetch @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.secure @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.privileged @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.writealloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.readalloc @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.modifiable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.user.amba_prot.bufferable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.address @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.source @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.size @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.param @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.bits.opcode @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate nodeIn.a.ready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire nodeOut : { psel : UInt<1>, penable : UInt<1>, pwrite : UInt<1>, paddr : UInt<29>, pprot : UInt<3>, pwdata : UInt<32>, pstrb : UInt<4>, pauser : { }, flip pready : UInt<1>, flip pslverr : UInt<1>, flip prdata : UInt<32>, pduser : { }} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate nodeOut.prdata @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.pslverr @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.pready @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.pstrb @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.pwdata @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.pprot @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.paddr @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.pwrite @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.penable @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate nodeOut.psel @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] connect auto.out, nodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect nodeIn, auto.in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, address : UInt<29>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.mask, UInt<4>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.source, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.param, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] connect _WIRE.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:74] wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, address : UInt<29>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.bits, _WIRE.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, _WIRE.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.ready, _WIRE.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 264:61] connect _WIRE_1.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 61:18] wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.corrupt, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.data, UInt<32>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.address, UInt<29>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.source, UInt<7>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.size, UInt<2>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.param, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.bits.opcode, UInt<3>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] connect _WIRE_2.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:74] wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.bits, _WIRE_2.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.valid, _WIRE_2.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, _WIRE_2.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 265:61] connect _WIRE_3.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 62:18] wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.valid, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] connect _WIRE_4.ready, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:74] wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.bits, _WIRE_4.bits @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.valid, _WIRE_4.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, _WIRE_4.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Bundles.scala 267:61] connect _WIRE_5.ready, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 63:18] wire d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 71:19] inst nodeIn_d_q of Queue1_TLBundleD_a29d32s7k1z2u @[src/main/scala/chisel3/util/Decoupled.scala 362:21] connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, d.valid @[src/main/scala/chisel3/util/Decoupled.scala 364:22] connect nodeIn_d_q.io.enq.bits.corrupt, d.bits.corrupt @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.data, d.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.denied, d.bits.denied @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.sink, d.bits.sink @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.source, d.bits.source @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.size, d.bits.size @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.param, d.bits.param @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn_d_q.io.enq.bits.opcode, d.bits.opcode @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect d.ready, nodeIn_d_q.io.enq.ready @[src/main/scala/chisel3/util/Decoupled.scala 366:17] connect nodeIn.d.bits.corrupt, nodeIn_d_q.io.deq.bits.corrupt @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 72:12] connect nodeIn.d.bits.data, nodeIn_d_q.io.deq.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 72:12] connect nodeIn.d.bits.denied, nodeIn_d_q.io.deq.bits.denied @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 72:12] connect nodeIn.d.bits.sink, nodeIn_d_q.io.deq.bits.sink @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 72:12] connect nodeIn.d.bits.source, nodeIn_d_q.io.deq.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 72:12] connect nodeIn.d.bits.size, nodeIn_d_q.io.deq.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 72:12] connect nodeIn.d.bits.param, nodeIn_d_q.io.deq.bits.param @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 72:12] connect nodeIn.d.bits.opcode, nodeIn_d_q.io.deq.bits.opcode @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 72:12] connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 72:12] connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 72:12] inst a_q of Queue1_TLBundleA_a29d32s7k1z2u @[src/main/scala/chisel3/util/Decoupled.scala 362:21] connect a_q.clock, clock connect a_q.reset, reset connect a_q.io.enq.valid, nodeIn.a.valid @[src/main/scala/chisel3/util/Decoupled.scala 364:22] connect a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.data, nodeIn.a.bits.data @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.mask, nodeIn.a.bits.mask @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.user.amba_prot.fetch, nodeIn.a.bits.user.amba_prot.fetch @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.user.amba_prot.secure, nodeIn.a.bits.user.amba_prot.secure @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.user.amba_prot.privileged, nodeIn.a.bits.user.amba_prot.privileged @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.user.amba_prot.writealloc, nodeIn.a.bits.user.amba_prot.writealloc @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.user.amba_prot.readalloc, nodeIn.a.bits.user.amba_prot.readalloc @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.user.amba_prot.modifiable, nodeIn.a.bits.user.amba_prot.modifiable @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.user.amba_prot.bufferable, nodeIn.a.bits.user.amba_prot.bufferable @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.address, nodeIn.a.bits.address @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.source, nodeIn.a.bits.source @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.size, nodeIn.a.bits.size @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.param, nodeIn.a.bits.param @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode @[src/main/scala/chisel3/util/Decoupled.scala 365:21] connect nodeIn.a.ready, a_q.io.enq.ready @[src/main/scala/chisel3/util/Decoupled.scala 366:17] regreset a_enable : UInt<1>, clock, reset, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 77:29] node _a_sel_T = eq(nodeIn.d.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 78:41] node _a_sel_T_1 = or(_a_sel_T, nodeIn.d.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 78:53] reg a_sel_REG : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 78:40] connect a_sel_REG, _a_sel_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 78:40] node a_sel = and(a_q.io.deq.valid, a_sel_REG) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 78:30] node _a_write_opdata_T = bits(a_q.io.deq.bits.opcode, 2, 2) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:37] node a_write = eq(_a_write_opdata_T, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/Edges.scala 92:28] node _enable_d_T = eq(a_enable, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 81:31] node enable_d = and(a_sel, _enable_d_T) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 81:28] reg d_write : UInt<1>, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 82:31] when enable_d : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 82:31] connect d_write, a_write @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 82:31] reg d_source : UInt<7>, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 83:31] when enable_d : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 83:31] connect d_source, a_q.io.deq.bits.source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 83:31] reg d_size : UInt<2>, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 84:31] when enable_d : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 84:31] connect d_size, a_q.io.deq.bits.size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 84:31] reg d_echo : { }, clock @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 85:31] when enable_d : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 85:31] skip when a_sel : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 87:23] connect a_enable, UInt<1>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 87:34] node _T = and(d.ready, d.valid) @[src/main/scala/chisel3/util/Decoupled.scala 51:35] when _T : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 88:21] connect a_enable, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 88:32] connect nodeOut.psel, a_sel @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 90:19] connect nodeOut.penable, a_enable @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 91:19] connect nodeOut.pwrite, a_write @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 92:19] connect nodeOut.paddr, a_q.io.deq.bits.address @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 93:19] connect nodeOut.pprot, UInt<3>(0h1) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 94:19] connect nodeOut.pwdata, a_q.io.deq.bits.data @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 95:19] node _nodeOut_pstrb_T = mux(a_write, a_q.io.deq.bits.mask, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 96:25] connect nodeOut.pstrb, _nodeOut_pstrb_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 96:19] wire pprot : UInt<1>[3] @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 101:25] connect pprot[0], a_q.io.deq.bits.user.amba_prot.privileged @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 102:18] node _pprot_1_T = eq(a_q.io.deq.bits.user.amba_prot.secure, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 103:21] connect pprot[1], _pprot_1_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 103:18] connect pprot[2], a_q.io.deq.bits.user.amba_prot.fetch @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 104:18] node nodeOut_pprot_hi = cat(pprot[2], pprot[1]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 105:25] node _nodeOut_pprot_T = cat(nodeOut_pprot_hi, pprot[0]) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 105:25] connect nodeOut.pprot, _nodeOut_pprot_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 105:19] node _q_io_deq_ready_T = and(a_enable, nodeOut.pready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 108:27] connect a_q.io.deq.ready, _q_io_deq_ready_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 108:15] node _d_valid_T = and(a_enable, nodeOut.pready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 109:27] connect d.valid, _d_valid_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 109:15] node _T_1 = eq(d.valid, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 110:15] node _T_2 = or(_T_1, d.ready) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 110:24] node _T_3 = asUInt(reset) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 110:14] node _T_4 = eq(_T_3, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 110:14] when _T_4 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 110:14] node _T_5 = eq(_T_2, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 110:14] when _T_5 : @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 110:14] printf(clock, UInt<1>(0h1), "Assertion failed\n at ToAPB.scala:110 assert (!d.valid || d.ready)\n") : printf @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 110:14] assert(clock, _T_2, UInt<1>(0h1), "") : assert @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 110:14] node _d_bits_opcode_T = mux(d_write, UInt<1>(0h0), UInt<1>(0h1)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 112:28] connect d.bits.opcode, _d_bits_opcode_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 112:22] connect d.bits.param, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 113:22] connect d.bits.size, d_size @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 114:22] connect d.bits.source, d_source @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 115:22] connect d.bits.sink, UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 116:22] node _d_bits_denied_T = and(d_write, nodeOut.pslverr) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 117:34] connect d.bits.denied, _d_bits_denied_T @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 117:22] connect d.bits.data, nodeOut.prdata @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 118:22] node _d_bits_corrupt_T = eq(d_write, UInt<1>(0h0)) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 119:25] node _d_bits_corrupt_T_1 = and(_d_bits_corrupt_T, nodeOut.pslverr) @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 119:34] connect d.bits.corrupt, _d_bits_corrupt_T_1 @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 119:22] module FPGAGPSClockSinkDomain : @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 14:9] output auto : { flip tl2apb_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, dev_pps_out_out : UInt<1>, flip dev_rf_data_in : UInt<4>, flip dev_afe_clock_in : Clock, flip dev_tracking_clock_in : Clock, flip dev_acq_clock_in : Clock, dev_int_out : UInt<1>[10], flip clock_in : { clock : Clock, reset : Reset}} @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] output clock : Clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 21:19] output reset : Reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 22:19] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] inst dev of APBGpsBlock @[hardware/soc/scala/fpga/VCU118Peripherals.scala 672:34] connect dev.clock, childClock connect dev.reset, childReset inst tl2apb of TLToAPB @[hardware/upstream/rocket-chip/src/main/scala/tilelink/ToAPB.scala 134:28] connect tl2apb.clock, childClock connect tl2apb.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate clockNodeIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate clockNodeIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect dev.auto.in, tl2apb.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect clockNodeIn, auto.clock_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.dev_int_out, dev.auto.int_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect dev.auto.acq_clock_in, auto.dev_acq_clock_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect dev.auto.tracking_clock_in, auto.dev_tracking_clock_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect dev.auto.afe_clock_in, auto.dev_afe_clock_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect dev.auto.rf_data_in, auto.dev_rf_data_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect auto.dev_pps_out_out, dev.auto.pps_out_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 113:12] connect tl2apb.auto.in, auto.tl2apb_in @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 111:16] connect childClock, clockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 15:16] connect childReset, clockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 16:16] connect clock, clockNodeIn.clock @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 23:11] connect reset, clockNodeIn.reset @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockDomain.scala 24:11] module VCU118RocketSystem : @[hardware/soc/scala/fpga/VCU118Peripherals.scala 692:7] output auto : { } @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 107:25] input io : { aggregator_3 : { clock : Clock, reset : Reset}, aggregator_2 : { clock : Clock, reset : Reset}, aggregator_1 : { clock : Clock, reset : Reset}, aggregator_0 : { clock : Clock, reset : Reset}} @[hardware/upstream/rocket-chip/src/main/scala/subsystem/BaseSubsystem.scala 71:18] output psd : { } @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Periphery.scala 108:17] output resetctrl : { flip hartIsInReset : UInt<1>[1]} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Periphery.scala 116:25] output debug : { flip clock : Clock, flip reset : Reset, flip clockeddmi : { dmi : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<32>, op : UInt<2>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<32>, resp : UInt<2>}}}, dmiClock : Clock, dmiReset : Reset}, ndreset : UInt<1>, dmactive : UInt<1>, flip dmactiveAck : UInt<1>} @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Periphery.scala 125:19] input interrupts : UInt<0> @[hardware/upstream/rocket-chip/src/main/scala/subsystem/InterruptBus.scala 80:22] input uart_rxd : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSource.scala 27:19] output uart_txd : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 26:19] output spi_sck : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 26:19] output spi_csn : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 26:19] input spi_dq_i : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSource.scala 27:19] output spi_dq_o : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 26:19] output spi_dq_oe : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 26:19] output pmod_spi_sck : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 26:19] output pmod_spi_csn : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 26:19] input pmod_spi_dq_i : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSource.scala 27:19] output pmod_spi_dq_o : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 26:19] output pmod_spi_dq_oe : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 26:19] input pmod_irq : UInt<1> @[hardware/soc/scala/fpga/VCU118Peripherals.scala 711:20] input gps_acq_clk : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSource.scala 27:19] input gps_trck_clk : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSource.scala 27:19] input gps_rf_clk : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSource.scala 27:19] input gps_rf_data : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSource.scala 27:19] output gps_pps : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 26:19] wire childClock : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 153:31] wire childReset : Reset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 156:31] node _childClock_T = asClock(UInt<1>(0h0)) @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:25] connect childClock, _childClock_T @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 158:14] invalidate childReset @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 159:14] inst ibus of ClockSinkDomain @[hardware/upstream/rocket-chip/src/main/scala/subsystem/BaseSubsystem.scala 63:24] inst aggregator of ClockGroupAggregator_aggregator @[hardware/upstream/rocket-chip/src/main/scala/prci/ClockGroup.scala 66:69] inst sbus of SystemBus @[hardware/upstream/rocket-chip/src/main/scala/subsystem/SystemBus.scala 31:26] inst pbus of PeripheryBus_pbus @[hardware/upstream/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala 37:26] inst fbus of FrontBus @[hardware/upstream/rocket-chip/src/main/scala/subsystem/FrontBus.scala 23:26] inst cbus of PeripheryBus_cbus @[hardware/upstream/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala 37:26] inst tile_prci_domain of TilePRCIDomain @[hardware/upstream/rocket-chip/src/main/scala/subsystem/HasTiles.scala 163:38] inst xbar of IntXbar_i1_o1 @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 52:26] inst xbar_1 of IntXbar_i1_o1_1 @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 52:26] inst xbar_2 of IntXbar_i1_o1_2 @[hardware/upstream/rocket-chip/src/main/scala/interrupts/Xbar.scala 52:26] inst tileHartIdNexusNode of BundleBridgeNexus_UInt1_2 @[hardware/upstream/rocket-chip/src/main/scala/subsystem/HasTiles.scala 75:39] inst broadcast of BundleBridgeNexus_UInt32_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/package.scala 25:31] inst clint_domain of CLINTClockSinkDomain @[hardware/upstream/rocket-chip/src/main/scala/tilelink/BusWrapper.scala 89:28] inst plic_domain of PLICClockSinkDomain @[hardware/upstream/rocket-chip/src/main/scala/tilelink/BusWrapper.scala 89:28] inst tlDM of TLDebugModule @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Periphery.scala 88:26] inst debugCustomXbarOpt of DebugCustomXbar @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Periphery.scala 80:75] inst nexus of BundleBridgeNexus_TraceBundle @[hardware/upstream/rocket-chip/src/main/scala/prci/BundleBridgeBlockDuringReset.scala 24:27] inst nexus_1 of BundleBridgeNexus_TraceCoreInterface @[hardware/upstream/rocket-chip/src/main/scala/prci/BundleBridgeBlockDuringReset.scala 24:27] inst bootrom_domain of bootromClockSinkDomain @[hardware/upstream/rocket-chip/src/main/scala/tilelink/BusWrapper.scala 89:28] inst fpga_uart_domain of FPGAUARTClockSinkDomain @[hardware/upstream/rocket-chip/src/main/scala/tilelink/BusWrapper.scala 89:28] inst fpga_spi_domain of FPGASPIClockSinkDomain @[hardware/upstream/rocket-chip/src/main/scala/tilelink/BusWrapper.scala 89:28] inst fpga_pmod_spi_domain of FPGAPMODSPIClockSinkDomain @[hardware/upstream/rocket-chip/src/main/scala/tilelink/BusWrapper.scala 89:28] inst fpga_gps_domain of FPGAGPSClockSinkDomain @[hardware/upstream/rocket-chip/src/main/scala/tilelink/BusWrapper.scala 89:28] wire allClockGroupsNodeOut : { member : { sbus_3 : { clock : Clock, reset : Reset}, sbus_2 : { clock : Clock, reset : Reset}, sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate allClockGroupsNodeOut.member.sbus_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate allClockGroupsNodeOut.member.sbus_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate allClockGroupsNodeOut.member.sbus_1.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate allClockGroupsNodeOut.member.sbus_1.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate allClockGroupsNodeOut.member.sbus_2.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate allClockGroupsNodeOut.member.sbus_2.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate allClockGroupsNodeOut.member.sbus_3.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate allClockGroupsNodeOut.member.sbus_3.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire allClockGroupsNodeIn : { member : { sbus_3 : { clock : Clock, reset : Reset}, sbus_2 : { clock : Clock, reset : Reset}, sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate allClockGroupsNodeIn.member.sbus_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate allClockGroupsNodeIn.member.sbus_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate allClockGroupsNodeIn.member.sbus_1.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate allClockGroupsNodeIn.member.sbus_1.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate allClockGroupsNodeIn.member.sbus_2.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate allClockGroupsNodeIn.member.sbus_2.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate allClockGroupsNodeIn.member.sbus_3.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate allClockGroupsNodeIn.member.sbus_3.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect allClockGroupsNodeOut, allClockGroupsNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire sourceOut : { member : { aggregator_3 : { clock : Clock, reset : Reset}, aggregator_2 : { clock : Clock, reset : Reset}, aggregator_1 : { clock : Clock, reset : Reset}, aggregator_0 : { clock : Clock, reset : Reset}}} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate sourceOut.member.aggregator_0.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate sourceOut.member.aggregator_0.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate sourceOut.member.aggregator_1.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate sourceOut.member.aggregator_1.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate sourceOut.member.aggregator_2.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate sourceOut.member.aggregator_2.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate sourceOut.member.aggregator_3.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] invalidate sourceOut.member.aggregator_3.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire tileHaltSinkNodeIn : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tileHaltSinkNodeIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire tileWFISinkNodeIn : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tileWFISinkNodeIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire tileCeaseSinkNodeIn : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate tileCeaseSinkNodeIn[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire domainIn : { clock : Clock, reset : Reset} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate domainIn.reset @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate domainIn.clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire debugNodesOut : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate debugNodesOut.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire debugNodesIn : { sync : UInt<1>[1]} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate debugNodesIn.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect debugNodesOut, debugNodesIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/IdentityNode.scala 22:56] wire traceCoreNodesIn : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, ctx : UInt<32>, tval : UInt<32>, cause : UInt<32>, time : UInt<32>} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate traceCoreNodesIn.time @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate traceCoreNodesIn.cause @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate traceCoreNodesIn.tval @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate traceCoreNodesIn.ctx @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate traceCoreNodesIn.priv @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate traceCoreNodesIn.group[0].ilastsize @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate traceCoreNodesIn.group[0].itype @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate traceCoreNodesIn.group[0].iaddr @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate traceCoreNodesIn.group[0].iretire @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire traceNodesIn : { insns : { valid : UInt<1>, iaddr : UInt<34>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<34>}[1], time : UInt<64>} @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate traceNodesIn.time @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate traceNodesIn.insns[0].tval @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate traceNodesIn.insns[0].cause @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate traceNodesIn.insns[0].interrupt @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate traceNodesIn.insns[0].exception @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate traceNodesIn.insns[0].priv @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate traceNodesIn.insns[0].insn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate traceNodesIn.insns[0].iaddr @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] invalidate traceNodesIn.insns[0].valid @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire bootROMResetVectorSourceNodeOut : UInt<32> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate bootROMResetVectorSourceNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire uartRXSourceNodeOut : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate uartRXSourceNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire gpsAcqClockSourceNodeOut : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate gpsAcqClockSourceNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire gpsTrackingClockSourceNodeOut : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate gpsTrackingClockSourceNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire gpsRfClockSourceNodeOut : Clock @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate gpsRfClockSourceNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire gpsRfDataSourceNodeOut : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate gpsRfDataSourceNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire pmodIRQIntNodeOut : UInt<1>[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate pmodIRQIntNodeOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire txdNodeIn : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate txdNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire spiDQISourceNodeOut : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate spiDQISourceNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire sckNodeIn : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate sckNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire csnNodeIn : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate csnNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire dqOutNodeIn : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate dqOutNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire dqOeNodeIn : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate dqOeNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire pmodSPIDQISourceNodeOut : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 543:17] invalidate pmodSPIDQISourceNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 546:7] wire sckNodeIn_1 : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate sckNodeIn_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire csnNodeIn_1 : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate csnNodeIn_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire dqOutNodeIn_1 : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate dqOutNodeIn_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire dqOeNodeIn_1 : UInt<4> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate dqOeNodeIn_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] wire ppsOutNodeIn : UInt<1> @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 552:17] invalidate ppsOutNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/nodes/MixedNode.scala 555:7] connect plic_domain.auto.plic_int_in[0], ibus.auto.int_bus_anon_out[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect plic_domain.auto.plic_int_in[1], ibus.auto.int_bus_anon_out[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect plic_domain.auto.plic_int_in[2], ibus.auto.int_bus_anon_out[2] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect plic_domain.auto.plic_int_in[3], ibus.auto.int_bus_anon_out[3] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect plic_domain.auto.plic_int_in[4], ibus.auto.int_bus_anon_out[4] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect plic_domain.auto.plic_int_in[5], ibus.auto.int_bus_anon_out[5] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect plic_domain.auto.plic_int_in[6], ibus.auto.int_bus_anon_out[6] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect plic_domain.auto.plic_int_in[7], ibus.auto.int_bus_anon_out[7] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect plic_domain.auto.plic_int_in[8], ibus.auto.int_bus_anon_out[8] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect plic_domain.auto.plic_int_in[9], ibus.auto.int_bus_anon_out[9] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect plic_domain.auto.plic_int_in[10], ibus.auto.int_bus_anon_out[10] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect sbus.auto.sbus_clock_groups_in, allClockGroupsNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect allClockGroupsNodeIn, aggregator.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect aggregator.auto.in, sourceOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect cbus.auto.cbus_clock_groups_in, sbus.auto.sbus_clock_groups_out_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fbus.auto.fbus_clock_groups_in, sbus.auto.sbus_clock_groups_out_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect ibus.auto.clock_in, sbus.auto.fixedClockNode_anon_out_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tile_prci_domain.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fpga_uart_domain.auto.clock_in, pbus.auto.fixedClockNode_anon_out_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fpga_spi_domain.auto.clock_in, pbus.auto.fixedClockNode_anon_out_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fpga_pmod_spi_domain.auto.clock_in, pbus.auto.fixedClockNode_anon_out_2 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fpga_gps_domain.auto.clock_in, pbus.auto.fixedClockNode_anon_out_3 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect pbus.auto.pbus_clock_groups_in, cbus.auto.cbus_clock_groups_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect clint_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_0 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect plic_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect domainIn, cbus.auto.fixedClockNode_anon_out_2 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect bootrom_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_3 @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect cbus.auto.bus_xing_in, sbus.auto.coupler_to_bus_named_cbus_bus_xing_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect pbus.auto.bus_xing_in, cbus.auto.coupler_to_bus_named_pbus_bus_xing_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect sbus.auto.coupler_from_bus_named_fbus_bus_xing_in, fbus.auto.bus_xing_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect nexus.auto.in, tile_prci_domain.auto.element_reset_domain_rockettile_trace_source_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect nexus_1.auto.in, tile_prci_domain.auto.element_reset_domain_rockettile_trace_core_source_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect tileHaltSinkNodeIn, xbar.auto.anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tileWFISinkNodeIn, xbar_1.auto.anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tileCeaseSinkNodeIn, xbar_2.auto.anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tile_prci_domain.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tile_prci_domain.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect clint_domain.auto.clint_in, cbus.auto.coupler_to_clint_fragmenter_anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect plic_domain.auto.plic_in, cbus.auto.coupler_to_plic_fragmenter_anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect debugNodesIn, tlDM.auto.dmOuter_int_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect fbus.auto.coupler_from_debug_sb_widget_anon_in, tlDM.auto.dmInner_dmInner_sb2tlOpt_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tlDM.auto.dmInner_dmInner_tl_in, cbus.auto.coupler_to_debug_fragmenter_anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect tlDM.auto.dmInner_dmInner_custom_in, debugCustomXbarOpt.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tile_prci_domain.auto.intsink_in.sync[0], debugNodesOut.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in, tile_prci_domain.auto.tl_master_clock_xing_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tile_prci_domain.auto.tl_slave_clock_xing_in, cbus.auto.coupler_to_rockettile_tl_slave_clock_xing_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out.sync[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect tile_prci_domain.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out.sync[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect xbar.auto.anon_in[0], tile_prci_domain.auto.intsink_out_0[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect xbar_1.auto.anon_in[0], tile_prci_domain.auto.intsink_out_1[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect xbar_2.auto.anon_in[0], tile_prci_domain.auto.intsink_out_2[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect traceNodesIn, nexus.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect traceCoreNodesIn, nexus_1.auto.out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect broadcast.auto.in, bootROMResetVectorSourceNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect bootrom_domain.auto.bootrom_in, cbus.auto.coupler_to_bootrom_fragmenter_anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fpga_uart_domain.auto.dev_rxd_in, uartRXSourceNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fpga_gps_domain.auto.dev_acq_clock_in, gpsAcqClockSourceNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fpga_gps_domain.auto.dev_tracking_clock_in, gpsTrackingClockSourceNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fpga_gps_domain.auto.dev_afe_clock_in, gpsRfClockSourceNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fpga_gps_domain.auto.dev_rf_data_in, gpsRfDataSourceNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect ibus.auto.with_no_name_in[0], pmodIRQIntNodeOut[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect txdNodeIn, fpga_uart_domain.auto.dev_txd_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect fpga_uart_domain.auto.dev_in, pbus.auto.coupler_to_fpga_uart_fragmenter_anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fpga_spi_domain.auto.dev_dq_in_in, spiDQISourceNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect sckNodeIn, fpga_spi_domain.auto.dev_sck_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect csnNodeIn, fpga_spi_domain.auto.dev_csn_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect dqOutNodeIn, fpga_spi_domain.auto.dev_dq_out_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect dqOeNodeIn, fpga_spi_domain.auto.dev_dq_oe_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect fpga_spi_domain.auto.dev_in, pbus.auto.coupler_to_fpga_spi_fragmenter_anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect fpga_pmod_spi_domain.auto.dev_dq_in_in, pmodSPIDQISourceNodeOut @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect sckNodeIn_1, fpga_pmod_spi_domain.auto.dev_sck_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect csnNodeIn_1, fpga_pmod_spi_domain.auto.dev_csn_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect dqOutNodeIn_1, fpga_pmod_spi_domain.auto.dev_dq_out_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect dqOeNodeIn_1, fpga_pmod_spi_domain.auto.dev_dq_oe_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect fpga_pmod_spi_domain.auto.dev_in, pbus.auto.coupler_to_fpga_pmod_spi_fragmenter_anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect ibus.auto.int_bus_anon_in[0], fpga_gps_domain.auto.dev_int_out[0] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect ibus.auto.int_bus_anon_in[1], fpga_gps_domain.auto.dev_int_out[1] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect ibus.auto.int_bus_anon_in[2], fpga_gps_domain.auto.dev_int_out[2] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect ibus.auto.int_bus_anon_in[3], fpga_gps_domain.auto.dev_int_out[3] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect ibus.auto.int_bus_anon_in[4], fpga_gps_domain.auto.dev_int_out[4] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect ibus.auto.int_bus_anon_in[5], fpga_gps_domain.auto.dev_int_out[5] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect ibus.auto.int_bus_anon_in[6], fpga_gps_domain.auto.dev_int_out[6] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect ibus.auto.int_bus_anon_in[7], fpga_gps_domain.auto.dev_int_out[7] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect ibus.auto.int_bus_anon_in[8], fpga_gps_domain.auto.dev_int_out[8] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect ibus.auto.int_bus_anon_in[9], fpga_gps_domain.auto.dev_int_out[9] @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect ppsOutNodeIn, fpga_gps_domain.auto.dev_pps_out_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 97:18] connect fpga_gps_domain.auto.tl2apb_in, pbus.auto.coupler_to_gps_fragmenter_anon_out @[dependencies/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala 99:18] connect sourceOut.member.aggregator_0, io.aggregator_0 @[hardware/upstream/rocket-chip/src/main/scala/subsystem/BaseSubsystem.scala 74:71] connect sourceOut.member.aggregator_1, io.aggregator_1 @[hardware/upstream/rocket-chip/src/main/scala/subsystem/BaseSubsystem.scala 74:71] connect sourceOut.member.aggregator_2, io.aggregator_2 @[hardware/upstream/rocket-chip/src/main/scala/subsystem/BaseSubsystem.scala 74:71] connect sourceOut.member.aggregator_3, io.aggregator_3 @[hardware/upstream/rocket-chip/src/main/scala/subsystem/BaseSubsystem.scala 74:71] connect tlDM.io.tl_reset, domainIn.reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Periphery.scala 114:32] connect tlDM.io.tl_clock, domainIn.clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Periphery.scala 115:32] connect tlDM.io.hartIsInReset[0], resetctrl.hartIsInReset[0] @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Periphery.scala 117:37] connect tlDM.io.dmi, debug.clockeddmi @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Periphery.scala 136:66] connect tlDM.io.debug_reset, debug.reset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Periphery.scala 148:36] connect tlDM.io.debug_clock, debug.clock @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Periphery.scala 149:36] connect debug.ndreset, tlDM.io.ctrl.ndreset @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Periphery.scala 151:19] connect debug.dmactive, tlDM.io.ctrl.dmactive @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Periphery.scala 152:20] connect tlDM.io.ctrl.dmactiveAck, debug.dmactiveAck @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Periphery.scala 153:41] connect tlDM.io.ctrl.debugUnavail[0], UInt<1>(0h0) @[hardware/upstream/rocket-chip/src/main/scala/devices/debug/Periphery.scala 157:54] connect bootROMResetVectorSourceNodeOut, UInt<17>(0h10000) @[hardware/upstream/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala 113:45] regreset int_rtc_tick_c_value : UInt<7>, clint_domain.clock, clint_domain.reset, UInt<7>(0h0) @[src/main/scala/chisel3/util/Counter.scala 61:40] wire int_rtc_tick : UInt<1> @[src/main/scala/chisel3/util/Counter.scala 117:24] connect int_rtc_tick, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 117:24] when UInt<1>(0h1) : @[src/main/scala/chisel3/util/Counter.scala 118:16] node int_rtc_tick_wrap_wrap = eq(int_rtc_tick_c_value, UInt<7>(0h63)) @[src/main/scala/chisel3/util/Counter.scala 73:24] node _int_rtc_tick_wrap_value_T = add(int_rtc_tick_c_value, UInt<1>(0h1)) @[src/main/scala/chisel3/util/Counter.scala 77:24] node _int_rtc_tick_wrap_value_T_1 = tail(_int_rtc_tick_wrap_value_T, 1) @[src/main/scala/chisel3/util/Counter.scala 77:24] connect int_rtc_tick_c_value, _int_rtc_tick_wrap_value_T_1 @[src/main/scala/chisel3/util/Counter.scala 77:15] when int_rtc_tick_wrap_wrap : @[src/main/scala/chisel3/util/Counter.scala 87:20] connect int_rtc_tick_c_value, UInt<1>(0h0) @[src/main/scala/chisel3/util/Counter.scala 87:28] connect int_rtc_tick, int_rtc_tick_wrap_wrap @[src/main/scala/chisel3/util/Counter.scala 118:23] connect clint_domain.tick, int_rtc_tick @[hardware/upstream/rocket-chip/src/main/scala/subsystem/RTC.scala 31:38] connect uartRXSourceNodeOut, uart_rxd @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSource.scala 32:12] connect uart_txd, txdNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 31:8] connect spi_sck, sckNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 31:8] connect spi_csn, csnNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 31:8] connect spiDQISourceNodeOut, spi_dq_i @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSource.scala 32:12] connect spi_dq_o, dqOutNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 31:8] connect spi_dq_oe, dqOeNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 31:8] connect pmod_spi_sck, sckNodeIn_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 31:8] connect pmod_spi_csn, csnNodeIn_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 31:8] connect pmodSPIDQISourceNodeOut, pmod_spi_dq_i @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSource.scala 32:12] connect pmod_spi_dq_o, dqOutNodeIn_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 31:8] connect pmod_spi_dq_oe, dqOeNodeIn_1 @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 31:8] connect gpsAcqClockSourceNodeOut, gps_acq_clk @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSource.scala 32:12] connect gpsTrackingClockSourceNodeOut, gps_trck_clk @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSource.scala 32:12] connect gpsRfClockSourceNodeOut, gps_rf_clk @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSource.scala 32:12] connect gpsRfDataSourceNodeOut, gps_rf_data @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSource.scala 32:12] connect gps_pps, ppsOutNodeIn @[dependencies/diplomacy/diplomacy/src/diplomacy/bundlebridge/BundleBridgeSink.scala 31:8] connect pmodIRQIntNodeOut[0], pmod_irq @[hardware/soc/scala/fpga/VCU118Peripherals.scala 720:12]